1 /* Allocate registers within a basic block, for GNU compiler.
2 Copyright (C) 1987, 88, 91, 93-6, 1997 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* Allocation of hard register numbers to pseudo registers is done in
23 two passes. In this pass we consider only regs that are born and
24 die once within one basic block. We do this one basic block at a
25 time. Then the next pass allocates the registers that remain.
26 Two passes are used because this pass uses methods that work only
27 on linear code, but that do a better job than the general methods
28 used in global_alloc, and more quickly too.
30 The assignments made are recorded in the vector reg_renumber
31 whose space is allocated here. The rtl code itself is not altered.
33 We assign each instruction in the basic block a number
34 which is its order from the beginning of the block.
35 Then we can represent the lifetime of a pseudo register with
36 a pair of numbers, and check for conflicts easily.
37 We can record the availability of hard registers with a
38 HARD_REG_SET for each instruction. The HARD_REG_SET
39 contains 0 or 1 for each hard reg.
41 To avoid register shuffling, we tie registers together when one
42 dies by being copied into another, or dies in an instruction that
43 does arithmetic to produce another. The tied registers are
44 allocated as one. Registers with different reg class preferences
45 can never be tied unless the class preferred by one is a subclass
46 of the one preferred by the other.
48 Tying is represented with "quantity numbers".
49 A non-tied register is given a new quantity number.
50 Tied registers have the same quantity number.
52 We have provision to exempt registers, even when they are contained
53 within the block, that can be tied to others that are not contained in it.
54 This is so that global_alloc could process them both and tie them then.
55 But this is currently disabled since tying in global_alloc is not
58 /* Pseudos allocated here cannot be reallocated by global.c if the hard
59 register is used as a spill register. So we don't allocate such pseudos
60 here if their preferred class is likely to be used by spills. */
66 #include "basic-block.h"
68 #include "hard-reg-set.h"
69 #include "insn-config.h"
73 /* Next quantity number available for allocation. */
77 /* In all the following vectors indexed by quantity number. */
79 /* Element Q is the hard reg number chosen for quantity Q,
80 or -1 if none was found. */
82 static short *qty_phys_reg;
84 /* We maintain two hard register sets that indicate suggested hard registers
85 for each quantity. The first, qty_phys_copy_sugg, contains hard registers
86 that are tied to the quantity by a simple copy. The second contains all
87 hard registers that are tied to the quantity via an arithmetic operation.
89 The former register set is given priority for allocation. This tends to
90 eliminate copy insns. */
92 /* Element Q is a set of hard registers that are suggested for quantity Q by
95 static HARD_REG_SET *qty_phys_copy_sugg;
97 /* Element Q is a set of hard registers that are suggested for quantity Q by
100 static HARD_REG_SET *qty_phys_sugg;
102 /* Element Q is the number of suggested registers in qty_phys_copy_sugg. */
104 static short *qty_phys_num_copy_sugg;
106 /* Element Q is the number of suggested registers in qty_phys_sugg. */
108 static short *qty_phys_num_sugg;
110 /* Element Q is the number of refs to quantity Q. */
112 static int *qty_n_refs;
114 /* Element Q is a reg class contained in (smaller than) the
115 preferred classes of all the pseudo regs that are tied in quantity Q.
116 This is the preferred class for allocating that quantity. */
118 static enum reg_class *qty_min_class;
120 /* Insn number (counting from head of basic block)
121 where quantity Q was born. -1 if birth has not been recorded. */
123 static int *qty_birth;
125 /* Insn number (counting from head of basic block)
126 where quantity Q died. Due to the way tying is done,
127 and the fact that we consider in this pass only regs that die but once,
128 a quantity can die only once. Each quantity's life span
129 is a set of consecutive insns. -1 if death has not been recorded. */
131 static int *qty_death;
133 /* Number of words needed to hold the data in quantity Q.
134 This depends on its machine mode. It is used for these purposes:
135 1. It is used in computing the relative importances of qtys,
136 which determines the order in which we look for regs for them.
137 2. It is used in rules that prevent tying several registers of
138 different sizes in a way that is geometrically impossible
139 (see combine_regs). */
141 static int *qty_size;
143 /* This holds the mode of the registers that are tied to qty Q,
144 or VOIDmode if registers with differing modes are tied together. */
146 static enum machine_mode *qty_mode;
148 /* Number of times a reg tied to qty Q lives across a CALL_INSN. */
150 static int *qty_n_calls_crossed;
152 /* Register class within which we allocate qty Q if we can't get
153 its preferred class. */
155 static enum reg_class *qty_alternate_class;
157 /* Element Q is the SCRATCH expression for which this quantity is being
158 allocated or 0 if this quantity is allocating registers. */
160 static rtx *qty_scratch_rtx;
162 /* Element Q is nonzero if this quantity has been used in a SUBREG
163 that changes its size. */
165 static char *qty_changes_size;
167 /* Element Q is the register number of one pseudo register whose
168 reg_qty value is Q, or -1 is this quantity is for a SCRATCH. This
169 register should be the head of the chain maintained in reg_next_in_qty. */
171 static int *qty_first_reg;
173 /* If (REG N) has been assigned a quantity number, is a register number
174 of another register assigned the same quantity number, or -1 for the
175 end of the chain. qty_first_reg point to the head of this chain. */
177 static int *reg_next_in_qty;
179 /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg
181 of -1 if this register cannot be allocated by local-alloc,
182 or -2 if not known yet.
184 Note that if we see a use or death of pseudo register N with
185 reg_qty[N] == -2, register N must be local to the current block. If
186 it were used in more than one block, we would have reg_qty[N] == -1.
187 This relies on the fact that if reg_basic_block[N] is >= 0, register N
188 will not appear in any other block. We save a considerable number of
189 tests by exploiting this.
191 If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not
196 /* The offset (in words) of register N within its quantity.
197 This can be nonzero if register N is SImode, and has been tied
198 to a subreg of a DImode register. */
200 static char *reg_offset;
202 /* Vector of substitutions of register numbers,
203 used to map pseudo regs into hardware regs.
204 This is set up as a result of register allocation.
205 Element N is the hard reg assigned to pseudo reg N,
206 or is -1 if no hard reg was assigned.
207 If N is a hard reg number, element N is N. */
211 /* Set of hard registers live at the current point in the scan
212 of the instructions in a basic block. */
214 static HARD_REG_SET regs_live;
216 /* Each set of hard registers indicates registers live at a particular
217 point in the basic block. For N even, regs_live_at[N] says which
218 hard registers are needed *after* insn N/2 (i.e., they may not
219 conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1.
221 If an object is to conflict with the inputs of insn J but not the
222 outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly,
223 if it is to conflict with the outputs of insn J but not the inputs of
224 insn J + 1, it is said to die at index J*2 + 1. */
226 static HARD_REG_SET *regs_live_at;
230 int scratch_list_length;
231 static int scratch_index;
233 /* Communicate local vars `insn_number' and `insn'
234 from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */
235 static int this_insn_number;
236 static rtx this_insn;
238 /* Used to communicate changes made by update_equiv_regs to
239 memref_referenced_p. reg_equiv_replacement is set for any REG_EQUIV note
240 found or created, so that we can keep track of what memory accesses might
241 be created later, e.g. by reload. */
243 static rtx *reg_equiv_replacement;
245 static void alloc_qty PROTO((int, enum machine_mode, int, int));
246 static void alloc_qty_for_scratch PROTO((rtx, int, rtx, int, int));
247 static void validate_equiv_mem_from_store PROTO((rtx, rtx));
248 static int validate_equiv_mem PROTO((rtx, rtx, rtx));
249 static int contains_replace_regs PROTO((rtx, char *));
250 static int memref_referenced_p PROTO((rtx, rtx));
251 static int memref_used_between_p PROTO((rtx, rtx, rtx));
252 static void optimize_reg_copy_1 PROTO((rtx, rtx, rtx));
253 static void optimize_reg_copy_2 PROTO((rtx, rtx, rtx));
254 static void update_equiv_regs PROTO((void));
255 static void block_alloc PROTO((int));
256 static int qty_sugg_compare PROTO((int, int));
257 static int qty_sugg_compare_1 PROTO((const GENERIC_PTR, const GENERIC_PTR));
258 static int qty_compare PROTO((int, int));
259 static int qty_compare_1 PROTO((const GENERIC_PTR, const GENERIC_PTR));
260 static int combine_regs PROTO((rtx, rtx, int, int, rtx, int));
261 static int reg_meets_class_p PROTO((int, enum reg_class));
262 static int reg_classes_overlap_p PROTO((enum reg_class, enum reg_class,
264 static void update_qty_class PROTO((int, int));
265 static void reg_is_set PROTO((rtx, rtx));
266 static void reg_is_born PROTO((rtx, int));
267 static void wipe_dead_reg PROTO((rtx, int));
268 static int find_free_reg PROTO((enum reg_class, enum machine_mode,
269 int, int, int, int, int));
270 static void mark_life PROTO((int, enum machine_mode, int));
271 static void post_mark_life PROTO((int, enum machine_mode, int, int, int));
272 static int no_conflict_p PROTO((rtx, rtx, rtx));
273 static int requires_inout PROTO((char *));
275 /* Allocate a new quantity (new within current basic block)
276 for register number REGNO which is born at index BIRTH
277 within the block. MODE and SIZE are info on reg REGNO. */
280 alloc_qty (regno, mode, size, birth)
282 enum machine_mode mode;
285 register int qty = next_qty++;
287 reg_qty[regno] = qty;
288 reg_offset[regno] = 0;
289 reg_next_in_qty[regno] = -1;
291 qty_first_reg[qty] = regno;
292 qty_size[qty] = size;
293 qty_mode[qty] = mode;
294 qty_birth[qty] = birth;
295 qty_n_calls_crossed[qty] = REG_N_CALLS_CROSSED (regno);
296 qty_min_class[qty] = reg_preferred_class (regno);
297 qty_alternate_class[qty] = reg_alternate_class (regno);
298 qty_n_refs[qty] = REG_N_REFS (regno);
299 qty_changes_size[qty] = REG_CHANGES_SIZE (regno);
302 /* Similar to `alloc_qty', but allocates a quantity for a SCRATCH rtx
303 used as operand N in INSN. We assume here that the SCRATCH is used in
307 alloc_qty_for_scratch (scratch, n, insn, insn_code_num, insn_number)
311 int insn_code_num, insn_number;
314 enum reg_class class;
318 #ifdef REGISTER_CONSTRAINTS
319 /* If we haven't yet computed which alternative will be used, do so now.
320 Then set P to the constraints for that alternative. */
321 if (which_alternative == -1)
322 if (! constrain_operands (insn_code_num, 0))
325 for (p = insn_operand_constraint[insn_code_num][n], i = 0;
326 *p && i < which_alternative; p++)
330 /* Compute the class required for this SCRATCH. If we don't need a
331 register, the class will remain NO_REGS. If we guessed the alternative
332 number incorrectly, reload will fix things up for us. */
335 while ((c = *p++) != '\0' && c != ',')
338 case '=': case '+': case '?':
339 case '#': case '&': case '!':
341 case '0': case '1': case '2': case '3': case '4':
342 case 'm': case '<': case '>': case 'V': case 'o':
343 case 'E': case 'F': case 'G': case 'H':
344 case 's': case 'i': case 'n':
345 case 'I': case 'J': case 'K': case 'L':
346 case 'M': case 'N': case 'O': case 'P':
347 #ifdef EXTRA_CONSTRAINT
348 case 'Q': case 'R': case 'S': case 'T': case 'U':
351 /* These don't say anything we care about. */
355 /* We don't need to allocate this SCRATCH. */
359 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
364 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER (c)];
368 if (class == NO_REGS)
371 #else /* REGISTER_CONSTRAINTS */
373 class = GENERAL_REGS;
379 qty_first_reg[qty] = -1;
380 qty_scratch_rtx[qty] = scratch;
381 qty_size[qty] = GET_MODE_SIZE (GET_MODE (scratch));
382 qty_mode[qty] = GET_MODE (scratch);
383 qty_birth[qty] = 2 * insn_number - 1;
384 qty_death[qty] = 2 * insn_number + 1;
385 qty_n_calls_crossed[qty] = 0;
386 qty_min_class[qty] = class;
387 qty_alternate_class[qty] = NO_REGS;
389 qty_changes_size[qty] = 0;
392 /* Main entry point of this file. */
400 /* Leaf functions and non-leaf functions have different needs.
401 If defined, let the machine say what kind of ordering we
403 #ifdef ORDER_REGS_FOR_LOCAL_ALLOC
404 ORDER_REGS_FOR_LOCAL_ALLOC;
407 /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected
409 update_equiv_regs ();
411 /* This sets the maximum number of quantities we can have. Quantity
412 numbers start at zero and we can have one for each pseudo plus the
413 number of SCRATCHes in the largest block, in the worst case. */
414 max_qty = (max_regno - FIRST_PSEUDO_REGISTER) + max_scratch;
416 /* Allocate vectors of temporary data.
417 See the declarations of these variables, above,
418 for what they mean. */
420 /* There can be up to MAX_SCRATCH * N_BASIC_BLOCKS SCRATCHes to allocate.
421 Instead of allocating this much memory from now until the end of
422 reload, only allocate space for MAX_QTY SCRATCHes. If there are more
423 reload will allocate them. */
425 scratch_list_length = max_qty;
426 scratch_list = (rtx *) xmalloc (scratch_list_length * sizeof (rtx));
427 bzero ((char *) scratch_list, scratch_list_length * sizeof (rtx));
428 scratch_block = (int *) xmalloc (scratch_list_length * sizeof (int));
429 bzero ((char *) scratch_block, scratch_list_length * sizeof (int));
432 qty_phys_reg = (short *) alloca (max_qty * sizeof (short));
434 = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET));
435 qty_phys_num_copy_sugg = (short *) alloca (max_qty * sizeof (short));
436 qty_phys_sugg = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET));
437 qty_phys_num_sugg = (short *) alloca (max_qty * sizeof (short));
438 qty_birth = (int *) alloca (max_qty * sizeof (int));
439 qty_death = (int *) alloca (max_qty * sizeof (int));
440 qty_scratch_rtx = (rtx *) alloca (max_qty * sizeof (rtx));
441 qty_first_reg = (int *) alloca (max_qty * sizeof (int));
442 qty_size = (int *) alloca (max_qty * sizeof (int));
444 = (enum machine_mode *) alloca (max_qty * sizeof (enum machine_mode));
445 qty_n_calls_crossed = (int *) alloca (max_qty * sizeof (int));
447 = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class));
449 = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class));
450 qty_n_refs = (int *) alloca (max_qty * sizeof (int));
451 qty_changes_size = (char *) alloca (max_qty * sizeof (char));
453 reg_qty = (int *) alloca (max_regno * sizeof (int));
454 reg_offset = (char *) alloca (max_regno * sizeof (char));
455 reg_next_in_qty = (int *) alloca (max_regno * sizeof (int));
457 /* Allocate the reg_renumber array */
458 allocate_reg_info (max_regno, FALSE, TRUE);
460 /* Determine which pseudo-registers can be allocated by local-alloc.
461 In general, these are the registers used only in a single block and
462 which only die once. However, if a register's preferred class has only
463 a few entries, don't allocate this register here unless it is preferred
464 or nothing since retry_global_alloc won't be able to move it to
465 GENERAL_REGS if a reload register of this class is needed.
467 We need not be concerned with which block actually uses the register
468 since we will never see it outside that block. */
470 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
472 if (REG_BASIC_BLOCK (i) >= 0 && REG_N_DEATHS (i) == 1
473 && (reg_alternate_class (i) == NO_REGS
474 || ! CLASS_LIKELY_SPILLED_P (reg_preferred_class (i))))
480 /* Force loop below to initialize entire quantity array. */
483 /* Allocate each block's local registers, block by block. */
485 for (b = 0; b < n_basic_blocks; b++)
487 /* NEXT_QTY indicates which elements of the `qty_...'
488 vectors might need to be initialized because they were used
489 for the previous block; it is set to the entire array before
490 block 0. Initialize those, with explicit loop if there are few,
491 else with bzero and bcopy. Do not initialize vectors that are
492 explicit set by `alloc_qty'. */
496 for (i = 0; i < next_qty; i++)
498 qty_scratch_rtx[i] = 0;
499 CLEAR_HARD_REG_SET (qty_phys_copy_sugg[i]);
500 qty_phys_num_copy_sugg[i] = 0;
501 CLEAR_HARD_REG_SET (qty_phys_sugg[i]);
502 qty_phys_num_sugg[i] = 0;
507 #define CLEAR(vector) \
508 bzero ((char *) (vector), (sizeof (*(vector))) * next_qty);
510 CLEAR (qty_scratch_rtx);
511 CLEAR (qty_phys_copy_sugg);
512 CLEAR (qty_phys_num_copy_sugg);
513 CLEAR (qty_phys_sugg);
514 CLEAR (qty_phys_num_sugg);
526 /* Depth of loops we are in while in update_equiv_regs. */
527 static int loop_depth;
529 /* Used for communication between the following two functions: contains
530 a MEM that we wish to ensure remains unchanged. */
531 static rtx equiv_mem;
533 /* Set nonzero if EQUIV_MEM is modified. */
534 static int equiv_mem_modified;
536 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
537 Called via note_stores. */
540 validate_equiv_mem_from_store (dest, set)
544 if ((GET_CODE (dest) == REG
545 && reg_overlap_mentioned_p (dest, equiv_mem))
546 || (GET_CODE (dest) == MEM
547 && true_dependence (dest, VOIDmode, equiv_mem, rtx_varies_p)))
548 equiv_mem_modified = 1;
551 /* Verify that no store between START and the death of REG invalidates
552 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
553 by storing into an overlapping memory location, or with a non-const
556 Return 1 if MEMREF remains valid. */
559 validate_equiv_mem (start, reg, memref)
568 equiv_mem_modified = 0;
570 /* If the memory reference has side effects or is volatile, it isn't a
571 valid equivalence. */
572 if (side_effects_p (memref))
575 for (insn = start; insn && ! equiv_mem_modified; insn = NEXT_INSN (insn))
577 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
580 if (find_reg_note (insn, REG_DEAD, reg))
583 if (GET_CODE (insn) == CALL_INSN && ! RTX_UNCHANGING_P (memref)
584 && ! CONST_CALL_P (insn))
587 note_stores (PATTERN (insn), validate_equiv_mem_from_store);
589 /* If a register mentioned in MEMREF is modified via an
590 auto-increment, we lose the equivalence. Do the same if one
591 dies; although we could extend the life, it doesn't seem worth
594 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
595 if ((REG_NOTE_KIND (note) == REG_INC
596 || REG_NOTE_KIND (note) == REG_DEAD)
597 && GET_CODE (XEXP (note, 0)) == REG
598 && reg_overlap_mentioned_p (XEXP (note, 0), memref))
605 /* TRUE if X uses any registers for which reg_equiv_replace is true. */
608 contains_replace_regs (x, reg_equiv_replace)
610 char *reg_equiv_replace;
614 enum rtx_code code = GET_CODE (x);
630 return reg_equiv_replace[REGNO (x)];
633 fmt = GET_RTX_FORMAT (code);
634 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
638 if (contains_replace_regs (XEXP (x, i), reg_equiv_replace))
642 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
643 if (contains_replace_regs (XVECEXP (x, i, j), reg_equiv_replace))
651 /* TRUE if X references a memory location that would be affected by a store
655 memref_referenced_p (memref, x)
661 enum rtx_code code = GET_CODE (x);
677 return (reg_equiv_replacement[REGNO (x)]
678 && memref_referenced_p (memref,
679 reg_equiv_replacement[REGNO (x)]));
682 if (true_dependence (memref, VOIDmode, x, rtx_varies_p))
687 /* If we are setting a MEM, it doesn't count (its address does), but any
688 other SET_DEST that has a MEM in it is referencing the MEM. */
689 if (GET_CODE (SET_DEST (x)) == MEM)
691 if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0)))
694 else if (memref_referenced_p (memref, SET_DEST (x)))
697 return memref_referenced_p (memref, SET_SRC (x));
703 fmt = GET_RTX_FORMAT (code);
704 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
708 if (memref_referenced_p (memref, XEXP (x, i)))
712 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
713 if (memref_referenced_p (memref, XVECEXP (x, i, j)))
721 /* TRUE if some insn in the range (START, END] references a memory location
722 that would be affected by a store to MEMREF. */
725 memref_used_between_p (memref, start, end)
732 for (insn = NEXT_INSN (start); insn != NEXT_INSN (end);
733 insn = NEXT_INSN (insn))
734 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
735 && memref_referenced_p (memref, PATTERN (insn)))
741 /* INSN is a copy from SRC to DEST, both registers, and SRC does not die
744 Search forward to see if SRC dies before either it or DEST is modified,
745 but don't scan past the end of a basic block. If so, we can replace SRC
746 with DEST and let SRC die in INSN.
748 This will reduce the number of registers live in that range and may enable
749 DEST to be tied to SRC, thus often saving one register in addition to a
750 register-register copy. */
753 optimize_reg_copy_1 (insn, dest, src)
761 int sregno = REGNO (src);
762 int dregno = REGNO (dest);
764 /* We don't want to mess with hard regs if register classes are small. */
766 || (SMALL_REGISTER_CLASSES
767 && (sregno < FIRST_PSEUDO_REGISTER
768 || dregno < FIRST_PSEUDO_REGISTER))
769 /* We don't see all updates to SP if they are in an auto-inc memory
770 reference, so we must disallow this optimization on them. */
771 || sregno == STACK_POINTER_REGNUM || dregno == STACK_POINTER_REGNUM)
774 for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p))
776 if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN
777 || (GET_CODE (p) == NOTE
778 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG
779 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END)))
782 if (GET_RTX_CLASS (GET_CODE (p)) != 'i')
785 if (reg_set_p (src, p) || reg_set_p (dest, p)
786 /* Don't change a USE of a register. */
787 || (GET_CODE (PATTERN (p)) == USE
788 && reg_overlap_mentioned_p (src, XEXP (PATTERN (p), 0))))
791 /* See if all of SRC dies in P. This test is slightly more
792 conservative than it needs to be. */
793 if ((note = find_regno_note (p, REG_DEAD, sregno)) != 0
794 && GET_MODE (XEXP (note, 0)) == GET_MODE (src))
802 /* We can do the optimization. Scan forward from INSN again,
803 replacing regs as we go. Set FAILED if a replacement can't
804 be done. In that case, we can't move the death note for SRC.
805 This should be rare. */
807 /* Set to stop at next insn. */
808 for (q = next_real_insn (insn);
809 q != next_real_insn (p);
810 q = next_real_insn (q))
812 if (reg_overlap_mentioned_p (src, PATTERN (q)))
814 /* If SRC is a hard register, we might miss some
815 overlapping registers with validate_replace_rtx,
816 so we would have to undo it. We can't if DEST is
817 present in the insn, so fail in that combination
819 if (sregno < FIRST_PSEUDO_REGISTER
820 && reg_mentioned_p (dest, PATTERN (q)))
823 /* Replace all uses and make sure that the register
824 isn't still present. */
825 else if (validate_replace_rtx (src, dest, q)
826 && (sregno >= FIRST_PSEUDO_REGISTER
827 || ! reg_overlap_mentioned_p (src,
830 /* We assume that a register is used exactly once per
831 insn in the updates below. If this is not correct,
832 no great harm is done. */
833 if (sregno >= FIRST_PSEUDO_REGISTER)
834 REG_N_REFS (sregno) -= loop_depth;
835 if (dregno >= FIRST_PSEUDO_REGISTER)
836 REG_N_REFS (dregno) += loop_depth;
840 validate_replace_rtx (dest, src, q);
845 /* Count the insns and CALL_INSNs passed. If we passed the
846 death note of DEST, show increased live length. */
851 /* If the insn in which SRC dies is a CALL_INSN, don't count it
852 as a call that has been crossed. Otherwise, count it. */
853 if (q != p && GET_CODE (q) == CALL_INSN)
860 /* If DEST dies here, remove the death note and save it for
861 later. Make sure ALL of DEST dies here; again, this is
862 overly conservative. */
864 && (dest_death = find_regno_note (q, REG_DEAD, dregno)) != 0
865 && GET_MODE (XEXP (dest_death, 0)) == GET_MODE (dest))
866 remove_note (q, dest_death);
871 if (sregno >= FIRST_PSEUDO_REGISTER)
873 if (REG_LIVE_LENGTH (sregno) >= 0)
875 REG_LIVE_LENGTH (sregno) -= length;
876 /* reg_live_length is only an approximation after
877 combine if sched is not run, so make sure that we
878 still have a reasonable value. */
879 if (REG_LIVE_LENGTH (sregno) < 2)
880 REG_LIVE_LENGTH (sregno) = 2;
883 REG_N_CALLS_CROSSED (sregno) -= n_calls;
886 if (dregno >= FIRST_PSEUDO_REGISTER)
888 if (REG_LIVE_LENGTH (dregno) >= 0)
889 REG_LIVE_LENGTH (dregno) += d_length;
891 REG_N_CALLS_CROSSED (dregno) += d_n_calls;
894 /* Move death note of SRC from P to INSN. */
895 remove_note (p, note);
896 XEXP (note, 1) = REG_NOTES (insn);
897 REG_NOTES (insn) = note;
900 /* Put death note of DEST on P if we saw it die. */
903 XEXP (dest_death, 1) = REG_NOTES (p);
904 REG_NOTES (p) = dest_death;
910 /* If SRC is a hard register which is set or killed in some other
911 way, we can't do this optimization. */
912 else if (sregno < FIRST_PSEUDO_REGISTER
913 && dead_or_set_p (p, src))
918 /* INSN is a copy of SRC to DEST, in which SRC dies. See if we now have
919 a sequence of insns that modify DEST followed by an insn that sets
920 SRC to DEST in which DEST dies, with no prior modification of DEST.
921 (There is no need to check if the insns in between actually modify
922 DEST. We should not have cases where DEST is not modified, but
923 the optimization is safe if no such modification is detected.)
924 In that case, we can replace all uses of DEST, starting with INSN and
925 ending with the set of SRC to DEST, with SRC. We do not do this
926 optimization if a CALL_INSN is crossed unless SRC already crosses a
927 call or if DEST dies before the copy back to SRC.
929 It is assumed that DEST and SRC are pseudos; it is too complicated to do
930 this for hard registers since the substitutions we may make might fail. */
933 optimize_reg_copy_2 (insn, dest, src)
940 int sregno = REGNO (src);
941 int dregno = REGNO (dest);
943 for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p))
945 if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN
946 || (GET_CODE (p) == NOTE
947 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG
948 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END)))
951 if (GET_RTX_CLASS (GET_CODE (p)) != 'i')
954 set = single_set (p);
955 if (set && SET_SRC (set) == dest && SET_DEST (set) == src
956 && find_reg_note (p, REG_DEAD, dest))
958 /* We can do the optimization. Scan forward from INSN again,
959 replacing regs as we go. */
961 /* Set to stop at next insn. */
962 for (q = insn; q != NEXT_INSN (p); q = NEXT_INSN (q))
963 if (GET_RTX_CLASS (GET_CODE (q)) == 'i')
965 if (reg_mentioned_p (dest, PATTERN (q)))
967 PATTERN (q) = replace_rtx (PATTERN (q), dest, src);
969 /* We assume that a register is used exactly once per
970 insn in the updates below. If this is not correct,
971 no great harm is done. */
972 REG_N_REFS (dregno) -= loop_depth;
973 REG_N_REFS (sregno) += loop_depth;
977 if (GET_CODE (q) == CALL_INSN)
979 REG_N_CALLS_CROSSED (dregno)--;
980 REG_N_CALLS_CROSSED (sregno)++;
984 remove_note (p, find_reg_note (p, REG_DEAD, dest));
985 REG_N_DEATHS (dregno)--;
986 remove_note (insn, find_reg_note (insn, REG_DEAD, src));
987 REG_N_DEATHS (sregno)--;
991 if (reg_set_p (src, p)
992 || find_reg_note (p, REG_DEAD, dest)
993 || (GET_CODE (p) == CALL_INSN && REG_N_CALLS_CROSSED (sregno) == 0))
998 /* Find registers that are equivalent to a single value throughout the
999 compilation (either because they can be referenced in memory or are set once
1000 from a single constant). Lower their priority for a register.
1002 If such a register is only referenced once, try substituting its value
1003 into the using insn. If it succeeds, we can eliminate the register
1007 update_equiv_regs ()
1009 rtx *reg_equiv_init_insn = (rtx *) alloca (max_regno * sizeof (rtx *));
1010 /* Set when an attempt should be made to replace a register with the
1011 associated reg_equiv_replacement entry at the end of this function. */
1012 char *reg_equiv_replace
1013 = (char *) alloca (max_regno * sizeof *reg_equiv_replace);
1017 reg_equiv_replacement = (rtx *) alloca (max_regno * sizeof (rtx *));
1019 bzero ((char *) reg_equiv_init_insn, max_regno * sizeof (rtx *));
1020 bzero ((char *) reg_equiv_replacement, max_regno * sizeof (rtx *));
1021 bzero ((char *) reg_equiv_replace, max_regno * sizeof *reg_equiv_replace);
1023 init_alias_analysis ();
1027 /* Scan the insns and find which registers have equivalences. Do this
1028 in a separate scan of the insns because (due to -fcse-follow-jumps)
1029 a register can be set below its use. */
1030 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1033 rtx set = single_set (insn);
1037 if (GET_CODE (insn) == NOTE)
1039 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
1041 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
1045 /* If this insn contains more (or less) than a single SET, ignore it. */
1049 dest = SET_DEST (set);
1050 src = SET_SRC (set);
1052 /* If this sets a MEM to the contents of a REG that is only used
1053 in a single basic block, see if the register is always equivalent
1054 to that memory location and if moving the store from INSN to the
1055 insn that set REG is safe. If so, put a REG_EQUIV note on the
1058 Don't add a REG_EQUIV note if the insn already has one. The existing
1059 REG_EQUIV is likely more useful than the one we are adding.
1061 If one of the regs in the address is marked as reg_equiv_replace,
1062 then we can't add this REG_EQUIV note. The reg_equiv_replace
1063 optimization may move the set of this register immediately before
1064 insn, which puts it after reg_equiv_init_insn[regno], and hence
1065 the mention in the REG_EQUIV note would be to an uninitialized
1068 if (GET_CODE (dest) == MEM && GET_CODE (SET_SRC (set)) == REG
1069 && (regno = REGNO (SET_SRC (set))) >= FIRST_PSEUDO_REGISTER
1070 && REG_BASIC_BLOCK (regno) >= 0
1071 && reg_equiv_init_insn[regno] != 0
1072 && ! find_reg_note (insn, REG_EQUIV, NULL_RTX)
1073 && ! contains_replace_regs (XEXP (dest, 0), reg_equiv_replace)
1074 && validate_equiv_mem (reg_equiv_init_insn[regno], SET_SRC (set),
1076 && ! memref_used_between_p (SET_DEST (set),
1077 reg_equiv_init_insn[regno], insn))
1078 REG_NOTES (reg_equiv_init_insn[regno])
1079 = gen_rtx (EXPR_LIST, REG_EQUIV, dest,
1080 REG_NOTES (reg_equiv_init_insn[regno]));
1082 /* If this is a register-register copy where SRC is not dead, see if we
1084 if (flag_expensive_optimizations && GET_CODE (dest) == REG
1085 && GET_CODE (SET_SRC (set)) == REG
1086 && ! find_reg_note (insn, REG_DEAD, SET_SRC (set)))
1087 optimize_reg_copy_1 (insn, dest, SET_SRC (set));
1089 /* Similarly for a pseudo-pseudo copy when SRC is dead. */
1090 else if (flag_expensive_optimizations && GET_CODE (dest) == REG
1091 && REGNO (dest) >= FIRST_PSEUDO_REGISTER
1092 && GET_CODE (SET_SRC (set)) == REG
1093 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER
1094 && find_reg_note (insn, REG_DEAD, SET_SRC (set)))
1095 optimize_reg_copy_2 (insn, dest, SET_SRC (set));
1097 /* Otherwise, we only handle the case of a pseudo register being set
1098 once and only if neither the source nor the destination are
1099 in a register class that's likely to be spilled. */
1100 if (GET_CODE (dest) != REG
1101 || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER
1102 || REG_N_SETS (regno) != 1
1103 || CLASS_LIKELY_SPILLED_P (reg_preferred_class (REGNO (dest)))
1104 || (GET_CODE (src) == REG
1105 && REGNO (src) >= FIRST_PSEUDO_REGISTER
1106 && CLASS_LIKELY_SPILLED_P (reg_preferred_class (REGNO (src)))))
1109 note = find_reg_note (insn, REG_EQUAL, NULL_RTX);
1111 #ifdef DONT_RECORD_EQUIVALENCE
1112 /* Allow the target to reject promotions of some REG_EQUAL notes to
1115 In some cases this can improve register allocation if the existence
1116 of the REG_EQUIV note is likely to increase the lifetime of a register
1117 that is likely to be spilled.
1119 It may also be necessary if the target can't handle certain constant
1120 expressions appearing randomly in insns, but for whatever reason
1121 those expressions must be considered legitimate constant expressions
1122 to prevent them from being forced into memory. */
1123 if (note && DONT_RECORD_EQUIVALENCE (note))
1127 /* Record this insn as initializing this register. */
1128 reg_equiv_init_insn[regno] = insn;
1130 /* If this register is known to be equal to a constant, record that
1131 it is always equivalent to the constant. */
1132 if (note && CONSTANT_P (XEXP (note, 0)))
1133 PUT_MODE (note, (enum machine_mode) REG_EQUIV);
1135 /* If this insn introduces a "constant" register, decrease the priority
1136 of that register. Record this insn if the register is only used once
1137 more and the equivalence value is the same as our source.
1139 The latter condition is checked for two reasons: First, it is an
1140 indication that it may be more efficient to actually emit the insn
1141 as written (if no registers are available, reload will substitute
1142 the equivalence). Secondly, it avoids problems with any registers
1143 dying in this insn whose death notes would be missed.
1145 If we don't have a REG_EQUIV note, see if this insn is loading
1146 a register used only in one basic block from a MEM. If so, and the
1147 MEM remains unchanged for the life of the register, add a REG_EQUIV
1150 note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
1152 if (note == 0 && REG_BASIC_BLOCK (regno) >= 0
1153 && GET_CODE (SET_SRC (set)) == MEM
1154 && validate_equiv_mem (insn, dest, SET_SRC (set)))
1155 REG_NOTES (insn) = note = gen_rtx (EXPR_LIST, REG_EQUIV, SET_SRC (set),
1160 int regno = REGNO (dest);
1162 reg_equiv_replacement[regno] = XEXP (note, 0);
1164 /* Don't mess with things live during setjmp. */
1165 if (REG_LIVE_LENGTH (regno) >= 0)
1167 /* Note that the statement below does not affect the priority
1169 REG_LIVE_LENGTH (regno) *= 2;
1172 /* If the register is referenced exactly twice, meaning it is
1173 set once and used once, indicate that the reference may be
1174 replaced by the equivalence we computed above. If the
1175 register is only used in one basic block, this can't succeed
1176 or combine would have done it.
1178 It would be nice to use "loop_depth * 2" in the compare
1179 below. Unfortunately, LOOP_DEPTH need not be constant within
1180 a basic block so this would be too complicated.
1182 This case normally occurs when a parameter is read from
1183 memory and then used exactly once, not in a loop. */
1185 if (REG_N_REFS (regno) == 2
1186 && REG_BASIC_BLOCK (regno) < 0
1187 && rtx_equal_p (XEXP (note, 0), SET_SRC (set)))
1188 reg_equiv_replace[regno] = 1;
1193 /* Now scan all regs killed in an insn to see if any of them are
1194 registers only used that once. If so, see if we can replace the
1195 reference with the equivalent from. If we can, delete the
1196 initializing reference and this register will go away. If we
1197 can't replace the reference, and the instruction is not in a
1198 loop, then move the register initialization just before the use,
1199 so that they are in the same basic block. */
1202 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1206 /* Keep track of which basic block we are in. */
1207 if (block + 1 < n_basic_blocks
1208 && basic_block_head[block + 1] == insn)
1211 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
1213 if (GET_CODE (insn) == NOTE)
1215 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
1217 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
1228 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1230 if (REG_NOTE_KIND (link) == REG_DEAD
1231 /* Make sure this insn still refers to the register. */
1232 && reg_mentioned_p (XEXP (link, 0), PATTERN (insn)))
1234 int regno = REGNO (XEXP (link, 0));
1237 if (! reg_equiv_replace[regno])
1240 equiv_insn = reg_equiv_init_insn[regno];
1242 if (validate_replace_rtx (regno_reg_rtx[regno],
1243 reg_equiv_replacement[regno], insn))
1245 remove_death (regno, insn);
1246 REG_N_REFS (regno) = 0;
1247 PUT_CODE (equiv_insn, NOTE);
1248 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1249 NOTE_SOURCE_FILE (equiv_insn) = 0;
1251 /* If we aren't in a loop, and there are no calls in
1252 INSN or in the initialization of the register, then
1253 move the initialization of the register to just
1254 before INSN. Update the flow information. */
1256 && GET_CODE (equiv_insn) == INSN
1257 && GET_CODE (insn) == INSN
1258 && REG_BASIC_BLOCK (regno) < 0)
1262 emit_insn_before (copy_rtx (PATTERN (equiv_insn)), insn);
1263 REG_NOTES (PREV_INSN (insn)) = REG_NOTES (equiv_insn);
1265 PUT_CODE (equiv_insn, NOTE);
1266 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1267 NOTE_SOURCE_FILE (equiv_insn) = 0;
1268 REG_NOTES (equiv_insn) = 0;
1271 REG_BASIC_BLOCK (regno) = 0;
1273 REG_BASIC_BLOCK (regno) = block;
1274 REG_N_CALLS_CROSSED (regno) = 0;
1275 REG_LIVE_LENGTH (regno) = 2;
1277 if (block >= 0 && insn == basic_block_head[block])
1278 basic_block_head[block] = PREV_INSN (insn);
1280 for (l = 0; l < n_basic_blocks; l++)
1281 CLEAR_REGNO_REG_SET (basic_block_live_at_start[l], regno);
1288 /* Allocate hard regs to the pseudo regs used only within block number B.
1289 Only the pseudos that die but once can be handled. */
1298 int insn_number = 0;
1300 int max_uid = get_max_uid ();
1302 int no_conflict_combined_regno = -1;
1303 /* Counter to prevent allocating more SCRATCHes than can be stored
1305 int scratches_allocated = scratch_index;
1307 /* Count the instructions in the basic block. */
1309 insn = basic_block_end[b];
1312 if (GET_CODE (insn) != NOTE)
1313 if (++insn_count > max_uid)
1315 if (insn == basic_block_head[b])
1317 insn = PREV_INSN (insn);
1320 /* +2 to leave room for a post_mark_life at the last insn and for
1321 the birth of a CLOBBER in the first insn. */
1322 regs_live_at = (HARD_REG_SET *) alloca ((2 * insn_count + 2)
1323 * sizeof (HARD_REG_SET));
1324 bzero ((char *) regs_live_at, (2 * insn_count + 2) * sizeof (HARD_REG_SET));
1326 /* Initialize table of hardware registers currently live. */
1328 REG_SET_TO_HARD_REG_SET (regs_live, basic_block_live_at_start[b]);
1330 /* This loop scans the instructions of the basic block
1331 and assigns quantities to registers.
1332 It computes which registers to tie. */
1334 insn = basic_block_head[b];
1337 register rtx body = PATTERN (insn);
1339 if (GET_CODE (insn) != NOTE)
1342 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1344 register rtx link, set;
1345 register int win = 0;
1346 register rtx r0, r1;
1347 int combined_regno = -1;
1349 int insn_code_number = recog_memoized (insn);
1351 this_insn_number = insn_number;
1354 if (insn_code_number >= 0)
1355 insn_extract (insn);
1356 which_alternative = -1;
1358 /* Is this insn suitable for tying two registers?
1359 If so, try doing that.
1360 Suitable insns are those with at least two operands and where
1361 operand 0 is an output that is a register that is not
1364 We can tie operand 0 with some operand that dies in this insn.
1365 First look for operands that are required to be in the same
1366 register as operand 0. If we find such, only try tying that
1367 operand or one that can be put into that operand if the
1368 operation is commutative. If we don't find an operand
1369 that is required to be in the same register as operand 0,
1370 we can tie with any operand.
1372 Subregs in place of regs are also ok.
1374 If tying is done, WIN is set nonzero. */
1376 if (insn_code_number >= 0
1377 #ifdef REGISTER_CONSTRAINTS
1378 && insn_n_operands[insn_code_number] > 1
1379 && insn_operand_constraint[insn_code_number][0][0] == '='
1380 && insn_operand_constraint[insn_code_number][0][1] != '&'
1382 && GET_CODE (PATTERN (insn)) == SET
1383 && rtx_equal_p (SET_DEST (PATTERN (insn)), recog_operand[0])
1387 #ifdef REGISTER_CONSTRAINTS
1388 /* If non-negative, is an operand that must match operand 0. */
1389 int must_match_0 = -1;
1390 /* Counts number of alternatives that require a match with
1392 int n_matching_alts = 0;
1394 for (i = 1; i < insn_n_operands[insn_code_number]; i++)
1396 char *p = insn_operand_constraint[insn_code_number][i];
1397 int this_match = (requires_inout (p));
1399 n_matching_alts += this_match;
1400 if (this_match == insn_n_alternatives[insn_code_number])
1405 r0 = recog_operand[0];
1406 for (i = 1; i < insn_n_operands[insn_code_number]; i++)
1408 #ifdef REGISTER_CONSTRAINTS
1409 /* Skip this operand if we found an operand that
1410 must match operand 0 and this operand isn't it
1411 and can't be made to be it by commutativity. */
1413 if (must_match_0 >= 0 && i != must_match_0
1414 && ! (i == must_match_0 + 1
1415 && insn_operand_constraint[insn_code_number][i-1][0] == '%')
1416 && ! (i == must_match_0 - 1
1417 && insn_operand_constraint[insn_code_number][i][0] == '%'))
1420 /* Likewise if each alternative has some operand that
1421 must match operand zero. In that case, skip any
1422 operand that doesn't list operand 0 since we know that
1423 the operand always conflicts with operand 0. We
1424 ignore commutatity in this case to keep things simple. */
1425 if (n_matching_alts == insn_n_alternatives[insn_code_number]
1426 && (0 == requires_inout
1427 (insn_operand_constraint[insn_code_number][i])))
1431 r1 = recog_operand[i];
1433 /* If the operand is an address, find a register in it.
1434 There may be more than one register, but we only try one
1437 #ifdef REGISTER_CONSTRAINTS
1438 insn_operand_constraint[insn_code_number][i][0] == 'p'
1440 insn_operand_address_p[insn_code_number][i]
1443 while (GET_CODE (r1) == PLUS || GET_CODE (r1) == MULT)
1446 if (GET_CODE (r0) == REG || GET_CODE (r0) == SUBREG)
1448 /* We have two priorities for hard register preferences.
1449 If we have a move insn or an insn whose first input
1450 can only be in the same register as the output, give
1451 priority to an equivalence found from that insn. */
1453 = ((SET_DEST (body) == r0 && SET_SRC (body) == r1)
1454 #ifdef REGISTER_CONSTRAINTS
1455 || (r1 == recog_operand[i] && must_match_0 >= 0)
1459 if (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1460 win = combine_regs (r1, r0, may_save_copy,
1461 insn_number, insn, 0);
1468 /* Recognize an insn sequence with an ultimate result
1469 which can safely overlap one of the inputs.
1470 The sequence begins with a CLOBBER of its result,
1471 and ends with an insn that copies the result to itself
1472 and has a REG_EQUAL note for an equivalent formula.
1473 That note indicates what the inputs are.
1474 The result and the input can overlap if each insn in
1475 the sequence either doesn't mention the input
1476 or has a REG_NO_CONFLICT note to inhibit the conflict.
1478 We do the combining test at the CLOBBER so that the
1479 destination register won't have had a quantity number
1480 assigned, since that would prevent combining. */
1482 if (GET_CODE (PATTERN (insn)) == CLOBBER
1483 && (r0 = XEXP (PATTERN (insn), 0),
1484 GET_CODE (r0) == REG)
1485 && (link = find_reg_note (insn, REG_LIBCALL, NULL_RTX)) != 0
1486 && XEXP (link, 0) != 0
1487 && GET_CODE (XEXP (link, 0)) == INSN
1488 && (set = single_set (XEXP (link, 0))) != 0
1489 && SET_DEST (set) == r0 && SET_SRC (set) == r0
1490 && (note = find_reg_note (XEXP (link, 0), REG_EQUAL,
1493 if (r1 = XEXP (note, 0), GET_CODE (r1) == REG
1494 /* Check that we have such a sequence. */
1495 && no_conflict_p (insn, r0, r1))
1496 win = combine_regs (r1, r0, 1, insn_number, insn, 1);
1497 else if (GET_RTX_FORMAT (GET_CODE (XEXP (note, 0)))[0] == 'e'
1498 && (r1 = XEXP (XEXP (note, 0), 0),
1499 GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1500 && no_conflict_p (insn, r0, r1))
1501 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1503 /* Here we care if the operation to be computed is
1505 else if ((GET_CODE (XEXP (note, 0)) == EQ
1506 || GET_CODE (XEXP (note, 0)) == NE
1507 || GET_RTX_CLASS (GET_CODE (XEXP (note, 0))) == 'c')
1508 && (r1 = XEXP (XEXP (note, 0), 1),
1509 (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG))
1510 && no_conflict_p (insn, r0, r1))
1511 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1513 /* If we did combine something, show the register number
1514 in question so that we know to ignore its death. */
1516 no_conflict_combined_regno = REGNO (r1);
1519 /* If registers were just tied, set COMBINED_REGNO
1520 to the number of the register used in this insn
1521 that was tied to the register set in this insn.
1522 This register's qty should not be "killed". */
1526 while (GET_CODE (r1) == SUBREG)
1527 r1 = SUBREG_REG (r1);
1528 combined_regno = REGNO (r1);
1531 /* Mark the death of everything that dies in this instruction,
1532 except for anything that was just combined. */
1534 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1535 if (REG_NOTE_KIND (link) == REG_DEAD
1536 && GET_CODE (XEXP (link, 0)) == REG
1537 && combined_regno != REGNO (XEXP (link, 0))
1538 && (no_conflict_combined_regno != REGNO (XEXP (link, 0))
1539 || ! find_reg_note (insn, REG_NO_CONFLICT, XEXP (link, 0))))
1540 wipe_dead_reg (XEXP (link, 0), 0);
1542 /* Allocate qty numbers for all registers local to this block
1543 that are born (set) in this instruction.
1544 A pseudo that already has a qty is not changed. */
1546 note_stores (PATTERN (insn), reg_is_set);
1548 /* If anything is set in this insn and then unused, mark it as dying
1549 after this insn, so it will conflict with our outputs. This
1550 can't match with something that combined, and it doesn't matter
1551 if it did. Do this after the calls to reg_is_set since these
1552 die after, not during, the current insn. */
1554 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1555 if (REG_NOTE_KIND (link) == REG_UNUSED
1556 && GET_CODE (XEXP (link, 0)) == REG)
1557 wipe_dead_reg (XEXP (link, 0), 1);
1559 /* Allocate quantities for any SCRATCH operands of this insn. */
1561 if (insn_code_number >= 0)
1562 for (i = 0; i < insn_n_operands[insn_code_number]; i++)
1563 if (GET_CODE (recog_operand[i]) == SCRATCH
1564 && scratches_allocated++ < scratch_list_length)
1565 alloc_qty_for_scratch (recog_operand[i], i, insn,
1566 insn_code_number, insn_number);
1568 /* If this is an insn that has a REG_RETVAL note pointing at a
1569 CLOBBER insn, we have reached the end of a REG_NO_CONFLICT
1570 block, so clear any register number that combined within it. */
1571 if ((note = find_reg_note (insn, REG_RETVAL, NULL_RTX)) != 0
1572 && GET_CODE (XEXP (note, 0)) == INSN
1573 && GET_CODE (PATTERN (XEXP (note, 0))) == CLOBBER)
1574 no_conflict_combined_regno = -1;
1577 /* Set the registers live after INSN_NUMBER. Note that we never
1578 record the registers live before the block's first insn, since no
1579 pseudos we care about are live before that insn. */
1581 IOR_HARD_REG_SET (regs_live_at[2 * insn_number], regs_live);
1582 IOR_HARD_REG_SET (regs_live_at[2 * insn_number + 1], regs_live);
1584 if (insn == basic_block_end[b])
1587 insn = NEXT_INSN (insn);
1590 /* Now every register that is local to this basic block
1591 should have been given a quantity, or else -1 meaning ignore it.
1592 Every quantity should have a known birth and death.
1594 Order the qtys so we assign them registers in order of the
1595 number of suggested registers they need so we allocate those with
1596 the most restrictive needs first. */
1598 qty_order = (int *) alloca (next_qty * sizeof (int));
1599 for (i = 0; i < next_qty; i++)
1602 #define EXCHANGE(I1, I2) \
1603 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1608 /* Make qty_order[2] be the one to allocate last. */
1609 if (qty_sugg_compare (0, 1) > 0)
1611 if (qty_sugg_compare (1, 2) > 0)
1614 /* ... Fall through ... */
1616 /* Put the best one to allocate in qty_order[0]. */
1617 if (qty_sugg_compare (0, 1) > 0)
1620 /* ... Fall through ... */
1624 /* Nothing to do here. */
1628 qsort (qty_order, next_qty, sizeof (int), qty_sugg_compare_1);
1631 /* Try to put each quantity in a suggested physical register, if it has one.
1632 This may cause registers to be allocated that otherwise wouldn't be, but
1633 this seems acceptable in local allocation (unlike global allocation). */
1634 for (i = 0; i < next_qty; i++)
1637 if (qty_phys_num_sugg[q] != 0 || qty_phys_num_copy_sugg[q] != 0)
1638 qty_phys_reg[q] = find_free_reg (qty_min_class[q], qty_mode[q], q,
1639 0, 1, qty_birth[q], qty_death[q]);
1641 qty_phys_reg[q] = -1;
1644 /* Order the qtys so we assign them registers in order of
1645 decreasing length of life. Normally call qsort, but if we
1646 have only a very small number of quantities, sort them ourselves. */
1648 for (i = 0; i < next_qty; i++)
1651 #define EXCHANGE(I1, I2) \
1652 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1657 /* Make qty_order[2] be the one to allocate last. */
1658 if (qty_compare (0, 1) > 0)
1660 if (qty_compare (1, 2) > 0)
1663 /* ... Fall through ... */
1665 /* Put the best one to allocate in qty_order[0]. */
1666 if (qty_compare (0, 1) > 0)
1669 /* ... Fall through ... */
1673 /* Nothing to do here. */
1677 qsort (qty_order, next_qty, sizeof (int), qty_compare_1);
1680 /* Now for each qty that is not a hardware register,
1681 look for a hardware register to put it in.
1682 First try the register class that is cheapest for this qty,
1683 if there is more than one class. */
1685 for (i = 0; i < next_qty; i++)
1688 if (qty_phys_reg[q] < 0)
1690 if (N_REG_CLASSES > 1)
1692 qty_phys_reg[q] = find_free_reg (qty_min_class[q],
1693 qty_mode[q], q, 0, 0,
1694 qty_birth[q], qty_death[q]);
1695 if (qty_phys_reg[q] >= 0)
1699 if (qty_alternate_class[q] != NO_REGS)
1700 qty_phys_reg[q] = find_free_reg (qty_alternate_class[q],
1701 qty_mode[q], q, 0, 0,
1702 qty_birth[q], qty_death[q]);
1706 /* Now propagate the register assignments
1707 to the pseudo regs belonging to the qtys. */
1709 for (q = 0; q < next_qty; q++)
1710 if (qty_phys_reg[q] >= 0)
1712 for (i = qty_first_reg[q]; i >= 0; i = reg_next_in_qty[i])
1713 reg_renumber[i] = qty_phys_reg[q] + reg_offset[i];
1714 if (qty_scratch_rtx[q])
1716 if (GET_CODE (qty_scratch_rtx[q]) == REG)
1719 qty_scratch_rtx[q] = gen_rtx (REG, GET_MODE (qty_scratch_rtx[q]),
1722 scratch_block[scratch_index] = b;
1723 scratch_list[scratch_index++] = qty_scratch_rtx[q];
1728 /* Compare two quantities' priority for getting real registers.
1729 We give shorter-lived quantities higher priority.
1730 Quantities with more references are also preferred, as are quantities that
1731 require multiple registers. This is the identical prioritization as
1732 done by global-alloc.
1734 We used to give preference to registers with *longer* lives, but using
1735 the same algorithm in both local- and global-alloc can speed up execution
1736 of some programs by as much as a factor of three! */
1738 /* Note that the quotient will never be bigger than
1739 the value of floor_log2 times the maximum number of
1740 times a register can occur in one insn (surely less than 100).
1741 Multiplying this by 10000 can't overflow.
1742 QTY_CMP_PRI is also used by qty_sugg_compare. */
1744 #define QTY_CMP_PRI(q) \
1745 ((int) (((double) (floor_log2 (qty_n_refs[q]) * qty_n_refs[q] * qty_size[q]) \
1746 / (qty_death[q] - qty_birth[q])) * 10000))
1749 qty_compare (q1, q2)
1752 return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1756 qty_compare_1 (q1p, q2p)
1757 const GENERIC_PTR q1p;
1758 const GENERIC_PTR q2p;
1760 register int q1 = *(int *)q1p, q2 = *(int *)q2p;
1761 register int tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1766 /* If qtys are equally good, sort by qty number,
1767 so that the results of qsort leave nothing to chance. */
1771 /* Compare two quantities' priority for getting real registers. This version
1772 is called for quantities that have suggested hard registers. First priority
1773 goes to quantities that have copy preferences, then to those that have
1774 normal preferences. Within those groups, quantities with the lower
1775 number of preferences have the highest priority. Of those, we use the same
1776 algorithm as above. */
1778 #define QTY_CMP_SUGG(q) \
1779 (qty_phys_num_copy_sugg[q] \
1780 ? qty_phys_num_copy_sugg[q] \
1781 : qty_phys_num_sugg[q] * FIRST_PSEUDO_REGISTER)
1784 qty_sugg_compare (q1, q2)
1787 register int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2);
1792 return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1796 qty_sugg_compare_1 (q1p, q2p)
1797 const GENERIC_PTR q1p;
1798 const GENERIC_PTR q2p;
1800 register int q1 = *(int *)q1p, q2 = *(int *)q2p;
1801 register int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2);
1806 tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1810 /* If qtys are equally good, sort by qty number,
1811 so that the results of qsort leave nothing to chance. */
1818 /* Attempt to combine the two registers (rtx's) USEDREG and SETREG.
1819 Returns 1 if have done so, or 0 if cannot.
1821 Combining registers means marking them as having the same quantity
1822 and adjusting the offsets within the quantity if either of
1825 We don't actually combine a hard reg with a pseudo; instead
1826 we just record the hard reg as the suggestion for the pseudo's quantity.
1827 If we really combined them, we could lose if the pseudo lives
1828 across an insn that clobbers the hard reg (eg, movstr).
1830 ALREADY_DEAD is non-zero if USEDREG is known to be dead even though
1831 there is no REG_DEAD note on INSN. This occurs during the processing
1832 of REG_NO_CONFLICT blocks.
1834 MAY_SAVE_COPYCOPY is non-zero if this insn is simply copying USEDREG to
1835 SETREG or if the input and output must share a register.
1836 In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG.
1838 There are elaborate checks for the validity of combining. */
1842 combine_regs (usedreg, setreg, may_save_copy, insn_number, insn, already_dead)
1843 rtx usedreg, setreg;
1849 register int ureg, sreg;
1850 register int offset = 0;
1854 /* Determine the numbers and sizes of registers being used. If a subreg
1855 is present that does not change the entire register, don't consider
1856 this a copy insn. */
1858 while (GET_CODE (usedreg) == SUBREG)
1860 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (usedreg))) > UNITS_PER_WORD)
1862 offset += SUBREG_WORD (usedreg);
1863 usedreg = SUBREG_REG (usedreg);
1865 if (GET_CODE (usedreg) != REG)
1867 ureg = REGNO (usedreg);
1868 usize = REG_SIZE (usedreg);
1870 while (GET_CODE (setreg) == SUBREG)
1872 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (setreg))) > UNITS_PER_WORD)
1874 offset -= SUBREG_WORD (setreg);
1875 setreg = SUBREG_REG (setreg);
1877 if (GET_CODE (setreg) != REG)
1879 sreg = REGNO (setreg);
1880 ssize = REG_SIZE (setreg);
1882 /* If UREG is a pseudo-register that hasn't already been assigned a
1883 quantity number, it means that it is not local to this block or dies
1884 more than once. In either event, we can't do anything with it. */
1885 if ((ureg >= FIRST_PSEUDO_REGISTER && reg_qty[ureg] < 0)
1886 /* Do not combine registers unless one fits within the other. */
1887 || (offset > 0 && usize + offset > ssize)
1888 || (offset < 0 && usize + offset < ssize)
1889 /* Do not combine with a smaller already-assigned object
1890 if that smaller object is already combined with something bigger. */
1891 || (ssize > usize && ureg >= FIRST_PSEUDO_REGISTER
1892 && usize < qty_size[reg_qty[ureg]])
1893 /* Can't combine if SREG is not a register we can allocate. */
1894 || (sreg >= FIRST_PSEUDO_REGISTER && reg_qty[sreg] == -1)
1895 /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note.
1896 These have already been taken care of. This probably wouldn't
1897 combine anyway, but don't take any chances. */
1898 || (ureg >= FIRST_PSEUDO_REGISTER
1899 && find_reg_note (insn, REG_NO_CONFLICT, usedreg))
1900 /* Don't tie something to itself. In most cases it would make no
1901 difference, but it would screw up if the reg being tied to itself
1902 also dies in this insn. */
1904 /* Don't try to connect two different hardware registers. */
1905 || (ureg < FIRST_PSEUDO_REGISTER && sreg < FIRST_PSEUDO_REGISTER)
1906 /* Don't connect two different machine modes if they have different
1907 implications as to which registers may be used. */
1908 || !MODES_TIEABLE_P (GET_MODE (usedreg), GET_MODE (setreg)))
1911 /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in
1912 qty_phys_sugg for the pseudo instead of tying them.
1914 Return "failure" so that the lifespan of UREG is terminated here;
1915 that way the two lifespans will be disjoint and nothing will prevent
1916 the pseudo reg from being given this hard reg. */
1918 if (ureg < FIRST_PSEUDO_REGISTER)
1920 /* Allocate a quantity number so we have a place to put our
1922 if (reg_qty[sreg] == -2)
1923 reg_is_born (setreg, 2 * insn_number);
1925 if (reg_qty[sreg] >= 0)
1928 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg))
1930 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg);
1931 qty_phys_num_copy_sugg[reg_qty[sreg]]++;
1933 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg))
1935 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg);
1936 qty_phys_num_sugg[reg_qty[sreg]]++;
1942 /* Similarly for SREG a hard register and UREG a pseudo register. */
1944 if (sreg < FIRST_PSEUDO_REGISTER)
1947 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg))
1949 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg);
1950 qty_phys_num_copy_sugg[reg_qty[ureg]]++;
1952 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg))
1954 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg);
1955 qty_phys_num_sugg[reg_qty[ureg]]++;
1960 /* At this point we know that SREG and UREG are both pseudos.
1961 Do nothing if SREG already has a quantity or is a register that we
1963 if (reg_qty[sreg] >= -1
1964 /* If we are not going to let any regs live across calls,
1965 don't tie a call-crossing reg to a non-call-crossing reg. */
1966 || (current_function_has_nonlocal_label
1967 && ((REG_N_CALLS_CROSSED (ureg) > 0)
1968 != (REG_N_CALLS_CROSSED (sreg) > 0))))
1971 /* We don't already know about SREG, so tie it to UREG
1972 if this is the last use of UREG, provided the classes they want
1975 if ((already_dead || find_regno_note (insn, REG_DEAD, ureg))
1976 && reg_meets_class_p (sreg, qty_min_class[reg_qty[ureg]]))
1978 /* Add SREG to UREG's quantity. */
1979 sqty = reg_qty[ureg];
1980 reg_qty[sreg] = sqty;
1981 reg_offset[sreg] = reg_offset[ureg] + offset;
1982 reg_next_in_qty[sreg] = qty_first_reg[sqty];
1983 qty_first_reg[sqty] = sreg;
1985 /* If SREG's reg class is smaller, set qty_min_class[SQTY]. */
1986 update_qty_class (sqty, sreg);
1988 /* Update info about quantity SQTY. */
1989 qty_n_calls_crossed[sqty] += REG_N_CALLS_CROSSED (sreg);
1990 qty_n_refs[sqty] += REG_N_REFS (sreg);
1995 for (i = qty_first_reg[sqty]; i >= 0; i = reg_next_in_qty[i])
1996 reg_offset[i] -= offset;
1998 qty_size[sqty] = ssize;
1999 qty_mode[sqty] = GET_MODE (setreg);
2008 /* Return 1 if the preferred class of REG allows it to be tied
2009 to a quantity or register whose class is CLASS.
2010 True if REG's reg class either contains or is contained in CLASS. */
2013 reg_meets_class_p (reg, class)
2015 enum reg_class class;
2017 register enum reg_class rclass = reg_preferred_class (reg);
2018 return (reg_class_subset_p (rclass, class)
2019 || reg_class_subset_p (class, rclass));
2022 /* Return 1 if the two specified classes have registers in common.
2023 If CALL_SAVED, then consider only call-saved registers. */
2026 reg_classes_overlap_p (c1, c2, call_saved)
2027 register enum reg_class c1;
2028 register enum reg_class c2;
2034 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
2035 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
2037 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2038 if (TEST_HARD_REG_BIT (c, i)
2039 && (! call_saved || ! call_used_regs[i]))
2045 /* Update the class of QTY assuming that REG is being tied to it. */
2048 update_qty_class (qty, reg)
2052 enum reg_class rclass = reg_preferred_class (reg);
2053 if (reg_class_subset_p (rclass, qty_min_class[qty]))
2054 qty_min_class[qty] = rclass;
2056 rclass = reg_alternate_class (reg);
2057 if (reg_class_subset_p (rclass, qty_alternate_class[qty]))
2058 qty_alternate_class[qty] = rclass;
2060 if (REG_CHANGES_SIZE (reg))
2061 qty_changes_size[qty] = 1;
2064 /* Handle something which alters the value of an rtx REG.
2066 REG is whatever is set or clobbered. SETTER is the rtx that
2067 is modifying the register.
2069 If it is not really a register, we do nothing.
2070 The file-global variables `this_insn' and `this_insn_number'
2071 carry info from `block_alloc'. */
2074 reg_is_set (reg, setter)
2078 /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of
2079 a hard register. These may actually not exist any more. */
2081 if (GET_CODE (reg) != SUBREG
2082 && GET_CODE (reg) != REG)
2085 /* Mark this register as being born. If it is used in a CLOBBER, mark
2086 it as being born halfway between the previous insn and this insn so that
2087 it conflicts with our inputs but not the outputs of the previous insn. */
2089 reg_is_born (reg, 2 * this_insn_number - (GET_CODE (setter) == CLOBBER));
2092 /* Handle beginning of the life of register REG.
2093 BIRTH is the index at which this is happening. */
2096 reg_is_born (reg, birth)
2102 if (GET_CODE (reg) == SUBREG)
2103 regno = REGNO (SUBREG_REG (reg)) + SUBREG_WORD (reg);
2105 regno = REGNO (reg);
2107 if (regno < FIRST_PSEUDO_REGISTER)
2109 mark_life (regno, GET_MODE (reg), 1);
2111 /* If the register was to have been born earlier that the present
2112 insn, mark it as live where it is actually born. */
2113 if (birth < 2 * this_insn_number)
2114 post_mark_life (regno, GET_MODE (reg), 1, birth, 2 * this_insn_number);
2118 if (reg_qty[regno] == -2)
2119 alloc_qty (regno, GET_MODE (reg), PSEUDO_REGNO_SIZE (regno), birth);
2121 /* If this register has a quantity number, show that it isn't dead. */
2122 if (reg_qty[regno] >= 0)
2123 qty_death[reg_qty[regno]] = -1;
2127 /* Record the death of REG in the current insn. If OUTPUT_P is non-zero,
2128 REG is an output that is dying (i.e., it is never used), otherwise it
2129 is an input (the normal case).
2130 If OUTPUT_P is 1, then we extend the life past the end of this insn. */
2133 wipe_dead_reg (reg, output_p)
2137 register int regno = REGNO (reg);
2139 /* If this insn has multiple results,
2140 and the dead reg is used in one of the results,
2141 extend its life to after this insn,
2142 so it won't get allocated together with any other result of this insn. */
2143 if (GET_CODE (PATTERN (this_insn)) == PARALLEL
2144 && !single_set (this_insn))
2147 for (i = XVECLEN (PATTERN (this_insn), 0) - 1; i >= 0; i--)
2149 rtx set = XVECEXP (PATTERN (this_insn), 0, i);
2150 if (GET_CODE (set) == SET
2151 && GET_CODE (SET_DEST (set)) != REG
2152 && !rtx_equal_p (reg, SET_DEST (set))
2153 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
2158 /* If this register is used in an auto-increment address, then extend its
2159 life to after this insn, so that it won't get allocated together with
2160 the result of this insn. */
2161 if (! output_p && find_regno_note (this_insn, REG_INC, regno))
2164 if (regno < FIRST_PSEUDO_REGISTER)
2166 mark_life (regno, GET_MODE (reg), 0);
2168 /* If a hard register is dying as an output, mark it as in use at
2169 the beginning of this insn (the above statement would cause this
2172 post_mark_life (regno, GET_MODE (reg), 1,
2173 2 * this_insn_number, 2 * this_insn_number+ 1);
2176 else if (reg_qty[regno] >= 0)
2177 qty_death[reg_qty[regno]] = 2 * this_insn_number + output_p;
2180 /* Find a block of SIZE words of hard regs in reg_class CLASS
2181 that can hold something of machine-mode MODE
2182 (but actually we test only the first of the block for holding MODE)
2183 and still free between insn BORN_INDEX and insn DEAD_INDEX,
2184 and return the number of the first of them.
2185 Return -1 if such a block cannot be found.
2186 If QTY crosses calls, insist on a register preserved by calls,
2187 unless ACCEPT_CALL_CLOBBERED is nonzero.
2189 If JUST_TRY_SUGGESTED is non-zero, only try to see if the suggested
2190 register is available. If not, return -1. */
2193 find_free_reg (class, mode, qty, accept_call_clobbered, just_try_suggested,
2194 born_index, dead_index)
2195 enum reg_class class;
2196 enum machine_mode mode;
2198 int accept_call_clobbered;
2199 int just_try_suggested;
2200 int born_index, dead_index;
2202 register int i, ins;
2204 register /* Declare it register if it's a scalar. */
2206 HARD_REG_SET used, first_used;
2207 #ifdef ELIMINABLE_REGS
2208 static struct {int from, to; } eliminables[] = ELIMINABLE_REGS;
2211 /* Validate our parameters. */
2212 if (born_index < 0 || born_index > dead_index)
2215 /* Don't let a pseudo live in a reg across a function call
2216 if we might get a nonlocal goto. */
2217 if (current_function_has_nonlocal_label
2218 && qty_n_calls_crossed[qty] > 0)
2221 if (accept_call_clobbered)
2222 COPY_HARD_REG_SET (used, call_fixed_reg_set);
2223 else if (qty_n_calls_crossed[qty] == 0)
2224 COPY_HARD_REG_SET (used, fixed_reg_set);
2226 COPY_HARD_REG_SET (used, call_used_reg_set);
2228 if (accept_call_clobbered)
2229 IOR_HARD_REG_SET (used, losing_caller_save_reg_set);
2231 for (ins = born_index; ins < dead_index; ins++)
2232 IOR_HARD_REG_SET (used, regs_live_at[ins]);
2234 IOR_COMPL_HARD_REG_SET (used, reg_class_contents[(int) class]);
2236 /* Don't use the frame pointer reg in local-alloc even if
2237 we may omit the frame pointer, because if we do that and then we
2238 need a frame pointer, reload won't know how to move the pseudo
2239 to another hard reg. It can move only regs made by global-alloc.
2241 This is true of any register that can be eliminated. */
2242 #ifdef ELIMINABLE_REGS
2243 for (i = 0; i < sizeof eliminables / sizeof eliminables[0]; i++)
2244 SET_HARD_REG_BIT (used, eliminables[i].from);
2245 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
2246 /* If FRAME_POINTER_REGNUM is not a real register, then protect the one
2247 that it might be eliminated into. */
2248 SET_HARD_REG_BIT (used, HARD_FRAME_POINTER_REGNUM);
2251 SET_HARD_REG_BIT (used, FRAME_POINTER_REGNUM);
2254 #ifdef CLASS_CANNOT_CHANGE_SIZE
2255 if (qty_changes_size[qty])
2256 IOR_HARD_REG_SET (used,
2257 reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE]);
2260 /* Normally, the registers that can be used for the first register in
2261 a multi-register quantity are the same as those that can be used for
2262 subsequent registers. However, if just trying suggested registers,
2263 restrict our consideration to them. If there are copy-suggested
2264 register, try them. Otherwise, try the arithmetic-suggested
2266 COPY_HARD_REG_SET (first_used, used);
2268 if (just_try_suggested)
2270 if (qty_phys_num_copy_sugg[qty] != 0)
2271 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_copy_sugg[qty]);
2273 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_sugg[qty]);
2276 /* If all registers are excluded, we can't do anything. */
2277 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) ALL_REGS], first_used, fail);
2279 /* If at least one would be suitable, test each hard reg. */
2281 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2283 #ifdef REG_ALLOC_ORDER
2284 int regno = reg_alloc_order[i];
2288 if (! TEST_HARD_REG_BIT (first_used, regno)
2289 && HARD_REGNO_MODE_OK (regno, mode))
2292 register int size1 = HARD_REGNO_NREGS (regno, mode);
2293 for (j = 1; j < size1 && ! TEST_HARD_REG_BIT (used, regno + j); j++);
2296 /* Mark that this register is in use between its birth and death
2298 post_mark_life (regno, mode, 1, born_index, dead_index);
2301 #ifndef REG_ALLOC_ORDER
2302 i += j; /* Skip starting points we know will lose */
2309 /* If we are just trying suggested register, we have just tried copy-
2310 suggested registers, and there are arithmetic-suggested registers,
2313 /* If it would be profitable to allocate a call-clobbered register
2314 and save and restore it around calls, do that. */
2315 if (just_try_suggested && qty_phys_num_copy_sugg[qty] != 0
2316 && qty_phys_num_sugg[qty] != 0)
2318 /* Don't try the copy-suggested regs again. */
2319 qty_phys_num_copy_sugg[qty] = 0;
2320 return find_free_reg (class, mode, qty, accept_call_clobbered, 1,
2321 born_index, dead_index);
2324 /* We need not check to see if the current function has nonlocal
2325 labels because we don't put any pseudos that are live over calls in
2326 registers in that case. */
2328 if (! accept_call_clobbered
2329 && flag_caller_saves
2330 && ! just_try_suggested
2331 && qty_n_calls_crossed[qty] != 0
2332 && CALLER_SAVE_PROFITABLE (qty_n_refs[qty], qty_n_calls_crossed[qty]))
2334 i = find_free_reg (class, mode, qty, 1, 0, born_index, dead_index);
2336 caller_save_needed = 1;
2342 /* Mark that REGNO with machine-mode MODE is live starting from the current
2343 insn (if LIFE is non-zero) or dead starting at the current insn (if LIFE
2347 mark_life (regno, mode, life)
2349 enum machine_mode mode;
2352 register int j = HARD_REGNO_NREGS (regno, mode);
2355 SET_HARD_REG_BIT (regs_live, regno + j);
2358 CLEAR_HARD_REG_BIT (regs_live, regno + j);
2361 /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE
2362 is non-zero) or dead (if LIFE is zero) from insn number BIRTH (inclusive)
2363 to insn number DEATH (exclusive). */
2366 post_mark_life (regno, mode, life, birth, death)
2368 enum machine_mode mode;
2369 int life, birth, death;
2371 register int j = HARD_REGNO_NREGS (regno, mode);
2373 register /* Declare it register if it's a scalar. */
2375 HARD_REG_SET this_reg;
2377 CLEAR_HARD_REG_SET (this_reg);
2379 SET_HARD_REG_BIT (this_reg, regno + j);
2382 while (birth < death)
2384 IOR_HARD_REG_SET (regs_live_at[birth], this_reg);
2388 while (birth < death)
2390 AND_COMPL_HARD_REG_SET (regs_live_at[birth], this_reg);
2395 /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0
2396 is the register being clobbered, and R1 is a register being used in
2397 the equivalent expression.
2399 If R1 dies in the block and has a REG_NO_CONFLICT note on every insn
2400 in which it is used, return 1.
2402 Otherwise, return 0. */
2405 no_conflict_p (insn, r0, r1)
2409 rtx note = find_reg_note (insn, REG_LIBCALL, NULL_RTX);
2412 /* If R1 is a hard register, return 0 since we handle this case
2413 when we scan the insns that actually use it. */
2416 || (GET_CODE (r1) == REG && REGNO (r1) < FIRST_PSEUDO_REGISTER)
2417 || (GET_CODE (r1) == SUBREG && GET_CODE (SUBREG_REG (r1)) == REG
2418 && REGNO (SUBREG_REG (r1)) < FIRST_PSEUDO_REGISTER))
2421 last = XEXP (note, 0);
2423 for (p = NEXT_INSN (insn); p && p != last; p = NEXT_INSN (p))
2424 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
2426 if (find_reg_note (p, REG_DEAD, r1))
2429 /* There must be a REG_NO_CONFLICT note on every insn, otherwise
2430 some earlier optimization pass has inserted instructions into
2431 the sequence, and it is not safe to perform this optimization.
2432 Note that emit_no_conflict_block always ensures that this is
2433 true when these sequences are created. */
2434 if (! find_reg_note (p, REG_NO_CONFLICT, r1))
2441 #ifdef REGISTER_CONSTRAINTS
2443 /* Return the number of alternatives for which the constraint string P
2444 indicates that the operand must be equal to operand 0 and that no register
2453 int reg_allowed = 0;
2454 int num_matching_alts = 0;
2459 case '=': case '+': case '?':
2460 case '#': case '&': case '!':
2462 case '1': case '2': case '3': case '4':
2463 case 'm': case '<': case '>': case 'V': case 'o':
2464 case 'E': case 'F': case 'G': case 'H':
2465 case 's': case 'i': case 'n':
2466 case 'I': case 'J': case 'K': case 'L':
2467 case 'M': case 'N': case 'O': case 'P':
2468 #ifdef EXTRA_CONSTRAINT
2469 case 'Q': case 'R': case 'S': case 'T': case 'U':
2472 /* These don't say anything we care about. */
2476 if (found_zero && ! reg_allowed)
2477 num_matching_alts++;
2479 found_zero = reg_allowed = 0;
2493 if (found_zero && ! reg_allowed)
2494 num_matching_alts++;
2496 return num_matching_alts;
2498 #endif /* REGISTER_CONSTRAINTS */
2501 dump_local_alloc (file)
2505 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
2506 if (reg_renumber[i] != -1)
2507 fprintf (file, ";; Register %d in %d.\n", i, reg_renumber[i]);
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