1 /* Allocate registers within a basic block, for GNU compiler.
2 Copyright (C) 1987, 88, 91, 93-97, 1998 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* Allocation of hard register numbers to pseudo registers is done in
23 two passes. In this pass we consider only regs that are born and
24 die once within one basic block. We do this one basic block at a
25 time. Then the next pass allocates the registers that remain.
26 Two passes are used because this pass uses methods that work only
27 on linear code, but that do a better job than the general methods
28 used in global_alloc, and more quickly too.
30 The assignments made are recorded in the vector reg_renumber
31 whose space is allocated here. The rtl code itself is not altered.
33 We assign each instruction in the basic block a number
34 which is its order from the beginning of the block.
35 Then we can represent the lifetime of a pseudo register with
36 a pair of numbers, and check for conflicts easily.
37 We can record the availability of hard registers with a
38 HARD_REG_SET for each instruction. The HARD_REG_SET
39 contains 0 or 1 for each hard reg.
41 To avoid register shuffling, we tie registers together when one
42 dies by being copied into another, or dies in an instruction that
43 does arithmetic to produce another. The tied registers are
44 allocated as one. Registers with different reg class preferences
45 can never be tied unless the class preferred by one is a subclass
46 of the one preferred by the other.
48 Tying is represented with "quantity numbers".
49 A non-tied register is given a new quantity number.
50 Tied registers have the same quantity number.
52 We have provision to exempt registers, even when they are contained
53 within the block, that can be tied to others that are not contained in it.
54 This is so that global_alloc could process them both and tie them then.
55 But this is currently disabled since tying in global_alloc is not
58 /* Pseudos allocated here cannot be reallocated by global.c if the hard
59 register is used as a spill register. So we don't allocate such pseudos
60 here if their preferred class is likely to be used by spills. */
66 #include "basic-block.h"
68 #include "hard-reg-set.h"
69 #include "insn-config.h"
73 /* Next quantity number available for allocation. */
77 /* In all the following vectors indexed by quantity number. */
79 /* Element Q is the hard reg number chosen for quantity Q,
80 or -1 if none was found. */
82 static short *qty_phys_reg;
84 /* We maintain two hard register sets that indicate suggested hard registers
85 for each quantity. The first, qty_phys_copy_sugg, contains hard registers
86 that are tied to the quantity by a simple copy. The second contains all
87 hard registers that are tied to the quantity via an arithmetic operation.
89 The former register set is given priority for allocation. This tends to
90 eliminate copy insns. */
92 /* Element Q is a set of hard registers that are suggested for quantity Q by
95 static HARD_REG_SET *qty_phys_copy_sugg;
97 /* Element Q is a set of hard registers that are suggested for quantity Q by
100 static HARD_REG_SET *qty_phys_sugg;
102 /* Element Q is the number of suggested registers in qty_phys_copy_sugg. */
104 static short *qty_phys_num_copy_sugg;
106 /* Element Q is the number of suggested registers in qty_phys_sugg. */
108 static short *qty_phys_num_sugg;
110 /* Element Q is the number of refs to quantity Q. */
112 static int *qty_n_refs;
114 /* Element Q is a reg class contained in (smaller than) the
115 preferred classes of all the pseudo regs that are tied in quantity Q.
116 This is the preferred class for allocating that quantity. */
118 static enum reg_class *qty_min_class;
120 /* Insn number (counting from head of basic block)
121 where quantity Q was born. -1 if birth has not been recorded. */
123 static int *qty_birth;
125 /* Insn number (counting from head of basic block)
126 where quantity Q died. Due to the way tying is done,
127 and the fact that we consider in this pass only regs that die but once,
128 a quantity can die only once. Each quantity's life span
129 is a set of consecutive insns. -1 if death has not been recorded. */
131 static int *qty_death;
133 /* Number of words needed to hold the data in quantity Q.
134 This depends on its machine mode. It is used for these purposes:
135 1. It is used in computing the relative importances of qtys,
136 which determines the order in which we look for regs for them.
137 2. It is used in rules that prevent tying several registers of
138 different sizes in a way that is geometrically impossible
139 (see combine_regs). */
141 static int *qty_size;
143 /* This holds the mode of the registers that are tied to qty Q,
144 or VOIDmode if registers with differing modes are tied together. */
146 static enum machine_mode *qty_mode;
148 /* Number of times a reg tied to qty Q lives across a CALL_INSN. */
150 static int *qty_n_calls_crossed;
152 /* Register class within which we allocate qty Q if we can't get
153 its preferred class. */
155 static enum reg_class *qty_alternate_class;
157 /* Element Q is the SCRATCH expression for which this quantity is being
158 allocated or 0 if this quantity is allocating registers. */
160 static rtx *qty_scratch_rtx;
162 /* Element Q is nonzero if this quantity has been used in a SUBREG
163 that changes its size. */
165 static char *qty_changes_size;
167 /* Element Q is the register number of one pseudo register whose
168 reg_qty value is Q, or -1 is this quantity is for a SCRATCH. This
169 register should be the head of the chain maintained in reg_next_in_qty. */
171 static int *qty_first_reg;
173 /* If (REG N) has been assigned a quantity number, is a register number
174 of another register assigned the same quantity number, or -1 for the
175 end of the chain. qty_first_reg point to the head of this chain. */
177 static int *reg_next_in_qty;
179 /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg
181 of -1 if this register cannot be allocated by local-alloc,
182 or -2 if not known yet.
184 Note that if we see a use or death of pseudo register N with
185 reg_qty[N] == -2, register N must be local to the current block. If
186 it were used in more than one block, we would have reg_qty[N] == -1.
187 This relies on the fact that if reg_basic_block[N] is >= 0, register N
188 will not appear in any other block. We save a considerable number of
189 tests by exploiting this.
191 If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not
196 /* The offset (in words) of register N within its quantity.
197 This can be nonzero if register N is SImode, and has been tied
198 to a subreg of a DImode register. */
200 static char *reg_offset;
202 /* Vector of substitutions of register numbers,
203 used to map pseudo regs into hardware regs.
204 This is set up as a result of register allocation.
205 Element N is the hard reg assigned to pseudo reg N,
206 or is -1 if no hard reg was assigned.
207 If N is a hard reg number, element N is N. */
211 /* Set of hard registers live at the current point in the scan
212 of the instructions in a basic block. */
214 static HARD_REG_SET regs_live;
216 /* Each set of hard registers indicates registers live at a particular
217 point in the basic block. For N even, regs_live_at[N] says which
218 hard registers are needed *after* insn N/2 (i.e., they may not
219 conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1.
221 If an object is to conflict with the inputs of insn J but not the
222 outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly,
223 if it is to conflict with the outputs of insn J but not the inputs of
224 insn J + 1, it is said to die at index J*2 + 1. */
226 static HARD_REG_SET *regs_live_at;
230 int scratch_list_length;
231 static int scratch_index;
233 /* Communicate local vars `insn_number' and `insn'
234 from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */
235 static int this_insn_number;
236 static rtx this_insn;
238 /* Used to communicate changes made by update_equiv_regs to
239 memref_referenced_p. reg_equiv_replacement is set for any REG_EQUIV note
240 found or created, so that we can keep track of what memory accesses might
241 be created later, e.g. by reload. */
243 static rtx *reg_equiv_replacement;
245 static void alloc_qty PROTO((int, enum machine_mode, int, int));
246 static void alloc_qty_for_scratch PROTO((rtx, int, rtx, int, int));
247 static void validate_equiv_mem_from_store PROTO((rtx, rtx));
248 static int validate_equiv_mem PROTO((rtx, rtx, rtx));
249 static int contains_replace_regs PROTO((rtx, char *));
250 static int memref_referenced_p PROTO((rtx, rtx));
251 static int memref_used_between_p PROTO((rtx, rtx, rtx));
252 static void update_equiv_regs PROTO((void));
253 static void block_alloc PROTO((int));
254 static int qty_sugg_compare PROTO((int, int));
255 static int qty_sugg_compare_1 PROTO((const GENERIC_PTR, const GENERIC_PTR));
256 static int qty_compare PROTO((int, int));
257 static int qty_compare_1 PROTO((const GENERIC_PTR, const GENERIC_PTR));
258 static int combine_regs PROTO((rtx, rtx, int, int, rtx, int));
259 static int reg_meets_class_p PROTO((int, enum reg_class));
260 static void update_qty_class PROTO((int, int));
261 static void reg_is_set PROTO((rtx, rtx));
262 static void reg_is_born PROTO((rtx, int));
263 static void wipe_dead_reg PROTO((rtx, int));
264 static int find_free_reg PROTO((enum reg_class, enum machine_mode,
265 int, int, int, int, int));
266 static void mark_life PROTO((int, enum machine_mode, int));
267 static void post_mark_life PROTO((int, enum machine_mode, int, int, int));
268 static int no_conflict_p PROTO((rtx, rtx, rtx));
269 static int requires_inout PROTO((char *));
271 /* Allocate a new quantity (new within current basic block)
272 for register number REGNO which is born at index BIRTH
273 within the block. MODE and SIZE are info on reg REGNO. */
276 alloc_qty (regno, mode, size, birth)
278 enum machine_mode mode;
281 register int qty = next_qty++;
283 reg_qty[regno] = qty;
284 reg_offset[regno] = 0;
285 reg_next_in_qty[regno] = -1;
287 qty_first_reg[qty] = regno;
288 qty_size[qty] = size;
289 qty_mode[qty] = mode;
290 qty_birth[qty] = birth;
291 qty_n_calls_crossed[qty] = REG_N_CALLS_CROSSED (regno);
292 qty_min_class[qty] = reg_preferred_class (regno);
293 qty_alternate_class[qty] = reg_alternate_class (regno);
294 qty_n_refs[qty] = REG_N_REFS (regno);
295 qty_changes_size[qty] = REG_CHANGES_SIZE (regno);
298 /* Similar to `alloc_qty', but allocates a quantity for a SCRATCH rtx
299 used as operand N in INSN. We assume here that the SCRATCH is used in
303 alloc_qty_for_scratch (scratch, n, insn, insn_code_num, insn_number)
307 int insn_code_num, insn_number;
310 enum reg_class class;
314 #ifdef REGISTER_CONSTRAINTS
315 /* If we haven't yet computed which alternative will be used, do so now.
316 Then set P to the constraints for that alternative. */
317 if (which_alternative == -1)
318 if (! constrain_operands (insn_code_num, 0))
321 for (p = insn_operand_constraint[insn_code_num][n], i = 0;
322 *p && i < which_alternative; p++)
326 /* Compute the class required for this SCRATCH. If we don't need a
327 register, the class will remain NO_REGS. If we guessed the alternative
328 number incorrectly, reload will fix things up for us. */
331 while ((c = *p++) != '\0' && c != ',')
334 case '=': case '+': case '?':
335 case '#': case '&': case '!':
337 case '0': case '1': case '2': case '3': case '4':
338 case 'm': case '<': case '>': case 'V': case 'o':
339 case 'E': case 'F': case 'G': case 'H':
340 case 's': case 'i': case 'n':
341 case 'I': case 'J': case 'K': case 'L':
342 case 'M': case 'N': case 'O': case 'P':
343 #ifdef EXTRA_CONSTRAINT
344 case 'Q': case 'R': case 'S': case 'T': case 'U':
347 /* These don't say anything we care about. */
351 /* We don't need to allocate this SCRATCH. */
355 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
360 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER (c)];
364 if (class == NO_REGS)
367 #else /* REGISTER_CONSTRAINTS */
369 class = GENERAL_REGS;
375 qty_first_reg[qty] = -1;
376 qty_scratch_rtx[qty] = scratch;
377 qty_size[qty] = GET_MODE_SIZE (GET_MODE (scratch));
378 qty_mode[qty] = GET_MODE (scratch);
379 qty_birth[qty] = 2 * insn_number - 1;
380 qty_death[qty] = 2 * insn_number + 1;
381 qty_n_calls_crossed[qty] = 0;
382 qty_min_class[qty] = class;
383 qty_alternate_class[qty] = NO_REGS;
385 qty_changes_size[qty] = 0;
388 /* Main entry point of this file. */
396 /* Leaf functions and non-leaf functions have different needs.
397 If defined, let the machine say what kind of ordering we
399 #ifdef ORDER_REGS_FOR_LOCAL_ALLOC
400 ORDER_REGS_FOR_LOCAL_ALLOC;
403 /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected
405 update_equiv_regs ();
407 /* This sets the maximum number of quantities we can have. Quantity
408 numbers start at zero and we can have one for each pseudo plus the
409 number of SCRATCHes in the largest block, in the worst case. */
410 max_qty = (max_regno - FIRST_PSEUDO_REGISTER) + max_scratch;
412 /* Allocate vectors of temporary data.
413 See the declarations of these variables, above,
414 for what they mean. */
416 /* There can be up to MAX_SCRATCH * N_BASIC_BLOCKS SCRATCHes to allocate.
417 Instead of allocating this much memory from now until the end of
418 reload, only allocate space for MAX_QTY SCRATCHes. If there are more
419 reload will allocate them. */
421 scratch_list_length = max_qty;
422 scratch_list = (rtx *) xmalloc (scratch_list_length * sizeof (rtx));
423 bzero ((char *) scratch_list, scratch_list_length * sizeof (rtx));
424 scratch_block = (int *) xmalloc (scratch_list_length * sizeof (int));
425 bzero ((char *) scratch_block, scratch_list_length * sizeof (int));
428 qty_phys_reg = (short *) alloca (max_qty * sizeof (short));
430 = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET));
431 qty_phys_num_copy_sugg = (short *) alloca (max_qty * sizeof (short));
432 qty_phys_sugg = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET));
433 qty_phys_num_sugg = (short *) alloca (max_qty * sizeof (short));
434 qty_birth = (int *) alloca (max_qty * sizeof (int));
435 qty_death = (int *) alloca (max_qty * sizeof (int));
436 qty_scratch_rtx = (rtx *) alloca (max_qty * sizeof (rtx));
437 qty_first_reg = (int *) alloca (max_qty * sizeof (int));
438 qty_size = (int *) alloca (max_qty * sizeof (int));
440 = (enum machine_mode *) alloca (max_qty * sizeof (enum machine_mode));
441 qty_n_calls_crossed = (int *) alloca (max_qty * sizeof (int));
443 = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class));
445 = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class));
446 qty_n_refs = (int *) alloca (max_qty * sizeof (int));
447 qty_changes_size = (char *) alloca (max_qty * sizeof (char));
449 reg_qty = (int *) alloca (max_regno * sizeof (int));
450 reg_offset = (char *) alloca (max_regno * sizeof (char));
451 reg_next_in_qty = (int *) alloca (max_regno * sizeof (int));
453 /* Allocate the reg_renumber array */
454 allocate_reg_info (max_regno, FALSE, TRUE);
456 /* Determine which pseudo-registers can be allocated by local-alloc.
457 In general, these are the registers used only in a single block and
458 which only die once. However, if a register's preferred class has only
459 a few entries, don't allocate this register here unless it is preferred
460 or nothing since retry_global_alloc won't be able to move it to
461 GENERAL_REGS if a reload register of this class is needed.
463 We need not be concerned with which block actually uses the register
464 since we will never see it outside that block. */
466 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
468 if (REG_BASIC_BLOCK (i) >= 0 && REG_N_DEATHS (i) == 1
469 && (reg_alternate_class (i) == NO_REGS
470 || ! CLASS_LIKELY_SPILLED_P (reg_preferred_class (i))))
476 /* Force loop below to initialize entire quantity array. */
479 /* Allocate each block's local registers, block by block. */
481 for (b = 0; b < n_basic_blocks; b++)
483 /* NEXT_QTY indicates which elements of the `qty_...'
484 vectors might need to be initialized because they were used
485 for the previous block; it is set to the entire array before
486 block 0. Initialize those, with explicit loop if there are few,
487 else with bzero and bcopy. Do not initialize vectors that are
488 explicit set by `alloc_qty'. */
492 for (i = 0; i < next_qty; i++)
494 qty_scratch_rtx[i] = 0;
495 CLEAR_HARD_REG_SET (qty_phys_copy_sugg[i]);
496 qty_phys_num_copy_sugg[i] = 0;
497 CLEAR_HARD_REG_SET (qty_phys_sugg[i]);
498 qty_phys_num_sugg[i] = 0;
503 #define CLEAR(vector) \
504 bzero ((char *) (vector), (sizeof (*(vector))) * next_qty);
506 CLEAR (qty_scratch_rtx);
507 CLEAR (qty_phys_copy_sugg);
508 CLEAR (qty_phys_num_copy_sugg);
509 CLEAR (qty_phys_sugg);
510 CLEAR (qty_phys_num_sugg);
522 /* Depth of loops we are in while in update_equiv_regs. */
523 static int loop_depth;
525 /* Used for communication between the following two functions: contains
526 a MEM that we wish to ensure remains unchanged. */
527 static rtx equiv_mem;
529 /* Set nonzero if EQUIV_MEM is modified. */
530 static int equiv_mem_modified;
532 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
533 Called via note_stores. */
536 validate_equiv_mem_from_store (dest, set)
540 if ((GET_CODE (dest) == REG
541 && reg_overlap_mentioned_p (dest, equiv_mem))
542 || (GET_CODE (dest) == MEM
543 && true_dependence (dest, VOIDmode, equiv_mem, rtx_varies_p)))
544 equiv_mem_modified = 1;
547 /* Verify that no store between START and the death of REG invalidates
548 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
549 by storing into an overlapping memory location, or with a non-const
552 Return 1 if MEMREF remains valid. */
555 validate_equiv_mem (start, reg, memref)
564 equiv_mem_modified = 0;
566 /* If the memory reference has side effects or is volatile, it isn't a
567 valid equivalence. */
568 if (side_effects_p (memref))
571 for (insn = start; insn && ! equiv_mem_modified; insn = NEXT_INSN (insn))
573 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
576 if (find_reg_note (insn, REG_DEAD, reg))
579 if (GET_CODE (insn) == CALL_INSN && ! RTX_UNCHANGING_P (memref)
580 && ! CONST_CALL_P (insn))
583 note_stores (PATTERN (insn), validate_equiv_mem_from_store);
585 /* If a register mentioned in MEMREF is modified via an
586 auto-increment, we lose the equivalence. Do the same if one
587 dies; although we could extend the life, it doesn't seem worth
590 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
591 if ((REG_NOTE_KIND (note) == REG_INC
592 || REG_NOTE_KIND (note) == REG_DEAD)
593 && GET_CODE (XEXP (note, 0)) == REG
594 && reg_overlap_mentioned_p (XEXP (note, 0), memref))
601 /* TRUE if X uses any registers for which reg_equiv_replace is true. */
604 contains_replace_regs (x, reg_equiv_replace)
606 char *reg_equiv_replace;
610 enum rtx_code code = GET_CODE (x);
626 return reg_equiv_replace[REGNO (x)];
632 fmt = GET_RTX_FORMAT (code);
633 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
637 if (contains_replace_regs (XEXP (x, i), reg_equiv_replace))
641 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
642 if (contains_replace_regs (XVECEXP (x, i, j), reg_equiv_replace))
650 /* TRUE if X references a memory location that would be affected by a store
654 memref_referenced_p (memref, x)
660 enum rtx_code code = GET_CODE (x);
676 return (reg_equiv_replacement[REGNO (x)]
677 && memref_referenced_p (memref,
678 reg_equiv_replacement[REGNO (x)]));
681 if (true_dependence (memref, VOIDmode, x, rtx_varies_p))
686 /* If we are setting a MEM, it doesn't count (its address does), but any
687 other SET_DEST that has a MEM in it is referencing the MEM. */
688 if (GET_CODE (SET_DEST (x)) == MEM)
690 if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0)))
693 else if (memref_referenced_p (memref, SET_DEST (x)))
696 return memref_referenced_p (memref, SET_SRC (x));
702 fmt = GET_RTX_FORMAT (code);
703 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
707 if (memref_referenced_p (memref, XEXP (x, i)))
711 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
712 if (memref_referenced_p (memref, XVECEXP (x, i, j)))
720 /* TRUE if some insn in the range (START, END] references a memory location
721 that would be affected by a store to MEMREF. */
724 memref_used_between_p (memref, start, end)
731 for (insn = NEXT_INSN (start); insn != NEXT_INSN (end);
732 insn = NEXT_INSN (insn))
733 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
734 && memref_referenced_p (memref, PATTERN (insn)))
740 /* Find registers that are equivalent to a single value throughout the
741 compilation (either because they can be referenced in memory or are set once
742 from a single constant). Lower their priority for a register.
744 If such a register is only referenced once, try substituting its value
745 into the using insn. If it succeeds, we can eliminate the register
751 rtx *reg_equiv_init_insn = (rtx *) alloca (max_regno * sizeof (rtx *));
752 /* Set when an attempt should be made to replace a register with the
753 associated reg_equiv_replacement entry at the end of this function. */
754 char *reg_equiv_replace
755 = (char *) alloca (max_regno * sizeof *reg_equiv_replace);
759 reg_equiv_replacement = (rtx *) alloca (max_regno * sizeof (rtx *));
761 bzero ((char *) reg_equiv_init_insn, max_regno * sizeof (rtx *));
762 bzero ((char *) reg_equiv_replacement, max_regno * sizeof (rtx *));
763 bzero ((char *) reg_equiv_replace, max_regno * sizeof *reg_equiv_replace);
765 init_alias_analysis ();
769 /* Scan the insns and find which registers have equivalences. Do this
770 in a separate scan of the insns because (due to -fcse-follow-jumps)
771 a register can be set below its use. */
772 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
775 rtx set = single_set (insn);
779 if (GET_CODE (insn) == NOTE)
781 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
783 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
787 /* If this insn contains more (or less) than a single SET, ignore it. */
791 dest = SET_DEST (set);
794 /* If this sets a MEM to the contents of a REG that is only used
795 in a single basic block, see if the register is always equivalent
796 to that memory location and if moving the store from INSN to the
797 insn that set REG is safe. If so, put a REG_EQUIV note on the
800 Don't add a REG_EQUIV note if the insn already has one. The existing
801 REG_EQUIV is likely more useful than the one we are adding.
803 If one of the regs in the address is marked as reg_equiv_replace,
804 then we can't add this REG_EQUIV note. The reg_equiv_replace
805 optimization may move the set of this register immediately before
806 insn, which puts it after reg_equiv_init_insn[regno], and hence
807 the mention in the REG_EQUIV note would be to an uninitialized
810 if (GET_CODE (dest) == MEM && GET_CODE (SET_SRC (set)) == REG
811 && (regno = REGNO (SET_SRC (set))) >= FIRST_PSEUDO_REGISTER
812 && REG_BASIC_BLOCK (regno) >= 0
813 && reg_equiv_init_insn[regno] != 0
814 && ! find_reg_note (insn, REG_EQUIV, NULL_RTX)
815 && ! contains_replace_regs (XEXP (dest, 0), reg_equiv_replace)
816 && validate_equiv_mem (reg_equiv_init_insn[regno], SET_SRC (set),
818 && ! memref_used_between_p (SET_DEST (set),
819 reg_equiv_init_insn[regno], insn))
820 REG_NOTES (reg_equiv_init_insn[regno])
821 = gen_rtx_EXPR_LIST (REG_EQUIV, dest,
822 REG_NOTES (reg_equiv_init_insn[regno]));
824 /* We only handle the case of a pseudo register being set
825 once and only if neither the source nor the destination are
826 in a register class that's likely to be spilled. */
827 if (GET_CODE (dest) != REG
828 || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER
829 || REG_N_SETS (regno) != 1
830 || CLASS_LIKELY_SPILLED_P (reg_preferred_class (REGNO (dest)))
831 || (GET_CODE (src) == REG
832 && REGNO (src) >= FIRST_PSEUDO_REGISTER
833 && CLASS_LIKELY_SPILLED_P (reg_preferred_class (REGNO (src)))))
836 note = find_reg_note (insn, REG_EQUAL, NULL_RTX);
838 #ifdef DONT_RECORD_EQUIVALENCE
839 /* Allow the target to reject promotions of some REG_EQUAL notes to
842 In some cases this can improve register allocation if the existence
843 of the REG_EQUIV note is likely to increase the lifetime of a register
844 that is likely to be spilled.
846 It may also be necessary if the target can't handle certain constant
847 expressions appearing randomly in insns, but for whatever reason
848 those expressions must be considered legitimate constant expressions
849 to prevent them from being forced into memory. */
850 if (note && DONT_RECORD_EQUIVALENCE (note))
854 /* Record this insn as initializing this register. */
855 reg_equiv_init_insn[regno] = insn;
857 /* If this register is known to be equal to a constant, record that
858 it is always equivalent to the constant. */
859 if (note && CONSTANT_P (XEXP (note, 0)))
860 PUT_MODE (note, (enum machine_mode) REG_EQUIV);
862 /* If this insn introduces a "constant" register, decrease the priority
863 of that register. Record this insn if the register is only used once
864 more and the equivalence value is the same as our source.
866 The latter condition is checked for two reasons: First, it is an
867 indication that it may be more efficient to actually emit the insn
868 as written (if no registers are available, reload will substitute
869 the equivalence). Secondly, it avoids problems with any registers
870 dying in this insn whose death notes would be missed.
872 If we don't have a REG_EQUIV note, see if this insn is loading
873 a register used only in one basic block from a MEM. If so, and the
874 MEM remains unchanged for the life of the register, add a REG_EQUIV
877 note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
879 if (note == 0 && REG_BASIC_BLOCK (regno) >= 0
880 && GET_CODE (SET_SRC (set)) == MEM
881 && validate_equiv_mem (insn, dest, SET_SRC (set)))
882 REG_NOTES (insn) = note = gen_rtx_EXPR_LIST (REG_EQUIV, SET_SRC (set),
887 int regno = REGNO (dest);
889 reg_equiv_replacement[regno] = XEXP (note, 0);
891 /* Don't mess with things live during setjmp. */
892 if (REG_LIVE_LENGTH (regno) >= 0)
894 /* Note that the statement below does not affect the priority
896 REG_LIVE_LENGTH (regno) *= 2;
899 /* If the register is referenced exactly twice, meaning it is
900 set once and used once, indicate that the reference may be
901 replaced by the equivalence we computed above. If the
902 register is only used in one basic block, this can't succeed
903 or combine would have done it.
905 It would be nice to use "loop_depth * 2" in the compare
906 below. Unfortunately, LOOP_DEPTH need not be constant within
907 a basic block so this would be too complicated.
909 This case normally occurs when a parameter is read from
910 memory and then used exactly once, not in a loop. */
912 if (REG_N_REFS (regno) == 2
913 && REG_BASIC_BLOCK (regno) < 0
914 && rtx_equal_p (XEXP (note, 0), SET_SRC (set)))
915 reg_equiv_replace[regno] = 1;
920 /* Now scan all regs killed in an insn to see if any of them are
921 registers only used that once. If so, see if we can replace the
922 reference with the equivalent from. If we can, delete the
923 initializing reference and this register will go away. If we
924 can't replace the reference, and the instruction is not in a
925 loop, then move the register initialization just before the use,
926 so that they are in the same basic block. */
929 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
933 /* Keep track of which basic block we are in. */
934 if (block + 1 < n_basic_blocks
935 && basic_block_head[block + 1] == insn)
938 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
940 if (GET_CODE (insn) == NOTE)
942 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
944 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
955 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
957 if (REG_NOTE_KIND (link) == REG_DEAD
958 /* Make sure this insn still refers to the register. */
959 && reg_mentioned_p (XEXP (link, 0), PATTERN (insn)))
961 int regno = REGNO (XEXP (link, 0));
964 if (! reg_equiv_replace[regno])
967 equiv_insn = reg_equiv_init_insn[regno];
969 if (validate_replace_rtx (regno_reg_rtx[regno],
970 reg_equiv_replacement[regno], insn))
972 remove_death (regno, insn);
973 REG_N_REFS (regno) = 0;
974 PUT_CODE (equiv_insn, NOTE);
975 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
976 NOTE_SOURCE_FILE (equiv_insn) = 0;
978 /* If we aren't in a loop, and there are no calls in
979 INSN or in the initialization of the register, then
980 move the initialization of the register to just
981 before INSN. Update the flow information. */
983 && GET_CODE (equiv_insn) == INSN
984 && GET_CODE (insn) == INSN
985 && REG_BASIC_BLOCK (regno) < 0)
989 emit_insn_before (copy_rtx (PATTERN (equiv_insn)), insn);
990 REG_NOTES (PREV_INSN (insn)) = REG_NOTES (equiv_insn);
992 PUT_CODE (equiv_insn, NOTE);
993 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
994 NOTE_SOURCE_FILE (equiv_insn) = 0;
995 REG_NOTES (equiv_insn) = 0;
998 REG_BASIC_BLOCK (regno) = 0;
1000 REG_BASIC_BLOCK (regno) = block;
1001 REG_N_CALLS_CROSSED (regno) = 0;
1002 REG_LIVE_LENGTH (regno) = 2;
1004 if (block >= 0 && insn == basic_block_head[block])
1005 basic_block_head[block] = PREV_INSN (insn);
1007 for (l = 0; l < n_basic_blocks; l++)
1008 CLEAR_REGNO_REG_SET (basic_block_live_at_start[l], regno);
1015 /* Allocate hard regs to the pseudo regs used only within block number B.
1016 Only the pseudos that die but once can be handled. */
1025 int insn_number = 0;
1027 int max_uid = get_max_uid ();
1029 int no_conflict_combined_regno = -1;
1030 /* Counter to prevent allocating more SCRATCHes than can be stored
1032 int scratches_allocated = scratch_index;
1034 /* Count the instructions in the basic block. */
1036 insn = basic_block_end[b];
1039 if (GET_CODE (insn) != NOTE)
1040 if (++insn_count > max_uid)
1042 if (insn == basic_block_head[b])
1044 insn = PREV_INSN (insn);
1047 /* +2 to leave room for a post_mark_life at the last insn and for
1048 the birth of a CLOBBER in the first insn. */
1049 regs_live_at = (HARD_REG_SET *) alloca ((2 * insn_count + 2)
1050 * sizeof (HARD_REG_SET));
1051 bzero ((char *) regs_live_at, (2 * insn_count + 2) * sizeof (HARD_REG_SET));
1053 /* Initialize table of hardware registers currently live. */
1055 REG_SET_TO_HARD_REG_SET (regs_live, basic_block_live_at_start[b]);
1057 /* This loop scans the instructions of the basic block
1058 and assigns quantities to registers.
1059 It computes which registers to tie. */
1061 insn = basic_block_head[b];
1064 register rtx body = PATTERN (insn);
1066 if (GET_CODE (insn) != NOTE)
1069 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1071 register rtx link, set;
1072 register int win = 0;
1073 register rtx r0, r1;
1074 int combined_regno = -1;
1076 int insn_code_number = recog_memoized (insn);
1078 this_insn_number = insn_number;
1081 if (insn_code_number >= 0)
1082 insn_extract (insn);
1083 which_alternative = -1;
1085 /* Is this insn suitable for tying two registers?
1086 If so, try doing that.
1087 Suitable insns are those with at least two operands and where
1088 operand 0 is an output that is a register that is not
1091 We can tie operand 0 with some operand that dies in this insn.
1092 First look for operands that are required to be in the same
1093 register as operand 0. If we find such, only try tying that
1094 operand or one that can be put into that operand if the
1095 operation is commutative. If we don't find an operand
1096 that is required to be in the same register as operand 0,
1097 we can tie with any operand.
1099 Subregs in place of regs are also ok.
1101 If tying is done, WIN is set nonzero. */
1103 if (insn_code_number >= 0
1104 #ifdef REGISTER_CONSTRAINTS
1105 && insn_n_operands[insn_code_number] > 1
1106 && insn_operand_constraint[insn_code_number][0][0] == '='
1107 && insn_operand_constraint[insn_code_number][0][1] != '&'
1109 && GET_CODE (PATTERN (insn)) == SET
1110 && rtx_equal_p (SET_DEST (PATTERN (insn)), recog_operand[0])
1114 #ifdef REGISTER_CONSTRAINTS
1115 /* If non-negative, is an operand that must match operand 0. */
1116 int must_match_0 = -1;
1117 /* Counts number of alternatives that require a match with
1119 int n_matching_alts = 0;
1121 for (i = 1; i < insn_n_operands[insn_code_number]; i++)
1123 char *p = insn_operand_constraint[insn_code_number][i];
1124 int this_match = (requires_inout (p));
1126 n_matching_alts += this_match;
1127 if (this_match == insn_n_alternatives[insn_code_number])
1132 r0 = recog_operand[0];
1133 for (i = 1; i < insn_n_operands[insn_code_number]; i++)
1135 #ifdef REGISTER_CONSTRAINTS
1136 /* Skip this operand if we found an operand that
1137 must match operand 0 and this operand isn't it
1138 and can't be made to be it by commutativity. */
1140 if (must_match_0 >= 0 && i != must_match_0
1141 && ! (i == must_match_0 + 1
1142 && insn_operand_constraint[insn_code_number][i-1][0] == '%')
1143 && ! (i == must_match_0 - 1
1144 && insn_operand_constraint[insn_code_number][i][0] == '%'))
1147 /* Likewise if each alternative has some operand that
1148 must match operand zero. In that case, skip any
1149 operand that doesn't list operand 0 since we know that
1150 the operand always conflicts with operand 0. We
1151 ignore commutatity in this case to keep things simple. */
1152 if (n_matching_alts == insn_n_alternatives[insn_code_number]
1153 && (0 == requires_inout
1154 (insn_operand_constraint[insn_code_number][i])))
1158 r1 = recog_operand[i];
1160 /* If the operand is an address, find a register in it.
1161 There may be more than one register, but we only try one
1164 #ifdef REGISTER_CONSTRAINTS
1165 insn_operand_constraint[insn_code_number][i][0] == 'p'
1167 insn_operand_address_p[insn_code_number][i]
1170 while (GET_CODE (r1) == PLUS || GET_CODE (r1) == MULT)
1173 if (GET_CODE (r0) == REG || GET_CODE (r0) == SUBREG)
1175 /* We have two priorities for hard register preferences.
1176 If we have a move insn or an insn whose first input
1177 can only be in the same register as the output, give
1178 priority to an equivalence found from that insn. */
1180 = ((SET_DEST (body) == r0 && SET_SRC (body) == r1)
1181 #ifdef REGISTER_CONSTRAINTS
1182 || (r1 == recog_operand[i] && must_match_0 >= 0)
1186 if (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1187 win = combine_regs (r1, r0, may_save_copy,
1188 insn_number, insn, 0);
1195 /* Recognize an insn sequence with an ultimate result
1196 which can safely overlap one of the inputs.
1197 The sequence begins with a CLOBBER of its result,
1198 and ends with an insn that copies the result to itself
1199 and has a REG_EQUAL note for an equivalent formula.
1200 That note indicates what the inputs are.
1201 The result and the input can overlap if each insn in
1202 the sequence either doesn't mention the input
1203 or has a REG_NO_CONFLICT note to inhibit the conflict.
1205 We do the combining test at the CLOBBER so that the
1206 destination register won't have had a quantity number
1207 assigned, since that would prevent combining. */
1209 if (GET_CODE (PATTERN (insn)) == CLOBBER
1210 && (r0 = XEXP (PATTERN (insn), 0),
1211 GET_CODE (r0) == REG)
1212 && (link = find_reg_note (insn, REG_LIBCALL, NULL_RTX)) != 0
1213 && XEXP (link, 0) != 0
1214 && GET_CODE (XEXP (link, 0)) == INSN
1215 && (set = single_set (XEXP (link, 0))) != 0
1216 && SET_DEST (set) == r0 && SET_SRC (set) == r0
1217 && (note = find_reg_note (XEXP (link, 0), REG_EQUAL,
1220 if (r1 = XEXP (note, 0), GET_CODE (r1) == REG
1221 /* Check that we have such a sequence. */
1222 && no_conflict_p (insn, r0, r1))
1223 win = combine_regs (r1, r0, 1, insn_number, insn, 1);
1224 else if (GET_RTX_FORMAT (GET_CODE (XEXP (note, 0)))[0] == 'e'
1225 && (r1 = XEXP (XEXP (note, 0), 0),
1226 GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1227 && no_conflict_p (insn, r0, r1))
1228 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1230 /* Here we care if the operation to be computed is
1232 else if ((GET_CODE (XEXP (note, 0)) == EQ
1233 || GET_CODE (XEXP (note, 0)) == NE
1234 || GET_RTX_CLASS (GET_CODE (XEXP (note, 0))) == 'c')
1235 && (r1 = XEXP (XEXP (note, 0), 1),
1236 (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG))
1237 && no_conflict_p (insn, r0, r1))
1238 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1240 /* If we did combine something, show the register number
1241 in question so that we know to ignore its death. */
1243 no_conflict_combined_regno = REGNO (r1);
1246 /* If registers were just tied, set COMBINED_REGNO
1247 to the number of the register used in this insn
1248 that was tied to the register set in this insn.
1249 This register's qty should not be "killed". */
1253 while (GET_CODE (r1) == SUBREG)
1254 r1 = SUBREG_REG (r1);
1255 combined_regno = REGNO (r1);
1258 /* Mark the death of everything that dies in this instruction,
1259 except for anything that was just combined. */
1261 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1262 if (REG_NOTE_KIND (link) == REG_DEAD
1263 && GET_CODE (XEXP (link, 0)) == REG
1264 && combined_regno != REGNO (XEXP (link, 0))
1265 && (no_conflict_combined_regno != REGNO (XEXP (link, 0))
1266 || ! find_reg_note (insn, REG_NO_CONFLICT, XEXP (link, 0))))
1267 wipe_dead_reg (XEXP (link, 0), 0);
1269 /* Allocate qty numbers for all registers local to this block
1270 that are born (set) in this instruction.
1271 A pseudo that already has a qty is not changed. */
1273 note_stores (PATTERN (insn), reg_is_set);
1275 /* If anything is set in this insn and then unused, mark it as dying
1276 after this insn, so it will conflict with our outputs. This
1277 can't match with something that combined, and it doesn't matter
1278 if it did. Do this after the calls to reg_is_set since these
1279 die after, not during, the current insn. */
1281 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1282 if (REG_NOTE_KIND (link) == REG_UNUSED
1283 && GET_CODE (XEXP (link, 0)) == REG)
1284 wipe_dead_reg (XEXP (link, 0), 1);
1286 /* Allocate quantities for any SCRATCH operands of this insn. */
1288 if (insn_code_number >= 0)
1289 for (i = 0; i < insn_n_operands[insn_code_number]; i++)
1290 if (GET_CODE (recog_operand[i]) == SCRATCH
1291 && scratches_allocated++ < scratch_list_length)
1292 alloc_qty_for_scratch (recog_operand[i], i, insn,
1293 insn_code_number, insn_number);
1295 /* If this is an insn that has a REG_RETVAL note pointing at a
1296 CLOBBER insn, we have reached the end of a REG_NO_CONFLICT
1297 block, so clear any register number that combined within it. */
1298 if ((note = find_reg_note (insn, REG_RETVAL, NULL_RTX)) != 0
1299 && GET_CODE (XEXP (note, 0)) == INSN
1300 && GET_CODE (PATTERN (XEXP (note, 0))) == CLOBBER)
1301 no_conflict_combined_regno = -1;
1304 /* Set the registers live after INSN_NUMBER. Note that we never
1305 record the registers live before the block's first insn, since no
1306 pseudos we care about are live before that insn. */
1308 IOR_HARD_REG_SET (regs_live_at[2 * insn_number], regs_live);
1309 IOR_HARD_REG_SET (regs_live_at[2 * insn_number + 1], regs_live);
1311 if (insn == basic_block_end[b])
1314 insn = NEXT_INSN (insn);
1317 /* Now every register that is local to this basic block
1318 should have been given a quantity, or else -1 meaning ignore it.
1319 Every quantity should have a known birth and death.
1321 Order the qtys so we assign them registers in order of the
1322 number of suggested registers they need so we allocate those with
1323 the most restrictive needs first. */
1325 qty_order = (int *) alloca (next_qty * sizeof (int));
1326 for (i = 0; i < next_qty; i++)
1329 #define EXCHANGE(I1, I2) \
1330 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1335 /* Make qty_order[2] be the one to allocate last. */
1336 if (qty_sugg_compare (0, 1) > 0)
1338 if (qty_sugg_compare (1, 2) > 0)
1341 /* ... Fall through ... */
1343 /* Put the best one to allocate in qty_order[0]. */
1344 if (qty_sugg_compare (0, 1) > 0)
1347 /* ... Fall through ... */
1351 /* Nothing to do here. */
1355 qsort (qty_order, next_qty, sizeof (int), qty_sugg_compare_1);
1358 /* Try to put each quantity in a suggested physical register, if it has one.
1359 This may cause registers to be allocated that otherwise wouldn't be, but
1360 this seems acceptable in local allocation (unlike global allocation). */
1361 for (i = 0; i < next_qty; i++)
1364 if (qty_phys_num_sugg[q] != 0 || qty_phys_num_copy_sugg[q] != 0)
1365 qty_phys_reg[q] = find_free_reg (qty_min_class[q], qty_mode[q], q,
1366 0, 1, qty_birth[q], qty_death[q]);
1368 qty_phys_reg[q] = -1;
1371 /* Order the qtys so we assign them registers in order of
1372 decreasing length of life. Normally call qsort, but if we
1373 have only a very small number of quantities, sort them ourselves. */
1375 for (i = 0; i < next_qty; i++)
1378 #define EXCHANGE(I1, I2) \
1379 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1384 /* Make qty_order[2] be the one to allocate last. */
1385 if (qty_compare (0, 1) > 0)
1387 if (qty_compare (1, 2) > 0)
1390 /* ... Fall through ... */
1392 /* Put the best one to allocate in qty_order[0]. */
1393 if (qty_compare (0, 1) > 0)
1396 /* ... Fall through ... */
1400 /* Nothing to do here. */
1404 qsort (qty_order, next_qty, sizeof (int), qty_compare_1);
1407 /* Now for each qty that is not a hardware register,
1408 look for a hardware register to put it in.
1409 First try the register class that is cheapest for this qty,
1410 if there is more than one class. */
1412 for (i = 0; i < next_qty; i++)
1415 if (qty_phys_reg[q] < 0)
1417 if (N_REG_CLASSES > 1)
1419 qty_phys_reg[q] = find_free_reg (qty_min_class[q],
1420 qty_mode[q], q, 0, 0,
1421 qty_birth[q], qty_death[q]);
1422 if (qty_phys_reg[q] >= 0)
1426 if (qty_alternate_class[q] != NO_REGS)
1427 qty_phys_reg[q] = find_free_reg (qty_alternate_class[q],
1428 qty_mode[q], q, 0, 0,
1429 qty_birth[q], qty_death[q]);
1433 /* Now propagate the register assignments
1434 to the pseudo regs belonging to the qtys. */
1436 for (q = 0; q < next_qty; q++)
1437 if (qty_phys_reg[q] >= 0)
1439 for (i = qty_first_reg[q]; i >= 0; i = reg_next_in_qty[i])
1440 reg_renumber[i] = qty_phys_reg[q] + reg_offset[i];
1441 if (qty_scratch_rtx[q])
1443 if (GET_CODE (qty_scratch_rtx[q]) == REG)
1445 qty_scratch_rtx[q] = gen_rtx_REG (GET_MODE (qty_scratch_rtx[q]),
1447 scratch_block[scratch_index] = b;
1448 scratch_list[scratch_index++] = qty_scratch_rtx[q];
1454 /* Compare two quantities' priority for getting real registers.
1455 We give shorter-lived quantities higher priority.
1456 Quantities with more references are also preferred, as are quantities that
1457 require multiple registers. This is the identical prioritization as
1458 done by global-alloc.
1460 We used to give preference to registers with *longer* lives, but using
1461 the same algorithm in both local- and global-alloc can speed up execution
1462 of some programs by as much as a factor of three! */
1464 /* Note that the quotient will never be bigger than
1465 the value of floor_log2 times the maximum number of
1466 times a register can occur in one insn (surely less than 100).
1467 Multiplying this by 10000 can't overflow.
1468 QTY_CMP_PRI is also used by qty_sugg_compare. */
1470 #define QTY_CMP_PRI(q) \
1471 ((int) (((double) (floor_log2 (qty_n_refs[q]) * qty_n_refs[q] * qty_size[q]) \
1472 / (qty_death[q] - qty_birth[q])) * 10000))
1475 qty_compare (q1, q2)
1478 return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1482 qty_compare_1 (q1p, q2p)
1483 const GENERIC_PTR q1p;
1484 const GENERIC_PTR q2p;
1486 register int q1 = *(int *)q1p, q2 = *(int *)q2p;
1487 register int tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1492 /* If qtys are equally good, sort by qty number,
1493 so that the results of qsort leave nothing to chance. */
1497 /* Compare two quantities' priority for getting real registers. This version
1498 is called for quantities that have suggested hard registers. First priority
1499 goes to quantities that have copy preferences, then to those that have
1500 normal preferences. Within those groups, quantities with the lower
1501 number of preferences have the highest priority. Of those, we use the same
1502 algorithm as above. */
1504 #define QTY_CMP_SUGG(q) \
1505 (qty_phys_num_copy_sugg[q] \
1506 ? qty_phys_num_copy_sugg[q] \
1507 : qty_phys_num_sugg[q] * FIRST_PSEUDO_REGISTER)
1510 qty_sugg_compare (q1, q2)
1513 register int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2);
1518 return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1522 qty_sugg_compare_1 (q1p, q2p)
1523 const GENERIC_PTR q1p;
1524 const GENERIC_PTR q2p;
1526 register int q1 = *(int *)q1p, q2 = *(int *)q2p;
1527 register int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2);
1532 tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1536 /* If qtys are equally good, sort by qty number,
1537 so that the results of qsort leave nothing to chance. */
1544 /* Attempt to combine the two registers (rtx's) USEDREG and SETREG.
1545 Returns 1 if have done so, or 0 if cannot.
1547 Combining registers means marking them as having the same quantity
1548 and adjusting the offsets within the quantity if either of
1551 We don't actually combine a hard reg with a pseudo; instead
1552 we just record the hard reg as the suggestion for the pseudo's quantity.
1553 If we really combined them, we could lose if the pseudo lives
1554 across an insn that clobbers the hard reg (eg, movstr).
1556 ALREADY_DEAD is non-zero if USEDREG is known to be dead even though
1557 there is no REG_DEAD note on INSN. This occurs during the processing
1558 of REG_NO_CONFLICT blocks.
1560 MAY_SAVE_COPYCOPY is non-zero if this insn is simply copying USEDREG to
1561 SETREG or if the input and output must share a register.
1562 In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG.
1564 There are elaborate checks for the validity of combining. */
1568 combine_regs (usedreg, setreg, may_save_copy, insn_number, insn, already_dead)
1569 rtx usedreg, setreg;
1575 register int ureg, sreg;
1576 register int offset = 0;
1580 /* Determine the numbers and sizes of registers being used. If a subreg
1581 is present that does not change the entire register, don't consider
1582 this a copy insn. */
1584 while (GET_CODE (usedreg) == SUBREG)
1586 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (usedreg))) > UNITS_PER_WORD)
1588 offset += SUBREG_WORD (usedreg);
1589 usedreg = SUBREG_REG (usedreg);
1591 if (GET_CODE (usedreg) != REG)
1593 ureg = REGNO (usedreg);
1594 usize = REG_SIZE (usedreg);
1596 while (GET_CODE (setreg) == SUBREG)
1598 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (setreg))) > UNITS_PER_WORD)
1600 offset -= SUBREG_WORD (setreg);
1601 setreg = SUBREG_REG (setreg);
1603 if (GET_CODE (setreg) != REG)
1605 sreg = REGNO (setreg);
1606 ssize = REG_SIZE (setreg);
1608 /* If UREG is a pseudo-register that hasn't already been assigned a
1609 quantity number, it means that it is not local to this block or dies
1610 more than once. In either event, we can't do anything with it. */
1611 if ((ureg >= FIRST_PSEUDO_REGISTER && reg_qty[ureg] < 0)
1612 /* Do not combine registers unless one fits within the other. */
1613 || (offset > 0 && usize + offset > ssize)
1614 || (offset < 0 && usize + offset < ssize)
1615 /* Do not combine with a smaller already-assigned object
1616 if that smaller object is already combined with something bigger. */
1617 || (ssize > usize && ureg >= FIRST_PSEUDO_REGISTER
1618 && usize < qty_size[reg_qty[ureg]])
1619 /* Can't combine if SREG is not a register we can allocate. */
1620 || (sreg >= FIRST_PSEUDO_REGISTER && reg_qty[sreg] == -1)
1621 /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note.
1622 These have already been taken care of. This probably wouldn't
1623 combine anyway, but don't take any chances. */
1624 || (ureg >= FIRST_PSEUDO_REGISTER
1625 && find_reg_note (insn, REG_NO_CONFLICT, usedreg))
1626 /* Don't tie something to itself. In most cases it would make no
1627 difference, but it would screw up if the reg being tied to itself
1628 also dies in this insn. */
1630 /* Don't try to connect two different hardware registers. */
1631 || (ureg < FIRST_PSEUDO_REGISTER && sreg < FIRST_PSEUDO_REGISTER)
1632 /* Don't connect two different machine modes if they have different
1633 implications as to which registers may be used. */
1634 || !MODES_TIEABLE_P (GET_MODE (usedreg), GET_MODE (setreg)))
1637 /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in
1638 qty_phys_sugg for the pseudo instead of tying them.
1640 Return "failure" so that the lifespan of UREG is terminated here;
1641 that way the two lifespans will be disjoint and nothing will prevent
1642 the pseudo reg from being given this hard reg. */
1644 if (ureg < FIRST_PSEUDO_REGISTER)
1646 /* Allocate a quantity number so we have a place to put our
1648 if (reg_qty[sreg] == -2)
1649 reg_is_born (setreg, 2 * insn_number);
1651 if (reg_qty[sreg] >= 0)
1654 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg))
1656 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg);
1657 qty_phys_num_copy_sugg[reg_qty[sreg]]++;
1659 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg))
1661 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg);
1662 qty_phys_num_sugg[reg_qty[sreg]]++;
1668 /* Similarly for SREG a hard register and UREG a pseudo register. */
1670 if (sreg < FIRST_PSEUDO_REGISTER)
1673 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg))
1675 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg);
1676 qty_phys_num_copy_sugg[reg_qty[ureg]]++;
1678 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg))
1680 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg);
1681 qty_phys_num_sugg[reg_qty[ureg]]++;
1686 /* At this point we know that SREG and UREG are both pseudos.
1687 Do nothing if SREG already has a quantity or is a register that we
1689 if (reg_qty[sreg] >= -1
1690 /* If we are not going to let any regs live across calls,
1691 don't tie a call-crossing reg to a non-call-crossing reg. */
1692 || (current_function_has_nonlocal_label
1693 && ((REG_N_CALLS_CROSSED (ureg) > 0)
1694 != (REG_N_CALLS_CROSSED (sreg) > 0))))
1697 /* We don't already know about SREG, so tie it to UREG
1698 if this is the last use of UREG, provided the classes they want
1701 if ((already_dead || find_regno_note (insn, REG_DEAD, ureg))
1702 && reg_meets_class_p (sreg, qty_min_class[reg_qty[ureg]]))
1704 /* Add SREG to UREG's quantity. */
1705 sqty = reg_qty[ureg];
1706 reg_qty[sreg] = sqty;
1707 reg_offset[sreg] = reg_offset[ureg] + offset;
1708 reg_next_in_qty[sreg] = qty_first_reg[sqty];
1709 qty_first_reg[sqty] = sreg;
1711 /* If SREG's reg class is smaller, set qty_min_class[SQTY]. */
1712 update_qty_class (sqty, sreg);
1714 /* Update info about quantity SQTY. */
1715 qty_n_calls_crossed[sqty] += REG_N_CALLS_CROSSED (sreg);
1716 qty_n_refs[sqty] += REG_N_REFS (sreg);
1721 for (i = qty_first_reg[sqty]; i >= 0; i = reg_next_in_qty[i])
1722 reg_offset[i] -= offset;
1724 qty_size[sqty] = ssize;
1725 qty_mode[sqty] = GET_MODE (setreg);
1734 /* Return 1 if the preferred class of REG allows it to be tied
1735 to a quantity or register whose class is CLASS.
1736 True if REG's reg class either contains or is contained in CLASS. */
1739 reg_meets_class_p (reg, class)
1741 enum reg_class class;
1743 register enum reg_class rclass = reg_preferred_class (reg);
1744 return (reg_class_subset_p (rclass, class)
1745 || reg_class_subset_p (class, rclass));
1748 /* Update the class of QTY assuming that REG is being tied to it. */
1751 update_qty_class (qty, reg)
1755 enum reg_class rclass = reg_preferred_class (reg);
1756 if (reg_class_subset_p (rclass, qty_min_class[qty]))
1757 qty_min_class[qty] = rclass;
1759 rclass = reg_alternate_class (reg);
1760 if (reg_class_subset_p (rclass, qty_alternate_class[qty]))
1761 qty_alternate_class[qty] = rclass;
1763 if (REG_CHANGES_SIZE (reg))
1764 qty_changes_size[qty] = 1;
1767 /* Handle something which alters the value of an rtx REG.
1769 REG is whatever is set or clobbered. SETTER is the rtx that
1770 is modifying the register.
1772 If it is not really a register, we do nothing.
1773 The file-global variables `this_insn' and `this_insn_number'
1774 carry info from `block_alloc'. */
1777 reg_is_set (reg, setter)
1781 /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of
1782 a hard register. These may actually not exist any more. */
1784 if (GET_CODE (reg) != SUBREG
1785 && GET_CODE (reg) != REG)
1788 /* Mark this register as being born. If it is used in a CLOBBER, mark
1789 it as being born halfway between the previous insn and this insn so that
1790 it conflicts with our inputs but not the outputs of the previous insn. */
1792 reg_is_born (reg, 2 * this_insn_number - (GET_CODE (setter) == CLOBBER));
1795 /* Handle beginning of the life of register REG.
1796 BIRTH is the index at which this is happening. */
1799 reg_is_born (reg, birth)
1805 if (GET_CODE (reg) == SUBREG)
1806 regno = REGNO (SUBREG_REG (reg)) + SUBREG_WORD (reg);
1808 regno = REGNO (reg);
1810 if (regno < FIRST_PSEUDO_REGISTER)
1812 mark_life (regno, GET_MODE (reg), 1);
1814 /* If the register was to have been born earlier that the present
1815 insn, mark it as live where it is actually born. */
1816 if (birth < 2 * this_insn_number)
1817 post_mark_life (regno, GET_MODE (reg), 1, birth, 2 * this_insn_number);
1821 if (reg_qty[regno] == -2)
1822 alloc_qty (regno, GET_MODE (reg), PSEUDO_REGNO_SIZE (regno), birth);
1824 /* If this register has a quantity number, show that it isn't dead. */
1825 if (reg_qty[regno] >= 0)
1826 qty_death[reg_qty[regno]] = -1;
1830 /* Record the death of REG in the current insn. If OUTPUT_P is non-zero,
1831 REG is an output that is dying (i.e., it is never used), otherwise it
1832 is an input (the normal case).
1833 If OUTPUT_P is 1, then we extend the life past the end of this insn. */
1836 wipe_dead_reg (reg, output_p)
1840 register int regno = REGNO (reg);
1842 /* If this insn has multiple results,
1843 and the dead reg is used in one of the results,
1844 extend its life to after this insn,
1845 so it won't get allocated together with any other result of this insn. */
1846 if (GET_CODE (PATTERN (this_insn)) == PARALLEL
1847 && !single_set (this_insn))
1850 for (i = XVECLEN (PATTERN (this_insn), 0) - 1; i >= 0; i--)
1852 rtx set = XVECEXP (PATTERN (this_insn), 0, i);
1853 if (GET_CODE (set) == SET
1854 && GET_CODE (SET_DEST (set)) != REG
1855 && !rtx_equal_p (reg, SET_DEST (set))
1856 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
1861 /* If this register is used in an auto-increment address, then extend its
1862 life to after this insn, so that it won't get allocated together with
1863 the result of this insn. */
1864 if (! output_p && find_regno_note (this_insn, REG_INC, regno))
1867 if (regno < FIRST_PSEUDO_REGISTER)
1869 mark_life (regno, GET_MODE (reg), 0);
1871 /* If a hard register is dying as an output, mark it as in use at
1872 the beginning of this insn (the above statement would cause this
1875 post_mark_life (regno, GET_MODE (reg), 1,
1876 2 * this_insn_number, 2 * this_insn_number+ 1);
1879 else if (reg_qty[regno] >= 0)
1880 qty_death[reg_qty[regno]] = 2 * this_insn_number + output_p;
1883 /* Find a block of SIZE words of hard regs in reg_class CLASS
1884 that can hold something of machine-mode MODE
1885 (but actually we test only the first of the block for holding MODE)
1886 and still free between insn BORN_INDEX and insn DEAD_INDEX,
1887 and return the number of the first of them.
1888 Return -1 if such a block cannot be found.
1889 If QTY crosses calls, insist on a register preserved by calls,
1890 unless ACCEPT_CALL_CLOBBERED is nonzero.
1892 If JUST_TRY_SUGGESTED is non-zero, only try to see if the suggested
1893 register is available. If not, return -1. */
1896 find_free_reg (class, mode, qty, accept_call_clobbered, just_try_suggested,
1897 born_index, dead_index)
1898 enum reg_class class;
1899 enum machine_mode mode;
1901 int accept_call_clobbered;
1902 int just_try_suggested;
1903 int born_index, dead_index;
1905 register int i, ins;
1907 register /* Declare it register if it's a scalar. */
1909 HARD_REG_SET used, first_used;
1910 #ifdef ELIMINABLE_REGS
1911 static struct {int from, to; } eliminables[] = ELIMINABLE_REGS;
1914 /* Validate our parameters. */
1915 if (born_index < 0 || born_index > dead_index)
1918 /* Don't let a pseudo live in a reg across a function call
1919 if we might get a nonlocal goto. */
1920 if (current_function_has_nonlocal_label
1921 && qty_n_calls_crossed[qty] > 0)
1924 if (accept_call_clobbered)
1925 COPY_HARD_REG_SET (used, call_fixed_reg_set);
1926 else if (qty_n_calls_crossed[qty] == 0)
1927 COPY_HARD_REG_SET (used, fixed_reg_set);
1929 COPY_HARD_REG_SET (used, call_used_reg_set);
1931 if (accept_call_clobbered)
1932 IOR_HARD_REG_SET (used, losing_caller_save_reg_set);
1934 for (ins = born_index; ins < dead_index; ins++)
1935 IOR_HARD_REG_SET (used, regs_live_at[ins]);
1937 IOR_COMPL_HARD_REG_SET (used, reg_class_contents[(int) class]);
1939 /* Don't use the frame pointer reg in local-alloc even if
1940 we may omit the frame pointer, because if we do that and then we
1941 need a frame pointer, reload won't know how to move the pseudo
1942 to another hard reg. It can move only regs made by global-alloc.
1944 This is true of any register that can be eliminated. */
1945 #ifdef ELIMINABLE_REGS
1946 for (i = 0; i < sizeof eliminables / sizeof eliminables[0]; i++)
1947 SET_HARD_REG_BIT (used, eliminables[i].from);
1948 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
1949 /* If FRAME_POINTER_REGNUM is not a real register, then protect the one
1950 that it might be eliminated into. */
1951 SET_HARD_REG_BIT (used, HARD_FRAME_POINTER_REGNUM);
1954 SET_HARD_REG_BIT (used, FRAME_POINTER_REGNUM);
1957 #ifdef CLASS_CANNOT_CHANGE_SIZE
1958 if (qty_changes_size[qty])
1959 IOR_HARD_REG_SET (used,
1960 reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE]);
1963 /* Normally, the registers that can be used for the first register in
1964 a multi-register quantity are the same as those that can be used for
1965 subsequent registers. However, if just trying suggested registers,
1966 restrict our consideration to them. If there are copy-suggested
1967 register, try them. Otherwise, try the arithmetic-suggested
1969 COPY_HARD_REG_SET (first_used, used);
1971 if (just_try_suggested)
1973 if (qty_phys_num_copy_sugg[qty] != 0)
1974 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_copy_sugg[qty]);
1976 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_sugg[qty]);
1979 /* If all registers are excluded, we can't do anything. */
1980 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) ALL_REGS], first_used, fail);
1982 /* If at least one would be suitable, test each hard reg. */
1984 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1986 #ifdef REG_ALLOC_ORDER
1987 int regno = reg_alloc_order[i];
1991 if (! TEST_HARD_REG_BIT (first_used, regno)
1992 && HARD_REGNO_MODE_OK (regno, mode))
1995 register int size1 = HARD_REGNO_NREGS (regno, mode);
1996 for (j = 1; j < size1 && ! TEST_HARD_REG_BIT (used, regno + j); j++);
1999 /* Mark that this register is in use between its birth and death
2001 post_mark_life (regno, mode, 1, born_index, dead_index);
2004 #ifndef REG_ALLOC_ORDER
2005 i += j; /* Skip starting points we know will lose */
2012 /* If we are just trying suggested register, we have just tried copy-
2013 suggested registers, and there are arithmetic-suggested registers,
2016 /* If it would be profitable to allocate a call-clobbered register
2017 and save and restore it around calls, do that. */
2018 if (just_try_suggested && qty_phys_num_copy_sugg[qty] != 0
2019 && qty_phys_num_sugg[qty] != 0)
2021 /* Don't try the copy-suggested regs again. */
2022 qty_phys_num_copy_sugg[qty] = 0;
2023 return find_free_reg (class, mode, qty, accept_call_clobbered, 1,
2024 born_index, dead_index);
2027 /* We need not check to see if the current function has nonlocal
2028 labels because we don't put any pseudos that are live over calls in
2029 registers in that case. */
2031 if (! accept_call_clobbered
2032 && flag_caller_saves
2033 && ! just_try_suggested
2034 && qty_n_calls_crossed[qty] != 0
2035 && CALLER_SAVE_PROFITABLE (qty_n_refs[qty], qty_n_calls_crossed[qty]))
2037 i = find_free_reg (class, mode, qty, 1, 0, born_index, dead_index);
2039 caller_save_needed = 1;
2045 /* Mark that REGNO with machine-mode MODE is live starting from the current
2046 insn (if LIFE is non-zero) or dead starting at the current insn (if LIFE
2050 mark_life (regno, mode, life)
2052 enum machine_mode mode;
2055 register int j = HARD_REGNO_NREGS (regno, mode);
2058 SET_HARD_REG_BIT (regs_live, regno + j);
2061 CLEAR_HARD_REG_BIT (regs_live, regno + j);
2064 /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE
2065 is non-zero) or dead (if LIFE is zero) from insn number BIRTH (inclusive)
2066 to insn number DEATH (exclusive). */
2069 post_mark_life (regno, mode, life, birth, death)
2071 enum machine_mode mode;
2072 int life, birth, death;
2074 register int j = HARD_REGNO_NREGS (regno, mode);
2076 register /* Declare it register if it's a scalar. */
2078 HARD_REG_SET this_reg;
2080 CLEAR_HARD_REG_SET (this_reg);
2082 SET_HARD_REG_BIT (this_reg, regno + j);
2085 while (birth < death)
2087 IOR_HARD_REG_SET (regs_live_at[birth], this_reg);
2091 while (birth < death)
2093 AND_COMPL_HARD_REG_SET (regs_live_at[birth], this_reg);
2098 /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0
2099 is the register being clobbered, and R1 is a register being used in
2100 the equivalent expression.
2102 If R1 dies in the block and has a REG_NO_CONFLICT note on every insn
2103 in which it is used, return 1.
2105 Otherwise, return 0. */
2108 no_conflict_p (insn, r0, r1)
2112 rtx note = find_reg_note (insn, REG_LIBCALL, NULL_RTX);
2115 /* If R1 is a hard register, return 0 since we handle this case
2116 when we scan the insns that actually use it. */
2119 || (GET_CODE (r1) == REG && REGNO (r1) < FIRST_PSEUDO_REGISTER)
2120 || (GET_CODE (r1) == SUBREG && GET_CODE (SUBREG_REG (r1)) == REG
2121 && REGNO (SUBREG_REG (r1)) < FIRST_PSEUDO_REGISTER))
2124 last = XEXP (note, 0);
2126 for (p = NEXT_INSN (insn); p && p != last; p = NEXT_INSN (p))
2127 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
2129 if (find_reg_note (p, REG_DEAD, r1))
2132 /* There must be a REG_NO_CONFLICT note on every insn, otherwise
2133 some earlier optimization pass has inserted instructions into
2134 the sequence, and it is not safe to perform this optimization.
2135 Note that emit_no_conflict_block always ensures that this is
2136 true when these sequences are created. */
2137 if (! find_reg_note (p, REG_NO_CONFLICT, r1))
2144 #ifdef REGISTER_CONSTRAINTS
2146 /* Return the number of alternatives for which the constraint string P
2147 indicates that the operand must be equal to operand 0 and that no register
2156 int reg_allowed = 0;
2157 int num_matching_alts = 0;
2162 case '=': case '+': case '?':
2163 case '#': case '&': case '!':
2165 case '1': case '2': case '3': case '4':
2166 case 'm': case '<': case '>': case 'V': case 'o':
2167 case 'E': case 'F': case 'G': case 'H':
2168 case 's': case 'i': case 'n':
2169 case 'I': case 'J': case 'K': case 'L':
2170 case 'M': case 'N': case 'O': case 'P':
2171 #ifdef EXTRA_CONSTRAINT
2172 case 'Q': case 'R': case 'S': case 'T': case 'U':
2175 /* These don't say anything we care about. */
2179 if (found_zero && ! reg_allowed)
2180 num_matching_alts++;
2182 found_zero = reg_allowed = 0;
2196 if (found_zero && ! reg_allowed)
2197 num_matching_alts++;
2199 return num_matching_alts;
2201 #endif /* REGISTER_CONSTRAINTS */
2204 dump_local_alloc (file)
2208 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
2209 if (reg_renumber[i] != -1)
2210 fprintf (file, ";; Register %d in %d.\n", i, reg_renumber[i]);