1 /* Allocate registers within a basic block, for GNU compiler.
2 Copyright (C) 1987, 88, 91, 93-98, 1999 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* Allocation of hard register numbers to pseudo registers is done in
23 two passes. In this pass we consider only regs that are born and
24 die once within one basic block. We do this one basic block at a
25 time. Then the next pass allocates the registers that remain.
26 Two passes are used because this pass uses methods that work only
27 on linear code, but that do a better job than the general methods
28 used in global_alloc, and more quickly too.
30 The assignments made are recorded in the vector reg_renumber
31 whose space is allocated here. The rtl code itself is not altered.
33 We assign each instruction in the basic block a number
34 which is its order from the beginning of the block.
35 Then we can represent the lifetime of a pseudo register with
36 a pair of numbers, and check for conflicts easily.
37 We can record the availability of hard registers with a
38 HARD_REG_SET for each instruction. The HARD_REG_SET
39 contains 0 or 1 for each hard reg.
41 To avoid register shuffling, we tie registers together when one
42 dies by being copied into another, or dies in an instruction that
43 does arithmetic to produce another. The tied registers are
44 allocated as one. Registers with different reg class preferences
45 can never be tied unless the class preferred by one is a subclass
46 of the one preferred by the other.
48 Tying is represented with "quantity numbers".
49 A non-tied register is given a new quantity number.
50 Tied registers have the same quantity number.
52 We have provision to exempt registers, even when they are contained
53 within the block, that can be tied to others that are not contained in it.
54 This is so that global_alloc could process them both and tie them then.
55 But this is currently disabled since tying in global_alloc is not
58 /* Pseudos allocated here can be reallocated by global.c if the hard register
59 is used as a spill register. Currently we don't allocate such pseudos
60 here if their preferred class is likely to be used by spills. */
67 #include "basic-block.h"
70 #include "hard-reg-set.h"
71 #include "insn-config.h"
72 #include "insn-attr.h"
77 /* Next quantity number available for allocation. */
81 /* In all the following vectors indexed by quantity number. */
83 /* Element Q is the hard reg number chosen for quantity Q,
84 or -1 if none was found. */
86 static short *qty_phys_reg;
88 /* We maintain two hard register sets that indicate suggested hard registers
89 for each quantity. The first, qty_phys_copy_sugg, contains hard registers
90 that are tied to the quantity by a simple copy. The second contains all
91 hard registers that are tied to the quantity via an arithmetic operation.
93 The former register set is given priority for allocation. This tends to
94 eliminate copy insns. */
96 /* Element Q is a set of hard registers that are suggested for quantity Q by
99 static HARD_REG_SET *qty_phys_copy_sugg;
101 /* Element Q is a set of hard registers that are suggested for quantity Q by
104 static HARD_REG_SET *qty_phys_sugg;
106 /* Element Q is the number of suggested registers in qty_phys_copy_sugg. */
108 static short *qty_phys_num_copy_sugg;
110 /* Element Q is the number of suggested registers in qty_phys_sugg. */
112 static short *qty_phys_num_sugg;
114 /* Element Q is the number of refs to quantity Q. */
116 static int *qty_n_refs;
118 /* Element Q is a reg class contained in (smaller than) the
119 preferred classes of all the pseudo regs that are tied in quantity Q.
120 This is the preferred class for allocating that quantity. */
122 static enum reg_class *qty_min_class;
124 /* Insn number (counting from head of basic block)
125 where quantity Q was born. -1 if birth has not been recorded. */
127 static int *qty_birth;
129 /* Insn number (counting from head of basic block)
130 where quantity Q died. Due to the way tying is done,
131 and the fact that we consider in this pass only regs that die but once,
132 a quantity can die only once. Each quantity's life span
133 is a set of consecutive insns. -1 if death has not been recorded. */
135 static int *qty_death;
137 /* Number of words needed to hold the data in quantity Q.
138 This depends on its machine mode. It is used for these purposes:
139 1. It is used in computing the relative importances of qtys,
140 which determines the order in which we look for regs for them.
141 2. It is used in rules that prevent tying several registers of
142 different sizes in a way that is geometrically impossible
143 (see combine_regs). */
145 static int *qty_size;
147 /* This holds the mode of the registers that are tied to qty Q,
148 or VOIDmode if registers with differing modes are tied together. */
150 static enum machine_mode *qty_mode;
152 /* Number of times a reg tied to qty Q lives across a CALL_INSN. */
154 static int *qty_n_calls_crossed;
156 /* Register class within which we allocate qty Q if we can't get
157 its preferred class. */
159 static enum reg_class *qty_alternate_class;
161 /* Element Q is nonzero if this quantity has been used in a SUBREG
162 that changes its size. */
164 static char *qty_changes_size;
166 /* Element Q is the register number of one pseudo register whose
167 reg_qty value is Q. This register should be the head of the chain
168 maintained in reg_next_in_qty. */
170 static int *qty_first_reg;
172 /* If (REG N) has been assigned a quantity number, is a register number
173 of another register assigned the same quantity number, or -1 for the
174 end of the chain. qty_first_reg point to the head of this chain. */
176 static int *reg_next_in_qty;
178 /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg
180 of -1 if this register cannot be allocated by local-alloc,
181 or -2 if not known yet.
183 Note that if we see a use or death of pseudo register N with
184 reg_qty[N] == -2, register N must be local to the current block. If
185 it were used in more than one block, we would have reg_qty[N] == -1.
186 This relies on the fact that if reg_basic_block[N] is >= 0, register N
187 will not appear in any other block. We save a considerable number of
188 tests by exploiting this.
190 If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not
195 /* The offset (in words) of register N within its quantity.
196 This can be nonzero if register N is SImode, and has been tied
197 to a subreg of a DImode register. */
199 static char *reg_offset;
201 /* Vector of substitutions of register numbers,
202 used to map pseudo regs into hardware regs.
203 This is set up as a result of register allocation.
204 Element N is the hard reg assigned to pseudo reg N,
205 or is -1 if no hard reg was assigned.
206 If N is a hard reg number, element N is N. */
210 /* Set of hard registers live at the current point in the scan
211 of the instructions in a basic block. */
213 static HARD_REG_SET regs_live;
215 /* Each set of hard registers indicates registers live at a particular
216 point in the basic block. For N even, regs_live_at[N] says which
217 hard registers are needed *after* insn N/2 (i.e., they may not
218 conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1.
220 If an object is to conflict with the inputs of insn J but not the
221 outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly,
222 if it is to conflict with the outputs of insn J but not the inputs of
223 insn J + 1, it is said to die at index J*2 + 1. */
225 static HARD_REG_SET *regs_live_at;
227 /* Communicate local vars `insn_number' and `insn'
228 from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */
229 static int this_insn_number;
230 static rtx this_insn;
232 /* Used to communicate changes made by update_equiv_regs to
233 memref_referenced_p. reg_equiv_replacement is set for any REG_EQUIV note
234 found or created, so that we can keep track of what memory accesses might
235 be created later, e.g. by reload. */
237 static rtx *reg_equiv_replacement;
239 /* Used for communication between update_equiv_regs and no_equiv. */
240 static rtx *reg_equiv_init_insns;
242 /* Nonzero if we recorded an equivalence for a LABEL_REF. */
243 static int recorded_label_ref;
245 static void alloc_qty PROTO((int, enum machine_mode, int, int));
246 static void validate_equiv_mem_from_store PROTO((rtx, rtx));
247 static int validate_equiv_mem PROTO((rtx, rtx, rtx));
248 static int contains_replace_regs PROTO((rtx, char *));
249 static int memref_referenced_p PROTO((rtx, rtx));
250 static int memref_used_between_p PROTO((rtx, rtx, rtx));
251 static void update_equiv_regs PROTO((void));
252 static void no_equiv PROTO((rtx, rtx));
253 static void block_alloc PROTO((int));
254 static int qty_sugg_compare PROTO((int, int));
255 static int qty_sugg_compare_1 PROTO((const PTR, const PTR));
256 static int qty_compare PROTO((int, int));
257 static int qty_compare_1 PROTO((const PTR, const PTR));
258 static int combine_regs PROTO((rtx, rtx, int, int, rtx, int));
259 static int reg_meets_class_p PROTO((int, enum reg_class));
260 static void update_qty_class PROTO((int, int));
261 static void reg_is_set PROTO((rtx, rtx));
262 static void reg_is_born PROTO((rtx, int));
263 static void wipe_dead_reg PROTO((rtx, int));
264 static int find_free_reg PROTO((enum reg_class, enum machine_mode,
265 int, int, int, int, int));
266 static void mark_life PROTO((int, enum machine_mode, int));
267 static void post_mark_life PROTO((int, enum machine_mode, int, int, int));
268 static int no_conflict_p PROTO((rtx, rtx, rtx));
269 static int requires_inout PROTO((const char *));
271 /* Allocate a new quantity (new within current basic block)
272 for register number REGNO which is born at index BIRTH
273 within the block. MODE and SIZE are info on reg REGNO. */
276 alloc_qty (regno, mode, size, birth)
278 enum machine_mode mode;
281 register int qty = next_qty++;
283 reg_qty[regno] = qty;
284 reg_offset[regno] = 0;
285 reg_next_in_qty[regno] = -1;
287 qty_first_reg[qty] = regno;
288 qty_size[qty] = size;
289 qty_mode[qty] = mode;
290 qty_birth[qty] = birth;
291 qty_n_calls_crossed[qty] = REG_N_CALLS_CROSSED (regno);
292 qty_min_class[qty] = reg_preferred_class (regno);
293 qty_alternate_class[qty] = reg_alternate_class (regno);
294 qty_n_refs[qty] = REG_N_REFS (regno);
295 qty_changes_size[qty] = REG_CHANGES_SIZE (regno);
298 /* Main entry point of this file. */
306 /* We need to keep track of whether or not we recorded a LABEL_REF so
307 that we know if the jump optimizer needs to be rerun. */
308 recorded_label_ref = 0;
310 /* Leaf functions and non-leaf functions have different needs.
311 If defined, let the machine say what kind of ordering we
313 #ifdef ORDER_REGS_FOR_LOCAL_ALLOC
314 ORDER_REGS_FOR_LOCAL_ALLOC;
317 /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected
319 update_equiv_regs ();
321 /* This sets the maximum number of quantities we can have. Quantity
322 numbers start at zero and we can have one for each pseudo. */
323 max_qty = (max_regno - FIRST_PSEUDO_REGISTER);
325 /* Allocate vectors of temporary data.
326 See the declarations of these variables, above,
327 for what they mean. */
329 qty_phys_reg = (short *) alloca (max_qty * sizeof (short));
331 = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET));
332 qty_phys_num_copy_sugg = (short *) alloca (max_qty * sizeof (short));
333 qty_phys_sugg = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET));
334 qty_phys_num_sugg = (short *) alloca (max_qty * sizeof (short));
335 qty_birth = (int *) alloca (max_qty * sizeof (int));
336 qty_death = (int *) alloca (max_qty * sizeof (int));
337 qty_first_reg = (int *) alloca (max_qty * sizeof (int));
338 qty_size = (int *) alloca (max_qty * sizeof (int));
340 = (enum machine_mode *) alloca (max_qty * sizeof (enum machine_mode));
341 qty_n_calls_crossed = (int *) alloca (max_qty * sizeof (int));
343 = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class));
345 = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class));
346 qty_n_refs = (int *) alloca (max_qty * sizeof (int));
347 qty_changes_size = (char *) alloca (max_qty * sizeof (char));
349 reg_qty = (int *) xmalloc (max_regno * sizeof (int));
350 reg_offset = (char *) xmalloc (max_regno * sizeof (char));
351 reg_next_in_qty = (int *) xmalloc(max_regno * sizeof (int));
353 /* Allocate the reg_renumber array */
354 allocate_reg_info (max_regno, FALSE, TRUE);
356 /* Determine which pseudo-registers can be allocated by local-alloc.
357 In general, these are the registers used only in a single block and
358 which only die once. However, if a register's preferred class has only
359 a few entries, don't allocate this register here unless it is preferred
360 or nothing since retry_global_alloc won't be able to move it to
361 GENERAL_REGS if a reload register of this class is needed.
363 We need not be concerned with which block actually uses the register
364 since we will never see it outside that block. */
366 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
368 if (REG_BASIC_BLOCK (i) >= 0 && REG_N_DEATHS (i) == 1
369 && (reg_alternate_class (i) == NO_REGS
370 || ! CLASS_LIKELY_SPILLED_P (reg_preferred_class (i))))
376 /* Force loop below to initialize entire quantity array. */
379 /* Allocate each block's local registers, block by block. */
381 for (b = 0; b < n_basic_blocks; b++)
383 /* NEXT_QTY indicates which elements of the `qty_...'
384 vectors might need to be initialized because they were used
385 for the previous block; it is set to the entire array before
386 block 0. Initialize those, with explicit loop if there are few,
387 else with bzero and bcopy. Do not initialize vectors that are
388 explicit set by `alloc_qty'. */
392 for (i = 0; i < next_qty; i++)
394 CLEAR_HARD_REG_SET (qty_phys_copy_sugg[i]);
395 qty_phys_num_copy_sugg[i] = 0;
396 CLEAR_HARD_REG_SET (qty_phys_sugg[i]);
397 qty_phys_num_sugg[i] = 0;
402 #define CLEAR(vector) \
403 bzero ((char *) (vector), (sizeof (*(vector))) * next_qty);
405 CLEAR (qty_phys_copy_sugg);
406 CLEAR (qty_phys_num_copy_sugg);
407 CLEAR (qty_phys_sugg);
408 CLEAR (qty_phys_num_sugg);
421 free (reg_next_in_qty);
422 return recorded_label_ref;
425 /* Depth of loops we are in while in update_equiv_regs. */
426 static int loop_depth;
428 /* Used for communication between the following two functions: contains
429 a MEM that we wish to ensure remains unchanged. */
430 static rtx equiv_mem;
432 /* Set nonzero if EQUIV_MEM is modified. */
433 static int equiv_mem_modified;
435 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
436 Called via note_stores. */
439 validate_equiv_mem_from_store (dest, set)
441 rtx set ATTRIBUTE_UNUSED;
443 if ((GET_CODE (dest) == REG
444 && reg_overlap_mentioned_p (dest, equiv_mem))
445 || (GET_CODE (dest) == MEM
446 && true_dependence (dest, VOIDmode, equiv_mem, rtx_varies_p)))
447 equiv_mem_modified = 1;
450 /* Verify that no store between START and the death of REG invalidates
451 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
452 by storing into an overlapping memory location, or with a non-const
455 Return 1 if MEMREF remains valid. */
458 validate_equiv_mem (start, reg, memref)
467 equiv_mem_modified = 0;
469 /* If the memory reference has side effects or is volatile, it isn't a
470 valid equivalence. */
471 if (side_effects_p (memref))
474 for (insn = start; insn && ! equiv_mem_modified; insn = NEXT_INSN (insn))
476 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
479 if (find_reg_note (insn, REG_DEAD, reg))
482 if (GET_CODE (insn) == CALL_INSN && ! RTX_UNCHANGING_P (memref)
483 && ! CONST_CALL_P (insn))
486 note_stores (PATTERN (insn), validate_equiv_mem_from_store);
488 /* If a register mentioned in MEMREF is modified via an
489 auto-increment, we lose the equivalence. Do the same if one
490 dies; although we could extend the life, it doesn't seem worth
493 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
494 if ((REG_NOTE_KIND (note) == REG_INC
495 || REG_NOTE_KIND (note) == REG_DEAD)
496 && GET_CODE (XEXP (note, 0)) == REG
497 && reg_overlap_mentioned_p (XEXP (note, 0), memref))
504 /* TRUE if X uses any registers for which reg_equiv_replace is true. */
507 contains_replace_regs (x, reg_equiv_replace)
509 char *reg_equiv_replace;
513 enum rtx_code code = GET_CODE (x);
529 return reg_equiv_replace[REGNO (x)];
535 fmt = GET_RTX_FORMAT (code);
536 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
540 if (contains_replace_regs (XEXP (x, i), reg_equiv_replace))
544 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
545 if (contains_replace_regs (XVECEXP (x, i, j), reg_equiv_replace))
553 /* TRUE if X references a memory location that would be affected by a store
557 memref_referenced_p (memref, x)
563 enum rtx_code code = GET_CODE (x);
579 return (reg_equiv_replacement[REGNO (x)]
580 && memref_referenced_p (memref,
581 reg_equiv_replacement[REGNO (x)]));
584 if (true_dependence (memref, VOIDmode, x, rtx_varies_p))
589 /* If we are setting a MEM, it doesn't count (its address does), but any
590 other SET_DEST that has a MEM in it is referencing the MEM. */
591 if (GET_CODE (SET_DEST (x)) == MEM)
593 if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0)))
596 else if (memref_referenced_p (memref, SET_DEST (x)))
599 return memref_referenced_p (memref, SET_SRC (x));
605 fmt = GET_RTX_FORMAT (code);
606 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
610 if (memref_referenced_p (memref, XEXP (x, i)))
614 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
615 if (memref_referenced_p (memref, XVECEXP (x, i, j)))
623 /* TRUE if some insn in the range (START, END] references a memory location
624 that would be affected by a store to MEMREF. */
627 memref_used_between_p (memref, start, end)
634 for (insn = NEXT_INSN (start); insn != NEXT_INSN (end);
635 insn = NEXT_INSN (insn))
636 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
637 && memref_referenced_p (memref, PATTERN (insn)))
643 /* Return nonzero if the rtx X is invariant over the current function. */
645 function_invariant_p (x)
650 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
652 if (GET_CODE (x) == PLUS
653 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
654 && CONSTANT_P (XEXP (x, 1)))
659 /* Find registers that are equivalent to a single value throughout the
660 compilation (either because they can be referenced in memory or are set once
661 from a single constant). Lower their priority for a register.
663 If such a register is only referenced once, try substituting its value
664 into the using insn. If it succeeds, we can eliminate the register
670 /* Set when an attempt should be made to replace a register with the
671 associated reg_equiv_replacement entry at the end of this function. */
672 char *reg_equiv_replace
673 = (char *) alloca (max_regno * sizeof *reg_equiv_replace);
677 reg_equiv_init_insns = (rtx *) alloca (max_regno * sizeof (rtx));
678 reg_equiv_replacement = (rtx *) alloca (max_regno * sizeof (rtx));
680 bzero ((char *) reg_equiv_init_insns, max_regno * sizeof (rtx));
681 bzero ((char *) reg_equiv_replacement, max_regno * sizeof (rtx));
682 bzero ((char *) reg_equiv_replace, max_regno * sizeof *reg_equiv_replace);
684 init_alias_analysis ();
688 /* Scan the insns and find which registers have equivalences. Do this
689 in a separate scan of the insns because (due to -fcse-follow-jumps)
690 a register can be set below its use. */
691 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
698 if (GET_CODE (insn) == NOTE)
700 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
702 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
706 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
709 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
710 if (REG_NOTE_KIND (note) == REG_INC)
711 no_equiv (XEXP (note, 0), note);
713 set = single_set (insn);
715 /* If this insn contains more (or less) than a single SET,
716 only mark all destinations as having no known equivalence. */
719 note_stores (PATTERN (insn), no_equiv);
722 else if (GET_CODE (PATTERN (insn)) == PARALLEL)
726 for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--)
728 rtx part = XVECEXP (PATTERN (insn), 0, i);
730 note_stores (part, no_equiv);
734 dest = SET_DEST (set);
737 /* If this sets a MEM to the contents of a REG that is only used
738 in a single basic block, see if the register is always equivalent
739 to that memory location and if moving the store from INSN to the
740 insn that set REG is safe. If so, put a REG_EQUIV note on the
743 Don't add a REG_EQUIV note if the insn already has one. The existing
744 REG_EQUIV is likely more useful than the one we are adding.
746 If one of the regs in the address is marked as reg_equiv_replace,
747 then we can't add this REG_EQUIV note. The reg_equiv_replace
748 optimization may move the set of this register immediately before
749 insn, which puts it after reg_equiv_init_insns[regno], and hence
750 the mention in the REG_EQUIV note would be to an uninitialized
752 /* ????? This test isn't good enough; we might see a MEM with a use of
753 a pseudo register before we see its setting insn that will cause
754 reg_equiv_replace for that pseudo to be set.
755 Equivalences to MEMs should be made in another pass, after the
756 reg_equiv_replace information has been gathered. */
758 if (GET_CODE (dest) == MEM && GET_CODE (src) == REG
759 && (regno = REGNO (src)) >= FIRST_PSEUDO_REGISTER
760 && REG_BASIC_BLOCK (regno) >= 0
761 && REG_N_SETS (regno) == 1
762 && reg_equiv_init_insns[regno] != 0
763 && reg_equiv_init_insns[regno] != const0_rtx
764 && ! find_reg_note (insn, REG_EQUIV, NULL_RTX)
765 && ! contains_replace_regs (XEXP (dest, 0), reg_equiv_replace))
767 rtx init_insn = XEXP (reg_equiv_init_insns[regno], 0);
768 if (validate_equiv_mem (init_insn, src, dest)
769 && ! memref_used_between_p (dest, init_insn, insn))
770 REG_NOTES (init_insn)
771 = gen_rtx_EXPR_LIST (REG_EQUIV, dest, REG_NOTES (init_insn));
774 /* We only handle the case of a pseudo register being set
775 once, or always to the same value. */
776 /* ??? The mn10200 port breaks if we add equivalences for
777 values that need an ADDRESS_REGS register and set them equivalent
778 to a MEM of a pseudo. The actual problem is in the over-conservative
779 handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in
780 calculate_needs, but we traditionally work around this problem
781 here by rejecting equivalences when the destination is in a register
782 that's likely spilled. This is fragile, of course, since the
783 preferred class of a pseudo depends on all instructions that set
786 if (GET_CODE (dest) != REG
787 || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER
788 || reg_equiv_init_insns[regno] == const0_rtx
789 || (CLASS_LIKELY_SPILLED_P (reg_preferred_class (regno))
790 && GET_CODE (src) == MEM))
792 /* This might be seting a SUBREG of a pseudo, a pseudo that is
793 also set somewhere else to a constant. */
794 note_stores (set, no_equiv);
797 /* Don't handle the equivalence if the source is in a register
798 class that's likely to be spilled. */
799 if (GET_CODE (src) == REG
800 && REGNO (src) >= FIRST_PSEUDO_REGISTER
801 && CLASS_LIKELY_SPILLED_P (reg_preferred_class (REGNO (src))))
803 no_equiv (dest, set);
807 note = find_reg_note (insn, REG_EQUAL, NULL_RTX);
809 if (REG_N_SETS (regno) != 1
811 || ! function_invariant_p (XEXP (note, 0))
812 || (reg_equiv_replacement[regno]
813 && ! rtx_equal_p (XEXP (note, 0),
814 reg_equiv_replacement[regno]))))
816 no_equiv (dest, set);
819 /* Record this insn as initializing this register. */
820 reg_equiv_init_insns[regno]
821 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init_insns[regno]);
823 /* If this register is known to be equal to a constant, record that
824 it is always equivalent to the constant. */
825 if (note && function_invariant_p (XEXP (note, 0)))
826 PUT_MODE (note, (enum machine_mode) REG_EQUIV);
828 /* If this insn introduces a "constant" register, decrease the priority
829 of that register. Record this insn if the register is only used once
830 more and the equivalence value is the same as our source.
832 The latter condition is checked for two reasons: First, it is an
833 indication that it may be more efficient to actually emit the insn
834 as written (if no registers are available, reload will substitute
835 the equivalence). Secondly, it avoids problems with any registers
836 dying in this insn whose death notes would be missed.
838 If we don't have a REG_EQUIV note, see if this insn is loading
839 a register used only in one basic block from a MEM. If so, and the
840 MEM remains unchanged for the life of the register, add a REG_EQUIV
843 note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
845 if (note == 0 && REG_BASIC_BLOCK (regno) >= 0
846 && GET_CODE (SET_SRC (set)) == MEM
847 && validate_equiv_mem (insn, dest, SET_SRC (set)))
848 REG_NOTES (insn) = note = gen_rtx_EXPR_LIST (REG_EQUIV, SET_SRC (set),
853 int regno = REGNO (dest);
855 /* Record whether or not we created a REG_EQUIV note for a LABEL_REF.
856 We might end up substituting the LABEL_REF for uses of the
857 pseudo here or later. That kind of transformation may turn an
858 indirect jump into a direct jump, in which case we must rerun the
859 jump optimizer to ensure that the JUMP_LABEL fields are valid. */
860 if (GET_CODE (XEXP (note, 0)) == LABEL_REF
861 || (GET_CODE (XEXP (note, 0)) == CONST
862 && GET_CODE (XEXP (XEXP (note, 0), 0)) == PLUS
863 && (GET_CODE (XEXP (XEXP (XEXP (note, 0), 0), 0))
865 recorded_label_ref = 1;
868 reg_equiv_replacement[regno] = XEXP (note, 0);
870 /* Don't mess with things live during setjmp. */
871 if (REG_LIVE_LENGTH (regno) >= 0)
873 /* Note that the statement below does not affect the priority
875 REG_LIVE_LENGTH (regno) *= 2;
878 /* If the register is referenced exactly twice, meaning it is
879 set once and used once, indicate that the reference may be
880 replaced by the equivalence we computed above. If the
881 register is only used in one basic block, this can't succeed
882 or combine would have done it.
884 It would be nice to use "loop_depth * 2" in the compare
885 below. Unfortunately, LOOP_DEPTH need not be constant within
886 a basic block so this would be too complicated.
888 This case normally occurs when a parameter is read from
889 memory and then used exactly once, not in a loop. */
891 if (REG_N_REFS (regno) == 2
892 && REG_BASIC_BLOCK (regno) < 0
893 && rtx_equal_p (XEXP (note, 0), SET_SRC (set)))
894 reg_equiv_replace[regno] = 1;
899 /* Now scan all regs killed in an insn to see if any of them are
900 registers only used that once. If so, see if we can replace the
901 reference with the equivalent from. If we can, delete the
902 initializing reference and this register will go away. If we
903 can't replace the reference, and the instruction is not in a
904 loop, then move the register initialization just before the use,
905 so that they are in the same basic block. */
908 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
912 /* Keep track of which basic block we are in. */
913 if (block + 1 < n_basic_blocks
914 && BLOCK_HEAD (block + 1) == insn)
917 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
919 if (GET_CODE (insn) == NOTE)
921 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
923 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
934 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
936 if (REG_NOTE_KIND (link) == REG_DEAD
937 /* Make sure this insn still refers to the register. */
938 && reg_mentioned_p (XEXP (link, 0), PATTERN (insn)))
940 int regno = REGNO (XEXP (link, 0));
943 if (! reg_equiv_replace[regno])
946 /* reg_equiv_replace[REGNO] gets set only when
947 REG_N_REFS[REGNO] is 2, i.e. the register is set
948 once and used once. (If it were only set, but not used,
949 flow would have deleted the setting insns.) Hence
950 there can only be one insn in reg_equiv_init_insns. */
951 equiv_insn = XEXP (reg_equiv_init_insns[regno], 0);
953 if (validate_replace_rtx (regno_reg_rtx[regno],
954 reg_equiv_replacement[regno], insn))
956 remove_death (regno, insn);
957 REG_N_REFS (regno) = 0;
958 PUT_CODE (equiv_insn, NOTE);
959 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
960 NOTE_SOURCE_FILE (equiv_insn) = 0;
962 /* If we aren't in a loop, and there are no calls in
963 INSN or in the initialization of the register, then
964 move the initialization of the register to just
965 before INSN. Update the flow information. */
967 && GET_CODE (equiv_insn) == INSN
968 && GET_CODE (insn) == INSN
969 && REG_BASIC_BLOCK (regno) < 0)
973 emit_insn_before (copy_rtx (PATTERN (equiv_insn)), insn);
974 REG_NOTES (PREV_INSN (insn)) = REG_NOTES (equiv_insn);
975 REG_NOTES (equiv_insn) = 0;
977 PUT_CODE (equiv_insn, NOTE);
978 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
979 NOTE_SOURCE_FILE (equiv_insn) = 0;
982 REG_BASIC_BLOCK (regno) = 0;
984 REG_BASIC_BLOCK (regno) = block;
985 REG_N_CALLS_CROSSED (regno) = 0;
986 REG_LIVE_LENGTH (regno) = 2;
988 if (block >= 0 && insn == BLOCK_HEAD (block))
989 BLOCK_HEAD (block) = PREV_INSN (insn);
991 for (l = 0; l < n_basic_blocks; l++)
992 CLEAR_REGNO_REG_SET (BASIC_BLOCK (l)->global_live_at_start,
1000 /* Mark REG as having no known equivalence.
1001 Some instructions might have been proceessed before and furnished
1002 with REG_EQUIV notes for this register; these notes will have to be
1004 STORE is the piece of RTL that does the non-constant / conflicting
1005 assignment - a SET, CLOBBER or REG_INC note. It is currently not used,
1006 but needs to be there because this function is called from note_stores. */
1008 no_equiv (reg, store)
1009 rtx reg, store ATTRIBUTE_UNUSED;
1014 if (GET_CODE (reg) != REG)
1016 regno = REGNO (reg);
1017 list = reg_equiv_init_insns[regno];
1018 if (list == const0_rtx)
1020 for (; list; list = XEXP (list, 1))
1022 rtx insn = XEXP (list, 0);
1023 remove_note (insn, find_reg_note (insn, REG_EQUIV, NULL_RTX));
1025 reg_equiv_init_insns[regno] = const0_rtx;
1026 reg_equiv_replacement[regno] = NULL_RTX;
1029 /* Allocate hard regs to the pseudo regs used only within block number B.
1030 Only the pseudos that die but once can be handled. */
1039 int insn_number = 0;
1041 int max_uid = get_max_uid ();
1043 int no_conflict_combined_regno = -1;
1045 /* Count the instructions in the basic block. */
1047 insn = BLOCK_END (b);
1050 if (GET_CODE (insn) != NOTE)
1051 if (++insn_count > max_uid)
1053 if (insn == BLOCK_HEAD (b))
1055 insn = PREV_INSN (insn);
1058 /* +2 to leave room for a post_mark_life at the last insn and for
1059 the birth of a CLOBBER in the first insn. */
1060 regs_live_at = (HARD_REG_SET *) alloca ((2 * insn_count + 2)
1061 * sizeof (HARD_REG_SET));
1062 bzero ((char *) regs_live_at, (2 * insn_count + 2) * sizeof (HARD_REG_SET));
1064 /* Initialize table of hardware registers currently live. */
1066 REG_SET_TO_HARD_REG_SET (regs_live, BASIC_BLOCK (b)->global_live_at_start);
1068 /* This loop scans the instructions of the basic block
1069 and assigns quantities to registers.
1070 It computes which registers to tie. */
1072 insn = BLOCK_HEAD (b);
1075 if (GET_CODE (insn) != NOTE)
1078 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1080 register rtx link, set;
1081 register int win = 0;
1082 register rtx r0, r1;
1083 int combined_regno = -1;
1086 this_insn_number = insn_number;
1089 extract_insn (insn);
1090 which_alternative = -1;
1092 /* Is this insn suitable for tying two registers?
1093 If so, try doing that.
1094 Suitable insns are those with at least two operands and where
1095 operand 0 is an output that is a register that is not
1098 We can tie operand 0 with some operand that dies in this insn.
1099 First look for operands that are required to be in the same
1100 register as operand 0. If we find such, only try tying that
1101 operand or one that can be put into that operand if the
1102 operation is commutative. If we don't find an operand
1103 that is required to be in the same register as operand 0,
1104 we can tie with any operand.
1106 Subregs in place of regs are also ok.
1108 If tying is done, WIN is set nonzero. */
1110 if (recog_data.n_operands > 1
1111 && recog_data.constraints[0][0] == '='
1112 && recog_data.constraints[0][1] != '&')
1114 /* If non-negative, is an operand that must match operand 0. */
1115 int must_match_0 = -1;
1116 /* Counts number of alternatives that require a match with
1118 int n_matching_alts = 0;
1120 for (i = 1; i < recog_data.n_operands; i++)
1122 const char *p = recog_data.constraints[i];
1123 int this_match = (requires_inout (p));
1125 n_matching_alts += this_match;
1126 if (this_match == recog_data.n_alternatives)
1130 r0 = recog_data.operand[0];
1131 for (i = 1; i < recog_data.n_operands; i++)
1133 /* Skip this operand if we found an operand that
1134 must match operand 0 and this operand isn't it
1135 and can't be made to be it by commutativity. */
1137 if (must_match_0 >= 0 && i != must_match_0
1138 && ! (i == must_match_0 + 1
1139 && recog_data.constraints[i-1][0] == '%')
1140 && ! (i == must_match_0 - 1
1141 && recog_data.constraints[i][0] == '%'))
1144 /* Likewise if each alternative has some operand that
1145 must match operand zero. In that case, skip any
1146 operand that doesn't list operand 0 since we know that
1147 the operand always conflicts with operand 0. We
1148 ignore commutatity in this case to keep things simple. */
1149 if (n_matching_alts == recog_data.n_alternatives
1150 && 0 == requires_inout (recog_data.constraints[i]))
1153 r1 = recog_data.operand[i];
1155 /* If the operand is an address, find a register in it.
1156 There may be more than one register, but we only try one
1158 if (recog_data.constraints[i][0] == 'p')
1159 while (GET_CODE (r1) == PLUS || GET_CODE (r1) == MULT)
1162 if (GET_CODE (r0) == REG || GET_CODE (r0) == SUBREG)
1164 /* We have two priorities for hard register preferences.
1165 If we have a move insn or an insn whose first input
1166 can only be in the same register as the output, give
1167 priority to an equivalence found from that insn. */
1169 = (r1 == recog_data.operand[i] && must_match_0 >= 0);
1171 if (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1172 win = combine_regs (r1, r0, may_save_copy,
1173 insn_number, insn, 0);
1180 /* Recognize an insn sequence with an ultimate result
1181 which can safely overlap one of the inputs.
1182 The sequence begins with a CLOBBER of its result,
1183 and ends with an insn that copies the result to itself
1184 and has a REG_EQUAL note for an equivalent formula.
1185 That note indicates what the inputs are.
1186 The result and the input can overlap if each insn in
1187 the sequence either doesn't mention the input
1188 or has a REG_NO_CONFLICT note to inhibit the conflict.
1190 We do the combining test at the CLOBBER so that the
1191 destination register won't have had a quantity number
1192 assigned, since that would prevent combining. */
1194 if (GET_CODE (PATTERN (insn)) == CLOBBER
1195 && (r0 = XEXP (PATTERN (insn), 0),
1196 GET_CODE (r0) == REG)
1197 && (link = find_reg_note (insn, REG_LIBCALL, NULL_RTX)) != 0
1198 && XEXP (link, 0) != 0
1199 && GET_CODE (XEXP (link, 0)) == INSN
1200 && (set = single_set (XEXP (link, 0))) != 0
1201 && SET_DEST (set) == r0 && SET_SRC (set) == r0
1202 && (note = find_reg_note (XEXP (link, 0), REG_EQUAL,
1205 if (r1 = XEXP (note, 0), GET_CODE (r1) == REG
1206 /* Check that we have such a sequence. */
1207 && no_conflict_p (insn, r0, r1))
1208 win = combine_regs (r1, r0, 1, insn_number, insn, 1);
1209 else if (GET_RTX_FORMAT (GET_CODE (XEXP (note, 0)))[0] == 'e'
1210 && (r1 = XEXP (XEXP (note, 0), 0),
1211 GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1212 && no_conflict_p (insn, r0, r1))
1213 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1215 /* Here we care if the operation to be computed is
1217 else if ((GET_CODE (XEXP (note, 0)) == EQ
1218 || GET_CODE (XEXP (note, 0)) == NE
1219 || GET_RTX_CLASS (GET_CODE (XEXP (note, 0))) == 'c')
1220 && (r1 = XEXP (XEXP (note, 0), 1),
1221 (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG))
1222 && no_conflict_p (insn, r0, r1))
1223 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1225 /* If we did combine something, show the register number
1226 in question so that we know to ignore its death. */
1228 no_conflict_combined_regno = REGNO (r1);
1231 /* If registers were just tied, set COMBINED_REGNO
1232 to the number of the register used in this insn
1233 that was tied to the register set in this insn.
1234 This register's qty should not be "killed". */
1238 while (GET_CODE (r1) == SUBREG)
1239 r1 = SUBREG_REG (r1);
1240 combined_regno = REGNO (r1);
1243 /* Mark the death of everything that dies in this instruction,
1244 except for anything that was just combined. */
1246 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1247 if (REG_NOTE_KIND (link) == REG_DEAD
1248 && GET_CODE (XEXP (link, 0)) == REG
1249 && combined_regno != REGNO (XEXP (link, 0))
1250 && (no_conflict_combined_regno != REGNO (XEXP (link, 0))
1251 || ! find_reg_note (insn, REG_NO_CONFLICT, XEXP (link, 0))))
1252 wipe_dead_reg (XEXP (link, 0), 0);
1254 /* Allocate qty numbers for all registers local to this block
1255 that are born (set) in this instruction.
1256 A pseudo that already has a qty is not changed. */
1258 note_stores (PATTERN (insn), reg_is_set);
1260 /* If anything is set in this insn and then unused, mark it as dying
1261 after this insn, so it will conflict with our outputs. This
1262 can't match with something that combined, and it doesn't matter
1263 if it did. Do this after the calls to reg_is_set since these
1264 die after, not during, the current insn. */
1266 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1267 if (REG_NOTE_KIND (link) == REG_UNUSED
1268 && GET_CODE (XEXP (link, 0)) == REG)
1269 wipe_dead_reg (XEXP (link, 0), 1);
1271 /* If this is an insn that has a REG_RETVAL note pointing at a
1272 CLOBBER insn, we have reached the end of a REG_NO_CONFLICT
1273 block, so clear any register number that combined within it. */
1274 if ((note = find_reg_note (insn, REG_RETVAL, NULL_RTX)) != 0
1275 && GET_CODE (XEXP (note, 0)) == INSN
1276 && GET_CODE (PATTERN (XEXP (note, 0))) == CLOBBER)
1277 no_conflict_combined_regno = -1;
1280 /* Set the registers live after INSN_NUMBER. Note that we never
1281 record the registers live before the block's first insn, since no
1282 pseudos we care about are live before that insn. */
1284 IOR_HARD_REG_SET (regs_live_at[2 * insn_number], regs_live);
1285 IOR_HARD_REG_SET (regs_live_at[2 * insn_number + 1], regs_live);
1287 if (insn == BLOCK_END (b))
1290 insn = NEXT_INSN (insn);
1293 /* Now every register that is local to this basic block
1294 should have been given a quantity, or else -1 meaning ignore it.
1295 Every quantity should have a known birth and death.
1297 Order the qtys so we assign them registers in order of the
1298 number of suggested registers they need so we allocate those with
1299 the most restrictive needs first. */
1301 qty_order = (int *) alloca (next_qty * sizeof (int));
1302 for (i = 0; i < next_qty; i++)
1305 #define EXCHANGE(I1, I2) \
1306 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1311 /* Make qty_order[2] be the one to allocate last. */
1312 if (qty_sugg_compare (0, 1) > 0)
1314 if (qty_sugg_compare (1, 2) > 0)
1317 /* ... Fall through ... */
1319 /* Put the best one to allocate in qty_order[0]. */
1320 if (qty_sugg_compare (0, 1) > 0)
1323 /* ... Fall through ... */
1327 /* Nothing to do here. */
1331 qsort (qty_order, next_qty, sizeof (int), qty_sugg_compare_1);
1334 /* Try to put each quantity in a suggested physical register, if it has one.
1335 This may cause registers to be allocated that otherwise wouldn't be, but
1336 this seems acceptable in local allocation (unlike global allocation). */
1337 for (i = 0; i < next_qty; i++)
1340 if (qty_phys_num_sugg[q] != 0 || qty_phys_num_copy_sugg[q] != 0)
1341 qty_phys_reg[q] = find_free_reg (qty_min_class[q], qty_mode[q], q,
1342 0, 1, qty_birth[q], qty_death[q]);
1344 qty_phys_reg[q] = -1;
1347 /* Order the qtys so we assign them registers in order of
1348 decreasing length of life. Normally call qsort, but if we
1349 have only a very small number of quantities, sort them ourselves. */
1351 for (i = 0; i < next_qty; i++)
1354 #define EXCHANGE(I1, I2) \
1355 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1360 /* Make qty_order[2] be the one to allocate last. */
1361 if (qty_compare (0, 1) > 0)
1363 if (qty_compare (1, 2) > 0)
1366 /* ... Fall through ... */
1368 /* Put the best one to allocate in qty_order[0]. */
1369 if (qty_compare (0, 1) > 0)
1372 /* ... Fall through ... */
1376 /* Nothing to do here. */
1380 qsort (qty_order, next_qty, sizeof (int), qty_compare_1);
1383 /* Now for each qty that is not a hardware register,
1384 look for a hardware register to put it in.
1385 First try the register class that is cheapest for this qty,
1386 if there is more than one class. */
1388 for (i = 0; i < next_qty; i++)
1391 if (qty_phys_reg[q] < 0)
1393 #ifdef INSN_SCHEDULING
1394 /* These values represent the adjusted lifetime of a qty so
1395 that it conflicts with qtys which appear near the start/end
1396 of this qty's lifetime.
1398 The purpose behind extending the lifetime of this qty is to
1399 discourage the register allocator from creating false
1402 The adjustment value is choosen to indicate that this qty
1403 conflicts with all the qtys in the instructions immediately
1404 before and after the lifetime of this qty.
1406 Experiments have shown that higher values tend to hurt
1407 overall code performance.
1409 If allocation using the extended lifetime fails we will try
1410 again with the qty's unadjusted lifetime. */
1411 int fake_birth = MAX (0, qty_birth[q] - 2 + qty_birth[q] % 2);
1412 int fake_death = MIN (insn_number * 2 + 1,
1413 qty_death[q] + 2 - qty_death[q] % 2);
1416 if (N_REG_CLASSES > 1)
1418 #ifdef INSN_SCHEDULING
1419 /* We try to avoid using hard registers allocated to qtys which
1420 are born immediately after this qty or die immediately before
1423 This optimization is only appropriate when we will run
1424 a scheduling pass after reload and we are not optimizing
1426 if (flag_schedule_insns_after_reload
1428 && !SMALL_REGISTER_CLASSES)
1431 qty_phys_reg[q] = find_free_reg (qty_min_class[q],
1432 qty_mode[q], q, 0, 0,
1433 fake_birth, fake_death);
1434 if (qty_phys_reg[q] >= 0)
1438 qty_phys_reg[q] = find_free_reg (qty_min_class[q],
1439 qty_mode[q], q, 0, 0,
1440 qty_birth[q], qty_death[q]);
1441 if (qty_phys_reg[q] >= 0)
1445 #ifdef INSN_SCHEDULING
1446 /* Similarly, avoid false dependencies. */
1447 if (flag_schedule_insns_after_reload
1449 && !SMALL_REGISTER_CLASSES
1450 && qty_alternate_class[q] != NO_REGS)
1451 qty_phys_reg[q] = find_free_reg (qty_alternate_class[q],
1452 qty_mode[q], q, 0, 0,
1453 fake_birth, fake_death);
1455 if (qty_alternate_class[q] != NO_REGS)
1456 qty_phys_reg[q] = find_free_reg (qty_alternate_class[q],
1457 qty_mode[q], q, 0, 0,
1458 qty_birth[q], qty_death[q]);
1462 /* Now propagate the register assignments
1463 to the pseudo regs belonging to the qtys. */
1465 for (q = 0; q < next_qty; q++)
1466 if (qty_phys_reg[q] >= 0)
1468 for (i = qty_first_reg[q]; i >= 0; i = reg_next_in_qty[i])
1469 reg_renumber[i] = qty_phys_reg[q] + reg_offset[i];
1473 /* Compare two quantities' priority for getting real registers.
1474 We give shorter-lived quantities higher priority.
1475 Quantities with more references are also preferred, as are quantities that
1476 require multiple registers. This is the identical prioritization as
1477 done by global-alloc.
1479 We used to give preference to registers with *longer* lives, but using
1480 the same algorithm in both local- and global-alloc can speed up execution
1481 of some programs by as much as a factor of three! */
1483 /* Note that the quotient will never be bigger than
1484 the value of floor_log2 times the maximum number of
1485 times a register can occur in one insn (surely less than 100).
1486 Multiplying this by 10000 can't overflow.
1487 QTY_CMP_PRI is also used by qty_sugg_compare. */
1489 #define QTY_CMP_PRI(q) \
1490 ((int) (((double) (floor_log2 (qty_n_refs[q]) * qty_n_refs[q] * qty_size[q]) \
1491 / (qty_death[q] - qty_birth[q])) * 10000))
1494 qty_compare (q1, q2)
1497 return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1501 qty_compare_1 (q1p, q2p)
1505 register int q1 = *(int *)q1p, q2 = *(int *)q2p;
1506 register int tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1511 /* If qtys are equally good, sort by qty number,
1512 so that the results of qsort leave nothing to chance. */
1516 /* Compare two quantities' priority for getting real registers. This version
1517 is called for quantities that have suggested hard registers. First priority
1518 goes to quantities that have copy preferences, then to those that have
1519 normal preferences. Within those groups, quantities with the lower
1520 number of preferences have the highest priority. Of those, we use the same
1521 algorithm as above. */
1523 #define QTY_CMP_SUGG(q) \
1524 (qty_phys_num_copy_sugg[q] \
1525 ? qty_phys_num_copy_sugg[q] \
1526 : qty_phys_num_sugg[q] * FIRST_PSEUDO_REGISTER)
1529 qty_sugg_compare (q1, q2)
1532 register int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2);
1537 return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1541 qty_sugg_compare_1 (q1p, q2p)
1545 register int q1 = *(int *)q1p, q2 = *(int *)q2p;
1546 register int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2);
1551 tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1555 /* If qtys are equally good, sort by qty number,
1556 so that the results of qsort leave nothing to chance. */
1563 /* Attempt to combine the two registers (rtx's) USEDREG and SETREG.
1564 Returns 1 if have done so, or 0 if cannot.
1566 Combining registers means marking them as having the same quantity
1567 and adjusting the offsets within the quantity if either of
1570 We don't actually combine a hard reg with a pseudo; instead
1571 we just record the hard reg as the suggestion for the pseudo's quantity.
1572 If we really combined them, we could lose if the pseudo lives
1573 across an insn that clobbers the hard reg (eg, movstr).
1575 ALREADY_DEAD is non-zero if USEDREG is known to be dead even though
1576 there is no REG_DEAD note on INSN. This occurs during the processing
1577 of REG_NO_CONFLICT blocks.
1579 MAY_SAVE_COPYCOPY is non-zero if this insn is simply copying USEDREG to
1580 SETREG or if the input and output must share a register.
1581 In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG.
1583 There are elaborate checks for the validity of combining. */
1587 combine_regs (usedreg, setreg, may_save_copy, insn_number, insn, already_dead)
1588 rtx usedreg, setreg;
1594 register int ureg, sreg;
1595 register int offset = 0;
1599 /* Determine the numbers and sizes of registers being used. If a subreg
1600 is present that does not change the entire register, don't consider
1601 this a copy insn. */
1603 while (GET_CODE (usedreg) == SUBREG)
1605 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (usedreg))) > UNITS_PER_WORD)
1607 offset += SUBREG_WORD (usedreg);
1608 usedreg = SUBREG_REG (usedreg);
1610 if (GET_CODE (usedreg) != REG)
1612 ureg = REGNO (usedreg);
1613 usize = REG_SIZE (usedreg);
1615 while (GET_CODE (setreg) == SUBREG)
1617 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (setreg))) > UNITS_PER_WORD)
1619 offset -= SUBREG_WORD (setreg);
1620 setreg = SUBREG_REG (setreg);
1622 if (GET_CODE (setreg) != REG)
1624 sreg = REGNO (setreg);
1625 ssize = REG_SIZE (setreg);
1627 /* If UREG is a pseudo-register that hasn't already been assigned a
1628 quantity number, it means that it is not local to this block or dies
1629 more than once. In either event, we can't do anything with it. */
1630 if ((ureg >= FIRST_PSEUDO_REGISTER && reg_qty[ureg] < 0)
1631 /* Do not combine registers unless one fits within the other. */
1632 || (offset > 0 && usize + offset > ssize)
1633 || (offset < 0 && usize + offset < ssize)
1634 /* Do not combine with a smaller already-assigned object
1635 if that smaller object is already combined with something bigger. */
1636 || (ssize > usize && ureg >= FIRST_PSEUDO_REGISTER
1637 && usize < qty_size[reg_qty[ureg]])
1638 /* Can't combine if SREG is not a register we can allocate. */
1639 || (sreg >= FIRST_PSEUDO_REGISTER && reg_qty[sreg] == -1)
1640 /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note.
1641 These have already been taken care of. This probably wouldn't
1642 combine anyway, but don't take any chances. */
1643 || (ureg >= FIRST_PSEUDO_REGISTER
1644 && find_reg_note (insn, REG_NO_CONFLICT, usedreg))
1645 /* Don't tie something to itself. In most cases it would make no
1646 difference, but it would screw up if the reg being tied to itself
1647 also dies in this insn. */
1649 /* Don't try to connect two different hardware registers. */
1650 || (ureg < FIRST_PSEUDO_REGISTER && sreg < FIRST_PSEUDO_REGISTER)
1651 /* Don't use a hard reg that might be spilled. */
1652 || (ureg < FIRST_PSEUDO_REGISTER
1653 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (ureg)))
1654 || (sreg < FIRST_PSEUDO_REGISTER
1655 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (sreg)))
1656 /* Don't connect two different machine modes if they have different
1657 implications as to which registers may be used. */
1658 || !MODES_TIEABLE_P (GET_MODE (usedreg), GET_MODE (setreg)))
1661 /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in
1662 qty_phys_sugg for the pseudo instead of tying them.
1664 Return "failure" so that the lifespan of UREG is terminated here;
1665 that way the two lifespans will be disjoint and nothing will prevent
1666 the pseudo reg from being given this hard reg. */
1668 if (ureg < FIRST_PSEUDO_REGISTER)
1670 /* Allocate a quantity number so we have a place to put our
1672 if (reg_qty[sreg] == -2)
1673 reg_is_born (setreg, 2 * insn_number);
1675 if (reg_qty[sreg] >= 0)
1678 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg))
1680 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg);
1681 qty_phys_num_copy_sugg[reg_qty[sreg]]++;
1683 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg))
1685 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg);
1686 qty_phys_num_sugg[reg_qty[sreg]]++;
1692 /* Similarly for SREG a hard register and UREG a pseudo register. */
1694 if (sreg < FIRST_PSEUDO_REGISTER)
1697 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg))
1699 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg);
1700 qty_phys_num_copy_sugg[reg_qty[ureg]]++;
1702 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg))
1704 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg);
1705 qty_phys_num_sugg[reg_qty[ureg]]++;
1710 /* At this point we know that SREG and UREG are both pseudos.
1711 Do nothing if SREG already has a quantity or is a register that we
1713 if (reg_qty[sreg] >= -1
1714 /* If we are not going to let any regs live across calls,
1715 don't tie a call-crossing reg to a non-call-crossing reg. */
1716 || (current_function_has_nonlocal_label
1717 && ((REG_N_CALLS_CROSSED (ureg) > 0)
1718 != (REG_N_CALLS_CROSSED (sreg) > 0))))
1721 /* We don't already know about SREG, so tie it to UREG
1722 if this is the last use of UREG, provided the classes they want
1725 if ((already_dead || find_regno_note (insn, REG_DEAD, ureg))
1726 && reg_meets_class_p (sreg, qty_min_class[reg_qty[ureg]]))
1728 /* Add SREG to UREG's quantity. */
1729 sqty = reg_qty[ureg];
1730 reg_qty[sreg] = sqty;
1731 reg_offset[sreg] = reg_offset[ureg] + offset;
1732 reg_next_in_qty[sreg] = qty_first_reg[sqty];
1733 qty_first_reg[sqty] = sreg;
1735 /* If SREG's reg class is smaller, set qty_min_class[SQTY]. */
1736 update_qty_class (sqty, sreg);
1738 /* Update info about quantity SQTY. */
1739 qty_n_calls_crossed[sqty] += REG_N_CALLS_CROSSED (sreg);
1740 qty_n_refs[sqty] += REG_N_REFS (sreg);
1745 for (i = qty_first_reg[sqty]; i >= 0; i = reg_next_in_qty[i])
1746 reg_offset[i] -= offset;
1748 qty_size[sqty] = ssize;
1749 qty_mode[sqty] = GET_MODE (setreg);
1758 /* Return 1 if the preferred class of REG allows it to be tied
1759 to a quantity or register whose class is CLASS.
1760 True if REG's reg class either contains or is contained in CLASS. */
1763 reg_meets_class_p (reg, class)
1765 enum reg_class class;
1767 register enum reg_class rclass = reg_preferred_class (reg);
1768 return (reg_class_subset_p (rclass, class)
1769 || reg_class_subset_p (class, rclass));
1772 /* Update the class of QTY assuming that REG is being tied to it. */
1775 update_qty_class (qty, reg)
1779 enum reg_class rclass = reg_preferred_class (reg);
1780 if (reg_class_subset_p (rclass, qty_min_class[qty]))
1781 qty_min_class[qty] = rclass;
1783 rclass = reg_alternate_class (reg);
1784 if (reg_class_subset_p (rclass, qty_alternate_class[qty]))
1785 qty_alternate_class[qty] = rclass;
1787 if (REG_CHANGES_SIZE (reg))
1788 qty_changes_size[qty] = 1;
1791 /* Handle something which alters the value of an rtx REG.
1793 REG is whatever is set or clobbered. SETTER is the rtx that
1794 is modifying the register.
1796 If it is not really a register, we do nothing.
1797 The file-global variables `this_insn' and `this_insn_number'
1798 carry info from `block_alloc'. */
1801 reg_is_set (reg, setter)
1805 /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of
1806 a hard register. These may actually not exist any more. */
1808 if (GET_CODE (reg) != SUBREG
1809 && GET_CODE (reg) != REG)
1812 /* Mark this register as being born. If it is used in a CLOBBER, mark
1813 it as being born halfway between the previous insn and this insn so that
1814 it conflicts with our inputs but not the outputs of the previous insn. */
1816 reg_is_born (reg, 2 * this_insn_number - (GET_CODE (setter) == CLOBBER));
1819 /* Handle beginning of the life of register REG.
1820 BIRTH is the index at which this is happening. */
1823 reg_is_born (reg, birth)
1829 if (GET_CODE (reg) == SUBREG)
1830 regno = REGNO (SUBREG_REG (reg)) + SUBREG_WORD (reg);
1832 regno = REGNO (reg);
1834 if (regno < FIRST_PSEUDO_REGISTER)
1836 mark_life (regno, GET_MODE (reg), 1);
1838 /* If the register was to have been born earlier that the present
1839 insn, mark it as live where it is actually born. */
1840 if (birth < 2 * this_insn_number)
1841 post_mark_life (regno, GET_MODE (reg), 1, birth, 2 * this_insn_number);
1845 if (reg_qty[regno] == -2)
1846 alloc_qty (regno, GET_MODE (reg), PSEUDO_REGNO_SIZE (regno), birth);
1848 /* If this register has a quantity number, show that it isn't dead. */
1849 if (reg_qty[regno] >= 0)
1850 qty_death[reg_qty[regno]] = -1;
1854 /* Record the death of REG in the current insn. If OUTPUT_P is non-zero,
1855 REG is an output that is dying (i.e., it is never used), otherwise it
1856 is an input (the normal case).
1857 If OUTPUT_P is 1, then we extend the life past the end of this insn. */
1860 wipe_dead_reg (reg, output_p)
1864 register int regno = REGNO (reg);
1866 /* If this insn has multiple results,
1867 and the dead reg is used in one of the results,
1868 extend its life to after this insn,
1869 so it won't get allocated together with any other result of this insn.
1871 It is unsafe to use !single_set here since it will ignore an unused
1872 output. Just because an output is unused does not mean the compiler
1873 can assume the side effect will not occur. Consider if REG appears
1874 in the address of an output and we reload the output. If we allocate
1875 REG to the same hard register as an unused output we could set the hard
1876 register before the output reload insn. */
1877 if (GET_CODE (PATTERN (this_insn)) == PARALLEL
1878 && multiple_sets (this_insn))
1881 for (i = XVECLEN (PATTERN (this_insn), 0) - 1; i >= 0; i--)
1883 rtx set = XVECEXP (PATTERN (this_insn), 0, i);
1884 if (GET_CODE (set) == SET
1885 && GET_CODE (SET_DEST (set)) != REG
1886 && !rtx_equal_p (reg, SET_DEST (set))
1887 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
1892 /* If this register is used in an auto-increment address, then extend its
1893 life to after this insn, so that it won't get allocated together with
1894 the result of this insn. */
1895 if (! output_p && find_regno_note (this_insn, REG_INC, regno))
1898 if (regno < FIRST_PSEUDO_REGISTER)
1900 mark_life (regno, GET_MODE (reg), 0);
1902 /* If a hard register is dying as an output, mark it as in use at
1903 the beginning of this insn (the above statement would cause this
1906 post_mark_life (regno, GET_MODE (reg), 1,
1907 2 * this_insn_number, 2 * this_insn_number+ 1);
1910 else if (reg_qty[regno] >= 0)
1911 qty_death[reg_qty[regno]] = 2 * this_insn_number + output_p;
1914 /* Find a block of SIZE words of hard regs in reg_class CLASS
1915 that can hold something of machine-mode MODE
1916 (but actually we test only the first of the block for holding MODE)
1917 and still free between insn BORN_INDEX and insn DEAD_INDEX,
1918 and return the number of the first of them.
1919 Return -1 if such a block cannot be found.
1920 If QTY crosses calls, insist on a register preserved by calls,
1921 unless ACCEPT_CALL_CLOBBERED is nonzero.
1923 If JUST_TRY_SUGGESTED is non-zero, only try to see if the suggested
1924 register is available. If not, return -1. */
1927 find_free_reg (class, mode, qty, accept_call_clobbered, just_try_suggested,
1928 born_index, dead_index)
1929 enum reg_class class;
1930 enum machine_mode mode;
1932 int accept_call_clobbered;
1933 int just_try_suggested;
1934 int born_index, dead_index;
1936 register int i, ins;
1938 register /* Declare it register if it's a scalar. */
1940 HARD_REG_SET used, first_used;
1941 #ifdef ELIMINABLE_REGS
1942 static struct {int from, to; } eliminables[] = ELIMINABLE_REGS;
1945 /* Validate our parameters. */
1946 if (born_index < 0 || born_index > dead_index)
1949 /* Don't let a pseudo live in a reg across a function call
1950 if we might get a nonlocal goto. */
1951 if (current_function_has_nonlocal_label
1952 && qty_n_calls_crossed[qty] > 0)
1955 if (accept_call_clobbered)
1956 COPY_HARD_REG_SET (used, call_fixed_reg_set);
1957 else if (qty_n_calls_crossed[qty] == 0)
1958 COPY_HARD_REG_SET (used, fixed_reg_set);
1960 COPY_HARD_REG_SET (used, call_used_reg_set);
1962 if (accept_call_clobbered)
1963 IOR_HARD_REG_SET (used, losing_caller_save_reg_set);
1965 for (ins = born_index; ins < dead_index; ins++)
1966 IOR_HARD_REG_SET (used, regs_live_at[ins]);
1968 IOR_COMPL_HARD_REG_SET (used, reg_class_contents[(int) class]);
1970 /* Don't use the frame pointer reg in local-alloc even if
1971 we may omit the frame pointer, because if we do that and then we
1972 need a frame pointer, reload won't know how to move the pseudo
1973 to another hard reg. It can move only regs made by global-alloc.
1975 This is true of any register that can be eliminated. */
1976 #ifdef ELIMINABLE_REGS
1977 for (i = 0; i < (int)(sizeof eliminables / sizeof eliminables[0]); i++)
1978 SET_HARD_REG_BIT (used, eliminables[i].from);
1979 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
1980 /* If FRAME_POINTER_REGNUM is not a real register, then protect the one
1981 that it might be eliminated into. */
1982 SET_HARD_REG_BIT (used, HARD_FRAME_POINTER_REGNUM);
1985 SET_HARD_REG_BIT (used, FRAME_POINTER_REGNUM);
1988 #ifdef CLASS_CANNOT_CHANGE_SIZE
1989 if (qty_changes_size[qty])
1990 IOR_HARD_REG_SET (used,
1991 reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE]);
1994 /* Normally, the registers that can be used for the first register in
1995 a multi-register quantity are the same as those that can be used for
1996 subsequent registers. However, if just trying suggested registers,
1997 restrict our consideration to them. If there are copy-suggested
1998 register, try them. Otherwise, try the arithmetic-suggested
2000 COPY_HARD_REG_SET (first_used, used);
2002 if (just_try_suggested)
2004 if (qty_phys_num_copy_sugg[qty] != 0)
2005 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_copy_sugg[qty]);
2007 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_sugg[qty]);
2010 /* If all registers are excluded, we can't do anything. */
2011 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) ALL_REGS], first_used, fail);
2013 /* If at least one would be suitable, test each hard reg. */
2015 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2017 #ifdef REG_ALLOC_ORDER
2018 int regno = reg_alloc_order[i];
2022 if (! TEST_HARD_REG_BIT (first_used, regno)
2023 && HARD_REGNO_MODE_OK (regno, mode)
2024 && (qty_n_calls_crossed[qty] == 0
2025 || accept_call_clobbered
2026 || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)))
2029 register int size1 = HARD_REGNO_NREGS (regno, mode);
2030 for (j = 1; j < size1 && ! TEST_HARD_REG_BIT (used, regno + j); j++);
2033 /* Mark that this register is in use between its birth and death
2035 post_mark_life (regno, mode, 1, born_index, dead_index);
2038 #ifndef REG_ALLOC_ORDER
2039 i += j; /* Skip starting points we know will lose */
2046 /* If we are just trying suggested register, we have just tried copy-
2047 suggested registers, and there are arithmetic-suggested registers,
2050 /* If it would be profitable to allocate a call-clobbered register
2051 and save and restore it around calls, do that. */
2052 if (just_try_suggested && qty_phys_num_copy_sugg[qty] != 0
2053 && qty_phys_num_sugg[qty] != 0)
2055 /* Don't try the copy-suggested regs again. */
2056 qty_phys_num_copy_sugg[qty] = 0;
2057 return find_free_reg (class, mode, qty, accept_call_clobbered, 1,
2058 born_index, dead_index);
2061 /* We need not check to see if the current function has nonlocal
2062 labels because we don't put any pseudos that are live over calls in
2063 registers in that case. */
2065 if (! accept_call_clobbered
2066 && flag_caller_saves
2067 && ! just_try_suggested
2068 && qty_n_calls_crossed[qty] != 0
2069 && CALLER_SAVE_PROFITABLE (qty_n_refs[qty], qty_n_calls_crossed[qty]))
2071 i = find_free_reg (class, mode, qty, 1, 0, born_index, dead_index);
2073 caller_save_needed = 1;
2079 /* Mark that REGNO with machine-mode MODE is live starting from the current
2080 insn (if LIFE is non-zero) or dead starting at the current insn (if LIFE
2084 mark_life (regno, mode, life)
2086 enum machine_mode mode;
2089 register int j = HARD_REGNO_NREGS (regno, mode);
2092 SET_HARD_REG_BIT (regs_live, regno + j);
2095 CLEAR_HARD_REG_BIT (regs_live, regno + j);
2098 /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE
2099 is non-zero) or dead (if LIFE is zero) from insn number BIRTH (inclusive)
2100 to insn number DEATH (exclusive). */
2103 post_mark_life (regno, mode, life, birth, death)
2105 enum machine_mode mode;
2106 int life, birth, death;
2108 register int j = HARD_REGNO_NREGS (regno, mode);
2110 register /* Declare it register if it's a scalar. */
2112 HARD_REG_SET this_reg;
2114 CLEAR_HARD_REG_SET (this_reg);
2116 SET_HARD_REG_BIT (this_reg, regno + j);
2119 while (birth < death)
2121 IOR_HARD_REG_SET (regs_live_at[birth], this_reg);
2125 while (birth < death)
2127 AND_COMPL_HARD_REG_SET (regs_live_at[birth], this_reg);
2132 /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0
2133 is the register being clobbered, and R1 is a register being used in
2134 the equivalent expression.
2136 If R1 dies in the block and has a REG_NO_CONFLICT note on every insn
2137 in which it is used, return 1.
2139 Otherwise, return 0. */
2142 no_conflict_p (insn, r0, r1)
2146 rtx note = find_reg_note (insn, REG_LIBCALL, NULL_RTX);
2149 /* If R1 is a hard register, return 0 since we handle this case
2150 when we scan the insns that actually use it. */
2153 || (GET_CODE (r1) == REG && REGNO (r1) < FIRST_PSEUDO_REGISTER)
2154 || (GET_CODE (r1) == SUBREG && GET_CODE (SUBREG_REG (r1)) == REG
2155 && REGNO (SUBREG_REG (r1)) < FIRST_PSEUDO_REGISTER))
2158 last = XEXP (note, 0);
2160 for (p = NEXT_INSN (insn); p && p != last; p = NEXT_INSN (p))
2161 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
2163 if (find_reg_note (p, REG_DEAD, r1))
2166 /* There must be a REG_NO_CONFLICT note on every insn, otherwise
2167 some earlier optimization pass has inserted instructions into
2168 the sequence, and it is not safe to perform this optimization.
2169 Note that emit_no_conflict_block always ensures that this is
2170 true when these sequences are created. */
2171 if (! find_reg_note (p, REG_NO_CONFLICT, r1))
2178 /* Return the number of alternatives for which the constraint string P
2179 indicates that the operand must be equal to operand 0 and that no register
2188 int reg_allowed = 0;
2189 int num_matching_alts = 0;
2194 case '=': case '+': case '?':
2195 case '#': case '&': case '!':
2197 case '1': case '2': case '3': case '4': case '5':
2198 case '6': case '7': case '8': case '9':
2199 case 'm': case '<': case '>': case 'V': case 'o':
2200 case 'E': case 'F': case 'G': case 'H':
2201 case 's': case 'i': case 'n':
2202 case 'I': case 'J': case 'K': case 'L':
2203 case 'M': case 'N': case 'O': case 'P':
2204 #ifdef EXTRA_CONSTRAINT
2205 case 'Q': case 'R': case 'S': case 'T': case 'U':
2208 /* These don't say anything we care about. */
2212 if (found_zero && ! reg_allowed)
2213 num_matching_alts++;
2215 found_zero = reg_allowed = 0;
2229 if (found_zero && ! reg_allowed)
2230 num_matching_alts++;
2232 return num_matching_alts;
2236 dump_local_alloc (file)
2240 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
2241 if (reg_renumber[i] != -1)
2242 fprintf (file, ";; Register %d in %d.\n", i, reg_renumber[i]);