1 /* Allocate registers within a basic block, for GNU compiler.
2 Copyright (C) 1987, 1988, 1991, 1993, 1994 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21 /* Allocation of hard register numbers to pseudo registers is done in
22 two passes. In this pass we consider only regs that are born and
23 die once within one basic block. We do this one basic block at a
24 time. Then the next pass allocates the registers that remain.
25 Two passes are used because this pass uses methods that work only
26 on linear code, but that do a better job than the general methods
27 used in global_alloc, and more quickly too.
29 The assignments made are recorded in the vector reg_renumber
30 whose space is allocated here. The rtl code itself is not altered.
32 We assign each instruction in the basic block a number
33 which is its order from the beginning of the block.
34 Then we can represent the lifetime of a pseudo register with
35 a pair of numbers, and check for conflicts easily.
36 We can record the availability of hard registers with a
37 HARD_REG_SET for each instruction. The HARD_REG_SET
38 contains 0 or 1 for each hard reg.
40 To avoid register shuffling, we tie registers together when one
41 dies by being copied into another, or dies in an instruction that
42 does arithmetic to produce another. The tied registers are
43 allocated as one. Registers with different reg class preferences
44 can never be tied unless the class preferred by one is a subclass
45 of the one preferred by the other.
47 Tying is represented with "quantity numbers".
48 A non-tied register is given a new quantity number.
49 Tied registers have the same quantity number.
51 We have provision to exempt registers, even when they are contained
52 within the block, that can be tied to others that are not contained in it.
53 This is so that global_alloc could process them both and tie them then.
54 But this is currently disabled since tying in global_alloc is not
61 #include "basic-block.h"
63 #include "hard-reg-set.h"
64 #include "insn-config.h"
68 /* Pseudos allocated here cannot be reallocated by global.c if the hard
69 register is used as a spill register. So we don't allocate such pseudos
70 here if their preferred class is likely to be used by spills.
72 On most machines, the appropriate test is if the class has one
73 register, so we default to that. */
75 #ifndef CLASS_LIKELY_SPILLED_P
76 #define CLASS_LIKELY_SPILLED_P(CLASS) (reg_class_size[(int) (CLASS)] == 1)
79 /* Next quantity number available for allocation. */
83 /* In all the following vectors indexed by quantity number. */
85 /* Element Q is the hard reg number chosen for quantity Q,
86 or -1 if none was found. */
88 static short *qty_phys_reg;
90 /* We maintain two hard register sets that indicate suggested hard registers
91 for each quantity. The first, qty_phys_copy_sugg, contains hard registers
92 that are tied to the quantity by a simple copy. The second contains all
93 hard registers that are tied to the quantity via an arithmetic operation.
95 The former register set is given priority for allocation. This tends to
96 eliminate copy insns. */
98 /* Element Q is a set of hard registers that are suggested for quantity Q by
101 static HARD_REG_SET *qty_phys_copy_sugg;
103 /* Element Q is a set of hard registers that are suggested for quantity Q by
106 static HARD_REG_SET *qty_phys_sugg;
108 /* Element Q is the number of suggested registers in qty_phys_copy_sugg. */
110 static short *qty_phys_num_copy_sugg;
112 /* Element Q is the number of suggested registers in qty_phys_sugg. */
114 static short *qty_phys_num_sugg;
116 /* Element Q is the number of refs to quantity Q. */
118 static int *qty_n_refs;
120 /* Element Q is a reg class contained in (smaller than) the
121 preferred classes of all the pseudo regs that are tied in quantity Q.
122 This is the preferred class for allocating that quantity. */
124 static enum reg_class *qty_min_class;
126 /* Insn number (counting from head of basic block)
127 where quantity Q was born. -1 if birth has not been recorded. */
129 static int *qty_birth;
131 /* Insn number (counting from head of basic block)
132 where quantity Q died. Due to the way tying is done,
133 and the fact that we consider in this pass only regs that die but once,
134 a quantity can die only once. Each quantity's life span
135 is a set of consecutive insns. -1 if death has not been recorded. */
137 static int *qty_death;
139 /* Number of words needed to hold the data in quantity Q.
140 This depends on its machine mode. It is used for these purposes:
141 1. It is used in computing the relative importances of qtys,
142 which determines the order in which we look for regs for them.
143 2. It is used in rules that prevent tying several registers of
144 different sizes in a way that is geometrically impossible
145 (see combine_regs). */
147 static int *qty_size;
149 /* This holds the mode of the registers that are tied to qty Q,
150 or VOIDmode if registers with differing modes are tied together. */
152 static enum machine_mode *qty_mode;
154 /* Number of times a reg tied to qty Q lives across a CALL_INSN. */
156 static int *qty_n_calls_crossed;
158 /* Register class within which we allocate qty Q if we can't get
159 its preferred class. */
161 static enum reg_class *qty_alternate_class;
163 /* Element Q is the SCRATCH expression for which this quantity is being
164 allocated or 0 if this quantity is allocating registers. */
166 static rtx *qty_scratch_rtx;
168 /* Element Q is the register number of one pseudo register whose
169 reg_qty value is Q, or -1 is this quantity is for a SCRATCH. This
170 register should be the head of the chain maintained in reg_next_in_qty. */
172 static int *qty_first_reg;
174 /* If (REG N) has been assigned a quantity number, is a register number
175 of another register assigned the same quantity number, or -1 for the
176 end of the chain. qty_first_reg point to the head of this chain. */
178 static int *reg_next_in_qty;
180 /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg
182 of -1 if this register cannot be allocated by local-alloc,
183 or -2 if not known yet.
185 Note that if we see a use or death of pseudo register N with
186 reg_qty[N] == -2, register N must be local to the current block. If
187 it were used in more than one block, we would have reg_qty[N] == -1.
188 This relies on the fact that if reg_basic_block[N] is >= 0, register N
189 will not appear in any other block. We save a considerable number of
190 tests by exploiting this.
192 If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not
197 /* The offset (in words) of register N within its quantity.
198 This can be nonzero if register N is SImode, and has been tied
199 to a subreg of a DImode register. */
201 static char *reg_offset;
203 /* Vector of substitutions of register numbers,
204 used to map pseudo regs into hardware regs.
205 This is set up as a result of register allocation.
206 Element N is the hard reg assigned to pseudo reg N,
207 or is -1 if no hard reg was assigned.
208 If N is a hard reg number, element N is N. */
212 /* Set of hard registers live at the current point in the scan
213 of the instructions in a basic block. */
215 static HARD_REG_SET regs_live;
217 /* Each set of hard registers indicates registers live at a particular
218 point in the basic block. For N even, regs_live_at[N] says which
219 hard registers are needed *after* insn N/2 (i.e., they may not
220 conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1.
222 If an object is to conflict with the inputs of insn J but not the
223 outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly,
224 if it is to conflict with the outputs of insn J but not the inputs of
225 insn J + 1, it is said to die at index J*2 + 1. */
227 static HARD_REG_SET *regs_live_at;
231 int scratch_list_length;
232 static int scratch_index;
234 /* Communicate local vars `insn_number' and `insn'
235 from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */
236 static int this_insn_number;
237 static rtx this_insn;
239 static void alloc_qty PROTO((int, enum machine_mode, int, int));
240 static void alloc_qty_for_scratch PROTO((rtx, int, rtx, int, int));
241 static void validate_equiv_mem_from_store PROTO((rtx, rtx));
242 static int validate_equiv_mem PROTO((rtx, rtx, rtx));
243 static int memref_referenced_p PROTO((rtx, rtx));
244 static int memref_used_between_p PROTO((rtx, rtx, rtx));
245 static void optimize_reg_copy_1 PROTO((rtx, rtx, rtx));
246 static void optimize_reg_copy_2 PROTO((rtx, rtx, rtx));
247 static void update_equiv_regs PROTO((void));
248 static void block_alloc PROTO((int));
249 static int qty_sugg_compare PROTO((int, int));
250 static int qty_sugg_compare_1 PROTO((int *, int *));
251 static int qty_compare PROTO((int, int));
252 static int qty_compare_1 PROTO((int *, int *));
253 static int combine_regs PROTO((rtx, rtx, int, int, rtx, int));
254 static int reg_meets_class_p PROTO((int, enum reg_class));
255 static int reg_classes_overlap_p PROTO((enum reg_class, enum reg_class,
257 static void update_qty_class PROTO((int, int));
258 static void reg_is_set PROTO((rtx, rtx));
259 static void reg_is_born PROTO((rtx, int));
260 static void wipe_dead_reg PROTO((rtx, int));
261 static int find_free_reg PROTO((enum reg_class, enum machine_mode,
262 int, int, int, int, int));
263 static void mark_life PROTO((int, enum machine_mode, int));
264 static void post_mark_life PROTO((int, enum machine_mode, int, int, int));
265 static int no_conflict_p PROTO((rtx, rtx, rtx));
266 static int requires_inout PROTO((char *));
268 /* Allocate a new quantity (new within current basic block)
269 for register number REGNO which is born at index BIRTH
270 within the block. MODE and SIZE are info on reg REGNO. */
273 alloc_qty (regno, mode, size, birth)
275 enum machine_mode mode;
278 register int qty = next_qty++;
280 reg_qty[regno] = qty;
281 reg_offset[regno] = 0;
282 reg_next_in_qty[regno] = -1;
284 qty_first_reg[qty] = regno;
285 qty_size[qty] = size;
286 qty_mode[qty] = mode;
287 qty_birth[qty] = birth;
288 qty_n_calls_crossed[qty] = reg_n_calls_crossed[regno];
289 qty_min_class[qty] = reg_preferred_class (regno);
290 qty_alternate_class[qty] = reg_alternate_class (regno);
291 qty_n_refs[qty] = reg_n_refs[regno];
294 /* Similar to `alloc_qty', but allocates a quantity for a SCRATCH rtx
295 used as operand N in INSN. We assume here that the SCRATCH is used in
299 alloc_qty_for_scratch (scratch, n, insn, insn_code_num, insn_number)
303 int insn_code_num, insn_number;
306 enum reg_class class;
310 #ifdef REGISTER_CONSTRAINTS
311 /* If we haven't yet computed which alternative will be used, do so now.
312 Then set P to the constraints for that alternative. */
313 if (which_alternative == -1)
314 if (! constrain_operands (insn_code_num, 0))
317 for (p = insn_operand_constraint[insn_code_num][n], i = 0;
318 *p && i < which_alternative; p++)
322 /* Compute the class required for this SCRATCH. If we don't need a
323 register, the class will remain NO_REGS. If we guessed the alternative
324 number incorrectly, reload will fix things up for us. */
327 while ((c = *p++) != '\0' && c != ',')
330 case '=': case '+': case '?':
331 case '#': case '&': case '!':
333 case '0': case '1': case '2': case '3': case '4':
334 case 'm': case '<': case '>': case 'V': case 'o':
335 case 'E': case 'F': case 'G': case 'H':
336 case 's': case 'i': case 'n':
337 case 'I': case 'J': case 'K': case 'L':
338 case 'M': case 'N': case 'O': case 'P':
339 #ifdef EXTRA_CONSTRAINT
340 case 'Q': case 'R': case 'S': case 'T': case 'U':
343 /* These don't say anything we care about. */
347 /* We don't need to allocate this SCRATCH. */
351 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
356 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER (c)];
360 if (class == NO_REGS)
363 #else /* REGISTER_CONSTRAINTS */
365 class = GENERAL_REGS;
371 qty_first_reg[qty] = -1;
372 qty_scratch_rtx[qty] = scratch;
373 qty_size[qty] = GET_MODE_SIZE (GET_MODE (scratch));
374 qty_mode[qty] = GET_MODE (scratch);
375 qty_birth[qty] = 2 * insn_number - 1;
376 qty_death[qty] = 2 * insn_number + 1;
377 qty_n_calls_crossed[qty] = 0;
378 qty_min_class[qty] = class;
379 qty_alternate_class[qty] = NO_REGS;
383 /* Main entry point of this file. */
391 /* Leaf functions and non-leaf functions have different needs.
392 If defined, let the machine say what kind of ordering we
394 #ifdef ORDER_REGS_FOR_LOCAL_ALLOC
395 ORDER_REGS_FOR_LOCAL_ALLOC;
398 /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected
400 update_equiv_regs ();
402 /* This sets the maximum number of quantities we can have. Quantity
403 numbers start at zero and we can have one for each pseudo plus the
404 number of SCRATCHes in the largest block, in the worst case. */
405 max_qty = (max_regno - FIRST_PSEUDO_REGISTER) + max_scratch;
407 /* Allocate vectors of temporary data.
408 See the declarations of these variables, above,
409 for what they mean. */
411 /* There can be up to MAX_SCRATCH * N_BASIC_BLOCKS SCRATCHes to allocate.
412 Instead of allocating this much memory from now until the end of
413 reload, only allocate space for MAX_QTY SCRATCHes. If there are more
414 reload will allocate them. */
416 scratch_list_length = max_qty;
417 scratch_list = (rtx *) xmalloc (scratch_list_length * sizeof (rtx));
418 bzero ((char *) scratch_list, scratch_list_length * sizeof (rtx));
419 scratch_block = (int *) xmalloc (scratch_list_length * sizeof (int));
420 bzero ((char *) scratch_block, scratch_list_length * sizeof (int));
423 qty_phys_reg = (short *) alloca (max_qty * sizeof (short));
425 = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET));
426 qty_phys_num_copy_sugg = (short *) alloca (max_qty * sizeof (short));
427 qty_phys_sugg = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET));
428 qty_phys_num_sugg = (short *) alloca (max_qty * sizeof (short));
429 qty_birth = (int *) alloca (max_qty * sizeof (int));
430 qty_death = (int *) alloca (max_qty * sizeof (int));
431 qty_scratch_rtx = (rtx *) alloca (max_qty * sizeof (rtx));
432 qty_first_reg = (int *) alloca (max_qty * sizeof (int));
433 qty_size = (int *) alloca (max_qty * sizeof (int));
435 = (enum machine_mode *) alloca (max_qty * sizeof (enum machine_mode));
436 qty_n_calls_crossed = (int *) alloca (max_qty * sizeof (int));
438 = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class));
440 = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class));
441 qty_n_refs = (int *) alloca (max_qty * sizeof (int));
443 reg_qty = (int *) alloca (max_regno * sizeof (int));
444 reg_offset = (char *) alloca (max_regno * sizeof (char));
445 reg_next_in_qty = (int *) alloca (max_regno * sizeof (int));
447 reg_renumber = (short *) oballoc (max_regno * sizeof (short));
448 for (i = 0; i < max_regno; i++)
449 reg_renumber[i] = -1;
451 /* Determine which pseudo-registers can be allocated by local-alloc.
452 In general, these are the registers used only in a single block and
453 which only die once. However, if a register's preferred class has only
454 a few entries, don't allocate this register here unless it is preferred
455 or nothing since retry_global_alloc won't be able to move it to
456 GENERAL_REGS if a reload register of this class is needed.
458 We need not be concerned with which block actually uses the register
459 since we will never see it outside that block. */
461 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
463 if (reg_basic_block[i] >= 0 && reg_n_deaths[i] == 1
464 && (reg_alternate_class (i) == NO_REGS
465 || ! CLASS_LIKELY_SPILLED_P (reg_preferred_class (i))))
471 /* Force loop below to initialize entire quantity array. */
474 /* Allocate each block's local registers, block by block. */
476 for (b = 0; b < n_basic_blocks; b++)
478 /* NEXT_QTY indicates which elements of the `qty_...'
479 vectors might need to be initialized because they were used
480 for the previous block; it is set to the entire array before
481 block 0. Initialize those, with explicit loop if there are few,
482 else with bzero and bcopy. Do not initialize vectors that are
483 explicit set by `alloc_qty'. */
487 for (i = 0; i < next_qty; i++)
489 qty_scratch_rtx[i] = 0;
490 CLEAR_HARD_REG_SET (qty_phys_copy_sugg[i]);
491 qty_phys_num_copy_sugg[i] = 0;
492 CLEAR_HARD_REG_SET (qty_phys_sugg[i]);
493 qty_phys_num_sugg[i] = 0;
498 #define CLEAR(vector) \
499 bzero ((char *) (vector), (sizeof (*(vector))) * next_qty);
501 CLEAR (qty_scratch_rtx);
502 CLEAR (qty_phys_copy_sugg);
503 CLEAR (qty_phys_num_copy_sugg);
504 CLEAR (qty_phys_sugg);
505 CLEAR (qty_phys_num_sugg);
517 /* Depth of loops we are in while in update_equiv_regs. */
518 static int loop_depth;
520 /* Used for communication between the following two functions: contains
521 a MEM that we wish to ensure remains unchanged. */
522 static rtx equiv_mem;
524 /* Set nonzero if EQUIV_MEM is modified. */
525 static int equiv_mem_modified;
527 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
528 Called via note_stores. */
531 validate_equiv_mem_from_store (dest, set)
535 if ((GET_CODE (dest) == REG
536 && reg_overlap_mentioned_p (dest, equiv_mem))
537 || (GET_CODE (dest) == MEM
538 && true_dependence (dest, equiv_mem)))
539 equiv_mem_modified = 1;
542 /* Verify that no store between START and the death of REG invalidates
543 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
544 by storing into an overlapping memory location, or with a non-const
547 Return 1 if MEMREF remains valid. */
550 validate_equiv_mem (start, reg, memref)
559 equiv_mem_modified = 0;
561 /* If the memory reference has side effects or is volatile, it isn't a
562 valid equivalence. */
563 if (side_effects_p (memref))
566 for (insn = start; insn && ! equiv_mem_modified; insn = NEXT_INSN (insn))
568 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
571 if (find_reg_note (insn, REG_DEAD, reg))
574 if (GET_CODE (insn) == CALL_INSN && ! RTX_UNCHANGING_P (memref)
575 && ! CONST_CALL_P (insn))
578 note_stores (PATTERN (insn), validate_equiv_mem_from_store);
580 /* If a register mentioned in MEMREF is modified via an
581 auto-increment, we lose the equivalence. Do the same if one
582 dies; although we could extend the life, it doesn't seem worth
585 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
586 if ((REG_NOTE_KIND (note) == REG_INC
587 || REG_NOTE_KIND (note) == REG_DEAD)
588 && GET_CODE (XEXP (note, 0)) == REG
589 && reg_overlap_mentioned_p (XEXP (note, 0), memref))
596 /* TRUE if X references a memory location that would be affected by a store
600 memref_referenced_p (memref, x)
606 enum rtx_code code = GET_CODE (x);
623 if (true_dependence (memref, x))
628 /* If we are setting a MEM, it doesn't count (its address does), but any
629 other SET_DEST that has a MEM in it is referencing the MEM. */
630 if (GET_CODE (SET_DEST (x)) == MEM)
632 if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0)))
635 else if (memref_referenced_p (memref, SET_DEST (x)))
638 return memref_referenced_p (memref, SET_SRC (x));
641 fmt = GET_RTX_FORMAT (code);
642 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
646 if (memref_referenced_p (memref, XEXP (x, i)))
650 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
651 if (memref_referenced_p (memref, XVECEXP (x, i, j)))
659 /* TRUE if some insn in the range (START, END] references a memory location
660 that would be affected by a store to MEMREF. */
663 memref_used_between_p (memref, start, end)
670 for (insn = NEXT_INSN (start); insn != NEXT_INSN (end);
671 insn = NEXT_INSN (insn))
672 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
673 && memref_referenced_p (memref, PATTERN (insn)))
679 /* INSN is a copy from SRC to DEST, both registers, and SRC does not die
682 Search forward to see if SRC dies before either it or DEST is modified,
683 but don't scan past the end of a basic block. If so, we can replace SRC
684 with DEST and let SRC die in INSN.
686 This will reduce the number of registers live in that range and may enable
687 DEST to be tied to SRC, thus often saving one register in addition to a
688 register-register copy. */
691 optimize_reg_copy_1 (insn, dest, src)
699 int sregno = REGNO (src);
700 int dregno = REGNO (dest);
703 #ifdef SMALL_REGISTER_CLASSES
704 /* We don't want to mess with hard regs if register classes are small. */
705 || sregno < FIRST_PSEUDO_REGISTER || dregno < FIRST_PSEUDO_REGISTER
707 /* We don't see all updates to SP if they are in an auto-inc memory
708 reference, so we must disallow this optimization on them. */
709 || sregno == STACK_POINTER_REGNUM || dregno == STACK_POINTER_REGNUM)
712 for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p))
714 if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN
715 || (GET_CODE (p) == NOTE
716 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG
717 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END)))
720 if (GET_RTX_CLASS (GET_CODE (p)) != 'i')
723 if (reg_set_p (src, p) || reg_set_p (dest, p)
724 /* Don't change a USE of a register. */
725 || (GET_CODE (PATTERN (p)) == USE
726 && reg_overlap_mentioned_p (src, XEXP (PATTERN (p), 0))))
729 /* See if all of SRC dies in P. This test is slightly more
730 conservative than it needs to be. */
731 if ((note = find_regno_note (p, REG_DEAD, sregno)) != 0
732 && GET_MODE (XEXP (note, 0)) == GET_MODE (src))
740 /* We can do the optimization. Scan forward from INSN again,
741 replacing regs as we go. Set FAILED if a replacement can't
742 be done. In that case, we can't move the death note for SRC.
743 This should be rare. */
745 /* Set to stop at next insn. */
746 for (q = next_real_insn (insn);
747 q != next_real_insn (p);
748 q = next_real_insn (q))
750 if (reg_overlap_mentioned_p (src, PATTERN (q)))
752 /* If SRC is a hard register, we might miss some
753 overlapping registers with validate_replace_rtx,
754 so we would have to undo it. We can't if DEST is
755 present in the insn, so fail in that combination
757 if (sregno < FIRST_PSEUDO_REGISTER
758 && reg_mentioned_p (dest, PATTERN (q)))
761 /* Replace all uses and make sure that the register
762 isn't still present. */
763 else if (validate_replace_rtx (src, dest, q)
764 && (sregno >= FIRST_PSEUDO_REGISTER
765 || ! reg_overlap_mentioned_p (src,
768 /* We assume that a register is used exactly once per
769 insn in the updates below. If this is not correct,
770 no great harm is done. */
771 if (sregno >= FIRST_PSEUDO_REGISTER)
772 reg_n_refs[sregno] -= loop_depth;
773 if (dregno >= FIRST_PSEUDO_REGISTER)
774 reg_n_refs[dregno] += loop_depth;
778 validate_replace_rtx (dest, src, q);
783 /* Count the insns and CALL_INSNs passed. If we passed the
784 death note of DEST, show increased live length. */
789 /* If the insn in which SRC dies is a CALL_INSN, don't count it
790 as a call that has been crossed. Otherwise, count it. */
791 if (q != p && GET_CODE (q) == CALL_INSN)
798 /* If DEST dies here, remove the death note and save it for
799 later. Make sure ALL of DEST dies here; again, this is
800 overly conservative. */
802 && (dest_death = find_regno_note (q, REG_DEAD, dregno)) != 0
803 && GET_MODE (XEXP (dest_death, 0)) == GET_MODE (dest))
804 remove_note (q, dest_death);
809 if (sregno >= FIRST_PSEUDO_REGISTER)
811 reg_live_length[sregno] -= length;
812 /* reg_live_length is only an approximation after combine
813 if sched is not run, so make sure that we still have
814 a reasonable value. */
815 if (reg_live_length[sregno] < 2)
816 reg_live_length[sregno] = 2;
817 reg_n_calls_crossed[sregno] -= n_calls;
820 if (dregno >= FIRST_PSEUDO_REGISTER)
822 reg_live_length[dregno] += d_length;
823 reg_n_calls_crossed[dregno] += d_n_calls;
826 /* Move death note of SRC from P to INSN. */
827 remove_note (p, note);
828 XEXP (note, 1) = REG_NOTES (insn);
829 REG_NOTES (insn) = note;
832 /* Put death note of DEST on P if we saw it die. */
835 XEXP (dest_death, 1) = REG_NOTES (p);
836 REG_NOTES (p) = dest_death;
842 /* If SRC is a hard register which is set or killed in some other
843 way, we can't do this optimization. */
844 else if (sregno < FIRST_PSEUDO_REGISTER
845 && dead_or_set_p (p, src))
850 /* INSN is a copy of SRC to DEST, in which SRC dies. See if we now have
851 a sequence of insns that modify DEST followed by an insn that sets
852 SRC to DEST in which DEST dies, with no prior modification of DEST.
853 (There is no need to check if the insns in between actually modify
854 DEST. We should not have cases where DEST is not modified, but
855 the optimization is safe if no such modification is detected.)
856 In that case, we can replace all uses of DEST, starting with INSN and
857 ending with the set of SRC to DEST, with SRC. We do not do this
858 optimization if a CALL_INSN is crossed unless SRC already crosses a
861 It is assumed that DEST and SRC are pseudos; it is too complicated to do
862 this for hard registers since the substitutions we may make might fail. */
865 optimize_reg_copy_2 (insn, dest, src)
872 int sregno = REGNO (src);
873 int dregno = REGNO (dest);
875 for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p))
877 if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN
878 || (GET_CODE (p) == NOTE
879 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG
880 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END)))
883 if (GET_RTX_CLASS (GET_CODE (p)) != 'i')
886 set = single_set (p);
887 if (set && SET_SRC (set) == dest && SET_DEST (set) == src
888 && find_reg_note (p, REG_DEAD, dest))
890 /* We can do the optimization. Scan forward from INSN again,
891 replacing regs as we go. */
893 /* Set to stop at next insn. */
894 for (q = insn; q != NEXT_INSN (p); q = NEXT_INSN (q))
895 if (GET_RTX_CLASS (GET_CODE (q)) == 'i')
897 if (reg_mentioned_p (dest, PATTERN (q)))
899 PATTERN (q) = replace_rtx (PATTERN (q), dest, src);
901 /* We assume that a register is used exactly once per
902 insn in the updates below. If this is not correct,
903 no great harm is done. */
904 reg_n_refs[dregno] -= loop_depth;
905 reg_n_refs[sregno] += loop_depth;
909 if (GET_CODE (q) == CALL_INSN)
911 reg_n_calls_crossed[dregno]--;
912 reg_n_calls_crossed[sregno]++;
916 remove_note (p, find_reg_note (p, REG_DEAD, dest));
917 reg_n_deaths[dregno]--;
918 remove_note (insn, find_reg_note (insn, REG_DEAD, src));
919 reg_n_deaths[sregno]--;
923 if (reg_set_p (src, p)
924 || (GET_CODE (p) == CALL_INSN && reg_n_calls_crossed[sregno] == 0))
929 /* Find registers that are equivalent to a single value throughout the
930 compilation (either because they can be referenced in memory or are set once
931 from a single constant). Lower their priority for a register.
933 If such a register is only referenced once, try substituting its value
934 into the using insn. If it succeeds, we can eliminate the register
940 rtx *reg_equiv_init_insn = (rtx *) alloca (max_regno * sizeof (rtx *));
941 rtx *reg_equiv_replacement = (rtx *) alloca (max_regno * sizeof (rtx *));
944 bzero ((char *) reg_equiv_init_insn, max_regno * sizeof (rtx *));
945 bzero ((char *) reg_equiv_replacement, max_regno * sizeof (rtx *));
947 init_alias_analysis ();
951 /* Scan the insns and find which registers have equivalences. Do this
952 in a separate scan of the insns because (due to -fcse-follow-jumps)
953 a register can be set below its use. */
954 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
957 rtx set = single_set (insn);
961 if (GET_CODE (insn) == NOTE)
963 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
965 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
969 /* If this insn contains more (or less) than a single SET, ignore it. */
973 dest = SET_DEST (set);
975 /* If this sets a MEM to the contents of a REG that is only used
976 in a single basic block, see if the register is always equivalent
977 to that memory location and if moving the store from INSN to the
978 insn that set REG is safe. If so, put a REG_EQUIV note on the
979 initializing insn. */
981 if (GET_CODE (dest) == MEM && GET_CODE (SET_SRC (set)) == REG
982 && (regno = REGNO (SET_SRC (set))) >= FIRST_PSEUDO_REGISTER
983 && reg_basic_block[regno] >= 0
984 && reg_equiv_init_insn[regno] != 0
985 && validate_equiv_mem (reg_equiv_init_insn[regno], SET_SRC (set),
987 && ! memref_used_between_p (SET_DEST (set),
988 reg_equiv_init_insn[regno], insn))
989 REG_NOTES (reg_equiv_init_insn[regno])
990 = gen_rtx (EXPR_LIST, REG_EQUIV, dest,
991 REG_NOTES (reg_equiv_init_insn[regno]));
993 /* If this is a register-register copy where SRC is not dead, see if we
995 if (flag_expensive_optimizations && GET_CODE (dest) == REG
996 && GET_CODE (SET_SRC (set)) == REG
997 && ! find_reg_note (insn, REG_DEAD, SET_SRC (set)))
998 optimize_reg_copy_1 (insn, dest, SET_SRC (set));
1000 /* Similarly for a pseudo-pseudo copy when SRC is dead. */
1001 else if (flag_expensive_optimizations && GET_CODE (dest) == REG
1002 && REGNO (dest) >= FIRST_PSEUDO_REGISTER
1003 && GET_CODE (SET_SRC (set)) == REG
1004 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER
1005 && find_reg_note (insn, REG_DEAD, SET_SRC (set)))
1006 optimize_reg_copy_2 (insn, dest, SET_SRC (set));
1008 /* Otherwise, we only handle the case of a pseudo register being set
1010 if (GET_CODE (dest) != REG
1011 || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER
1012 || reg_n_sets[regno] != 1)
1015 note = find_reg_note (insn, REG_EQUAL, NULL_RTX);
1017 /* Record this insn as initializing this register. */
1018 reg_equiv_init_insn[regno] = insn;
1020 /* If this register is known to be equal to a constant, record that
1021 it is always equivalent to the constant. */
1022 if (note && CONSTANT_P (XEXP (note, 0)))
1023 PUT_MODE (note, (enum machine_mode) REG_EQUIV);
1025 /* If this insn introduces a "constant" register, decrease the priority
1026 of that register. Record this insn if the register is only used once
1027 more and the equivalence value is the same as our source.
1029 The latter condition is checked for two reasons: First, it is an
1030 indication that it may be more efficient to actually emit the insn
1031 as written (if no registers are available, reload will substitute
1032 the equivalence). Secondly, it avoids problems with any registers
1033 dying in this insn whose death notes would be missed.
1035 If we don't have a REG_EQUIV note, see if this insn is loading
1036 a register used only in one basic block from a MEM. If so, and the
1037 MEM remains unchanged for the life of the register, add a REG_EQUIV
1040 note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
1042 if (note == 0 && reg_basic_block[regno] >= 0
1043 && GET_CODE (SET_SRC (set)) == MEM
1044 && validate_equiv_mem (insn, dest, SET_SRC (set)))
1045 REG_NOTES (insn) = note = gen_rtx (EXPR_LIST, REG_EQUIV, SET_SRC (set),
1048 /* Don't mess with things live during setjmp. */
1049 if (note && reg_live_length[regno] >= 0)
1051 int regno = REGNO (dest);
1053 /* Note that the statement below does not affect the priority
1055 reg_live_length[regno] *= 2;
1057 /* If the register is referenced exactly twice, meaning it is set
1058 once and used once, indicate that the reference may be replaced
1059 by the equivalence we computed above. If the register is only
1060 used in one basic block, this can't succeed or combine would
1063 It would be nice to use "loop_depth * 2" in the compare
1064 below. Unfortunately, LOOP_DEPTH need not be constant within
1065 a basic block so this would be too complicated.
1067 This case normally occurs when a parameter is read from memory
1068 and then used exactly once, not in a loop. */
1070 if (reg_n_refs[regno] == 2
1071 && reg_basic_block[regno] < 0
1072 && rtx_equal_p (XEXP (note, 0), SET_SRC (set)))
1073 reg_equiv_replacement[regno] = SET_SRC (set);
1077 /* Now scan all regs killed in an insn to see if any of them are registers
1078 only used that once. If so, see if we can replace the reference with
1079 the equivalent from. If we can, delete the initializing reference
1080 and this register will go away. */
1081 for (insn = next_active_insn (get_insns ());
1083 insn = next_active_insn (insn))
1087 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1088 if (REG_NOTE_KIND (link) == REG_DEAD
1089 /* Make sure this insn still refers to the register. */
1090 && reg_mentioned_p (XEXP (link, 0), PATTERN (insn)))
1092 int regno = REGNO (XEXP (link, 0));
1094 if (reg_equiv_replacement[regno]
1095 && validate_replace_rtx (regno_reg_rtx[regno],
1096 reg_equiv_replacement[regno], insn))
1098 rtx equiv_insn = reg_equiv_init_insn[regno];
1100 remove_death (regno, insn);
1101 reg_n_refs[regno] = 0;
1102 PUT_CODE (equiv_insn, NOTE);
1103 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1104 NOTE_SOURCE_FILE (equiv_insn) = 0;
1110 /* Allocate hard regs to the pseudo regs used only within block number B.
1111 Only the pseudos that die but once can be handled. */
1120 int insn_number = 0;
1122 int max_uid = get_max_uid ();
1124 int no_conflict_combined_regno = -1;
1125 /* Counter to prevent allocating more SCRATCHes than can be stored
1127 int scratches_allocated = scratch_index;
1129 /* Count the instructions in the basic block. */
1131 insn = basic_block_end[b];
1134 if (GET_CODE (insn) != NOTE)
1135 if (++insn_count > max_uid)
1137 if (insn == basic_block_head[b])
1139 insn = PREV_INSN (insn);
1142 /* +2 to leave room for a post_mark_life at the last insn and for
1143 the birth of a CLOBBER in the first insn. */
1144 regs_live_at = (HARD_REG_SET *) alloca ((2 * insn_count + 2)
1145 * sizeof (HARD_REG_SET));
1146 bzero ((char *) regs_live_at, (2 * insn_count + 2) * sizeof (HARD_REG_SET));
1148 /* Initialize table of hardware registers currently live. */
1151 regs_live = *basic_block_live_at_start[b];
1153 COPY_HARD_REG_SET (regs_live, basic_block_live_at_start[b]);
1156 /* This loop scans the instructions of the basic block
1157 and assigns quantities to registers.
1158 It computes which registers to tie. */
1160 insn = basic_block_head[b];
1163 register rtx body = PATTERN (insn);
1165 if (GET_CODE (insn) != NOTE)
1168 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1170 register rtx link, set;
1171 register int win = 0;
1172 register rtx r0, r1;
1173 int combined_regno = -1;
1175 int insn_code_number = recog_memoized (insn);
1177 this_insn_number = insn_number;
1180 if (insn_code_number >= 0)
1181 insn_extract (insn);
1182 which_alternative = -1;
1184 /* Is this insn suitable for tying two registers?
1185 If so, try doing that.
1186 Suitable insns are those with at least two operands and where
1187 operand 0 is an output that is a register that is not
1190 We can tie operand 0 with some operand that dies in this insn.
1191 First look for operands that are required to be in the same
1192 register as operand 0. If we find such, only try tying that
1193 operand or one that can be put into that operand if the
1194 operation is commutative. If we don't find an operand
1195 that is required to be in the same register as operand 0,
1196 we can tie with any operand.
1198 Subregs in place of regs are also ok.
1200 If tying is done, WIN is set nonzero. */
1202 if (insn_code_number >= 0
1203 #ifdef REGISTER_CONSTRAINTS
1204 && insn_n_operands[insn_code_number] > 1
1205 && insn_operand_constraint[insn_code_number][0][0] == '='
1206 && insn_operand_constraint[insn_code_number][0][1] != '&'
1208 && GET_CODE (PATTERN (insn)) == SET
1209 && rtx_equal_p (SET_DEST (PATTERN (insn)), recog_operand[0])
1213 #ifdef REGISTER_CONSTRAINTS
1214 /* If non-negative, is an operand that must match operand 0. */
1215 int must_match_0 = -1;
1216 /* Counts number of alternatives that require a match with
1218 int n_matching_alts = 0;
1220 for (i = 1; i < insn_n_operands[insn_code_number]; i++)
1222 char *p = insn_operand_constraint[insn_code_number][i];
1223 int this_match = (requires_inout (p));
1225 n_matching_alts += this_match;
1226 if (this_match == insn_n_alternatives[insn_code_number])
1231 r0 = recog_operand[0];
1232 for (i = 1; i < insn_n_operands[insn_code_number]; i++)
1234 #ifdef REGISTER_CONSTRAINTS
1235 /* Skip this operand if we found an operand that
1236 must match operand 0 and this operand isn't it
1237 and can't be made to be it by commutativity. */
1239 if (must_match_0 >= 0 && i != must_match_0
1240 && ! (i == must_match_0 + 1
1241 && insn_operand_constraint[insn_code_number][i-1][0] == '%')
1242 && ! (i == must_match_0 - 1
1243 && insn_operand_constraint[insn_code_number][i][0] == '%'))
1246 /* Likewise if each alternative has some operand that
1247 must match operand zero. In that case, skip any
1248 operand that doesn't list operand 0 since we know that
1249 the operand always conflicts with operand 0. We
1250 ignore commutatity in this case to keep things simple. */
1251 if (n_matching_alts == insn_n_alternatives[insn_code_number]
1252 && (0 == requires_inout
1253 (insn_operand_constraint[insn_code_number][i])))
1257 r1 = recog_operand[i];
1259 /* If the operand is an address, find a register in it.
1260 There may be more than one register, but we only try one
1263 #ifdef REGISTER_CONSTRAINTS
1264 insn_operand_constraint[insn_code_number][i][0] == 'p'
1266 insn_operand_address_p[insn_code_number][i]
1269 while (GET_CODE (r1) == PLUS || GET_CODE (r1) == MULT)
1272 if (GET_CODE (r0) == REG || GET_CODE (r0) == SUBREG)
1274 /* We have two priorities for hard register preferences.
1275 If we have a move insn or an insn whose first input
1276 can only be in the same register as the output, give
1277 priority to an equivalence found from that insn. */
1279 = ((SET_DEST (body) == r0 && SET_SRC (body) == r1)
1280 #ifdef REGISTER_CONSTRAINTS
1281 || (r1 == recog_operand[i] && must_match_0 >= 0)
1285 if (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1286 win = combine_regs (r1, r0, may_save_copy,
1287 insn_number, insn, 0);
1292 /* Recognize an insn sequence with an ultimate result
1293 which can safely overlap one of the inputs.
1294 The sequence begins with a CLOBBER of its result,
1295 and ends with an insn that copies the result to itself
1296 and has a REG_EQUAL note for an equivalent formula.
1297 That note indicates what the inputs are.
1298 The result and the input can overlap if each insn in
1299 the sequence either doesn't mention the input
1300 or has a REG_NO_CONFLICT note to inhibit the conflict.
1302 We do the combining test at the CLOBBER so that the
1303 destination register won't have had a quantity number
1304 assigned, since that would prevent combining. */
1306 if (GET_CODE (PATTERN (insn)) == CLOBBER
1307 && (r0 = XEXP (PATTERN (insn), 0),
1308 GET_CODE (r0) == REG)
1309 && (link = find_reg_note (insn, REG_LIBCALL, NULL_RTX)) != 0
1310 && XEXP (link, 0) != 0
1311 && GET_CODE (XEXP (link, 0)) == INSN
1312 && (set = single_set (XEXP (link, 0))) != 0
1313 && SET_DEST (set) == r0 && SET_SRC (set) == r0
1314 && (note = find_reg_note (XEXP (link, 0), REG_EQUAL,
1317 if (r1 = XEXP (note, 0), GET_CODE (r1) == REG
1318 /* Check that we have such a sequence. */
1319 && no_conflict_p (insn, r0, r1))
1320 win = combine_regs (r1, r0, 1, insn_number, insn, 1);
1321 else if (GET_RTX_FORMAT (GET_CODE (XEXP (note, 0)))[0] == 'e'
1322 && (r1 = XEXP (XEXP (note, 0), 0),
1323 GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1324 && no_conflict_p (insn, r0, r1))
1325 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1327 /* Here we care if the operation to be computed is
1329 else if ((GET_CODE (XEXP (note, 0)) == EQ
1330 || GET_CODE (XEXP (note, 0)) == NE
1331 || GET_RTX_CLASS (GET_CODE (XEXP (note, 0))) == 'c')
1332 && (r1 = XEXP (XEXP (note, 0), 1),
1333 (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG))
1334 && no_conflict_p (insn, r0, r1))
1335 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1337 /* If we did combine something, show the register number
1338 in question so that we know to ignore its death. */
1340 no_conflict_combined_regno = REGNO (r1);
1343 /* If registers were just tied, set COMBINED_REGNO
1344 to the number of the register used in this insn
1345 that was tied to the register set in this insn.
1346 This register's qty should not be "killed". */
1350 while (GET_CODE (r1) == SUBREG)
1351 r1 = SUBREG_REG (r1);
1352 combined_regno = REGNO (r1);
1355 /* Mark the death of everything that dies in this instruction,
1356 except for anything that was just combined. */
1358 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1359 if (REG_NOTE_KIND (link) == REG_DEAD
1360 && GET_CODE (XEXP (link, 0)) == REG
1361 && combined_regno != REGNO (XEXP (link, 0))
1362 && (no_conflict_combined_regno != REGNO (XEXP (link, 0))
1363 || ! find_reg_note (insn, REG_NO_CONFLICT, XEXP (link, 0))))
1364 wipe_dead_reg (XEXP (link, 0), 0);
1366 /* Allocate qty numbers for all registers local to this block
1367 that are born (set) in this instruction.
1368 A pseudo that already has a qty is not changed. */
1370 note_stores (PATTERN (insn), reg_is_set);
1372 /* If anything is set in this insn and then unused, mark it as dying
1373 after this insn, so it will conflict with our outputs. This
1374 can't match with something that combined, and it doesn't matter
1375 if it did. Do this after the calls to reg_is_set since these
1376 die after, not during, the current insn. */
1378 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1379 if (REG_NOTE_KIND (link) == REG_UNUSED
1380 && GET_CODE (XEXP (link, 0)) == REG)
1381 wipe_dead_reg (XEXP (link, 0), 1);
1383 /* Allocate quantities for any SCRATCH operands of this insn. */
1385 if (insn_code_number >= 0)
1386 for (i = 0; i < insn_n_operands[insn_code_number]; i++)
1387 if (GET_CODE (recog_operand[i]) == SCRATCH
1388 && scratches_allocated++ < scratch_list_length)
1389 alloc_qty_for_scratch (recog_operand[i], i, insn,
1390 insn_code_number, insn_number);
1392 /* If this is an insn that has a REG_RETVAL note pointing at a
1393 CLOBBER insn, we have reached the end of a REG_NO_CONFLICT
1394 block, so clear any register number that combined within it. */
1395 if ((note = find_reg_note (insn, REG_RETVAL, NULL_RTX)) != 0
1396 && GET_CODE (XEXP (note, 0)) == INSN
1397 && GET_CODE (PATTERN (XEXP (note, 0))) == CLOBBER)
1398 no_conflict_combined_regno = -1;
1401 /* Set the registers live after INSN_NUMBER. Note that we never
1402 record the registers live before the block's first insn, since no
1403 pseudos we care about are live before that insn. */
1405 IOR_HARD_REG_SET (regs_live_at[2 * insn_number], regs_live);
1406 IOR_HARD_REG_SET (regs_live_at[2 * insn_number + 1], regs_live);
1408 if (insn == basic_block_end[b])
1411 insn = NEXT_INSN (insn);
1414 /* Now every register that is local to this basic block
1415 should have been given a quantity, or else -1 meaning ignore it.
1416 Every quantity should have a known birth and death.
1418 Order the qtys so we assign them registers in order of the
1419 number of suggested registers they need so we allocate those with
1420 the most restrictive needs first. */
1422 qty_order = (int *) alloca (next_qty * sizeof (int));
1423 for (i = 0; i < next_qty; i++)
1426 #define EXCHANGE(I1, I2) \
1427 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1432 /* Make qty_order[2] be the one to allocate last. */
1433 if (qty_sugg_compare (0, 1) > 0)
1435 if (qty_sugg_compare (1, 2) > 0)
1438 /* ... Fall through ... */
1440 /* Put the best one to allocate in qty_order[0]. */
1441 if (qty_sugg_compare (0, 1) > 0)
1444 /* ... Fall through ... */
1448 /* Nothing to do here. */
1452 qsort (qty_order, next_qty, sizeof (int), qty_sugg_compare_1);
1455 /* Try to put each quantity in a suggested physical register, if it has one.
1456 This may cause registers to be allocated that otherwise wouldn't be, but
1457 this seems acceptable in local allocation (unlike global allocation). */
1458 for (i = 0; i < next_qty; i++)
1461 if (qty_phys_num_sugg[q] != 0 || qty_phys_num_copy_sugg[q] != 0)
1462 qty_phys_reg[q] = find_free_reg (qty_min_class[q], qty_mode[q], q,
1463 0, 1, qty_birth[q], qty_death[q]);
1465 qty_phys_reg[q] = -1;
1468 /* Order the qtys so we assign them registers in order of
1469 decreasing length of life. Normally call qsort, but if we
1470 have only a very small number of quantities, sort them ourselves. */
1472 for (i = 0; i < next_qty; i++)
1475 #define EXCHANGE(I1, I2) \
1476 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1481 /* Make qty_order[2] be the one to allocate last. */
1482 if (qty_compare (0, 1) > 0)
1484 if (qty_compare (1, 2) > 0)
1487 /* ... Fall through ... */
1489 /* Put the best one to allocate in qty_order[0]. */
1490 if (qty_compare (0, 1) > 0)
1493 /* ... Fall through ... */
1497 /* Nothing to do here. */
1501 qsort (qty_order, next_qty, sizeof (int), qty_compare_1);
1504 /* Now for each qty that is not a hardware register,
1505 look for a hardware register to put it in.
1506 First try the register class that is cheapest for this qty,
1507 if there is more than one class. */
1509 for (i = 0; i < next_qty; i++)
1512 if (qty_phys_reg[q] < 0)
1514 if (N_REG_CLASSES > 1)
1516 qty_phys_reg[q] = find_free_reg (qty_min_class[q],
1517 qty_mode[q], q, 0, 0,
1518 qty_birth[q], qty_death[q]);
1519 if (qty_phys_reg[q] >= 0)
1523 if (qty_alternate_class[q] != NO_REGS)
1524 qty_phys_reg[q] = find_free_reg (qty_alternate_class[q],
1525 qty_mode[q], q, 0, 0,
1526 qty_birth[q], qty_death[q]);
1530 /* Now propagate the register assignments
1531 to the pseudo regs belonging to the qtys. */
1533 for (q = 0; q < next_qty; q++)
1534 if (qty_phys_reg[q] >= 0)
1536 for (i = qty_first_reg[q]; i >= 0; i = reg_next_in_qty[i])
1537 reg_renumber[i] = qty_phys_reg[q] + reg_offset[i];
1538 if (qty_scratch_rtx[q])
1540 if (GET_CODE (qty_scratch_rtx[q]) == REG)
1542 PUT_CODE (qty_scratch_rtx[q], REG);
1543 REGNO (qty_scratch_rtx[q]) = qty_phys_reg[q];
1545 scratch_block[scratch_index] = b;
1546 scratch_list[scratch_index++] = qty_scratch_rtx[q];
1548 /* Must clear the USED field, because it will have been set by
1549 copy_rtx_if_shared, but the leaf_register code expects that
1550 it is zero in all REG rtx. copy_rtx_if_shared does not set the
1551 used bit for REGs, but does for SCRATCHes. */
1552 qty_scratch_rtx[q]->used = 0;
1557 /* Compare two quantities' priority for getting real registers.
1558 We give shorter-lived quantities higher priority.
1559 Quantities with more references are also preferred, as are quantities that
1560 require multiple registers. This is the identical prioritization as
1561 done by global-alloc.
1563 We used to give preference to registers with *longer* lives, but using
1564 the same algorithm in both local- and global-alloc can speed up execution
1565 of some programs by as much as a factor of three! */
1568 qty_compare (q1, q2)
1571 /* Note that the quotient will never be bigger than
1572 the value of floor_log2 times the maximum number of
1573 times a register can occur in one insn (surely less than 100).
1574 Multiplying this by 10000 can't overflow. */
1576 = (((double) (floor_log2 (qty_n_refs[q1]) * qty_n_refs[q1] * qty_size[q1])
1577 / (qty_death[q1] - qty_birth[q1]))
1580 = (((double) (floor_log2 (qty_n_refs[q2]) * qty_n_refs[q2] * qty_size[q2])
1581 / (qty_death[q2] - qty_birth[q2]))
1587 qty_compare_1 (q1, q2)
1592 /* Note that the quotient will never be bigger than
1593 the value of floor_log2 times the maximum number of
1594 times a register can occur in one insn (surely less than 100).
1595 Multiplying this by 10000 can't overflow. */
1597 = (((double) (floor_log2 (qty_n_refs[*q1]) * qty_n_refs[*q1]
1599 / (qty_death[*q1] - qty_birth[*q1]))
1602 = (((double) (floor_log2 (qty_n_refs[*q2]) * qty_n_refs[*q2]
1604 / (qty_death[*q2] - qty_birth[*q2]))
1608 if (tem != 0) return tem;
1609 /* If qtys are equally good, sort by qty number,
1610 so that the results of qsort leave nothing to chance. */
1614 /* Compare two quantities' priority for getting real registers. This version
1615 is called for quantities that have suggested hard registers. First priority
1616 goes to quantities that have copy preferences, then to those that have
1617 normal preferences. Within those groups, quantities with the lower
1618 number of preferenes have the highest priority. Of those, we use the same
1619 algorithm as above. */
1622 qty_sugg_compare (q1, q2)
1625 register int sugg1 = (qty_phys_num_copy_sugg[q1]
1626 ? qty_phys_num_copy_sugg[q1]
1627 : qty_phys_num_sugg[q1] * FIRST_PSEUDO_REGISTER);
1628 register int sugg2 = (qty_phys_num_copy_sugg[q2]
1629 ? qty_phys_num_copy_sugg[q2]
1630 : qty_phys_num_sugg[q2] * FIRST_PSEUDO_REGISTER);
1631 /* Note that the quotient will never be bigger than
1632 the value of floor_log2 times the maximum number of
1633 times a register can occur in one insn (surely less than 100).
1634 Multiplying this by 10000 can't overflow. */
1636 = (((double) (floor_log2 (qty_n_refs[q1]) * qty_n_refs[q1] * qty_size[q1])
1637 / (qty_death[q1] - qty_birth[q1]))
1640 = (((double) (floor_log2 (qty_n_refs[q2]) * qty_n_refs[q2] * qty_size[q2])
1641 / (qty_death[q2] - qty_birth[q2]))
1645 return sugg1 - sugg2;
1651 qty_sugg_compare_1 (q1, q2)
1654 register int sugg1 = (qty_phys_num_copy_sugg[*q1]
1655 ? qty_phys_num_copy_sugg[*q1]
1656 : qty_phys_num_sugg[*q1] * FIRST_PSEUDO_REGISTER);
1657 register int sugg2 = (qty_phys_num_copy_sugg[*q2]
1658 ? qty_phys_num_copy_sugg[*q2]
1659 : qty_phys_num_sugg[*q2] * FIRST_PSEUDO_REGISTER);
1661 /* Note that the quotient will never be bigger than
1662 the value of floor_log2 times the maximum number of
1663 times a register can occur in one insn (surely less than 100).
1664 Multiplying this by 10000 can't overflow. */
1666 = (((double) (floor_log2 (qty_n_refs[*q1]) * qty_n_refs[*q1]
1668 / (qty_death[*q1] - qty_birth[*q1]))
1671 = (((double) (floor_log2 (qty_n_refs[*q2]) * qty_n_refs[*q2]
1673 / (qty_death[*q2] - qty_birth[*q2]))
1677 return sugg1 - sugg2;
1682 /* If qtys are equally good, sort by qty number,
1683 so that the results of qsort leave nothing to chance. */
1687 /* Attempt to combine the two registers (rtx's) USEDREG and SETREG.
1688 Returns 1 if have done so, or 0 if cannot.
1690 Combining registers means marking them as having the same quantity
1691 and adjusting the offsets within the quantity if either of
1694 We don't actually combine a hard reg with a pseudo; instead
1695 we just record the hard reg as the suggestion for the pseudo's quantity.
1696 If we really combined them, we could lose if the pseudo lives
1697 across an insn that clobbers the hard reg (eg, movstr).
1699 ALREADY_DEAD is non-zero if USEDREG is known to be dead even though
1700 there is no REG_DEAD note on INSN. This occurs during the processing
1701 of REG_NO_CONFLICT blocks.
1703 MAY_SAVE_COPYCOPY is non-zero if this insn is simply copying USEDREG to
1704 SETREG or if the input and output must share a register.
1705 In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG.
1707 There are elaborate checks for the validity of combining. */
1711 combine_regs (usedreg, setreg, may_save_copy, insn_number, insn, already_dead)
1712 rtx usedreg, setreg;
1718 register int ureg, sreg;
1719 register int offset = 0;
1723 /* Determine the numbers and sizes of registers being used. If a subreg
1724 is present that does not change the entire register, don't consider
1725 this a copy insn. */
1727 while (GET_CODE (usedreg) == SUBREG)
1729 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (usedreg))) > UNITS_PER_WORD)
1731 offset += SUBREG_WORD (usedreg);
1732 usedreg = SUBREG_REG (usedreg);
1734 if (GET_CODE (usedreg) != REG)
1736 ureg = REGNO (usedreg);
1737 usize = REG_SIZE (usedreg);
1739 while (GET_CODE (setreg) == SUBREG)
1741 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (setreg))) > UNITS_PER_WORD)
1743 offset -= SUBREG_WORD (setreg);
1744 setreg = SUBREG_REG (setreg);
1746 if (GET_CODE (setreg) != REG)
1748 sreg = REGNO (setreg);
1749 ssize = REG_SIZE (setreg);
1751 /* If UREG is a pseudo-register that hasn't already been assigned a
1752 quantity number, it means that it is not local to this block or dies
1753 more than once. In either event, we can't do anything with it. */
1754 if ((ureg >= FIRST_PSEUDO_REGISTER && reg_qty[ureg] < 0)
1755 /* Do not combine registers unless one fits within the other. */
1756 || (offset > 0 && usize + offset > ssize)
1757 || (offset < 0 && usize + offset < ssize)
1758 /* Do not combine with a smaller already-assigned object
1759 if that smaller object is already combined with something bigger. */
1760 || (ssize > usize && ureg >= FIRST_PSEUDO_REGISTER
1761 && usize < qty_size[reg_qty[ureg]])
1762 /* Can't combine if SREG is not a register we can allocate. */
1763 || (sreg >= FIRST_PSEUDO_REGISTER && reg_qty[sreg] == -1)
1764 /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note.
1765 These have already been taken care of. This probably wouldn't
1766 combine anyway, but don't take any chances. */
1767 || (ureg >= FIRST_PSEUDO_REGISTER
1768 && find_reg_note (insn, REG_NO_CONFLICT, usedreg))
1769 /* Don't tie something to itself. In most cases it would make no
1770 difference, but it would screw up if the reg being tied to itself
1771 also dies in this insn. */
1773 /* Don't try to connect two different hardware registers. */
1774 || (ureg < FIRST_PSEUDO_REGISTER && sreg < FIRST_PSEUDO_REGISTER)
1775 /* Don't connect two different machine modes if they have different
1776 implications as to which registers may be used. */
1777 || !MODES_TIEABLE_P (GET_MODE (usedreg), GET_MODE (setreg)))
1780 /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in
1781 qty_phys_sugg for the pseudo instead of tying them.
1783 Return "failure" so that the lifespan of UREG is terminated here;
1784 that way the two lifespans will be disjoint and nothing will prevent
1785 the pseudo reg from being given this hard reg. */
1787 if (ureg < FIRST_PSEUDO_REGISTER)
1789 /* Allocate a quantity number so we have a place to put our
1791 if (reg_qty[sreg] == -2)
1792 reg_is_born (setreg, 2 * insn_number);
1794 if (reg_qty[sreg] >= 0)
1797 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg))
1799 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg);
1800 qty_phys_num_copy_sugg[reg_qty[sreg]]++;
1802 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg))
1804 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg);
1805 qty_phys_num_sugg[reg_qty[sreg]]++;
1811 /* Similarly for SREG a hard register and UREG a pseudo register. */
1813 if (sreg < FIRST_PSEUDO_REGISTER)
1816 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg))
1818 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg);
1819 qty_phys_num_copy_sugg[reg_qty[ureg]]++;
1821 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg))
1823 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg);
1824 qty_phys_num_sugg[reg_qty[ureg]]++;
1829 /* At this point we know that SREG and UREG are both pseudos.
1830 Do nothing if SREG already has a quantity or is a register that we
1832 if (reg_qty[sreg] >= -1
1833 /* If we are not going to let any regs live across calls,
1834 don't tie a call-crossing reg to a non-call-crossing reg. */
1835 || (current_function_has_nonlocal_label
1836 && ((reg_n_calls_crossed[ureg] > 0)
1837 != (reg_n_calls_crossed[sreg] > 0))))
1840 /* We don't already know about SREG, so tie it to UREG
1841 if this is the last use of UREG, provided the classes they want
1844 if ((already_dead || find_regno_note (insn, REG_DEAD, ureg))
1845 && reg_meets_class_p (sreg, qty_min_class[reg_qty[ureg]]))
1847 /* Add SREG to UREG's quantity. */
1848 sqty = reg_qty[ureg];
1849 reg_qty[sreg] = sqty;
1850 reg_offset[sreg] = reg_offset[ureg] + offset;
1851 reg_next_in_qty[sreg] = qty_first_reg[sqty];
1852 qty_first_reg[sqty] = sreg;
1854 /* If SREG's reg class is smaller, set qty_min_class[SQTY]. */
1855 update_qty_class (sqty, sreg);
1857 /* Update info about quantity SQTY. */
1858 qty_n_calls_crossed[sqty] += reg_n_calls_crossed[sreg];
1859 qty_n_refs[sqty] += reg_n_refs[sreg];
1864 for (i = qty_first_reg[sqty]; i >= 0; i = reg_next_in_qty[i])
1865 reg_offset[i] -= offset;
1867 qty_size[sqty] = ssize;
1868 qty_mode[sqty] = GET_MODE (setreg);
1877 /* Return 1 if the preferred class of REG allows it to be tied
1878 to a quantity or register whose class is CLASS.
1879 True if REG's reg class either contains or is contained in CLASS. */
1882 reg_meets_class_p (reg, class)
1884 enum reg_class class;
1886 register enum reg_class rclass = reg_preferred_class (reg);
1887 return (reg_class_subset_p (rclass, class)
1888 || reg_class_subset_p (class, rclass));
1891 /* Return 1 if the two specified classes have registers in common.
1892 If CALL_SAVED, then consider only call-saved registers. */
1895 reg_classes_overlap_p (c1, c2, call_saved)
1896 register enum reg_class c1;
1897 register enum reg_class c2;
1903 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
1904 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
1906 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1907 if (TEST_HARD_REG_BIT (c, i)
1908 && (! call_saved || ! call_used_regs[i]))
1914 /* Update the class of QTY assuming that REG is being tied to it. */
1917 update_qty_class (qty, reg)
1921 enum reg_class rclass = reg_preferred_class (reg);
1922 if (reg_class_subset_p (rclass, qty_min_class[qty]))
1923 qty_min_class[qty] = rclass;
1925 rclass = reg_alternate_class (reg);
1926 if (reg_class_subset_p (rclass, qty_alternate_class[qty]))
1927 qty_alternate_class[qty] = rclass;
1930 /* Handle something which alters the value of an rtx REG.
1932 REG is whatever is set or clobbered. SETTER is the rtx that
1933 is modifying the register.
1935 If it is not really a register, we do nothing.
1936 The file-global variables `this_insn' and `this_insn_number'
1937 carry info from `block_alloc'. */
1940 reg_is_set (reg, setter)
1944 /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of
1945 a hard register. These may actually not exist any more. */
1947 if (GET_CODE (reg) != SUBREG
1948 && GET_CODE (reg) != REG)
1951 /* Mark this register as being born. If it is used in a CLOBBER, mark
1952 it as being born halfway between the previous insn and this insn so that
1953 it conflicts with our inputs but not the outputs of the previous insn. */
1955 reg_is_born (reg, 2 * this_insn_number - (GET_CODE (setter) == CLOBBER));
1958 /* Handle beginning of the life of register REG.
1959 BIRTH is the index at which this is happening. */
1962 reg_is_born (reg, birth)
1968 if (GET_CODE (reg) == SUBREG)
1969 regno = REGNO (SUBREG_REG (reg)) + SUBREG_WORD (reg);
1971 regno = REGNO (reg);
1973 if (regno < FIRST_PSEUDO_REGISTER)
1975 mark_life (regno, GET_MODE (reg), 1);
1977 /* If the register was to have been born earlier that the present
1978 insn, mark it as live where it is actually born. */
1979 if (birth < 2 * this_insn_number)
1980 post_mark_life (regno, GET_MODE (reg), 1, birth, 2 * this_insn_number);
1984 if (reg_qty[regno] == -2)
1985 alloc_qty (regno, GET_MODE (reg), PSEUDO_REGNO_SIZE (regno), birth);
1987 /* If this register has a quantity number, show that it isn't dead. */
1988 if (reg_qty[regno] >= 0)
1989 qty_death[reg_qty[regno]] = -1;
1993 /* Record the death of REG in the current insn. If OUTPUT_P is non-zero,
1994 REG is an output that is dying (i.e., it is never used), otherwise it
1995 is an input (the normal case).
1996 If OUTPUT_P is 1, then we extend the life past the end of this insn. */
1999 wipe_dead_reg (reg, output_p)
2003 register int regno = REGNO (reg);
2005 /* If this insn has multiple results,
2006 and the dead reg is used in one of the results,
2007 extend its life to after this insn,
2008 so it won't get allocated together with any other result of this insn. */
2009 if (GET_CODE (PATTERN (this_insn)) == PARALLEL
2010 && !single_set (this_insn))
2013 for (i = XVECLEN (PATTERN (this_insn), 0) - 1; i >= 0; i--)
2015 rtx set = XVECEXP (PATTERN (this_insn), 0, i);
2016 if (GET_CODE (set) == SET
2017 && GET_CODE (SET_DEST (set)) != REG
2018 && !rtx_equal_p (reg, SET_DEST (set))
2019 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
2024 if (regno < FIRST_PSEUDO_REGISTER)
2026 mark_life (regno, GET_MODE (reg), 0);
2028 /* If a hard register is dying as an output, mark it as in use at
2029 the beginning of this insn (the above statement would cause this
2032 post_mark_life (regno, GET_MODE (reg), 1,
2033 2 * this_insn_number, 2 * this_insn_number+ 1);
2036 else if (reg_qty[regno] >= 0)
2037 qty_death[reg_qty[regno]] = 2 * this_insn_number + output_p;
2040 /* Find a block of SIZE words of hard regs in reg_class CLASS
2041 that can hold something of machine-mode MODE
2042 (but actually we test only the first of the block for holding MODE)
2043 and still free between insn BORN_INDEX and insn DEAD_INDEX,
2044 and return the number of the first of them.
2045 Return -1 if such a block cannot be found.
2046 If QTY crosses calls, insist on a register preserved by calls,
2047 unless ACCEPT_CALL_CLOBBERED is nonzero.
2049 If JUST_TRY_SUGGESTED is non-zero, only try to see if the suggested
2050 register is available. If not, return -1. */
2053 find_free_reg (class, mode, qty, accept_call_clobbered, just_try_suggested,
2054 born_index, dead_index)
2055 enum reg_class class;
2056 enum machine_mode mode;
2058 int accept_call_clobbered;
2059 int just_try_suggested;
2060 int born_index, dead_index;
2062 register int i, ins;
2064 register /* Declare it register if it's a scalar. */
2066 HARD_REG_SET used, first_used;
2067 #ifdef ELIMINABLE_REGS
2068 static struct {int from, to; } eliminables[] = ELIMINABLE_REGS;
2071 /* Validate our parameters. */
2072 if (born_index < 0 || born_index > dead_index)
2075 /* Don't let a pseudo live in a reg across a function call
2076 if we might get a nonlocal goto. */
2077 if (current_function_has_nonlocal_label
2078 && qty_n_calls_crossed[qty] > 0)
2081 if (accept_call_clobbered)
2082 COPY_HARD_REG_SET (used, call_fixed_reg_set);
2083 else if (qty_n_calls_crossed[qty] == 0)
2084 COPY_HARD_REG_SET (used, fixed_reg_set);
2086 COPY_HARD_REG_SET (used, call_used_reg_set);
2088 for (ins = born_index; ins < dead_index; ins++)
2089 IOR_HARD_REG_SET (used, regs_live_at[ins]);
2091 IOR_COMPL_HARD_REG_SET (used, reg_class_contents[(int) class]);
2093 /* Don't use the frame pointer reg in local-alloc even if
2094 we may omit the frame pointer, because if we do that and then we
2095 need a frame pointer, reload won't know how to move the pseudo
2096 to another hard reg. It can move only regs made by global-alloc.
2098 This is true of any register that can be eliminated. */
2099 #ifdef ELIMINABLE_REGS
2100 for (i = 0; i < sizeof eliminables / sizeof eliminables[0]; i++)
2101 SET_HARD_REG_BIT (used, eliminables[i].from);
2102 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
2103 /* If FRAME_POINTER_REGNUM is not a real register, then protect the one
2104 that it might be eliminated into. */
2105 SET_HARD_REG_BIT (used, HARD_FRAME_POINTER_REGNUM);
2108 SET_HARD_REG_BIT (used, FRAME_POINTER_REGNUM);
2111 /* Normally, the registers that can be used for the first register in
2112 a multi-register quantity are the same as those that can be used for
2113 subsequent registers. However, if just trying suggested registers,
2114 restrict our consideration to them. If there are copy-suggested
2115 register, try them. Otherwise, try the arithmetic-suggested
2117 COPY_HARD_REG_SET (first_used, used);
2119 if (just_try_suggested)
2121 if (qty_phys_num_copy_sugg[qty] != 0)
2122 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_copy_sugg[qty]);
2124 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_sugg[qty]);
2127 /* If all registers are excluded, we can't do anything. */
2128 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) ALL_REGS], first_used, fail);
2130 /* If at least one would be suitable, test each hard reg. */
2132 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2134 #ifdef REG_ALLOC_ORDER
2135 int regno = reg_alloc_order[i];
2139 if (! TEST_HARD_REG_BIT (first_used, regno)
2140 && HARD_REGNO_MODE_OK (regno, mode))
2143 register int size1 = HARD_REGNO_NREGS (regno, mode);
2144 for (j = 1; j < size1 && ! TEST_HARD_REG_BIT (used, regno + j); j++);
2147 /* Mark that this register is in use between its birth and death
2149 post_mark_life (regno, mode, 1, born_index, dead_index);
2152 #ifndef REG_ALLOC_ORDER
2153 i += j; /* Skip starting points we know will lose */
2160 /* If we are just trying suggested register, we have just tried copy-
2161 suggested registers, and there are arithmetic-suggested registers,
2164 /* If it would be profitable to allocate a call-clobbered register
2165 and save and restore it around calls, do that. */
2166 if (just_try_suggested && qty_phys_num_copy_sugg[qty] != 0
2167 && qty_phys_num_sugg[qty] != 0)
2169 /* Don't try the copy-suggested regs again. */
2170 qty_phys_num_copy_sugg[qty] = 0;
2171 return find_free_reg (class, mode, qty, accept_call_clobbered, 1,
2172 born_index, dead_index);
2175 /* We need not check to see if the current function has nonlocal
2176 labels because we don't put any pseudos that are live over calls in
2177 registers in that case. */
2179 if (! accept_call_clobbered
2180 && flag_caller_saves
2181 && ! just_try_suggested
2182 && qty_n_calls_crossed[qty] != 0
2183 && CALLER_SAVE_PROFITABLE (qty_n_refs[qty], qty_n_calls_crossed[qty]))
2185 i = find_free_reg (class, mode, qty, 1, 0, born_index, dead_index);
2187 caller_save_needed = 1;
2193 /* Mark that REGNO with machine-mode MODE is live starting from the current
2194 insn (if LIFE is non-zero) or dead starting at the current insn (if LIFE
2198 mark_life (regno, mode, life)
2200 enum machine_mode mode;
2203 register int j = HARD_REGNO_NREGS (regno, mode);
2206 SET_HARD_REG_BIT (regs_live, regno + j);
2209 CLEAR_HARD_REG_BIT (regs_live, regno + j);
2212 /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE
2213 is non-zero) or dead (if LIFE is zero) from insn number BIRTH (inclusive)
2214 to insn number DEATH (exclusive). */
2217 post_mark_life (regno, mode, life, birth, death)
2219 enum machine_mode mode;
2220 int life, birth, death;
2222 register int j = HARD_REGNO_NREGS (regno, mode);
2224 register /* Declare it register if it's a scalar. */
2226 HARD_REG_SET this_reg;
2228 CLEAR_HARD_REG_SET (this_reg);
2230 SET_HARD_REG_BIT (this_reg, regno + j);
2233 while (birth < death)
2235 IOR_HARD_REG_SET (regs_live_at[birth], this_reg);
2239 while (birth < death)
2241 AND_COMPL_HARD_REG_SET (regs_live_at[birth], this_reg);
2246 /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0
2247 is the register being clobbered, and R1 is a register being used in
2248 the equivalent expression.
2250 If R1 dies in the block and has a REG_NO_CONFLICT note on every insn
2251 in which it is used, return 1.
2253 Otherwise, return 0. */
2256 no_conflict_p (insn, r0, r1)
2260 rtx note = find_reg_note (insn, REG_LIBCALL, NULL_RTX);
2263 /* If R1 is a hard register, return 0 since we handle this case
2264 when we scan the insns that actually use it. */
2267 || (GET_CODE (r1) == REG && REGNO (r1) < FIRST_PSEUDO_REGISTER)
2268 || (GET_CODE (r1) == SUBREG && GET_CODE (SUBREG_REG (r1)) == REG
2269 && REGNO (SUBREG_REG (r1)) < FIRST_PSEUDO_REGISTER))
2272 last = XEXP (note, 0);
2274 for (p = NEXT_INSN (insn); p && p != last; p = NEXT_INSN (p))
2275 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
2277 if (find_reg_note (p, REG_DEAD, r1))
2280 if (reg_mentioned_p (r1, PATTERN (p))
2281 && ! find_reg_note (p, REG_NO_CONFLICT, r1))
2288 #ifdef REGISTER_CONSTRAINTS
2290 /* Return the number of alternatives for which the constraint string P
2291 indicates that the operand must be equal to operand 0 and that no register
2300 int reg_allowed = 0;
2301 int num_matching_alts = 0;
2306 case '=': case '+': case '?':
2307 case '#': case '&': case '!':
2309 case '1': case '2': case '3': case '4':
2310 case 'm': case '<': case '>': case 'V': case 'o':
2311 case 'E': case 'F': case 'G': case 'H':
2312 case 's': case 'i': case 'n':
2313 case 'I': case 'J': case 'K': case 'L':
2314 case 'M': case 'N': case 'O': case 'P':
2315 #ifdef EXTRA_CONSTRAINT
2316 case 'Q': case 'R': case 'S': case 'T': case 'U':
2319 /* These don't say anything we care about. */
2323 if (found_zero && ! reg_allowed)
2324 num_matching_alts++;
2326 found_zero = reg_allowed = 0;
2340 if (found_zero && ! reg_allowed)
2341 num_matching_alts++;
2343 return num_matching_alts;
2345 #endif /* REGISTER_CONSTRAINTS */
2348 dump_local_alloc (file)
2352 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
2353 if (reg_renumber[i] != -1)
2354 fprintf (file, ";; Register %d in %d.\n", i, reg_renumber[i]);