1 /* Allocate registers within a basic block, for GNU compiler.
2 Copyright (C) 1987, 1988, 1991, 1993, 1994 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* Allocation of hard register numbers to pseudo registers is done in
23 two passes. In this pass we consider only regs that are born and
24 die once within one basic block. We do this one basic block at a
25 time. Then the next pass allocates the registers that remain.
26 Two passes are used because this pass uses methods that work only
27 on linear code, but that do a better job than the general methods
28 used in global_alloc, and more quickly too.
30 The assignments made are recorded in the vector reg_renumber
31 whose space is allocated here. The rtl code itself is not altered.
33 We assign each instruction in the basic block a number
34 which is its order from the beginning of the block.
35 Then we can represent the lifetime of a pseudo register with
36 a pair of numbers, and check for conflicts easily.
37 We can record the availability of hard registers with a
38 HARD_REG_SET for each instruction. The HARD_REG_SET
39 contains 0 or 1 for each hard reg.
41 To avoid register shuffling, we tie registers together when one
42 dies by being copied into another, or dies in an instruction that
43 does arithmetic to produce another. The tied registers are
44 allocated as one. Registers with different reg class preferences
45 can never be tied unless the class preferred by one is a subclass
46 of the one preferred by the other.
48 Tying is represented with "quantity numbers".
49 A non-tied register is given a new quantity number.
50 Tied registers have the same quantity number.
52 We have provision to exempt registers, even when they are contained
53 within the block, that can be tied to others that are not contained in it.
54 This is so that global_alloc could process them both and tie them then.
55 But this is currently disabled since tying in global_alloc is not
62 #include "basic-block.h"
64 #include "hard-reg-set.h"
65 #include "insn-config.h"
69 /* Pseudos allocated here cannot be reallocated by global.c if the hard
70 register is used as a spill register. So we don't allocate such pseudos
71 here if their preferred class is likely to be used by spills.
73 On most machines, the appropriate test is if the class has one
74 register, so we default to that. */
76 #ifndef CLASS_LIKELY_SPILLED_P
77 #define CLASS_LIKELY_SPILLED_P(CLASS) (reg_class_size[(int) (CLASS)] == 1)
80 /* Next quantity number available for allocation. */
84 /* In all the following vectors indexed by quantity number. */
86 /* Element Q is the hard reg number chosen for quantity Q,
87 or -1 if none was found. */
89 static short *qty_phys_reg;
91 /* We maintain two hard register sets that indicate suggested hard registers
92 for each quantity. The first, qty_phys_copy_sugg, contains hard registers
93 that are tied to the quantity by a simple copy. The second contains all
94 hard registers that are tied to the quantity via an arithmetic operation.
96 The former register set is given priority for allocation. This tends to
97 eliminate copy insns. */
99 /* Element Q is a set of hard registers that are suggested for quantity Q by
102 static HARD_REG_SET *qty_phys_copy_sugg;
104 /* Element Q is a set of hard registers that are suggested for quantity Q by
107 static HARD_REG_SET *qty_phys_sugg;
109 /* Element Q is the number of suggested registers in qty_phys_copy_sugg. */
111 static short *qty_phys_num_copy_sugg;
113 /* Element Q is the number of suggested registers in qty_phys_sugg. */
115 static short *qty_phys_num_sugg;
117 /* Element Q is the number of refs to quantity Q. */
119 static int *qty_n_refs;
121 /* Element Q is a reg class contained in (smaller than) the
122 preferred classes of all the pseudo regs that are tied in quantity Q.
123 This is the preferred class for allocating that quantity. */
125 static enum reg_class *qty_min_class;
127 /* Insn number (counting from head of basic block)
128 where quantity Q was born. -1 if birth has not been recorded. */
130 static int *qty_birth;
132 /* Insn number (counting from head of basic block)
133 where quantity Q died. Due to the way tying is done,
134 and the fact that we consider in this pass only regs that die but once,
135 a quantity can die only once. Each quantity's life span
136 is a set of consecutive insns. -1 if death has not been recorded. */
138 static int *qty_death;
140 /* Number of words needed to hold the data in quantity Q.
141 This depends on its machine mode. It is used for these purposes:
142 1. It is used in computing the relative importances of qtys,
143 which determines the order in which we look for regs for them.
144 2. It is used in rules that prevent tying several registers of
145 different sizes in a way that is geometrically impossible
146 (see combine_regs). */
148 static int *qty_size;
150 /* This holds the mode of the registers that are tied to qty Q,
151 or VOIDmode if registers with differing modes are tied together. */
153 static enum machine_mode *qty_mode;
155 /* Number of times a reg tied to qty Q lives across a CALL_INSN. */
157 static int *qty_n_calls_crossed;
159 /* Register class within which we allocate qty Q if we can't get
160 its preferred class. */
162 static enum reg_class *qty_alternate_class;
164 /* Element Q is the SCRATCH expression for which this quantity is being
165 allocated or 0 if this quantity is allocating registers. */
167 static rtx *qty_scratch_rtx;
169 /* Element Q is nonzero if this quantity has been used in a SUBREG
170 that changes its size. */
172 static char *qty_changes_size;
174 /* Element Q is the register number of one pseudo register whose
175 reg_qty value is Q, or -1 is this quantity is for a SCRATCH. This
176 register should be the head of the chain maintained in reg_next_in_qty. */
178 static int *qty_first_reg;
180 /* If (REG N) has been assigned a quantity number, is a register number
181 of another register assigned the same quantity number, or -1 for the
182 end of the chain. qty_first_reg point to the head of this chain. */
184 static int *reg_next_in_qty;
186 /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg
188 of -1 if this register cannot be allocated by local-alloc,
189 or -2 if not known yet.
191 Note that if we see a use or death of pseudo register N with
192 reg_qty[N] == -2, register N must be local to the current block. If
193 it were used in more than one block, we would have reg_qty[N] == -1.
194 This relies on the fact that if reg_basic_block[N] is >= 0, register N
195 will not appear in any other block. We save a considerable number of
196 tests by exploiting this.
198 If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not
203 /* The offset (in words) of register N within its quantity.
204 This can be nonzero if register N is SImode, and has been tied
205 to a subreg of a DImode register. */
207 static char *reg_offset;
209 /* Vector of substitutions of register numbers,
210 used to map pseudo regs into hardware regs.
211 This is set up as a result of register allocation.
212 Element N is the hard reg assigned to pseudo reg N,
213 or is -1 if no hard reg was assigned.
214 If N is a hard reg number, element N is N. */
218 /* Set of hard registers live at the current point in the scan
219 of the instructions in a basic block. */
221 static HARD_REG_SET regs_live;
223 /* Each set of hard registers indicates registers live at a particular
224 point in the basic block. For N even, regs_live_at[N] says which
225 hard registers are needed *after* insn N/2 (i.e., they may not
226 conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1.
228 If an object is to conflict with the inputs of insn J but not the
229 outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly,
230 if it is to conflict with the outputs of insn J but not the inputs of
231 insn J + 1, it is said to die at index J*2 + 1. */
233 static HARD_REG_SET *regs_live_at;
237 int scratch_list_length;
238 static int scratch_index;
240 /* Communicate local vars `insn_number' and `insn'
241 from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */
242 static int this_insn_number;
243 static rtx this_insn;
245 static void alloc_qty PROTO((int, enum machine_mode, int, int));
246 static void alloc_qty_for_scratch PROTO((rtx, int, rtx, int, int));
247 static void validate_equiv_mem_from_store PROTO((rtx, rtx));
248 static int validate_equiv_mem PROTO((rtx, rtx, rtx));
249 static int memref_referenced_p PROTO((rtx, rtx));
250 static int memref_used_between_p PROTO((rtx, rtx, rtx));
251 static void optimize_reg_copy_1 PROTO((rtx, rtx, rtx));
252 static void optimize_reg_copy_2 PROTO((rtx, rtx, rtx));
253 static void update_equiv_regs PROTO((void));
254 static void block_alloc PROTO((int));
255 static int qty_sugg_compare PROTO((int, int));
256 static int qty_sugg_compare_1 PROTO((int *, int *));
257 static int qty_compare PROTO((int, int));
258 static int qty_compare_1 PROTO((int *, int *));
259 static int combine_regs PROTO((rtx, rtx, int, int, rtx, int));
260 static int reg_meets_class_p PROTO((int, enum reg_class));
261 static int reg_classes_overlap_p PROTO((enum reg_class, enum reg_class,
263 static void update_qty_class PROTO((int, int));
264 static void reg_is_set PROTO((rtx, rtx));
265 static void reg_is_born PROTO((rtx, int));
266 static void wipe_dead_reg PROTO((rtx, int));
267 static int find_free_reg PROTO((enum reg_class, enum machine_mode,
268 int, int, int, int, int));
269 static void mark_life PROTO((int, enum machine_mode, int));
270 static void post_mark_life PROTO((int, enum machine_mode, int, int, int));
271 static int no_conflict_p PROTO((rtx, rtx, rtx));
272 static int requires_inout PROTO((char *));
274 /* Allocate a new quantity (new within current basic block)
275 for register number REGNO which is born at index BIRTH
276 within the block. MODE and SIZE are info on reg REGNO. */
279 alloc_qty (regno, mode, size, birth)
281 enum machine_mode mode;
284 register int qty = next_qty++;
286 reg_qty[regno] = qty;
287 reg_offset[regno] = 0;
288 reg_next_in_qty[regno] = -1;
290 qty_first_reg[qty] = regno;
291 qty_size[qty] = size;
292 qty_mode[qty] = mode;
293 qty_birth[qty] = birth;
294 qty_n_calls_crossed[qty] = reg_n_calls_crossed[regno];
295 qty_min_class[qty] = reg_preferred_class (regno);
296 qty_alternate_class[qty] = reg_alternate_class (regno);
297 qty_n_refs[qty] = reg_n_refs[regno];
298 qty_changes_size[qty] = reg_changes_size[regno];
301 /* Similar to `alloc_qty', but allocates a quantity for a SCRATCH rtx
302 used as operand N in INSN. We assume here that the SCRATCH is used in
306 alloc_qty_for_scratch (scratch, n, insn, insn_code_num, insn_number)
310 int insn_code_num, insn_number;
313 enum reg_class class;
317 #ifdef REGISTER_CONSTRAINTS
318 /* If we haven't yet computed which alternative will be used, do so now.
319 Then set P to the constraints for that alternative. */
320 if (which_alternative == -1)
321 if (! constrain_operands (insn_code_num, 0))
324 for (p = insn_operand_constraint[insn_code_num][n], i = 0;
325 *p && i < which_alternative; p++)
329 /* Compute the class required for this SCRATCH. If we don't need a
330 register, the class will remain NO_REGS. If we guessed the alternative
331 number incorrectly, reload will fix things up for us. */
334 while ((c = *p++) != '\0' && c != ',')
337 case '=': case '+': case '?':
338 case '#': case '&': case '!':
340 case '0': case '1': case '2': case '3': case '4':
341 case 'm': case '<': case '>': case 'V': case 'o':
342 case 'E': case 'F': case 'G': case 'H':
343 case 's': case 'i': case 'n':
344 case 'I': case 'J': case 'K': case 'L':
345 case 'M': case 'N': case 'O': case 'P':
346 #ifdef EXTRA_CONSTRAINT
347 case 'Q': case 'R': case 'S': case 'T': case 'U':
350 /* These don't say anything we care about. */
354 /* We don't need to allocate this SCRATCH. */
358 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
363 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER (c)];
367 if (class == NO_REGS)
370 #else /* REGISTER_CONSTRAINTS */
372 class = GENERAL_REGS;
378 qty_first_reg[qty] = -1;
379 qty_scratch_rtx[qty] = scratch;
380 qty_size[qty] = GET_MODE_SIZE (GET_MODE (scratch));
381 qty_mode[qty] = GET_MODE (scratch);
382 qty_birth[qty] = 2 * insn_number - 1;
383 qty_death[qty] = 2 * insn_number + 1;
384 qty_n_calls_crossed[qty] = 0;
385 qty_min_class[qty] = class;
386 qty_alternate_class[qty] = NO_REGS;
388 qty_changes_size[qty] = 0;
391 /* Main entry point of this file. */
399 /* Leaf functions and non-leaf functions have different needs.
400 If defined, let the machine say what kind of ordering we
402 #ifdef ORDER_REGS_FOR_LOCAL_ALLOC
403 ORDER_REGS_FOR_LOCAL_ALLOC;
406 /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected
408 update_equiv_regs ();
410 /* This sets the maximum number of quantities we can have. Quantity
411 numbers start at zero and we can have one for each pseudo plus the
412 number of SCRATCHes in the largest block, in the worst case. */
413 max_qty = (max_regno - FIRST_PSEUDO_REGISTER) + max_scratch;
415 /* Allocate vectors of temporary data.
416 See the declarations of these variables, above,
417 for what they mean. */
419 /* There can be up to MAX_SCRATCH * N_BASIC_BLOCKS SCRATCHes to allocate.
420 Instead of allocating this much memory from now until the end of
421 reload, only allocate space for MAX_QTY SCRATCHes. If there are more
422 reload will allocate them. */
424 scratch_list_length = max_qty;
425 scratch_list = (rtx *) xmalloc (scratch_list_length * sizeof (rtx));
426 bzero ((char *) scratch_list, scratch_list_length * sizeof (rtx));
427 scratch_block = (int *) xmalloc (scratch_list_length * sizeof (int));
428 bzero ((char *) scratch_block, scratch_list_length * sizeof (int));
431 qty_phys_reg = (short *) alloca (max_qty * sizeof (short));
433 = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET));
434 qty_phys_num_copy_sugg = (short *) alloca (max_qty * sizeof (short));
435 qty_phys_sugg = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET));
436 qty_phys_num_sugg = (short *) alloca (max_qty * sizeof (short));
437 qty_birth = (int *) alloca (max_qty * sizeof (int));
438 qty_death = (int *) alloca (max_qty * sizeof (int));
439 qty_scratch_rtx = (rtx *) alloca (max_qty * sizeof (rtx));
440 qty_first_reg = (int *) alloca (max_qty * sizeof (int));
441 qty_size = (int *) alloca (max_qty * sizeof (int));
443 = (enum machine_mode *) alloca (max_qty * sizeof (enum machine_mode));
444 qty_n_calls_crossed = (int *) alloca (max_qty * sizeof (int));
446 = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class));
448 = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class));
449 qty_n_refs = (int *) alloca (max_qty * sizeof (int));
450 qty_changes_size = (char *) alloca (max_qty * sizeof (char));
452 reg_qty = (int *) alloca (max_regno * sizeof (int));
453 reg_offset = (char *) alloca (max_regno * sizeof (char));
454 reg_next_in_qty = (int *) alloca (max_regno * sizeof (int));
456 reg_renumber = (short *) oballoc (max_regno * sizeof (short));
457 for (i = 0; i < max_regno; i++)
458 reg_renumber[i] = -1;
460 /* Determine which pseudo-registers can be allocated by local-alloc.
461 In general, these are the registers used only in a single block and
462 which only die once. However, if a register's preferred class has only
463 a few entries, don't allocate this register here unless it is preferred
464 or nothing since retry_global_alloc won't be able to move it to
465 GENERAL_REGS if a reload register of this class is needed.
467 We need not be concerned with which block actually uses the register
468 since we will never see it outside that block. */
470 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
472 if (reg_basic_block[i] >= 0 && reg_n_deaths[i] == 1
473 && (reg_alternate_class (i) == NO_REGS
474 || ! CLASS_LIKELY_SPILLED_P (reg_preferred_class (i))))
480 /* Force loop below to initialize entire quantity array. */
483 /* Allocate each block's local registers, block by block. */
485 for (b = 0; b < n_basic_blocks; b++)
487 /* NEXT_QTY indicates which elements of the `qty_...'
488 vectors might need to be initialized because they were used
489 for the previous block; it is set to the entire array before
490 block 0. Initialize those, with explicit loop if there are few,
491 else with bzero and bcopy. Do not initialize vectors that are
492 explicit set by `alloc_qty'. */
496 for (i = 0; i < next_qty; i++)
498 qty_scratch_rtx[i] = 0;
499 CLEAR_HARD_REG_SET (qty_phys_copy_sugg[i]);
500 qty_phys_num_copy_sugg[i] = 0;
501 CLEAR_HARD_REG_SET (qty_phys_sugg[i]);
502 qty_phys_num_sugg[i] = 0;
507 #define CLEAR(vector) \
508 bzero ((char *) (vector), (sizeof (*(vector))) * next_qty);
510 CLEAR (qty_scratch_rtx);
511 CLEAR (qty_phys_copy_sugg);
512 CLEAR (qty_phys_num_copy_sugg);
513 CLEAR (qty_phys_sugg);
514 CLEAR (qty_phys_num_sugg);
526 /* Depth of loops we are in while in update_equiv_regs. */
527 static int loop_depth;
529 /* Used for communication between the following two functions: contains
530 a MEM that we wish to ensure remains unchanged. */
531 static rtx equiv_mem;
533 /* Set nonzero if EQUIV_MEM is modified. */
534 static int equiv_mem_modified;
536 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
537 Called via note_stores. */
540 validate_equiv_mem_from_store (dest, set)
544 if ((GET_CODE (dest) == REG
545 && reg_overlap_mentioned_p (dest, equiv_mem))
546 || (GET_CODE (dest) == MEM
547 && true_dependence (dest, equiv_mem)))
548 equiv_mem_modified = 1;
551 /* Verify that no store between START and the death of REG invalidates
552 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
553 by storing into an overlapping memory location, or with a non-const
556 Return 1 if MEMREF remains valid. */
559 validate_equiv_mem (start, reg, memref)
568 equiv_mem_modified = 0;
570 /* If the memory reference has side effects or is volatile, it isn't a
571 valid equivalence. */
572 if (side_effects_p (memref))
575 for (insn = start; insn && ! equiv_mem_modified; insn = NEXT_INSN (insn))
577 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
580 if (find_reg_note (insn, REG_DEAD, reg))
583 if (GET_CODE (insn) == CALL_INSN && ! RTX_UNCHANGING_P (memref)
584 && ! CONST_CALL_P (insn))
587 note_stores (PATTERN (insn), validate_equiv_mem_from_store);
589 /* If a register mentioned in MEMREF is modified via an
590 auto-increment, we lose the equivalence. Do the same if one
591 dies; although we could extend the life, it doesn't seem worth
594 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
595 if ((REG_NOTE_KIND (note) == REG_INC
596 || REG_NOTE_KIND (note) == REG_DEAD)
597 && GET_CODE (XEXP (note, 0)) == REG
598 && reg_overlap_mentioned_p (XEXP (note, 0), memref))
605 /* TRUE if X references a memory location that would be affected by a store
609 memref_referenced_p (memref, x)
615 enum rtx_code code = GET_CODE (x);
632 if (true_dependence (memref, x))
637 /* If we are setting a MEM, it doesn't count (its address does), but any
638 other SET_DEST that has a MEM in it is referencing the MEM. */
639 if (GET_CODE (SET_DEST (x)) == MEM)
641 if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0)))
644 else if (memref_referenced_p (memref, SET_DEST (x)))
647 return memref_referenced_p (memref, SET_SRC (x));
650 fmt = GET_RTX_FORMAT (code);
651 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
655 if (memref_referenced_p (memref, XEXP (x, i)))
659 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
660 if (memref_referenced_p (memref, XVECEXP (x, i, j)))
668 /* TRUE if some insn in the range (START, END] references a memory location
669 that would be affected by a store to MEMREF. */
672 memref_used_between_p (memref, start, end)
679 for (insn = NEXT_INSN (start); insn != NEXT_INSN (end);
680 insn = NEXT_INSN (insn))
681 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
682 && memref_referenced_p (memref, PATTERN (insn)))
688 /* INSN is a copy from SRC to DEST, both registers, and SRC does not die
691 Search forward to see if SRC dies before either it or DEST is modified,
692 but don't scan past the end of a basic block. If so, we can replace SRC
693 with DEST and let SRC die in INSN.
695 This will reduce the number of registers live in that range and may enable
696 DEST to be tied to SRC, thus often saving one register in addition to a
697 register-register copy. */
700 optimize_reg_copy_1 (insn, dest, src)
708 int sregno = REGNO (src);
709 int dregno = REGNO (dest);
712 #ifdef SMALL_REGISTER_CLASSES
713 /* We don't want to mess with hard regs if register classes are small. */
714 || sregno < FIRST_PSEUDO_REGISTER || dregno < FIRST_PSEUDO_REGISTER
716 /* We don't see all updates to SP if they are in an auto-inc memory
717 reference, so we must disallow this optimization on them. */
718 || sregno == STACK_POINTER_REGNUM || dregno == STACK_POINTER_REGNUM)
721 for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p))
723 if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN
724 || (GET_CODE (p) == NOTE
725 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG
726 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END)))
729 if (GET_RTX_CLASS (GET_CODE (p)) != 'i')
732 if (reg_set_p (src, p) || reg_set_p (dest, p)
733 /* Don't change a USE of a register. */
734 || (GET_CODE (PATTERN (p)) == USE
735 && reg_overlap_mentioned_p (src, XEXP (PATTERN (p), 0))))
738 /* See if all of SRC dies in P. This test is slightly more
739 conservative than it needs to be. */
740 if ((note = find_regno_note (p, REG_DEAD, sregno)) != 0
741 && GET_MODE (XEXP (note, 0)) == GET_MODE (src))
749 /* We can do the optimization. Scan forward from INSN again,
750 replacing regs as we go. Set FAILED if a replacement can't
751 be done. In that case, we can't move the death note for SRC.
752 This should be rare. */
754 /* Set to stop at next insn. */
755 for (q = next_real_insn (insn);
756 q != next_real_insn (p);
757 q = next_real_insn (q))
759 if (reg_overlap_mentioned_p (src, PATTERN (q)))
761 /* If SRC is a hard register, we might miss some
762 overlapping registers with validate_replace_rtx,
763 so we would have to undo it. We can't if DEST is
764 present in the insn, so fail in that combination
766 if (sregno < FIRST_PSEUDO_REGISTER
767 && reg_mentioned_p (dest, PATTERN (q)))
770 /* Replace all uses and make sure that the register
771 isn't still present. */
772 else if (validate_replace_rtx (src, dest, q)
773 && (sregno >= FIRST_PSEUDO_REGISTER
774 || ! reg_overlap_mentioned_p (src,
777 /* We assume that a register is used exactly once per
778 insn in the updates below. If this is not correct,
779 no great harm is done. */
780 if (sregno >= FIRST_PSEUDO_REGISTER)
781 reg_n_refs[sregno] -= loop_depth;
782 if (dregno >= FIRST_PSEUDO_REGISTER)
783 reg_n_refs[dregno] += loop_depth;
787 validate_replace_rtx (dest, src, q);
792 /* Count the insns and CALL_INSNs passed. If we passed the
793 death note of DEST, show increased live length. */
798 /* If the insn in which SRC dies is a CALL_INSN, don't count it
799 as a call that has been crossed. Otherwise, count it. */
800 if (q != p && GET_CODE (q) == CALL_INSN)
807 /* If DEST dies here, remove the death note and save it for
808 later. Make sure ALL of DEST dies here; again, this is
809 overly conservative. */
811 && (dest_death = find_regno_note (q, REG_DEAD, dregno)) != 0
812 && GET_MODE (XEXP (dest_death, 0)) == GET_MODE (dest))
813 remove_note (q, dest_death);
818 if (sregno >= FIRST_PSEUDO_REGISTER)
820 reg_live_length[sregno] -= length;
821 /* reg_live_length is only an approximation after combine
822 if sched is not run, so make sure that we still have
823 a reasonable value. */
824 if (reg_live_length[sregno] < 2)
825 reg_live_length[sregno] = 2;
826 reg_n_calls_crossed[sregno] -= n_calls;
829 if (dregno >= FIRST_PSEUDO_REGISTER)
831 reg_live_length[dregno] += d_length;
832 reg_n_calls_crossed[dregno] += d_n_calls;
835 /* Move death note of SRC from P to INSN. */
836 remove_note (p, note);
837 XEXP (note, 1) = REG_NOTES (insn);
838 REG_NOTES (insn) = note;
841 /* Put death note of DEST on P if we saw it die. */
844 XEXP (dest_death, 1) = REG_NOTES (p);
845 REG_NOTES (p) = dest_death;
851 /* If SRC is a hard register which is set or killed in some other
852 way, we can't do this optimization. */
853 else if (sregno < FIRST_PSEUDO_REGISTER
854 && dead_or_set_p (p, src))
859 /* INSN is a copy of SRC to DEST, in which SRC dies. See if we now have
860 a sequence of insns that modify DEST followed by an insn that sets
861 SRC to DEST in which DEST dies, with no prior modification of DEST.
862 (There is no need to check if the insns in between actually modify
863 DEST. We should not have cases where DEST is not modified, but
864 the optimization is safe if no such modification is detected.)
865 In that case, we can replace all uses of DEST, starting with INSN and
866 ending with the set of SRC to DEST, with SRC. We do not do this
867 optimization if a CALL_INSN is crossed unless SRC already crosses a
870 It is assumed that DEST and SRC are pseudos; it is too complicated to do
871 this for hard registers since the substitutions we may make might fail. */
874 optimize_reg_copy_2 (insn, dest, src)
881 int sregno = REGNO (src);
882 int dregno = REGNO (dest);
884 for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p))
886 if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN
887 || (GET_CODE (p) == NOTE
888 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG
889 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END)))
892 if (GET_RTX_CLASS (GET_CODE (p)) != 'i')
895 set = single_set (p);
896 if (set && SET_SRC (set) == dest && SET_DEST (set) == src
897 && find_reg_note (p, REG_DEAD, dest))
899 /* We can do the optimization. Scan forward from INSN again,
900 replacing regs as we go. */
902 /* Set to stop at next insn. */
903 for (q = insn; q != NEXT_INSN (p); q = NEXT_INSN (q))
904 if (GET_RTX_CLASS (GET_CODE (q)) == 'i')
906 if (reg_mentioned_p (dest, PATTERN (q)))
908 PATTERN (q) = replace_rtx (PATTERN (q), dest, src);
910 /* We assume that a register is used exactly once per
911 insn in the updates below. If this is not correct,
912 no great harm is done. */
913 reg_n_refs[dregno] -= loop_depth;
914 reg_n_refs[sregno] += loop_depth;
918 if (GET_CODE (q) == CALL_INSN)
920 reg_n_calls_crossed[dregno]--;
921 reg_n_calls_crossed[sregno]++;
925 remove_note (p, find_reg_note (p, REG_DEAD, dest));
926 reg_n_deaths[dregno]--;
927 remove_note (insn, find_reg_note (insn, REG_DEAD, src));
928 reg_n_deaths[sregno]--;
932 if (reg_set_p (src, p)
933 || (GET_CODE (p) == CALL_INSN && reg_n_calls_crossed[sregno] == 0))
938 /* Find registers that are equivalent to a single value throughout the
939 compilation (either because they can be referenced in memory or are set once
940 from a single constant). Lower their priority for a register.
942 If such a register is only referenced once, try substituting its value
943 into the using insn. If it succeeds, we can eliminate the register
949 rtx *reg_equiv_init_insn = (rtx *) alloca (max_regno * sizeof (rtx *));
950 rtx *reg_equiv_replacement = (rtx *) alloca (max_regno * sizeof (rtx *));
953 bzero ((char *) reg_equiv_init_insn, max_regno * sizeof (rtx *));
954 bzero ((char *) reg_equiv_replacement, max_regno * sizeof (rtx *));
956 init_alias_analysis ();
960 /* Scan the insns and find which registers have equivalences. Do this
961 in a separate scan of the insns because (due to -fcse-follow-jumps)
962 a register can be set below its use. */
963 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
966 rtx set = single_set (insn);
970 if (GET_CODE (insn) == NOTE)
972 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
974 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
978 /* If this insn contains more (or less) than a single SET, ignore it. */
982 dest = SET_DEST (set);
984 /* If this sets a MEM to the contents of a REG that is only used
985 in a single basic block, see if the register is always equivalent
986 to that memory location and if moving the store from INSN to the
987 insn that set REG is safe. If so, put a REG_EQUIV note on the
988 initializing insn. */
990 if (GET_CODE (dest) == MEM && GET_CODE (SET_SRC (set)) == REG
991 && (regno = REGNO (SET_SRC (set))) >= FIRST_PSEUDO_REGISTER
992 && reg_basic_block[regno] >= 0
993 && reg_equiv_init_insn[regno] != 0
994 && validate_equiv_mem (reg_equiv_init_insn[regno], SET_SRC (set),
996 && ! memref_used_between_p (SET_DEST (set),
997 reg_equiv_init_insn[regno], insn))
998 REG_NOTES (reg_equiv_init_insn[regno])
999 = gen_rtx (EXPR_LIST, REG_EQUIV, dest,
1000 REG_NOTES (reg_equiv_init_insn[regno]));
1002 /* If this is a register-register copy where SRC is not dead, see if we
1004 if (flag_expensive_optimizations && GET_CODE (dest) == REG
1005 && GET_CODE (SET_SRC (set)) == REG
1006 && ! find_reg_note (insn, REG_DEAD, SET_SRC (set)))
1007 optimize_reg_copy_1 (insn, dest, SET_SRC (set));
1009 /* Similarly for a pseudo-pseudo copy when SRC is dead. */
1010 else if (flag_expensive_optimizations && GET_CODE (dest) == REG
1011 && REGNO (dest) >= FIRST_PSEUDO_REGISTER
1012 && GET_CODE (SET_SRC (set)) == REG
1013 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER
1014 && find_reg_note (insn, REG_DEAD, SET_SRC (set)))
1015 optimize_reg_copy_2 (insn, dest, SET_SRC (set));
1017 /* Otherwise, we only handle the case of a pseudo register being set
1019 if (GET_CODE (dest) != REG
1020 || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER
1021 || reg_n_sets[regno] != 1)
1024 note = find_reg_note (insn, REG_EQUAL, NULL_RTX);
1026 /* Record this insn as initializing this register. */
1027 reg_equiv_init_insn[regno] = insn;
1029 /* If this register is known to be equal to a constant, record that
1030 it is always equivalent to the constant. */
1031 if (note && CONSTANT_P (XEXP (note, 0)))
1032 PUT_MODE (note, (enum machine_mode) REG_EQUIV);
1034 /* If this insn introduces a "constant" register, decrease the priority
1035 of that register. Record this insn if the register is only used once
1036 more and the equivalence value is the same as our source.
1038 The latter condition is checked for two reasons: First, it is an
1039 indication that it may be more efficient to actually emit the insn
1040 as written (if no registers are available, reload will substitute
1041 the equivalence). Secondly, it avoids problems with any registers
1042 dying in this insn whose death notes would be missed.
1044 If we don't have a REG_EQUIV note, see if this insn is loading
1045 a register used only in one basic block from a MEM. If so, and the
1046 MEM remains unchanged for the life of the register, add a REG_EQUIV
1049 note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
1051 if (note == 0 && reg_basic_block[regno] >= 0
1052 && GET_CODE (SET_SRC (set)) == MEM
1053 && validate_equiv_mem (insn, dest, SET_SRC (set)))
1054 REG_NOTES (insn) = note = gen_rtx (EXPR_LIST, REG_EQUIV, SET_SRC (set),
1057 /* Don't mess with things live during setjmp. */
1058 if (note && reg_live_length[regno] >= 0)
1060 int regno = REGNO (dest);
1062 /* Note that the statement below does not affect the priority
1064 reg_live_length[regno] *= 2;
1066 /* If the register is referenced exactly twice, meaning it is set
1067 once and used once, indicate that the reference may be replaced
1068 by the equivalence we computed above. If the register is only
1069 used in one basic block, this can't succeed or combine would
1072 It would be nice to use "loop_depth * 2" in the compare
1073 below. Unfortunately, LOOP_DEPTH need not be constant within
1074 a basic block so this would be too complicated.
1076 This case normally occurs when a parameter is read from memory
1077 and then used exactly once, not in a loop. */
1079 if (reg_n_refs[regno] == 2
1080 && reg_basic_block[regno] < 0
1081 && rtx_equal_p (XEXP (note, 0), SET_SRC (set)))
1082 reg_equiv_replacement[regno] = SET_SRC (set);
1086 /* Now scan all regs killed in an insn to see if any of them are registers
1087 only used that once. If so, see if we can replace the reference with
1088 the equivalent from. If we can, delete the initializing reference
1089 and this register will go away. */
1090 for (insn = next_active_insn (get_insns ());
1092 insn = next_active_insn (insn))
1096 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1097 if (REG_NOTE_KIND (link) == REG_DEAD
1098 /* Make sure this insn still refers to the register. */
1099 && reg_mentioned_p (XEXP (link, 0), PATTERN (insn)))
1101 int regno = REGNO (XEXP (link, 0));
1103 if (reg_equiv_replacement[regno]
1104 && validate_replace_rtx (regno_reg_rtx[regno],
1105 reg_equiv_replacement[regno], insn))
1107 rtx equiv_insn = reg_equiv_init_insn[regno];
1109 remove_death (regno, insn);
1110 reg_n_refs[regno] = 0;
1111 PUT_CODE (equiv_insn, NOTE);
1112 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1113 NOTE_SOURCE_FILE (equiv_insn) = 0;
1119 /* Allocate hard regs to the pseudo regs used only within block number B.
1120 Only the pseudos that die but once can be handled. */
1129 int insn_number = 0;
1131 int max_uid = get_max_uid ();
1133 int no_conflict_combined_regno = -1;
1134 /* Counter to prevent allocating more SCRATCHes than can be stored
1136 int scratches_allocated = scratch_index;
1138 /* Count the instructions in the basic block. */
1140 insn = basic_block_end[b];
1143 if (GET_CODE (insn) != NOTE)
1144 if (++insn_count > max_uid)
1146 if (insn == basic_block_head[b])
1148 insn = PREV_INSN (insn);
1151 /* +2 to leave room for a post_mark_life at the last insn and for
1152 the birth of a CLOBBER in the first insn. */
1153 regs_live_at = (HARD_REG_SET *) alloca ((2 * insn_count + 2)
1154 * sizeof (HARD_REG_SET));
1155 bzero ((char *) regs_live_at, (2 * insn_count + 2) * sizeof (HARD_REG_SET));
1157 /* Initialize table of hardware registers currently live. */
1160 regs_live = *basic_block_live_at_start[b];
1162 COPY_HARD_REG_SET (regs_live, basic_block_live_at_start[b]);
1165 /* This loop scans the instructions of the basic block
1166 and assigns quantities to registers.
1167 It computes which registers to tie. */
1169 insn = basic_block_head[b];
1172 register rtx body = PATTERN (insn);
1174 if (GET_CODE (insn) != NOTE)
1177 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1179 register rtx link, set;
1180 register int win = 0;
1181 register rtx r0, r1;
1182 int combined_regno = -1;
1184 int insn_code_number = recog_memoized (insn);
1186 this_insn_number = insn_number;
1189 if (insn_code_number >= 0)
1190 insn_extract (insn);
1191 which_alternative = -1;
1193 /* Is this insn suitable for tying two registers?
1194 If so, try doing that.
1195 Suitable insns are those with at least two operands and where
1196 operand 0 is an output that is a register that is not
1199 We can tie operand 0 with some operand that dies in this insn.
1200 First look for operands that are required to be in the same
1201 register as operand 0. If we find such, only try tying that
1202 operand or one that can be put into that operand if the
1203 operation is commutative. If we don't find an operand
1204 that is required to be in the same register as operand 0,
1205 we can tie with any operand.
1207 Subregs in place of regs are also ok.
1209 If tying is done, WIN is set nonzero. */
1211 if (insn_code_number >= 0
1212 #ifdef REGISTER_CONSTRAINTS
1213 && insn_n_operands[insn_code_number] > 1
1214 && insn_operand_constraint[insn_code_number][0][0] == '='
1215 && insn_operand_constraint[insn_code_number][0][1] != '&'
1217 && GET_CODE (PATTERN (insn)) == SET
1218 && rtx_equal_p (SET_DEST (PATTERN (insn)), recog_operand[0])
1222 #ifdef REGISTER_CONSTRAINTS
1223 /* If non-negative, is an operand that must match operand 0. */
1224 int must_match_0 = -1;
1225 /* Counts number of alternatives that require a match with
1227 int n_matching_alts = 0;
1229 for (i = 1; i < insn_n_operands[insn_code_number]; i++)
1231 char *p = insn_operand_constraint[insn_code_number][i];
1232 int this_match = (requires_inout (p));
1234 n_matching_alts += this_match;
1235 if (this_match == insn_n_alternatives[insn_code_number])
1240 r0 = recog_operand[0];
1241 for (i = 1; i < insn_n_operands[insn_code_number]; i++)
1243 #ifdef REGISTER_CONSTRAINTS
1244 /* Skip this operand if we found an operand that
1245 must match operand 0 and this operand isn't it
1246 and can't be made to be it by commutativity. */
1248 if (must_match_0 >= 0 && i != must_match_0
1249 && ! (i == must_match_0 + 1
1250 && insn_operand_constraint[insn_code_number][i-1][0] == '%')
1251 && ! (i == must_match_0 - 1
1252 && insn_operand_constraint[insn_code_number][i][0] == '%'))
1255 /* Likewise if each alternative has some operand that
1256 must match operand zero. In that case, skip any
1257 operand that doesn't list operand 0 since we know that
1258 the operand always conflicts with operand 0. We
1259 ignore commutatity in this case to keep things simple. */
1260 if (n_matching_alts == insn_n_alternatives[insn_code_number]
1261 && (0 == requires_inout
1262 (insn_operand_constraint[insn_code_number][i])))
1266 r1 = recog_operand[i];
1268 /* If the operand is an address, find a register in it.
1269 There may be more than one register, but we only try one
1272 #ifdef REGISTER_CONSTRAINTS
1273 insn_operand_constraint[insn_code_number][i][0] == 'p'
1275 insn_operand_address_p[insn_code_number][i]
1278 while (GET_CODE (r1) == PLUS || GET_CODE (r1) == MULT)
1281 if (GET_CODE (r0) == REG || GET_CODE (r0) == SUBREG)
1283 /* We have two priorities for hard register preferences.
1284 If we have a move insn or an insn whose first input
1285 can only be in the same register as the output, give
1286 priority to an equivalence found from that insn. */
1288 = ((SET_DEST (body) == r0 && SET_SRC (body) == r1)
1289 #ifdef REGISTER_CONSTRAINTS
1290 || (r1 == recog_operand[i] && must_match_0 >= 0)
1294 if (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1295 win = combine_regs (r1, r0, may_save_copy,
1296 insn_number, insn, 0);
1303 /* Recognize an insn sequence with an ultimate result
1304 which can safely overlap one of the inputs.
1305 The sequence begins with a CLOBBER of its result,
1306 and ends with an insn that copies the result to itself
1307 and has a REG_EQUAL note for an equivalent formula.
1308 That note indicates what the inputs are.
1309 The result and the input can overlap if each insn in
1310 the sequence either doesn't mention the input
1311 or has a REG_NO_CONFLICT note to inhibit the conflict.
1313 We do the combining test at the CLOBBER so that the
1314 destination register won't have had a quantity number
1315 assigned, since that would prevent combining. */
1317 if (GET_CODE (PATTERN (insn)) == CLOBBER
1318 && (r0 = XEXP (PATTERN (insn), 0),
1319 GET_CODE (r0) == REG)
1320 && (link = find_reg_note (insn, REG_LIBCALL, NULL_RTX)) != 0
1321 && XEXP (link, 0) != 0
1322 && GET_CODE (XEXP (link, 0)) == INSN
1323 && (set = single_set (XEXP (link, 0))) != 0
1324 && SET_DEST (set) == r0 && SET_SRC (set) == r0
1325 && (note = find_reg_note (XEXP (link, 0), REG_EQUAL,
1328 if (r1 = XEXP (note, 0), GET_CODE (r1) == REG
1329 /* Check that we have such a sequence. */
1330 && no_conflict_p (insn, r0, r1))
1331 win = combine_regs (r1, r0, 1, insn_number, insn, 1);
1332 else if (GET_RTX_FORMAT (GET_CODE (XEXP (note, 0)))[0] == 'e'
1333 && (r1 = XEXP (XEXP (note, 0), 0),
1334 GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1335 && no_conflict_p (insn, r0, r1))
1336 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1338 /* Here we care if the operation to be computed is
1340 else if ((GET_CODE (XEXP (note, 0)) == EQ
1341 || GET_CODE (XEXP (note, 0)) == NE
1342 || GET_RTX_CLASS (GET_CODE (XEXP (note, 0))) == 'c')
1343 && (r1 = XEXP (XEXP (note, 0), 1),
1344 (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG))
1345 && no_conflict_p (insn, r0, r1))
1346 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1348 /* If we did combine something, show the register number
1349 in question so that we know to ignore its death. */
1351 no_conflict_combined_regno = REGNO (r1);
1354 /* If registers were just tied, set COMBINED_REGNO
1355 to the number of the register used in this insn
1356 that was tied to the register set in this insn.
1357 This register's qty should not be "killed". */
1361 while (GET_CODE (r1) == SUBREG)
1362 r1 = SUBREG_REG (r1);
1363 combined_regno = REGNO (r1);
1366 /* Mark the death of everything that dies in this instruction,
1367 except for anything that was just combined. */
1369 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1370 if (REG_NOTE_KIND (link) == REG_DEAD
1371 && GET_CODE (XEXP (link, 0)) == REG
1372 && combined_regno != REGNO (XEXP (link, 0))
1373 && (no_conflict_combined_regno != REGNO (XEXP (link, 0))
1374 || ! find_reg_note (insn, REG_NO_CONFLICT, XEXP (link, 0))))
1375 wipe_dead_reg (XEXP (link, 0), 0);
1377 /* Allocate qty numbers for all registers local to this block
1378 that are born (set) in this instruction.
1379 A pseudo that already has a qty is not changed. */
1381 note_stores (PATTERN (insn), reg_is_set);
1383 /* If anything is set in this insn and then unused, mark it as dying
1384 after this insn, so it will conflict with our outputs. This
1385 can't match with something that combined, and it doesn't matter
1386 if it did. Do this after the calls to reg_is_set since these
1387 die after, not during, the current insn. */
1389 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1390 if (REG_NOTE_KIND (link) == REG_UNUSED
1391 && GET_CODE (XEXP (link, 0)) == REG)
1392 wipe_dead_reg (XEXP (link, 0), 1);
1394 /* Allocate quantities for any SCRATCH operands of this insn. */
1396 if (insn_code_number >= 0)
1397 for (i = 0; i < insn_n_operands[insn_code_number]; i++)
1398 if (GET_CODE (recog_operand[i]) == SCRATCH
1399 && scratches_allocated++ < scratch_list_length)
1400 alloc_qty_for_scratch (recog_operand[i], i, insn,
1401 insn_code_number, insn_number);
1403 /* If this is an insn that has a REG_RETVAL note pointing at a
1404 CLOBBER insn, we have reached the end of a REG_NO_CONFLICT
1405 block, so clear any register number that combined within it. */
1406 if ((note = find_reg_note (insn, REG_RETVAL, NULL_RTX)) != 0
1407 && GET_CODE (XEXP (note, 0)) == INSN
1408 && GET_CODE (PATTERN (XEXP (note, 0))) == CLOBBER)
1409 no_conflict_combined_regno = -1;
1412 /* Set the registers live after INSN_NUMBER. Note that we never
1413 record the registers live before the block's first insn, since no
1414 pseudos we care about are live before that insn. */
1416 IOR_HARD_REG_SET (regs_live_at[2 * insn_number], regs_live);
1417 IOR_HARD_REG_SET (regs_live_at[2 * insn_number + 1], regs_live);
1419 if (insn == basic_block_end[b])
1422 insn = NEXT_INSN (insn);
1425 /* Now every register that is local to this basic block
1426 should have been given a quantity, or else -1 meaning ignore it.
1427 Every quantity should have a known birth and death.
1429 Order the qtys so we assign them registers in order of the
1430 number of suggested registers they need so we allocate those with
1431 the most restrictive needs first. */
1433 qty_order = (int *) alloca (next_qty * sizeof (int));
1434 for (i = 0; i < next_qty; i++)
1437 #define EXCHANGE(I1, I2) \
1438 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1443 /* Make qty_order[2] be the one to allocate last. */
1444 if (qty_sugg_compare (0, 1) > 0)
1446 if (qty_sugg_compare (1, 2) > 0)
1449 /* ... Fall through ... */
1451 /* Put the best one to allocate in qty_order[0]. */
1452 if (qty_sugg_compare (0, 1) > 0)
1455 /* ... Fall through ... */
1459 /* Nothing to do here. */
1463 qsort (qty_order, next_qty, sizeof (int), qty_sugg_compare_1);
1466 /* Try to put each quantity in a suggested physical register, if it has one.
1467 This may cause registers to be allocated that otherwise wouldn't be, but
1468 this seems acceptable in local allocation (unlike global allocation). */
1469 for (i = 0; i < next_qty; i++)
1472 if (qty_phys_num_sugg[q] != 0 || qty_phys_num_copy_sugg[q] != 0)
1473 qty_phys_reg[q] = find_free_reg (qty_min_class[q], qty_mode[q], q,
1474 0, 1, qty_birth[q], qty_death[q]);
1476 qty_phys_reg[q] = -1;
1479 /* Order the qtys so we assign them registers in order of
1480 decreasing length of life. Normally call qsort, but if we
1481 have only a very small number of quantities, sort them ourselves. */
1483 for (i = 0; i < next_qty; i++)
1486 #define EXCHANGE(I1, I2) \
1487 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1492 /* Make qty_order[2] be the one to allocate last. */
1493 if (qty_compare (0, 1) > 0)
1495 if (qty_compare (1, 2) > 0)
1498 /* ... Fall through ... */
1500 /* Put the best one to allocate in qty_order[0]. */
1501 if (qty_compare (0, 1) > 0)
1504 /* ... Fall through ... */
1508 /* Nothing to do here. */
1512 qsort (qty_order, next_qty, sizeof (int), qty_compare_1);
1515 /* Now for each qty that is not a hardware register,
1516 look for a hardware register to put it in.
1517 First try the register class that is cheapest for this qty,
1518 if there is more than one class. */
1520 for (i = 0; i < next_qty; i++)
1523 if (qty_phys_reg[q] < 0)
1525 if (N_REG_CLASSES > 1)
1527 qty_phys_reg[q] = find_free_reg (qty_min_class[q],
1528 qty_mode[q], q, 0, 0,
1529 qty_birth[q], qty_death[q]);
1530 if (qty_phys_reg[q] >= 0)
1534 if (qty_alternate_class[q] != NO_REGS)
1535 qty_phys_reg[q] = find_free_reg (qty_alternate_class[q],
1536 qty_mode[q], q, 0, 0,
1537 qty_birth[q], qty_death[q]);
1541 /* Now propagate the register assignments
1542 to the pseudo regs belonging to the qtys. */
1544 for (q = 0; q < next_qty; q++)
1545 if (qty_phys_reg[q] >= 0)
1547 for (i = qty_first_reg[q]; i >= 0; i = reg_next_in_qty[i])
1548 reg_renumber[i] = qty_phys_reg[q] + reg_offset[i];
1549 if (qty_scratch_rtx[q])
1551 if (GET_CODE (qty_scratch_rtx[q]) == REG)
1553 PUT_CODE (qty_scratch_rtx[q], REG);
1554 REGNO (qty_scratch_rtx[q]) = qty_phys_reg[q];
1556 scratch_block[scratch_index] = b;
1557 scratch_list[scratch_index++] = qty_scratch_rtx[q];
1559 /* Must clear the USED field, because it will have been set by
1560 copy_rtx_if_shared, but the leaf_register code expects that
1561 it is zero in all REG rtx. copy_rtx_if_shared does not set the
1562 used bit for REGs, but does for SCRATCHes. */
1563 qty_scratch_rtx[q]->used = 0;
1568 /* Compare two quantities' priority for getting real registers.
1569 We give shorter-lived quantities higher priority.
1570 Quantities with more references are also preferred, as are quantities that
1571 require multiple registers. This is the identical prioritization as
1572 done by global-alloc.
1574 We used to give preference to registers with *longer* lives, but using
1575 the same algorithm in both local- and global-alloc can speed up execution
1576 of some programs by as much as a factor of three! */
1579 qty_compare (q1, q2)
1582 /* Note that the quotient will never be bigger than
1583 the value of floor_log2 times the maximum number of
1584 times a register can occur in one insn (surely less than 100).
1585 Multiplying this by 10000 can't overflow. */
1587 = (((double) (floor_log2 (qty_n_refs[q1]) * qty_n_refs[q1] * qty_size[q1])
1588 / (qty_death[q1] - qty_birth[q1]))
1591 = (((double) (floor_log2 (qty_n_refs[q2]) * qty_n_refs[q2] * qty_size[q2])
1592 / (qty_death[q2] - qty_birth[q2]))
1598 qty_compare_1 (q1, q2)
1603 /* Note that the quotient will never be bigger than
1604 the value of floor_log2 times the maximum number of
1605 times a register can occur in one insn (surely less than 100).
1606 Multiplying this by 10000 can't overflow. */
1608 = (((double) (floor_log2 (qty_n_refs[*q1]) * qty_n_refs[*q1]
1610 / (qty_death[*q1] - qty_birth[*q1]))
1613 = (((double) (floor_log2 (qty_n_refs[*q2]) * qty_n_refs[*q2]
1615 / (qty_death[*q2] - qty_birth[*q2]))
1619 if (tem != 0) return tem;
1620 /* If qtys are equally good, sort by qty number,
1621 so that the results of qsort leave nothing to chance. */
1625 /* Compare two quantities' priority for getting real registers. This version
1626 is called for quantities that have suggested hard registers. First priority
1627 goes to quantities that have copy preferences, then to those that have
1628 normal preferences. Within those groups, quantities with the lower
1629 number of preferences have the highest priority. Of those, we use the same
1630 algorithm as above. */
1633 qty_sugg_compare (q1, q2)
1636 register int sugg1 = (qty_phys_num_copy_sugg[q1]
1637 ? qty_phys_num_copy_sugg[q1]
1638 : qty_phys_num_sugg[q1] * FIRST_PSEUDO_REGISTER);
1639 register int sugg2 = (qty_phys_num_copy_sugg[q2]
1640 ? qty_phys_num_copy_sugg[q2]
1641 : qty_phys_num_sugg[q2] * FIRST_PSEUDO_REGISTER);
1642 /* Note that the quotient will never be bigger than
1643 the value of floor_log2 times the maximum number of
1644 times a register can occur in one insn (surely less than 100).
1645 Multiplying this by 10000 can't overflow. */
1647 = (((double) (floor_log2 (qty_n_refs[q1]) * qty_n_refs[q1] * qty_size[q1])
1648 / (qty_death[q1] - qty_birth[q1]))
1651 = (((double) (floor_log2 (qty_n_refs[q2]) * qty_n_refs[q2] * qty_size[q2])
1652 / (qty_death[q2] - qty_birth[q2]))
1656 return sugg1 - sugg2;
1662 qty_sugg_compare_1 (q1, q2)
1665 register int sugg1 = (qty_phys_num_copy_sugg[*q1]
1666 ? qty_phys_num_copy_sugg[*q1]
1667 : qty_phys_num_sugg[*q1] * FIRST_PSEUDO_REGISTER);
1668 register int sugg2 = (qty_phys_num_copy_sugg[*q2]
1669 ? qty_phys_num_copy_sugg[*q2]
1670 : qty_phys_num_sugg[*q2] * FIRST_PSEUDO_REGISTER);
1672 /* Note that the quotient will never be bigger than
1673 the value of floor_log2 times the maximum number of
1674 times a register can occur in one insn (surely less than 100).
1675 Multiplying this by 10000 can't overflow. */
1677 = (((double) (floor_log2 (qty_n_refs[*q1]) * qty_n_refs[*q1]
1679 / (qty_death[*q1] - qty_birth[*q1]))
1682 = (((double) (floor_log2 (qty_n_refs[*q2]) * qty_n_refs[*q2]
1684 / (qty_death[*q2] - qty_birth[*q2]))
1688 return sugg1 - sugg2;
1693 /* If qtys are equally good, sort by qty number,
1694 so that the results of qsort leave nothing to chance. */
1698 /* Attempt to combine the two registers (rtx's) USEDREG and SETREG.
1699 Returns 1 if have done so, or 0 if cannot.
1701 Combining registers means marking them as having the same quantity
1702 and adjusting the offsets within the quantity if either of
1705 We don't actually combine a hard reg with a pseudo; instead
1706 we just record the hard reg as the suggestion for the pseudo's quantity.
1707 If we really combined them, we could lose if the pseudo lives
1708 across an insn that clobbers the hard reg (eg, movstr).
1710 ALREADY_DEAD is non-zero if USEDREG is known to be dead even though
1711 there is no REG_DEAD note on INSN. This occurs during the processing
1712 of REG_NO_CONFLICT blocks.
1714 MAY_SAVE_COPYCOPY is non-zero if this insn is simply copying USEDREG to
1715 SETREG or if the input and output must share a register.
1716 In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG.
1718 There are elaborate checks for the validity of combining. */
1722 combine_regs (usedreg, setreg, may_save_copy, insn_number, insn, already_dead)
1723 rtx usedreg, setreg;
1729 register int ureg, sreg;
1730 register int offset = 0;
1734 /* Determine the numbers and sizes of registers being used. If a subreg
1735 is present that does not change the entire register, don't consider
1736 this a copy insn. */
1738 while (GET_CODE (usedreg) == SUBREG)
1740 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (usedreg))) > UNITS_PER_WORD)
1742 offset += SUBREG_WORD (usedreg);
1743 usedreg = SUBREG_REG (usedreg);
1745 if (GET_CODE (usedreg) != REG)
1747 ureg = REGNO (usedreg);
1748 usize = REG_SIZE (usedreg);
1750 while (GET_CODE (setreg) == SUBREG)
1752 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (setreg))) > UNITS_PER_WORD)
1754 offset -= SUBREG_WORD (setreg);
1755 setreg = SUBREG_REG (setreg);
1757 if (GET_CODE (setreg) != REG)
1759 sreg = REGNO (setreg);
1760 ssize = REG_SIZE (setreg);
1762 /* If UREG is a pseudo-register that hasn't already been assigned a
1763 quantity number, it means that it is not local to this block or dies
1764 more than once. In either event, we can't do anything with it. */
1765 if ((ureg >= FIRST_PSEUDO_REGISTER && reg_qty[ureg] < 0)
1766 /* Do not combine registers unless one fits within the other. */
1767 || (offset > 0 && usize + offset > ssize)
1768 || (offset < 0 && usize + offset < ssize)
1769 /* Do not combine with a smaller already-assigned object
1770 if that smaller object is already combined with something bigger. */
1771 || (ssize > usize && ureg >= FIRST_PSEUDO_REGISTER
1772 && usize < qty_size[reg_qty[ureg]])
1773 /* Can't combine if SREG is not a register we can allocate. */
1774 || (sreg >= FIRST_PSEUDO_REGISTER && reg_qty[sreg] == -1)
1775 /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note.
1776 These have already been taken care of. This probably wouldn't
1777 combine anyway, but don't take any chances. */
1778 || (ureg >= FIRST_PSEUDO_REGISTER
1779 && find_reg_note (insn, REG_NO_CONFLICT, usedreg))
1780 /* Don't tie something to itself. In most cases it would make no
1781 difference, but it would screw up if the reg being tied to itself
1782 also dies in this insn. */
1784 /* Don't try to connect two different hardware registers. */
1785 || (ureg < FIRST_PSEUDO_REGISTER && sreg < FIRST_PSEUDO_REGISTER)
1786 /* Don't connect two different machine modes if they have different
1787 implications as to which registers may be used. */
1788 || !MODES_TIEABLE_P (GET_MODE (usedreg), GET_MODE (setreg)))
1791 /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in
1792 qty_phys_sugg for the pseudo instead of tying them.
1794 Return "failure" so that the lifespan of UREG is terminated here;
1795 that way the two lifespans will be disjoint and nothing will prevent
1796 the pseudo reg from being given this hard reg. */
1798 if (ureg < FIRST_PSEUDO_REGISTER)
1800 /* Allocate a quantity number so we have a place to put our
1802 if (reg_qty[sreg] == -2)
1803 reg_is_born (setreg, 2 * insn_number);
1805 if (reg_qty[sreg] >= 0)
1808 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg))
1810 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg);
1811 qty_phys_num_copy_sugg[reg_qty[sreg]]++;
1813 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg))
1815 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg);
1816 qty_phys_num_sugg[reg_qty[sreg]]++;
1822 /* Similarly for SREG a hard register and UREG a pseudo register. */
1824 if (sreg < FIRST_PSEUDO_REGISTER)
1827 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg))
1829 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg);
1830 qty_phys_num_copy_sugg[reg_qty[ureg]]++;
1832 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg))
1834 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg);
1835 qty_phys_num_sugg[reg_qty[ureg]]++;
1840 /* At this point we know that SREG and UREG are both pseudos.
1841 Do nothing if SREG already has a quantity or is a register that we
1843 if (reg_qty[sreg] >= -1
1844 /* If we are not going to let any regs live across calls,
1845 don't tie a call-crossing reg to a non-call-crossing reg. */
1846 || (current_function_has_nonlocal_label
1847 && ((reg_n_calls_crossed[ureg] > 0)
1848 != (reg_n_calls_crossed[sreg] > 0))))
1851 /* We don't already know about SREG, so tie it to UREG
1852 if this is the last use of UREG, provided the classes they want
1855 if ((already_dead || find_regno_note (insn, REG_DEAD, ureg))
1856 && reg_meets_class_p (sreg, qty_min_class[reg_qty[ureg]]))
1858 /* Add SREG to UREG's quantity. */
1859 sqty = reg_qty[ureg];
1860 reg_qty[sreg] = sqty;
1861 reg_offset[sreg] = reg_offset[ureg] + offset;
1862 reg_next_in_qty[sreg] = qty_first_reg[sqty];
1863 qty_first_reg[sqty] = sreg;
1865 /* If SREG's reg class is smaller, set qty_min_class[SQTY]. */
1866 update_qty_class (sqty, sreg);
1868 /* Update info about quantity SQTY. */
1869 qty_n_calls_crossed[sqty] += reg_n_calls_crossed[sreg];
1870 qty_n_refs[sqty] += reg_n_refs[sreg];
1875 for (i = qty_first_reg[sqty]; i >= 0; i = reg_next_in_qty[i])
1876 reg_offset[i] -= offset;
1878 qty_size[sqty] = ssize;
1879 qty_mode[sqty] = GET_MODE (setreg);
1888 /* Return 1 if the preferred class of REG allows it to be tied
1889 to a quantity or register whose class is CLASS.
1890 True if REG's reg class either contains or is contained in CLASS. */
1893 reg_meets_class_p (reg, class)
1895 enum reg_class class;
1897 register enum reg_class rclass = reg_preferred_class (reg);
1898 return (reg_class_subset_p (rclass, class)
1899 || reg_class_subset_p (class, rclass));
1902 /* Return 1 if the two specified classes have registers in common.
1903 If CALL_SAVED, then consider only call-saved registers. */
1906 reg_classes_overlap_p (c1, c2, call_saved)
1907 register enum reg_class c1;
1908 register enum reg_class c2;
1914 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
1915 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
1917 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1918 if (TEST_HARD_REG_BIT (c, i)
1919 && (! call_saved || ! call_used_regs[i]))
1925 /* Update the class of QTY assuming that REG is being tied to it. */
1928 update_qty_class (qty, reg)
1932 enum reg_class rclass = reg_preferred_class (reg);
1933 if (reg_class_subset_p (rclass, qty_min_class[qty]))
1934 qty_min_class[qty] = rclass;
1936 rclass = reg_alternate_class (reg);
1937 if (reg_class_subset_p (rclass, qty_alternate_class[qty]))
1938 qty_alternate_class[qty] = rclass;
1940 if (reg_changes_size[reg])
1941 qty_changes_size[qty] = 1;
1944 /* Handle something which alters the value of an rtx REG.
1946 REG is whatever is set or clobbered. SETTER is the rtx that
1947 is modifying the register.
1949 If it is not really a register, we do nothing.
1950 The file-global variables `this_insn' and `this_insn_number'
1951 carry info from `block_alloc'. */
1954 reg_is_set (reg, setter)
1958 /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of
1959 a hard register. These may actually not exist any more. */
1961 if (GET_CODE (reg) != SUBREG
1962 && GET_CODE (reg) != REG)
1965 /* Mark this register as being born. If it is used in a CLOBBER, mark
1966 it as being born halfway between the previous insn and this insn so that
1967 it conflicts with our inputs but not the outputs of the previous insn. */
1969 reg_is_born (reg, 2 * this_insn_number - (GET_CODE (setter) == CLOBBER));
1972 /* Handle beginning of the life of register REG.
1973 BIRTH is the index at which this is happening. */
1976 reg_is_born (reg, birth)
1982 if (GET_CODE (reg) == SUBREG)
1983 regno = REGNO (SUBREG_REG (reg)) + SUBREG_WORD (reg);
1985 regno = REGNO (reg);
1987 if (regno < FIRST_PSEUDO_REGISTER)
1989 mark_life (regno, GET_MODE (reg), 1);
1991 /* If the register was to have been born earlier that the present
1992 insn, mark it as live where it is actually born. */
1993 if (birth < 2 * this_insn_number)
1994 post_mark_life (regno, GET_MODE (reg), 1, birth, 2 * this_insn_number);
1998 if (reg_qty[regno] == -2)
1999 alloc_qty (regno, GET_MODE (reg), PSEUDO_REGNO_SIZE (regno), birth);
2001 /* If this register has a quantity number, show that it isn't dead. */
2002 if (reg_qty[regno] >= 0)
2003 qty_death[reg_qty[regno]] = -1;
2007 /* Record the death of REG in the current insn. If OUTPUT_P is non-zero,
2008 REG is an output that is dying (i.e., it is never used), otherwise it
2009 is an input (the normal case).
2010 If OUTPUT_P is 1, then we extend the life past the end of this insn. */
2013 wipe_dead_reg (reg, output_p)
2017 register int regno = REGNO (reg);
2019 /* If this insn has multiple results,
2020 and the dead reg is used in one of the results,
2021 extend its life to after this insn,
2022 so it won't get allocated together with any other result of this insn. */
2023 if (GET_CODE (PATTERN (this_insn)) == PARALLEL
2024 && !single_set (this_insn))
2027 for (i = XVECLEN (PATTERN (this_insn), 0) - 1; i >= 0; i--)
2029 rtx set = XVECEXP (PATTERN (this_insn), 0, i);
2030 if (GET_CODE (set) == SET
2031 && GET_CODE (SET_DEST (set)) != REG
2032 && !rtx_equal_p (reg, SET_DEST (set))
2033 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
2038 if (regno < FIRST_PSEUDO_REGISTER)
2040 mark_life (regno, GET_MODE (reg), 0);
2042 /* If a hard register is dying as an output, mark it as in use at
2043 the beginning of this insn (the above statement would cause this
2046 post_mark_life (regno, GET_MODE (reg), 1,
2047 2 * this_insn_number, 2 * this_insn_number+ 1);
2050 else if (reg_qty[regno] >= 0)
2051 qty_death[reg_qty[regno]] = 2 * this_insn_number + output_p;
2054 /* Find a block of SIZE words of hard regs in reg_class CLASS
2055 that can hold something of machine-mode MODE
2056 (but actually we test only the first of the block for holding MODE)
2057 and still free between insn BORN_INDEX and insn DEAD_INDEX,
2058 and return the number of the first of them.
2059 Return -1 if such a block cannot be found.
2060 If QTY crosses calls, insist on a register preserved by calls,
2061 unless ACCEPT_CALL_CLOBBERED is nonzero.
2063 If JUST_TRY_SUGGESTED is non-zero, only try to see if the suggested
2064 register is available. If not, return -1. */
2067 find_free_reg (class, mode, qty, accept_call_clobbered, just_try_suggested,
2068 born_index, dead_index)
2069 enum reg_class class;
2070 enum machine_mode mode;
2072 int accept_call_clobbered;
2073 int just_try_suggested;
2074 int born_index, dead_index;
2076 register int i, ins;
2078 register /* Declare it register if it's a scalar. */
2080 HARD_REG_SET used, first_used;
2081 #ifdef ELIMINABLE_REGS
2082 static struct {int from, to; } eliminables[] = ELIMINABLE_REGS;
2085 /* Validate our parameters. */
2086 if (born_index < 0 || born_index > dead_index)
2089 /* Don't let a pseudo live in a reg across a function call
2090 if we might get a nonlocal goto. */
2091 if (current_function_has_nonlocal_label
2092 && qty_n_calls_crossed[qty] > 0)
2095 if (accept_call_clobbered)
2096 COPY_HARD_REG_SET (used, call_fixed_reg_set);
2097 else if (qty_n_calls_crossed[qty] == 0)
2098 COPY_HARD_REG_SET (used, fixed_reg_set);
2100 COPY_HARD_REG_SET (used, call_used_reg_set);
2102 for (ins = born_index; ins < dead_index; ins++)
2103 IOR_HARD_REG_SET (used, regs_live_at[ins]);
2105 IOR_COMPL_HARD_REG_SET (used, reg_class_contents[(int) class]);
2107 /* Don't use the frame pointer reg in local-alloc even if
2108 we may omit the frame pointer, because if we do that and then we
2109 need a frame pointer, reload won't know how to move the pseudo
2110 to another hard reg. It can move only regs made by global-alloc.
2112 This is true of any register that can be eliminated. */
2113 #ifdef ELIMINABLE_REGS
2114 for (i = 0; i < sizeof eliminables / sizeof eliminables[0]; i++)
2115 SET_HARD_REG_BIT (used, eliminables[i].from);
2116 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
2117 /* If FRAME_POINTER_REGNUM is not a real register, then protect the one
2118 that it might be eliminated into. */
2119 SET_HARD_REG_BIT (used, HARD_FRAME_POINTER_REGNUM);
2122 SET_HARD_REG_BIT (used, FRAME_POINTER_REGNUM);
2125 #ifdef CLASS_CANNOT_CHANGE_SIZE
2126 if (qty_changes_size[qty])
2127 IOR_HARD_REG_SET (used,
2128 reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE]);
2131 /* Normally, the registers that can be used for the first register in
2132 a multi-register quantity are the same as those that can be used for
2133 subsequent registers. However, if just trying suggested registers,
2134 restrict our consideration to them. If there are copy-suggested
2135 register, try them. Otherwise, try the arithmetic-suggested
2137 COPY_HARD_REG_SET (first_used, used);
2139 if (just_try_suggested)
2141 if (qty_phys_num_copy_sugg[qty] != 0)
2142 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_copy_sugg[qty]);
2144 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_sugg[qty]);
2147 /* If all registers are excluded, we can't do anything. */
2148 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) ALL_REGS], first_used, fail);
2150 /* If at least one would be suitable, test each hard reg. */
2152 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2154 #ifdef REG_ALLOC_ORDER
2155 int regno = reg_alloc_order[i];
2159 if (! TEST_HARD_REG_BIT (first_used, regno)
2160 && HARD_REGNO_MODE_OK (regno, mode))
2163 register int size1 = HARD_REGNO_NREGS (regno, mode);
2164 for (j = 1; j < size1 && ! TEST_HARD_REG_BIT (used, regno + j); j++);
2167 /* Mark that this register is in use between its birth and death
2169 post_mark_life (regno, mode, 1, born_index, dead_index);
2172 #ifndef REG_ALLOC_ORDER
2173 i += j; /* Skip starting points we know will lose */
2180 /* If we are just trying suggested register, we have just tried copy-
2181 suggested registers, and there are arithmetic-suggested registers,
2184 /* If it would be profitable to allocate a call-clobbered register
2185 and save and restore it around calls, do that. */
2186 if (just_try_suggested && qty_phys_num_copy_sugg[qty] != 0
2187 && qty_phys_num_sugg[qty] != 0)
2189 /* Don't try the copy-suggested regs again. */
2190 qty_phys_num_copy_sugg[qty] = 0;
2191 return find_free_reg (class, mode, qty, accept_call_clobbered, 1,
2192 born_index, dead_index);
2195 /* We need not check to see if the current function has nonlocal
2196 labels because we don't put any pseudos that are live over calls in
2197 registers in that case. */
2199 if (! accept_call_clobbered
2200 && flag_caller_saves
2201 && ! just_try_suggested
2202 && qty_n_calls_crossed[qty] != 0
2203 && CALLER_SAVE_PROFITABLE (qty_n_refs[qty], qty_n_calls_crossed[qty]))
2205 i = find_free_reg (class, mode, qty, 1, 0, born_index, dead_index);
2207 caller_save_needed = 1;
2213 /* Mark that REGNO with machine-mode MODE is live starting from the current
2214 insn (if LIFE is non-zero) or dead starting at the current insn (if LIFE
2218 mark_life (regno, mode, life)
2220 enum machine_mode mode;
2223 register int j = HARD_REGNO_NREGS (regno, mode);
2226 SET_HARD_REG_BIT (regs_live, regno + j);
2229 CLEAR_HARD_REG_BIT (regs_live, regno + j);
2232 /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE
2233 is non-zero) or dead (if LIFE is zero) from insn number BIRTH (inclusive)
2234 to insn number DEATH (exclusive). */
2237 post_mark_life (regno, mode, life, birth, death)
2239 enum machine_mode mode;
2240 int life, birth, death;
2242 register int j = HARD_REGNO_NREGS (regno, mode);
2244 register /* Declare it register if it's a scalar. */
2246 HARD_REG_SET this_reg;
2248 CLEAR_HARD_REG_SET (this_reg);
2250 SET_HARD_REG_BIT (this_reg, regno + j);
2253 while (birth < death)
2255 IOR_HARD_REG_SET (regs_live_at[birth], this_reg);
2259 while (birth < death)
2261 AND_COMPL_HARD_REG_SET (regs_live_at[birth], this_reg);
2266 /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0
2267 is the register being clobbered, and R1 is a register being used in
2268 the equivalent expression.
2270 If R1 dies in the block and has a REG_NO_CONFLICT note on every insn
2271 in which it is used, return 1.
2273 Otherwise, return 0. */
2276 no_conflict_p (insn, r0, r1)
2280 rtx note = find_reg_note (insn, REG_LIBCALL, NULL_RTX);
2283 /* If R1 is a hard register, return 0 since we handle this case
2284 when we scan the insns that actually use it. */
2287 || (GET_CODE (r1) == REG && REGNO (r1) < FIRST_PSEUDO_REGISTER)
2288 || (GET_CODE (r1) == SUBREG && GET_CODE (SUBREG_REG (r1)) == REG
2289 && REGNO (SUBREG_REG (r1)) < FIRST_PSEUDO_REGISTER))
2292 last = XEXP (note, 0);
2294 for (p = NEXT_INSN (insn); p && p != last; p = NEXT_INSN (p))
2295 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
2297 if (find_reg_note (p, REG_DEAD, r1))
2300 if (reg_mentioned_p (r1, PATTERN (p))
2301 && ! find_reg_note (p, REG_NO_CONFLICT, r1))
2308 #ifdef REGISTER_CONSTRAINTS
2310 /* Return the number of alternatives for which the constraint string P
2311 indicates that the operand must be equal to operand 0 and that no register
2320 int reg_allowed = 0;
2321 int num_matching_alts = 0;
2326 case '=': case '+': case '?':
2327 case '#': case '&': case '!':
2329 case '1': case '2': case '3': case '4':
2330 case 'm': case '<': case '>': case 'V': case 'o':
2331 case 'E': case 'F': case 'G': case 'H':
2332 case 's': case 'i': case 'n':
2333 case 'I': case 'J': case 'K': case 'L':
2334 case 'M': case 'N': case 'O': case 'P':
2335 #ifdef EXTRA_CONSTRAINT
2336 case 'Q': case 'R': case 'S': case 'T': case 'U':
2339 /* These don't say anything we care about. */
2343 if (found_zero && ! reg_allowed)
2344 num_matching_alts++;
2346 found_zero = reg_allowed = 0;
2360 if (found_zero && ! reg_allowed)
2361 num_matching_alts++;
2363 return num_matching_alts;
2365 #endif /* REGISTER_CONSTRAINTS */
2368 dump_local_alloc (file)
2372 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
2373 if (reg_renumber[i] != -1)
2374 fprintf (file, ";; Register %d in %d.\n", i, reg_renumber[i]);