1 /* Integrated Register Allocator (IRA) entry point.
2 Copyright (C) 2006, 2007, 2008, 2009, 2010, 2011
3 Free Software Foundation, Inc.
4 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* The integrated register allocator (IRA) is a
23 regional register allocator performing graph coloring on a top-down
24 traversal of nested regions. Graph coloring in a region is based
25 on Chaitin-Briggs algorithm. It is called integrated because
26 register coalescing, register live range splitting, and choosing a
27 better hard register are done on-the-fly during coloring. Register
28 coalescing and choosing a cheaper hard register is done by hard
29 register preferencing during hard register assigning. The live
30 range splitting is a byproduct of the regional register allocation.
32 Major IRA notions are:
34 o *Region* is a part of CFG where graph coloring based on
35 Chaitin-Briggs algorithm is done. IRA can work on any set of
36 nested CFG regions forming a tree. Currently the regions are
37 the entire function for the root region and natural loops for
38 the other regions. Therefore data structure representing a
39 region is called loop_tree_node.
41 o *Allocno class* is a register class used for allocation of
42 given allocno. It means that only hard register of given
43 register class can be assigned to given allocno. In reality,
44 even smaller subset of (*profitable*) hard registers can be
45 assigned. In rare cases, the subset can be even smaller
46 because our modification of Chaitin-Briggs algorithm requires
47 that sets of hard registers can be assigned to allocnos forms a
48 forest, i.e. the sets can be ordered in a way where any
49 previous set is not intersected with given set or is a superset
52 o *Pressure class* is a register class belonging to a set of
53 register classes containing all of the hard-registers available
54 for register allocation. The set of all pressure classes for a
55 target is defined in the corresponding machine-description file
56 according some criteria. Register pressure is calculated only
57 for pressure classes and it affects some IRA decisions as
58 forming allocation regions.
60 o *Allocno* represents the live range of a pseudo-register in a
61 region. Besides the obvious attributes like the corresponding
62 pseudo-register number, allocno class, conflicting allocnos and
63 conflicting hard-registers, there are a few allocno attributes
64 which are important for understanding the allocation algorithm:
66 - *Live ranges*. This is a list of ranges of *program points*
67 where the allocno lives. Program points represent places
68 where a pseudo can be born or become dead (there are
69 approximately two times more program points than the insns)
70 and they are represented by integers starting with 0. The
71 live ranges are used to find conflicts between allocnos.
72 They also play very important role for the transformation of
73 the IRA internal representation of several regions into a one
74 region representation. The later is used during the reload
75 pass work because each allocno represents all of the
76 corresponding pseudo-registers.
78 - *Hard-register costs*. This is a vector of size equal to the
79 number of available hard-registers of the allocno class. The
80 cost of a callee-clobbered hard-register for an allocno is
81 increased by the cost of save/restore code around the calls
82 through the given allocno's life. If the allocno is a move
83 instruction operand and another operand is a hard-register of
84 the allocno class, the cost of the hard-register is decreased
87 When an allocno is assigned, the hard-register with minimal
88 full cost is used. Initially, a hard-register's full cost is
89 the corresponding value from the hard-register's cost vector.
90 If the allocno is connected by a *copy* (see below) to
91 another allocno which has just received a hard-register, the
92 cost of the hard-register is decreased. Before choosing a
93 hard-register for an allocno, the allocno's current costs of
94 the hard-registers are modified by the conflict hard-register
95 costs of all of the conflicting allocnos which are not
98 - *Conflict hard-register costs*. This is a vector of the same
99 size as the hard-register costs vector. To permit an
100 unassigned allocno to get a better hard-register, IRA uses
101 this vector to calculate the final full cost of the
102 available hard-registers. Conflict hard-register costs of an
103 unassigned allocno are also changed with a change of the
104 hard-register cost of the allocno when a copy involving the
105 allocno is processed as described above. This is done to
106 show other unassigned allocnos that a given allocno prefers
107 some hard-registers in order to remove the move instruction
108 corresponding to the copy.
110 o *Cap*. If a pseudo-register does not live in a region but
111 lives in a nested region, IRA creates a special allocno called
112 a cap in the outer region. A region cap is also created for a
115 o *Copy*. Allocnos can be connected by copies. Copies are used
116 to modify hard-register costs for allocnos during coloring.
117 Such modifications reflects a preference to use the same
118 hard-register for the allocnos connected by copies. Usually
119 copies are created for move insns (in this case it results in
120 register coalescing). But IRA also creates copies for operands
121 of an insn which should be assigned to the same hard-register
122 due to constraints in the machine description (it usually
123 results in removing a move generated in reload to satisfy
124 the constraints) and copies referring to the allocno which is
125 the output operand of an instruction and the allocno which is
126 an input operand dying in the instruction (creation of such
127 copies results in less register shuffling). IRA *does not*
128 create copies between the same register allocnos from different
129 regions because we use another technique for propagating
130 hard-register preference on the borders of regions.
132 Allocnos (including caps) for the upper region in the region tree
133 *accumulate* information important for coloring from allocnos with
134 the same pseudo-register from nested regions. This includes
135 hard-register and memory costs, conflicts with hard-registers,
136 allocno conflicts, allocno copies and more. *Thus, attributes for
137 allocnos in a region have the same values as if the region had no
138 subregions*. It means that attributes for allocnos in the
139 outermost region corresponding to the function have the same values
140 as though the allocation used only one region which is the entire
141 function. It also means that we can look at IRA work as if the
142 first IRA did allocation for all function then it improved the
143 allocation for loops then their subloops and so on.
145 IRA major passes are:
147 o Building IRA internal representation which consists of the
150 * First, IRA builds regions and creates allocnos (file
151 ira-build.c) and initializes most of their attributes.
153 * Then IRA finds an allocno class for each allocno and
154 calculates its initial (non-accumulated) cost of memory and
155 each hard-register of its allocno class (file ira-cost.c).
157 * IRA creates live ranges of each allocno, calulates register
158 pressure for each pressure class in each region, sets up
159 conflict hard registers for each allocno and info about calls
160 the allocno lives through (file ira-lives.c).
162 * IRA removes low register pressure loops from the regions
163 mostly to speed IRA up (file ira-build.c).
165 * IRA propagates accumulated allocno info from lower region
166 allocnos to corresponding upper region allocnos (file
169 * IRA creates all caps (file ira-build.c).
171 * Having live-ranges of allocnos and their classes, IRA creates
172 conflicting allocnos for each allocno. Conflicting allocnos
173 are stored as a bit vector or array of pointers to the
174 conflicting allocnos whatever is more profitable (file
175 ira-conflicts.c). At this point IRA creates allocno copies.
177 o Coloring. Now IRA has all necessary info to start graph coloring
178 process. It is done in each region on top-down traverse of the
179 region tree (file ira-color.c). There are following subpasses:
181 * Finding profitable hard registers of corresponding allocno
182 class for each allocno. For example, only callee-saved hard
183 registers are frequently profitable for allocnos living
184 through colors. If the profitable hard register set of
185 allocno does not form a tree based on subset relation, we use
186 some approximation to form the tree. This approximation is
187 used to figure out trivial colorability of allocnos. The
188 approximation is a pretty rare case.
190 * Putting allocnos onto the coloring stack. IRA uses Briggs
191 optimistic coloring which is a major improvement over
192 Chaitin's coloring. Therefore IRA does not spill allocnos at
193 this point. There is some freedom in the order of putting
194 allocnos on the stack which can affect the final result of
195 the allocation. IRA uses some heuristics to improve the
198 We also use a modification of Chaitin-Briggs algorithm which
199 works for intersected register classes of allocnos. To
200 figure out trivial colorability of allocnos, the mentioned
201 above tree of hard register sets is used. To get an idea how
202 the algorithm works in i386 example, let us consider an
203 allocno to which any general hard register can be assigned.
204 If the allocno conflicts with eight allocnos to which only
205 EAX register can be assigned, given allocno is still
206 trivially colorable because all conflicting allocnos might be
207 assigned only to EAX and all other general hard registers are
210 To get an idea of the used trivial colorability criterion, it
211 is also useful to read article "Graph-Coloring Register
212 Allocation for Irregular Architectures" by Michael D. Smith
213 and Glen Holloway. Major difference between the article
214 approach and approach used in IRA is that Smith's approach
215 takes register classes only from machine description and IRA
216 calculate register classes from intermediate code too
217 (e.g. an explicit usage of hard registers in RTL code for
218 parameter passing can result in creation of additional
219 register classes which contain or exclude the hard
220 registers). That makes IRA approach useful for improving
221 coloring even for architectures with regular register files
222 and in fact some benchmarking shows the improvement for
223 regular class architectures is even bigger than for irregular
224 ones. Another difference is that Smith's approach chooses
225 intersection of classes of all insn operands in which a given
226 pseudo occurs. IRA can use bigger classes if it is still
227 more profitable than memory usage.
229 * Popping the allocnos from the stack and assigning them hard
230 registers. If IRA can not assign a hard register to an
231 allocno and the allocno is coalesced, IRA undoes the
232 coalescing and puts the uncoalesced allocnos onto the stack in
233 the hope that some such allocnos will get a hard register
234 separately. If IRA fails to assign hard register or memory
235 is more profitable for it, IRA spills the allocno. IRA
236 assigns the allocno the hard-register with minimal full
237 allocation cost which reflects the cost of usage of the
238 hard-register for the allocno and cost of usage of the
239 hard-register for allocnos conflicting with given allocno.
241 * Chaitin-Briggs coloring assigns as many pseudos as possible
242 to hard registers. After coloringh we try to improve
243 allocation with cost point of view. We improve the
244 allocation by spilling some allocnos and assigning the freed
245 hard registers to other allocnos if it decreases the overall
248 * After allono assigning in the region, IRA modifies the hard
249 register and memory costs for the corresponding allocnos in
250 the subregions to reflect the cost of possible loads, stores,
251 or moves on the border of the region and its subregions.
252 When default regional allocation algorithm is used
253 (-fira-algorithm=mixed), IRA just propagates the assignment
254 for allocnos if the register pressure in the region for the
255 corresponding pressure class is less than number of available
256 hard registers for given pressure class.
258 o Spill/restore code moving. When IRA performs an allocation
259 by traversing regions in top-down order, it does not know what
260 happens below in the region tree. Therefore, sometimes IRA
261 misses opportunities to perform a better allocation. A simple
262 optimization tries to improve allocation in a region having
263 subregions and containing in another region. If the
264 corresponding allocnos in the subregion are spilled, it spills
265 the region allocno if it is profitable. The optimization
266 implements a simple iterative algorithm performing profitable
267 transformations while they are still possible. It is fast in
268 practice, so there is no real need for a better time complexity
271 o Code change. After coloring, two allocnos representing the
272 same pseudo-register outside and inside a region respectively
273 may be assigned to different locations (hard-registers or
274 memory). In this case IRA creates and uses a new
275 pseudo-register inside the region and adds code to move allocno
276 values on the region's borders. This is done during top-down
277 traversal of the regions (file ira-emit.c). In some
278 complicated cases IRA can create a new allocno to move allocno
279 values (e.g. when a swap of values stored in two hard-registers
280 is needed). At this stage, the new allocno is marked as
281 spilled. IRA still creates the pseudo-register and the moves
282 on the region borders even when both allocnos were assigned to
283 the same hard-register. If the reload pass spills a
284 pseudo-register for some reason, the effect will be smaller
285 because another allocno will still be in the hard-register. In
286 most cases, this is better then spilling both allocnos. If
287 reload does not change the allocation for the two
288 pseudo-registers, the trivial move will be removed by
289 post-reload optimizations. IRA does not generate moves for
290 allocnos assigned to the same hard register when the default
291 regional allocation algorithm is used and the register pressure
292 in the region for the corresponding pressure class is less than
293 number of available hard registers for given pressure class.
294 IRA also does some optimizations to remove redundant stores and
295 to reduce code duplication on the region borders.
297 o Flattening internal representation. After changing code, IRA
298 transforms its internal representation for several regions into
299 one region representation (file ira-build.c). This process is
300 called IR flattening. Such process is more complicated than IR
301 rebuilding would be, but is much faster.
303 o After IR flattening, IRA tries to assign hard registers to all
304 spilled allocnos. This is impelemented by a simple and fast
305 priority coloring algorithm (see function
306 ira_reassign_conflict_allocnos::ira-color.c). Here new allocnos
307 created during the code change pass can be assigned to hard
310 o At the end IRA calls the reload pass. The reload pass
311 communicates with IRA through several functions in file
312 ira-color.c to improve its decisions in
314 * sharing stack slots for the spilled pseudos based on IRA info
315 about pseudo-register conflicts.
317 * reassigning hard-registers to all spilled pseudos at the end
318 of each reload iteration.
320 * choosing a better hard-register to spill based on IRA info
321 about pseudo-register live ranges and the register pressure
322 in places where the pseudo-register lives.
324 IRA uses a lot of data representing the target processors. These
325 data are initilized in file ira.c.
327 If function has no loops (or the loops are ignored when
328 -fira-algorithm=CB is used), we have classic Chaitin-Briggs
329 coloring (only instead of separate pass of coalescing, we use hard
330 register preferencing). In such case, IRA works much faster
331 because many things are not made (like IR flattening, the
332 spill/restore optimization, and the code change).
334 Literature is worth to read for better understanding the code:
336 o Preston Briggs, Keith D. Cooper, Linda Torczon. Improvements to
337 Graph Coloring Register Allocation.
339 o David Callahan, Brian Koblenz. Register allocation via
340 hierarchical graph coloring.
342 o Keith Cooper, Anshuman Dasgupta, Jason Eckhardt. Revisiting Graph
343 Coloring Register Allocation: A Study of the Chaitin-Briggs and
344 Callahan-Koblenz Algorithms.
346 o Guei-Yuan Lueh, Thomas Gross, and Ali-Reza Adl-Tabatabai. Global
347 Register Allocation Based on Graph Fusion.
349 o Michael D. Smith and Glenn Holloway. Graph-Coloring Register
350 Allocation for Irregular Architectures
352 o Vladimir Makarov. The Integrated Register Allocator for GCC.
354 o Vladimir Makarov. The top-down register allocator for irregular
355 register file architectures.
362 #include "coretypes.h"
371 #include "hard-reg-set.h"
372 #include "basic-block.h"
378 #include "tree-pass.h"
382 #include "diagnostic-core.h"
383 #include "integrate.h"
388 struct target_ira default_target_ira;
389 struct target_ira_int default_target_ira_int;
390 #if SWITCHABLE_TARGET
391 struct target_ira *this_target_ira = &default_target_ira;
392 struct target_ira_int *this_target_ira_int = &default_target_ira_int;
395 /* A modified value of flag `-fira-verbose' used internally. */
396 int internal_flag_ira_verbose;
398 /* Dump file of the allocator if it is not NULL. */
401 /* The number of elements in the following array. */
402 int ira_spilled_reg_stack_slots_num;
404 /* The following array contains info about spilled pseudo-registers
405 stack slots used in current function so far. */
406 struct ira_spilled_reg_stack_slot *ira_spilled_reg_stack_slots;
408 /* Correspondingly overall cost of the allocation, cost of the
409 allocnos assigned to hard-registers, cost of the allocnos assigned
410 to memory, cost of loads, stores and register move insns generated
411 for pseudo-register live range splitting (see ira-emit.c). */
412 int ira_overall_cost;
413 int ira_reg_cost, ira_mem_cost;
414 int ira_load_cost, ira_store_cost, ira_shuffle_cost;
415 int ira_move_loops_num, ira_additional_jumps_num;
417 /* All registers that can be eliminated. */
419 HARD_REG_SET eliminable_regset;
421 /* Temporary hard reg set used for a different calculation. */
422 static HARD_REG_SET temp_hard_regset;
426 /* The function sets up the map IRA_REG_MODE_HARD_REGSET. */
428 setup_reg_mode_hard_regset (void)
430 int i, m, hard_regno;
432 for (m = 0; m < NUM_MACHINE_MODES; m++)
433 for (hard_regno = 0; hard_regno < FIRST_PSEUDO_REGISTER; hard_regno++)
435 CLEAR_HARD_REG_SET (ira_reg_mode_hard_regset[hard_regno][m]);
436 for (i = hard_regno_nregs[hard_regno][m] - 1; i >= 0; i--)
437 if (hard_regno + i < FIRST_PSEUDO_REGISTER)
438 SET_HARD_REG_BIT (ira_reg_mode_hard_regset[hard_regno][m],
444 #define no_unit_alloc_regs \
445 (this_target_ira_int->x_no_unit_alloc_regs)
447 /* The function sets up the three arrays declared above. */
449 setup_class_hard_regs (void)
451 int cl, i, hard_regno, n;
452 HARD_REG_SET processed_hard_reg_set;
454 ira_assert (SHRT_MAX >= FIRST_PSEUDO_REGISTER);
455 for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--)
457 COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
458 AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
459 CLEAR_HARD_REG_SET (processed_hard_reg_set);
460 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
462 ira_non_ordered_class_hard_regs[cl][i] = -1;
463 ira_class_hard_reg_index[cl][i] = -1;
465 for (n = 0, i = 0; i < FIRST_PSEUDO_REGISTER; i++)
467 #ifdef REG_ALLOC_ORDER
468 hard_regno = reg_alloc_order[i];
472 if (TEST_HARD_REG_BIT (processed_hard_reg_set, hard_regno))
474 SET_HARD_REG_BIT (processed_hard_reg_set, hard_regno);
475 if (! TEST_HARD_REG_BIT (temp_hard_regset, hard_regno))
476 ira_class_hard_reg_index[cl][hard_regno] = -1;
479 ira_class_hard_reg_index[cl][hard_regno] = n;
480 ira_class_hard_regs[cl][n++] = hard_regno;
483 ira_class_hard_regs_num[cl] = n;
484 for (n = 0, i = 0; i < FIRST_PSEUDO_REGISTER; i++)
485 if (TEST_HARD_REG_BIT (temp_hard_regset, i))
486 ira_non_ordered_class_hard_regs[cl][n++] = i;
487 ira_assert (ira_class_hard_regs_num[cl] == n);
491 /* Set up IRA_AVAILABLE_CLASS_REGS. */
493 setup_available_class_regs (void)
497 memset (ira_available_class_regs, 0, sizeof (ira_available_class_regs));
498 for (i = 0; i < N_REG_CLASSES; i++)
500 COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[i]);
501 AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
502 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
503 if (TEST_HARD_REG_BIT (temp_hard_regset, j))
504 ira_available_class_regs[i]++;
508 /* Set up global variables defining info about hard registers for the
509 allocation. These depend on USE_HARD_FRAME_P whose TRUE value means
510 that we can use the hard frame pointer for the allocation. */
512 setup_alloc_regs (bool use_hard_frame_p)
514 #ifdef ADJUST_REG_ALLOC_ORDER
515 ADJUST_REG_ALLOC_ORDER;
517 COPY_HARD_REG_SET (no_unit_alloc_regs, fixed_reg_set);
518 if (! use_hard_frame_p)
519 SET_HARD_REG_BIT (no_unit_alloc_regs, HARD_FRAME_POINTER_REGNUM);
520 setup_class_hard_regs ();
521 setup_available_class_regs ();
526 #define alloc_reg_class_subclasses \
527 (this_target_ira_int->x_alloc_reg_class_subclasses)
529 /* Initialize the table of subclasses of each reg class. */
531 setup_reg_subclasses (void)
534 HARD_REG_SET temp_hard_regset2;
536 for (i = 0; i < N_REG_CLASSES; i++)
537 for (j = 0; j < N_REG_CLASSES; j++)
538 alloc_reg_class_subclasses[i][j] = LIM_REG_CLASSES;
540 for (i = 0; i < N_REG_CLASSES; i++)
542 if (i == (int) NO_REGS)
545 COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[i]);
546 AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
547 if (hard_reg_set_empty_p (temp_hard_regset))
549 for (j = 0; j < N_REG_CLASSES; j++)
554 COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[j]);
555 AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs);
556 if (! hard_reg_set_subset_p (temp_hard_regset,
559 p = &alloc_reg_class_subclasses[j][0];
560 while (*p != LIM_REG_CLASSES) p++;
561 *p = (enum reg_class) i;
568 /* Set up IRA_MEMORY_MOVE_COST and IRA_MAX_MEMORY_MOVE_COST. */
570 setup_class_subset_and_memory_move_costs (void)
572 int cl, cl2, mode, cost;
573 HARD_REG_SET temp_hard_regset2;
575 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
576 ira_memory_move_cost[mode][NO_REGS][0]
577 = ira_memory_move_cost[mode][NO_REGS][1] = SHRT_MAX;
578 for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--)
580 if (cl != (int) NO_REGS)
581 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
583 ira_max_memory_move_cost[mode][cl][0]
584 = ira_memory_move_cost[mode][cl][0]
585 = memory_move_cost ((enum machine_mode) mode,
586 (enum reg_class) cl, false);
587 ira_max_memory_move_cost[mode][cl][1]
588 = ira_memory_move_cost[mode][cl][1]
589 = memory_move_cost ((enum machine_mode) mode,
590 (enum reg_class) cl, true);
591 /* Costs for NO_REGS are used in cost calculation on the
592 1st pass when the preferred register classes are not
593 known yet. In this case we take the best scenario. */
594 if (ira_memory_move_cost[mode][NO_REGS][0]
595 > ira_memory_move_cost[mode][cl][0])
596 ira_max_memory_move_cost[mode][NO_REGS][0]
597 = ira_memory_move_cost[mode][NO_REGS][0]
598 = ira_memory_move_cost[mode][cl][0];
599 if (ira_memory_move_cost[mode][NO_REGS][1]
600 > ira_memory_move_cost[mode][cl][1])
601 ira_max_memory_move_cost[mode][NO_REGS][1]
602 = ira_memory_move_cost[mode][NO_REGS][1]
603 = ira_memory_move_cost[mode][cl][1];
606 for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--)
607 for (cl2 = (int) N_REG_CLASSES - 1; cl2 >= 0; cl2--)
609 COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
610 AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
611 COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl2]);
612 AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs);
613 ira_class_subset_p[cl][cl2]
614 = hard_reg_set_subset_p (temp_hard_regset, temp_hard_regset2);
615 if (! hard_reg_set_empty_p (temp_hard_regset2)
616 && hard_reg_set_subset_p (reg_class_contents[cl2],
617 reg_class_contents[cl]))
618 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
620 cost = ira_memory_move_cost[mode][cl2][0];
621 if (cost > ira_max_memory_move_cost[mode][cl][0])
622 ira_max_memory_move_cost[mode][cl][0] = cost;
623 cost = ira_memory_move_cost[mode][cl2][1];
624 if (cost > ira_max_memory_move_cost[mode][cl][1])
625 ira_max_memory_move_cost[mode][cl][1] = cost;
628 for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--)
629 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
631 ira_memory_move_cost[mode][cl][0]
632 = ira_max_memory_move_cost[mode][cl][0];
633 ira_memory_move_cost[mode][cl][1]
634 = ira_max_memory_move_cost[mode][cl][1];
636 setup_reg_subclasses ();
641 /* Define the following macro if allocation through malloc if
643 #define IRA_NO_OBSTACK
645 #ifndef IRA_NO_OBSTACK
646 /* Obstack used for storing all dynamic data (except bitmaps) of the
648 static struct obstack ira_obstack;
651 /* Obstack used for storing all bitmaps of the IRA. */
652 static struct bitmap_obstack ira_bitmap_obstack;
654 /* Allocate memory of size LEN for IRA data. */
656 ira_allocate (size_t len)
660 #ifndef IRA_NO_OBSTACK
661 res = obstack_alloc (&ira_obstack, len);
668 /* Free memory ADDR allocated for IRA data. */
670 ira_free (void *addr ATTRIBUTE_UNUSED)
672 #ifndef IRA_NO_OBSTACK
680 /* Allocate and returns bitmap for IRA. */
682 ira_allocate_bitmap (void)
684 return BITMAP_ALLOC (&ira_bitmap_obstack);
687 /* Free bitmap B allocated for IRA. */
689 ira_free_bitmap (bitmap b ATTRIBUTE_UNUSED)
696 /* Output information about allocation of all allocnos (except for
697 caps) into file F. */
699 ira_print_disposition (FILE *f)
705 fprintf (f, "Disposition:");
706 max_regno = max_reg_num ();
707 for (n = 0, i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
708 for (a = ira_regno_allocno_map[i];
710 a = ALLOCNO_NEXT_REGNO_ALLOCNO (a))
715 fprintf (f, " %4d:r%-4d", ALLOCNO_NUM (a), ALLOCNO_REGNO (a));
716 if ((bb = ALLOCNO_LOOP_TREE_NODE (a)->bb) != NULL)
717 fprintf (f, "b%-3d", bb->index);
719 fprintf (f, "l%-3d", ALLOCNO_LOOP_TREE_NODE (a)->loop->num);
720 if (ALLOCNO_HARD_REGNO (a) >= 0)
721 fprintf (f, " %3d", ALLOCNO_HARD_REGNO (a));
728 /* Outputs information about allocation of all allocnos into
731 ira_debug_disposition (void)
733 ira_print_disposition (stderr);
738 /* Set up ira_stack_reg_pressure_class which is the biggest pressure
739 register class containing stack registers or NO_REGS if there are
740 no stack registers. To find this class, we iterate through all
741 register pressure classes and choose the first register pressure
742 class containing all the stack registers and having the biggest
745 setup_stack_reg_pressure_class (void)
747 ira_stack_reg_pressure_class = NO_REGS;
752 HARD_REG_SET temp_hard_regset2;
754 CLEAR_HARD_REG_SET (temp_hard_regset);
755 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
756 SET_HARD_REG_BIT (temp_hard_regset, i);
758 for (i = 0; i < ira_pressure_classes_num; i++)
760 cl = ira_pressure_classes[i];
761 COPY_HARD_REG_SET (temp_hard_regset2, temp_hard_regset);
762 AND_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl]);
763 size = hard_reg_set_size (temp_hard_regset2);
767 ira_stack_reg_pressure_class = cl;
774 /* Find pressure classes which are register classes for which we
775 calculate register pressure in IRA, register pressure sensitive
776 insn scheduling, and register pressure sensitive loop invariant
779 To make register pressure calculation easy, we always use
780 non-intersected register pressure classes. A move of hard
781 registers from one register pressure class is not more expensive
782 than load and store of the hard registers. Most likely an allocno
783 class will be a subset of a register pressure class and in many
784 cases a register pressure class. That makes usage of register
785 pressure classes a good approximation to find a high register
788 setup_pressure_classes (void)
790 int cost, i, n, curr;
792 enum reg_class pressure_classes[N_REG_CLASSES];
794 HARD_REG_SET temp_hard_regset2;
798 for (cl = 0; cl < N_REG_CLASSES; cl++)
800 if (ira_available_class_regs[cl] == 0)
802 /* Check that the moves between any hard registers of the
803 current class are not more expensive for a legal mode than
804 load/store of the hard registers of the current class. Such
805 class is a potential candidate to be a register pressure
807 for (m = 0; m < NUM_MACHINE_MODES; m++)
809 COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
810 AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
811 AND_COMPL_HARD_REG_SET (temp_hard_regset,
812 ira_prohibited_class_mode_regs[cl][m]);
813 if (hard_reg_set_empty_p (temp_hard_regset))
815 ira_init_register_move_cost_if_necessary ((enum machine_mode) m);
816 cost = ira_register_move_cost[m][cl][cl];
817 if (cost <= ira_max_memory_move_cost[m][cl][1]
818 || cost <= ira_max_memory_move_cost[m][cl][0])
821 if (m >= NUM_MACHINE_MODES)
825 COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
826 AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
827 /* Remove so far added pressure classes which are subset of the
828 current candidate class. Prefer GENERAL_REGS as a pressure
829 register class to another class containing the same
830 allocatable hard registers. We do this because machine
831 dependent cost hooks might give wrong costs for the latter
832 class but always give the right cost for the former class
834 for (i = 0; i < n; i++)
836 cl2 = pressure_classes[i];
837 COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl2]);
838 AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs);
839 if (hard_reg_set_subset_p (temp_hard_regset, temp_hard_regset2)
840 && (! hard_reg_set_equal_p (temp_hard_regset, temp_hard_regset2)
841 || cl2 == (int) GENERAL_REGS))
843 pressure_classes[curr++] = (enum reg_class) cl2;
847 if (hard_reg_set_subset_p (temp_hard_regset2, temp_hard_regset)
848 && (! hard_reg_set_equal_p (temp_hard_regset2, temp_hard_regset)
849 || cl == (int) GENERAL_REGS))
851 pressure_classes[curr++] = (enum reg_class) cl2;
853 /* If the current candidate is a subset of a so far added
854 pressure class, don't add it to the list of the pressure
857 pressure_classes[curr++] = (enum reg_class) cl;
860 #ifdef ENABLE_IRA_CHECKING
861 /* Check pressure classes correctness: here we check that hard
862 registers from all register pressure classes contains all hard
863 registers available for the allocation. */
864 CLEAR_HARD_REG_SET (temp_hard_regset);
865 CLEAR_HARD_REG_SET (temp_hard_regset2);
866 for (cl = 0; cl <= LIM_REG_CLASSES; cl++)
868 for (i = 0; i < n; i++)
869 if ((int) pressure_classes[i] == cl)
871 IOR_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl]);
873 IOR_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
875 AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
876 AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs);
877 ira_assert (hard_reg_set_subset_p (temp_hard_regset2, temp_hard_regset));
879 ira_pressure_classes_num = 0;
880 for (i = 0; i < n; i++)
882 cl = (int) pressure_classes[i];
883 ira_reg_pressure_class_p[cl] = true;
884 ira_pressure_classes[ira_pressure_classes_num++] = (enum reg_class) cl;
886 setup_stack_reg_pressure_class ();
889 /* Set up IRA_ALLOCNO_CLASSES, IRA_ALLOCNO_CLASSES_NUM,
890 IRA_IMPORTANT_CLASSES, and IRA_IMPORTANT_CLASSES_NUM.
892 Target may have many subtargets and not all target hard regiters can
893 be used for allocation, e.g. x86 port in 32-bit mode can not use
894 hard registers introduced in x86-64 like r8-r15). Some classes
895 might have the same allocatable hard registers, e.g. INDEX_REGS
896 and GENERAL_REGS in x86 port in 32-bit mode. To decrease different
897 calculations efforts we introduce allocno classes which contain
898 unique non-empty sets of allocatable hard-registers.
900 Pseudo class cost calculation in ira-costs.c is very expensive.
901 Therefore we are trying to decrease number of classes involved in
902 such calculation. Register classes used in the cost calculation
903 are called important classes. They are allocno classes and other
904 non-empty classes whose allocatable hard register sets are inside
905 of an allocno class hard register set. From the first sight, it
906 looks like that they are just allocno classes. It is not true. In
907 example of x86-port in 32-bit mode, allocno classes will contain
908 GENERAL_REGS but not LEGACY_REGS (because allocatable hard
909 registers are the same for the both classes). The important
910 classes will contain GENERAL_REGS and LEGACY_REGS. It is done
911 because a machine description insn constraint may refers for
912 LEGACY_REGS and code in ira-costs.c is mostly base on investigation
913 of the insn constraints. */
915 setup_allocno_and_important_classes (void)
919 HARD_REG_SET temp_hard_regset2;
920 static enum reg_class classes[LIM_REG_CLASSES + 1];
923 /* Collect classes which contain unique sets of allocatable hard
924 registers. Prefer GENERAL_REGS to other classes containing the
925 same set of hard registers. */
926 for (i = 0; i <= LIM_REG_CLASSES; i++)
928 COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[i]);
929 AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
930 for (j = 0; j < n; j++)
933 COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl]);
934 AND_COMPL_HARD_REG_SET (temp_hard_regset2,
936 if (hard_reg_set_equal_p (temp_hard_regset,
941 classes[n++] = (enum reg_class) i;
942 else if (i == GENERAL_REGS)
943 /* Prefer general regs. For i386 example, it means that
944 we prefer GENERAL_REGS over INDEX_REGS or LEGACY_REGS
945 (all of them consists of the same available hard
947 classes[j] = (enum reg_class) i;
949 classes[n] = LIM_REG_CLASSES;
951 /* Set up classes which can be used for allocnos as classes
952 conatining non-empty unique sets of allocatable hard
954 ira_allocno_classes_num = 0;
955 for (i = 0; (cl = classes[i]) != LIM_REG_CLASSES; i++)
957 COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
958 AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
959 if (hard_reg_set_empty_p (temp_hard_regset))
961 ira_allocno_classes[ira_allocno_classes_num++] = (enum reg_class) cl;
963 ira_important_classes_num = 0;
964 /* Add non-allocno classes containing to non-empty set of
965 allocatable hard regs. */
966 for (cl = 0; cl < N_REG_CLASSES; cl++)
968 COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
969 AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
970 if (! hard_reg_set_empty_p (temp_hard_regset))
973 for (j = 0; j < ira_allocno_classes_num; j++)
975 COPY_HARD_REG_SET (temp_hard_regset2,
976 reg_class_contents[ira_allocno_classes[j]]);
977 AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs);
978 if ((enum reg_class) cl == ira_allocno_classes[j])
980 else if (hard_reg_set_subset_p (temp_hard_regset,
984 if (set_p && j >= ira_allocno_classes_num)
985 ira_important_classes[ira_important_classes_num++]
986 = (enum reg_class) cl;
989 /* Now add allocno classes to the important classes. */
990 for (j = 0; j < ira_allocno_classes_num; j++)
991 ira_important_classes[ira_important_classes_num++]
992 = ira_allocno_classes[j];
993 for (cl = 0; cl < N_REG_CLASSES; cl++)
995 ira_reg_allocno_class_p[cl] = false;
996 ira_reg_pressure_class_p[cl] = false;
998 for (j = 0; j < ira_allocno_classes_num; j++)
999 ira_reg_allocno_class_p[ira_allocno_classes[j]] = true;
1000 setup_pressure_classes ();
1003 /* Setup translation in CLASS_TRANSLATE of all classes into a class
1004 given by array CLASSES of length CLASSES_NUM. The function is used
1005 make translation any reg class to an allocno class or to an
1006 pressure class. This translation is necessary for some
1007 calculations when we can use only allocno or pressure classes and
1008 such translation represents an approximate representation of all
1011 The translation in case when allocatable hard register set of a
1012 given class is subset of allocatable hard register set of a class
1013 in CLASSES is pretty simple. We use smallest classes from CLASSES
1014 containing a given class. If allocatable hard register set of a
1015 given class is not a subset of any corresponding set of a class
1016 from CLASSES, we use the cheapest (with load/store point of view)
1017 class from CLASSES whose set intersects with given class set */
1019 setup_class_translate_array (enum reg_class *class_translate,
1020 int classes_num, enum reg_class *classes)
1023 enum reg_class aclass, best_class, *cl_ptr;
1024 int i, cost, min_cost, best_cost;
1026 for (cl = 0; cl < N_REG_CLASSES; cl++)
1027 class_translate[cl] = NO_REGS;
1029 for (i = 0; i < classes_num; i++)
1031 aclass = classes[i];
1032 for (cl_ptr = &alloc_reg_class_subclasses[aclass][0];
1033 (cl = *cl_ptr) != LIM_REG_CLASSES;
1035 if (class_translate[cl] == NO_REGS)
1036 class_translate[cl] = aclass;
1037 class_translate[aclass] = aclass;
1039 /* For classes which are not fully covered by one of given classes
1040 (in other words covered by more one given class), use the
1042 for (cl = 0; cl < N_REG_CLASSES; cl++)
1044 if (cl == NO_REGS || class_translate[cl] != NO_REGS)
1046 best_class = NO_REGS;
1047 best_cost = INT_MAX;
1048 for (i = 0; i < classes_num; i++)
1050 aclass = classes[i];
1051 COPY_HARD_REG_SET (temp_hard_regset,
1052 reg_class_contents[aclass]);
1053 AND_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
1054 AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
1055 if (! hard_reg_set_empty_p (temp_hard_regset))
1058 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
1060 cost = (ira_memory_move_cost[mode][cl][0]
1061 + ira_memory_move_cost[mode][cl][1]);
1062 if (min_cost > cost)
1065 if (best_class == NO_REGS || best_cost > min_cost)
1067 best_class = aclass;
1068 best_cost = min_cost;
1072 class_translate[cl] = best_class;
1076 /* Set up array IRA_ALLOCNO_CLASS_TRANSLATE and
1077 IRA_PRESSURE_CLASS_TRANSLATE. */
1079 setup_class_translate (void)
1081 setup_class_translate_array (ira_allocno_class_translate,
1082 ira_allocno_classes_num, ira_allocno_classes);
1083 setup_class_translate_array (ira_pressure_class_translate,
1084 ira_pressure_classes_num, ira_pressure_classes);
1087 /* Order numbers of allocno classes in original target allocno class
1088 array, -1 for non-allocno classes. */
1089 static int allocno_class_order[N_REG_CLASSES];
1091 /* The function used to sort the important classes. */
1093 comp_reg_classes_func (const void *v1p, const void *v2p)
1095 enum reg_class cl1 = *(const enum reg_class *) v1p;
1096 enum reg_class cl2 = *(const enum reg_class *) v2p;
1097 enum reg_class tcl1, tcl2;
1100 tcl1 = ira_allocno_class_translate[cl1];
1101 tcl2 = ira_allocno_class_translate[cl2];
1102 if (tcl1 != NO_REGS && tcl2 != NO_REGS
1103 && (diff = allocno_class_order[tcl1] - allocno_class_order[tcl2]) != 0)
1105 return (int) cl1 - (int) cl2;
1108 /* For correct work of function setup_reg_class_relation we need to
1109 reorder important classes according to the order of their allocno
1110 classes. It places important classes containing the same
1111 allocatable hard register set adjacent to each other and allocno
1112 class with the allocatable hard register set right after the other
1113 important classes with the same set.
1115 In example from comments of function
1116 setup_allocno_and_important_classes, it places LEGACY_REGS and
1117 GENERAL_REGS close to each other and GENERAL_REGS is after
1120 reorder_important_classes (void)
1124 for (i = 0; i < N_REG_CLASSES; i++)
1125 allocno_class_order[i] = -1;
1126 for (i = 0; i < ira_allocno_classes_num; i++)
1127 allocno_class_order[ira_allocno_classes[i]] = i;
1128 qsort (ira_important_classes, ira_important_classes_num,
1129 sizeof (enum reg_class), comp_reg_classes_func);
1130 for (i = 0; i < ira_important_classes_num; i++)
1131 ira_important_class_nums[ira_important_classes[i]] = i;
1134 /* Set up IRA_REG_CLASS_SUBUNION, IRA_REG_CLASS_SUPERUNION,
1135 IRA_REG_CLASS_SUPER_CLASSES, IRA_REG_CLASSES_INTERSECT, and
1136 IRA_REG_CLASSES_INTERSECT_P. For the meaning of the relations,
1137 please see corresponding comments in ira-int.h. */
1139 setup_reg_class_relations (void)
1141 int i, cl1, cl2, cl3;
1142 HARD_REG_SET intersection_set, union_set, temp_set2;
1143 bool important_class_p[N_REG_CLASSES];
1145 memset (important_class_p, 0, sizeof (important_class_p));
1146 for (i = 0; i < ira_important_classes_num; i++)
1147 important_class_p[ira_important_classes[i]] = true;
1148 for (cl1 = 0; cl1 < N_REG_CLASSES; cl1++)
1150 ira_reg_class_super_classes[cl1][0] = LIM_REG_CLASSES;
1151 for (cl2 = 0; cl2 < N_REG_CLASSES; cl2++)
1153 ira_reg_classes_intersect_p[cl1][cl2] = false;
1154 ira_reg_class_intersect[cl1][cl2] = NO_REGS;
1155 COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl1]);
1156 AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
1157 COPY_HARD_REG_SET (temp_set2, reg_class_contents[cl2]);
1158 AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs);
1159 if (hard_reg_set_empty_p (temp_hard_regset)
1160 && hard_reg_set_empty_p (temp_set2))
1162 /* The both classes have no allocatable hard registers
1163 -- take all class hard registers into account and use
1164 reg_class_subunion and reg_class_superunion. */
1167 cl3 = reg_class_subclasses[cl1][i];
1168 if (cl3 == LIM_REG_CLASSES)
1170 if (reg_class_subset_p (ira_reg_class_intersect[cl1][cl2],
1171 (enum reg_class) cl3))
1172 ira_reg_class_intersect[cl1][cl2] = (enum reg_class) cl3;
1174 ira_reg_class_subunion[cl1][cl2] = reg_class_subunion[cl1][cl2];
1175 ira_reg_class_superunion[cl1][cl2] = reg_class_superunion[cl1][cl2];
1178 ira_reg_classes_intersect_p[cl1][cl2]
1179 = hard_reg_set_intersect_p (temp_hard_regset, temp_set2);
1180 if (important_class_p[cl1] && important_class_p[cl2]
1181 && hard_reg_set_subset_p (temp_hard_regset, temp_set2))
1183 /* CL1 and CL2 are important classes and CL1 allocatable
1184 hard register set is inside of CL2 allocatable hard
1185 registers -- make CL1 a superset of CL2. */
1188 p = &ira_reg_class_super_classes[cl1][0];
1189 while (*p != LIM_REG_CLASSES)
1191 *p++ = (enum reg_class) cl2;
1192 *p = LIM_REG_CLASSES;
1194 ira_reg_class_subunion[cl1][cl2] = NO_REGS;
1195 ira_reg_class_superunion[cl1][cl2] = NO_REGS;
1196 COPY_HARD_REG_SET (intersection_set, reg_class_contents[cl1]);
1197 AND_HARD_REG_SET (intersection_set, reg_class_contents[cl2]);
1198 AND_COMPL_HARD_REG_SET (intersection_set, no_unit_alloc_regs);
1199 COPY_HARD_REG_SET (union_set, reg_class_contents[cl1]);
1200 IOR_HARD_REG_SET (union_set, reg_class_contents[cl2]);
1201 AND_COMPL_HARD_REG_SET (union_set, no_unit_alloc_regs);
1202 for (i = 0; i < ira_important_classes_num; i++)
1204 cl3 = ira_important_classes[i];
1205 COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl3]);
1206 AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
1207 if (hard_reg_set_subset_p (temp_hard_regset, intersection_set))
1209 /* CL3 allocatable hard register set is inside of
1210 intersection of allocatable hard register sets
1214 reg_class_contents[(int)
1215 ira_reg_class_intersect[cl1][cl2]]);
1216 AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs);
1217 if (! hard_reg_set_subset_p (temp_hard_regset, temp_set2)
1218 /* If the allocatable hard register sets are the
1219 same, prefer GENERAL_REGS or the smallest
1220 class for debugging purposes. */
1221 || (hard_reg_set_equal_p (temp_hard_regset, temp_set2)
1222 && (cl3 == GENERAL_REGS
1223 || (ira_reg_class_intersect[cl1][cl2] != GENERAL_REGS
1224 && hard_reg_set_subset_p
1225 (reg_class_contents[cl3],
1227 [(int) ira_reg_class_intersect[cl1][cl2]])))))
1228 ira_reg_class_intersect[cl1][cl2] = (enum reg_class) cl3;
1230 if (hard_reg_set_subset_p (temp_hard_regset, union_set))
1232 /* CL3 allocatbale hard register set is inside of
1233 union of allocatable hard register sets of CL1
1237 reg_class_contents[(int) ira_reg_class_subunion[cl1][cl2]]);
1238 AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs);
1239 if (ira_reg_class_subunion[cl1][cl2] == NO_REGS
1240 || (hard_reg_set_subset_p (temp_set2, temp_hard_regset)
1242 && (! hard_reg_set_equal_p (temp_set2,
1244 || cl3 == GENERAL_REGS
1245 /* If the allocatable hard register sets are the
1246 same, prefer GENERAL_REGS or the smallest
1247 class for debugging purposes. */
1248 || (ira_reg_class_subunion[cl1][cl2] != GENERAL_REGS
1249 && hard_reg_set_subset_p
1250 (reg_class_contents[cl3],
1252 [(int) ira_reg_class_subunion[cl1][cl2]])))))
1253 ira_reg_class_subunion[cl1][cl2] = (enum reg_class) cl3;
1255 if (hard_reg_set_subset_p (union_set, temp_hard_regset))
1257 /* CL3 allocatable hard register set contains union
1258 of allocatable hard register sets of CL1 and
1262 reg_class_contents[(int) ira_reg_class_superunion[cl1][cl2]]);
1263 AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs);
1264 if (ira_reg_class_superunion[cl1][cl2] == NO_REGS
1265 || (hard_reg_set_subset_p (temp_hard_regset, temp_set2)
1267 && (! hard_reg_set_equal_p (temp_set2,
1269 || cl3 == GENERAL_REGS
1270 /* If the allocatable hard register sets are the
1271 same, prefer GENERAL_REGS or the smallest
1272 class for debugging purposes. */
1273 || (ira_reg_class_superunion[cl1][cl2] != GENERAL_REGS
1274 && hard_reg_set_subset_p
1275 (reg_class_contents[cl3],
1277 [(int) ira_reg_class_superunion[cl1][cl2]])))))
1278 ira_reg_class_superunion[cl1][cl2] = (enum reg_class) cl3;
1285 /* Output all possible allocno classes and the translation map into
1288 print_classes (FILE *f, bool pressure_p)
1290 int classes_num = (pressure_p
1291 ? ira_pressure_classes_num : ira_allocno_classes_num);
1292 enum reg_class *classes = (pressure_p
1293 ? ira_pressure_classes : ira_allocno_classes);
1294 enum reg_class *class_translate = (pressure_p
1295 ? ira_pressure_class_translate
1296 : ira_allocno_class_translate);
1297 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1300 fprintf (f, "%s classes:\n", pressure_p ? "Pressure" : "Allocno");
1301 for (i = 0; i < classes_num; i++)
1302 fprintf (f, " %s", reg_class_names[classes[i]]);
1303 fprintf (f, "\nClass translation:\n");
1304 for (i = 0; i < N_REG_CLASSES; i++)
1305 fprintf (f, " %s -> %s\n", reg_class_names[i],
1306 reg_class_names[class_translate[i]]);
1309 /* Output all possible allocno and translation classes and the
1310 translation maps into stderr. */
1312 ira_debug_allocno_classes (void)
1314 print_classes (stderr, false);
1315 print_classes (stderr, true);
1318 /* Set up different arrays concerning class subsets, allocno and
1319 important classes. */
1321 find_reg_classes (void)
1323 setup_allocno_and_important_classes ();
1324 setup_class_translate ();
1325 reorder_important_classes ();
1326 setup_reg_class_relations ();
1331 /* Set up the array above. */
1333 setup_hard_regno_aclass (void)
1337 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1340 ira_hard_regno_allocno_class[i]
1341 = (TEST_HARD_REG_BIT (no_unit_alloc_regs, i)
1343 : ira_allocno_class_translate[REGNO_REG_CLASS (i)]);
1347 ira_hard_regno_allocno_class[i] = NO_REGS;
1348 for (j = 0; j < ira_allocno_classes_num; j++)
1350 cl = ira_allocno_classes[j];
1351 if (ira_class_hard_reg_index[cl][i] >= 0)
1353 ira_hard_regno_allocno_class[i] = cl;
1363 /* Form IRA_REG_CLASS_MAX_NREGS and IRA_REG_CLASS_MIN_NREGS maps. */
1365 setup_reg_class_nregs (void)
1369 for (m = 0; m < MAX_MACHINE_MODE; m++)
1371 for (cl = 0; cl < N_REG_CLASSES; cl++)
1372 ira_reg_class_max_nregs[cl][m]
1373 = ira_reg_class_min_nregs[cl][m]
1374 = CLASS_MAX_NREGS ((enum reg_class) cl, (enum machine_mode) m);
1375 for (cl = 0; cl < N_REG_CLASSES; cl++)
1377 (cl2 = alloc_reg_class_subclasses[cl][i]) != LIM_REG_CLASSES;
1379 if (ira_reg_class_min_nregs[cl2][m]
1380 < ira_reg_class_min_nregs[cl][m])
1381 ira_reg_class_min_nregs[cl][m] = ira_reg_class_min_nregs[cl2][m];
1387 /* Set up IRA_PROHIBITED_CLASS_MODE_REGS. */
1389 setup_prohibited_class_mode_regs (void)
1391 int j, k, hard_regno, cl;
1393 for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--)
1395 for (j = 0; j < NUM_MACHINE_MODES; j++)
1397 CLEAR_HARD_REG_SET (ira_prohibited_class_mode_regs[cl][j]);
1398 for (k = ira_class_hard_regs_num[cl] - 1; k >= 0; k--)
1400 hard_regno = ira_class_hard_regs[cl][k];
1401 if (! HARD_REGNO_MODE_OK (hard_regno, (enum machine_mode) j))
1402 SET_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j],
1409 /* Clarify IRA_PROHIBITED_CLASS_MODE_REGS by excluding hard registers
1410 spanning from one register pressure class to another one. It is
1411 called after defining the pressure classes. */
1413 clarify_prohibited_class_mode_regs (void)
1415 int j, k, hard_regno, cl, pclass, nregs;
1417 for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--)
1418 for (j = 0; j < NUM_MACHINE_MODES; j++)
1419 for (k = ira_class_hard_regs_num[cl] - 1; k >= 0; k--)
1421 hard_regno = ira_class_hard_regs[cl][k];
1422 if (TEST_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], hard_regno))
1424 nregs = hard_regno_nregs[hard_regno][j];
1425 pclass = ira_pressure_class_translate[REGNO_REG_CLASS (hard_regno)];
1426 for (nregs-- ;nregs >= 0; nregs--)
1427 if (((enum reg_class) pclass
1428 != ira_pressure_class_translate[REGNO_REG_CLASS
1429 (hard_regno + nregs)]))
1431 SET_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j],
1440 /* Allocate and initialize IRA_REGISTER_MOVE_COST,
1441 IRA_MAX_REGISTER_MOVE_COST, IRA_MAY_MOVE_IN_COST,
1442 IRA_MAY_MOVE_OUT_COST, IRA_MAX_MAY_MOVE_IN_COST, and
1443 IRA_MAX_MAY_MOVE_OUT_COST for MODE if it is not done yet. */
1445 ira_init_register_move_cost (enum machine_mode mode)
1449 ira_assert (ira_register_move_cost[mode] == NULL
1450 && ira_max_register_move_cost[mode] == NULL
1451 && ira_may_move_in_cost[mode] == NULL
1452 && ira_may_move_out_cost[mode] == NULL
1453 && ira_max_may_move_in_cost[mode] == NULL
1454 && ira_max_may_move_out_cost[mode] == NULL);
1455 if (move_cost[mode] == NULL)
1456 init_move_cost (mode);
1457 ira_register_move_cost[mode] = move_cost[mode];
1458 /* Don't use ira_allocate because the tables exist out of scope of a
1460 ira_max_register_move_cost[mode]
1461 = (move_table *) xmalloc (sizeof (move_table) * N_REG_CLASSES);
1462 memcpy (ira_max_register_move_cost[mode], ira_register_move_cost[mode],
1463 sizeof (move_table) * N_REG_CLASSES);
1464 for (cl1 = 0; cl1 < N_REG_CLASSES; cl1++)
1466 COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl1]);
1467 AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
1468 if (hard_reg_set_empty_p (temp_hard_regset))
1470 for (cl2 = 0; cl2 < N_REG_CLASSES; cl2++)
1471 if (hard_reg_set_subset_p (reg_class_contents[cl1],
1472 reg_class_contents[cl2]))
1473 for (cl3 = 0; cl3 < N_REG_CLASSES; cl3++)
1475 if (ira_max_register_move_cost[mode][cl2][cl3]
1476 < ira_register_move_cost[mode][cl1][cl3])
1477 ira_max_register_move_cost[mode][cl2][cl3]
1478 = ira_register_move_cost[mode][cl1][cl3];
1479 if (ira_max_register_move_cost[mode][cl3][cl2]
1480 < ira_register_move_cost[mode][cl3][cl1])
1481 ira_max_register_move_cost[mode][cl3][cl2]
1482 = ira_register_move_cost[mode][cl3][cl1];
1485 ira_may_move_in_cost[mode]
1486 = (move_table *) xmalloc (sizeof (move_table) * N_REG_CLASSES);
1487 memcpy (ira_may_move_in_cost[mode], may_move_in_cost[mode],
1488 sizeof (move_table) * N_REG_CLASSES);
1489 ira_may_move_out_cost[mode]
1490 = (move_table *) xmalloc (sizeof (move_table) * N_REG_CLASSES);
1491 memcpy (ira_may_move_out_cost[mode], may_move_out_cost[mode],
1492 sizeof (move_table) * N_REG_CLASSES);
1493 ira_max_may_move_in_cost[mode]
1494 = (move_table *) xmalloc (sizeof (move_table) * N_REG_CLASSES);
1495 memcpy (ira_max_may_move_in_cost[mode], ira_max_register_move_cost[mode],
1496 sizeof (move_table) * N_REG_CLASSES);
1497 ira_max_may_move_out_cost[mode]
1498 = (move_table *) xmalloc (sizeof (move_table) * N_REG_CLASSES);
1499 memcpy (ira_max_may_move_out_cost[mode], ira_max_register_move_cost[mode],
1500 sizeof (move_table) * N_REG_CLASSES);
1501 for (cl1 = 0; cl1 < N_REG_CLASSES; cl1++)
1503 for (cl2 = 0; cl2 < N_REG_CLASSES; cl2++)
1505 COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl2]);
1506 AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
1507 if (hard_reg_set_empty_p (temp_hard_regset))
1509 if (ira_class_subset_p[cl1][cl2])
1510 ira_may_move_in_cost[mode][cl1][cl2] = 0;
1511 if (ira_class_subset_p[cl2][cl1])
1512 ira_may_move_out_cost[mode][cl1][cl2] = 0;
1513 if (ira_class_subset_p[cl1][cl2])
1514 ira_max_may_move_in_cost[mode][cl1][cl2] = 0;
1515 if (ira_class_subset_p[cl2][cl1])
1516 ira_max_may_move_out_cost[mode][cl1][cl2] = 0;
1517 ira_register_move_cost[mode][cl1][cl2]
1518 = ira_max_register_move_cost[mode][cl1][cl2];
1519 ira_may_move_in_cost[mode][cl1][cl2]
1520 = ira_max_may_move_in_cost[mode][cl1][cl2];
1521 ira_may_move_out_cost[mode][cl1][cl2]
1522 = ira_max_may_move_out_cost[mode][cl1][cl2];
1529 /* This is called once during compiler work. It sets up
1530 different arrays whose values don't depend on the compiled
1533 ira_init_once (void)
1537 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
1539 ira_register_move_cost[mode] = NULL;
1540 ira_max_register_move_cost[mode] = NULL;
1541 ira_may_move_in_cost[mode] = NULL;
1542 ira_may_move_out_cost[mode] = NULL;
1543 ira_max_may_move_in_cost[mode] = NULL;
1544 ira_max_may_move_out_cost[mode] = NULL;
1546 ira_init_costs_once ();
1549 /* Free ira_max_register_move_cost, ira_may_move_in_cost,
1550 ira_may_move_out_cost, ira_max_may_move_in_cost, and
1551 ira_max_may_move_out_cost for each mode. */
1553 free_register_move_costs (void)
1557 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
1559 if (ira_max_register_move_cost[mode] != NULL)
1560 free (ira_max_register_move_cost[mode]);
1561 if (ira_may_move_in_cost[mode] != NULL)
1562 free (ira_may_move_in_cost[mode]);
1563 if (ira_may_move_out_cost[mode] != NULL)
1564 free (ira_may_move_out_cost[mode]);
1565 if (ira_max_may_move_in_cost[mode] != NULL)
1566 free (ira_max_may_move_in_cost[mode]);
1567 if (ira_max_may_move_out_cost[mode] != NULL)
1568 free (ira_max_may_move_out_cost[mode]);
1569 ira_register_move_cost[mode] = NULL;
1570 ira_max_register_move_cost[mode] = NULL;
1571 ira_may_move_in_cost[mode] = NULL;
1572 ira_may_move_out_cost[mode] = NULL;
1573 ira_max_may_move_in_cost[mode] = NULL;
1574 ira_max_may_move_out_cost[mode] = NULL;
1578 /* This is called every time when register related information is
1583 free_register_move_costs ();
1584 setup_reg_mode_hard_regset ();
1585 setup_alloc_regs (flag_omit_frame_pointer != 0);
1586 setup_class_subset_and_memory_move_costs ();
1587 setup_reg_class_nregs ();
1588 setup_prohibited_class_mode_regs ();
1589 find_reg_classes ();
1590 clarify_prohibited_class_mode_regs ();
1591 setup_hard_regno_aclass ();
1595 /* Function called once at the end of compiler work. */
1597 ira_finish_once (void)
1599 ira_finish_costs_once ();
1600 free_register_move_costs ();
1604 #define ira_prohibited_mode_move_regs_initialized_p \
1605 (this_target_ira_int->x_ira_prohibited_mode_move_regs_initialized_p)
1607 /* Set up IRA_PROHIBITED_MODE_MOVE_REGS. */
1609 setup_prohibited_mode_move_regs (void)
1612 rtx test_reg1, test_reg2, move_pat, move_insn;
1614 if (ira_prohibited_mode_move_regs_initialized_p)
1616 ira_prohibited_mode_move_regs_initialized_p = true;
1617 test_reg1 = gen_rtx_REG (VOIDmode, 0);
1618 test_reg2 = gen_rtx_REG (VOIDmode, 0);
1619 move_pat = gen_rtx_SET (VOIDmode, test_reg1, test_reg2);
1620 move_insn = gen_rtx_INSN (VOIDmode, 0, 0, 0, 0, move_pat, 0, -1, 0);
1621 for (i = 0; i < NUM_MACHINE_MODES; i++)
1623 SET_HARD_REG_SET (ira_prohibited_mode_move_regs[i]);
1624 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
1626 if (! HARD_REGNO_MODE_OK (j, (enum machine_mode) i))
1628 SET_REGNO_RAW (test_reg1, j);
1629 PUT_MODE (test_reg1, (enum machine_mode) i);
1630 SET_REGNO_RAW (test_reg2, j);
1631 PUT_MODE (test_reg2, (enum machine_mode) i);
1632 INSN_CODE (move_insn) = -1;
1633 recog_memoized (move_insn);
1634 if (INSN_CODE (move_insn) < 0)
1636 extract_insn (move_insn);
1637 if (! constrain_operands (1))
1639 CLEAR_HARD_REG_BIT (ira_prohibited_mode_move_regs[i], j);
1646 /* Return nonzero if REGNO is a particularly bad choice for reloading X. */
1648 ira_bad_reload_regno_1 (int regno, rtx x)
1652 enum reg_class pref;
1654 /* We only deal with pseudo regs. */
1655 if (! x || GET_CODE (x) != REG)
1658 x_regno = REGNO (x);
1659 if (x_regno < FIRST_PSEUDO_REGISTER)
1662 /* If the pseudo prefers REGNO explicitly, then do not consider
1663 REGNO a bad spill choice. */
1664 pref = reg_preferred_class (x_regno);
1665 if (reg_class_size[pref] == 1)
1666 return !TEST_HARD_REG_BIT (reg_class_contents[pref], regno);
1668 /* If the pseudo conflicts with REGNO, then we consider REGNO a
1669 poor choice for a reload regno. */
1670 a = ira_regno_allocno_map[x_regno];
1671 n = ALLOCNO_NUM_OBJECTS (a);
1672 for (i = 0; i < n; i++)
1674 ira_object_t obj = ALLOCNO_OBJECT (a, i);
1675 if (TEST_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), regno))
1681 /* Return nonzero if REGNO is a particularly bad choice for reloading
1684 ira_bad_reload_regno (int regno, rtx in, rtx out)
1686 return (ira_bad_reload_regno_1 (regno, in)
1687 || ira_bad_reload_regno_1 (regno, out));
1690 /* Return TRUE if *LOC contains an asm. */
1692 insn_contains_asm_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
1696 if (GET_CODE (*loc) == ASM_OPERANDS)
1702 /* Return TRUE if INSN contains an ASM. */
1704 insn_contains_asm (rtx insn)
1706 return for_each_rtx (&insn, insn_contains_asm_1, NULL);
1709 /* Add register clobbers from asm statements. */
1711 compute_regs_asm_clobbered (void)
1718 FOR_BB_INSNS_REVERSE (bb, insn)
1722 if (insn_contains_asm (insn))
1723 for (def_rec = DF_INSN_DEFS (insn); *def_rec; def_rec++)
1725 df_ref def = *def_rec;
1726 unsigned int dregno = DF_REF_REGNO (def);
1727 if (HARD_REGISTER_NUM_P (dregno))
1728 add_to_hard_reg_set (&crtl->asm_clobbers,
1729 GET_MODE (DF_REF_REAL_REG (def)),
1737 /* Set up ELIMINABLE_REGSET, IRA_NO_ALLOC_REGS, and REGS_EVER_LIVE. */
1739 ira_setup_eliminable_regset (void)
1741 #ifdef ELIMINABLE_REGS
1743 static const struct {const int from, to; } eliminables[] = ELIMINABLE_REGS;
1745 /* FIXME: If EXIT_IGNORE_STACK is set, we will not save and restore
1746 sp for alloca. So we can't eliminate the frame pointer in that
1747 case. At some point, we should improve this by emitting the
1748 sp-adjusting insns for this case. */
1750 = (! flag_omit_frame_pointer
1751 || (cfun->calls_alloca && EXIT_IGNORE_STACK)
1752 /* We need the frame pointer to catch stack overflow exceptions
1753 if the stack pointer is moving. */
1754 || (flag_stack_check && STACK_CHECK_MOVING_SP)
1755 || crtl->accesses_prior_frames
1756 || crtl->stack_realign_needed
1757 || targetm.frame_pointer_required ());
1759 frame_pointer_needed = need_fp;
1761 COPY_HARD_REG_SET (ira_no_alloc_regs, no_unit_alloc_regs);
1762 CLEAR_HARD_REG_SET (eliminable_regset);
1764 compute_regs_asm_clobbered ();
1766 /* Build the regset of all eliminable registers and show we can't
1767 use those that we already know won't be eliminated. */
1768 #ifdef ELIMINABLE_REGS
1769 for (i = 0; i < (int) ARRAY_SIZE (eliminables); i++)
1772 = (! targetm.can_eliminate (eliminables[i].from, eliminables[i].to)
1773 || (eliminables[i].to == STACK_POINTER_REGNUM && need_fp));
1775 if (!TEST_HARD_REG_BIT (crtl->asm_clobbers, eliminables[i].from))
1777 SET_HARD_REG_BIT (eliminable_regset, eliminables[i].from);
1780 SET_HARD_REG_BIT (ira_no_alloc_regs, eliminables[i].from);
1782 else if (cannot_elim)
1783 error ("%s cannot be used in asm here",
1784 reg_names[eliminables[i].from]);
1786 df_set_regs_ever_live (eliminables[i].from, true);
1788 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1789 if (!TEST_HARD_REG_BIT (crtl->asm_clobbers, HARD_FRAME_POINTER_REGNUM))
1791 SET_HARD_REG_BIT (eliminable_regset, HARD_FRAME_POINTER_REGNUM);
1793 SET_HARD_REG_BIT (ira_no_alloc_regs, HARD_FRAME_POINTER_REGNUM);
1796 error ("%s cannot be used in asm here",
1797 reg_names[HARD_FRAME_POINTER_REGNUM]);
1799 df_set_regs_ever_live (HARD_FRAME_POINTER_REGNUM, true);
1803 if (!TEST_HARD_REG_BIT (crtl->asm_clobbers, HARD_FRAME_POINTER_REGNUM))
1805 SET_HARD_REG_BIT (eliminable_regset, FRAME_POINTER_REGNUM);
1807 SET_HARD_REG_BIT (ira_no_alloc_regs, FRAME_POINTER_REGNUM);
1810 error ("%s cannot be used in asm here", reg_names[FRAME_POINTER_REGNUM]);
1812 df_set_regs_ever_live (FRAME_POINTER_REGNUM, true);
1818 /* The length of the following two arrays. */
1819 int ira_reg_equiv_len;
1821 /* The element value is TRUE if the corresponding regno value is
1823 bool *ira_reg_equiv_invariant_p;
1825 /* The element value is equiv constant of given pseudo-register or
1827 rtx *ira_reg_equiv_const;
1829 /* Set up the two arrays declared above. */
1831 find_reg_equiv_invariant_const (void)
1835 rtx list, insn, note, constant, x;
1837 for (i = FIRST_PSEUDO_REGISTER; i < VEC_length (reg_equivs_t, reg_equivs); i++)
1839 constant = NULL_RTX;
1840 invariant_p = false;
1841 for (list = reg_equiv_init (i); list != NULL_RTX; list = XEXP (list, 1))
1843 insn = XEXP (list, 0);
1844 note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
1846 if (note == NULL_RTX)
1851 if (! CONSTANT_P (x)
1852 || ! flag_pic || LEGITIMATE_PIC_OPERAND_P (x))
1854 /* It can happen that a REG_EQUIV note contains a MEM
1855 that is not a legitimate memory operand. As later
1856 stages of the reload assume that all addresses found
1857 in the reg_equiv_* arrays were originally legitimate,
1858 we ignore such REG_EQUIV notes. */
1859 if (memory_operand (x, VOIDmode))
1860 invariant_p = MEM_READONLY_P (x);
1861 else if (function_invariant_p (x))
1863 if (GET_CODE (x) == PLUS
1864 || x == frame_pointer_rtx || x == arg_pointer_rtx)
1871 ira_reg_equiv_invariant_p[i] = invariant_p;
1872 ira_reg_equiv_const[i] = constant;
1878 /* Vector of substitutions of register numbers,
1879 used to map pseudo regs into hardware regs.
1880 This is set up as a result of register allocation.
1881 Element N is the hard reg assigned to pseudo reg N,
1882 or is -1 if no hard reg was assigned.
1883 If N is a hard reg number, element N is N. */
1884 short *reg_renumber;
1886 /* Set up REG_RENUMBER and CALLER_SAVE_NEEDED (used by reload) from
1887 the allocation found by IRA. */
1889 setup_reg_renumber (void)
1891 int regno, hard_regno;
1893 ira_allocno_iterator ai;
1895 caller_save_needed = 0;
1896 FOR_EACH_ALLOCNO (a, ai)
1898 /* There are no caps at this point. */
1899 ira_assert (ALLOCNO_CAP_MEMBER (a) == NULL);
1900 if (! ALLOCNO_ASSIGNED_P (a))
1901 /* It can happen if A is not referenced but partially anticipated
1902 somewhere in a region. */
1903 ALLOCNO_ASSIGNED_P (a) = true;
1904 ira_free_allocno_updated_costs (a);
1905 hard_regno = ALLOCNO_HARD_REGNO (a);
1906 regno = ALLOCNO_REGNO (a);
1907 reg_renumber[regno] = (hard_regno < 0 ? -1 : hard_regno);
1908 if (hard_regno >= 0)
1911 enum reg_class pclass;
1914 pclass = ira_pressure_class_translate[REGNO_REG_CLASS (hard_regno)];
1915 nwords = ALLOCNO_NUM_OBJECTS (a);
1916 for (i = 0; i < nwords; i++)
1918 obj = ALLOCNO_OBJECT (a, i);
1919 IOR_COMPL_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj),
1920 reg_class_contents[pclass]);
1922 if (ALLOCNO_CALLS_CROSSED_NUM (a) != 0
1923 && ! ira_hard_reg_not_in_set_p (hard_regno, ALLOCNO_MODE (a),
1926 ira_assert (!optimize || flag_caller_saves
1927 || regno >= ira_reg_equiv_len
1928 || ira_reg_equiv_const[regno]
1929 || ira_reg_equiv_invariant_p[regno]);
1930 caller_save_needed = 1;
1936 /* Set up allocno assignment flags for further allocation
1939 setup_allocno_assignment_flags (void)
1943 ira_allocno_iterator ai;
1945 FOR_EACH_ALLOCNO (a, ai)
1947 if (! ALLOCNO_ASSIGNED_P (a))
1948 /* It can happen if A is not referenced but partially anticipated
1949 somewhere in a region. */
1950 ira_free_allocno_updated_costs (a);
1951 hard_regno = ALLOCNO_HARD_REGNO (a);
1952 /* Don't assign hard registers to allocnos which are destination
1953 of removed store at the end of loop. It has no sense to keep
1954 the same value in different hard registers. It is also
1955 impossible to assign hard registers correctly to such
1956 allocnos because the cost info and info about intersected
1957 calls are incorrect for them. */
1958 ALLOCNO_ASSIGNED_P (a) = (hard_regno >= 0
1959 || ALLOCNO_EMIT_DATA (a)->mem_optimized_dest_p
1960 || (ALLOCNO_MEMORY_COST (a)
1961 - ALLOCNO_CLASS_COST (a)) < 0);
1962 ira_assert (hard_regno < 0
1963 || ! ira_hard_reg_not_in_set_p (hard_regno, ALLOCNO_MODE (a),
1965 [ALLOCNO_CLASS (a)]));
1969 /* Evaluate overall allocation cost and the costs for using hard
1970 registers and memory for allocnos. */
1972 calculate_allocation_cost (void)
1974 int hard_regno, cost;
1976 ira_allocno_iterator ai;
1978 ira_overall_cost = ira_reg_cost = ira_mem_cost = 0;
1979 FOR_EACH_ALLOCNO (a, ai)
1981 hard_regno = ALLOCNO_HARD_REGNO (a);
1982 ira_assert (hard_regno < 0
1983 || ! ira_hard_reg_not_in_set_p
1984 (hard_regno, ALLOCNO_MODE (a),
1985 reg_class_contents[ALLOCNO_CLASS (a)]));
1988 cost = ALLOCNO_MEMORY_COST (a);
1989 ira_mem_cost += cost;
1991 else if (ALLOCNO_HARD_REG_COSTS (a) != NULL)
1993 cost = (ALLOCNO_HARD_REG_COSTS (a)
1994 [ira_class_hard_reg_index
1995 [ALLOCNO_CLASS (a)][hard_regno]]);
1996 ira_reg_cost += cost;
2000 cost = ALLOCNO_CLASS_COST (a);
2001 ira_reg_cost += cost;
2003 ira_overall_cost += cost;
2006 if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL)
2008 fprintf (ira_dump_file,
2009 "+++Costs: overall %d, reg %d, mem %d, ld %d, st %d, move %d\n",
2010 ira_overall_cost, ira_reg_cost, ira_mem_cost,
2011 ira_load_cost, ira_store_cost, ira_shuffle_cost);
2012 fprintf (ira_dump_file, "+++ move loops %d, new jumps %d\n",
2013 ira_move_loops_num, ira_additional_jumps_num);
2018 #ifdef ENABLE_IRA_CHECKING
2019 /* Check the correctness of the allocation. We do need this because
2020 of complicated code to transform more one region internal
2021 representation into one region representation. */
2023 check_allocation (void)
2026 int hard_regno, nregs, conflict_nregs;
2027 ira_allocno_iterator ai;
2029 FOR_EACH_ALLOCNO (a, ai)
2031 int n = ALLOCNO_NUM_OBJECTS (a);
2034 if (ALLOCNO_CAP_MEMBER (a) != NULL
2035 || (hard_regno = ALLOCNO_HARD_REGNO (a)) < 0)
2037 nregs = hard_regno_nregs[hard_regno][ALLOCNO_MODE (a)];
2039 /* We allocated a single hard register. */
2042 /* We allocated multiple hard registers, and we will test
2043 conflicts in a granularity of single hard regs. */
2046 for (i = 0; i < n; i++)
2048 ira_object_t obj = ALLOCNO_OBJECT (a, i);
2049 ira_object_t conflict_obj;
2050 ira_object_conflict_iterator oci;
2051 int this_regno = hard_regno;
2054 if (WORDS_BIG_ENDIAN)
2055 this_regno += n - i - 1;
2059 FOR_EACH_OBJECT_CONFLICT (obj, conflict_obj, oci)
2061 ira_allocno_t conflict_a = OBJECT_ALLOCNO (conflict_obj);
2062 int conflict_hard_regno = ALLOCNO_HARD_REGNO (conflict_a);
2063 if (conflict_hard_regno < 0)
2068 [conflict_hard_regno][ALLOCNO_MODE (conflict_a)]);
2070 if (ALLOCNO_NUM_OBJECTS (conflict_a) > 1
2071 && conflict_nregs == ALLOCNO_NUM_OBJECTS (conflict_a))
2073 if (WORDS_BIG_ENDIAN)
2074 conflict_hard_regno += (ALLOCNO_NUM_OBJECTS (conflict_a)
2075 - OBJECT_SUBWORD (conflict_obj) - 1);
2077 conflict_hard_regno += OBJECT_SUBWORD (conflict_obj);
2081 if ((conflict_hard_regno <= this_regno
2082 && this_regno < conflict_hard_regno + conflict_nregs)
2083 || (this_regno <= conflict_hard_regno
2084 && conflict_hard_regno < this_regno + nregs))
2086 fprintf (stderr, "bad allocation for %d and %d\n",
2087 ALLOCNO_REGNO (a), ALLOCNO_REGNO (conflict_a));
2096 /* Fix values of array REG_EQUIV_INIT after live range splitting done
2099 fix_reg_equiv_init (void)
2101 unsigned int max_regno = max_reg_num ();
2102 int i, new_regno, max;
2103 rtx x, prev, next, insn, set;
2105 if (VEC_length (reg_equivs_t, reg_equivs) < max_regno)
2107 max = VEC_length (reg_equivs_t, reg_equivs);
2109 for (i = FIRST_PSEUDO_REGISTER; i < max; i++)
2110 for (prev = NULL_RTX, x = reg_equiv_init (i);
2116 set = single_set (insn);
2117 ira_assert (set != NULL_RTX
2118 && (REG_P (SET_DEST (set)) || REG_P (SET_SRC (set))));
2119 if (REG_P (SET_DEST (set))
2120 && ((int) REGNO (SET_DEST (set)) == i
2121 || (int) ORIGINAL_REGNO (SET_DEST (set)) == i))
2122 new_regno = REGNO (SET_DEST (set));
2123 else if (REG_P (SET_SRC (set))
2124 && ((int) REGNO (SET_SRC (set)) == i
2125 || (int) ORIGINAL_REGNO (SET_SRC (set)) == i))
2126 new_regno = REGNO (SET_SRC (set));
2133 if (prev == NULL_RTX)
2134 reg_equiv_init (i) = next;
2136 XEXP (prev, 1) = next;
2137 XEXP (x, 1) = reg_equiv_init (new_regno);
2138 reg_equiv_init (new_regno) = x;
2144 #ifdef ENABLE_IRA_CHECKING
2145 /* Print redundant memory-memory copies. */
2147 print_redundant_copies (void)
2151 ira_copy_t cp, next_cp;
2152 ira_allocno_iterator ai;
2154 FOR_EACH_ALLOCNO (a, ai)
2156 if (ALLOCNO_CAP_MEMBER (a) != NULL)
2159 hard_regno = ALLOCNO_HARD_REGNO (a);
2160 if (hard_regno >= 0)
2162 for (cp = ALLOCNO_COPIES (a); cp != NULL; cp = next_cp)
2164 next_cp = cp->next_first_allocno_copy;
2167 next_cp = cp->next_second_allocno_copy;
2168 if (internal_flag_ira_verbose > 4 && ira_dump_file != NULL
2169 && cp->insn != NULL_RTX
2170 && ALLOCNO_HARD_REGNO (cp->first) == hard_regno)
2171 fprintf (ira_dump_file,
2172 " Redundant move from %d(freq %d):%d\n",
2173 INSN_UID (cp->insn), cp->freq, hard_regno);
2179 /* Setup preferred and alternative classes for new pseudo-registers
2180 created by IRA starting with START. */
2182 setup_preferred_alternate_classes_for_new_pseudos (int start)
2185 int max_regno = max_reg_num ();
2187 for (i = start; i < max_regno; i++)
2189 old_regno = ORIGINAL_REGNO (regno_reg_rtx[i]);
2190 ira_assert (i != old_regno);
2191 setup_reg_classes (i, reg_preferred_class (old_regno),
2192 reg_alternate_class (old_regno),
2193 reg_allocno_class (old_regno));
2194 if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL)
2195 fprintf (ira_dump_file,
2196 " New r%d: setting preferred %s, alternative %s\n",
2197 i, reg_class_names[reg_preferred_class (old_regno)],
2198 reg_class_names[reg_alternate_class (old_regno)]);
2204 /* Regional allocation can create new pseudo-registers. This function
2205 expands some arrays for pseudo-registers. */
2207 expand_reg_info (int old_size)
2210 int size = max_reg_num ();
2213 for (i = old_size; i < size; i++)
2214 setup_reg_classes (i, GENERAL_REGS, ALL_REGS, GENERAL_REGS);
2217 /* Return TRUE if there is too high register pressure in the function.
2218 It is used to decide when stack slot sharing is worth to do. */
2220 too_high_register_pressure_p (void)
2223 enum reg_class pclass;
2225 for (i = 0; i < ira_pressure_classes_num; i++)
2227 pclass = ira_pressure_classes[i];
2228 if (ira_loop_tree_root->reg_pressure[pclass] > 10000)
2236 /* Indicate that hard register number FROM was eliminated and replaced with
2237 an offset from hard register number TO. The status of hard registers live
2238 at the start of a basic block is updated by replacing a use of FROM with
2242 mark_elimination (int from, int to)
2248 /* We don't use LIVE info in IRA. */
2249 bitmap r = DF_LR_IN (bb);
2251 if (REGNO_REG_SET_P (r, from))
2253 CLEAR_REGNO_REG_SET (r, from);
2254 SET_REGNO_REG_SET (r, to);
2263 /* Set when a REG_EQUIV note is found or created. Use to
2264 keep track of what memory accesses might be created later,
2268 /* The list of each instruction which initializes this register. */
2270 /* Loop depth is used to recognize equivalences which appear
2271 to be present within the same loop (or in an inner loop). */
2273 /* Nonzero if this had a preexisting REG_EQUIV note. */
2274 int is_arg_equivalence;
2275 /* Set when an attempt should be made to replace a register
2276 with the associated src_p entry. */
2280 /* reg_equiv[N] (where N is a pseudo reg number) is the equivalence
2281 structure for that register. */
2282 static struct equivalence *reg_equiv;
2284 /* Used for communication between the following two functions: contains
2285 a MEM that we wish to ensure remains unchanged. */
2286 static rtx equiv_mem;
2288 /* Set nonzero if EQUIV_MEM is modified. */
2289 static int equiv_mem_modified;
2291 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
2292 Called via note_stores. */
2294 validate_equiv_mem_from_store (rtx dest, const_rtx set ATTRIBUTE_UNUSED,
2295 void *data ATTRIBUTE_UNUSED)
2298 && reg_overlap_mentioned_p (dest, equiv_mem))
2300 && true_dependence (dest, VOIDmode, equiv_mem, rtx_varies_p)))
2301 equiv_mem_modified = 1;
2304 /* Verify that no store between START and the death of REG invalidates
2305 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
2306 by storing into an overlapping memory location, or with a non-const
2309 Return 1 if MEMREF remains valid. */
2311 validate_equiv_mem (rtx start, rtx reg, rtx memref)
2317 equiv_mem_modified = 0;
2319 /* If the memory reference has side effects or is volatile, it isn't a
2320 valid equivalence. */
2321 if (side_effects_p (memref))
2324 for (insn = start; insn && ! equiv_mem_modified; insn = NEXT_INSN (insn))
2326 if (! INSN_P (insn))
2329 if (find_reg_note (insn, REG_DEAD, reg))
2332 /* This used to ignore readonly memory and const/pure calls. The problem
2333 is the equivalent form may reference a pseudo which gets assigned a
2334 call clobbered hard reg. When we later replace REG with its
2335 equivalent form, the value in the call-clobbered reg has been
2336 changed and all hell breaks loose. */
2340 note_stores (PATTERN (insn), validate_equiv_mem_from_store, NULL);
2342 /* If a register mentioned in MEMREF is modified via an
2343 auto-increment, we lose the equivalence. Do the same if one
2344 dies; although we could extend the life, it doesn't seem worth
2347 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
2348 if ((REG_NOTE_KIND (note) == REG_INC
2349 || REG_NOTE_KIND (note) == REG_DEAD)
2350 && REG_P (XEXP (note, 0))
2351 && reg_overlap_mentioned_p (XEXP (note, 0), memref))
2358 /* Returns zero if X is known to be invariant. */
2360 equiv_init_varies_p (rtx x)
2362 RTX_CODE code = GET_CODE (x);
2369 return !MEM_READONLY_P (x) || equiv_init_varies_p (XEXP (x, 0));
2381 return reg_equiv[REGNO (x)].replace == 0 && rtx_varies_p (x, 0);
2384 if (MEM_VOLATILE_P (x))
2393 fmt = GET_RTX_FORMAT (code);
2394 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2397 if (equiv_init_varies_p (XEXP (x, i)))
2400 else if (fmt[i] == 'E')
2403 for (j = 0; j < XVECLEN (x, i); j++)
2404 if (equiv_init_varies_p (XVECEXP (x, i, j)))
2411 /* Returns nonzero if X (used to initialize register REGNO) is movable.
2412 X is only movable if the registers it uses have equivalent initializations
2413 which appear to be within the same loop (or in an inner loop) and movable
2414 or if they are not candidates for local_alloc and don't vary. */
2416 equiv_init_movable_p (rtx x, int regno)
2420 enum rtx_code code = GET_CODE (x);
2425 return equiv_init_movable_p (SET_SRC (x), regno);
2440 return ((reg_equiv[REGNO (x)].loop_depth >= reg_equiv[regno].loop_depth
2441 && reg_equiv[REGNO (x)].replace)
2442 || (REG_BASIC_BLOCK (REGNO (x)) < NUM_FIXED_BLOCKS
2443 && ! rtx_varies_p (x, 0)));
2445 case UNSPEC_VOLATILE:
2449 if (MEM_VOLATILE_P (x))
2458 fmt = GET_RTX_FORMAT (code);
2459 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2463 if (! equiv_init_movable_p (XEXP (x, i), regno))
2467 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2468 if (! equiv_init_movable_p (XVECEXP (x, i, j), regno))
2476 /* TRUE if X uses any registers for which reg_equiv[REGNO].replace is
2479 contains_replace_regs (rtx x)
2483 enum rtx_code code = GET_CODE (x);
2500 return reg_equiv[REGNO (x)].replace;
2506 fmt = GET_RTX_FORMAT (code);
2507 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2511 if (contains_replace_regs (XEXP (x, i)))
2515 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2516 if (contains_replace_regs (XVECEXP (x, i, j)))
2524 /* TRUE if X references a memory location that would be affected by a store
2527 memref_referenced_p (rtx memref, rtx x)
2531 enum rtx_code code = GET_CODE (x);
2549 return (reg_equiv[REGNO (x)].replacement
2550 && memref_referenced_p (memref,
2551 reg_equiv[REGNO (x)].replacement));
2554 if (true_dependence (memref, VOIDmode, x, rtx_varies_p))
2559 /* If we are setting a MEM, it doesn't count (its address does), but any
2560 other SET_DEST that has a MEM in it is referencing the MEM. */
2561 if (MEM_P (SET_DEST (x)))
2563 if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0)))
2566 else if (memref_referenced_p (memref, SET_DEST (x)))
2569 return memref_referenced_p (memref, SET_SRC (x));
2575 fmt = GET_RTX_FORMAT (code);
2576 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2580 if (memref_referenced_p (memref, XEXP (x, i)))
2584 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2585 if (memref_referenced_p (memref, XVECEXP (x, i, j)))
2593 /* TRUE if some insn in the range (START, END] references a memory location
2594 that would be affected by a store to MEMREF. */
2596 memref_used_between_p (rtx memref, rtx start, rtx end)
2600 for (insn = NEXT_INSN (start); insn != NEXT_INSN (end);
2601 insn = NEXT_INSN (insn))
2603 if (!NONDEBUG_INSN_P (insn))
2606 if (memref_referenced_p (memref, PATTERN (insn)))
2609 /* Nonconst functions may access memory. */
2610 if (CALL_P (insn) && (! RTL_CONST_CALL_P (insn)))
2617 /* Mark REG as having no known equivalence.
2618 Some instructions might have been processed before and furnished
2619 with REG_EQUIV notes for this register; these notes will have to be
2621 STORE is the piece of RTL that does the non-constant / conflicting
2622 assignment - a SET, CLOBBER or REG_INC note. It is currently not used,
2623 but needs to be there because this function is called from note_stores. */
2625 no_equiv (rtx reg, const_rtx store ATTRIBUTE_UNUSED,
2626 void *data ATTRIBUTE_UNUSED)
2633 regno = REGNO (reg);
2634 list = reg_equiv[regno].init_insns;
2635 if (list == const0_rtx)
2637 reg_equiv[regno].init_insns = const0_rtx;
2638 reg_equiv[regno].replacement = NULL_RTX;
2639 /* This doesn't matter for equivalences made for argument registers, we
2640 should keep their initialization insns. */
2641 if (reg_equiv[regno].is_arg_equivalence)
2643 reg_equiv_init (regno) = NULL_RTX;
2644 for (; list; list = XEXP (list, 1))
2646 rtx insn = XEXP (list, 0);
2647 remove_note (insn, find_reg_note (insn, REG_EQUIV, NULL_RTX));
2651 /* In DEBUG_INSN location adjust REGs from CLEARED_REGS bitmap to the
2652 equivalent replacement. */
2655 adjust_cleared_regs (rtx loc, const_rtx old_rtx ATTRIBUTE_UNUSED, void *data)
2659 bitmap cleared_regs = (bitmap) data;
2660 if (bitmap_bit_p (cleared_regs, REGNO (loc)))
2661 return simplify_replace_fn_rtx (*reg_equiv[REGNO (loc)].src_p,
2662 NULL_RTX, adjust_cleared_regs, data);
2667 /* Nonzero if we recorded an equivalence for a LABEL_REF. */
2668 static int recorded_label_ref;
2670 /* Find registers that are equivalent to a single value throughout the
2671 compilation (either because they can be referenced in memory or are
2672 set once from a single constant). Lower their priority for a
2675 If such a register is only referenced once, try substituting its
2676 value into the using insn. If it succeeds, we can eliminate the
2677 register completely.
2679 Initialize the REG_EQUIV_INIT array of initializing insns.
2681 Return non-zero if jump label rebuilding should be done. */
2683 update_equiv_regs (void)
2688 bitmap cleared_regs;
2690 /* We need to keep track of whether or not we recorded a LABEL_REF so
2691 that we know if the jump optimizer needs to be rerun. */
2692 recorded_label_ref = 0;
2694 reg_equiv = XCNEWVEC (struct equivalence, max_regno);
2697 init_alias_analysis ();
2699 /* Scan the insns and find which registers have equivalences. Do this
2700 in a separate scan of the insns because (due to -fcse-follow-jumps)
2701 a register can be set below its use. */
2704 loop_depth = bb->loop_depth;
2706 for (insn = BB_HEAD (bb);
2707 insn != NEXT_INSN (BB_END (bb));
2708 insn = NEXT_INSN (insn))
2715 if (! INSN_P (insn))
2718 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
2719 if (REG_NOTE_KIND (note) == REG_INC)
2720 no_equiv (XEXP (note, 0), note, NULL);
2722 set = single_set (insn);
2724 /* If this insn contains more (or less) than a single SET,
2725 only mark all destinations as having no known equivalence. */
2728 note_stores (PATTERN (insn), no_equiv, NULL);
2731 else if (GET_CODE (PATTERN (insn)) == PARALLEL)
2735 for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--)
2737 rtx part = XVECEXP (PATTERN (insn), 0, i);
2739 note_stores (part, no_equiv, NULL);
2743 dest = SET_DEST (set);
2744 src = SET_SRC (set);
2746 /* See if this is setting up the equivalence between an argument
2747 register and its stack slot. */
2748 note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
2751 gcc_assert (REG_P (dest));
2752 regno = REGNO (dest);
2754 /* Note that we don't want to clear reg_equiv_init even if there
2755 are multiple sets of this register. */
2756 reg_equiv[regno].is_arg_equivalence = 1;
2758 /* Record for reload that this is an equivalencing insn. */
2759 if (rtx_equal_p (src, XEXP (note, 0)))
2760 reg_equiv_init (regno)
2761 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init (regno));
2763 /* Continue normally in case this is a candidate for
2770 /* We only handle the case of a pseudo register being set
2771 once, or always to the same value. */
2772 /* ??? The mn10200 port breaks if we add equivalences for
2773 values that need an ADDRESS_REGS register and set them equivalent
2774 to a MEM of a pseudo. The actual problem is in the over-conservative
2775 handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in
2776 calculate_needs, but we traditionally work around this problem
2777 here by rejecting equivalences when the destination is in a register
2778 that's likely spilled. This is fragile, of course, since the
2779 preferred class of a pseudo depends on all instructions that set
2783 || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER
2784 || reg_equiv[regno].init_insns == const0_rtx
2785 || (targetm.class_likely_spilled_p (reg_preferred_class (regno))
2786 && MEM_P (src) && ! reg_equiv[regno].is_arg_equivalence))
2788 /* This might be setting a SUBREG of a pseudo, a pseudo that is
2789 also set somewhere else to a constant. */
2790 note_stores (set, no_equiv, NULL);
2794 note = find_reg_note (insn, REG_EQUAL, NULL_RTX);
2796 /* cse sometimes generates function invariants, but doesn't put a
2797 REG_EQUAL note on the insn. Since this note would be redundant,
2798 there's no point creating it earlier than here. */
2799 if (! note && ! rtx_varies_p (src, 0))
2800 note = set_unique_reg_note (insn, REG_EQUAL, copy_rtx (src));
2802 /* Don't bother considering a REG_EQUAL note containing an EXPR_LIST
2803 since it represents a function call */
2804 if (note && GET_CODE (XEXP (note, 0)) == EXPR_LIST)
2807 if (DF_REG_DEF_COUNT (regno) != 1
2809 || rtx_varies_p (XEXP (note, 0), 0)
2810 || (reg_equiv[regno].replacement
2811 && ! rtx_equal_p (XEXP (note, 0),
2812 reg_equiv[regno].replacement))))
2814 no_equiv (dest, set, NULL);
2817 /* Record this insn as initializing this register. */
2818 reg_equiv[regno].init_insns
2819 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv[regno].init_insns);
2821 /* If this register is known to be equal to a constant, record that
2822 it is always equivalent to the constant. */
2823 if (DF_REG_DEF_COUNT (regno) == 1
2824 && note && ! rtx_varies_p (XEXP (note, 0), 0))
2826 rtx note_value = XEXP (note, 0);
2827 remove_note (insn, note);
2828 set_unique_reg_note (insn, REG_EQUIV, note_value);
2831 /* If this insn introduces a "constant" register, decrease the priority
2832 of that register. Record this insn if the register is only used once
2833 more and the equivalence value is the same as our source.
2835 The latter condition is checked for two reasons: First, it is an
2836 indication that it may be more efficient to actually emit the insn
2837 as written (if no registers are available, reload will substitute
2838 the equivalence). Secondly, it avoids problems with any registers
2839 dying in this insn whose death notes would be missed.
2841 If we don't have a REG_EQUIV note, see if this insn is loading
2842 a register used only in one basic block from a MEM. If so, and the
2843 MEM remains unchanged for the life of the register, add a REG_EQUIV
2846 note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
2848 if (note == 0 && REG_BASIC_BLOCK (regno) >= NUM_FIXED_BLOCKS
2849 && MEM_P (SET_SRC (set))
2850 && validate_equiv_mem (insn, dest, SET_SRC (set)))
2851 note = set_unique_reg_note (insn, REG_EQUIV, copy_rtx (SET_SRC (set)));
2855 int regno = REGNO (dest);
2856 rtx x = XEXP (note, 0);
2858 /* If we haven't done so, record for reload that this is an
2859 equivalencing insn. */
2860 if (!reg_equiv[regno].is_arg_equivalence)
2861 reg_equiv_init (regno)
2862 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init (regno));
2864 /* Record whether or not we created a REG_EQUIV note for a LABEL_REF.
2865 We might end up substituting the LABEL_REF for uses of the
2866 pseudo here or later. That kind of transformation may turn an
2867 indirect jump into a direct jump, in which case we must rerun the
2868 jump optimizer to ensure that the JUMP_LABEL fields are valid. */
2869 if (GET_CODE (x) == LABEL_REF
2870 || (GET_CODE (x) == CONST
2871 && GET_CODE (XEXP (x, 0)) == PLUS
2872 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF)))
2873 recorded_label_ref = 1;
2875 reg_equiv[regno].replacement = x;
2876 reg_equiv[regno].src_p = &SET_SRC (set);
2877 reg_equiv[regno].loop_depth = loop_depth;
2879 /* Don't mess with things live during setjmp. */
2880 if (REG_LIVE_LENGTH (regno) >= 0 && optimize)
2882 /* Note that the statement below does not affect the priority
2884 REG_LIVE_LENGTH (regno) *= 2;
2886 /* If the register is referenced exactly twice, meaning it is
2887 set once and used once, indicate that the reference may be
2888 replaced by the equivalence we computed above. Do this
2889 even if the register is only used in one block so that
2890 dependencies can be handled where the last register is
2891 used in a different block (i.e. HIGH / LO_SUM sequences)
2892 and to reduce the number of registers alive across
2895 if (REG_N_REFS (regno) == 2
2896 && (rtx_equal_p (x, src)
2897 || ! equiv_init_varies_p (src))
2898 && NONJUMP_INSN_P (insn)
2899 && equiv_init_movable_p (PATTERN (insn), regno))
2900 reg_equiv[regno].replace = 1;
2909 /* A second pass, to gather additional equivalences with memory. This needs
2910 to be done after we know which registers we are going to replace. */
2912 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
2917 if (! INSN_P (insn))
2920 set = single_set (insn);
2924 dest = SET_DEST (set);
2925 src = SET_SRC (set);
2927 /* If this sets a MEM to the contents of a REG that is only used
2928 in a single basic block, see if the register is always equivalent
2929 to that memory location and if moving the store from INSN to the
2930 insn that set REG is safe. If so, put a REG_EQUIV note on the
2933 Don't add a REG_EQUIV note if the insn already has one. The existing
2934 REG_EQUIV is likely more useful than the one we are adding.
2936 If one of the regs in the address has reg_equiv[REGNO].replace set,
2937 then we can't add this REG_EQUIV note. The reg_equiv[REGNO].replace
2938 optimization may move the set of this register immediately before
2939 insn, which puts it after reg_equiv[REGNO].init_insns, and hence
2940 the mention in the REG_EQUIV note would be to an uninitialized
2943 if (MEM_P (dest) && REG_P (src)
2944 && (regno = REGNO (src)) >= FIRST_PSEUDO_REGISTER
2945 && REG_BASIC_BLOCK (regno) >= NUM_FIXED_BLOCKS
2946 && DF_REG_DEF_COUNT (regno) == 1
2947 && reg_equiv[regno].init_insns != 0
2948 && reg_equiv[regno].init_insns != const0_rtx
2949 && ! find_reg_note (XEXP (reg_equiv[regno].init_insns, 0),
2950 REG_EQUIV, NULL_RTX)
2951 && ! contains_replace_regs (XEXP (dest, 0)))
2953 rtx init_insn = XEXP (reg_equiv[regno].init_insns, 0);
2954 if (validate_equiv_mem (init_insn, src, dest)
2955 && ! memref_used_between_p (dest, init_insn, insn)
2956 /* Attaching a REG_EQUIV note will fail if INIT_INSN has
2958 && set_unique_reg_note (init_insn, REG_EQUIV, copy_rtx (dest)))
2960 /* This insn makes the equivalence, not the one initializing
2962 reg_equiv_init (regno)
2963 = gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX);
2964 df_notes_rescan (init_insn);
2969 cleared_regs = BITMAP_ALLOC (NULL);
2970 /* Now scan all regs killed in an insn to see if any of them are
2971 registers only used that once. If so, see if we can replace the
2972 reference with the equivalent form. If we can, delete the
2973 initializing reference and this register will go away. If we
2974 can't replace the reference, and the initializing reference is
2975 within the same loop (or in an inner loop), then move the register
2976 initialization just before the use, so that they are in the same
2978 FOR_EACH_BB_REVERSE (bb)
2980 loop_depth = bb->loop_depth;
2981 for (insn = BB_END (bb);
2982 insn != PREV_INSN (BB_HEAD (bb));
2983 insn = PREV_INSN (insn))
2987 if (! INSN_P (insn))
2990 /* Don't substitute into a non-local goto, this confuses CFG. */
2992 && find_reg_note (insn, REG_NON_LOCAL_GOTO, NULL_RTX))
2995 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
2997 if (REG_NOTE_KIND (link) == REG_DEAD
2998 /* Make sure this insn still refers to the register. */
2999 && reg_mentioned_p (XEXP (link, 0), PATTERN (insn)))
3001 int regno = REGNO (XEXP (link, 0));
3004 if (! reg_equiv[regno].replace
3005 || reg_equiv[regno].loop_depth < loop_depth
3006 /* There is no sense to move insns if we did
3007 register pressure-sensitive scheduling was
3008 done because it will not improve allocation
3009 but worsen insn schedule with a big
3011 || (flag_sched_pressure && flag_schedule_insns))
3014 /* reg_equiv[REGNO].replace gets set only when
3015 REG_N_REFS[REGNO] is 2, i.e. the register is set
3016 once and used once. (If it were only set, but not used,
3017 flow would have deleted the setting insns.) Hence
3018 there can only be one insn in reg_equiv[REGNO].init_insns. */
3019 gcc_assert (reg_equiv[regno].init_insns
3020 && !XEXP (reg_equiv[regno].init_insns, 1));
3021 equiv_insn = XEXP (reg_equiv[regno].init_insns, 0);
3023 /* We may not move instructions that can throw, since
3024 that changes basic block boundaries and we are not
3025 prepared to adjust the CFG to match. */
3026 if (can_throw_internal (equiv_insn))
3029 if (asm_noperands (PATTERN (equiv_insn)) < 0
3030 && validate_replace_rtx (regno_reg_rtx[regno],
3031 *(reg_equiv[regno].src_p), insn))
3037 /* Find the last note. */
3038 for (last_link = link; XEXP (last_link, 1);
3039 last_link = XEXP (last_link, 1))
3042 /* Append the REG_DEAD notes from equiv_insn. */
3043 equiv_link = REG_NOTES (equiv_insn);
3047 equiv_link = XEXP (equiv_link, 1);
3048 if (REG_NOTE_KIND (note) == REG_DEAD)
3050 remove_note (equiv_insn, note);
3051 XEXP (last_link, 1) = note;
3052 XEXP (note, 1) = NULL_RTX;
3057 remove_death (regno, insn);
3058 SET_REG_N_REFS (regno, 0);
3059 REG_FREQ (regno) = 0;
3060 delete_insn (equiv_insn);
3062 reg_equiv[regno].init_insns
3063 = XEXP (reg_equiv[regno].init_insns, 1);
3065 reg_equiv_init (regno) = NULL_RTX;
3066 bitmap_set_bit (cleared_regs, regno);
3068 /* Move the initialization of the register to just before
3069 INSN. Update the flow information. */
3070 else if (prev_nondebug_insn (insn) != equiv_insn)
3074 new_insn = emit_insn_before (PATTERN (equiv_insn), insn);
3075 REG_NOTES (new_insn) = REG_NOTES (equiv_insn);
3076 REG_NOTES (equiv_insn) = 0;
3077 /* Rescan it to process the notes. */
3078 df_insn_rescan (new_insn);
3080 /* Make sure this insn is recognized before
3081 reload begins, otherwise
3082 eliminate_regs_in_insn will die. */
3083 INSN_CODE (new_insn) = INSN_CODE (equiv_insn);
3085 delete_insn (equiv_insn);
3087 XEXP (reg_equiv[regno].init_insns, 0) = new_insn;
3089 REG_BASIC_BLOCK (regno) = bb->index;
3090 REG_N_CALLS_CROSSED (regno) = 0;
3091 REG_FREQ_CALLS_CROSSED (regno) = 0;
3092 REG_N_THROWING_CALLS_CROSSED (regno) = 0;
3093 REG_LIVE_LENGTH (regno) = 2;
3095 if (insn == BB_HEAD (bb))
3096 BB_HEAD (bb) = PREV_INSN (insn);
3098 reg_equiv_init (regno)
3099 = gen_rtx_INSN_LIST (VOIDmode, new_insn, NULL_RTX);
3100 bitmap_set_bit (cleared_regs, regno);
3107 if (!bitmap_empty_p (cleared_regs))
3111 bitmap_and_compl_into (DF_LIVE_IN (bb), cleared_regs);
3112 bitmap_and_compl_into (DF_LIVE_OUT (bb), cleared_regs);
3113 bitmap_and_compl_into (DF_LR_IN (bb), cleared_regs);
3114 bitmap_and_compl_into (DF_LR_OUT (bb), cleared_regs);
3117 /* Last pass - adjust debug insns referencing cleared regs. */
3118 if (MAY_HAVE_DEBUG_INSNS)
3119 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
3120 if (DEBUG_INSN_P (insn))
3122 rtx old_loc = INSN_VAR_LOCATION_LOC (insn);
3123 INSN_VAR_LOCATION_LOC (insn)
3124 = simplify_replace_fn_rtx (old_loc, NULL_RTX,
3125 adjust_cleared_regs,
3126 (void *) cleared_regs);
3127 if (old_loc != INSN_VAR_LOCATION_LOC (insn))
3128 df_insn_rescan (insn);
3132 BITMAP_FREE (cleared_regs);
3137 end_alias_analysis ();
3139 return recorded_label_ref;
3144 /* Print chain C to FILE. */
3146 print_insn_chain (FILE *file, struct insn_chain *c)
3148 fprintf (file, "insn=%d, ", INSN_UID(c->insn));
3149 bitmap_print (file, &c->live_throughout, "live_throughout: ", ", ");
3150 bitmap_print (file, &c->dead_or_set, "dead_or_set: ", "\n");
3154 /* Print all reload_insn_chains to FILE. */
3156 print_insn_chains (FILE *file)
3158 struct insn_chain *c;
3159 for (c = reload_insn_chain; c ; c = c->next)
3160 print_insn_chain (file, c);
3163 /* Return true if pseudo REGNO should be added to set live_throughout
3164 or dead_or_set of the insn chains for reload consideration. */
3166 pseudo_for_reload_consideration_p (int regno)
3168 /* Consider spilled pseudos too for IRA because they still have a
3169 chance to get hard-registers in the reload when IRA is used. */
3170 return (reg_renumber[regno] >= 0 || ira_conflicts_p);
3173 /* Init LIVE_SUBREGS[ALLOCNUM] and LIVE_SUBREGS_USED[ALLOCNUM] using
3174 REG to the number of nregs, and INIT_VALUE to get the
3175 initialization. ALLOCNUM need not be the regno of REG. */
3177 init_live_subregs (bool init_value, sbitmap *live_subregs,
3178 int *live_subregs_used, int allocnum, rtx reg)
3180 unsigned int regno = REGNO (SUBREG_REG (reg));
3181 int size = GET_MODE_SIZE (GET_MODE (regno_reg_rtx[regno]));
3183 gcc_assert (size > 0);
3185 /* Been there, done that. */
3186 if (live_subregs_used[allocnum])
3189 /* Create a new one with zeros. */
3190 if (live_subregs[allocnum] == NULL)
3191 live_subregs[allocnum] = sbitmap_alloc (size);
3193 /* If the entire reg was live before blasting into subregs, we need
3194 to init all of the subregs to ones else init to 0. */
3196 sbitmap_ones (live_subregs[allocnum]);
3198 sbitmap_zero (live_subregs[allocnum]);
3200 /* Set the number of bits that we really want. */
3201 live_subregs_used[allocnum] = size;
3204 /* Walk the insns of the current function and build reload_insn_chain,
3205 and record register life information. */
3207 build_insn_chain (void)
3210 struct insn_chain **p = &reload_insn_chain;
3212 struct insn_chain *c = NULL;
3213 struct insn_chain *next = NULL;
3214 bitmap live_relevant_regs = BITMAP_ALLOC (NULL);
3215 bitmap elim_regset = BITMAP_ALLOC (NULL);
3216 /* live_subregs is a vector used to keep accurate information about
3217 which hardregs are live in multiword pseudos. live_subregs and
3218 live_subregs_used are indexed by pseudo number. The live_subreg
3219 entry for a particular pseudo is only used if the corresponding
3220 element is non zero in live_subregs_used. The value in
3221 live_subregs_used is number of bytes that the pseudo can
3223 sbitmap *live_subregs = XCNEWVEC (sbitmap, max_regno);
3224 int *live_subregs_used = XNEWVEC (int, max_regno);
3226 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3227 if (TEST_HARD_REG_BIT (eliminable_regset, i))
3228 bitmap_set_bit (elim_regset, i);
3229 FOR_EACH_BB_REVERSE (bb)
3234 CLEAR_REG_SET (live_relevant_regs);
3235 memset (live_subregs_used, 0, max_regno * sizeof (int));
3237 EXECUTE_IF_SET_IN_BITMAP (DF_LR_OUT (bb), 0, i, bi)
3239 if (i >= FIRST_PSEUDO_REGISTER)
3241 bitmap_set_bit (live_relevant_regs, i);
3244 EXECUTE_IF_SET_IN_BITMAP (DF_LR_OUT (bb),
3245 FIRST_PSEUDO_REGISTER, i, bi)
3247 if (pseudo_for_reload_consideration_p (i))
3248 bitmap_set_bit (live_relevant_regs, i);
3251 FOR_BB_INSNS_REVERSE (bb, insn)
3253 if (!NOTE_P (insn) && !BARRIER_P (insn))
3255 unsigned int uid = INSN_UID (insn);
3259 c = new_insn_chain ();
3266 c->block = bb->index;
3269 for (def_rec = DF_INSN_UID_DEFS (uid); *def_rec; def_rec++)
3271 df_ref def = *def_rec;
3272 unsigned int regno = DF_REF_REGNO (def);
3274 /* Ignore may clobbers because these are generated
3275 from calls. However, every other kind of def is
3276 added to dead_or_set. */
3277 if (!DF_REF_FLAGS_IS_SET (def, DF_REF_MAY_CLOBBER))
3279 if (regno < FIRST_PSEUDO_REGISTER)
3281 if (!fixed_regs[regno])
3282 bitmap_set_bit (&c->dead_or_set, regno);
3284 else if (pseudo_for_reload_consideration_p (regno))
3285 bitmap_set_bit (&c->dead_or_set, regno);
3288 if ((regno < FIRST_PSEUDO_REGISTER
3289 || reg_renumber[regno] >= 0
3291 && (!DF_REF_FLAGS_IS_SET (def, DF_REF_CONDITIONAL)))
3293 rtx reg = DF_REF_REG (def);
3295 /* We can model subregs, but not if they are
3296 wrapped in ZERO_EXTRACTS. */
3297 if (GET_CODE (reg) == SUBREG
3298 && !DF_REF_FLAGS_IS_SET (def, DF_REF_ZERO_EXTRACT))
3300 unsigned int start = SUBREG_BYTE (reg);
3301 unsigned int last = start
3302 + GET_MODE_SIZE (GET_MODE (reg));
3305 (bitmap_bit_p (live_relevant_regs, regno),
3306 live_subregs, live_subregs_used, regno, reg);
3308 if (!DF_REF_FLAGS_IS_SET
3309 (def, DF_REF_STRICT_LOW_PART))
3311 /* Expand the range to cover entire words.
3312 Bytes added here are "don't care". */
3314 = start / UNITS_PER_WORD * UNITS_PER_WORD;
3315 last = ((last + UNITS_PER_WORD - 1)
3316 / UNITS_PER_WORD * UNITS_PER_WORD);
3319 /* Ignore the paradoxical bits. */
3320 if ((int)last > live_subregs_used[regno])
3321 last = live_subregs_used[regno];
3323 while (start < last)
3325 RESET_BIT (live_subregs[regno], start);
3329 if (sbitmap_empty_p (live_subregs[regno]))
3331 live_subregs_used[regno] = 0;
3332 bitmap_clear_bit (live_relevant_regs, regno);
3335 /* Set live_relevant_regs here because
3336 that bit has to be true to get us to
3337 look at the live_subregs fields. */
3338 bitmap_set_bit (live_relevant_regs, regno);
3342 /* DF_REF_PARTIAL is generated for
3343 subregs, STRICT_LOW_PART, and
3344 ZERO_EXTRACT. We handle the subreg
3345 case above so here we have to keep from
3346 modeling the def as a killing def. */
3347 if (!DF_REF_FLAGS_IS_SET (def, DF_REF_PARTIAL))
3349 bitmap_clear_bit (live_relevant_regs, regno);
3350 live_subregs_used[regno] = 0;
3356 bitmap_and_compl_into (live_relevant_regs, elim_regset);
3357 bitmap_copy (&c->live_throughout, live_relevant_regs);
3360 for (use_rec = DF_INSN_UID_USES (uid); *use_rec; use_rec++)
3362 df_ref use = *use_rec;
3363 unsigned int regno = DF_REF_REGNO (use);
3364 rtx reg = DF_REF_REG (use);
3366 /* DF_REF_READ_WRITE on a use means that this use
3367 is fabricated from a def that is a partial set
3368 to a multiword reg. Here, we only model the
3369 subreg case that is not wrapped in ZERO_EXTRACT
3370 precisely so we do not need to look at the
3372 if (DF_REF_FLAGS_IS_SET (use, DF_REF_READ_WRITE)
3373 && !DF_REF_FLAGS_IS_SET (use, DF_REF_ZERO_EXTRACT)
3374 && DF_REF_FLAGS_IS_SET (use, DF_REF_SUBREG))
3377 /* Add the last use of each var to dead_or_set. */
3378 if (!bitmap_bit_p (live_relevant_regs, regno))
3380 if (regno < FIRST_PSEUDO_REGISTER)
3382 if (!fixed_regs[regno])
3383 bitmap_set_bit (&c->dead_or_set, regno);
3385 else if (pseudo_for_reload_consideration_p (regno))
3386 bitmap_set_bit (&c->dead_or_set, regno);
3389 if (regno < FIRST_PSEUDO_REGISTER
3390 || pseudo_for_reload_consideration_p (regno))
3392 if (GET_CODE (reg) == SUBREG
3393 && !DF_REF_FLAGS_IS_SET (use,
3395 | DF_REF_ZERO_EXTRACT))
3397 unsigned int start = SUBREG_BYTE (reg);
3398 unsigned int last = start
3399 + GET_MODE_SIZE (GET_MODE (reg));
3402 (bitmap_bit_p (live_relevant_regs, regno),
3403 live_subregs, live_subregs_used, regno, reg);
3405 /* Ignore the paradoxical bits. */
3406 if ((int)last > live_subregs_used[regno])
3407 last = live_subregs_used[regno];
3409 while (start < last)
3411 SET_BIT (live_subregs[regno], start);
3416 /* Resetting the live_subregs_used is
3417 effectively saying do not use the subregs
3418 because we are reading the whole
3420 live_subregs_used[regno] = 0;
3421 bitmap_set_bit (live_relevant_regs, regno);
3427 /* FIXME!! The following code is a disaster. Reload needs to see the
3428 labels and jump tables that are just hanging out in between
3429 the basic blocks. See pr33676. */
3430 insn = BB_HEAD (bb);
3432 /* Skip over the barriers and cruft. */
3433 while (insn && (BARRIER_P (insn) || NOTE_P (insn)
3434 || BLOCK_FOR_INSN (insn) == bb))
3435 insn = PREV_INSN (insn);
3437 /* While we add anything except barriers and notes, the focus is
3438 to get the labels and jump tables into the
3439 reload_insn_chain. */
3442 if (!NOTE_P (insn) && !BARRIER_P (insn))
3444 if (BLOCK_FOR_INSN (insn))
3447 c = new_insn_chain ();
3453 /* The block makes no sense here, but it is what the old
3455 c->block = bb->index;
3457 bitmap_copy (&c->live_throughout, live_relevant_regs);
3459 insn = PREV_INSN (insn);
3463 for (i = 0; i < (unsigned int) max_regno; i++)
3464 if (live_subregs[i])
3465 free (live_subregs[i]);
3467 reload_insn_chain = c;
3470 free (live_subregs);
3471 free (live_subregs_used);
3472 BITMAP_FREE (live_relevant_regs);
3473 BITMAP_FREE (elim_regset);
3476 print_insn_chains (dump_file);
3481 /* All natural loops. */
3482 struct loops ira_loops;
3484 /* True if we have allocno conflicts. It is false for non-optimized
3485 mode or when the conflict table is too big. */
3486 bool ira_conflicts_p;
3488 /* This is the main entry of IRA. */
3492 int overall_cost_before, allocated_reg_info_size;
3494 int max_regno_before_ira, ira_max_point_before_emit;
3496 int saved_flag_ira_share_spill_slots;
3499 timevar_push (TV_IRA);
3501 if (flag_caller_saves)
3502 init_caller_save ();
3504 if (flag_ira_verbose < 10)
3506 internal_flag_ira_verbose = flag_ira_verbose;
3511 internal_flag_ira_verbose = flag_ira_verbose - 10;
3512 ira_dump_file = stderr;
3515 ira_conflicts_p = optimize > 0;
3516 setup_prohibited_mode_move_regs ();
3518 df_note_add_problem ();
3522 df_live_add_problem ();
3523 df_live_set_all_dirty ();
3525 #ifdef ENABLE_CHECKING
3526 df->changeable_flags |= DF_VERIFY_SCHEDULED;
3529 df_clear_flags (DF_NO_INSN_RESCAN);
3530 regstat_init_n_sets_and_refs ();
3531 regstat_compute_ri ();
3533 /* If we are not optimizing, then this is the only place before
3534 register allocation where dataflow is done. And that is needed
3535 to generate these warnings. */
3537 generate_setjmp_warnings ();
3539 /* Determine if the current function is a leaf before running IRA
3540 since this can impact optimizations done by the prologue and
3541 epilogue thus changing register elimination offsets. */
3542 current_function_is_leaf = leaf_function_p ();
3544 if (resize_reg_info () && flag_ira_loop_pressure)
3545 ira_set_pseudo_classes (ira_dump_file);
3547 rebuild_p = update_equiv_regs ();
3549 #ifndef IRA_NO_OBSTACK
3550 gcc_obstack_init (&ira_obstack);
3552 bitmap_obstack_initialize (&ira_bitmap_obstack);
3555 max_regno = max_reg_num ();
3556 ira_reg_equiv_len = max_regno;
3557 ira_reg_equiv_invariant_p
3558 = (bool *) ira_allocate (max_regno * sizeof (bool));
3559 memset (ira_reg_equiv_invariant_p, 0, max_regno * sizeof (bool));
3560 ira_reg_equiv_const = (rtx *) ira_allocate (max_regno * sizeof (rtx));
3561 memset (ira_reg_equiv_const, 0, max_regno * sizeof (rtx));
3562 find_reg_equiv_invariant_const ();
3565 timevar_push (TV_JUMP);
3566 rebuild_jump_labels (get_insns ());
3567 if (purge_all_dead_edges ())
3568 delete_unreachable_blocks ();
3569 timevar_pop (TV_JUMP);
3573 max_regno_before_ira = allocated_reg_info_size = max_reg_num ();
3574 ira_setup_eliminable_regset ();
3576 ira_overall_cost = ira_reg_cost = ira_mem_cost = 0;
3577 ira_load_cost = ira_store_cost = ira_shuffle_cost = 0;
3578 ira_move_loops_num = ira_additional_jumps_num = 0;
3580 ira_assert (current_loops == NULL);
3581 flow_loops_find (&ira_loops);
3582 record_loop_exits ();
3583 current_loops = &ira_loops;
3585 if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL)
3586 fprintf (ira_dump_file, "Building IRA IR\n");
3587 loops_p = ira_build (optimize
3588 && (flag_ira_region == IRA_REGION_ALL
3589 || flag_ira_region == IRA_REGION_MIXED));
3591 ira_assert (ira_conflicts_p || !loops_p);
3593 saved_flag_ira_share_spill_slots = flag_ira_share_spill_slots;
3594 if (too_high_register_pressure_p () || cfun->calls_setjmp)
3595 /* It is just wasting compiler's time to pack spilled pseudos into
3596 stack slots in this case -- prohibit it. We also do this if
3597 there is setjmp call because a variable not modified between
3598 setjmp and longjmp the compiler is required to preserve its
3599 value and sharing slots does not guarantee it. */
3600 flag_ira_share_spill_slots = FALSE;
3604 ira_max_point_before_emit = ira_max_point;
3606 ira_initiate_emit_data ();
3610 if (ira_conflicts_p)
3612 max_regno = max_reg_num ();
3615 ira_initiate_assign ();
3618 expand_reg_info (allocated_reg_info_size);
3619 setup_preferred_alternate_classes_for_new_pseudos
3620 (allocated_reg_info_size);
3621 allocated_reg_info_size = max_regno;
3623 if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL)
3624 fprintf (ira_dump_file, "Flattening IR\n");
3625 ira_flattening (max_regno_before_ira, ira_max_point_before_emit);
3626 /* New insns were generated: add notes and recalculate live
3630 flow_loops_find (&ira_loops);
3631 record_loop_exits ();
3632 current_loops = &ira_loops;
3634 setup_allocno_assignment_flags ();
3635 ira_initiate_assign ();
3636 ira_reassign_conflict_allocnos (max_regno);
3640 ira_finish_emit_data ();
3642 setup_reg_renumber ();
3644 calculate_allocation_cost ();
3646 #ifdef ENABLE_IRA_CHECKING
3647 if (ira_conflicts_p)
3648 check_allocation ();
3651 if (delete_trivially_dead_insns (get_insns (), max_reg_num ()))
3654 if (max_regno != max_regno_before_ira)
3656 regstat_free_n_sets_and_refs ();
3658 regstat_init_n_sets_and_refs ();
3659 regstat_compute_ri ();
3662 overall_cost_before = ira_overall_cost;
3663 if (! ira_conflicts_p)
3667 fix_reg_equiv_init ();
3669 #ifdef ENABLE_IRA_CHECKING
3670 print_redundant_copies ();
3673 ira_spilled_reg_stack_slots_num = 0;
3674 ira_spilled_reg_stack_slots
3675 = ((struct ira_spilled_reg_stack_slot *)
3676 ira_allocate (max_regno
3677 * sizeof (struct ira_spilled_reg_stack_slot)));
3678 memset (ira_spilled_reg_stack_slots, 0,
3679 max_regno * sizeof (struct ira_spilled_reg_stack_slot));
3681 allocate_initial_values (reg_equivs);
3683 timevar_pop (TV_IRA);
3685 timevar_push (TV_RELOAD);
3686 df_set_flags (DF_NO_INSN_RESCAN);
3687 build_insn_chain ();
3689 reload_completed = !reload (get_insns (), ira_conflicts_p);
3691 timevar_pop (TV_RELOAD);
3693 timevar_push (TV_IRA);
3695 if (ira_conflicts_p)
3697 ira_free (ira_spilled_reg_stack_slots);
3699 ira_finish_assign ();
3702 if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL
3703 && overall_cost_before != ira_overall_cost)
3704 fprintf (ira_dump_file, "+++Overall after reload %d\n", ira_overall_cost);
3707 flag_ira_share_spill_slots = saved_flag_ira_share_spill_slots;
3709 flow_loops_free (&ira_loops);
3710 free_dominance_info (CDI_DOMINATORS);
3712 bb->loop_father = NULL;
3713 current_loops = NULL;
3716 regstat_free_n_sets_and_refs ();
3720 cleanup_cfg (CLEANUP_EXPENSIVE);
3722 ira_free (ira_reg_equiv_invariant_p);
3723 ira_free (ira_reg_equiv_const);
3726 bitmap_obstack_release (&ira_bitmap_obstack);
3727 #ifndef IRA_NO_OBSTACK
3728 obstack_free (&ira_obstack, NULL);
3731 /* The code after the reload has changed so much that at this point
3732 we might as well just rescan everything. Not that
3733 df_rescan_all_insns is not going to help here because it does not
3734 touch the artificial uses and defs. */
3735 df_finish_pass (true);
3737 df_live_add_problem ();
3738 df_scan_alloc (NULL);
3744 timevar_pop (TV_IRA);
3755 /* Run the integrated register allocator. */
3757 rest_of_handle_ira (void)
3763 struct rtl_opt_pass pass_ira =
3768 gate_ira, /* gate */
3769 rest_of_handle_ira, /* execute */
3772 0, /* static_pass_number */
3773 TV_NONE, /* tv_id */
3774 0, /* properties_required */
3775 0, /* properties_provided */
3776 0, /* properties_destroyed */
3777 0, /* todo_flags_start */
3779 TODO_ggc_collect /* todo_flags_finish */