1 /* IRA processing allocno lives to build allocno live ranges.
2 Copyright (C) 2006, 2007, 2008, 2009
3 Free Software Foundation, Inc.
4 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
32 #include "hard-reg-set.h"
33 #include "basic-block.h"
34 #include "insn-config.h"
39 #include "sparseset.h"
42 /* The code in this file is similar to one in global but the code
43 works on the allocno basis and creates live ranges instead of
44 pseudo-register conflicts. */
46 /* Program points are enumerated by numbers from range
47 0..IRA_MAX_POINT-1. There are approximately two times more program
48 points than insns. Program points are places in the program where
49 liveness info can be changed. In most general case (there are more
50 complicated cases too) some program points correspond to places
51 where input operand dies and other ones correspond to places where
52 output operands are born. */
55 /* Arrays of size IRA_MAX_POINT mapping a program point to the allocno
56 live ranges with given start/finish point. */
57 allocno_live_range_t *ira_start_point_ranges, *ira_finish_point_ranges;
59 /* Number of the current program point. */
60 static int curr_point;
62 /* Point where register pressure excess started or -1 if there is no
63 register pressure excess. Excess pressure for a register class at
64 some point means that there are more allocnos of given register
65 class living at the point than number of hard-registers of the
66 class available for the allocation. It is defined only for cover
68 static int high_pressure_start_point[N_REG_CLASSES];
70 /* Allocnos live at current point in the scan. */
71 static sparseset allocnos_live;
73 /* Set of hard regs (except eliminable ones) currently live. */
74 static HARD_REG_SET hard_regs_live;
76 /* The loop tree node corresponding to the current basic block. */
77 static ira_loop_tree_node_t curr_bb_node;
79 /* The number of the last processed call. */
80 static int last_call_num;
81 /* The number of last call at which given allocno was saved. */
82 static int *allocno_saved_at_call;
84 /* The function processing birth of register REGNO. It updates living
85 hard regs and conflict hard regs for living allocnos or starts a
86 new live range for the allocno corresponding to REGNO if it is
89 make_regno_born (int regno)
93 allocno_live_range_t p;
95 if (regno < FIRST_PSEUDO_REGISTER)
97 SET_HARD_REG_BIT (hard_regs_live, regno);
98 EXECUTE_IF_SET_IN_SPARSESET (allocnos_live, i)
100 SET_HARD_REG_BIT (ALLOCNO_CONFLICT_HARD_REGS (ira_allocnos[i]),
102 SET_HARD_REG_BIT (ALLOCNO_TOTAL_CONFLICT_HARD_REGS (ira_allocnos[i]),
107 a = ira_curr_regno_allocno_map[regno];
110 if ((p = ALLOCNO_LIVE_RANGES (a)) == NULL
111 || (p->finish != curr_point && p->finish + 1 != curr_point))
112 ALLOCNO_LIVE_RANGES (a)
113 = ira_create_allocno_live_range (a, curr_point, -1,
114 ALLOCNO_LIVE_RANGES (a));
117 /* Update ALLOCNO_EXCESS_PRESSURE_POINTS_NUM for allocno A. */
119 update_allocno_pressure_excess_length (ira_allocno_t a)
122 enum reg_class cover_class, cl;
123 allocno_live_range_t p;
125 cover_class = ALLOCNO_COVER_CLASS (a);
127 (cl = ira_reg_class_super_classes[cover_class][i]) != LIM_REG_CLASSES;
130 if (high_pressure_start_point[cl] < 0)
132 p = ALLOCNO_LIVE_RANGES (a);
133 ira_assert (p != NULL);
134 start = (high_pressure_start_point[cl] > p->start
135 ? high_pressure_start_point[cl] : p->start);
136 ALLOCNO_EXCESS_PRESSURE_POINTS_NUM (a) += curr_point - start + 1;
140 /* Process the death of register REGNO. This updates hard_regs_live
141 or finishes the current live range for the allocno corresponding to
144 make_regno_dead (int regno)
147 allocno_live_range_t p;
149 if (regno < FIRST_PSEUDO_REGISTER)
151 CLEAR_HARD_REG_BIT (hard_regs_live, regno);
154 a = ira_curr_regno_allocno_map[regno];
157 p = ALLOCNO_LIVE_RANGES (a);
158 ira_assert (p != NULL);
159 p->finish = curr_point;
160 update_allocno_pressure_excess_length (a);
163 /* The current register pressures for each cover class for the current
165 static int curr_reg_pressure[N_REG_CLASSES];
167 /* Mark allocno A as currently living and update current register
168 pressure, maximal register pressure for the current BB, start point
169 of the register pressure excess, and conflicting hard registers of
172 set_allocno_live (ira_allocno_t a)
175 enum reg_class cover_class, cl;
177 /* Invalidate because it is referenced. */
178 allocno_saved_at_call[ALLOCNO_NUM (a)] = 0;
179 if (sparseset_bit_p (allocnos_live, ALLOCNO_NUM (a)))
181 sparseset_set_bit (allocnos_live, ALLOCNO_NUM (a));
182 IOR_HARD_REG_SET (ALLOCNO_CONFLICT_HARD_REGS (a), hard_regs_live);
183 IOR_HARD_REG_SET (ALLOCNO_TOTAL_CONFLICT_HARD_REGS (a), hard_regs_live);
184 cover_class = ALLOCNO_COVER_CLASS (a);
186 (cl = ira_reg_class_super_classes[cover_class][i]) != LIM_REG_CLASSES;
189 curr_reg_pressure[cl] += ira_reg_class_nregs[cl][ALLOCNO_MODE (a)];
190 if (high_pressure_start_point[cl] < 0
191 && (curr_reg_pressure[cl] > ira_available_class_regs[cl]))
192 high_pressure_start_point[cl] = curr_point;
193 if (curr_bb_node->reg_pressure[cl] < curr_reg_pressure[cl])
194 curr_bb_node->reg_pressure[cl] = curr_reg_pressure[cl];
198 /* Mark allocno A as currently not living and update current register
199 pressure, start point of the register pressure excess, and register
200 pressure excess length for living allocnos. */
202 clear_allocno_live (ira_allocno_t a)
206 enum reg_class cover_class, cl;
209 /* Invalidate because it is referenced. */
210 allocno_saved_at_call[ALLOCNO_NUM (a)] = 0;
211 if (sparseset_bit_p (allocnos_live, ALLOCNO_NUM (a)))
213 cover_class = ALLOCNO_COVER_CLASS (a);
216 (cl = ira_reg_class_super_classes[cover_class][i])
220 curr_reg_pressure[cl] -= ira_reg_class_nregs[cl][ALLOCNO_MODE (a)];
221 ira_assert (curr_reg_pressure[cl] >= 0);
222 if (high_pressure_start_point[cl] >= 0
223 && curr_reg_pressure[cl] <= ira_available_class_regs[cl])
228 EXECUTE_IF_SET_IN_SPARSESET (allocnos_live, j)
229 update_allocno_pressure_excess_length (ira_allocnos[j]);
231 (cl = ira_reg_class_super_classes[cover_class][i])
234 if (high_pressure_start_point[cl] >= 0
235 && curr_reg_pressure[cl] <= ira_available_class_regs[cl])
236 high_pressure_start_point[cl] = -1;
240 sparseset_clear_bit (allocnos_live, ALLOCNO_NUM (a));
243 /* Mark the register REG as live. Store a 1 in hard_regs_live or
244 allocnos_live for this register or the corresponding allocno,
245 record how many consecutive hardware registers it actually
248 mark_reg_live (rtx reg)
252 gcc_assert (REG_P (reg));
255 if (regno >= FIRST_PSEUDO_REGISTER)
257 ira_allocno_t a = ira_curr_regno_allocno_map[regno];
261 if (sparseset_bit_p (allocnos_live, ALLOCNO_NUM (a)))
263 /* Invalidate because it is referenced. */
264 allocno_saved_at_call[ALLOCNO_NUM (a)] = 0;
267 set_allocno_live (a);
269 make_regno_born (regno);
271 else if (! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno))
273 int last = regno + hard_regno_nregs[regno][GET_MODE (reg)];
274 enum reg_class cover_class, cl;
278 if (! TEST_HARD_REG_BIT (hard_regs_live, regno)
279 && ! TEST_HARD_REG_BIT (eliminable_regset, regno))
281 cover_class = ira_hard_regno_cover_class[regno];
283 (cl = ira_reg_class_super_classes[cover_class][i])
287 curr_reg_pressure[cl]++;
288 if (high_pressure_start_point[cl] < 0
289 && (curr_reg_pressure[cl]
290 > ira_available_class_regs[cl]))
291 high_pressure_start_point[cl] = curr_point;
293 make_regno_born (regno);
295 (cl = ira_reg_class_super_classes[cover_class][i])
299 if (curr_bb_node->reg_pressure[cl] < curr_reg_pressure[cl])
300 curr_bb_node->reg_pressure[cl] = curr_reg_pressure[cl];
308 /* Mark the register referenced by use or def REF as live. */
310 mark_ref_live (df_ref ref)
314 reg = DF_REF_REG (ref);
315 if (GET_CODE (reg) == SUBREG)
316 reg = SUBREG_REG (reg);
320 /* Mark the register REG as dead. Store a 0 in hard_regs_live or
321 allocnos_live for the register. */
323 mark_reg_dead (rtx reg)
327 gcc_assert (REG_P (reg));
330 if (regno >= FIRST_PSEUDO_REGISTER)
332 ira_allocno_t a = ira_curr_regno_allocno_map[regno];
336 if (! sparseset_bit_p (allocnos_live, ALLOCNO_NUM (a)))
338 /* Invalidate because it is referenced. */
339 allocno_saved_at_call[ALLOCNO_NUM (a)] = 0;
342 clear_allocno_live (a);
344 make_regno_dead (regno);
346 else if (! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno))
350 int last = regno + hard_regno_nregs[regno][GET_MODE (reg)];
351 enum reg_class cover_class, cl;
356 if (TEST_HARD_REG_BIT (hard_regs_live, regno))
359 cover_class = ira_hard_regno_cover_class[regno];
361 (cl = ira_reg_class_super_classes[cover_class][i])
365 curr_reg_pressure[cl]--;
366 if (high_pressure_start_point[cl] >= 0
367 && curr_reg_pressure[cl] <= ira_available_class_regs[cl])
369 ira_assert (curr_reg_pressure[cl] >= 0);
373 EXECUTE_IF_SET_IN_SPARSESET (allocnos_live, j)
374 update_allocno_pressure_excess_length (ira_allocnos[j]);
376 (cl = ira_reg_class_super_classes[cover_class][i])
379 if (high_pressure_start_point[cl] >= 0
380 && (curr_reg_pressure[cl]
381 <= ira_available_class_regs[cl]))
382 high_pressure_start_point[cl] = -1;
384 make_regno_dead (regno);
391 /* Mark the register referenced by definition DEF as dead, if the
392 definition is a total one. */
394 mark_ref_dead (df_ref def)
398 if (DF_REF_FLAGS_IS_SET (def, DF_REF_PARTIAL)
399 || DF_REF_FLAGS_IS_SET (def, DF_REF_CONDITIONAL))
402 reg = DF_REF_REG (def);
403 if (GET_CODE (reg) == SUBREG)
404 reg = SUBREG_REG (reg);
408 /* Make pseudo REG conflicting with pseudo DREG, if the 1st pseudo
409 class is intersected with class CL. Advance the current program
410 point before making the conflict if ADVANCE_P. Return TRUE if we
411 will need to advance the current program point. */
413 make_pseudo_conflict (rtx reg, enum reg_class cl, rtx dreg, bool advance_p)
417 if (GET_CODE (reg) == SUBREG)
418 reg = SUBREG_REG (reg);
420 if (! REG_P (reg) || REGNO (reg) < FIRST_PSEUDO_REGISTER)
423 a = ira_curr_regno_allocno_map[REGNO (reg)];
424 if (! reg_classes_intersect_p (cl, ALLOCNO_COVER_CLASS (a)))
431 mark_reg_live (dreg);
433 mark_reg_dead (dreg);
438 /* Check and make if necessary conflicts for pseudo DREG of class
439 DEF_CL of the current insn with input operand USE of class USE_CL.
440 Advance the current program point before making the conflict if
441 ADVANCE_P. Return TRUE if we will need to advance the current
444 check_and_make_def_use_conflict (rtx dreg, enum reg_class def_cl,
445 int use, enum reg_class use_cl,
448 if (! reg_classes_intersect_p (def_cl, use_cl))
451 advance_p = make_pseudo_conflict (recog_data.operand[use],
452 use_cl, dreg, advance_p);
453 /* Reload may end up swapping commutative operands, so you
454 have to take both orderings into account. The
455 constraints for the two operands can be completely
456 different. (Indeed, if the constraints for the two
457 operands are the same for all alternatives, there's no
458 point marking them as commutative.) */
459 if (use < recog_data.n_operands + 1
460 && recog_data.constraints[use][0] == '%')
462 = make_pseudo_conflict (recog_data.operand[use + 1],
463 use_cl, dreg, advance_p);
465 && recog_data.constraints[use - 1][0] == '%')
467 = make_pseudo_conflict (recog_data.operand[use - 1],
468 use_cl, dreg, advance_p);
472 /* Check and make if necessary conflicts for definition DEF of class
473 DEF_CL of the current insn with input operands. Process only
474 constraints of alternative ALT. */
476 check_and_make_def_conflict (int alt, int def, enum reg_class def_cl)
480 enum reg_class use_cl, acl;
482 rtx dreg = recog_data.operand[def];
484 if (def_cl == NO_REGS)
487 if (GET_CODE (dreg) == SUBREG)
488 dreg = SUBREG_REG (dreg);
490 if (! REG_P (dreg) || REGNO (dreg) < FIRST_PSEUDO_REGISTER)
493 a = ira_curr_regno_allocno_map[REGNO (dreg)];
494 acl = ALLOCNO_COVER_CLASS (a);
495 if (! reg_classes_intersect_p (acl, def_cl))
500 for (use = 0; use < recog_data.n_operands; use++)
502 if (use == def || recog_data.operand_type[use] == OP_OUT)
505 if (recog_op_alt[use][alt].anything_ok)
508 use_cl = recog_op_alt[use][alt].cl;
510 advance_p = check_and_make_def_use_conflict (dreg, def_cl, use,
513 if ((use_match = recog_op_alt[use][alt].matches) >= 0)
515 if (use_match == def)
518 if (recog_op_alt[use_match][alt].anything_ok)
521 use_cl = recog_op_alt[use_match][alt].cl;
522 advance_p = check_and_make_def_use_conflict (dreg, def_cl, use,
528 /* Make conflicts of early clobber pseudo registers of the current
529 insn with its inputs. Avoid introducing unnecessary conflicts by
530 checking classes of the constraints and pseudos because otherwise
531 significant code degradation is possible for some targets. */
533 make_early_clobber_and_input_conflicts (void)
537 enum reg_class def_cl;
539 for (alt = 0; alt < recog_data.n_alternatives; alt++)
540 for (def = 0; def < recog_data.n_operands; def++)
543 if (recog_op_alt[def][alt].earlyclobber)
545 if (recog_op_alt[def][alt].anything_ok)
548 def_cl = recog_op_alt[def][alt].cl;
549 check_and_make_def_conflict (alt, def, def_cl);
551 if ((def_match = recog_op_alt[def][alt].matches) >= 0
552 && (recog_op_alt[def_match][alt].earlyclobber
553 || recog_op_alt[def][alt].earlyclobber))
555 if (recog_op_alt[def_match][alt].anything_ok)
558 def_cl = recog_op_alt[def_match][alt].cl;
559 check_and_make_def_conflict (alt, def, def_cl);
564 /* Mark early clobber hard registers of the current INSN as live (if
565 LIVE_P) or dead. Return true if there are such registers. */
567 mark_hard_reg_early_clobbers (rtx insn, bool live_p)
572 for (def_rec = DF_INSN_DEFS (insn); *def_rec; def_rec++)
573 if (DF_REF_FLAGS_IS_SET (*def_rec, DF_REF_MUST_CLOBBER))
575 rtx dreg = DF_REF_REG (*def_rec);
577 if (GET_CODE (dreg) == SUBREG)
578 dreg = SUBREG_REG (dreg);
579 if (! REG_P (dreg) || REGNO (dreg) >= FIRST_PSEUDO_REGISTER)
582 /* Hard register clobbers are believed to be early clobber
583 because there is no way to say that non-operand hard
584 register clobbers are not early ones. */
586 mark_ref_live (*def_rec);
588 mark_ref_dead (*def_rec);
595 /* Checks that CONSTRAINTS permits to use only one hard register. If
596 it is so, the function returns the class of the hard register.
597 Otherwise it returns NO_REGS. */
598 static enum reg_class
599 single_reg_class (const char *constraints, rtx op, rtx equiv_const)
602 enum reg_class cl, next_cl;
606 for (ignore_p = false;
608 constraints += CONSTRAINT_LEN (c, constraints))
628 || (equiv_const != NULL_RTX && CONSTANT_P (equiv_const)))
634 || (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == VOIDmode)
635 || (equiv_const != NULL_RTX
636 && (CONST_INT_P (equiv_const)
637 || (GET_CODE (equiv_const) == CONST_DOUBLE
638 && GET_MODE (equiv_const) == VOIDmode))))
643 if ((CONSTANT_P (op) && !CONST_INT_P (op)
644 && (GET_CODE (op) != CONST_DOUBLE || GET_MODE (op) != VOIDmode))
645 || (equiv_const != NULL_RTX
646 && CONSTANT_P (equiv_const)
647 && !CONST_INT_P (equiv_const)
648 && (GET_CODE (equiv_const) != CONST_DOUBLE
649 || GET_MODE (equiv_const) != VOIDmode)))
661 if ((CONST_INT_P (op)
662 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), c, constraints))
663 || (equiv_const != NULL_RTX
664 && CONST_INT_P (equiv_const)
665 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (equiv_const),
672 if (GET_CODE (op) == CONST_DOUBLE
673 || (GET_CODE (op) == CONST_VECTOR
674 && GET_MODE_CLASS (GET_MODE (op)) == MODE_VECTOR_FLOAT)
675 || (equiv_const != NULL_RTX
676 && (GET_CODE (equiv_const) == CONST_DOUBLE
677 || (GET_CODE (equiv_const) == CONST_VECTOR
678 && (GET_MODE_CLASS (GET_MODE (equiv_const))
679 == MODE_VECTOR_FLOAT)))))
685 if ((GET_CODE (op) == CONST_DOUBLE
686 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, c, constraints))
687 || (equiv_const != NULL_RTX
688 && GET_CODE (equiv_const) == CONST_DOUBLE
689 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (equiv_const,
692 /* ??? what about memory */
694 case 'a': case 'b': case 'c': case 'd': case 'e': case 'f':
695 case 'h': case 'j': case 'k': case 'l':
696 case 'q': case 't': case 'u':
697 case 'v': case 'w': case 'x': case 'y': case 'z':
698 case 'A': case 'B': case 'C': case 'D':
699 case 'Q': case 'R': case 'S': case 'T': case 'U':
700 case 'W': case 'Y': case 'Z':
703 : REG_CLASS_FROM_CONSTRAINT (c, constraints));
704 if ((cl != NO_REGS && next_cl != cl)
705 || (ira_available_class_regs[next_cl]
706 > ira_reg_class_nregs[next_cl][GET_MODE (op)]))
711 case '0': case '1': case '2': case '3': case '4':
712 case '5': case '6': case '7': case '8': case '9':
714 = single_reg_class (recog_data.constraints[c - '0'],
715 recog_data.operand[c - '0'], NULL_RTX);
716 if ((cl != NO_REGS && next_cl != cl)
717 || next_cl == NO_REGS
718 || (ira_available_class_regs[next_cl]
719 > ira_reg_class_nregs[next_cl][GET_MODE (op)]))
730 /* The function checks that operand OP_NUM of the current insn can use
731 only one hard register. If it is so, the function returns the
732 class of the hard register. Otherwise it returns NO_REGS. */
733 static enum reg_class
734 single_reg_operand_class (int op_num)
736 if (op_num < 0 || recog_data.n_alternatives == 0)
738 return single_reg_class (recog_data.constraints[op_num],
739 recog_data.operand[op_num], NULL_RTX);
742 /* The function sets up hard register set *SET to hard registers which
743 might be used by insn reloads because the constraints are too
746 ira_implicitly_set_insn_hard_regs (HARD_REG_SET *set)
752 enum machine_mode mode;
754 CLEAR_HARD_REG_SET (*set);
755 for (i = 0; i < recog_data.n_operands; i++)
757 op = recog_data.operand[i];
759 if (GET_CODE (op) == SUBREG)
760 op = SUBREG_REG (op);
762 if (GET_CODE (op) == SCRATCH
763 || (REG_P (op) && (regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER))
765 const char *p = recog_data.constraints[i];
767 mode = (GET_CODE (op) == SCRATCH
768 ? GET_MODE (op) : PSEUDO_REGNO_MODE (regno));
770 for (ignore_p = false; (c = *p); p += CONSTRAINT_LEN (c, p))
779 case 'a': case 'b': case 'c': case 'd': case 'e': case 'f':
780 case 'h': case 'j': case 'k': case 'l':
781 case 'q': case 't': case 'u':
782 case 'v': case 'w': case 'x': case 'y': case 'z':
783 case 'A': case 'B': case 'C': case 'D':
784 case 'Q': case 'R': case 'S': case 'T': case 'U':
785 case 'W': case 'Y': case 'Z':
788 : REG_CLASS_FROM_CONSTRAINT (c, p));
790 && (ira_available_class_regs[cl]
791 <= ira_reg_class_nregs[cl][mode]))
792 IOR_HARD_REG_SET (*set, reg_class_contents[cl]);
798 /* Processes input operands, if IN_P, or output operands otherwise of
799 the current insn with FREQ to find allocno which can use only one
800 hard register and makes other currently living allocnos conflicting
801 with the hard register. */
803 process_single_reg_class_operands (bool in_p, int freq)
807 enum reg_class cl, cover_class;
809 ira_allocno_t operand_a, a;
811 for (i = 0; i < recog_data.n_operands; i++)
813 operand = recog_data.operand[i];
814 if (in_p && recog_data.operand_type[i] != OP_IN
815 && recog_data.operand_type[i] != OP_INOUT)
817 if (! in_p && recog_data.operand_type[i] != OP_OUT
818 && recog_data.operand_type[i] != OP_INOUT)
820 cl = single_reg_operand_class (i);
826 if (GET_CODE (operand) == SUBREG)
827 operand = SUBREG_REG (operand);
830 && (regno = REGNO (operand)) >= FIRST_PSEUDO_REGISTER)
832 enum machine_mode mode;
833 enum reg_class cover_class;
835 operand_a = ira_curr_regno_allocno_map[regno];
836 mode = ALLOCNO_MODE (operand_a);
837 cover_class = ALLOCNO_COVER_CLASS (operand_a);
838 if (ira_class_subset_p[cl][cover_class]
839 && ira_class_hard_regs_num[cl] != 0
840 && (ira_class_hard_reg_index[cover_class]
841 [ira_class_hard_regs[cl][0]]) >= 0
842 && reg_class_size[cl] <= (unsigned) CLASS_MAX_NREGS (cl, mode))
847 ? ira_get_register_move_cost (mode, cover_class, cl)
848 : ira_get_register_move_cost (mode, cl, cover_class)));
849 ira_allocate_and_set_costs
850 (&ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a), cover_class, 0);
851 ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a)
852 [ira_class_hard_reg_index
853 [cover_class][ira_class_hard_regs[cl][0]]]
858 EXECUTE_IF_SET_IN_SPARSESET (allocnos_live, px)
860 a = ira_allocnos[px];
861 cover_class = ALLOCNO_COVER_CLASS (a);
864 /* We could increase costs of A instead of making it
865 conflicting with the hard register. But it works worse
866 because it will be spilled in reload in anyway. */
867 IOR_HARD_REG_SET (ALLOCNO_CONFLICT_HARD_REGS (a),
868 reg_class_contents[cl]);
869 IOR_HARD_REG_SET (ALLOCNO_TOTAL_CONFLICT_HARD_REGS (a),
870 reg_class_contents[cl]);
876 /* Return true when one of the predecessor edges of BB is marked with
877 EDGE_ABNORMAL_CALL or EDGE_EH. */
879 bb_has_abnormal_call_pred (basic_block bb)
884 FOR_EACH_EDGE (e, ei, bb->preds)
886 if (e->flags & (EDGE_ABNORMAL_CALL | EDGE_EH))
892 /* Process insns of the basic block given by its LOOP_TREE_NODE to
893 update allocno live ranges, allocno hard register conflicts,
894 intersected calls, and register pressure info for allocnos for the
895 basic block for and regions containing the basic block. */
897 process_bb_node_lives (ira_loop_tree_node_t loop_tree_node)
908 bb = loop_tree_node->bb;
911 for (i = 0; i < ira_reg_class_cover_size; i++)
913 curr_reg_pressure[ira_reg_class_cover[i]] = 0;
914 high_pressure_start_point[ira_reg_class_cover[i]] = -1;
916 curr_bb_node = loop_tree_node;
917 reg_live_out = DF_LR_OUT (bb);
918 sparseset_clear (allocnos_live);
919 REG_SET_TO_HARD_REG_SET (hard_regs_live, reg_live_out);
920 AND_COMPL_HARD_REG_SET (hard_regs_live, eliminable_regset);
921 AND_COMPL_HARD_REG_SET (hard_regs_live, ira_no_alloc_regs);
922 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
923 if (TEST_HARD_REG_BIT (hard_regs_live, i))
925 enum reg_class cover_class, cl;
927 cover_class = ira_class_translate[REGNO_REG_CLASS (i)];
929 (cl = ira_reg_class_super_classes[cover_class][j])
933 curr_reg_pressure[cl]++;
934 if (curr_bb_node->reg_pressure[cl] < curr_reg_pressure[cl])
935 curr_bb_node->reg_pressure[cl] = curr_reg_pressure[cl];
936 ira_assert (curr_reg_pressure[cl]
937 <= ira_available_class_regs[cl]);
940 EXECUTE_IF_SET_IN_BITMAP (reg_live_out, FIRST_PSEUDO_REGISTER, j, bi)
942 ira_allocno_t a = ira_curr_regno_allocno_map[j];
946 ira_assert (! sparseset_bit_p (allocnos_live, ALLOCNO_NUM (a)));
947 set_allocno_live (a);
951 freq = REG_FREQ_FROM_BB (bb);
955 /* Invalidate all allocno_saved_at_call entries. */
958 /* Scan the code of this basic block, noting which allocnos and
959 hard regs are born or die.
961 Note that this loop treats uninitialized values as live until
962 the beginning of the block. For example, if an instruction
963 uses (reg:DI foo), and only (subreg:SI (reg:DI foo) 0) is ever
964 set, FOO will remain live until the beginning of the block.
965 Likewise if FOO is not set at all. This is unnecessarily
966 pessimistic, but it probably doesn't matter much in practice. */
967 FOR_BB_INSNS_REVERSE (bb, insn)
969 df_ref *def_rec, *use_rec;
972 if (!NONDEBUG_INSN_P (insn))
975 if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL)
976 fprintf (ira_dump_file, " Insn %u(l%d): point = %d\n",
977 INSN_UID (insn), loop_tree_node->parent->loop->num,
980 /* Mark each defined value as live. We need to do this for
981 unused values because they still conflict with quantities
982 that are live at the time of the definition.
984 Ignore DF_REF_MAY_CLOBBERs on a call instruction. Such
985 references represent the effect of the called function
986 on a call-clobbered register. Marking the register as
987 live would stop us from allocating it to a call-crossing
989 call_p = CALL_P (insn);
990 for (def_rec = DF_INSN_DEFS (insn); *def_rec; def_rec++)
991 if (!call_p || !DF_REF_FLAGS_IS_SET (*def_rec, DF_REF_MAY_CLOBBER))
992 mark_ref_live (*def_rec);
994 /* If INSN has multiple outputs, then any value used in one
995 of the outputs conflicts with the other outputs. Model this
996 by making the used value live during the output phase.
998 It is unsafe to use !single_set here since it will ignore
999 an unused output. Just because an output is unused does
1000 not mean the compiler can assume the side effect will not
1001 occur. Consider if ALLOCNO appears in the address of an
1002 output and we reload the output. If we allocate ALLOCNO
1003 to the same hard register as an unused output we could
1004 set the hard register before the output reload insn. */
1005 if (GET_CODE (PATTERN (insn)) == PARALLEL && multiple_sets (insn))
1006 for (use_rec = DF_INSN_USES (insn); *use_rec; use_rec++)
1011 reg = DF_REF_REG (*use_rec);
1012 for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--)
1016 set = XVECEXP (PATTERN (insn), 0, i);
1017 if (GET_CODE (set) == SET
1018 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
1020 /* After the previous loop, this is a no-op if
1021 REG is contained within SET_DEST (SET). */
1022 mark_ref_live (*use_rec);
1028 extract_insn (insn);
1029 preprocess_constraints ();
1030 process_single_reg_class_operands (false, freq);
1032 /* See which defined values die here. */
1033 for (def_rec = DF_INSN_DEFS (insn); *def_rec; def_rec++)
1034 if (!call_p || !DF_REF_FLAGS_IS_SET (*def_rec, DF_REF_MAY_CLOBBER))
1035 mark_ref_dead (*def_rec);
1040 /* The current set of live allocnos are live across the call. */
1041 EXECUTE_IF_SET_IN_SPARSESET (allocnos_live, i)
1043 ira_allocno_t a = ira_allocnos[i];
1045 if (allocno_saved_at_call[i] != last_call_num)
1046 /* Here we are mimicking caller-save.c behaviour
1047 which does not save hard register at a call if
1048 it was saved on previous call in the same basic
1049 block and the hard register was not mentioned
1050 between the two calls. */
1051 ALLOCNO_CALL_FREQ (a) += freq;
1052 /* Mark it as saved at the next call. */
1053 allocno_saved_at_call[i] = last_call_num + 1;
1054 ALLOCNO_CALLS_CROSSED_NUM (a)++;
1055 /* Don't allocate allocnos that cross setjmps or any
1056 call, if this function receives a nonlocal
1058 if (cfun->has_nonlocal_label
1059 || find_reg_note (insn, REG_SETJMP,
1060 NULL_RTX) != NULL_RTX)
1062 SET_HARD_REG_SET (ALLOCNO_CONFLICT_HARD_REGS (a));
1063 SET_HARD_REG_SET (ALLOCNO_TOTAL_CONFLICT_HARD_REGS (a));
1065 if (can_throw_internal (insn))
1067 IOR_HARD_REG_SET (ALLOCNO_TOTAL_CONFLICT_HARD_REGS (a),
1069 IOR_HARD_REG_SET (ALLOCNO_CONFLICT_HARD_REGS (a),
1075 make_early_clobber_and_input_conflicts ();
1079 /* Mark each used value as live. */
1080 for (use_rec = DF_INSN_USES (insn); *use_rec; use_rec++)
1081 mark_ref_live (*use_rec);
1083 process_single_reg_class_operands (true, freq);
1085 set_p = mark_hard_reg_early_clobbers (insn, true);
1089 mark_hard_reg_early_clobbers (insn, false);
1091 /* Mark each hard reg as live again. For example, a
1092 hard register can be in clobber and in an insn
1094 for (use_rec = DF_INSN_USES (insn); *use_rec; use_rec++)
1096 rtx ureg = DF_REF_REG (*use_rec);
1098 if (GET_CODE (ureg) == SUBREG)
1099 ureg = SUBREG_REG (ureg);
1100 if (! REG_P (ureg) || REGNO (ureg) >= FIRST_PSEUDO_REGISTER)
1103 mark_ref_live (*use_rec);
1110 #ifdef EH_RETURN_DATA_REGNO
1111 if (bb_has_eh_pred (bb))
1114 unsigned int regno = EH_RETURN_DATA_REGNO (j);
1115 if (regno == INVALID_REGNUM)
1117 make_regno_born (regno);
1121 /* Allocnos can't go in stack regs at the start of a basic block
1122 that is reached by an abnormal edge. Likewise for call
1123 clobbered regs, because caller-save, fixup_abnormal_edges and
1124 possibly the table driven EH machinery are not quite ready to
1125 handle such allocnos live across such edges. */
1126 if (bb_has_abnormal_pred (bb))
1129 EXECUTE_IF_SET_IN_SPARSESET (allocnos_live, px)
1131 ALLOCNO_NO_STACK_REG_P (ira_allocnos[px]) = true;
1132 ALLOCNO_TOTAL_NO_STACK_REG_P (ira_allocnos[px]) = true;
1134 for (px = FIRST_STACK_REG; px <= LAST_STACK_REG; px++)
1135 make_regno_born (px);
1137 /* No need to record conflicts for call clobbered regs if we
1138 have nonlocal labels around, as we don't ever try to
1139 allocate such regs in this case. */
1140 if (!cfun->has_nonlocal_label && bb_has_abnormal_call_pred (bb))
1141 for (px = 0; px < FIRST_PSEUDO_REGISTER; px++)
1142 if (call_used_regs[px])
1143 make_regno_born (px);
1146 EXECUTE_IF_SET_IN_SPARSESET (allocnos_live, i)
1148 make_regno_dead (ALLOCNO_REGNO (ira_allocnos[i]));
1154 /* Propagate register pressure to upper loop tree nodes: */
1155 if (loop_tree_node != ira_loop_tree_root)
1156 for (i = 0; i < ira_reg_class_cover_size; i++)
1158 enum reg_class cover_class;
1160 cover_class = ira_reg_class_cover[i];
1161 if (loop_tree_node->reg_pressure[cover_class]
1162 > loop_tree_node->parent->reg_pressure[cover_class])
1163 loop_tree_node->parent->reg_pressure[cover_class]
1164 = loop_tree_node->reg_pressure[cover_class];
1168 /* Create and set up IRA_START_POINT_RANGES and
1169 IRA_FINISH_POINT_RANGES. */
1171 create_start_finish_chains (void)
1174 ira_allocno_iterator ai;
1175 allocno_live_range_t r;
1177 ira_start_point_ranges
1178 = (allocno_live_range_t *) ira_allocate (ira_max_point
1179 * sizeof (allocno_live_range_t));
1180 memset (ira_start_point_ranges, 0,
1181 ira_max_point * sizeof (allocno_live_range_t));
1182 ira_finish_point_ranges
1183 = (allocno_live_range_t *) ira_allocate (ira_max_point
1184 * sizeof (allocno_live_range_t));
1185 memset (ira_finish_point_ranges, 0,
1186 ira_max_point * sizeof (allocno_live_range_t));
1187 FOR_EACH_ALLOCNO (a, ai)
1189 for (r = ALLOCNO_LIVE_RANGES (a); r != NULL; r = r->next)
1191 r->start_next = ira_start_point_ranges[r->start];
1192 ira_start_point_ranges[r->start] = r;
1193 r->finish_next = ira_finish_point_ranges[r->finish];
1194 ira_finish_point_ranges[r->finish] = r;
1199 /* Rebuild IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES after
1200 new live ranges and program points were added as a result if new
1203 ira_rebuild_start_finish_chains (void)
1205 ira_free (ira_finish_point_ranges);
1206 ira_free (ira_start_point_ranges);
1207 create_start_finish_chains ();
1210 /* Compress allocno live ranges by removing program points where
1213 remove_some_program_points_and_update_live_ranges (void)
1219 ira_allocno_iterator ai;
1220 allocno_live_range_t r;
1221 bitmap born_or_died;
1224 born_or_died = ira_allocate_bitmap ();
1225 FOR_EACH_ALLOCNO (a, ai)
1227 for (r = ALLOCNO_LIVE_RANGES (a); r != NULL; r = r->next)
1229 ira_assert (r->start <= r->finish);
1230 bitmap_set_bit (born_or_died, r->start);
1231 bitmap_set_bit (born_or_died, r->finish);
1234 map = (int *) ira_allocate (sizeof (int) * ira_max_point);
1236 EXECUTE_IF_SET_IN_BITMAP(born_or_died, 0, i, bi)
1240 ira_free_bitmap (born_or_died);
1241 if (internal_flag_ira_verbose > 1 && ira_dump_file != NULL)
1242 fprintf (ira_dump_file, "Compressing live ranges: from %d to %d - %d%%\n",
1243 ira_max_point, n, 100 * n / ira_max_point);
1245 FOR_EACH_ALLOCNO (a, ai)
1247 for (r = ALLOCNO_LIVE_RANGES (a); r != NULL; r = r->next)
1249 r->start = map[r->start];
1250 r->finish = map[r->finish];
1256 /* Print live ranges R to file F. */
1258 ira_print_live_range_list (FILE *f, allocno_live_range_t r)
1260 for (; r != NULL; r = r->next)
1261 fprintf (f, " [%d..%d]", r->start, r->finish);
1265 /* Print live ranges R to stderr. */
1267 ira_debug_live_range_list (allocno_live_range_t r)
1269 ira_print_live_range_list (stderr, r);
1272 /* Print live ranges of allocno A to file F. */
1274 print_allocno_live_ranges (FILE *f, ira_allocno_t a)
1276 fprintf (f, " a%d(r%d):", ALLOCNO_NUM (a), ALLOCNO_REGNO (a));
1277 ira_print_live_range_list (f, ALLOCNO_LIVE_RANGES (a));
1280 /* Print live ranges of allocno A to stderr. */
1282 ira_debug_allocno_live_ranges (ira_allocno_t a)
1284 print_allocno_live_ranges (stderr, a);
1287 /* Print live ranges of all allocnos to file F. */
1289 print_live_ranges (FILE *f)
1292 ira_allocno_iterator ai;
1294 FOR_EACH_ALLOCNO (a, ai)
1295 print_allocno_live_ranges (f, a);
1298 /* Print live ranges of all allocnos to stderr. */
1300 ira_debug_live_ranges (void)
1302 print_live_ranges (stderr);
1305 /* The main entry function creates live ranges, set up
1306 CONFLICT_HARD_REGS and TOTAL_CONFLICT_HARD_REGS for allocnos, and
1307 calculate register pressure info. */
1309 ira_create_allocno_live_ranges (void)
1311 allocnos_live = sparseset_alloc (ira_allocnos_num);
1314 allocno_saved_at_call
1315 = (int *) ira_allocate (ira_allocnos_num * sizeof (int));
1316 memset (allocno_saved_at_call, 0, ira_allocnos_num * sizeof (int));
1317 ira_traverse_loop_tree (true, ira_loop_tree_root, NULL,
1318 process_bb_node_lives);
1319 ira_max_point = curr_point;
1320 create_start_finish_chains ();
1321 if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL)
1322 print_live_ranges (ira_dump_file);
1324 ira_free (allocno_saved_at_call);
1325 sparseset_free (allocnos_live);
1328 /* Compress allocno live ranges. */
1330 ira_compress_allocno_live_ranges (void)
1332 remove_some_program_points_and_update_live_ranges ();
1333 ira_rebuild_start_finish_chains ();
1334 if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL)
1336 fprintf (ira_dump_file, "Ranges after the compression:\n");
1337 print_live_ranges (ira_dump_file);
1341 /* Free arrays IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES. */
1343 ira_finish_allocno_live_ranges (void)
1345 ira_free (ira_finish_point_ranges);
1346 ira_free (ira_start_point_ranges);