1 /* IRA hard register and memory cost calculation for allocnos or pseudos.
2 Copyright (C) 2006, 2007, 2008, 2009
3 Free Software Foundation, Inc.
4 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
26 #include "hard-reg-set.h"
31 #include "basic-block.h"
33 #include "addresses.h"
34 #include "insn-config.h"
37 #include "diagnostic-core.h"
43 /* The flags is set up every time when we calculate pseudo register
44 classes through function ira_set_pseudo_classes. */
45 static bool pseudo_classes_defined_p = false;
47 /* TRUE if we work with allocnos. Otherwise we work with pseudos. */
48 static bool allocno_p;
50 /* Number of elements in arrays `in_inc_dec' and `costs'. */
51 static int cost_elements_num;
53 #ifdef FORBIDDEN_INC_DEC_CLASSES
54 /* Indexed by n, is TRUE if allocno or pseudo with number N is used in
55 an auto-inc or auto-dec context. */
56 static bool *in_inc_dec;
59 /* The `costs' struct records the cost of using hard registers of each
60 class considered for the calculation and of using memory for each
65 /* Costs for register classes start here. We process only some
66 register classes (cover classes on the 1st cost calculation
67 iteration and important classes on the 2nd iteration). */
71 /* Initialized once. It is a maximal possible size of the allocated
73 static int max_struct_costs_size;
75 /* Allocated and initialized once, and used to initialize cost values
77 static struct costs *init_cost;
79 /* Allocated once, and used for temporary purposes. */
80 static struct costs *temp_costs;
82 /* Allocated once, and used for the cost calculation. */
83 static struct costs *op_costs[MAX_RECOG_OPERANDS];
84 static struct costs *this_op_costs[MAX_RECOG_OPERANDS];
86 /* Costs of each class for each allocno or pseudo. */
87 static struct costs *costs;
89 /* Accumulated costs of each class for each allocno. */
90 static struct costs *total_allocno_costs;
92 /* Classes used for cost calculation. They may be different on
93 different iterations of the cost calculations or in different
94 optimization modes. */
95 static enum reg_class *cost_classes;
97 /* The size of the previous array. */
98 static int cost_classes_num;
100 /* Map: cost class -> order number (they start with 0) of the cost
101 class. The order number is negative for non-cost classes. */
102 static int cost_class_nums[N_REG_CLASSES];
104 /* It is the current size of struct costs. */
105 static int struct_costs_size;
107 /* Return pointer to structure containing costs of allocno or pseudo
108 with given NUM in array ARR. */
109 #define COSTS(arr, num) \
110 ((struct costs *) ((char *) (arr) + (num) * struct_costs_size))
112 /* Return index in COSTS when processing reg with REGNO. */
113 #define COST_INDEX(regno) (allocno_p \
114 ? ALLOCNO_NUM (ira_curr_regno_allocno_map[regno]) \
117 /* Record register class preferences of each allocno or pseudo. Null
118 value means no preferences. It happens on the 1st iteration of the
120 static enum reg_class *pref;
122 /* Allocated buffers for pref. */
123 static enum reg_class *pref_buffer;
125 /* Record cover register class of each allocno with the same regno. */
126 static enum reg_class *regno_cover_class;
128 /* Record cost gains for not allocating a register with an invariant
130 static int *regno_equiv_gains;
132 /* Execution frequency of the current insn. */
133 static int frequency;
137 /* Compute the cost of loading X into (if TO_P is TRUE) or from (if
138 TO_P is FALSE) a register of class RCLASS in mode MODE. X must not
139 be a pseudo register. */
141 copy_cost (rtx x, enum machine_mode mode, enum reg_class rclass, bool to_p,
142 secondary_reload_info *prev_sri)
144 secondary_reload_info sri;
145 enum reg_class secondary_class = NO_REGS;
147 /* If X is a SCRATCH, there is actually nothing to move since we are
148 assuming optimal allocation. */
149 if (GET_CODE (x) == SCRATCH)
152 /* Get the class we will actually use for a reload. */
153 rclass = PREFERRED_RELOAD_CLASS (x, rclass);
155 /* If we need a secondary reload for an intermediate, the cost is
156 that to load the input into the intermediate register, then to
158 sri.prev_sri = prev_sri;
161 = (enum reg_class) targetm.secondary_reload (to_p, x, rclass, mode, &sri);
163 if (secondary_class != NO_REGS)
165 if (!move_cost[mode])
166 init_move_cost (mode);
167 return (move_cost[mode][secondary_class][rclass] + sri.extra_cost
168 + copy_cost (x, mode, secondary_class, to_p, &sri));
171 /* For memory, use the memory move cost, for (hard) registers, use
172 the cost to move between the register classes, and use 2 for
173 everything else (constants). */
174 if (MEM_P (x) || rclass == NO_REGS)
175 return sri.extra_cost + ira_memory_move_cost[mode][rclass][to_p != 0];
178 if (!move_cost[mode])
179 init_move_cost (mode);
180 return (sri.extra_cost + move_cost[mode][REGNO_REG_CLASS (REGNO (x))][rclass]);
183 /* If this is a constant, we may eventually want to call rtx_cost
185 return sri.extra_cost + COSTS_N_INSNS (1);
190 /* Record the cost of using memory or hard registers of various
191 classes for the operands in INSN.
193 N_ALTS is the number of alternatives.
194 N_OPS is the number of operands.
195 OPS is an array of the operands.
196 MODES are the modes of the operands, in case any are VOIDmode.
197 CONSTRAINTS are the constraints to use for the operands. This array
198 is modified by this procedure.
200 This procedure works alternative by alternative. For each
201 alternative we assume that we will be able to allocate all allocnos
202 to their ideal register class and calculate the cost of using that
203 alternative. Then we compute, for each operand that is a
204 pseudo-register, the cost of having the allocno allocated to each
205 register class and using it in that alternative. To this cost is
206 added the cost of the alternative.
208 The cost of each class for this insn is its lowest cost among all
211 record_reg_classes (int n_alts, int n_ops, rtx *ops,
212 enum machine_mode *modes, const char **constraints,
213 rtx insn, struct costs **op_costs,
214 enum reg_class *pref)
219 int insn_allows_mem[MAX_RECOG_OPERANDS];
221 for (i = 0; i < n_ops; i++)
222 insn_allows_mem[i] = 0;
224 /* Process each alternative, each time minimizing an operand's cost
225 with the cost for each operand in that alternative. */
226 for (alt = 0; alt < n_alts; alt++)
228 enum reg_class classes[MAX_RECOG_OPERANDS];
229 int allows_mem[MAX_RECOG_OPERANDS];
230 enum reg_class rclass;
232 int alt_cost = 0, op_cost_add;
234 if (!recog_data.alternative_enabled_p[alt])
236 for (i = 0; i < recog_data.n_operands; i++)
237 constraints[i] = skip_alternative (constraints[i]);
242 for (i = 0; i < n_ops; i++)
245 const char *p = constraints[i];
247 enum machine_mode mode = modes[i];
251 /* Initially show we know nothing about the register class. */
252 classes[i] = NO_REGS;
255 /* If this operand has no constraints at all, we can
256 conclude nothing about it since anything is valid. */
259 if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER)
260 memset (this_op_costs[i], 0, struct_costs_size);
264 /* If this alternative is only relevant when this operand
265 matches a previous operand, we do different things
266 depending on whether this operand is a allocno-reg or not.
267 We must process any modifiers for the operand before we
268 can make this test. */
269 while (*p == '%' || *p == '=' || *p == '+' || *p == '&')
272 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0))
274 /* Copy class and whether memory is allowed from the
275 matching alternative. Then perform any needed cost
276 computations and/or adjustments. */
278 classes[i] = classes[j];
279 allows_mem[i] = allows_mem[j];
281 insn_allows_mem[i] = 1;
283 if (! REG_P (op) || REGNO (op) < FIRST_PSEUDO_REGISTER)
285 /* If this matches the other operand, we have no
286 added cost and we win. */
287 if (rtx_equal_p (ops[j], op))
289 /* If we can put the other operand into a register,
290 add to the cost of this alternative the cost to
291 copy this operand to the register used for the
293 else if (classes[j] != NO_REGS)
295 alt_cost += copy_cost (op, mode, classes[j], 1, NULL);
299 else if (! REG_P (ops[j])
300 || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER)
302 /* This op is an allocno but the one it matches is
305 /* If we can't put the other operand into a
306 register, this alternative can't be used. */
308 if (classes[j] == NO_REGS)
310 /* Otherwise, add to the cost of this alternative
311 the cost to copy the other operand to the hard
312 register used for this operand. */
314 alt_cost += copy_cost (ops[j], mode, classes[j], 1, NULL);
318 /* The costs of this operand are not the same as the
319 other operand since move costs are not symmetric.
320 Moreover, if we cannot tie them, this alternative
321 needs to do a copy, which is one insn. */
322 struct costs *pp = this_op_costs[i];
324 for (k = 0; k < cost_classes_num; k++)
326 rclass = cost_classes[k];
328 = (((recog_data.operand_type[i] != OP_OUT
329 ? ira_get_may_move_cost (mode, rclass,
330 classes[i], true) : 0)
331 + (recog_data.operand_type[i] != OP_IN
332 ? ira_get_may_move_cost (mode, classes[i],
337 /* If the alternative actually allows memory, make
338 things a bit cheaper since we won't need an extra
341 = ((recog_data.operand_type[i] != OP_IN
342 ? ira_memory_move_cost[mode][classes[i]][0] : 0)
343 + (recog_data.operand_type[i] != OP_OUT
344 ? ira_memory_move_cost[mode][classes[i]][1] : 0)
345 - allows_mem[i]) * frequency;
347 /* If we have assigned a class to this allocno in our
348 first pass, add a cost to this alternative
349 corresponding to what we would add if this allocno
350 were not in the appropriate class. We could use
351 cover class here but it is less accurate
355 enum reg_class pref_class = pref[COST_INDEX (REGNO (op))];
357 if (pref_class == NO_REGS)
359 += ((recog_data.operand_type[i] != OP_IN
360 ? ira_memory_move_cost[mode][classes[i]][0]
362 + (recog_data.operand_type[i] != OP_OUT
363 ? ira_memory_move_cost[mode][classes[i]][1]
365 else if (ira_reg_class_intersect
366 [pref_class][classes[i]] == NO_REGS)
367 alt_cost += ira_get_register_move_cost (mode,
371 if (REGNO (ops[i]) != REGNO (ops[j])
372 && ! find_reg_note (insn, REG_DEAD, op))
375 /* This is in place of ordinary cost computation for
376 this operand, so skip to the end of the
377 alternative (should be just one character). */
378 while (*p && *p++ != ',')
386 /* Scan all the constraint letters. See if the operand
387 matches any of the constraints. Collect the valid
388 register classes and see if this operand accepts
397 /* Ignore the next letter for this pass. */
403 case '!': case '#': case '&':
404 case '0': case '1': case '2': case '3': case '4':
405 case '5': case '6': case '7': case '8': case '9':
410 win = address_operand (op, GET_MODE (op));
411 /* We know this operand is an address, so we want it
412 to be allocated to a register that can be the
413 base of an address, i.e. BASE_REG_CLASS. */
415 = ira_reg_class_union[classes[i]]
416 [base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
419 case 'm': case 'o': case 'V':
420 /* It doesn't seem worth distinguishing between
421 offsettable and non-offsettable addresses
423 insn_allows_mem[i] = allows_mem[i] = 1;
430 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
431 || GET_CODE (XEXP (op, 0)) == POST_DEC))
437 && (GET_CODE (XEXP (op, 0)) == PRE_INC
438 || GET_CODE (XEXP (op, 0)) == POST_INC))
444 if (GET_CODE (op) == CONST_DOUBLE
445 || (GET_CODE (op) == CONST_VECTOR
446 && (GET_MODE_CLASS (GET_MODE (op))
447 == MODE_VECTOR_FLOAT)))
453 if (GET_CODE (op) == CONST_DOUBLE
454 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, c, p))
460 || (GET_CODE (op) == CONST_DOUBLE
461 && GET_MODE (op) == VOIDmode))
466 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)))
472 || (GET_CODE (op) == CONST_DOUBLE
473 && GET_MODE (op) == VOIDmode))
486 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), c, p))
497 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))))
499 insn_allows_mem[i] = allows_mem[i] = 1;
501 classes[i] = ira_reg_class_union[classes[i]][GENERAL_REGS];
505 if (REG_CLASS_FROM_CONSTRAINT (c, p) != NO_REGS)
506 classes[i] = ira_reg_class_union[classes[i]]
507 [REG_CLASS_FROM_CONSTRAINT (c, p)];
508 #ifdef EXTRA_CONSTRAINT_STR
509 else if (EXTRA_CONSTRAINT_STR (op, c, p))
512 if (EXTRA_MEMORY_CONSTRAINT (c, p))
514 /* Every MEM can be reloaded to fit. */
515 insn_allows_mem[i] = allows_mem[i] = 1;
519 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
521 /* Every address can be reloaded to fit. */
523 if (address_operand (op, GET_MODE (op)))
525 /* We know this operand is an address, so we
526 want it to be allocated to a hard register
527 that can be the base of an address,
528 i.e. BASE_REG_CLASS. */
530 = ira_reg_class_union[classes[i]]
531 [base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
536 p += CONSTRAINT_LEN (c, p);
543 /* How we account for this operand now depends on whether it
544 is a pseudo register or not. If it is, we first check if
545 any register classes are valid. If not, we ignore this
546 alternative, since we want to assume that all allocnos get
547 allocated for register preferencing. If some register
548 class is valid, compute the costs of moving the allocno
550 if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER)
552 if (classes[i] == NO_REGS)
554 /* We must always fail if the operand is a REG, but
555 we did not find a suitable class.
557 Otherwise we may perform an uninitialized read
558 from this_op_costs after the `continue' statement
564 struct costs *pp = this_op_costs[i];
566 for (k = 0; k < cost_classes_num; k++)
568 rclass = cost_classes[k];
570 = (((recog_data.operand_type[i] != OP_OUT
571 ? ira_get_may_move_cost (mode, rclass,
572 classes[i], true) : 0)
573 + (recog_data.operand_type[i] != OP_IN
574 ? ira_get_may_move_cost (mode, classes[i],
579 /* If the alternative actually allows memory, make
580 things a bit cheaper since we won't need an extra
583 = ((recog_data.operand_type[i] != OP_IN
584 ? ira_memory_move_cost[mode][classes[i]][0] : 0)
585 + (recog_data.operand_type[i] != OP_OUT
586 ? ira_memory_move_cost[mode][classes[i]][1] : 0)
587 - allows_mem[i]) * frequency;
588 /* If we have assigned a class to this allocno in our
589 first pass, add a cost to this alternative
590 corresponding to what we would add if this allocno
591 were not in the appropriate class. We could use
592 cover class here but it is less accurate
596 enum reg_class pref_class = pref[COST_INDEX (REGNO (op))];
598 if (pref_class == NO_REGS)
600 += ((recog_data.operand_type[i] != OP_IN
601 ? ira_memory_move_cost[mode][classes[i]][0]
603 + (recog_data.operand_type[i] != OP_OUT
604 ? ira_memory_move_cost[mode][classes[i]][1]
606 else if (ira_reg_class_intersect[pref_class][classes[i]]
608 alt_cost += ira_get_register_move_cost (mode,
615 /* Otherwise, if this alternative wins, either because we
616 have already determined that or if we have a hard
617 register of the proper class, there is no cost for this
619 else if (win || (REG_P (op)
620 && reg_fits_class_p (op, classes[i],
624 /* If registers are valid, the cost of this alternative
625 includes copying the object to and/or from a
627 else if (classes[i] != NO_REGS)
629 if (recog_data.operand_type[i] != OP_OUT)
630 alt_cost += copy_cost (op, mode, classes[i], 1, NULL);
632 if (recog_data.operand_type[i] != OP_IN)
633 alt_cost += copy_cost (op, mode, classes[i], 0, NULL);
635 /* The only other way this alternative can be used is if
636 this is a constant that could be placed into memory. */
637 else if (CONSTANT_P (op) && (allows_addr || allows_mem[i]))
638 alt_cost += ira_memory_move_cost[mode][classes[i]][1];
646 op_cost_add = alt_cost * frequency;
647 /* Finally, update the costs with the information we've
648 calculated about this alternative. */
649 for (i = 0; i < n_ops; i++)
650 if (REG_P (ops[i]) && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
652 struct costs *pp = op_costs[i], *qq = this_op_costs[i];
653 int scale = 1 + (recog_data.operand_type[i] == OP_INOUT);
655 pp->mem_cost = MIN (pp->mem_cost,
656 (qq->mem_cost + op_cost_add) * scale);
658 for (k = 0; k < cost_classes_num; k++)
660 = MIN (pp->cost[k], (qq->cost[k] + op_cost_add) * scale);
665 for (i = 0; i < n_ops; i++)
670 if (! REG_P (op) || REGNO (op) < FIRST_PSEUDO_REGISTER)
672 a = ira_curr_regno_allocno_map [REGNO (op)];
673 if (! ALLOCNO_BAD_SPILL_P (a) && insn_allows_mem[i] == 0)
674 ALLOCNO_BAD_SPILL_P (a) = true;
677 /* If this insn is a single set copying operand 1 to operand 0 and
678 one operand is an allocno with the other a hard reg or an allocno
679 that prefers a hard register that is in its own register class
680 then we may want to adjust the cost of that register class to -1.
682 Avoid the adjustment if the source does not die to avoid
683 stressing of register allocator by preferrencing two colliding
684 registers into single class.
686 Also avoid the adjustment if a copy between hard registers of the
687 class is expensive (ten times the cost of a default copy is
688 considered arbitrarily expensive). This avoids losing when the
689 preferred class is very expensive as the source of a copy
691 if ((set = single_set (insn)) != 0
692 && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set)
693 && REG_P (ops[0]) && REG_P (ops[1])
694 && find_regno_note (insn, REG_DEAD, REGNO (ops[1])))
695 for (i = 0; i <= 1; i++)
696 if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
698 unsigned int regno = REGNO (ops[!i]);
699 enum machine_mode mode = GET_MODE (ops[!i]);
700 enum reg_class rclass;
703 if (regno < FIRST_PSEUDO_REGISTER)
704 for (k = 0; k < cost_classes_num; k++)
706 rclass = cost_classes[k];
707 if (TEST_HARD_REG_BIT (reg_class_contents[rclass], regno)
708 && (reg_class_size[rclass]
709 == (unsigned) CLASS_MAX_NREGS (rclass, mode)))
711 if (reg_class_size[rclass] == 1)
712 op_costs[i]->cost[k] = -frequency;
716 nr < (unsigned) hard_regno_nregs[regno][mode];
718 if (! TEST_HARD_REG_BIT (reg_class_contents[rclass],
722 if (nr == (unsigned) hard_regno_nregs[regno][mode])
723 op_costs[i]->cost[k] = -frequency;
732 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudo registers. */
734 ok_for_index_p_nonstrict (rtx reg)
736 unsigned regno = REGNO (reg);
738 return regno >= FIRST_PSEUDO_REGISTER || REGNO_OK_FOR_INDEX_P (regno);
741 /* A version of regno_ok_for_base_p for use here, when all
742 pseudo-registers should count as OK. Arguments as for
743 regno_ok_for_base_p. */
745 ok_for_base_p_nonstrict (rtx reg, enum machine_mode mode,
746 enum rtx_code outer_code, enum rtx_code index_code)
748 unsigned regno = REGNO (reg);
750 if (regno >= FIRST_PSEUDO_REGISTER)
752 return ok_for_base_p_1 (regno, mode, outer_code, index_code);
755 /* Record the pseudo registers we must reload into hard registers in a
756 subexpression of a memory address, X.
758 If CONTEXT is 0, we are looking at the base part of an address,
759 otherwise we are looking at the index part.
761 MODE is the mode of the memory reference; OUTER_CODE and INDEX_CODE
762 give the context that the rtx appears in. These three arguments
763 are passed down to base_reg_class.
765 SCALE is twice the amount to multiply the cost by (it is twice so
766 we can represent half-cost adjustments). */
768 record_address_regs (enum machine_mode mode, rtx x, int context,
769 enum rtx_code outer_code, enum rtx_code index_code,
772 enum rtx_code code = GET_CODE (x);
773 enum reg_class rclass;
776 rclass = INDEX_REG_CLASS;
778 rclass = base_reg_class (mode, outer_code, index_code);
791 /* When we have an address that is a sum, we must determine
792 whether registers are "base" or "index" regs. If there is a
793 sum of two registers, we must choose one to be the "base".
794 Luckily, we can use the REG_POINTER to make a good choice
795 most of the time. We only need to do this on machines that
796 can have two registers in an address and where the base and
797 index register classes are different.
799 ??? This code used to set REGNO_POINTER_FLAG in some cases,
800 but that seems bogus since it should only be set when we are
801 sure the register is being used as a pointer. */
803 rtx arg0 = XEXP (x, 0);
804 rtx arg1 = XEXP (x, 1);
805 enum rtx_code code0 = GET_CODE (arg0);
806 enum rtx_code code1 = GET_CODE (arg1);
808 /* Look inside subregs. */
810 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0);
812 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1);
814 /* If this machine only allows one register per address, it
815 must be in the first operand. */
816 if (MAX_REGS_PER_ADDRESS == 1)
817 record_address_regs (mode, arg0, 0, PLUS, code1, scale);
819 /* If index and base registers are the same on this machine,
820 just record registers in any non-constant operands. We
821 assume here, as well as in the tests below, that all
822 addresses are in canonical form. */
823 else if (INDEX_REG_CLASS == base_reg_class (VOIDmode, PLUS, SCRATCH))
825 record_address_regs (mode, arg0, context, PLUS, code1, scale);
826 if (! CONSTANT_P (arg1))
827 record_address_regs (mode, arg1, context, PLUS, code0, scale);
830 /* If the second operand is a constant integer, it doesn't
831 change what class the first operand must be. */
832 else if (code1 == CONST_INT || code1 == CONST_DOUBLE)
833 record_address_regs (mode, arg0, context, PLUS, code1, scale);
834 /* If the second operand is a symbolic constant, the first
835 operand must be an index register. */
836 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF)
837 record_address_regs (mode, arg0, 1, PLUS, code1, scale);
838 /* If both operands are registers but one is already a hard
839 register of index or reg-base class, give the other the
840 class that the hard register is not. */
841 else if (code0 == REG && code1 == REG
842 && REGNO (arg0) < FIRST_PSEUDO_REGISTER
843 && (ok_for_base_p_nonstrict (arg0, mode, PLUS, REG)
844 || ok_for_index_p_nonstrict (arg0)))
845 record_address_regs (mode, arg1,
846 ok_for_base_p_nonstrict (arg0, mode, PLUS, REG)
849 else if (code0 == REG && code1 == REG
850 && REGNO (arg1) < FIRST_PSEUDO_REGISTER
851 && (ok_for_base_p_nonstrict (arg1, mode, PLUS, REG)
852 || ok_for_index_p_nonstrict (arg1)))
853 record_address_regs (mode, arg0,
854 ok_for_base_p_nonstrict (arg1, mode, PLUS, REG)
857 /* If one operand is known to be a pointer, it must be the
858 base with the other operand the index. Likewise if the
859 other operand is a MULT. */
860 else if ((code0 == REG && REG_POINTER (arg0)) || code1 == MULT)
862 record_address_regs (mode, arg0, 0, PLUS, code1, scale);
863 record_address_regs (mode, arg1, 1, PLUS, code0, scale);
865 else if ((code1 == REG && REG_POINTER (arg1)) || code0 == MULT)
867 record_address_regs (mode, arg0, 1, PLUS, code1, scale);
868 record_address_regs (mode, arg1, 0, PLUS, code0, scale);
870 /* Otherwise, count equal chances that each might be a base or
871 index register. This case should be rare. */
874 record_address_regs (mode, arg0, 0, PLUS, code1, scale / 2);
875 record_address_regs (mode, arg0, 1, PLUS, code1, scale / 2);
876 record_address_regs (mode, arg1, 0, PLUS, code0, scale / 2);
877 record_address_regs (mode, arg1, 1, PLUS, code0, scale / 2);
882 /* Double the importance of an allocno that is incremented or
883 decremented, since it would take two extra insns if it ends
884 up in the wrong place. */
887 record_address_regs (mode, XEXP (x, 0), 0, code,
888 GET_CODE (XEXP (XEXP (x, 1), 1)), 2 * scale);
889 if (REG_P (XEXP (XEXP (x, 1), 1)))
890 record_address_regs (mode, XEXP (XEXP (x, 1), 1), 1, code, REG,
898 /* Double the importance of an allocno that is incremented or
899 decremented, since it would take two extra insns if it ends
900 up in the wrong place. If the operand is a pseudo-register,
901 show it is being used in an INC_DEC context. */
902 #ifdef FORBIDDEN_INC_DEC_CLASSES
903 if (REG_P (XEXP (x, 0))
904 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER)
905 in_inc_dec[COST_INDEX (REGNO (XEXP (x, 0)))] = true;
907 record_address_regs (mode, XEXP (x, 0), 0, code, SCRATCH, 2 * scale);
916 if (REGNO (x) < FIRST_PSEUDO_REGISTER)
920 ALLOCNO_BAD_SPILL_P (ira_curr_regno_allocno_map[REGNO (x)]) = true;
921 pp = COSTS (costs, COST_INDEX (REGNO (x)));
922 pp->mem_cost += (ira_memory_move_cost[Pmode][rclass][1] * scale) / 2;
923 for (k = 0; k < cost_classes_num; k++)
927 += (ira_get_may_move_cost (Pmode, i, rclass, true) * scale) / 2;
934 const char *fmt = GET_RTX_FORMAT (code);
936 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
938 record_address_regs (mode, XEXP (x, i), context, code, SCRATCH,
946 /* Calculate the costs of insn operands. */
948 record_operand_costs (rtx insn, struct costs **op_costs, enum reg_class *pref)
950 const char *constraints[MAX_RECOG_OPERANDS];
951 enum machine_mode modes[MAX_RECOG_OPERANDS];
954 for (i = 0; i < recog_data.n_operands; i++)
956 constraints[i] = recog_data.constraints[i];
957 modes[i] = recog_data.operand_mode[i];
960 /* If we get here, we are set up to record the costs of all the
961 operands for this insn. Start by initializing the costs. Then
962 handle any address registers. Finally record the desired classes
963 for any allocnos, doing it twice if some pair of operands are
965 for (i = 0; i < recog_data.n_operands; i++)
967 memcpy (op_costs[i], init_cost, struct_costs_size);
969 if (GET_CODE (recog_data.operand[i]) == SUBREG)
970 recog_data.operand[i] = SUBREG_REG (recog_data.operand[i]);
972 if (MEM_P (recog_data.operand[i]))
973 record_address_regs (GET_MODE (recog_data.operand[i]),
974 XEXP (recog_data.operand[i], 0),
975 0, MEM, SCRATCH, frequency * 2);
976 else if (constraints[i][0] == 'p'
977 || EXTRA_ADDRESS_CONSTRAINT (constraints[i][0],
979 record_address_regs (VOIDmode, recog_data.operand[i], 0, ADDRESS,
980 SCRATCH, frequency * 2);
983 /* Check for commutative in a separate loop so everything will have
984 been initialized. We must do this even if one operand is a
985 constant--see addsi3 in m68k.md. */
986 for (i = 0; i < (int) recog_data.n_operands - 1; i++)
987 if (constraints[i][0] == '%')
989 const char *xconstraints[MAX_RECOG_OPERANDS];
992 /* Handle commutative operands by swapping the constraints.
993 We assume the modes are the same. */
994 for (j = 0; j < recog_data.n_operands; j++)
995 xconstraints[j] = constraints[j];
997 xconstraints[i] = constraints[i+1];
998 xconstraints[i+1] = constraints[i];
999 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
1000 recog_data.operand, modes,
1001 xconstraints, insn, op_costs, pref);
1003 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
1004 recog_data.operand, modes,
1005 constraints, insn, op_costs, pref);
1010 /* Process one insn INSN. Scan it and record each time it would save
1011 code to put a certain allocnos in a certain class. Return the last
1012 insn processed, so that the scan can be continued from there. */
1014 scan_one_insn (rtx insn)
1016 enum rtx_code pat_code;
1020 if (!NONDEBUG_INSN_P (insn))
1023 pat_code = GET_CODE (PATTERN (insn));
1024 if (pat_code == USE || pat_code == CLOBBER || pat_code == ASM_INPUT
1025 || pat_code == ADDR_VEC || pat_code == ADDR_DIFF_VEC)
1028 set = single_set (insn);
1029 extract_insn (insn);
1031 /* If this insn loads a parameter from its stack slot, then it
1032 represents a savings, rather than a cost, if the parameter is
1033 stored in memory. Record this fact. */
1034 if (set != 0 && REG_P (SET_DEST (set)) && MEM_P (SET_SRC (set))
1035 && (note = find_reg_note (insn, REG_EQUIV, NULL_RTX)) != NULL_RTX
1036 && MEM_P (XEXP (note, 0)))
1038 enum reg_class cl = GENERAL_REGS;
1039 rtx reg = SET_DEST (set);
1040 int num = COST_INDEX (REGNO (reg));
1044 COSTS (costs, num)->mem_cost
1045 -= ira_memory_move_cost[GET_MODE (reg)][cl][1] * frequency;
1046 record_address_regs (GET_MODE (SET_SRC (set)), XEXP (SET_SRC (set), 0),
1047 0, MEM, SCRATCH, frequency * 2);
1050 record_operand_costs (insn, op_costs, pref);
1052 /* Now add the cost for each operand to the total costs for its
1054 for (i = 0; i < recog_data.n_operands; i++)
1055 if (REG_P (recog_data.operand[i])
1056 && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER)
1058 int regno = REGNO (recog_data.operand[i]);
1059 struct costs *p = COSTS (costs, COST_INDEX (regno));
1060 struct costs *q = op_costs[i];
1062 p->mem_cost += q->mem_cost;
1063 for (k = 0; k < cost_classes_num; k++)
1064 p->cost[k] += q->cost[k];
1072 /* Print allocnos costs to file F. */
1074 print_allocno_costs (FILE *f)
1078 ira_allocno_iterator ai;
1080 ira_assert (allocno_p);
1082 FOR_EACH_ALLOCNO (a, ai)
1086 int regno = ALLOCNO_REGNO (a);
1088 i = ALLOCNO_NUM (a);
1089 fprintf (f, " a%d(r%d,", i, regno);
1090 if ((bb = ALLOCNO_LOOP_TREE_NODE (a)->bb) != NULL)
1091 fprintf (f, "b%d", bb->index);
1093 fprintf (f, "l%d", ALLOCNO_LOOP_TREE_NODE (a)->loop->num);
1094 fprintf (f, ") costs:");
1095 for (k = 0; k < cost_classes_num; k++)
1097 rclass = cost_classes[k];
1098 if (contains_reg_of_mode[rclass][PSEUDO_REGNO_MODE (regno)]
1099 #ifdef FORBIDDEN_INC_DEC_CLASSES
1100 && (! in_inc_dec[i] || ! forbidden_inc_dec_class[rclass])
1102 #ifdef CANNOT_CHANGE_MODE_CLASS
1103 && ! invalid_mode_change_p (regno, (enum reg_class) rclass,
1104 PSEUDO_REGNO_MODE (regno))
1108 fprintf (f, " %s:%d", reg_class_names[rclass],
1109 COSTS (costs, i)->cost[k]);
1110 if (flag_ira_region == IRA_REGION_ALL
1111 || flag_ira_region == IRA_REGION_MIXED)
1112 fprintf (f, ",%d", COSTS (total_allocno_costs, i)->cost[k]);
1115 fprintf (f, " MEM:%i\n", COSTS (costs, i)->mem_cost);
1119 /* Print pseudo costs to file F. */
1121 print_pseudo_costs (FILE *f)
1126 ira_assert (! allocno_p);
1128 for (regno = max_reg_num () - 1; regno >= FIRST_PSEUDO_REGISTER; regno--)
1130 if (regno_reg_rtx[regno] == NULL_RTX)
1132 fprintf (f, " r%d costs:", regno);
1133 for (k = 0; k < cost_classes_num; k++)
1135 rclass = cost_classes[k];
1136 if (contains_reg_of_mode[rclass][PSEUDO_REGNO_MODE (regno)]
1137 #ifdef FORBIDDEN_INC_DEC_CLASSES
1138 && (! in_inc_dec[regno] || ! forbidden_inc_dec_class[rclass])
1140 #ifdef CANNOT_CHANGE_MODE_CLASS
1141 && ! invalid_mode_change_p (regno, (enum reg_class) rclass,
1142 PSEUDO_REGNO_MODE (regno))
1145 fprintf (f, " %s:%d", reg_class_names[rclass],
1146 COSTS (costs, regno)->cost[k]);
1148 fprintf (f, " MEM:%i\n", COSTS (costs, regno)->mem_cost);
1152 /* Traverse the BB represented by LOOP_TREE_NODE to update the allocno
1155 process_bb_for_costs (basic_block bb)
1159 frequency = REG_FREQ_FROM_BB (bb);
1162 FOR_BB_INSNS (bb, insn)
1163 insn = scan_one_insn (insn);
1166 /* Traverse the BB represented by LOOP_TREE_NODE to update the allocno
1169 process_bb_node_for_costs (ira_loop_tree_node_t loop_tree_node)
1173 bb = loop_tree_node->bb;
1175 process_bb_for_costs (bb);
1178 /* Find costs of register classes and memory for allocnos or pseudos
1179 and their best costs. Set up preferred, alternative and cover
1180 classes for pseudos. */
1182 find_costs_and_classes (FILE *dump_file)
1189 #ifdef FORBIDDEN_INC_DEC_CLASSES
1190 in_inc_dec = ira_allocate (sizeof (bool) * cost_elements_num);
1191 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1194 if (!resize_reg_info () && allocno_p && pseudo_classes_defined_p)
1197 ira_allocno_iterator ai;
1200 FOR_EACH_ALLOCNO (a, ai)
1201 pref[ALLOCNO_NUM (a)] = reg_preferred_class (ALLOCNO_REGNO (a));
1202 if (flag_expensive_optimizations)
1206 /* Clear the flag for the next compiled function. */
1207 pseudo_classes_defined_p = false;
1208 /* Normally we scan the insns once and determine the best class to
1209 use for each allocno. However, if -fexpensive-optimizations are
1210 on, we do so twice, the second time using the tentative best
1211 classes to guide the selection. */
1212 for (pass = start; pass <= flag_expensive_optimizations; pass++)
1214 if ((!allocno_p || internal_flag_ira_verbose > 0) && dump_file)
1216 "\nPass %i for finding pseudo/allocno costs\n\n", pass);
1217 /* We could use only cover classes. Unfortunately it does not
1218 work well for some targets where some subclass of cover class
1219 is costly and wrong cover class is chosen. */
1220 for (i = 0; i < N_REG_CLASSES; i++)
1221 cost_class_nums[i] = -1;
1222 for (cost_classes_num = 0;
1223 cost_classes_num < ira_important_classes_num;
1226 cost_classes[cost_classes_num]
1227 = ira_important_classes[cost_classes_num];
1228 cost_class_nums[cost_classes[cost_classes_num]]
1232 = sizeof (struct costs) + sizeof (int) * (cost_classes_num - 1);
1233 /* Zero out our accumulation of the cost of each class for each
1235 memset (costs, 0, cost_elements_num * struct_costs_size);
1236 #ifdef FORBIDDEN_INC_DEC_CLASSES
1237 memset (in_inc_dec, 0, cost_elements_num * sizeof (bool));
1242 /* Scan the instructions and record each time it would save code
1243 to put a certain allocno in a certain class. */
1244 ira_traverse_loop_tree (true, ira_loop_tree_root,
1245 process_bb_node_for_costs, NULL);
1247 memcpy (total_allocno_costs, costs,
1248 max_struct_costs_size * ira_allocnos_num);
1255 process_bb_for_costs (bb);
1261 /* Now for each allocno look at how desirable each class is and
1262 find which class is preferred. */
1263 for (i = max_reg_num () - 1; i >= FIRST_PSEUDO_REGISTER; i--)
1265 ira_allocno_t a, parent_a;
1266 int rclass, a_num, parent_a_num;
1267 ira_loop_tree_node_t parent;
1268 int best_cost, allocno_cost;
1269 enum reg_class best, alt_class;
1270 #ifdef FORBIDDEN_INC_DEC_CLASSES
1271 int inc_dec_p = false;
1273 int equiv_savings = regno_equiv_gains[i];
1277 if (regno_reg_rtx[i] == NULL_RTX)
1279 #ifdef FORBIDDEN_INC_DEC_CLASSES
1280 inc_dec_p = in_inc_dec[i];
1282 memcpy (temp_costs, COSTS (costs, i), struct_costs_size);
1286 if (ira_regno_allocno_map[i] == NULL)
1288 memset (temp_costs, 0, struct_costs_size);
1289 /* Find cost of all allocnos with the same regno. */
1290 for (a = ira_regno_allocno_map[i];
1292 a = ALLOCNO_NEXT_REGNO_ALLOCNO (a))
1294 a_num = ALLOCNO_NUM (a);
1295 if ((flag_ira_region == IRA_REGION_ALL
1296 || flag_ira_region == IRA_REGION_MIXED)
1297 && (parent = ALLOCNO_LOOP_TREE_NODE (a)->parent) != NULL
1298 && (parent_a = parent->regno_allocno_map[i]) != NULL
1299 /* There are no caps yet. */
1300 && bitmap_bit_p (ALLOCNO_LOOP_TREE_NODE
1301 (a)->border_allocnos,
1304 /* Propagate costs to upper levels in the region
1306 parent_a_num = ALLOCNO_NUM (parent_a);
1307 for (k = 0; k < cost_classes_num; k++)
1308 COSTS (total_allocno_costs, parent_a_num)->cost[k]
1309 += COSTS (total_allocno_costs, a_num)->cost[k];
1310 COSTS (total_allocno_costs, parent_a_num)->mem_cost
1311 += COSTS (total_allocno_costs, a_num)->mem_cost;
1313 for (k = 0; k < cost_classes_num; k++)
1314 temp_costs->cost[k] += COSTS (costs, a_num)->cost[k];
1315 temp_costs->mem_cost += COSTS (costs, a_num)->mem_cost;
1316 #ifdef FORBIDDEN_INC_DEC_CLASSES
1317 if (in_inc_dec[a_num])
1322 if (equiv_savings < 0)
1323 temp_costs->mem_cost = -equiv_savings;
1324 else if (equiv_savings > 0)
1326 temp_costs->mem_cost = 0;
1327 for (k = 0; k < cost_classes_num; k++)
1328 temp_costs->cost[k] += equiv_savings;
1331 best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
1333 alt_class = NO_REGS;
1334 /* Find best common class for all allocnos with the same
1336 for (k = 0; k < cost_classes_num; k++)
1338 rclass = cost_classes[k];
1339 /* Ignore classes that are too small for this operand or
1340 invalid for an operand that was auto-incremented. */
1341 if (! contains_reg_of_mode[rclass][PSEUDO_REGNO_MODE (i)]
1342 #ifdef FORBIDDEN_INC_DEC_CLASSES
1343 || (inc_dec_p && forbidden_inc_dec_class[rclass])
1345 #ifdef CANNOT_CHANGE_MODE_CLASS
1346 || invalid_mode_change_p (i, (enum reg_class) rclass,
1347 PSEUDO_REGNO_MODE (i))
1351 if (temp_costs->cost[k] < best_cost)
1353 best_cost = temp_costs->cost[k];
1354 best = (enum reg_class) rclass;
1356 else if (temp_costs->cost[k] == best_cost)
1357 best = ira_reg_class_union[best][rclass];
1358 if (pass == flag_expensive_optimizations
1359 && temp_costs->cost[k] < temp_costs->mem_cost
1360 && (reg_class_size[reg_class_subunion[alt_class][rclass]]
1361 > reg_class_size[alt_class]))
1362 alt_class = reg_class_subunion[alt_class][rclass];
1364 alt_class = ira_class_translate[alt_class];
1365 if (best_cost > temp_costs->mem_cost)
1366 regno_cover_class[i] = NO_REGS;
1367 else if (flag_ira_algorithm == IRA_ALGORITHM_PRIORITY)
1368 /* Make the common class the biggest class of best and
1370 regno_cover_class[i] = alt_class == NO_REGS ? best : alt_class;
1372 /* Make the common class a cover class. Remember all
1373 allocnos with the same regno should have the same cover
1375 regno_cover_class[i] = ira_class_translate[best];
1376 if (pass == flag_expensive_optimizations)
1378 if (best_cost > temp_costs->mem_cost)
1379 best = alt_class = NO_REGS;
1380 else if (best == alt_class)
1381 alt_class = NO_REGS;
1382 setup_reg_classes (i, best, alt_class, regno_cover_class[i]);
1383 if ((!allocno_p || internal_flag_ira_verbose > 2)
1384 && dump_file != NULL)
1386 " r%d: preferred %s, alternative %s, cover %s\n",
1387 i, reg_class_names[best], reg_class_names[alt_class],
1388 reg_class_names[regno_cover_class[i]]);
1392 pref[i] = best_cost > temp_costs->mem_cost ? NO_REGS : best;
1395 for (a = ira_regno_allocno_map[i];
1397 a = ALLOCNO_NEXT_REGNO_ALLOCNO (a))
1399 a_num = ALLOCNO_NUM (a);
1400 if (regno_cover_class[i] == NO_REGS)
1404 /* Finding best class which is subset of the common
1406 best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
1407 allocno_cost = best_cost;
1409 for (k = 0; k < cost_classes_num; k++)
1411 rclass = cost_classes[k];
1412 if (! ira_class_subset_p[rclass][regno_cover_class[i]])
1414 /* Ignore classes that are too small for this
1415 operand or invalid for an operand that was
1416 auto-incremented. */
1417 if (! contains_reg_of_mode[rclass][PSEUDO_REGNO_MODE (i)]
1418 #ifdef FORBIDDEN_INC_DEC_CLASSES
1419 || (inc_dec_p && forbidden_inc_dec_class[rclass])
1421 #ifdef CANNOT_CHANGE_MODE_CLASS
1422 || invalid_mode_change_p (i, (enum reg_class) rclass,
1423 PSEUDO_REGNO_MODE (i))
1427 else if (COSTS (total_allocno_costs, a_num)->cost[k]
1431 = COSTS (total_allocno_costs, a_num)->cost[k];
1432 allocno_cost = COSTS (costs, a_num)->cost[k];
1433 best = (enum reg_class) rclass;
1435 else if (COSTS (total_allocno_costs, a_num)->cost[k]
1438 best = ira_reg_class_union[best][rclass];
1440 = MAX (allocno_cost, COSTS (costs, a_num)->cost[k]);
1443 ALLOCNO_COVER_CLASS_COST (a) = allocno_cost;
1445 ira_assert (flag_ira_algorithm == IRA_ALGORITHM_PRIORITY
1446 || ira_class_translate[best] == regno_cover_class[i]);
1447 if (internal_flag_ira_verbose > 2 && dump_file != NULL
1448 && (pass == 0 || pref[a_num] != best))
1450 fprintf (dump_file, " a%d (r%d,", a_num, i);
1451 if ((bb = ALLOCNO_LOOP_TREE_NODE (a)->bb) != NULL)
1452 fprintf (dump_file, "b%d", bb->index);
1454 fprintf (dump_file, "l%d",
1455 ALLOCNO_LOOP_TREE_NODE (a)->loop->num);
1456 fprintf (dump_file, ") best %s, cover %s\n",
1457 reg_class_names[best],
1458 reg_class_names[regno_cover_class[i]]);
1464 if (internal_flag_ira_verbose > 4 && dump_file)
1467 print_allocno_costs (dump_file);
1469 print_pseudo_costs (dump_file);
1470 fprintf (dump_file,"\n");
1473 #ifdef FORBIDDEN_INC_DEC_CLASSES
1474 ira_free (in_inc_dec);
1480 /* Process moves involving hard regs to modify allocno hard register
1481 costs. We can do this only after determining allocno cover class.
1482 If a hard register forms a register class, than moves with the hard
1483 register are already taken into account in class costs for the
1486 process_bb_node_for_hard_reg_moves (ira_loop_tree_node_t loop_tree_node)
1488 int i, freq, cost, src_regno, dst_regno, hard_regno;
1491 enum reg_class rclass, hard_reg_class;
1492 enum machine_mode mode;
1494 rtx insn, set, src, dst;
1496 bb = loop_tree_node->bb;
1499 freq = REG_FREQ_FROM_BB (bb);
1502 FOR_BB_INSNS (bb, insn)
1504 if (!NONDEBUG_INSN_P (insn))
1506 set = single_set (insn);
1507 if (set == NULL_RTX)
1509 dst = SET_DEST (set);
1510 src = SET_SRC (set);
1511 if (! REG_P (dst) || ! REG_P (src))
1513 dst_regno = REGNO (dst);
1514 src_regno = REGNO (src);
1515 if (dst_regno >= FIRST_PSEUDO_REGISTER
1516 && src_regno < FIRST_PSEUDO_REGISTER)
1518 hard_regno = src_regno;
1520 a = ira_curr_regno_allocno_map[dst_regno];
1522 else if (src_regno >= FIRST_PSEUDO_REGISTER
1523 && dst_regno < FIRST_PSEUDO_REGISTER)
1525 hard_regno = dst_regno;
1527 a = ira_curr_regno_allocno_map[src_regno];
1531 rclass = ALLOCNO_COVER_CLASS (a);
1532 if (! TEST_HARD_REG_BIT (reg_class_contents[rclass], hard_regno))
1534 i = ira_class_hard_reg_index[rclass][hard_regno];
1537 mode = ALLOCNO_MODE (a);
1538 hard_reg_class = REGNO_REG_CLASS (hard_regno);
1540 = (to_p ? ira_get_register_move_cost (mode, hard_reg_class, rclass)
1541 : ira_get_register_move_cost (mode, rclass, hard_reg_class)) * freq;
1542 ira_allocate_and_set_costs (&ALLOCNO_HARD_REG_COSTS (a), rclass,
1543 ALLOCNO_COVER_CLASS_COST (a));
1544 ira_allocate_and_set_costs (&ALLOCNO_CONFLICT_HARD_REG_COSTS (a),
1546 ALLOCNO_HARD_REG_COSTS (a)[i] -= cost;
1547 ALLOCNO_CONFLICT_HARD_REG_COSTS (a)[i] -= cost;
1548 ALLOCNO_COVER_CLASS_COST (a) = MIN (ALLOCNO_COVER_CLASS_COST (a),
1549 ALLOCNO_HARD_REG_COSTS (a)[i]);
1553 /* After we find hard register and memory costs for allocnos, define
1554 its cover class and modify hard register cost because insns moving
1555 allocno to/from hard registers. */
1557 setup_allocno_cover_class_and_costs (void)
1559 int i, j, n, regno, num;
1561 enum reg_class cover_class, rclass;
1563 ira_allocno_iterator ai;
1565 ira_assert (allocno_p);
1566 FOR_EACH_ALLOCNO (a, ai)
1568 i = ALLOCNO_NUM (a);
1569 cover_class = regno_cover_class[ALLOCNO_REGNO (a)];
1570 ira_assert (pref[i] == NO_REGS || cover_class != NO_REGS);
1571 ALLOCNO_MEMORY_COST (a) = COSTS (costs, i)->mem_cost;
1572 ira_set_allocno_cover_class (a, cover_class);
1573 if (cover_class == NO_REGS)
1575 ALLOCNO_AVAILABLE_REGS_NUM (a) = ira_available_class_regs[cover_class];
1576 if (optimize && ALLOCNO_COVER_CLASS (a) != pref[i])
1578 n = ira_class_hard_regs_num[cover_class];
1579 ALLOCNO_HARD_REG_COSTS (a)
1580 = reg_costs = ira_allocate_cost_vector (cover_class);
1581 for (j = n - 1; j >= 0; j--)
1583 regno = ira_class_hard_regs[cover_class][j];
1584 if (TEST_HARD_REG_BIT (reg_class_contents[pref[i]], regno))
1585 reg_costs[j] = ALLOCNO_COVER_CLASS_COST (a);
1588 rclass = REGNO_REG_CLASS (regno);
1589 num = cost_class_nums[rclass];
1592 /* The hard register class is not a cover class or a
1593 class not fully inside in a cover class -- use
1594 the allocno cover class. */
1595 ira_assert (ira_hard_regno_cover_class[regno]
1597 num = cost_class_nums[cover_class];
1599 reg_costs[j] = COSTS (costs, i)->cost[num];
1605 ira_traverse_loop_tree (true, ira_loop_tree_root,
1606 process_bb_node_for_hard_reg_moves, NULL);
1611 /* Function called once during compiler work. */
1613 ira_init_costs_once (void)
1618 for (i = 0; i < MAX_RECOG_OPERANDS; i++)
1621 this_op_costs[i] = NULL;
1624 cost_classes = NULL;
1627 /* Free allocated temporary cost vectors. */
1629 free_ira_costs (void)
1633 if (init_cost != NULL)
1636 for (i = 0; i < MAX_RECOG_OPERANDS; i++)
1638 if (op_costs[i] != NULL)
1640 if (this_op_costs[i] != NULL)
1641 free (this_op_costs[i]);
1642 op_costs[i] = this_op_costs[i] = NULL;
1644 if (temp_costs != NULL)
1647 if (cost_classes != NULL)
1648 free (cost_classes);
1649 cost_classes = NULL;
1652 /* This is called each time register related information is
1655 ira_init_costs (void)
1660 max_struct_costs_size
1661 = sizeof (struct costs) + sizeof (int) * (ira_important_classes_num - 1);
1662 /* Don't use ira_allocate because vectors live through several IRA calls. */
1663 init_cost = (struct costs *) xmalloc (max_struct_costs_size);
1664 init_cost->mem_cost = 1000000;
1665 for (i = 0; i < ira_important_classes_num; i++)
1666 init_cost->cost[i] = 1000000;
1667 for (i = 0; i < MAX_RECOG_OPERANDS; i++)
1669 op_costs[i] = (struct costs *) xmalloc (max_struct_costs_size);
1670 this_op_costs[i] = (struct costs *) xmalloc (max_struct_costs_size);
1672 temp_costs = (struct costs *) xmalloc (max_struct_costs_size);
1673 cost_classes = (enum reg_class *) xmalloc (sizeof (enum reg_class)
1674 * ira_important_classes_num);
1677 /* Function called once at the end of compiler work. */
1679 ira_finish_costs_once (void)
1686 /* Common initialization function for ira_costs and
1687 ira_set_pseudo_classes. */
1691 init_subregs_of_mode ();
1692 costs = (struct costs *) ira_allocate (max_struct_costs_size
1693 * cost_elements_num);
1695 = (enum reg_class *) ira_allocate (sizeof (enum reg_class)
1696 * cost_elements_num);
1698 = (enum reg_class *) ira_allocate (sizeof (enum reg_class)
1700 regno_equiv_gains = (int *) ira_allocate (sizeof (int) * max_reg_num ());
1701 memset (regno_equiv_gains, 0, sizeof (int) * max_reg_num ());
1704 /* Common finalization function for ira_costs and
1705 ira_set_pseudo_classes. */
1709 ira_free (regno_equiv_gains);
1710 ira_free (regno_cover_class);
1711 ira_free (pref_buffer);
1715 /* Entry function which defines cover class, memory and hard register
1716 costs for each allocno. */
1721 cost_elements_num = ira_allocnos_num;
1723 total_allocno_costs = (struct costs *) ira_allocate (max_struct_costs_size
1724 * ira_allocnos_num);
1725 calculate_elim_costs_all_insns ();
1726 find_costs_and_classes (ira_dump_file);
1727 setup_allocno_cover_class_and_costs ();
1729 ira_free (total_allocno_costs);
1732 /* Entry function which defines classes for pseudos. */
1734 ira_set_pseudo_classes (FILE *dump_file)
1737 internal_flag_ira_verbose = flag_ira_verbose;
1738 cost_elements_num = max_reg_num ();
1740 find_costs_and_classes (dump_file);
1741 pseudo_classes_defined_p = true;
1747 /* Change hard register costs for allocnos which lives through
1748 function calls. This is called only when we found all intersected
1749 calls during building allocno live ranges. */
1751 ira_tune_allocno_costs_and_cover_classes (void)
1754 int cost, min_cost, *reg_costs;
1755 enum reg_class cover_class, rclass;
1756 enum machine_mode mode;
1758 ira_allocno_iterator ai;
1760 FOR_EACH_ALLOCNO (a, ai)
1762 cover_class = ALLOCNO_COVER_CLASS (a);
1763 if (cover_class == NO_REGS)
1765 mode = ALLOCNO_MODE (a);
1766 n = ira_class_hard_regs_num[cover_class];
1768 if (ALLOCNO_CALLS_CROSSED_NUM (a) != 0)
1770 ira_allocate_and_set_costs
1771 (&ALLOCNO_HARD_REG_COSTS (a), cover_class,
1772 ALLOCNO_COVER_CLASS_COST (a));
1773 reg_costs = ALLOCNO_HARD_REG_COSTS (a);
1774 for (j = n - 1; j >= 0; j--)
1776 regno = ira_class_hard_regs[cover_class][j];
1777 rclass = REGNO_REG_CLASS (regno);
1779 if (! ira_hard_reg_not_in_set_p (regno, mode, call_used_reg_set)
1780 || HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))
1781 cost += (ALLOCNO_CALL_FREQ (a)
1782 * (ira_memory_move_cost[mode][rclass][0]
1783 + ira_memory_move_cost[mode][rclass][1]));
1784 #ifdef IRA_HARD_REGNO_ADD_COST_MULTIPLIER
1785 cost += ((ira_memory_move_cost[mode][rclass][0]
1786 + ira_memory_move_cost[mode][rclass][1])
1788 * IRA_HARD_REGNO_ADD_COST_MULTIPLIER (regno) / 2);
1790 reg_costs[j] += cost;
1791 if (min_cost > reg_costs[j])
1792 min_cost = reg_costs[j];
1795 if (min_cost != INT_MAX)
1796 ALLOCNO_COVER_CLASS_COST (a) = min_cost;
1798 /* Some targets allow pseudos to be allocated to unaligned
1799 sequences of hard registers. However, selecting an unaligned
1800 sequence can unnecessarily restrict later allocations. So
1801 increase the cost of unaligned hard regs to encourage the use
1802 of aligned hard regs. */
1806 if ((nregs = ira_reg_class_nregs[cover_class][ALLOCNO_MODE (a)]) > 1)
1808 ira_allocate_and_set_costs
1809 (&ALLOCNO_HARD_REG_COSTS (a), cover_class,
1810 ALLOCNO_COVER_CLASS_COST (a));
1811 reg_costs = ALLOCNO_HARD_REG_COSTS (a);
1812 for (j = n - 1; j >= 0; j--)
1816 regno = ira_non_ordered_class_hard_regs[cover_class][j];
1817 index = ira_class_hard_reg_index[cover_class][regno];
1818 ira_assert (index != -1);
1819 reg_costs[index] += ALLOCNO_FREQ (a);
1827 /* Add COST to the estimated gain for eliminating REGNO with its
1828 equivalence. If COST is zero, record that no such elimination is
1832 ira_adjust_equiv_reg_cost (unsigned regno, int cost)
1835 regno_equiv_gains[regno] = 0;
1837 regno_equiv_gains[regno] += cost;