1 /* Instruction scheduling pass.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com) Enhanced by,
5 and currently maintained by, Jim Wilson (wilson@cygnus.com)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it under
10 the terms of the GNU General Public License as published by the Free
11 Software Foundation; either version 3, or (at your option) any later
14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
23 /* Instruction scheduling pass. This file, along with sched-deps.c,
24 contains the generic parts. The actual entry point is found for
25 the normal instruction scheduling pass is found in sched-rgn.c.
27 We compute insn priorities based on data dependencies. Flow
28 analysis only creates a fraction of the data-dependencies we must
29 observe: namely, only those dependencies which the combiner can be
30 expected to use. For this pass, we must therefore create the
31 remaining dependencies we need to observe: register dependencies,
32 memory dependencies, dependencies to keep function calls in order,
33 and the dependence between a conditional branch and the setting of
34 condition codes are all dealt with here.
36 The scheduler first traverses the data flow graph, starting with
37 the last instruction, and proceeding to the first, assigning values
38 to insn_priority as it goes. This sorts the instructions
39 topologically by data dependence.
41 Once priorities have been established, we order the insns using
42 list scheduling. This works as follows: starting with a list of
43 all the ready insns, and sorted according to priority number, we
44 schedule the insn from the end of the list by placing its
45 predecessors in the list according to their priority order. We
46 consider this insn scheduled by setting the pointer to the "end" of
47 the list to point to the previous insn. When an insn has no
48 predecessors, we either queue it until sufficient time has elapsed
49 or add it to the ready list. As the instructions are scheduled or
50 when stalls are introduced, the queue advances and dumps insns into
51 the ready list. When all insns down to the lowest priority have
52 been scheduled, the critical path of the basic block has been made
53 as short as possible. The remaining insns are then scheduled in
56 The following list shows the order in which we want to break ties
57 among insns in the ready list:
59 1. choose insn with the longest path to end of bb, ties
61 2. choose insn with least contribution to register pressure,
63 3. prefer in-block upon interblock motion, ties broken by
64 4. prefer useful upon speculative motion, ties broken by
65 5. choose insn with largest control flow probability, ties
67 6. choose insn with the least dependences upon the previously
68 scheduled insn, or finally
69 7 choose the insn which has the most insns dependent on it.
70 8. choose insn with lowest UID.
72 Memory references complicate matters. Only if we can be certain
73 that memory references are not part of the data dependency graph
74 (via true, anti, or output dependence), can we move operations past
75 memory references. To first approximation, reads can be done
76 independently, while writes introduce dependencies. Better
77 approximations will yield fewer dependencies.
79 Before reload, an extended analysis of interblock data dependences
80 is required for interblock scheduling. This is performed in
81 compute_block_backward_dependences ().
83 Dependencies set up by memory references are treated in exactly the
84 same way as other dependencies, by using insn backward dependences
85 INSN_BACK_DEPS. INSN_BACK_DEPS are translated into forward dependences
86 INSN_FORW_DEPS the purpose of forward list scheduling.
88 Having optimized the critical path, we may have also unduly
89 extended the lifetimes of some registers. If an operation requires
90 that constants be loaded into registers, it is certainly desirable
91 to load those constants as early as necessary, but no earlier.
92 I.e., it will not do to load up a bunch of registers at the
93 beginning of a basic block only to use them at the end, if they
94 could be loaded later, since this may result in excessive register
97 Note that since branches are never in basic blocks, but only end
98 basic blocks, this pass will not move branches. But that is ok,
99 since we can use GNU's delayed branch scheduling pass to take care
102 Also note that no further optimizations based on algebraic
103 identities are performed, so this pass would be a good one to
104 perform instruction splitting, such as breaking up a multiply
105 instruction into shifts and adds where that is profitable.
107 Given the memory aliasing analysis that this pass should perform,
108 it should be possible to remove redundant stores to memory, and to
109 load values from registers instead of hitting memory.
111 Before reload, speculative insns are moved only if a 'proof' exists
112 that no exception will be caused by this, and if no live registers
113 exist that inhibit the motion (live registers constraints are not
114 represented by data dependence edges).
116 This pass must update information that subsequent passes expect to
117 be correct. Namely: reg_n_refs, reg_n_sets, reg_n_deaths,
118 reg_n_calls_crossed, and reg_live_length. Also, BB_HEAD, BB_END.
120 The information in the line number notes is carefully retained by
121 this pass. Notes that refer to the starting and ending of
122 exception regions are also carefully retained by this pass. All
123 other NOTE insns are grouped in their same relative order at the
124 beginning of basic blocks and regions that have been scheduled. */
128 #include "coretypes.h"
133 #include "hard-reg-set.h"
135 #include "function.h"
137 #include "insn-config.h"
138 #include "insn-attr.h"
142 #include "sched-int.h"
148 #ifdef INSN_SCHEDULING
150 /* issue_rate is the number of insns that can be scheduled in the same
151 machine cycle. It can be defined in the config/mach/mach.h file,
152 otherwise we set it to 1. */
154 static int issue_rate;
156 /* sched-verbose controls the amount of debugging output the
157 scheduler prints. It is controlled by -fsched-verbose=N:
158 N>0 and no -DSR : the output is directed to stderr.
159 N>=10 will direct the printouts to stderr (regardless of -dSR).
161 N=2: bb's probabilities, detailed ready list info, unit/insn info.
162 N=3: rtl at abort point, control-flow, regions info.
163 N=5: dependences info. */
165 static int sched_verbose_param = 0;
166 int sched_verbose = 0;
168 /* Debugging file. All printouts are sent to dump, which is always set,
169 either to stderr, or to the dump listing file (-dRS). */
170 FILE *sched_dump = 0;
172 /* Highest uid before scheduling. */
173 static int old_max_uid;
175 /* fix_sched_param() is called from toplev.c upon detection
176 of the -fsched-verbose=N option. */
179 fix_sched_param (const char *param, const char *val)
181 if (!strcmp (param, "verbose"))
182 sched_verbose_param = atoi (val);
184 warning (0, "fix_sched_param: unknown param: %s", param);
187 struct haifa_insn_data *h_i_d;
189 #define INSN_TICK(INSN) (h_i_d[INSN_UID (INSN)].tick)
190 #define INTER_TICK(INSN) (h_i_d[INSN_UID (INSN)].inter_tick)
192 /* If INSN_TICK of an instruction is equal to INVALID_TICK,
193 then it should be recalculated from scratch. */
194 #define INVALID_TICK (-(max_insn_queue_index + 1))
195 /* The minimal value of the INSN_TICK of an instruction. */
196 #define MIN_TICK (-max_insn_queue_index)
198 /* Issue points are used to distinguish between instructions in max_issue ().
199 For now, all instructions are equally good. */
200 #define ISSUE_POINTS(INSN) 1
202 /* List of important notes we must keep around. This is a pointer to the
203 last element in the list. */
204 static rtx note_list;
206 static struct spec_info_def spec_info_var;
207 /* Description of the speculative part of the scheduling.
208 If NULL - no speculation. */
209 spec_info_t spec_info;
211 /* True, if recovery block was added during scheduling of current block.
212 Used to determine, if we need to fix INSN_TICKs. */
213 static bool haifa_recovery_bb_recently_added_p;
215 /* True, if recovery block was added during this scheduling pass.
216 Used to determine if we should have empty memory pools of dependencies
217 after finishing current region. */
218 bool haifa_recovery_bb_ever_added_p;
220 /* Counters of different types of speculative instructions. */
221 static int nr_begin_data, nr_be_in_data, nr_begin_control, nr_be_in_control;
223 /* Array used in {unlink, restore}_bb_notes. */
224 static rtx *bb_header = 0;
226 /* Number of basic_blocks. */
227 static int old_last_basic_block;
229 /* Basic block after which recovery blocks will be created. */
230 static basic_block before_recovery;
234 /* An instruction is ready to be scheduled when all insns preceding it
235 have already been scheduled. It is important to ensure that all
236 insns which use its result will not be executed until its result
237 has been computed. An insn is maintained in one of four structures:
239 (P) the "Pending" set of insns which cannot be scheduled until
240 their dependencies have been satisfied.
241 (Q) the "Queued" set of insns that can be scheduled when sufficient
243 (R) the "Ready" list of unscheduled, uncommitted insns.
244 (S) the "Scheduled" list of insns.
246 Initially, all insns are either "Pending" or "Ready" depending on
247 whether their dependencies are satisfied.
249 Insns move from the "Ready" list to the "Scheduled" list as they
250 are committed to the schedule. As this occurs, the insns in the
251 "Pending" list have their dependencies satisfied and move to either
252 the "Ready" list or the "Queued" set depending on whether
253 sufficient time has passed to make them ready. As time passes,
254 insns move from the "Queued" set to the "Ready" list.
256 The "Pending" list (P) are the insns in the INSN_FORW_DEPS of the
257 unscheduled insns, i.e., those that are ready, queued, and pending.
258 The "Queued" set (Q) is implemented by the variable `insn_queue'.
259 The "Ready" list (R) is implemented by the variables `ready' and
261 The "Scheduled" list (S) is the new insn chain built by this pass.
263 The transition (R->S) is implemented in the scheduling loop in
264 `schedule_block' when the best insn to schedule is chosen.
265 The transitions (P->R and P->Q) are implemented in `schedule_insn' as
266 insns move from the ready list to the scheduled list.
267 The transition (Q->R) is implemented in 'queue_to_insn' as time
268 passes or stalls are introduced. */
270 /* Implement a circular buffer to delay instructions until sufficient
271 time has passed. For the new pipeline description interface,
272 MAX_INSN_QUEUE_INDEX is a power of two minus one which is not less
273 than maximal time of instruction execution computed by genattr.c on
274 the base maximal time of functional unit reservations and getting a
275 result. This is the longest time an insn may be queued. */
277 static rtx *insn_queue;
278 static int q_ptr = 0;
279 static int q_size = 0;
280 #define NEXT_Q(X) (((X)+1) & max_insn_queue_index)
281 #define NEXT_Q_AFTER(X, C) (((X)+C) & max_insn_queue_index)
283 #define QUEUE_SCHEDULED (-3)
284 #define QUEUE_NOWHERE (-2)
285 #define QUEUE_READY (-1)
286 /* QUEUE_SCHEDULED - INSN is scheduled.
287 QUEUE_NOWHERE - INSN isn't scheduled yet and is neither in
289 QUEUE_READY - INSN is in ready list.
290 N >= 0 - INSN queued for X [where NEXT_Q_AFTER (q_ptr, X) == N] cycles. */
292 #define QUEUE_INDEX(INSN) (h_i_d[INSN_UID (INSN)].queue_index)
294 /* The following variable value refers for all current and future
295 reservations of the processor units. */
298 /* The following variable value is size of memory representing all
299 current and future reservations of the processor units. */
300 static size_t dfa_state_size;
302 /* The following array is used to find the best insn from ready when
303 the automaton pipeline interface is used. */
304 static char *ready_try;
306 /* Describe the ready list of the scheduler.
307 VEC holds space enough for all insns in the current region. VECLEN
308 says how many exactly.
309 FIRST is the index of the element with the highest priority; i.e. the
310 last one in the ready list, since elements are ordered by ascending
312 N_READY determines how many insns are on the ready list. */
322 /* The pointer to the ready list. */
323 static struct ready_list *readyp;
325 /* Scheduling clock. */
326 static int clock_var;
328 /* Number of instructions in current scheduling region. */
329 static int rgn_n_insns;
331 static int may_trap_exp (rtx, int);
333 /* Nonzero iff the address is comprised from at most 1 register. */
334 #define CONST_BASED_ADDRESS_P(x) \
336 || ((GET_CODE (x) == PLUS || GET_CODE (x) == MINUS \
337 || (GET_CODE (x) == LO_SUM)) \
338 && (CONSTANT_P (XEXP (x, 0)) \
339 || CONSTANT_P (XEXP (x, 1)))))
341 /* Returns a class that insn with GET_DEST(insn)=x may belong to,
342 as found by analyzing insn's expression. */
345 may_trap_exp (rtx x, int is_store)
354 if (code == MEM && may_trap_p (x))
361 /* The insn uses memory: a volatile load. */
362 if (MEM_VOLATILE_P (x))
364 /* An exception-free load. */
367 /* A load with 1 base register, to be further checked. */
368 if (CONST_BASED_ADDRESS_P (XEXP (x, 0)))
369 return PFREE_CANDIDATE;
370 /* No info on the load, to be further checked. */
371 return PRISKY_CANDIDATE;
376 int i, insn_class = TRAP_FREE;
378 /* Neither store nor load, check if it may cause a trap. */
381 /* Recursive step: walk the insn... */
382 fmt = GET_RTX_FORMAT (code);
383 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
387 int tmp_class = may_trap_exp (XEXP (x, i), is_store);
388 insn_class = WORST_CLASS (insn_class, tmp_class);
390 else if (fmt[i] == 'E')
393 for (j = 0; j < XVECLEN (x, i); j++)
395 int tmp_class = may_trap_exp (XVECEXP (x, i, j), is_store);
396 insn_class = WORST_CLASS (insn_class, tmp_class);
397 if (insn_class == TRAP_RISKY || insn_class == IRISKY)
401 if (insn_class == TRAP_RISKY || insn_class == IRISKY)
408 /* Classifies insn for the purpose of verifying that it can be
409 moved speculatively, by examining it's patterns, returning:
410 TRAP_RISKY: store, or risky non-load insn (e.g. division by variable).
411 TRAP_FREE: non-load insn.
412 IFREE: load from a globally safe location.
413 IRISKY: volatile load.
414 PFREE_CANDIDATE, PRISKY_CANDIDATE: load that need to be checked for
415 being either PFREE or PRISKY. */
418 haifa_classify_insn (rtx insn)
420 rtx pat = PATTERN (insn);
421 int tmp_class = TRAP_FREE;
422 int insn_class = TRAP_FREE;
425 if (GET_CODE (pat) == PARALLEL)
427 int i, len = XVECLEN (pat, 0);
429 for (i = len - 1; i >= 0; i--)
431 code = GET_CODE (XVECEXP (pat, 0, i));
435 /* Test if it is a 'store'. */
436 tmp_class = may_trap_exp (XEXP (XVECEXP (pat, 0, i), 0), 1);
439 /* Test if it is a store. */
440 tmp_class = may_trap_exp (SET_DEST (XVECEXP (pat, 0, i)), 1);
441 if (tmp_class == TRAP_RISKY)
443 /* Test if it is a load. */
445 = WORST_CLASS (tmp_class,
446 may_trap_exp (SET_SRC (XVECEXP (pat, 0, i)),
451 tmp_class = TRAP_RISKY;
456 insn_class = WORST_CLASS (insn_class, tmp_class);
457 if (insn_class == TRAP_RISKY || insn_class == IRISKY)
463 code = GET_CODE (pat);
467 /* Test if it is a 'store'. */
468 tmp_class = may_trap_exp (XEXP (pat, 0), 1);
471 /* Test if it is a store. */
472 tmp_class = may_trap_exp (SET_DEST (pat), 1);
473 if (tmp_class == TRAP_RISKY)
475 /* Test if it is a load. */
477 WORST_CLASS (tmp_class,
478 may_trap_exp (SET_SRC (pat), 0));
482 tmp_class = TRAP_RISKY;
486 insn_class = tmp_class;
492 /* A typedef for rtx vector. */
493 typedef VEC(rtx, heap) *rtx_vec_t;
495 /* Forward declarations. */
497 static int priority (rtx);
498 static int rank_for_schedule (const void *, const void *);
499 static void swap_sort (rtx *, int);
500 static void queue_insn (rtx, int);
501 static int schedule_insn (rtx);
502 static int find_set_reg_weight (rtx);
503 static void find_insn_reg_weight (basic_block);
504 static void find_insn_reg_weight1 (rtx);
505 static void adjust_priority (rtx);
506 static void advance_one_cycle (void);
508 /* Notes handling mechanism:
509 =========================
510 Generally, NOTES are saved before scheduling and restored after scheduling.
511 The scheduler distinguishes between two types of notes:
513 (1) LOOP_BEGIN, LOOP_END, SETJMP, EHREGION_BEG, EHREGION_END notes:
514 Before scheduling a region, a pointer to the note is added to the insn
515 that follows or precedes it. (This happens as part of the data dependence
516 computation). After scheduling an insn, the pointer contained in it is
517 used for regenerating the corresponding note (in reemit_notes).
519 (2) All other notes (e.g. INSN_DELETED): Before scheduling a block,
520 these notes are put in a list (in rm_other_notes() and
521 unlink_other_notes ()). After scheduling the block, these notes are
522 inserted at the beginning of the block (in schedule_block()). */
524 static rtx unlink_other_notes (rtx, rtx);
525 static void reemit_notes (rtx);
527 static rtx *ready_lastpos (struct ready_list *);
528 static void ready_add (struct ready_list *, rtx, bool);
529 static void ready_sort (struct ready_list *);
530 static rtx ready_remove_first (struct ready_list *);
532 static void queue_to_ready (struct ready_list *);
533 static int early_queue_to_ready (state_t, struct ready_list *);
535 static void debug_ready_list (struct ready_list *);
537 static void move_insn (rtx);
539 /* The following functions are used to implement multi-pass scheduling
540 on the first cycle. */
541 static rtx ready_element (struct ready_list *, int);
542 static rtx ready_remove (struct ready_list *, int);
543 static void ready_remove_insn (rtx);
544 static int max_issue (struct ready_list *, int *, int);
546 static int choose_ready (struct ready_list *, rtx *);
548 static void fix_inter_tick (rtx, rtx);
549 static int fix_tick_ready (rtx);
550 static void change_queue_index (rtx, int);
552 /* The following functions are used to implement scheduling of data/control
553 speculative instructions. */
555 static void extend_h_i_d (void);
556 static void extend_ready (int);
557 static void extend_global (rtx);
558 static void extend_all (rtx);
559 static void init_h_i_d (rtx);
560 static void generate_recovery_code (rtx);
561 static void process_insn_forw_deps_be_in_spec (rtx, rtx, ds_t);
562 static void begin_speculative_block (rtx);
563 static void add_to_speculative_block (rtx);
564 static dw_t dep_weak (ds_t);
565 static edge find_fallthru_edge (basic_block);
566 static void init_before_recovery (void);
567 static basic_block create_recovery_block (void);
568 static void create_check_block_twin (rtx, bool);
569 static void fix_recovery_deps (basic_block);
570 static void change_pattern (rtx, rtx);
571 static int speculate_insn (rtx, ds_t, rtx *);
572 static void dump_new_block_header (int, basic_block, rtx, rtx);
573 static void restore_bb_notes (basic_block);
574 static void extend_bb (void);
575 static void fix_jump_move (rtx);
576 static void move_block_after_check (rtx);
577 static void move_succs (VEC(edge,gc) **, basic_block);
578 static void sched_remove_insn (rtx);
579 static void clear_priorities (rtx, rtx_vec_t *);
580 static void calc_priorities (rtx_vec_t);
581 static void add_jump_dependencies (rtx, rtx);
582 #ifdef ENABLE_CHECKING
583 static int has_edge_p (VEC(edge,gc) *, int);
584 static void check_cfg (rtx, rtx);
585 static void check_sched_flags (void);
588 #endif /* INSN_SCHEDULING */
590 /* Point to state used for the current scheduling pass. */
591 struct sched_info *current_sched_info;
593 #ifndef INSN_SCHEDULING
595 schedule_insns (void)
600 /* Working copy of frontend's sched_info variable. */
601 static struct sched_info current_sched_info_var;
603 /* Pointer to the last instruction scheduled. Used by rank_for_schedule,
604 so that insns independent of the last scheduled insn will be preferred
605 over dependent instructions. */
607 static rtx last_scheduled_insn;
609 /* Cached cost of the instruction. Use below function to get cost of the
610 insn. -1 here means that the field is not initialized. */
611 #define INSN_COST(INSN) (h_i_d[INSN_UID (INSN)].cost)
613 /* Compute cost of executing INSN.
614 This is the number of cycles between instruction issue and
615 instruction results. */
619 int cost = INSN_COST (insn);
623 /* A USE insn, or something else we don't need to
624 understand. We can't pass these directly to
625 result_ready_cost or insn_default_latency because it will
626 trigger a fatal error for unrecognizable insns. */
627 if (recog_memoized (insn) < 0)
629 INSN_COST (insn) = 0;
634 cost = insn_default_latency (insn);
638 INSN_COST (insn) = cost;
645 /* Compute cost of dependence LINK.
646 This is the number of cycles between instruction issue and
647 instruction results. */
649 dep_cost (dep_t link)
651 rtx used = DEP_CON (link);
654 /* A USE insn should never require the value used to be computed.
655 This allows the computation of a function's result and parameter
656 values to overlap the return and call. */
657 if (recog_memoized (used) < 0)
661 rtx insn = DEP_PRO (link);
662 enum reg_note dep_type = DEP_TYPE (link);
664 cost = insn_cost (insn);
666 if (INSN_CODE (insn) >= 0)
668 if (dep_type == REG_DEP_ANTI)
670 else if (dep_type == REG_DEP_OUTPUT)
672 cost = (insn_default_latency (insn)
673 - insn_default_latency (used));
677 else if (bypass_p (insn))
678 cost = insn_latency (insn, used);
681 if (targetm.sched.adjust_cost != NULL)
683 /* This variable is used for backward compatibility with the
685 rtx dep_cost_rtx_link = alloc_INSN_LIST (NULL_RTX, NULL_RTX);
687 /* Make it self-cycled, so that if some tries to walk over this
688 incomplete list he/she will be caught in an endless loop. */
689 XEXP (dep_cost_rtx_link, 1) = dep_cost_rtx_link;
691 /* Targets use only REG_NOTE_KIND of the link. */
692 PUT_REG_NOTE_KIND (dep_cost_rtx_link, DEP_TYPE (link));
694 cost = targetm.sched.adjust_cost (used, dep_cost_rtx_link,
697 free_INSN_LIST_node (dep_cost_rtx_link);
707 /* Return 'true' if DEP should be included in priority calculations. */
709 contributes_to_priority_p (dep_t dep)
711 /* Critical path is meaningful in block boundaries only. */
712 if (!current_sched_info->contributes_to_priority (DEP_CON (dep),
716 /* If flag COUNT_SPEC_IN_CRITICAL_PATH is set,
717 then speculative instructions will less likely be
718 scheduled. That is because the priority of
719 their producers will increase, and, thus, the
720 producers will more likely be scheduled, thus,
721 resolving the dependence. */
722 if ((current_sched_info->flags & DO_SPECULATION)
723 && !(spec_info->flags & COUNT_SPEC_IN_CRITICAL_PATH)
724 && (DEP_STATUS (dep) & SPECULATIVE))
730 /* Compute the priority number for INSN. */
737 /* We should not be interested in priority of an already scheduled insn. */
738 gcc_assert (QUEUE_INDEX (insn) != QUEUE_SCHEDULED);
740 if (!INSN_PRIORITY_KNOWN (insn))
742 int this_priority = 0;
744 if (sd_lists_empty_p (insn, SD_LIST_FORW))
745 /* ??? We should set INSN_PRIORITY to insn_cost when and insn has
746 some forward deps but all of them are ignored by
747 contributes_to_priority hook. At the moment we set priority of
749 this_priority = insn_cost (insn);
752 rtx prev_first, twin;
755 /* For recovery check instructions we calculate priority slightly
756 different than that of normal instructions. Instead of walking
757 through INSN_FORW_DEPS (check) list, we walk through
758 INSN_FORW_DEPS list of each instruction in the corresponding
761 rec = RECOVERY_BLOCK (insn);
762 if (!rec || rec == EXIT_BLOCK_PTR)
764 prev_first = PREV_INSN (insn);
769 prev_first = NEXT_INSN (BB_HEAD (rec));
770 twin = PREV_INSN (BB_END (rec));
775 sd_iterator_def sd_it;
778 FOR_EACH_DEP (twin, SD_LIST_FORW, sd_it, dep)
783 next = DEP_CON (dep);
785 if (BLOCK_FOR_INSN (next) != rec)
789 if (!contributes_to_priority_p (dep))
793 cost = dep_cost (dep);
796 struct _dep _dep1, *dep1 = &_dep1;
798 init_dep (dep1, insn, next, REG_DEP_ANTI);
800 cost = dep_cost (dep1);
803 next_priority = cost + priority (next);
805 if (next_priority > this_priority)
806 this_priority = next_priority;
810 twin = PREV_INSN (twin);
812 while (twin != prev_first);
814 INSN_PRIORITY (insn) = this_priority;
815 INSN_PRIORITY_STATUS (insn) = 1;
818 return INSN_PRIORITY (insn);
821 /* Macros and functions for keeping the priority queue sorted, and
822 dealing with queuing and dequeuing of instructions. */
824 #define SCHED_SORT(READY, N_READY) \
825 do { if ((N_READY) == 2) \
826 swap_sort (READY, N_READY); \
827 else if ((N_READY) > 2) \
828 qsort (READY, N_READY, sizeof (rtx), rank_for_schedule); } \
831 /* Returns a positive value if x is preferred; returns a negative value if
832 y is preferred. Should never return 0, since that will make the sort
836 rank_for_schedule (const void *x, const void *y)
838 rtx tmp = *(const rtx *) y;
839 rtx tmp2 = *(const rtx *) x;
840 int tmp_class, tmp2_class;
841 int val, priority_val, weight_val, info_val;
843 /* The insn in a schedule group should be issued the first. */
844 if (SCHED_GROUP_P (tmp) != SCHED_GROUP_P (tmp2))
845 return SCHED_GROUP_P (tmp2) ? 1 : -1;
847 /* Make sure that priority of TMP and TMP2 are initialized. */
848 gcc_assert (INSN_PRIORITY_KNOWN (tmp) && INSN_PRIORITY_KNOWN (tmp2));
850 /* Prefer insn with higher priority. */
851 priority_val = INSN_PRIORITY (tmp2) - INSN_PRIORITY (tmp);
856 /* Prefer speculative insn with greater dependencies weakness. */
863 ds1 = TODO_SPEC (tmp) & SPECULATIVE;
865 dw1 = dep_weak (ds1);
869 ds2 = TODO_SPEC (tmp2) & SPECULATIVE;
871 dw2 = dep_weak (ds2);
876 if (dw > (NO_DEP_WEAK / 8) || dw < -(NO_DEP_WEAK / 8))
880 /* Prefer an insn with smaller contribution to registers-pressure. */
881 if (!reload_completed &&
882 (weight_val = INSN_REG_WEIGHT (tmp) - INSN_REG_WEIGHT (tmp2)))
885 info_val = (*current_sched_info->rank) (tmp, tmp2);
889 /* Compare insns based on their relation to the last-scheduled-insn. */
890 if (INSN_P (last_scheduled_insn))
895 /* Classify the instructions into three classes:
896 1) Data dependent on last schedule insn.
897 2) Anti/Output dependent on last scheduled insn.
898 3) Independent of last scheduled insn, or has latency of one.
899 Choose the insn from the highest numbered class if different. */
900 dep1 = sd_find_dep_between (last_scheduled_insn, tmp, true);
902 if (dep1 == NULL || dep_cost (dep1) == 1)
904 else if (/* Data dependence. */
905 DEP_TYPE (dep1) == REG_DEP_TRUE)
910 dep2 = sd_find_dep_between (last_scheduled_insn, tmp2, true);
912 if (dep2 == NULL || dep_cost (dep2) == 1)
914 else if (/* Data dependence. */
915 DEP_TYPE (dep2) == REG_DEP_TRUE)
920 if ((val = tmp2_class - tmp_class))
924 /* Prefer the insn which has more later insns that depend on it.
925 This gives the scheduler more freedom when scheduling later
926 instructions at the expense of added register pressure. */
928 val = (sd_lists_size (tmp2, SD_LIST_FORW)
929 - sd_lists_size (tmp, SD_LIST_FORW));
934 /* If insns are equally good, sort by INSN_LUID (original insn order),
935 so that we make the sort stable. This minimizes instruction movement,
936 thus minimizing sched's effect on debugging and cross-jumping. */
937 return INSN_LUID (tmp) - INSN_LUID (tmp2);
940 /* Resort the array A in which only element at index N may be out of order. */
942 HAIFA_INLINE static void
943 swap_sort (rtx *a, int n)
948 while (i >= 0 && rank_for_schedule (a + i, &insn) >= 0)
956 /* Add INSN to the insn queue so that it can be executed at least
957 N_CYCLES after the currently executing insn. Preserve insns
958 chain for debugging purposes. */
960 HAIFA_INLINE static void
961 queue_insn (rtx insn, int n_cycles)
963 int next_q = NEXT_Q_AFTER (q_ptr, n_cycles);
964 rtx link = alloc_INSN_LIST (insn, insn_queue[next_q]);
966 gcc_assert (n_cycles <= max_insn_queue_index);
968 insn_queue[next_q] = link;
971 if (sched_verbose >= 2)
973 fprintf (sched_dump, ";;\t\tReady-->Q: insn %s: ",
974 (*current_sched_info->print_insn) (insn, 0));
976 fprintf (sched_dump, "queued for %d cycles.\n", n_cycles);
979 QUEUE_INDEX (insn) = next_q;
982 /* Remove INSN from queue. */
984 queue_remove (rtx insn)
986 gcc_assert (QUEUE_INDEX (insn) >= 0);
987 remove_free_INSN_LIST_elem (insn, &insn_queue[QUEUE_INDEX (insn)]);
989 QUEUE_INDEX (insn) = QUEUE_NOWHERE;
992 /* Return a pointer to the bottom of the ready list, i.e. the insn
993 with the lowest priority. */
995 HAIFA_INLINE static rtx *
996 ready_lastpos (struct ready_list *ready)
998 gcc_assert (ready->n_ready >= 1);
999 return ready->vec + ready->first - ready->n_ready + 1;
1002 /* Add an element INSN to the ready list so that it ends up with the
1003 lowest/highest priority depending on FIRST_P. */
1005 HAIFA_INLINE static void
1006 ready_add (struct ready_list *ready, rtx insn, bool first_p)
1010 if (ready->first == ready->n_ready)
1012 memmove (ready->vec + ready->veclen - ready->n_ready,
1013 ready_lastpos (ready),
1014 ready->n_ready * sizeof (rtx));
1015 ready->first = ready->veclen - 1;
1017 ready->vec[ready->first - ready->n_ready] = insn;
1021 if (ready->first == ready->veclen - 1)
1024 /* ready_lastpos() fails when called with (ready->n_ready == 0). */
1025 memmove (ready->vec + ready->veclen - ready->n_ready - 1,
1026 ready_lastpos (ready),
1027 ready->n_ready * sizeof (rtx));
1028 ready->first = ready->veclen - 2;
1030 ready->vec[++(ready->first)] = insn;
1035 gcc_assert (QUEUE_INDEX (insn) != QUEUE_READY);
1036 QUEUE_INDEX (insn) = QUEUE_READY;
1039 /* Remove the element with the highest priority from the ready list and
1042 HAIFA_INLINE static rtx
1043 ready_remove_first (struct ready_list *ready)
1047 gcc_assert (ready->n_ready);
1048 t = ready->vec[ready->first--];
1050 /* If the queue becomes empty, reset it. */
1051 if (ready->n_ready == 0)
1052 ready->first = ready->veclen - 1;
1054 gcc_assert (QUEUE_INDEX (t) == QUEUE_READY);
1055 QUEUE_INDEX (t) = QUEUE_NOWHERE;
1060 /* The following code implements multi-pass scheduling for the first
1061 cycle. In other words, we will try to choose ready insn which
1062 permits to start maximum number of insns on the same cycle. */
1064 /* Return a pointer to the element INDEX from the ready. INDEX for
1065 insn with the highest priority is 0, and the lowest priority has
1068 HAIFA_INLINE static rtx
1069 ready_element (struct ready_list *ready, int index)
1071 gcc_assert (ready->n_ready && index < ready->n_ready);
1073 return ready->vec[ready->first - index];
1076 /* Remove the element INDEX from the ready list and return it. INDEX
1077 for insn with the highest priority is 0, and the lowest priority
1080 HAIFA_INLINE static rtx
1081 ready_remove (struct ready_list *ready, int index)
1087 return ready_remove_first (ready);
1088 gcc_assert (ready->n_ready && index < ready->n_ready);
1089 t = ready->vec[ready->first - index];
1091 for (i = index; i < ready->n_ready; i++)
1092 ready->vec[ready->first - i] = ready->vec[ready->first - i - 1];
1093 QUEUE_INDEX (t) = QUEUE_NOWHERE;
1097 /* Remove INSN from the ready list. */
1099 ready_remove_insn (rtx insn)
1103 for (i = 0; i < readyp->n_ready; i++)
1104 if (ready_element (readyp, i) == insn)
1106 ready_remove (readyp, i);
1112 /* Sort the ready list READY by ascending priority, using the SCHED_SORT
1115 HAIFA_INLINE static void
1116 ready_sort (struct ready_list *ready)
1118 rtx *first = ready_lastpos (ready);
1119 SCHED_SORT (first, ready->n_ready);
1122 /* PREV is an insn that is ready to execute. Adjust its priority if that
1123 will help shorten or lengthen register lifetimes as appropriate. Also
1124 provide a hook for the target to tweek itself. */
1126 HAIFA_INLINE static void
1127 adjust_priority (rtx prev)
1129 /* ??? There used to be code here to try and estimate how an insn
1130 affected register lifetimes, but it did it by looking at REG_DEAD
1131 notes, which we removed in schedule_region. Nor did it try to
1132 take into account register pressure or anything useful like that.
1134 Revisit when we have a machine model to work with and not before. */
1136 if (targetm.sched.adjust_priority)
1137 INSN_PRIORITY (prev) =
1138 targetm.sched.adjust_priority (prev, INSN_PRIORITY (prev));
1141 /* Advance time on one cycle. */
1142 HAIFA_INLINE static void
1143 advance_one_cycle (void)
1145 if (targetm.sched.dfa_pre_cycle_insn)
1146 state_transition (curr_state,
1147 targetm.sched.dfa_pre_cycle_insn ());
1149 state_transition (curr_state, NULL);
1151 if (targetm.sched.dfa_post_cycle_insn)
1152 state_transition (curr_state,
1153 targetm.sched.dfa_post_cycle_insn ());
1156 /* Clock at which the previous instruction was issued. */
1157 static int last_clock_var;
1159 /* INSN is the "currently executing insn". Launch each insn which was
1160 waiting on INSN. READY is the ready list which contains the insns
1161 that are ready to fire. CLOCK is the current cycle. The function
1162 returns necessary cycle advance after issuing the insn (it is not
1163 zero for insns in a schedule group). */
1166 schedule_insn (rtx insn)
1168 sd_iterator_def sd_it;
1172 if (sched_verbose >= 1)
1176 print_insn (buf, insn, 0);
1178 fprintf (sched_dump, ";;\t%3i--> %-40s:", clock_var, buf);
1180 if (recog_memoized (insn) < 0)
1181 fprintf (sched_dump, "nothing");
1183 print_reservation (sched_dump, insn);
1184 fputc ('\n', sched_dump);
1187 /* Scheduling instruction should have all its dependencies resolved and
1188 should have been removed from the ready list. */
1189 gcc_assert (sd_lists_empty_p (insn, SD_LIST_BACK));
1191 gcc_assert (QUEUE_INDEX (insn) == QUEUE_NOWHERE);
1192 QUEUE_INDEX (insn) = QUEUE_SCHEDULED;
1194 gcc_assert (INSN_TICK (insn) >= MIN_TICK);
1195 if (INSN_TICK (insn) > clock_var)
1196 /* INSN has been prematurely moved from the queue to the ready list.
1197 This is possible only if following flag is set. */
1198 gcc_assert (flag_sched_stalled_insns);
1200 /* ??? Probably, if INSN is scheduled prematurely, we should leave
1201 INSN_TICK untouched. This is a machine-dependent issue, actually. */
1202 INSN_TICK (insn) = clock_var;
1204 /* Update dependent instructions. */
1205 for (sd_it = sd_iterator_start (insn, SD_LIST_FORW);
1206 sd_iterator_cond (&sd_it, &dep);)
1208 rtx next = DEP_CON (dep);
1210 /* Resolve the dependence between INSN and NEXT.
1211 sd_resolve_dep () moves current dep to another list thus
1212 advancing the iterator. */
1213 sd_resolve_dep (sd_it);
1215 if (!IS_SPECULATION_BRANCHY_CHECK_P (insn))
1219 effective_cost = try_ready (next);
1221 if (effective_cost >= 0
1222 && SCHED_GROUP_P (next)
1223 && advance < effective_cost)
1224 advance = effective_cost;
1227 /* Check always has only one forward dependence (to the first insn in
1228 the recovery block), therefore, this will be executed only once. */
1230 gcc_assert (sd_lists_empty_p (insn, SD_LIST_FORW));
1231 fix_recovery_deps (RECOVERY_BLOCK (insn));
1235 /* This is the place where scheduler doesn't *basically* need backward and
1236 forward dependencies for INSN anymore. Nevertheless they are used in
1237 heuristics in rank_for_schedule (), early_queue_to_ready () and in
1238 some targets (e.g. rs6000). Thus the earliest place where we *can*
1239 remove dependencies is after targetm.sched.md_finish () call in
1240 schedule_block (). But, on the other side, the safest place to remove
1241 dependencies is when we are finishing scheduling entire region. As we
1242 don't generate [many] dependencies during scheduling itself, we won't
1243 need memory until beginning of next region.
1244 Bottom line: Dependencies are removed for all insns in the end of
1245 scheduling the region. */
1247 /* Annotate the instruction with issue information -- TImode
1248 indicates that the instruction is expected not to be able
1249 to issue on the same cycle as the previous insn. A machine
1250 may use this information to decide how the instruction should
1253 && GET_CODE (PATTERN (insn)) != USE
1254 && GET_CODE (PATTERN (insn)) != CLOBBER)
1256 if (reload_completed)
1257 PUT_MODE (insn, clock_var > last_clock_var ? TImode : VOIDmode);
1258 last_clock_var = clock_var;
1264 /* Functions for handling of notes. */
1266 /* Delete notes beginning with INSN and put them in the chain
1267 of notes ended by NOTE_LIST.
1268 Returns the insn following the notes. */
1271 unlink_other_notes (rtx insn, rtx tail)
1273 rtx prev = PREV_INSN (insn);
1275 while (insn != tail && NOTE_NOT_BB_P (insn))
1277 rtx next = NEXT_INSN (insn);
1278 basic_block bb = BLOCK_FOR_INSN (insn);
1280 /* Delete the note from its current position. */
1282 NEXT_INSN (prev) = next;
1284 PREV_INSN (next) = prev;
1288 /* Basic block can begin with either LABEL or
1289 NOTE_INSN_BASIC_BLOCK. */
1290 gcc_assert (BB_HEAD (bb) != insn);
1292 /* Check if we are removing last insn in the BB. */
1293 if (BB_END (bb) == insn)
1297 /* See sched_analyze to see how these are handled. */
1298 if (NOTE_KIND (insn) != NOTE_INSN_EH_REGION_BEG
1299 && NOTE_KIND (insn) != NOTE_INSN_EH_REGION_END)
1301 /* Insert the note at the end of the notes list. */
1302 PREV_INSN (insn) = note_list;
1304 NEXT_INSN (note_list) = insn;
1313 /* Return the head and tail pointers of ebb starting at BEG and ending
1317 get_ebb_head_tail (basic_block beg, basic_block end, rtx *headp, rtx *tailp)
1319 rtx beg_head = BB_HEAD (beg);
1320 rtx beg_tail = BB_END (beg);
1321 rtx end_head = BB_HEAD (end);
1322 rtx end_tail = BB_END (end);
1324 /* Don't include any notes or labels at the beginning of the BEG
1325 basic block, or notes at the end of the END basic blocks. */
1327 if (LABEL_P (beg_head))
1328 beg_head = NEXT_INSN (beg_head);
1330 while (beg_head != beg_tail)
1331 if (NOTE_P (beg_head))
1332 beg_head = NEXT_INSN (beg_head);
1339 end_head = beg_head;
1340 else if (LABEL_P (end_head))
1341 end_head = NEXT_INSN (end_head);
1343 while (end_head != end_tail)
1344 if (NOTE_P (end_tail))
1345 end_tail = PREV_INSN (end_tail);
1352 /* Return nonzero if there are no real insns in the range [ HEAD, TAIL ]. */
1355 no_real_insns_p (rtx head, rtx tail)
1357 while (head != NEXT_INSN (tail))
1359 if (!NOTE_P (head) && !LABEL_P (head))
1361 head = NEXT_INSN (head);
1366 /* Delete notes between HEAD and TAIL and put them in the chain
1367 of notes ended by NOTE_LIST. */
1370 rm_other_notes (rtx head, rtx tail)
1376 if (head == tail && (! INSN_P (head)))
1379 next_tail = NEXT_INSN (tail);
1380 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
1384 /* Farm out notes, and maybe save them in NOTE_LIST.
1385 This is needed to keep the debugger from
1386 getting completely deranged. */
1387 if (NOTE_NOT_BB_P (insn))
1391 insn = unlink_other_notes (insn, next_tail);
1393 gcc_assert (prev != tail && prev != head && insn != next_tail);
1398 /* Functions for computation of registers live/usage info. */
1400 /* This function looks for a new register being defined.
1401 If the destination register is already used by the source,
1402 a new register is not needed. */
1405 find_set_reg_weight (rtx x)
1407 if (GET_CODE (x) == CLOBBER
1408 && register_operand (SET_DEST (x), VOIDmode))
1410 if (GET_CODE (x) == SET
1411 && register_operand (SET_DEST (x), VOIDmode))
1413 if (REG_P (SET_DEST (x)))
1415 if (!reg_mentioned_p (SET_DEST (x), SET_SRC (x)))
1425 /* Calculate INSN_REG_WEIGHT for all insns of a block. */
1428 find_insn_reg_weight (basic_block bb)
1430 rtx insn, next_tail, head, tail;
1432 get_ebb_head_tail (bb, bb, &head, &tail);
1433 next_tail = NEXT_INSN (tail);
1435 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
1436 find_insn_reg_weight1 (insn);
1439 /* Calculate INSN_REG_WEIGHT for single instruction.
1440 Separated from find_insn_reg_weight because of need
1441 to initialize new instruction in generate_recovery_code. */
1443 find_insn_reg_weight1 (rtx insn)
1448 /* Handle register life information. */
1449 if (! INSN_P (insn))
1452 /* Increment weight for each register born here. */
1454 reg_weight += find_set_reg_weight (x);
1455 if (GET_CODE (x) == PARALLEL)
1458 for (j = XVECLEN (x, 0) - 1; j >= 0; j--)
1460 x = XVECEXP (PATTERN (insn), 0, j);
1461 reg_weight += find_set_reg_weight (x);
1464 /* Decrement weight for each register that dies here. */
1465 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
1467 if (REG_NOTE_KIND (x) == REG_DEAD
1468 || REG_NOTE_KIND (x) == REG_UNUSED)
1472 INSN_REG_WEIGHT (insn) = reg_weight;
1475 /* Move insns that became ready to fire from queue to ready list. */
1478 queue_to_ready (struct ready_list *ready)
1484 q_ptr = NEXT_Q (q_ptr);
1486 if (dbg_cnt (sched_insn) == false)
1487 /* If debug counter is activated do not requeue insn next after
1488 last_scheduled_insn. */
1489 skip_insn = next_nonnote_insn (last_scheduled_insn);
1491 skip_insn = NULL_RTX;
1493 /* Add all pending insns that can be scheduled without stalls to the
1495 for (link = insn_queue[q_ptr]; link; link = XEXP (link, 1))
1497 insn = XEXP (link, 0);
1500 if (sched_verbose >= 2)
1501 fprintf (sched_dump, ";;\t\tQ-->Ready: insn %s: ",
1502 (*current_sched_info->print_insn) (insn, 0));
1504 /* If the ready list is full, delay the insn for 1 cycle.
1505 See the comment in schedule_block for the rationale. */
1506 if (!reload_completed
1507 && ready->n_ready > MAX_SCHED_READY_INSNS
1508 && !SCHED_GROUP_P (insn)
1509 && insn != skip_insn)
1511 if (sched_verbose >= 2)
1512 fprintf (sched_dump, "requeued because ready full\n");
1513 queue_insn (insn, 1);
1517 ready_add (ready, insn, false);
1518 if (sched_verbose >= 2)
1519 fprintf (sched_dump, "moving to ready without stalls\n");
1522 free_INSN_LIST_list (&insn_queue[q_ptr]);
1524 /* If there are no ready insns, stall until one is ready and add all
1525 of the pending insns at that point to the ready list. */
1526 if (ready->n_ready == 0)
1530 for (stalls = 1; stalls <= max_insn_queue_index; stalls++)
1532 if ((link = insn_queue[NEXT_Q_AFTER (q_ptr, stalls)]))
1534 for (; link; link = XEXP (link, 1))
1536 insn = XEXP (link, 0);
1539 if (sched_verbose >= 2)
1540 fprintf (sched_dump, ";;\t\tQ-->Ready: insn %s: ",
1541 (*current_sched_info->print_insn) (insn, 0));
1543 ready_add (ready, insn, false);
1544 if (sched_verbose >= 2)
1545 fprintf (sched_dump, "moving to ready with %d stalls\n", stalls);
1547 free_INSN_LIST_list (&insn_queue[NEXT_Q_AFTER (q_ptr, stalls)]);
1549 advance_one_cycle ();
1554 advance_one_cycle ();
1557 q_ptr = NEXT_Q_AFTER (q_ptr, stalls);
1558 clock_var += stalls;
1562 /* Used by early_queue_to_ready. Determines whether it is "ok" to
1563 prematurely move INSN from the queue to the ready list. Currently,
1564 if a target defines the hook 'is_costly_dependence', this function
1565 uses the hook to check whether there exist any dependences which are
1566 considered costly by the target, between INSN and other insns that
1567 have already been scheduled. Dependences are checked up to Y cycles
1568 back, with default Y=1; The flag -fsched-stalled-insns-dep=Y allows
1569 controlling this value.
1570 (Other considerations could be taken into account instead (or in
1571 addition) depending on user flags and target hooks. */
1574 ok_for_early_queue_removal (rtx insn)
1577 rtx prev_insn = last_scheduled_insn;
1579 if (targetm.sched.is_costly_dependence)
1581 for (n_cycles = flag_sched_stalled_insns_dep; n_cycles; n_cycles--)
1583 for ( ; prev_insn; prev_insn = PREV_INSN (prev_insn))
1587 if (!NOTE_P (prev_insn))
1591 dep = sd_find_dep_between (prev_insn, insn, true);
1595 cost = dep_cost (dep);
1597 if (targetm.sched.is_costly_dependence (dep, cost,
1598 flag_sched_stalled_insns_dep - n_cycles))
1603 if (GET_MODE (prev_insn) == TImode) /* end of dispatch group */
1609 prev_insn = PREV_INSN (prev_insn);
1617 /* Remove insns from the queue, before they become "ready" with respect
1618 to FU latency considerations. */
1621 early_queue_to_ready (state_t state, struct ready_list *ready)
1629 state_t temp_state = alloca (dfa_state_size);
1631 int insns_removed = 0;
1634 Flag '-fsched-stalled-insns=X' determines the aggressiveness of this
1637 X == 0: There is no limit on how many queued insns can be removed
1638 prematurely. (flag_sched_stalled_insns = -1).
1640 X >= 1: Only X queued insns can be removed prematurely in each
1641 invocation. (flag_sched_stalled_insns = X).
1643 Otherwise: Early queue removal is disabled.
1644 (flag_sched_stalled_insns = 0)
1647 if (! flag_sched_stalled_insns)
1650 for (stalls = 0; stalls <= max_insn_queue_index; stalls++)
1652 if ((link = insn_queue[NEXT_Q_AFTER (q_ptr, stalls)]))
1654 if (sched_verbose > 6)
1655 fprintf (sched_dump, ";; look at index %d + %d\n", q_ptr, stalls);
1660 next_link = XEXP (link, 1);
1661 insn = XEXP (link, 0);
1662 if (insn && sched_verbose > 6)
1663 print_rtl_single (sched_dump, insn);
1665 memcpy (temp_state, state, dfa_state_size);
1666 if (recog_memoized (insn) < 0)
1667 /* non-negative to indicate that it's not ready
1668 to avoid infinite Q->R->Q->R... */
1671 cost = state_transition (temp_state, insn);
1673 if (sched_verbose >= 6)
1674 fprintf (sched_dump, "transition cost = %d\n", cost);
1676 move_to_ready = false;
1679 move_to_ready = ok_for_early_queue_removal (insn);
1680 if (move_to_ready == true)
1682 /* move from Q to R */
1684 ready_add (ready, insn, false);
1687 XEXP (prev_link, 1) = next_link;
1689 insn_queue[NEXT_Q_AFTER (q_ptr, stalls)] = next_link;
1691 free_INSN_LIST_node (link);
1693 if (sched_verbose >= 2)
1694 fprintf (sched_dump, ";;\t\tEarly Q-->Ready: insn %s\n",
1695 (*current_sched_info->print_insn) (insn, 0));
1698 if (insns_removed == flag_sched_stalled_insns)
1699 /* Remove no more than flag_sched_stalled_insns insns
1700 from Q at a time. */
1701 return insns_removed;
1705 if (move_to_ready == false)
1712 } /* for stalls.. */
1714 return insns_removed;
1718 /* Print the ready list for debugging purposes. Callable from debugger. */
1721 debug_ready_list (struct ready_list *ready)
1726 if (ready->n_ready == 0)
1728 fprintf (sched_dump, "\n");
1732 p = ready_lastpos (ready);
1733 for (i = 0; i < ready->n_ready; i++)
1734 fprintf (sched_dump, " %s", (*current_sched_info->print_insn) (p[i], 0));
1735 fprintf (sched_dump, "\n");
1738 /* Search INSN for REG_SAVE_NOTE note pairs for
1739 NOTE_INSN_EHREGION_{BEG,END}; and convert them back into
1740 NOTEs. The REG_SAVE_NOTE note following first one is contains the
1741 saved value for NOTE_BLOCK_NUMBER which is useful for
1742 NOTE_INSN_EH_REGION_{BEG,END} NOTEs. */
1745 reemit_notes (rtx insn)
1747 rtx note, last = insn;
1749 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
1751 if (REG_NOTE_KIND (note) == REG_SAVE_NOTE)
1753 enum insn_note note_type = INTVAL (XEXP (note, 0));
1755 last = emit_note_before (note_type, last);
1756 remove_note (insn, note);
1761 /* Move INSN. Reemit notes if needed. Update CFG, if needed. */
1763 move_insn (rtx insn)
1765 rtx last = last_scheduled_insn;
1767 if (PREV_INSN (insn) != last)
1773 bb = BLOCK_FOR_INSN (insn);
1775 /* BB_HEAD is either LABEL or NOTE. */
1776 gcc_assert (BB_HEAD (bb) != insn);
1778 if (BB_END (bb) == insn)
1779 /* If this is last instruction in BB, move end marker one
1782 /* Jumps are always placed at the end of basic block. */
1783 jump_p = control_flow_insn_p (insn);
1786 || ((current_sched_info->flags & SCHED_RGN)
1787 && IS_SPECULATION_BRANCHY_CHECK_P (insn))
1788 || (current_sched_info->flags & SCHED_EBB));
1790 gcc_assert (BLOCK_FOR_INSN (PREV_INSN (insn)) == bb);
1792 BB_END (bb) = PREV_INSN (insn);
1795 gcc_assert (BB_END (bb) != last);
1798 /* We move the block note along with jump. */
1800 /* NT is needed for assertion below. */
1801 rtx nt = current_sched_info->next_tail;
1803 note = NEXT_INSN (insn);
1804 while (NOTE_NOT_BB_P (note) && note != nt)
1805 note = NEXT_INSN (note);
1809 || BARRIER_P (note)))
1810 note = NEXT_INSN (note);
1812 gcc_assert (NOTE_INSN_BASIC_BLOCK_P (note));
1817 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (note);
1818 PREV_INSN (NEXT_INSN (note)) = PREV_INSN (insn);
1820 NEXT_INSN (note) = NEXT_INSN (last);
1821 PREV_INSN (NEXT_INSN (last)) = note;
1823 NEXT_INSN (last) = insn;
1824 PREV_INSN (insn) = last;
1826 bb = BLOCK_FOR_INSN (last);
1830 fix_jump_move (insn);
1832 if (BLOCK_FOR_INSN (insn) != bb)
1833 move_block_after_check (insn);
1835 gcc_assert (BB_END (bb) == last);
1838 set_block_for_insn (insn, bb);
1839 df_insn_change_bb (insn);
1841 /* Update BB_END, if needed. */
1842 if (BB_END (bb) == last)
1846 reemit_notes (insn);
1848 SCHED_GROUP_P (insn) = 0;
1851 /* The following structure describe an entry of the stack of choices. */
1854 /* Ordinal number of the issued insn in the ready queue. */
1856 /* The number of the rest insns whose issues we should try. */
1858 /* The number of issued essential insns. */
1860 /* State after issuing the insn. */
1864 /* The following array is used to implement a stack of choices used in
1865 function max_issue. */
1866 static struct choice_entry *choice_stack;
1868 /* The following variable value is number of essential insns issued on
1869 the current cycle. An insn is essential one if it changes the
1870 processors state. */
1871 static int cycle_issued_insns;
1873 /* The following variable value is maximal number of tries of issuing
1874 insns for the first cycle multipass insn scheduling. We define
1875 this value as constant*(DFA_LOOKAHEAD**ISSUE_RATE). We would not
1876 need this constraint if all real insns (with non-negative codes)
1877 had reservations because in this case the algorithm complexity is
1878 O(DFA_LOOKAHEAD**ISSUE_RATE). Unfortunately, the dfa descriptions
1879 might be incomplete and such insn might occur. For such
1880 descriptions, the complexity of algorithm (without the constraint)
1881 could achieve DFA_LOOKAHEAD ** N , where N is the queue length. */
1882 static int max_lookahead_tries;
1884 /* The following value is value of hook
1885 `first_cycle_multipass_dfa_lookahead' at the last call of
1887 static int cached_first_cycle_multipass_dfa_lookahead = 0;
1889 /* The following value is value of `issue_rate' at the last call of
1891 static int cached_issue_rate = 0;
1893 /* The following function returns maximal (or close to maximal) number
1894 of insns which can be issued on the same cycle and one of which
1895 insns is insns with the best rank (the first insn in READY). To
1896 make this function tries different samples of ready insns. READY
1897 is current queue `ready'. Global array READY_TRY reflects what
1898 insns are already issued in this try. MAX_POINTS is the sum of points
1899 of all instructions in READY. The function stops immediately,
1900 if it reached the such a solution, that all instruction can be issued.
1901 INDEX will contain index of the best insn in READY. The following
1902 function is used only for first cycle multipass scheduling. */
1904 max_issue (struct ready_list *ready, int *index, int max_points)
1906 int n, i, all, n_ready, best, delay, tries_num, points = -1;
1907 struct choice_entry *top;
1911 memcpy (choice_stack->state, curr_state, dfa_state_size);
1913 top->rest = cached_first_cycle_multipass_dfa_lookahead;
1915 n_ready = ready->n_ready;
1916 for (all = i = 0; i < n_ready; i++)
1923 if (top->rest == 0 || i >= n_ready)
1925 if (top == choice_stack)
1927 if (best < top - choice_stack && ready_try [0])
1929 best = top - choice_stack;
1930 *index = choice_stack [1].index;
1932 if (top->n == max_points || best == all)
1938 memcpy (curr_state, top->state, dfa_state_size);
1940 else if (!ready_try [i])
1943 if (tries_num > max_lookahead_tries)
1945 insn = ready_element (ready, i);
1946 delay = state_transition (curr_state, insn);
1949 if (state_dead_lock_p (curr_state))
1954 if (memcmp (top->state, curr_state, dfa_state_size) != 0)
1955 n += ISSUE_POINTS (insn);
1957 top->rest = cached_first_cycle_multipass_dfa_lookahead;
1960 memcpy (top->state, curr_state, dfa_state_size);
1967 while (top != choice_stack)
1969 ready_try [top->index] = 0;
1972 memcpy (curr_state, choice_stack->state, dfa_state_size);
1974 if (sched_verbose >= 4)
1975 fprintf (sched_dump, ";;\t\tChoosed insn : %s; points: %d/%d\n",
1976 (*current_sched_info->print_insn) (ready_element (ready, *index),
1978 points, max_points);
1983 /* The following function chooses insn from READY and modifies
1984 *N_READY and READY. The following function is used only for first
1985 cycle multipass scheduling.
1987 -1 if cycle should be advanced,
1988 0 if INSN_PTR is set to point to the desirable insn,
1989 1 if choose_ready () should be restarted without advancing the cycle. */
1991 choose_ready (struct ready_list *ready, rtx *insn_ptr)
1995 if (dbg_cnt (sched_insn) == false)
1999 insn = next_nonnote_insn (last_scheduled_insn);
2001 if (QUEUE_INDEX (insn) == QUEUE_READY)
2002 /* INSN is in the ready_list. */
2004 ready_remove_insn (insn);
2009 /* INSN is in the queue. Advance cycle to move it to the ready list. */
2015 if (targetm.sched.first_cycle_multipass_dfa_lookahead)
2016 lookahead = targetm.sched.first_cycle_multipass_dfa_lookahead ();
2017 if (lookahead <= 0 || SCHED_GROUP_P (ready_element (ready, 0)))
2019 *insn_ptr = ready_remove_first (ready);
2024 /* Try to choose the better insn. */
2025 int index = 0, i, n;
2027 int more_issue, max_points, try_data = 1, try_control = 1;
2029 if (cached_first_cycle_multipass_dfa_lookahead != lookahead)
2031 cached_first_cycle_multipass_dfa_lookahead = lookahead;
2032 max_lookahead_tries = 100;
2033 for (i = 0; i < issue_rate; i++)
2034 max_lookahead_tries *= lookahead;
2036 insn = ready_element (ready, 0);
2037 if (INSN_CODE (insn) < 0)
2039 *insn_ptr = ready_remove_first (ready);
2044 && spec_info->flags & (PREFER_NON_DATA_SPEC
2045 | PREFER_NON_CONTROL_SPEC))
2047 for (i = 0, n = ready->n_ready; i < n; i++)
2052 x = ready_element (ready, i);
2055 if (spec_info->flags & PREFER_NON_DATA_SPEC
2056 && !(s & DATA_SPEC))
2059 if (!(spec_info->flags & PREFER_NON_CONTROL_SPEC)
2064 if (spec_info->flags & PREFER_NON_CONTROL_SPEC
2065 && !(s & CONTROL_SPEC))
2068 if (!(spec_info->flags & PREFER_NON_DATA_SPEC) || !try_data)
2074 if ((!try_data && (TODO_SPEC (insn) & DATA_SPEC))
2075 || (!try_control && (TODO_SPEC (insn) & CONTROL_SPEC))
2076 || (targetm.sched.first_cycle_multipass_dfa_lookahead_guard_spec
2077 && !targetm.sched.first_cycle_multipass_dfa_lookahead_guard_spec
2079 /* Discard speculative instruction that stands first in the ready
2082 change_queue_index (insn, 1);
2086 max_points = ISSUE_POINTS (insn);
2087 more_issue = issue_rate - cycle_issued_insns - 1;
2089 for (i = 1; i < ready->n_ready; i++)
2091 insn = ready_element (ready, i);
2093 = (INSN_CODE (insn) < 0
2094 || (!try_data && (TODO_SPEC (insn) & DATA_SPEC))
2095 || (!try_control && (TODO_SPEC (insn) & CONTROL_SPEC))
2096 || (targetm.sched.first_cycle_multipass_dfa_lookahead_guard
2097 && !targetm.sched.first_cycle_multipass_dfa_lookahead_guard
2100 if (!ready_try [i] && more_issue-- > 0)
2101 max_points += ISSUE_POINTS (insn);
2104 if (max_issue (ready, &index, max_points) == 0)
2106 *insn_ptr = ready_remove_first (ready);
2111 *insn_ptr = ready_remove (ready, index);
2117 /* Use forward list scheduling to rearrange insns of block pointed to by
2118 TARGET_BB, possibly bringing insns from subsequent blocks in the same
2122 schedule_block (basic_block *target_bb, int rgn_n_insns1)
2124 struct ready_list ready;
2125 int i, first_cycle_insn_p;
2127 state_t temp_state = NULL; /* It is used for multipass scheduling. */
2128 int sort_p, advance, start_clock_var;
2130 /* Head/tail info for this block. */
2131 rtx prev_head = current_sched_info->prev_head;
2132 rtx next_tail = current_sched_info->next_tail;
2133 rtx head = NEXT_INSN (prev_head);
2134 rtx tail = PREV_INSN (next_tail);
2136 /* We used to have code to avoid getting parameters moved from hard
2137 argument registers into pseudos.
2139 However, it was removed when it proved to be of marginal benefit
2140 and caused problems because schedule_block and compute_forward_dependences
2141 had different notions of what the "head" insn was. */
2143 gcc_assert (head != tail || INSN_P (head));
2145 haifa_recovery_bb_recently_added_p = false;
2149 dump_new_block_header (0, *target_bb, head, tail);
2151 state_reset (curr_state);
2153 /* Allocate the ready list. */
2157 choice_stack = NULL;
2160 extend_ready (rgn_n_insns1 + 1);
2162 ready.first = ready.veclen - 1;
2165 /* It is used for first cycle multipass scheduling. */
2166 temp_state = alloca (dfa_state_size);
2168 if (targetm.sched.md_init)
2169 targetm.sched.md_init (sched_dump, sched_verbose, ready.veclen);
2171 /* We start inserting insns after PREV_HEAD. */
2172 last_scheduled_insn = prev_head;
2174 gcc_assert (NOTE_P (last_scheduled_insn)
2175 && BLOCK_FOR_INSN (last_scheduled_insn) == *target_bb);
2177 /* Initialize INSN_QUEUE. Q_SIZE is the total number of insns in the
2182 insn_queue = alloca ((max_insn_queue_index + 1) * sizeof (rtx));
2183 memset (insn_queue, 0, (max_insn_queue_index + 1) * sizeof (rtx));
2185 /* Start just before the beginning of time. */
2188 /* We need queue and ready lists and clock_var be initialized
2189 in try_ready () (which is called through init_ready_list ()). */
2190 (*current_sched_info->init_ready_list) ();
2192 /* The algorithm is O(n^2) in the number of ready insns at any given
2193 time in the worst case. Before reload we are more likely to have
2194 big lists so truncate them to a reasonable size. */
2195 if (!reload_completed && ready.n_ready > MAX_SCHED_READY_INSNS)
2197 ready_sort (&ready);
2199 /* Find first free-standing insn past MAX_SCHED_READY_INSNS. */
2200 for (i = MAX_SCHED_READY_INSNS; i < ready.n_ready; i++)
2201 if (!SCHED_GROUP_P (ready_element (&ready, i)))
2204 if (sched_verbose >= 2)
2206 fprintf (sched_dump,
2207 ";;\t\tReady list on entry: %d insns\n", ready.n_ready);
2208 fprintf (sched_dump,
2209 ";;\t\t before reload => truncated to %d insns\n", i);
2212 /* Delay all insns past it for 1 cycle. If debug counter is
2213 activated make an exception for the insn right after
2214 last_scheduled_insn. */
2218 if (dbg_cnt (sched_insn) == false)
2219 skip_insn = next_nonnote_insn (last_scheduled_insn);
2221 skip_insn = NULL_RTX;
2223 while (i < ready.n_ready)
2227 insn = ready_remove (&ready, i);
2229 if (insn != skip_insn)
2230 queue_insn (insn, 1);
2235 /* Now we can restore basic block notes and maintain precise cfg. */
2236 restore_bb_notes (*target_bb);
2238 last_clock_var = -1;
2243 /* Loop until all the insns in BB are scheduled. */
2244 while ((*current_sched_info->schedule_more_p) ())
2248 start_clock_var = clock_var;
2252 advance_one_cycle ();
2254 /* Add to the ready list all pending insns that can be issued now.
2255 If there are no ready insns, increment clock until one
2256 is ready and add all pending insns at that point to the ready
2258 queue_to_ready (&ready);
2260 gcc_assert (ready.n_ready);
2262 if (sched_verbose >= 2)
2264 fprintf (sched_dump, ";;\t\tReady list after queue_to_ready: ");
2265 debug_ready_list (&ready);
2267 advance -= clock_var - start_clock_var;
2269 while (advance > 0);
2273 /* Sort the ready list based on priority. */
2274 ready_sort (&ready);
2276 if (sched_verbose >= 2)
2278 fprintf (sched_dump, ";;\t\tReady list after ready_sort: ");
2279 debug_ready_list (&ready);
2283 /* Allow the target to reorder the list, typically for
2284 better instruction bundling. */
2285 if (sort_p && targetm.sched.reorder
2286 && (ready.n_ready == 0
2287 || !SCHED_GROUP_P (ready_element (&ready, 0))))
2289 targetm.sched.reorder (sched_dump, sched_verbose,
2290 ready_lastpos (&ready),
2291 &ready.n_ready, clock_var);
2293 can_issue_more = issue_rate;
2295 first_cycle_insn_p = 1;
2296 cycle_issued_insns = 0;
2303 if (sched_verbose >= 2)
2305 fprintf (sched_dump, ";;\tReady list (t = %3d): ",
2307 debug_ready_list (&ready);
2310 if (ready.n_ready == 0
2312 && reload_completed)
2314 /* Allow scheduling insns directly from the queue in case
2315 there's nothing better to do (ready list is empty) but
2316 there are still vacant dispatch slots in the current cycle. */
2317 if (sched_verbose >= 6)
2318 fprintf (sched_dump,";;\t\tSecond chance\n");
2319 memcpy (temp_state, curr_state, dfa_state_size);
2320 if (early_queue_to_ready (temp_state, &ready))
2321 ready_sort (&ready);
2324 if (ready.n_ready == 0 || !can_issue_more
2325 || state_dead_lock_p (curr_state)
2326 || !(*current_sched_info->schedule_more_p) ())
2329 /* Select and remove the insn from the ready list. */
2335 res = choose_ready (&ready, &insn);
2341 /* Restart choose_ready (). */
2344 gcc_assert (insn != NULL_RTX);
2347 insn = ready_remove_first (&ready);
2349 if (targetm.sched.dfa_new_cycle
2350 && targetm.sched.dfa_new_cycle (sched_dump, sched_verbose,
2351 insn, last_clock_var,
2352 clock_var, &sort_p))
2353 /* SORT_P is used by the target to override sorting
2354 of the ready list. This is needed when the target
2355 has modified its internal structures expecting that
2356 the insn will be issued next. As we need the insn
2357 to have the highest priority (so it will be returned by
2358 the ready_remove_first call above), we invoke
2359 ready_add (&ready, insn, true).
2360 But, still, there is one issue: INSN can be later
2361 discarded by scheduler's front end through
2362 current_sched_info->can_schedule_ready_p, hence, won't
2365 ready_add (&ready, insn, true);
2370 memcpy (temp_state, curr_state, dfa_state_size);
2371 if (recog_memoized (insn) < 0)
2373 asm_p = (GET_CODE (PATTERN (insn)) == ASM_INPUT
2374 || asm_noperands (PATTERN (insn)) >= 0);
2375 if (!first_cycle_insn_p && asm_p)
2376 /* This is asm insn which is tryed to be issued on the
2377 cycle not first. Issue it on the next cycle. */
2380 /* A USE insn, or something else we don't need to
2381 understand. We can't pass these directly to
2382 state_transition because it will trigger a
2383 fatal error for unrecognizable insns. */
2388 cost = state_transition (temp_state, insn);
2397 queue_insn (insn, cost);
2398 if (SCHED_GROUP_P (insn))
2407 if (current_sched_info->can_schedule_ready_p
2408 && ! (*current_sched_info->can_schedule_ready_p) (insn))
2409 /* We normally get here only if we don't want to move
2410 insn from the split block. */
2412 TODO_SPEC (insn) = (TODO_SPEC (insn) & ~SPECULATIVE) | HARD_DEP;
2416 /* DECISION is made. */
2418 if (TODO_SPEC (insn) & SPECULATIVE)
2419 generate_recovery_code (insn);
2421 if (control_flow_insn_p (last_scheduled_insn)
2422 /* This is used to switch basic blocks by request
2423 from scheduler front-end (actually, sched-ebb.c only).
2424 This is used to process blocks with single fallthru
2425 edge. If succeeding block has jump, it [jump] will try
2426 move at the end of current bb, thus corrupting CFG. */
2427 || current_sched_info->advance_target_bb (*target_bb, insn))
2429 *target_bb = current_sched_info->advance_target_bb
2436 x = next_real_insn (last_scheduled_insn);
2438 dump_new_block_header (1, *target_bb, x, tail);
2441 last_scheduled_insn = bb_note (*target_bb);
2444 /* Update counters, etc in the scheduler's front end. */
2445 (*current_sched_info->begin_schedule_ready) (insn,
2446 last_scheduled_insn);
2449 last_scheduled_insn = insn;
2451 if (memcmp (curr_state, temp_state, dfa_state_size) != 0)
2453 cycle_issued_insns++;
2454 memcpy (curr_state, temp_state, dfa_state_size);
2457 if (targetm.sched.variable_issue)
2459 targetm.sched.variable_issue (sched_dump, sched_verbose,
2460 insn, can_issue_more);
2461 /* A naked CLOBBER or USE generates no instruction, so do
2462 not count them against the issue rate. */
2463 else if (GET_CODE (PATTERN (insn)) != USE
2464 && GET_CODE (PATTERN (insn)) != CLOBBER)
2467 advance = schedule_insn (insn);
2469 /* After issuing an asm insn we should start a new cycle. */
2470 if (advance == 0 && asm_p)
2475 first_cycle_insn_p = 0;
2477 /* Sort the ready list based on priority. This must be
2478 redone here, as schedule_insn may have readied additional
2479 insns that will not be sorted correctly. */
2480 if (ready.n_ready > 0)
2481 ready_sort (&ready);
2483 if (targetm.sched.reorder2
2484 && (ready.n_ready == 0
2485 || !SCHED_GROUP_P (ready_element (&ready, 0))))
2488 targetm.sched.reorder2 (sched_dump, sched_verbose,
2490 ? ready_lastpos (&ready) : NULL,
2491 &ready.n_ready, clock_var);
2499 fprintf (sched_dump, ";;\tReady list (final): ");
2500 debug_ready_list (&ready);
2503 if (current_sched_info->queue_must_finish_empty)
2504 /* Sanity check -- queue must be empty now. Meaningless if region has
2506 gcc_assert (!q_size && !ready.n_ready);
2509 /* We must maintain QUEUE_INDEX between blocks in region. */
2510 for (i = ready.n_ready - 1; i >= 0; i--)
2514 x = ready_element (&ready, i);
2515 QUEUE_INDEX (x) = QUEUE_NOWHERE;
2516 TODO_SPEC (x) = (TODO_SPEC (x) & ~SPECULATIVE) | HARD_DEP;
2520 for (i = 0; i <= max_insn_queue_index; i++)
2523 for (link = insn_queue[i]; link; link = XEXP (link, 1))
2528 QUEUE_INDEX (x) = QUEUE_NOWHERE;
2529 TODO_SPEC (x) = (TODO_SPEC (x) & ~SPECULATIVE) | HARD_DEP;
2531 free_INSN_LIST_list (&insn_queue[i]);
2535 if (!current_sched_info->queue_must_finish_empty
2536 || haifa_recovery_bb_recently_added_p)
2538 /* INSN_TICK (minimum clock tick at which the insn becomes
2539 ready) may be not correct for the insn in the subsequent
2540 blocks of the region. We should use a correct value of
2541 `clock_var' or modify INSN_TICK. It is better to keep
2542 clock_var value equal to 0 at the start of a basic block.
2543 Therefore we modify INSN_TICK here. */
2544 fix_inter_tick (NEXT_INSN (prev_head), last_scheduled_insn);
2547 if (targetm.sched.md_finish)
2549 targetm.sched.md_finish (sched_dump, sched_verbose);
2551 /* Target might have added some instructions to the scheduled block.
2552 in its md_finish () hook. These new insns don't have any data
2553 initialized and to identify them we extend h_i_d so that they'll
2558 /* Update head/tail boundaries. */
2559 head = NEXT_INSN (prev_head);
2560 tail = last_scheduled_insn;
2562 /* Restore-other-notes: NOTE_LIST is the end of a chain of notes
2563 previously found among the insns. Insert them at the beginning
2567 basic_block head_bb = BLOCK_FOR_INSN (head);
2568 rtx note_head = note_list;
2570 while (PREV_INSN (note_head))
2572 set_block_for_insn (note_head, head_bb);
2573 note_head = PREV_INSN (note_head);
2575 /* In the above cycle we've missed this note: */
2576 set_block_for_insn (note_head, head_bb);
2578 PREV_INSN (note_head) = PREV_INSN (head);
2579 NEXT_INSN (PREV_INSN (head)) = note_head;
2580 PREV_INSN (head) = note_list;
2581 NEXT_INSN (note_list) = head;
2588 fprintf (sched_dump, ";; total time = %d\n;; new head = %d\n",
2589 clock_var, INSN_UID (head));
2590 fprintf (sched_dump, ";; new tail = %d\n\n",
2594 current_sched_info->head = head;
2595 current_sched_info->tail = tail;
2600 for (i = 0; i <= rgn_n_insns; i++)
2601 free (choice_stack [i].state);
2602 free (choice_stack);
2605 /* Set_priorities: compute priority of each insn in the block. */
2608 set_priorities (rtx head, rtx tail)
2612 int sched_max_insns_priority =
2613 current_sched_info->sched_max_insns_priority;
2616 if (head == tail && (! INSN_P (head)))
2621 prev_head = PREV_INSN (head);
2622 for (insn = tail; insn != prev_head; insn = PREV_INSN (insn))
2628 (void) priority (insn);
2630 gcc_assert (INSN_PRIORITY_KNOWN (insn));
2632 sched_max_insns_priority = MAX (sched_max_insns_priority,
2633 INSN_PRIORITY (insn));
2636 current_sched_info->sched_max_insns_priority = sched_max_insns_priority;
2641 /* Next LUID to assign to an instruction. */
2644 /* Initialize some global state for the scheduler. */
2653 /* Switch to working copy of sched_info. */
2654 memcpy (¤t_sched_info_var, current_sched_info,
2655 sizeof (current_sched_info_var));
2656 current_sched_info = ¤t_sched_info_var;
2658 /* Disable speculative loads in their presence if cc0 defined. */
2660 flag_schedule_speculative_load = 0;
2663 /* Set dump and sched_verbose for the desired debugging output. If no
2664 dump-file was specified, but -fsched-verbose=N (any N), print to stderr.
2665 For -fsched-verbose=N, N>=10, print everything to stderr. */
2666 sched_verbose = sched_verbose_param;
2667 if (sched_verbose_param == 0 && dump_file)
2669 sched_dump = ((sched_verbose_param >= 10 || !dump_file)
2670 ? stderr : dump_file);
2672 /* Initialize SPEC_INFO. */
2673 if (targetm.sched.set_sched_flags)
2675 spec_info = &spec_info_var;
2676 targetm.sched.set_sched_flags (spec_info);
2677 if (current_sched_info->flags & DO_SPECULATION)
2678 spec_info->weakness_cutoff =
2679 (PARAM_VALUE (PARAM_SCHED_SPEC_PROB_CUTOFF) * MAX_DEP_WEAK) / 100;
2681 /* So we won't read anything accidentally. */
2683 #ifdef ENABLE_CHECKING
2684 check_sched_flags ();
2688 /* So we won't read anything accidentally. */
2691 /* Initialize issue_rate. */
2692 if (targetm.sched.issue_rate)
2693 issue_rate = targetm.sched.issue_rate ();
2697 if (cached_issue_rate != issue_rate)
2699 cached_issue_rate = issue_rate;
2700 /* To invalidate max_lookahead_tries: */
2701 cached_first_cycle_multipass_dfa_lookahead = 0;
2708 for (i = 0; i < old_max_uid; i++)
2711 h_i_d[i].todo_spec = HARD_DEP;
2712 h_i_d[i].queue_index = QUEUE_NOWHERE;
2713 h_i_d[i].tick = INVALID_TICK;
2714 h_i_d[i].inter_tick = INVALID_TICK;
2717 if (targetm.sched.init_dfa_pre_cycle_insn)
2718 targetm.sched.init_dfa_pre_cycle_insn ();
2720 if (targetm.sched.init_dfa_post_cycle_insn)
2721 targetm.sched.init_dfa_post_cycle_insn ();
2724 dfa_state_size = state_size ();
2725 curr_state = xmalloc (dfa_state_size);
2730 for (insn = BB_HEAD (b); ; insn = NEXT_INSN (insn))
2732 INSN_LUID (insn) = luid;
2734 /* Increment the next luid, unless this is a note. We don't
2735 really need separate IDs for notes and we don't want to
2736 schedule differently depending on whether or not there are
2737 line-number notes, i.e., depending on whether or not we're
2738 generating debugging information. */
2742 if (insn == BB_END (b))
2746 init_dependency_caches (luid);
2748 init_alias_analysis ();
2750 old_last_basic_block = 0;
2753 /* Compute INSN_REG_WEIGHT for all blocks. We must do this before
2754 removing death notes. */
2755 FOR_EACH_BB_REVERSE (b)
2756 find_insn_reg_weight (b);
2758 if (targetm.sched.md_init_global)
2759 targetm.sched.md_init_global (sched_dump, sched_verbose, old_max_uid);
2761 nr_begin_data = nr_begin_control = nr_be_in_data = nr_be_in_control = 0;
2762 before_recovery = 0;
2764 haifa_recovery_bb_ever_added_p = false;
2766 #ifdef ENABLE_CHECKING
2767 /* This is used preferably for finding bugs in check_cfg () itself. */
2772 /* Free global data used during insn scheduling. */
2780 free_dependency_caches ();
2781 end_alias_analysis ();
2783 if (targetm.sched.md_finish_global)
2784 targetm.sched.md_finish_global (sched_dump, sched_verbose);
2786 if (spec_info && spec_info->dump)
2788 char c = reload_completed ? 'a' : 'b';
2790 fprintf (spec_info->dump,
2791 ";; %s:\n", current_function_name ());
2793 fprintf (spec_info->dump,
2794 ";; Procedure %cr-begin-data-spec motions == %d\n",
2796 fprintf (spec_info->dump,
2797 ";; Procedure %cr-be-in-data-spec motions == %d\n",
2799 fprintf (spec_info->dump,
2800 ";; Procedure %cr-begin-control-spec motions == %d\n",
2801 c, nr_begin_control);
2802 fprintf (spec_info->dump,
2803 ";; Procedure %cr-be-in-control-spec motions == %d\n",
2804 c, nr_be_in_control);
2807 #ifdef ENABLE_CHECKING
2808 /* After reload ia64 backend clobbers CFG, so can't check anything. */
2809 if (!reload_completed)
2813 current_sched_info = NULL;
2816 /* Fix INSN_TICKs of the instructions in the current block as well as
2817 INSN_TICKs of their dependents.
2818 HEAD and TAIL are the begin and the end of the current scheduled block. */
2820 fix_inter_tick (rtx head, rtx tail)
2822 /* Set of instructions with corrected INSN_TICK. */
2823 bitmap_head processed;
2824 /* ??? It is doubtful if we should assume that cycle advance happens on
2825 basic block boundaries. Basically insns that are unconditionally ready
2826 on the start of the block are more preferable then those which have
2827 a one cycle dependency over insn from the previous block. */
2828 int next_clock = clock_var + 1;
2830 bitmap_initialize (&processed, 0);
2832 /* Iterates over scheduled instructions and fix their INSN_TICKs and
2833 INSN_TICKs of dependent instructions, so that INSN_TICKs are consistent
2834 across different blocks. */
2835 for (tail = NEXT_INSN (tail); head != tail; head = NEXT_INSN (head))
2840 sd_iterator_def sd_it;
2843 tick = INSN_TICK (head);
2844 gcc_assert (tick >= MIN_TICK);
2846 /* Fix INSN_TICK of instruction from just scheduled block. */
2847 if (!bitmap_bit_p (&processed, INSN_LUID (head)))
2849 bitmap_set_bit (&processed, INSN_LUID (head));
2852 if (tick < MIN_TICK)
2855 INSN_TICK (head) = tick;
2858 FOR_EACH_DEP (head, SD_LIST_RES_FORW, sd_it, dep)
2862 next = DEP_CON (dep);
2863 tick = INSN_TICK (next);
2865 if (tick != INVALID_TICK
2866 /* If NEXT has its INSN_TICK calculated, fix it.
2867 If not - it will be properly calculated from
2868 scratch later in fix_tick_ready. */
2869 && !bitmap_bit_p (&processed, INSN_LUID (next)))
2871 bitmap_set_bit (&processed, INSN_LUID (next));
2874 if (tick < MIN_TICK)
2877 if (tick > INTER_TICK (next))
2878 INTER_TICK (next) = tick;
2880 tick = INTER_TICK (next);
2882 INSN_TICK (next) = tick;
2887 bitmap_clear (&processed);
2890 /* Check if NEXT is ready to be added to the ready or queue list.
2891 If "yes", add it to the proper list.
2893 -1 - is not ready yet,
2894 0 - added to the ready list,
2895 0 < N - queued for N cycles. */
2897 try_ready (rtx next)
2901 ts = &TODO_SPEC (next);
2904 gcc_assert (!(old_ts & ~(SPECULATIVE | HARD_DEP))
2905 && ((old_ts & HARD_DEP)
2906 || (old_ts & SPECULATIVE)));
2908 if (sd_lists_empty_p (next, SD_LIST_BACK))
2909 /* NEXT has all its dependencies resolved. */
2911 /* Remove HARD_DEP bit from NEXT's status. */
2914 if (current_sched_info->flags & DO_SPECULATION)
2915 /* Remove all speculative bits from NEXT's status. */
2916 *ts &= ~SPECULATIVE;
2920 /* One of the NEXT's dependencies has been resolved.
2921 Recalcute NEXT's status. */
2923 *ts &= ~SPECULATIVE & ~HARD_DEP;
2925 if (sd_lists_empty_p (next, SD_LIST_HARD_BACK))
2926 /* Now we've got NEXT with speculative deps only.
2927 1. Look at the deps to see what we have to do.
2928 2. Check if we can do 'todo'. */
2930 sd_iterator_def sd_it;
2932 bool first_p = true;
2934 FOR_EACH_DEP (next, SD_LIST_BACK, sd_it, dep)
2936 ds_t ds = DEP_STATUS (dep) & SPECULATIVE;
2945 *ts = ds_merge (*ts, ds);
2948 if (dep_weak (*ts) < spec_info->weakness_cutoff)
2949 /* Too few points. */
2950 *ts = (*ts & ~SPECULATIVE) | HARD_DEP;
2957 gcc_assert (*ts == old_ts
2958 && QUEUE_INDEX (next) == QUEUE_NOWHERE);
2959 else if (current_sched_info->new_ready)
2960 *ts = current_sched_info->new_ready (next, *ts);
2962 /* * if !(old_ts & SPECULATIVE) (e.g. HARD_DEP or 0), then insn might
2963 have its original pattern or changed (speculative) one. This is due
2964 to changing ebb in region scheduling.
2965 * But if (old_ts & SPECULATIVE), then we are pretty sure that insn
2966 has speculative pattern.
2968 We can't assert (!(*ts & HARD_DEP) || *ts == old_ts) here because
2969 control-speculative NEXT could have been discarded by sched-rgn.c
2970 (the same case as when discarded by can_schedule_ready_p ()). */
2972 if ((*ts & SPECULATIVE)
2973 /* If (old_ts == *ts), then (old_ts & SPECULATIVE) and we don't
2974 need to change anything. */
2980 gcc_assert ((*ts & SPECULATIVE) && !(*ts & ~SPECULATIVE));
2982 res = speculate_insn (next, *ts, &new_pat);
2987 /* It would be nice to change DEP_STATUS of all dependences,
2988 which have ((DEP_STATUS & SPECULATIVE) == *ts) to HARD_DEP,
2989 so we won't reanalyze anything. */
2990 *ts = (*ts & ~SPECULATIVE) | HARD_DEP;
2994 /* We follow the rule, that every speculative insn
2995 has non-null ORIG_PAT. */
2996 if (!ORIG_PAT (next))
2997 ORIG_PAT (next) = PATTERN (next);
3001 if (!ORIG_PAT (next))
3002 /* If we gonna to overwrite the original pattern of insn,
3004 ORIG_PAT (next) = PATTERN (next);
3006 change_pattern (next, new_pat);
3014 /* We need to restore pattern only if (*ts == 0), because otherwise it is
3015 either correct (*ts & SPECULATIVE),
3016 or we simply don't care (*ts & HARD_DEP). */
3018 gcc_assert (!ORIG_PAT (next)
3019 || !IS_SPECULATION_BRANCHY_CHECK_P (next));
3023 /* We can't assert (QUEUE_INDEX (next) == QUEUE_NOWHERE) here because
3024 control-speculative NEXT could have been discarded by sched-rgn.c
3025 (the same case as when discarded by can_schedule_ready_p ()). */
3026 /*gcc_assert (QUEUE_INDEX (next) == QUEUE_NOWHERE);*/
3028 change_queue_index (next, QUEUE_NOWHERE);
3031 else if (!(*ts & BEGIN_SPEC) && ORIG_PAT (next) && !IS_SPECULATION_CHECK_P (next))
3032 /* We should change pattern of every previously speculative
3033 instruction - and we determine if NEXT was speculative by using
3034 ORIG_PAT field. Except one case - speculation checks have ORIG_PAT
3035 pat too, so skip them. */
3037 change_pattern (next, ORIG_PAT (next));
3038 ORIG_PAT (next) = 0;
3041 if (sched_verbose >= 2)
3043 int s = TODO_SPEC (next);
3045 fprintf (sched_dump, ";;\t\tdependencies resolved: insn %s",
3046 (*current_sched_info->print_insn) (next, 0));
3048 if (spec_info && spec_info->dump)
3051 fprintf (spec_info->dump, "; data-spec;");
3052 if (s & BEGIN_CONTROL)
3053 fprintf (spec_info->dump, "; control-spec;");
3054 if (s & BE_IN_CONTROL)
3055 fprintf (spec_info->dump, "; in-control-spec;");
3058 fprintf (sched_dump, "\n");
3061 adjust_priority (next);
3063 return fix_tick_ready (next);
3066 /* Calculate INSN_TICK of NEXT and add it to either ready or queue list. */
3068 fix_tick_ready (rtx next)
3072 if (!sd_lists_empty_p (next, SD_LIST_RES_BACK))
3075 sd_iterator_def sd_it;
3078 tick = INSN_TICK (next);
3079 /* if tick is not equal to INVALID_TICK, then update
3080 INSN_TICK of NEXT with the most recent resolved dependence
3081 cost. Otherwise, recalculate from scratch. */
3082 full_p = (tick == INVALID_TICK);
3084 FOR_EACH_DEP (next, SD_LIST_RES_BACK, sd_it, dep)
3086 rtx pro = DEP_PRO (dep);
3089 gcc_assert (INSN_TICK (pro) >= MIN_TICK);
3091 tick1 = INSN_TICK (pro) + dep_cost (dep);
3102 INSN_TICK (next) = tick;
3104 delay = tick - clock_var;
3106 delay = QUEUE_READY;
3108 change_queue_index (next, delay);
3113 /* Move NEXT to the proper queue list with (DELAY >= 1),
3114 or add it to the ready list (DELAY == QUEUE_READY),
3115 or remove it from ready and queue lists at all (DELAY == QUEUE_NOWHERE). */
3117 change_queue_index (rtx next, int delay)
3119 int i = QUEUE_INDEX (next);
3121 gcc_assert (QUEUE_NOWHERE <= delay && delay <= max_insn_queue_index
3123 gcc_assert (i != QUEUE_SCHEDULED);
3125 if ((delay > 0 && NEXT_Q_AFTER (q_ptr, delay) == i)
3126 || (delay < 0 && delay == i))
3127 /* We have nothing to do. */
3130 /* Remove NEXT from wherever it is now. */
3131 if (i == QUEUE_READY)
3132 ready_remove_insn (next);
3134 queue_remove (next);
3136 /* Add it to the proper place. */
3137 if (delay == QUEUE_READY)
3138 ready_add (readyp, next, false);
3139 else if (delay >= 1)
3140 queue_insn (next, delay);
3142 if (sched_verbose >= 2)
3144 fprintf (sched_dump, ";;\t\ttick updated: insn %s",
3145 (*current_sched_info->print_insn) (next, 0));
3147 if (delay == QUEUE_READY)
3148 fprintf (sched_dump, " into ready\n");
3149 else if (delay >= 1)
3150 fprintf (sched_dump, " into queue with cost=%d\n", delay);
3152 fprintf (sched_dump, " removed from ready or queue lists\n");
3156 /* Extend H_I_D data. */
3160 /* We use LUID 0 for the fake insn (UID 0) which holds dependencies for
3161 pseudos which do not cross calls. */
3162 int new_max_uid = get_max_uid () + 1;
3164 h_i_d = xrecalloc (h_i_d, new_max_uid, old_max_uid, sizeof (*h_i_d));
3165 old_max_uid = new_max_uid;
3167 if (targetm.sched.h_i_d_extended)
3168 targetm.sched.h_i_d_extended ();
3171 /* Extend READY, READY_TRY and CHOICE_STACK arrays.
3172 N_NEW_INSNS is the number of additional elements to allocate. */
3174 extend_ready (int n_new_insns)
3178 readyp->veclen = rgn_n_insns + n_new_insns + 1 + issue_rate;
3179 readyp->vec = XRESIZEVEC (rtx, readyp->vec, readyp->veclen);
3181 ready_try = xrecalloc (ready_try, rgn_n_insns + n_new_insns + 1,
3182 rgn_n_insns + 1, sizeof (char));
3184 rgn_n_insns += n_new_insns;
3186 choice_stack = XRESIZEVEC (struct choice_entry, choice_stack,
3189 for (i = rgn_n_insns; n_new_insns--; i--)
3190 choice_stack[i].state = xmalloc (dfa_state_size);
3193 /* Extend global scheduler structures (those, that live across calls to
3194 schedule_block) to include information about just emitted INSN. */
3196 extend_global (rtx insn)
3198 gcc_assert (INSN_P (insn));
3200 /* These structures have scheduler scope. */
3206 /* Init data handled in sched-deps.c. */
3207 sd_init_insn (insn);
3209 /* Extend dependency caches by one element. */
3210 extend_dependency_caches (1, false);
3213 /* Extends global and local scheduler structures to include information
3214 about just emitted INSN. */
3216 extend_all (rtx insn)
3218 extend_global (insn);
3220 /* These structures have block scope. */
3223 (*current_sched_info->add_remove_insn) (insn, 0);
3226 /* Initialize h_i_d entry of the new INSN with default values.
3227 Values, that are not explicitly initialized here, hold zero. */
3229 init_h_i_d (rtx insn)
3231 INSN_LUID (insn) = luid++;
3232 INSN_COST (insn) = -1;
3233 TODO_SPEC (insn) = HARD_DEP;
3234 QUEUE_INDEX (insn) = QUEUE_NOWHERE;
3235 INSN_TICK (insn) = INVALID_TICK;
3236 INTER_TICK (insn) = INVALID_TICK;
3237 find_insn_reg_weight1 (insn);
3240 /* Generates recovery code for INSN. */
3242 generate_recovery_code (rtx insn)
3244 if (TODO_SPEC (insn) & BEGIN_SPEC)
3245 begin_speculative_block (insn);
3247 /* Here we have insn with no dependencies to
3248 instructions other then CHECK_SPEC ones. */
3250 if (TODO_SPEC (insn) & BE_IN_SPEC)
3251 add_to_speculative_block (insn);
3255 Tries to add speculative dependencies of type FS between instructions
3256 in deps_list L and TWIN. */
3258 process_insn_forw_deps_be_in_spec (rtx insn, rtx twin, ds_t fs)
3260 sd_iterator_def sd_it;
3263 FOR_EACH_DEP (insn, SD_LIST_FORW, sd_it, dep)
3268 consumer = DEP_CON (dep);
3270 ds = DEP_STATUS (dep);
3272 if (/* If we want to create speculative dep. */
3274 /* And we can do that because this is a true dep. */
3275 && (ds & DEP_TYPES) == DEP_TRUE)
3277 gcc_assert (!(ds & BE_IN_SPEC));
3279 if (/* If this dep can be overcome with 'begin speculation'. */
3281 /* Then we have a choice: keep the dep 'begin speculative'
3282 or transform it into 'be in speculative'. */
3284 if (/* In try_ready we assert that if insn once became ready
3285 it can be removed from the ready (or queue) list only
3286 due to backend decision. Hence we can't let the
3287 probability of the speculative dep to decrease. */
3288 dep_weak (ds) <= dep_weak (fs))
3289 /* Transform it to be in speculative. */
3290 ds = (ds & ~BEGIN_SPEC) | fs;
3293 /* Mark the dep as 'be in speculative'. */
3298 dep_def _new_dep, *new_dep = &_new_dep;
3300 init_dep_1 (new_dep, twin, consumer, DEP_TYPE (dep), ds);
3301 sd_add_dep (new_dep, false);
3306 /* Generates recovery code for BEGIN speculative INSN. */
3308 begin_speculative_block (rtx insn)
3310 if (TODO_SPEC (insn) & BEGIN_DATA)
3312 if (TODO_SPEC (insn) & BEGIN_CONTROL)
3315 create_check_block_twin (insn, false);
3317 TODO_SPEC (insn) &= ~BEGIN_SPEC;
3320 /* Generates recovery code for BE_IN speculative INSN. */
3322 add_to_speculative_block (rtx insn)
3325 sd_iterator_def sd_it;
3328 rtx_vec_t priorities_roots;
3330 ts = TODO_SPEC (insn);
3331 gcc_assert (!(ts & ~BE_IN_SPEC));
3333 if (ts & BE_IN_DATA)
3335 if (ts & BE_IN_CONTROL)
3338 TODO_SPEC (insn) &= ~BE_IN_SPEC;
3339 gcc_assert (!TODO_SPEC (insn));
3341 DONE_SPEC (insn) |= ts;
3343 /* First we convert all simple checks to branchy. */
3344 for (sd_it = sd_iterator_start (insn, SD_LIST_SPEC_BACK);
3345 sd_iterator_cond (&sd_it, &dep);)
3347 rtx check = DEP_PRO (dep);
3349 if (IS_SPECULATION_SIMPLE_CHECK_P (check))
3351 create_check_block_twin (check, true);
3353 /* Restart search. */
3354 sd_it = sd_iterator_start (insn, SD_LIST_SPEC_BACK);
3357 /* Continue search. */
3358 sd_iterator_next (&sd_it);
3361 priorities_roots = NULL;
3362 clear_priorities (insn, &priorities_roots);
3369 /* Get the first backward dependency of INSN. */
3370 sd_it = sd_iterator_start (insn, SD_LIST_SPEC_BACK);
3371 if (!sd_iterator_cond (&sd_it, &dep))
3372 /* INSN has no backward dependencies left. */
3375 gcc_assert ((DEP_STATUS (dep) & BEGIN_SPEC) == 0
3376 && (DEP_STATUS (dep) & BE_IN_SPEC) != 0
3377 && (DEP_STATUS (dep) & DEP_TYPES) == DEP_TRUE);
3379 check = DEP_PRO (dep);
3381 gcc_assert (!IS_SPECULATION_CHECK_P (check) && !ORIG_PAT (check)
3382 && QUEUE_INDEX (check) == QUEUE_NOWHERE);
3384 rec = BLOCK_FOR_INSN (check);
3386 twin = emit_insn_before (copy_insn (PATTERN (insn)), BB_END (rec));
3387 extend_global (twin);
3389 sd_copy_back_deps (twin, insn, true);
3391 if (sched_verbose && spec_info->dump)
3392 /* INSN_BB (insn) isn't determined for twin insns yet.
3393 So we can't use current_sched_info->print_insn. */
3394 fprintf (spec_info->dump, ";;\t\tGenerated twin insn : %d/rec%d\n",
3395 INSN_UID (twin), rec->index);
3397 twins = alloc_INSN_LIST (twin, twins);
3399 /* Add dependences between TWIN and all appropriate
3400 instructions from REC. */
3401 FOR_EACH_DEP (insn, SD_LIST_SPEC_BACK, sd_it, dep)
3403 rtx pro = DEP_PRO (dep);
3405 gcc_assert (DEP_TYPE (dep) == REG_DEP_TRUE);
3407 /* INSN might have dependencies from the instructions from
3408 several recovery blocks. At this iteration we process those
3409 producers that reside in REC. */
3410 if (BLOCK_FOR_INSN (pro) == rec)
3412 dep_def _new_dep, *new_dep = &_new_dep;
3414 init_dep (new_dep, pro, twin, REG_DEP_TRUE);
3415 sd_add_dep (new_dep, false);
3419 process_insn_forw_deps_be_in_spec (insn, twin, ts);
3421 /* Remove all dependencies between INSN and insns in REC. */
3422 for (sd_it = sd_iterator_start (insn, SD_LIST_SPEC_BACK);
3423 sd_iterator_cond (&sd_it, &dep);)
3425 rtx pro = DEP_PRO (dep);
3427 if (BLOCK_FOR_INSN (pro) == rec)
3428 sd_delete_dep (sd_it);
3430 sd_iterator_next (&sd_it);
3434 /* We couldn't have added the dependencies between INSN and TWINS earlier
3435 because that would make TWINS appear in the INSN_BACK_DEPS (INSN). */
3440 twin = XEXP (twins, 0);
3443 dep_def _new_dep, *new_dep = &_new_dep;
3445 init_dep (new_dep, insn, twin, REG_DEP_OUTPUT);
3446 sd_add_dep (new_dep, false);
3449 twin = XEXP (twins, 1);
3450 free_INSN_LIST_node (twins);
3454 calc_priorities (priorities_roots);
3455 VEC_free (rtx, heap, priorities_roots);
3458 /* Extends and fills with zeros (only the new part) array pointed to by P. */
3460 xrecalloc (void *p, size_t new_nmemb, size_t old_nmemb, size_t size)
3462 gcc_assert (new_nmemb >= old_nmemb);
3463 p = XRESIZEVAR (void, p, new_nmemb * size);
3464 memset (((char *) p) + old_nmemb * size, 0, (new_nmemb - old_nmemb) * size);
3468 /* Return the probability of speculation success for the speculation
3476 dt = FIRST_SPEC_TYPE;
3481 res *= (ds_t) get_dep_weak (ds, dt);
3485 if (dt == LAST_SPEC_TYPE)
3487 dt <<= SPEC_TYPE_SHIFT;
3493 res /= MAX_DEP_WEAK;
3495 if (res < MIN_DEP_WEAK)
3498 gcc_assert (res <= MAX_DEP_WEAK);
3504 Find fallthru edge from PRED. */
3506 find_fallthru_edge (basic_block pred)
3512 succ = pred->next_bb;
3513 gcc_assert (succ->prev_bb == pred);
3515 if (EDGE_COUNT (pred->succs) <= EDGE_COUNT (succ->preds))
3517 FOR_EACH_EDGE (e, ei, pred->succs)
3518 if (e->flags & EDGE_FALLTHRU)
3520 gcc_assert (e->dest == succ);
3526 FOR_EACH_EDGE (e, ei, succ->preds)
3527 if (e->flags & EDGE_FALLTHRU)
3529 gcc_assert (e->src == pred);
3537 /* Initialize BEFORE_RECOVERY variable. */
3539 init_before_recovery (void)
3544 last = EXIT_BLOCK_PTR->prev_bb;
3545 e = find_fallthru_edge (last);
3549 /* We create two basic blocks:
3550 1. Single instruction block is inserted right after E->SRC
3552 2. Empty block right before EXIT_BLOCK.
3553 Between these two blocks recovery blocks will be emitted. */
3555 basic_block single, empty;
3558 single = create_empty_bb (last);
3559 empty = create_empty_bb (single);
3561 single->count = last->count;
3562 empty->count = last->count;
3563 single->frequency = last->frequency;
3564 empty->frequency = last->frequency;
3565 BB_COPY_PARTITION (single, last);
3566 BB_COPY_PARTITION (empty, last);
3568 redirect_edge_succ (e, single);
3569 make_single_succ_edge (single, empty, 0);
3570 make_single_succ_edge (empty, EXIT_BLOCK_PTR,
3571 EDGE_FALLTHRU | EDGE_CAN_FALLTHRU);
3573 label = block_label (empty);
3574 x = emit_jump_insn_after (gen_jump (label), BB_END (single));
3575 JUMP_LABEL (x) = label;
3576 LABEL_NUSES (label)++;
3579 emit_barrier_after (x);
3581 add_block (empty, 0);
3582 add_block (single, 0);
3584 before_recovery = single;
3586 if (sched_verbose >= 2 && spec_info->dump)
3587 fprintf (spec_info->dump,
3588 ";;\t\tFixed fallthru to EXIT : %d->>%d->%d->>EXIT\n",
3589 last->index, single->index, empty->index);
3592 before_recovery = last;
3595 /* Returns new recovery block. */
3597 create_recovery_block (void)
3603 haifa_recovery_bb_recently_added_p = true;
3604 haifa_recovery_bb_ever_added_p = true;
3606 if (!before_recovery)
3607 init_before_recovery ();
3609 barrier = get_last_bb_insn (before_recovery);
3610 gcc_assert (BARRIER_P (barrier));
3612 label = emit_label_after (gen_label_rtx (), barrier);
3614 rec = create_basic_block (label, label, before_recovery);
3616 /* Recovery block always end with an unconditional jump. */
3617 emit_barrier_after (BB_END (rec));
3619 if (BB_PARTITION (before_recovery) != BB_UNPARTITIONED)
3620 BB_SET_PARTITION (rec, BB_COLD_PARTITION);
3622 if (sched_verbose && spec_info->dump)
3623 fprintf (spec_info->dump, ";;\t\tGenerated recovery block rec%d\n",
3626 before_recovery = rec;
3631 /* This function creates recovery code for INSN. If MUTATE_P is nonzero,
3632 INSN is a simple check, that should be converted to branchy one. */
3634 create_check_block_twin (rtx insn, bool mutate_p)
3637 rtx label, check, twin;
3639 sd_iterator_def sd_it;
3641 dep_def _new_dep, *new_dep = &_new_dep;
3643 gcc_assert (ORIG_PAT (insn)
3645 || (IS_SPECULATION_SIMPLE_CHECK_P (insn)
3646 && !(TODO_SPEC (insn) & SPECULATIVE))));
3648 /* Create recovery block. */
3649 if (mutate_p || targetm.sched.needs_block_p (insn))
3651 rec = create_recovery_block ();
3652 label = BB_HEAD (rec);
3656 rec = EXIT_BLOCK_PTR;
3661 check = targetm.sched.gen_check (insn, label, mutate_p);
3663 if (rec != EXIT_BLOCK_PTR)
3665 /* To have mem_reg alive at the beginning of second_bb,
3666 we emit check BEFORE insn, so insn after splitting
3667 insn will be at the beginning of second_bb, which will
3668 provide us with the correct life information. */
3669 check = emit_jump_insn_before (check, insn);
3670 JUMP_LABEL (check) = label;
3671 LABEL_NUSES (label)++;
3674 check = emit_insn_before (check, insn);
3676 /* Extend data structures. */
3678 RECOVERY_BLOCK (check) = rec;
3680 if (sched_verbose && spec_info->dump)
3681 fprintf (spec_info->dump, ";;\t\tGenerated check insn : %s\n",
3682 (*current_sched_info->print_insn) (check, 0));
3684 gcc_assert (ORIG_PAT (insn));
3686 /* Initialize TWIN (twin is a duplicate of original instruction
3687 in the recovery block). */
3688 if (rec != EXIT_BLOCK_PTR)
3690 sd_iterator_def sd_it;
3693 FOR_EACH_DEP (insn, SD_LIST_RES_BACK, sd_it, dep)
3694 if ((DEP_STATUS (dep) & DEP_OUTPUT) != 0)
3696 struct _dep _dep2, *dep2 = &_dep2;
3698 init_dep (dep2, DEP_PRO (dep), check, REG_DEP_TRUE);
3700 sd_add_dep (dep2, true);
3703 twin = emit_insn_after (ORIG_PAT (insn), BB_END (rec));
3704 extend_global (twin);
3706 if (sched_verbose && spec_info->dump)
3707 /* INSN_BB (insn) isn't determined for twin insns yet.
3708 So we can't use current_sched_info->print_insn. */
3709 fprintf (spec_info->dump, ";;\t\tGenerated twin insn : %d/rec%d\n",
3710 INSN_UID (twin), rec->index);
3714 ORIG_PAT (check) = ORIG_PAT (insn);
3715 HAS_INTERNAL_DEP (check) = 1;
3717 /* ??? We probably should change all OUTPUT dependencies to
3721 /* Copy all resolved back dependencies of INSN to TWIN. This will
3722 provide correct value for INSN_TICK (TWIN). */
3723 sd_copy_back_deps (twin, insn, true);
3725 if (rec != EXIT_BLOCK_PTR)
3726 /* In case of branchy check, fix CFG. */
3728 basic_block first_bb, second_bb;
3733 first_bb = BLOCK_FOR_INSN (check);
3734 e = split_block (first_bb, check);
3735 /* split_block emits note if *check == BB_END. Probably it
3736 is better to rip that note off. */
3737 gcc_assert (e->src == first_bb);
3738 second_bb = e->dest;
3740 /* This is fixing of incoming edge. */
3741 /* ??? Which other flags should be specified? */
3742 if (BB_PARTITION (first_bb) != BB_PARTITION (rec))
3743 /* Partition type is the same, if it is "unpartitioned". */
3744 edge_flags = EDGE_CROSSING;
3748 e = make_edge (first_bb, rec, edge_flags);
3750 add_block (second_bb, first_bb);
3752 gcc_assert (NOTE_INSN_BASIC_BLOCK_P (BB_HEAD (second_bb)));
3753 label = block_label (second_bb);
3754 jump = emit_jump_insn_after (gen_jump (label), BB_END (rec));
3755 JUMP_LABEL (jump) = label;
3756 LABEL_NUSES (label)++;
3757 extend_global (jump);
3759 if (BB_PARTITION (second_bb) != BB_PARTITION (rec))
3760 /* Partition type is the same, if it is "unpartitioned". */
3762 /* Rewritten from cfgrtl.c. */
3763 if (flag_reorder_blocks_and_partition
3764 && targetm.have_named_sections
3765 /*&& !any_condjump_p (jump)*/)
3766 /* any_condjump_p (jump) == false.
3767 We don't need the same note for the check because
3768 any_condjump_p (check) == true. */
3770 REG_NOTES (jump) = gen_rtx_EXPR_LIST (REG_CROSSING_JUMP,
3774 edge_flags = EDGE_CROSSING;
3779 make_single_succ_edge (rec, second_bb, edge_flags);
3781 add_block (rec, EXIT_BLOCK_PTR);
3784 /* Move backward dependences from INSN to CHECK and
3785 move forward dependences from INSN to TWIN. */
3787 /* First, create dependencies between INSN's producers and CHECK & TWIN. */
3788 FOR_EACH_DEP (insn, SD_LIST_BACK, sd_it, dep)
3790 rtx pro = DEP_PRO (dep);
3793 /* If BEGIN_DATA: [insn ~~TRUE~~> producer]:
3794 check --TRUE--> producer ??? or ANTI ???
3795 twin --TRUE--> producer
3796 twin --ANTI--> check
3798 If BEGIN_CONTROL: [insn ~~ANTI~~> producer]:
3799 check --ANTI--> producer
3800 twin --ANTI--> producer
3801 twin --ANTI--> check
3803 If BE_IN_SPEC: [insn ~~TRUE~~> producer]:
3804 check ~~TRUE~~> producer
3805 twin ~~TRUE~~> producer
3806 twin --ANTI--> check */
3808 ds = DEP_STATUS (dep);
3810 if (ds & BEGIN_SPEC)
3812 gcc_assert (!mutate_p);
3816 init_dep_1 (new_dep, pro, check, DEP_TYPE (dep), ds);
3817 sd_add_dep (new_dep, false);
3819 if (rec != EXIT_BLOCK_PTR)
3821 DEP_CON (new_dep) = twin;
3822 sd_add_dep (new_dep, false);
3826 /* Second, remove backward dependencies of INSN. */
3827 for (sd_it = sd_iterator_start (insn, SD_LIST_SPEC_BACK);
3828 sd_iterator_cond (&sd_it, &dep);)
3830 if ((DEP_STATUS (dep) & BEGIN_SPEC)
3832 /* We can delete this dep because we overcome it with
3833 BEGIN_SPECULATION. */
3834 sd_delete_dep (sd_it);
3836 sd_iterator_next (&sd_it);
3839 /* Future Speculations. Determine what BE_IN speculations will be like. */
3842 /* Fields (DONE_SPEC (x) & BEGIN_SPEC) and CHECK_SPEC (x) are set only
3845 gcc_assert (!DONE_SPEC (insn));
3849 ds_t ts = TODO_SPEC (insn);
3851 DONE_SPEC (insn) = ts & BEGIN_SPEC;
3852 CHECK_SPEC (check) = ts & BEGIN_SPEC;
3854 /* Luckyness of future speculations solely depends upon initial
3855 BEGIN speculation. */
3856 if (ts & BEGIN_DATA)
3857 fs = set_dep_weak (fs, BE_IN_DATA, get_dep_weak (ts, BEGIN_DATA));
3858 if (ts & BEGIN_CONTROL)
3859 fs = set_dep_weak (fs, BE_IN_CONTROL,
3860 get_dep_weak (ts, BEGIN_CONTROL));
3863 CHECK_SPEC (check) = CHECK_SPEC (insn);
3865 /* Future speculations: call the helper. */
3866 process_insn_forw_deps_be_in_spec (insn, twin, fs);
3868 if (rec != EXIT_BLOCK_PTR)
3870 /* Which types of dependencies should we use here is,
3871 generally, machine-dependent question... But, for now,
3876 init_dep (new_dep, insn, check, REG_DEP_TRUE);
3877 sd_add_dep (new_dep, false);
3879 init_dep (new_dep, insn, twin, REG_DEP_OUTPUT);
3880 sd_add_dep (new_dep, false);
3884 if (spec_info->dump)
3885 fprintf (spec_info->dump, ";;\t\tRemoved simple check : %s\n",
3886 (*current_sched_info->print_insn) (insn, 0));
3888 /* Remove all dependencies of the INSN. */
3890 sd_it = sd_iterator_start (insn, (SD_LIST_FORW
3892 | SD_LIST_RES_BACK));
3893 while (sd_iterator_cond (&sd_it, &dep))
3894 sd_delete_dep (sd_it);
3897 /* If former check (INSN) already was moved to the ready (or queue)
3898 list, add new check (CHECK) there too. */
3899 if (QUEUE_INDEX (insn) != QUEUE_NOWHERE)
3902 /* Remove old check from instruction stream and free its
3904 sched_remove_insn (insn);
3907 init_dep (new_dep, check, twin, REG_DEP_ANTI);
3908 sd_add_dep (new_dep, false);
3912 init_dep_1 (new_dep, insn, check, REG_DEP_TRUE, DEP_TRUE | DEP_OUTPUT);
3913 sd_add_dep (new_dep, false);
3917 /* Fix priorities. If MUTATE_P is nonzero, this is not necessary,
3918 because it'll be done later in add_to_speculative_block. */
3920 rtx_vec_t priorities_roots = NULL;
3922 clear_priorities (twin, &priorities_roots);
3923 calc_priorities (priorities_roots);
3924 VEC_free (rtx, heap, priorities_roots);
3928 /* Removes dependency between instructions in the recovery block REC
3929 and usual region instructions. It keeps inner dependences so it
3930 won't be necessary to recompute them. */
3932 fix_recovery_deps (basic_block rec)
3934 rtx note, insn, jump, ready_list = 0;
3935 bitmap_head in_ready;
3938 bitmap_initialize (&in_ready, 0);
3940 /* NOTE - a basic block note. */
3941 note = NEXT_INSN (BB_HEAD (rec));
3942 gcc_assert (NOTE_INSN_BASIC_BLOCK_P (note));
3943 insn = BB_END (rec);
3944 gcc_assert (JUMP_P (insn));
3945 insn = PREV_INSN (insn);
3949 sd_iterator_def sd_it;
3952 for (sd_it = sd_iterator_start (insn, SD_LIST_FORW);
3953 sd_iterator_cond (&sd_it, &dep);)
3955 rtx consumer = DEP_CON (dep);
3957 if (BLOCK_FOR_INSN (consumer) != rec)
3959 sd_delete_dep (sd_it);
3961 if (!bitmap_bit_p (&in_ready, INSN_LUID (consumer)))
3963 ready_list = alloc_INSN_LIST (consumer, ready_list);
3964 bitmap_set_bit (&in_ready, INSN_LUID (consumer));
3969 gcc_assert ((DEP_STATUS (dep) & DEP_TYPES) == DEP_TRUE);
3971 sd_iterator_next (&sd_it);
3975 insn = PREV_INSN (insn);
3977 while (insn != note);
3979 bitmap_clear (&in_ready);
3981 /* Try to add instructions to the ready or queue list. */
3982 for (link = ready_list; link; link = XEXP (link, 1))
3983 try_ready (XEXP (link, 0));
3984 free_INSN_LIST_list (&ready_list);
3986 /* Fixing jump's dependences. */
3987 insn = BB_HEAD (rec);
3988 jump = BB_END (rec);
3990 gcc_assert (LABEL_P (insn));
3991 insn = NEXT_INSN (insn);
3993 gcc_assert (NOTE_INSN_BASIC_BLOCK_P (insn));
3994 add_jump_dependencies (insn, jump);
3997 /* Changes pattern of the INSN to NEW_PAT. */
3999 change_pattern (rtx insn, rtx new_pat)
4003 t = validate_change (insn, &PATTERN (insn), new_pat, 0);
4005 /* Invalidate INSN_COST, so it'll be recalculated. */
4006 INSN_COST (insn) = -1;
4007 /* Invalidate INSN_TICK, so it'll be recalculated. */
4008 INSN_TICK (insn) = INVALID_TICK;
4009 dfa_clear_single_insn_cache (insn);
4012 /* Return true if INSN can potentially be speculated with type DS. */
4014 sched_insn_is_legitimate_for_speculation_p (rtx insn, ds_t ds)
4016 if (HAS_INTERNAL_DEP (insn))
4019 if (!NONJUMP_INSN_P (insn))
4022 if (SCHED_GROUP_P (insn))
4025 if (IS_SPECULATION_CHECK_P (insn))
4028 if (side_effects_p (PATTERN (insn)))
4031 if ((ds & BE_IN_SPEC)
4032 && may_trap_p (PATTERN (insn)))
4038 /* -1 - can't speculate,
4039 0 - for speculation with REQUEST mode it is OK to use
4040 current instruction pattern,
4041 1 - need to change pattern for *NEW_PAT to be speculative. */
4043 speculate_insn (rtx insn, ds_t request, rtx *new_pat)
4045 gcc_assert (current_sched_info->flags & DO_SPECULATION
4046 && (request & SPECULATIVE)
4047 && sched_insn_is_legitimate_for_speculation_p (insn, request));
4049 if ((request & spec_info->mask) != request)
4052 if (request & BE_IN_SPEC
4053 && !(request & BEGIN_SPEC))
4056 return targetm.sched.speculate_insn (insn, request & BEGIN_SPEC, new_pat);
4059 /* Print some information about block BB, which starts with HEAD and
4060 ends with TAIL, before scheduling it.
4061 I is zero, if scheduler is about to start with the fresh ebb. */
4063 dump_new_block_header (int i, basic_block bb, rtx head, rtx tail)
4066 fprintf (sched_dump,
4067 ";; ======================================================\n");
4069 fprintf (sched_dump,
4070 ";; =====================ADVANCING TO=====================\n");
4071 fprintf (sched_dump,
4072 ";; -- basic block %d from %d to %d -- %s reload\n",
4073 bb->index, INSN_UID (head), INSN_UID (tail),
4074 (reload_completed ? "after" : "before"));
4075 fprintf (sched_dump,
4076 ";; ======================================================\n");
4077 fprintf (sched_dump, "\n");
4080 /* Unlink basic block notes and labels and saves them, so they
4081 can be easily restored. We unlink basic block notes in EBB to
4082 provide back-compatibility with the previous code, as target backends
4083 assume, that there'll be only instructions between
4084 current_sched_info->{head and tail}. We restore these notes as soon
4086 FIRST (LAST) is the first (last) basic block in the ebb.
4087 NB: In usual case (FIRST == LAST) nothing is really done. */
4089 unlink_bb_notes (basic_block first, basic_block last)
4091 /* We DON'T unlink basic block notes of the first block in the ebb. */
4095 bb_header = xmalloc (last_basic_block * sizeof (*bb_header));
4097 /* Make a sentinel. */
4098 if (last->next_bb != EXIT_BLOCK_PTR)
4099 bb_header[last->next_bb->index] = 0;
4101 first = first->next_bb;
4104 rtx prev, label, note, next;
4106 label = BB_HEAD (last);
4107 if (LABEL_P (label))
4108 note = NEXT_INSN (label);
4111 gcc_assert (NOTE_INSN_BASIC_BLOCK_P (note));
4113 prev = PREV_INSN (label);
4114 next = NEXT_INSN (note);
4115 gcc_assert (prev && next);
4117 NEXT_INSN (prev) = next;
4118 PREV_INSN (next) = prev;
4120 bb_header[last->index] = label;
4125 last = last->prev_bb;
4130 /* Restore basic block notes.
4131 FIRST is the first basic block in the ebb. */
4133 restore_bb_notes (basic_block first)
4138 /* We DON'T unlink basic block notes of the first block in the ebb. */
4139 first = first->next_bb;
4140 /* Remember: FIRST is actually a second basic block in the ebb. */
4142 while (first != EXIT_BLOCK_PTR
4143 && bb_header[first->index])
4145 rtx prev, label, note, next;
4147 label = bb_header[first->index];
4148 prev = PREV_INSN (label);
4149 next = NEXT_INSN (prev);
4151 if (LABEL_P (label))
4152 note = NEXT_INSN (label);
4155 gcc_assert (NOTE_INSN_BASIC_BLOCK_P (note));
4157 bb_header[first->index] = 0;
4159 NEXT_INSN (prev) = label;
4160 NEXT_INSN (note) = next;
4161 PREV_INSN (next) = note;
4163 first = first->next_bb;
4170 /* Extend per basic block data structures of the scheduler.
4171 If BB is NULL, initialize structures for the whole CFG.
4172 Otherwise, initialize them for the just created BB. */
4178 old_last_basic_block = last_basic_block;
4180 /* The following is done to keep current_sched_info->next_tail non null. */
4182 insn = BB_END (EXIT_BLOCK_PTR->prev_bb);
4183 if (NEXT_INSN (insn) == 0
4186 /* Don't emit a NOTE if it would end up before a BARRIER. */
4187 && !BARRIER_P (NEXT_INSN (insn))))
4189 rtx note = emit_note_after (NOTE_INSN_DELETED, insn);
4190 /* Make insn appear outside BB. */
4191 set_block_for_insn (note, NULL);
4192 BB_END (EXIT_BLOCK_PTR->prev_bb) = insn;
4196 /* Add a basic block BB to extended basic block EBB.
4197 If EBB is EXIT_BLOCK_PTR, then BB is recovery block.
4198 If EBB is NULL, then BB should be a new region. */
4200 add_block (basic_block bb, basic_block ebb)
4202 gcc_assert (current_sched_info->flags & NEW_BBS);
4206 if (current_sched_info->add_block)
4207 /* This changes only data structures of the front-end. */
4208 current_sched_info->add_block (bb, ebb);
4212 Fix CFG after both in- and inter-block movement of
4213 control_flow_insn_p JUMP. */
4215 fix_jump_move (rtx jump)
4217 basic_block bb, jump_bb, jump_bb_next;
4219 bb = BLOCK_FOR_INSN (PREV_INSN (jump));
4220 jump_bb = BLOCK_FOR_INSN (jump);
4221 jump_bb_next = jump_bb->next_bb;
4223 gcc_assert (current_sched_info->flags & SCHED_EBB
4224 || IS_SPECULATION_BRANCHY_CHECK_P (jump));
4226 if (!NOTE_INSN_BASIC_BLOCK_P (BB_END (jump_bb_next)))
4227 /* if jump_bb_next is not empty. */
4228 BB_END (jump_bb) = BB_END (jump_bb_next);
4230 if (BB_END (bb) != PREV_INSN (jump))
4231 /* Then there are instruction after jump that should be placed
4233 BB_END (jump_bb_next) = BB_END (bb);
4235 /* Otherwise jump_bb_next is empty. */
4236 BB_END (jump_bb_next) = NEXT_INSN (BB_HEAD (jump_bb_next));
4238 /* To make assertion in move_insn happy. */
4239 BB_END (bb) = PREV_INSN (jump);
4241 update_bb_for_insn (jump_bb_next);
4244 /* Fix CFG after interblock movement of control_flow_insn_p JUMP. */
4246 move_block_after_check (rtx jump)
4248 basic_block bb, jump_bb, jump_bb_next;
4251 bb = BLOCK_FOR_INSN (PREV_INSN (jump));
4252 jump_bb = BLOCK_FOR_INSN (jump);
4253 jump_bb_next = jump_bb->next_bb;
4255 update_bb_for_insn (jump_bb);
4257 gcc_assert (IS_SPECULATION_CHECK_P (jump)
4258 || IS_SPECULATION_CHECK_P (BB_END (jump_bb_next)));
4260 unlink_block (jump_bb_next);
4261 link_block (jump_bb_next, bb);
4265 move_succs (&(jump_bb->succs), bb);
4266 move_succs (&(jump_bb_next->succs), jump_bb);
4267 move_succs (&t, jump_bb_next);
4269 df_mark_solutions_dirty ();
4271 if (current_sched_info->fix_recovery_cfg)
4272 current_sched_info->fix_recovery_cfg
4273 (bb->index, jump_bb->index, jump_bb_next->index);
4276 /* Helper function for move_block_after_check.
4277 This functions attaches edge vector pointed to by SUCCSP to
4280 move_succs (VEC(edge,gc) **succsp, basic_block to)
4285 gcc_assert (to->succs == 0);
4287 to->succs = *succsp;
4289 FOR_EACH_EDGE (e, ei, to->succs)
4295 /* Remove INSN from the instruction stream.
4296 INSN should have any dependencies. */
4298 sched_remove_insn (rtx insn)
4300 sd_finish_insn (insn);
4302 change_queue_index (insn, QUEUE_NOWHERE);
4303 current_sched_info->add_remove_insn (insn, 1);
4307 /* Clear priorities of all instructions, that are forward dependent on INSN.
4308 Store in vector pointed to by ROOTS_PTR insns on which priority () should
4309 be invoked to initialize all cleared priorities. */
4311 clear_priorities (rtx insn, rtx_vec_t *roots_ptr)
4313 sd_iterator_def sd_it;
4315 bool insn_is_root_p = true;
4317 gcc_assert (QUEUE_INDEX (insn) != QUEUE_SCHEDULED);
4319 FOR_EACH_DEP (insn, SD_LIST_BACK, sd_it, dep)
4321 rtx pro = DEP_PRO (dep);
4323 if (INSN_PRIORITY_STATUS (pro) >= 0
4324 && QUEUE_INDEX (insn) != QUEUE_SCHEDULED)
4326 /* If DEP doesn't contribute to priority then INSN itself should
4327 be added to priority roots. */
4328 if (contributes_to_priority_p (dep))
4329 insn_is_root_p = false;
4331 INSN_PRIORITY_STATUS (pro) = -1;
4332 clear_priorities (pro, roots_ptr);
4337 VEC_safe_push (rtx, heap, *roots_ptr, insn);
4340 /* Recompute priorities of instructions, whose priorities might have been
4341 changed. ROOTS is a vector of instructions whose priority computation will
4342 trigger initialization of all cleared priorities. */
4344 calc_priorities (rtx_vec_t roots)
4349 for (i = 0; VEC_iterate (rtx, roots, i, insn); i++)
4354 /* Add dependences between JUMP and other instructions in the recovery
4355 block. INSN is the first insn the recovery block. */
4357 add_jump_dependencies (rtx insn, rtx jump)
4361 insn = NEXT_INSN (insn);
4365 if (sd_lists_empty_p (insn, SD_LIST_FORW))
4367 dep_def _new_dep, *new_dep = &_new_dep;
4369 init_dep (new_dep, insn, jump, REG_DEP_ANTI);
4370 sd_add_dep (new_dep, false);
4375 gcc_assert (!sd_lists_empty_p (jump, SD_LIST_BACK));
4378 /* Return the NOTE_INSN_BASIC_BLOCK of BB. */
4380 bb_note (basic_block bb)
4384 note = BB_HEAD (bb);
4386 note = NEXT_INSN (note);
4388 gcc_assert (NOTE_INSN_BASIC_BLOCK_P (note));
4392 #ifdef ENABLE_CHECKING
4393 /* Helper function for check_cfg.
4394 Return nonzero, if edge vector pointed to by EL has edge with TYPE in
4397 has_edge_p (VEC(edge,gc) *el, int type)
4402 FOR_EACH_EDGE (e, ei, el)
4403 if (e->flags & type)
4408 /* Check few properties of CFG between HEAD and TAIL.
4409 If HEAD (TAIL) is NULL check from the beginning (till the end) of the
4410 instruction stream. */
4412 check_cfg (rtx head, rtx tail)
4416 int not_first = 0, not_last;
4419 head = get_insns ();
4421 tail = get_last_insn ();
4422 next_tail = NEXT_INSN (tail);
4426 not_last = head != tail;
4429 gcc_assert (NEXT_INSN (PREV_INSN (head)) == head);
4431 gcc_assert (PREV_INSN (NEXT_INSN (head)) == head);
4434 || (NOTE_INSN_BASIC_BLOCK_P (head)
4436 || (not_first && !LABEL_P (PREV_INSN (head))))))
4438 gcc_assert (bb == 0);
4439 bb = BLOCK_FOR_INSN (head);
4441 gcc_assert (BB_HEAD (bb) == head);
4443 /* This is the case of jump table. See inside_basic_block_p (). */
4444 gcc_assert (LABEL_P (head) && !inside_basic_block_p (head));
4449 gcc_assert (!inside_basic_block_p (head));
4450 head = NEXT_INSN (head);
4454 gcc_assert (inside_basic_block_p (head)
4456 gcc_assert (BLOCK_FOR_INSN (head) == bb);
4460 head = NEXT_INSN (head);
4461 gcc_assert (NOTE_INSN_BASIC_BLOCK_P (head));
4465 if (control_flow_insn_p (head))
4467 gcc_assert (BB_END (bb) == head);
4469 if (any_uncondjump_p (head))
4470 gcc_assert (EDGE_COUNT (bb->succs) == 1
4471 && BARRIER_P (NEXT_INSN (head)));
4472 else if (any_condjump_p (head))
4473 gcc_assert (/* Usual case. */
4474 (EDGE_COUNT (bb->succs) > 1
4475 && !BARRIER_P (NEXT_INSN (head)))
4476 /* Or jump to the next instruction. */
4477 || (EDGE_COUNT (bb->succs) == 1
4478 && (BB_HEAD (EDGE_I (bb->succs, 0)->dest)
4479 == JUMP_LABEL (head))));
4481 if (BB_END (bb) == head)
4483 if (EDGE_COUNT (bb->succs) > 1)
4484 gcc_assert (control_flow_insn_p (head)
4485 || has_edge_p (bb->succs, EDGE_COMPLEX));
4489 head = NEXT_INSN (head);
4495 while (head != next_tail);
4497 gcc_assert (bb == 0);
4500 /* Perform a few consistency checks of flags in different data structures. */
4502 check_sched_flags (void)
4504 unsigned int f = current_sched_info->flags;
4506 if (flag_sched_stalled_insns)
4507 gcc_assert (!(f & DO_SPECULATION));
4508 if (f & DO_SPECULATION)
4509 gcc_assert (!flag_sched_stalled_insns
4511 && spec_info->mask);
4513 #endif /* ENABLE_CHECKING */
4515 #endif /* INSN_SCHEDULING */