1 /* Instruction scheduling pass.
2 Copyright (C) 1992, 93-97, 1998 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com) Enhanced by,
4 and currently maintained by, Jim Wilson (wilson@cygnus.com)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful, but
14 WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to the Free
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 /* Instruction scheduling pass.
26 This pass implements list scheduling within basic blocks. It is
27 run twice: (1) after flow analysis, but before register allocation,
28 and (2) after register allocation.
30 The first run performs interblock scheduling, moving insns between
31 different blocks in the same "region", and the second runs only
32 basic block scheduling.
34 Interblock motions performed are useful motions and speculative
35 motions, including speculative loads. Motions requiring code
36 duplication are not supported. The identification of motion type
37 and the check for validity of speculative motions requires
38 construction and analysis of the function's control flow graph.
39 The scheduler works as follows:
41 We compute insn priorities based on data dependencies. Flow
42 analysis only creates a fraction of the data-dependencies we must
43 observe: namely, only those dependencies which the combiner can be
44 expected to use. For this pass, we must therefore create the
45 remaining dependencies we need to observe: register dependencies,
46 memory dependencies, dependencies to keep function calls in order,
47 and the dependence between a conditional branch and the setting of
48 condition codes are all dealt with here.
50 The scheduler first traverses the data flow graph, starting with
51 the last instruction, and proceeding to the first, assigning values
52 to insn_priority as it goes. This sorts the instructions
53 topologically by data dependence.
55 Once priorities have been established, we order the insns using
56 list scheduling. This works as follows: starting with a list of
57 all the ready insns, and sorted according to priority number, we
58 schedule the insn from the end of the list by placing its
59 predecessors in the list according to their priority order. We
60 consider this insn scheduled by setting the pointer to the "end" of
61 the list to point to the previous insn. When an insn has no
62 predecessors, we either queue it until sufficient time has elapsed
63 or add it to the ready list. As the instructions are scheduled or
64 when stalls are introduced, the queue advances and dumps insns into
65 the ready list. When all insns down to the lowest priority have
66 been scheduled, the critical path of the basic block has been made
67 as short as possible. The remaining insns are then scheduled in
70 Function unit conflicts are resolved during forward list scheduling
71 by tracking the time when each insn is committed to the schedule
72 and from that, the time the function units it uses must be free.
73 As insns on the ready list are considered for scheduling, those
74 that would result in a blockage of the already committed insns are
75 queued until no blockage will result.
77 The following list shows the order in which we want to break ties
78 among insns in the ready list:
80 1. choose insn with the longest path to end of bb, ties
82 2. choose insn with least contribution to register pressure,
84 3. prefer in-block upon interblock motion, ties broken by
85 4. prefer useful upon speculative motion, ties broken by
86 5. choose insn with largest control flow probability, ties
88 6. choose insn with the least dependences upon the previously
89 scheduled insn, or finally
90 7 choose the insn which has the most insns dependent on it.
91 8. choose insn with lowest UID.
93 Memory references complicate matters. Only if we can be certain
94 that memory references are not part of the data dependency graph
95 (via true, anti, or output dependence), can we move operations past
96 memory references. To first approximation, reads can be done
97 independently, while writes introduce dependencies. Better
98 approximations will yield fewer dependencies.
100 Before reload, an extended analysis of interblock data dependences
101 is required for interblock scheduling. This is performed in
102 compute_block_backward_dependences ().
104 Dependencies set up by memory references are treated in exactly the
105 same way as other dependencies, by using LOG_LINKS backward
106 dependences. LOG_LINKS are translated into INSN_DEPEND forward
107 dependences for the purpose of forward list scheduling.
109 Having optimized the critical path, we may have also unduly
110 extended the lifetimes of some registers. If an operation requires
111 that constants be loaded into registers, it is certainly desirable
112 to load those constants as early as necessary, but no earlier.
113 I.e., it will not do to load up a bunch of registers at the
114 beginning of a basic block only to use them at the end, if they
115 could be loaded later, since this may result in excessive register
118 Note that since branches are never in basic blocks, but only end
119 basic blocks, this pass will not move branches. But that is ok,
120 since we can use GNU's delayed branch scheduling pass to take care
123 Also note that no further optimizations based on algebraic
124 identities are performed, so this pass would be a good one to
125 perform instruction splitting, such as breaking up a multiply
126 instruction into shifts and adds where that is profitable.
128 Given the memory aliasing analysis that this pass should perform,
129 it should be possible to remove redundant stores to memory, and to
130 load values from registers instead of hitting memory.
132 Before reload, speculative insns are moved only if a 'proof' exists
133 that no exception will be caused by this, and if no live registers
134 exist that inhibit the motion (live registers constraints are not
135 represented by data dependence edges).
137 This pass must update information that subsequent passes expect to
138 be correct. Namely: reg_n_refs, reg_n_sets, reg_n_deaths,
139 reg_n_calls_crossed, and reg_live_length. Also, basic_block_head,
142 The information in the line number notes is carefully retained by
143 this pass. Notes that refer to the starting and ending of
144 exception regions are also carefully retained by this pass. All
145 other NOTE insns are grouped in their same relative order at the
146 beginning of basic blocks and regions that have been scheduled.
148 The main entry point for this pass is schedule_insns(), called for
149 each function. The work of the scheduler is organized in three
150 levels: (1) function level: insns are subject to splitting,
151 control-flow-graph is constructed, regions are computed (after
152 reload, each region is of one block), (2) region level: control
153 flow graph attributes required for interblock scheduling are
154 computed (dominators, reachability, etc.), data dependences and
155 priorities are computed, and (3) block level: insns in the block
156 are actually scheduled. */
161 #include "basic-block.h"
163 #include "hard-reg-set.h"
165 #include "insn-config.h"
166 #include "insn-attr.h"
170 extern char *reg_known_equiv_p;
171 extern rtx *reg_known_value;
173 #ifdef INSN_SCHEDULING
175 /* target_units bitmask has 1 for each unit in the cpu. It should be
176 possible to compute this variable from the machine description.
177 But currently it is computed by examinning the insn list. Since
178 this is only needed for visualization, it seems an acceptable
179 solution. (For understanding the mapping of bits to units, see
180 definition of function_units[] in "insn-attrtab.c") */
182 static int target_units = 0;
184 /* issue_rate is the number of insns that can be scheduled in the same
185 machine cycle. It can be defined in the config/mach/mach.h file,
186 otherwise we set it to 1. */
188 static int issue_rate;
194 /* sched-verbose controls the amount of debugging output the
195 scheduler prints. It is controlled by -fsched-verbose-N:
196 N>0 and no -DSR : the output is directed to stderr.
197 N>=10 will direct the printouts to stderr (regardless of -dSR).
199 N=2: bb's probabilities, detailed ready list info, unit/insn info.
200 N=3: rtl at abort point, control-flow, regions info.
201 N=5: dependences info. */
203 #define MAX_RGN_BLOCKS 10
204 #define MAX_RGN_INSNS 100
206 static int sched_verbose_param = 0;
207 static int sched_verbose = 0;
209 /* nr_inter/spec counts interblock/speculative motion for the function */
210 static int nr_inter, nr_spec;
213 /* debugging file. all printouts are sent to dump, which is always set,
214 either to stderr, or to the dump listing file (-dRS). */
215 static FILE *dump = 0;
217 /* fix_sched_param() is called from toplev.c upon detection
218 of the -fsched-***-N options. */
221 fix_sched_param (param, val)
224 if (!strcmp (param, "verbose"))
225 sched_verbose_param = atoi (val);
227 warning ("fix_sched_param: unknown param: %s", param);
231 /* Arrays set up by scheduling for the same respective purposes as
232 similar-named arrays set up by flow analysis. We work with these
233 arrays during the scheduling pass so we can compare values against
236 Values of these arrays are copied at the end of this pass into the
237 arrays set up by flow analysis. */
238 static int *sched_reg_n_calls_crossed;
239 static int *sched_reg_live_length;
240 static int *sched_reg_basic_block;
242 /* We need to know the current block number during the post scheduling
243 update of live register information so that we can also update
244 REG_BASIC_BLOCK if a register changes blocks. */
245 static int current_block_num;
247 /* Element N is the next insn that sets (hard or pseudo) register
248 N within the current basic block; or zero, if there is no
249 such insn. Needed for new registers which may be introduced
250 by splitting insns. */
251 static rtx *reg_last_uses;
252 static rtx *reg_last_sets;
253 static regset reg_pending_sets;
254 static int reg_pending_sets_all;
256 /* Vector indexed by INSN_UID giving the original ordering of the insns. */
257 static int *insn_luid;
258 #define INSN_LUID(INSN) (insn_luid[INSN_UID (INSN)])
260 /* Vector indexed by INSN_UID giving each instruction a priority. */
261 static int *insn_priority;
262 #define INSN_PRIORITY(INSN) (insn_priority[INSN_UID (INSN)])
264 static short *insn_costs;
265 #define INSN_COST(INSN) insn_costs[INSN_UID (INSN)]
267 /* Vector indexed by INSN_UID giving an encoding of the function units
269 static short *insn_units;
270 #define INSN_UNIT(INSN) insn_units[INSN_UID (INSN)]
272 /* Vector indexed by INSN_UID giving each instruction a register-weight.
273 This weight is an estimation of the insn contribution to registers pressure. */
274 static int *insn_reg_weight;
275 #define INSN_REG_WEIGHT(INSN) (insn_reg_weight[INSN_UID (INSN)])
277 /* Vector indexed by INSN_UID giving list of insns which
278 depend upon INSN. Unlike LOG_LINKS, it represents forward dependences. */
279 static rtx *insn_depend;
280 #define INSN_DEPEND(INSN) insn_depend[INSN_UID (INSN)]
282 /* Vector indexed by INSN_UID. Initialized to the number of incoming
283 edges in forward dependence graph (= number of LOG_LINKS). As
284 scheduling procedes, dependence counts are decreased. An
285 instruction moves to the ready list when its counter is zero. */
286 static int *insn_dep_count;
287 #define INSN_DEP_COUNT(INSN) (insn_dep_count[INSN_UID (INSN)])
289 /* Vector indexed by INSN_UID giving an encoding of the blockage range
290 function. The unit and the range are encoded. */
291 static unsigned int *insn_blockage;
292 #define INSN_BLOCKAGE(INSN) insn_blockage[INSN_UID (INSN)]
294 #define BLOCKAGE_MASK ((1 << BLOCKAGE_BITS) - 1)
295 #define ENCODE_BLOCKAGE(U, R) \
296 ((((U) << UNIT_BITS) << BLOCKAGE_BITS \
297 | MIN_BLOCKAGE_COST (R)) << BLOCKAGE_BITS \
298 | MAX_BLOCKAGE_COST (R))
299 #define UNIT_BLOCKED(B) ((B) >> (2 * BLOCKAGE_BITS))
300 #define BLOCKAGE_RANGE(B) \
301 (((((B) >> BLOCKAGE_BITS) & BLOCKAGE_MASK) << (HOST_BITS_PER_INT / 2)) \
302 | ((B) & BLOCKAGE_MASK))
304 /* Encodings of the `<name>_unit_blockage_range' function. */
305 #define MIN_BLOCKAGE_COST(R) ((R) >> (HOST_BITS_PER_INT / 2))
306 #define MAX_BLOCKAGE_COST(R) ((R) & ((1 << (HOST_BITS_PER_INT / 2)) - 1))
308 #define DONE_PRIORITY -1
309 #define MAX_PRIORITY 0x7fffffff
310 #define TAIL_PRIORITY 0x7ffffffe
311 #define LAUNCH_PRIORITY 0x7f000001
312 #define DONE_PRIORITY_P(INSN) (INSN_PRIORITY (INSN) < 0)
313 #define LOW_PRIORITY_P(INSN) ((INSN_PRIORITY (INSN) & 0x7f000000) == 0)
315 /* Vector indexed by INSN_UID giving number of insns referring to this insn. */
316 static int *insn_ref_count;
317 #define INSN_REF_COUNT(INSN) (insn_ref_count[INSN_UID (INSN)])
319 /* Vector indexed by INSN_UID giving line-number note in effect for each
320 insn. For line-number notes, this indicates whether the note may be
322 static rtx *line_note;
323 #define LINE_NOTE(INSN) (line_note[INSN_UID (INSN)])
325 /* Vector indexed by basic block number giving the starting line-number
326 for each basic block. */
327 static rtx *line_note_head;
329 /* List of important notes we must keep around. This is a pointer to the
330 last element in the list. */
331 static rtx note_list;
333 /* Regsets telling whether a given register is live or dead before the last
334 scheduled insn. Must scan the instructions once before scheduling to
335 determine what registers are live or dead at the end of the block. */
336 static regset bb_live_regs;
338 /* Regset telling whether a given register is live after the insn currently
339 being scheduled. Before processing an insn, this is equal to bb_live_regs
340 above. This is used so that we can find registers that are newly born/dead
341 after processing an insn. */
342 static regset old_live_regs;
344 /* The chain of REG_DEAD notes. REG_DEAD notes are removed from all insns
345 during the initial scan and reused later. If there are not exactly as
346 many REG_DEAD notes in the post scheduled code as there were in the
347 prescheduled code then we trigger an abort because this indicates a bug. */
348 static rtx dead_notes;
352 /* An instruction is ready to be scheduled when all insns preceding it
353 have already been scheduled. It is important to ensure that all
354 insns which use its result will not be executed until its result
355 has been computed. An insn is maintained in one of four structures:
357 (P) the "Pending" set of insns which cannot be scheduled until
358 their dependencies have been satisfied.
359 (Q) the "Queued" set of insns that can be scheduled when sufficient
361 (R) the "Ready" list of unscheduled, uncommitted insns.
362 (S) the "Scheduled" list of insns.
364 Initially, all insns are either "Pending" or "Ready" depending on
365 whether their dependencies are satisfied.
367 Insns move from the "Ready" list to the "Scheduled" list as they
368 are committed to the schedule. As this occurs, the insns in the
369 "Pending" list have their dependencies satisfied and move to either
370 the "Ready" list or the "Queued" set depending on whether
371 sufficient time has passed to make them ready. As time passes,
372 insns move from the "Queued" set to the "Ready" list. Insns may
373 move from the "Ready" list to the "Queued" set if they are blocked
374 due to a function unit conflict.
376 The "Pending" list (P) are the insns in the INSN_DEPEND of the unscheduled
377 insns, i.e., those that are ready, queued, and pending.
378 The "Queued" set (Q) is implemented by the variable `insn_queue'.
379 The "Ready" list (R) is implemented by the variables `ready' and
381 The "Scheduled" list (S) is the new insn chain built by this pass.
383 The transition (R->S) is implemented in the scheduling loop in
384 `schedule_block' when the best insn to schedule is chosen.
385 The transition (R->Q) is implemented in `queue_insn' when an
386 insn is found to have a function unit conflict with the already
388 The transitions (P->R and P->Q) are implemented in `schedule_insn' as
389 insns move from the ready list to the scheduled list.
390 The transition (Q->R) is implemented in 'queue_to_insn' as time
391 passes or stalls are introduced. */
393 /* Implement a circular buffer to delay instructions until sufficient
394 time has passed. INSN_QUEUE_SIZE is a power of two larger than
395 MAX_BLOCKAGE and MAX_READY_COST computed by genattr.c. This is the
396 longest time an isnsn may be queued. */
397 static rtx insn_queue[INSN_QUEUE_SIZE];
398 static int q_ptr = 0;
399 static int q_size = 0;
400 #define NEXT_Q(X) (((X)+1) & (INSN_QUEUE_SIZE-1))
401 #define NEXT_Q_AFTER(X, C) (((X)+C) & (INSN_QUEUE_SIZE-1))
403 /* Vector indexed by INSN_UID giving the minimum clock tick at which
404 the insn becomes ready. This is used to note timing constraints for
405 insns in the pending list. */
406 static int *insn_tick;
407 #define INSN_TICK(INSN) (insn_tick[INSN_UID (INSN)])
409 /* Data structure for keeping track of register information
410 during that register's life. */
419 /* Forward declarations. */
420 static void add_dependence PROTO ((rtx, rtx, enum reg_note));
421 static void remove_dependence PROTO ((rtx, rtx));
422 static rtx find_insn_list PROTO ((rtx, rtx));
423 static int insn_unit PROTO ((rtx));
424 static unsigned int blockage_range PROTO ((int, rtx));
425 static void clear_units PROTO ((void));
426 static int actual_hazard_this_instance PROTO ((int, int, rtx, int, int));
427 static void schedule_unit PROTO ((int, rtx, int));
428 static int actual_hazard PROTO ((int, rtx, int, int));
429 static int potential_hazard PROTO ((int, rtx, int));
430 static int insn_cost PROTO ((rtx, rtx, rtx));
431 static int priority PROTO ((rtx));
432 static void free_pending_lists PROTO ((void));
433 static void add_insn_mem_dependence PROTO ((rtx *, rtx *, rtx, rtx));
434 static void flush_pending_lists PROTO ((rtx, int));
435 static void sched_analyze_1 PROTO ((rtx, rtx));
436 static void sched_analyze_2 PROTO ((rtx, rtx));
437 static void sched_analyze_insn PROTO ((rtx, rtx, rtx));
438 static void sched_analyze PROTO ((rtx, rtx));
439 static void sched_note_set PROTO ((rtx, int));
440 static int rank_for_schedule PROTO ((const GENERIC_PTR, const GENERIC_PTR));
441 static void swap_sort PROTO ((rtx *, int));
442 static void queue_insn PROTO ((rtx, int));
443 static int schedule_insn PROTO ((rtx, rtx *, int, int));
444 static void create_reg_dead_note PROTO ((rtx, rtx));
445 static void attach_deaths PROTO ((rtx, rtx, int));
446 static void attach_deaths_insn PROTO ((rtx));
447 static int new_sometimes_live PROTO ((struct sometimes *, int, int));
448 static void finish_sometimes_live PROTO ((struct sometimes *, int));
449 static int schedule_block PROTO ((int, int));
450 static rtx regno_use_in PROTO ((int, rtx));
451 static void split_hard_reg_notes PROTO ((rtx, rtx, rtx));
452 static void new_insn_dead_notes PROTO ((rtx, rtx, rtx, rtx));
453 static void update_n_sets PROTO ((rtx, int));
454 static void update_flow_info PROTO ((rtx, rtx, rtx, rtx));
455 static char *safe_concat PROTO ((char *, char *, char *));
456 static int insn_issue_delay PROTO ((rtx));
457 static int birthing_insn_p PROTO ((rtx));
458 static void adjust_priority PROTO ((rtx));
460 /* Mapping of insns to their original block prior to scheduling. */
461 static int *insn_orig_block;
462 #define INSN_BLOCK(insn) (insn_orig_block[INSN_UID (insn)])
464 /* Some insns (e.g. call) are not allowed to move across blocks. */
465 static char *cant_move;
466 #define CANT_MOVE(insn) (cant_move[INSN_UID (insn)])
468 /* Control flow graph edges are kept in circular lists. */
477 static edge *edge_table;
479 #define NEXT_IN(edge) (edge_table[edge].next_in)
480 #define NEXT_OUT(edge) (edge_table[edge].next_out)
481 #define FROM_BLOCK(edge) (edge_table[edge].from_block)
482 #define TO_BLOCK(edge) (edge_table[edge].to_block)
484 /* Number of edges in the control flow graph. (in fact larger than
485 that by 1, since edge 0 is unused.) */
488 /* Circular list of incoming/outgoing edges of a block */
489 static int *in_edges;
490 static int *out_edges;
492 #define IN_EDGES(block) (in_edges[block])
493 #define OUT_EDGES(block) (out_edges[block])
495 /* List of labels which cannot be deleted, needed for control
496 flow graph construction. */
497 extern rtx forced_labels;
500 static int is_cfg_nonregular PROTO ((void));
501 static int build_control_flow PROTO ((int_list_ptr *, int_list_ptr *,
503 static void new_edge PROTO ((int, int));
506 /* A region is the main entity for interblock scheduling: insns
507 are allowed to move between blocks in the same region, along
508 control flow graph edges, in the 'up' direction. */
511 int rgn_nr_blocks; /* number of blocks in region */
512 int rgn_blocks; /* blocks in the region (actually index in rgn_bb_table) */
516 /* Number of regions in the procedure */
517 static int nr_regions;
519 /* Table of region descriptions */
520 static region *rgn_table;
522 /* Array of lists of regions' blocks */
523 static int *rgn_bb_table;
525 /* Topological order of blocks in the region (if b2 is reachable from
526 b1, block_to_bb[b2] > block_to_bb[b1]).
527 Note: A basic block is always referred to by either block or b,
528 while its topological order name (in the region) is refered to by
531 static int *block_to_bb;
533 /* The number of the region containing a block. */
534 static int *containing_rgn;
536 #define RGN_NR_BLOCKS(rgn) (rgn_table[rgn].rgn_nr_blocks)
537 #define RGN_BLOCKS(rgn) (rgn_table[rgn].rgn_blocks)
538 #define BLOCK_TO_BB(block) (block_to_bb[block])
539 #define CONTAINING_RGN(block) (containing_rgn[block])
541 void debug_regions PROTO ((void));
542 static void find_single_block_region PROTO ((void));
543 static void find_rgns PROTO ((int_list_ptr *, int_list_ptr *,
544 int *, int *, sbitmap *));
545 static int too_large PROTO ((int, int *, int *));
547 extern void debug_live PROTO ((int, int));
549 /* Blocks of the current region being scheduled. */
550 static int current_nr_blocks;
551 static int current_blocks;
553 /* The mapping from bb to block */
554 #define BB_TO_BLOCK(bb) (rgn_bb_table[current_blocks + (bb)])
557 /* Bit vectors and bitset operations are needed for computations on
558 the control flow graph. */
560 typedef unsigned HOST_WIDE_INT *bitset;
563 int *first_member; /* pointer to the list start in bitlst_table. */
564 int nr_members; /* the number of members of the bit list. */
568 static int bitlst_table_last;
569 static int bitlst_table_size;
570 static int *bitlst_table;
572 static char bitset_member PROTO ((bitset, int, int));
573 static void extract_bitlst PROTO ((bitset, int, bitlst *));
575 /* target info declarations.
577 The block currently being scheduled is referred to as the "target" block,
578 while other blocks in the region from which insns can be moved to the
579 target are called "source" blocks. The candidate structure holds info
580 about such sources: are they valid? Speculative? Etc. */
581 typedef bitlst bblst;
592 static candidate *candidate_table;
594 /* A speculative motion requires checking live information on the path
595 from 'source' to 'target'. The split blocks are those to be checked.
596 After a speculative motion, live information should be modified in
599 Lists of split and update blocks for each candidate of the current
600 target are in array bblst_table */
601 static int *bblst_table, bblst_size, bblst_last;
603 #define IS_VALID(src) ( candidate_table[src].is_valid )
604 #define IS_SPECULATIVE(src) ( candidate_table[src].is_speculative )
605 #define SRC_PROB(src) ( candidate_table[src].src_prob )
607 /* The bb being currently scheduled. */
608 static int target_bb;
611 typedef bitlst edgelst;
613 /* target info functions */
614 static void split_edges PROTO ((int, int, edgelst *));
615 static void compute_trg_info PROTO ((int));
616 void debug_candidate PROTO ((int));
617 void debug_candidates PROTO ((int));
620 /* Bit-set of bbs, where bit 'i' stands for bb 'i'. */
621 typedef bitset bbset;
623 /* Number of words of the bbset. */
624 static int bbset_size;
626 /* Dominators array: dom[i] contains the bbset of dominators of
627 bb i in the region. */
630 /* bb 0 is the only region entry */
631 #define IS_RGN_ENTRY(bb) (!bb)
633 /* Is bb_src dominated by bb_trg. */
634 #define IS_DOMINATED(bb_src, bb_trg) \
635 ( bitset_member (dom[bb_src], bb_trg, bbset_size) )
637 /* Probability: Prob[i] is a float in [0, 1] which is the probability
638 of bb i relative to the region entry. */
641 /* The probability of bb_src, relative to bb_trg. Note, that while the
642 'prob[bb]' is a float in [0, 1], this macro returns an integer
644 #define GET_SRC_PROB(bb_src, bb_trg) ((int) (100.0 * (prob[bb_src] / \
647 /* Bit-set of edges, where bit i stands for edge i. */
648 typedef bitset edgeset;
650 /* Number of edges in the region. */
651 static int rgn_nr_edges;
653 /* Array of size rgn_nr_edges. */
654 static int *rgn_edges;
656 /* Number of words in an edgeset. */
657 static int edgeset_size;
659 /* Mapping from each edge in the graph to its number in the rgn. */
660 static int *edge_to_bit;
661 #define EDGE_TO_BIT(edge) (edge_to_bit[edge])
663 /* The split edges of a source bb is different for each target
664 bb. In order to compute this efficiently, the 'potential-split edges'
665 are computed for each bb prior to scheduling a region. This is actually
666 the split edges of each bb relative to the region entry.
668 pot_split[bb] is the set of potential split edges of bb. */
669 static edgeset *pot_split;
671 /* For every bb, a set of its ancestor edges. */
672 static edgeset *ancestor_edges;
674 static void compute_dom_prob_ps PROTO ((int));
676 #define ABS_VALUE(x) (((x)<0)?(-(x)):(x))
677 #define INSN_PROBABILITY(INSN) (SRC_PROB (BLOCK_TO_BB (INSN_BLOCK (INSN))))
678 #define IS_SPECULATIVE_INSN(INSN) (IS_SPECULATIVE (BLOCK_TO_BB (INSN_BLOCK (INSN))))
679 #define INSN_BB(INSN) (BLOCK_TO_BB (INSN_BLOCK (INSN)))
681 /* parameters affecting the decision of rank_for_schedule() */
682 #define MIN_DIFF_PRIORITY 2
683 #define MIN_PROBABILITY 40
684 #define MIN_PROB_DIFF 10
686 /* speculative scheduling functions */
687 static int check_live_1 PROTO ((int, rtx));
688 static void update_live_1 PROTO ((int, rtx));
689 static int check_live PROTO ((rtx, int));
690 static void update_live PROTO ((rtx, int));
691 static void set_spec_fed PROTO ((rtx));
692 static int is_pfree PROTO ((rtx, int, int));
693 static int find_conditional_protection PROTO ((rtx, int));
694 static int is_conditionally_protected PROTO ((rtx, int, int));
695 static int may_trap_exp PROTO ((rtx, int));
696 static int haifa_classify_insn PROTO ((rtx));
697 static int is_prisky PROTO ((rtx, int, int));
698 static int is_exception_free PROTO ((rtx, int, int));
700 static char find_insn_mem_list PROTO ((rtx, rtx, rtx, rtx));
701 static void compute_block_forward_dependences PROTO ((int));
702 static void init_rgn_data_dependences PROTO ((int));
703 static void add_branch_dependences PROTO ((rtx, rtx));
704 static void compute_block_backward_dependences PROTO ((int));
705 void debug_dependencies PROTO ((void));
707 /* Notes handling mechanism:
708 =========================
709 Generally, NOTES are saved before scheduling and restored after scheduling.
710 The scheduler distinguishes between three types of notes:
712 (1) LINE_NUMBER notes, generated and used for debugging. Here,
713 before scheduling a region, a pointer to the LINE_NUMBER note is
714 added to the insn following it (in save_line_notes()), and the note
715 is removed (in rm_line_notes() and unlink_line_notes()). After
716 scheduling the region, this pointer is used for regeneration of
717 the LINE_NUMBER note (in restore_line_notes()).
719 (2) LOOP_BEGIN, LOOP_END, SETJMP, EHREGION_BEG, EHREGION_END notes:
720 Before scheduling a region, a pointer to the note is added to the insn
721 that follows or precedes it. (This happens as part of the data dependence
722 computation). After scheduling an insn, the pointer contained in it is
723 used for regenerating the corresponding note (in reemit_notes).
725 (3) All other notes (e.g. INSN_DELETED): Before scheduling a block,
726 these notes are put in a list (in rm_other_notes() and
727 unlink_other_notes ()). After scheduling the block, these notes are
728 inserted at the beginning of the block (in schedule_block()). */
730 static rtx unlink_other_notes PROTO ((rtx, rtx));
731 static rtx unlink_line_notes PROTO ((rtx, rtx));
732 static void rm_line_notes PROTO ((int));
733 static void save_line_notes PROTO ((int));
734 static void restore_line_notes PROTO ((int));
735 static void rm_redundant_line_notes PROTO ((void));
736 static void rm_other_notes PROTO ((rtx, rtx));
737 static rtx reemit_notes PROTO ((rtx, rtx));
739 static void get_block_head_tail PROTO ((int, rtx *, rtx *));
741 static void find_pre_sched_live PROTO ((int));
742 static void find_post_sched_live PROTO ((int));
743 static void update_reg_usage PROTO ((void));
744 static int queue_to_ready PROTO ((rtx [], int));
746 static void debug_ready_list PROTO ((rtx[], int));
747 static void init_target_units PROTO ((void));
748 static void insn_print_units PROTO ((rtx));
749 static int get_visual_tbl_length PROTO ((void));
750 static void init_block_visualization PROTO ((void));
751 static void print_block_visualization PROTO ((int, char *));
752 static void visualize_scheduled_insns PROTO ((int, int));
753 static void visualize_no_unit PROTO ((rtx));
754 static void visualize_stall_cycles PROTO ((int, int));
755 static void print_exp PROTO ((char *, rtx, int));
756 static void print_value PROTO ((char *, rtx, int));
757 static void print_pattern PROTO ((char *, rtx, int));
758 static void print_insn PROTO ((char *, rtx, int));
759 void debug_reg_vector PROTO ((regset));
761 static rtx move_insn1 PROTO ((rtx, rtx));
762 static rtx move_insn PROTO ((rtx, rtx));
763 static rtx group_leader PROTO ((rtx));
764 static int set_priorities PROTO ((int));
765 static void init_rtx_vector PROTO ((rtx **, rtx *, int, int));
766 static void schedule_region PROTO ((int));
767 static void split_block_insns PROTO ((int));
769 #endif /* INSN_SCHEDULING */
771 #define SIZE_FOR_MODE(X) (GET_MODE_SIZE (GET_MODE (X)))
773 /* Helper functions for instruction scheduling. */
775 /* An INSN_LIST containing all INSN_LISTs allocated but currently unused. */
776 static rtx unused_insn_list;
778 /* An EXPR_LIST containing all EXPR_LISTs allocated but currently unused. */
779 static rtx unused_expr_list;
781 static void free_list PROTO ((rtx *, rtx *));
782 static rtx alloc_INSN_LIST PROTO ((rtx, rtx));
783 static rtx alloc_EXPR_LIST PROTO ((int, rtx, rtx));
786 free_list (listp, unused_listp)
787 rtx *listp, *unused_listp;
789 register rtx link, prev_link;
795 link = XEXP (prev_link, 1);
800 link = XEXP (link, 1);
803 XEXP (prev_link, 1) = *unused_listp;
804 *unused_listp = *listp;
809 alloc_INSN_LIST (val, next)
814 if (unused_insn_list)
816 r = unused_insn_list;
817 unused_insn_list = XEXP (r, 1);
820 PUT_REG_NOTE_KIND (r, VOIDmode);
823 r = gen_rtx_INSN_LIST (VOIDmode, val, next);
829 alloc_EXPR_LIST (kind, val, next)
835 if (unused_expr_list)
837 r = unused_expr_list;
838 unused_expr_list = XEXP (r, 1);
841 PUT_REG_NOTE_KIND (r, kind);
844 r = gen_rtx_EXPR_LIST (kind, val, next);
849 /* Add ELEM wrapped in an INSN_LIST with reg note kind DEP_TYPE to the
850 LOG_LINKS of INSN, if not already there. DEP_TYPE indicates the type
851 of dependence that this link represents. */
854 add_dependence (insn, elem, dep_type)
857 enum reg_note dep_type;
861 /* Don't depend an insn on itself. */
865 /* If elem is part of a sequence that must be scheduled together, then
866 make the dependence point to the last insn of the sequence.
867 When HAVE_cc0, it is possible for NOTEs to exist between users and
868 setters of the condition codes, so we must skip past notes here.
869 Otherwise, NOTEs are impossible here. */
871 next = NEXT_INSN (elem);
874 while (next && GET_CODE (next) == NOTE)
875 next = NEXT_INSN (next);
878 if (next && SCHED_GROUP_P (next)
879 && GET_CODE (next) != CODE_LABEL)
881 /* Notes will never intervene here though, so don't bother checking
883 /* We must reject CODE_LABELs, so that we don't get confused by one
884 that has LABEL_PRESERVE_P set, which is represented by the same
885 bit in the rtl as SCHED_GROUP_P. A CODE_LABEL can never be
887 while (NEXT_INSN (next) && SCHED_GROUP_P (NEXT_INSN (next))
888 && GET_CODE (NEXT_INSN (next)) != CODE_LABEL)
889 next = NEXT_INSN (next);
891 /* Again, don't depend an insn on itself. */
895 /* Make the dependence to NEXT, the last insn of the group, instead
896 of the original ELEM. */
900 #ifdef INSN_SCHEDULING
901 /* (This code is guarded by INSN_SCHEDULING, otherwise INSN_BB is undefined.)
902 No need for interblock dependences with calls, since
903 calls are not moved between blocks. Note: the edge where
904 elem is a CALL is still required. */
905 if (GET_CODE (insn) == CALL_INSN
906 && (INSN_BB (elem) != INSN_BB (insn)))
911 /* Check that we don't already have this dependence. */
912 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
913 if (XEXP (link, 0) == elem)
915 /* If this is a more restrictive type of dependence than the existing
916 one, then change the existing dependence to this type. */
917 if ((int) dep_type < (int) REG_NOTE_KIND (link))
918 PUT_REG_NOTE_KIND (link, dep_type);
921 /* Might want to check one level of transitivity to save conses. */
923 link = alloc_INSN_LIST (elem, LOG_LINKS (insn));
924 LOG_LINKS (insn) = link;
926 /* Insn dependency, not data dependency. */
927 PUT_REG_NOTE_KIND (link, dep_type);
930 /* Remove ELEM wrapped in an INSN_LIST from the LOG_LINKS
931 of INSN. Abort if not found. */
934 remove_dependence (insn, elem)
938 rtx prev, link, next;
941 for (prev = 0, link = LOG_LINKS (insn); link; link = next)
943 next = XEXP (link, 1);
944 if (XEXP (link, 0) == elem)
947 XEXP (prev, 1) = next;
949 LOG_LINKS (insn) = next;
951 XEXP (link, 1) = unused_insn_list;
952 unused_insn_list = link;
965 #ifndef INSN_SCHEDULING
967 schedule_insns (dump_file)
977 #define HAIFA_INLINE __inline
980 /* Computation of memory dependencies. */
982 /* The *_insns and *_mems are paired lists. Each pending memory operation
983 will have a pointer to the MEM rtx on one list and a pointer to the
984 containing insn on the other list in the same place in the list. */
986 /* We can't use add_dependence like the old code did, because a single insn
987 may have multiple memory accesses, and hence needs to be on the list
988 once for each memory access. Add_dependence won't let you add an insn
989 to a list more than once. */
991 /* An INSN_LIST containing all insns with pending read operations. */
992 static rtx pending_read_insns;
994 /* An EXPR_LIST containing all MEM rtx's which are pending reads. */
995 static rtx pending_read_mems;
997 /* An INSN_LIST containing all insns with pending write operations. */
998 static rtx pending_write_insns;
1000 /* An EXPR_LIST containing all MEM rtx's which are pending writes. */
1001 static rtx pending_write_mems;
1003 /* Indicates the combined length of the two pending lists. We must prevent
1004 these lists from ever growing too large since the number of dependencies
1005 produced is at least O(N*N), and execution time is at least O(4*N*N), as
1006 a function of the length of these pending lists. */
1008 static int pending_lists_length;
1010 /* The last insn upon which all memory references must depend.
1011 This is an insn which flushed the pending lists, creating a dependency
1012 between it and all previously pending memory references. This creates
1013 a barrier (or a checkpoint) which no memory reference is allowed to cross.
1015 This includes all non constant CALL_INSNs. When we do interprocedural
1016 alias analysis, this restriction can be relaxed.
1017 This may also be an INSN that writes memory if the pending lists grow
1020 static rtx last_pending_memory_flush;
1022 /* The last function call we have seen. All hard regs, and, of course,
1023 the last function call, must depend on this. */
1025 static rtx last_function_call;
1027 /* The LOG_LINKS field of this is a list of insns which use a pseudo register
1028 that does not already cross a call. We create dependencies between each
1029 of those insn and the next call insn, to ensure that they won't cross a call
1030 after scheduling is done. */
1032 static rtx sched_before_next_call;
1034 /* Pointer to the last instruction scheduled. Used by rank_for_schedule,
1035 so that insns independent of the last scheduled insn will be preferred
1036 over dependent instructions. */
1038 static rtx last_scheduled_insn;
1040 /* Data structures for the computation of data dependences in a regions. We
1041 keep one copy of each of the declared above variables for each bb in the
1042 region. Before analyzing the data dependences for a bb, its variables
1043 are initialized as a function of the variables of its predecessors. When
1044 the analysis for a bb completes, we save the contents of each variable X
1045 to a corresponding bb_X[bb] variable. For example, pending_read_insns is
1046 copied to bb_pending_read_insns[bb]. Another change is that few
1047 variables are now a list of insns rather than a single insn:
1048 last_pending_memory_flash, last_function_call, reg_last_sets. The
1049 manipulation of these variables was changed appropriately. */
1051 static rtx **bb_reg_last_uses;
1052 static rtx **bb_reg_last_sets;
1054 static rtx *bb_pending_read_insns;
1055 static rtx *bb_pending_read_mems;
1056 static rtx *bb_pending_write_insns;
1057 static rtx *bb_pending_write_mems;
1058 static int *bb_pending_lists_length;
1060 static rtx *bb_last_pending_memory_flush;
1061 static rtx *bb_last_function_call;
1062 static rtx *bb_sched_before_next_call;
1064 /* functions for construction of the control flow graph. */
1066 /* Return 1 if control flow graph should not be constructed, 0 otherwise.
1068 We decide not to build the control flow graph if there is possibly more
1069 than one entry to the function, if computed branches exist, of if we
1070 have nonlocal gotos. */
1073 is_cfg_nonregular ()
1079 /* If we have a label that could be the target of a nonlocal goto, then
1080 the cfg is not well structured. */
1081 if (nonlocal_label_rtx_list () != NULL)
1084 /* If we have any forced labels, then the cfg is not well structured. */
1088 /* If this function has a computed jump, then we consider the cfg
1089 not well structured. */
1090 if (current_function_has_computed_jump)
1093 /* If we have exception handlers, then we consider the cfg not well
1094 structured. ?!? We should be able to handle this now that flow.c
1095 computes an accurate cfg for EH. */
1096 if (exception_handler_labels)
1099 /* If we have non-jumping insns which refer to labels, then we consider
1100 the cfg not well structured. */
1101 /* check for labels referred to other thn by jumps */
1102 for (b = 0; b < n_basic_blocks; b++)
1103 for (insn = basic_block_head[b];; insn = NEXT_INSN (insn))
1105 code = GET_CODE (insn);
1106 if (GET_RTX_CLASS (code) == 'i')
1110 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
1111 if (REG_NOTE_KIND (note) == REG_LABEL)
1115 if (insn == basic_block_end[b])
1119 /* All the tests passed. Consider the cfg well structured. */
1123 /* Build the control flow graph and set nr_edges.
1125 Instead of trying to build a cfg ourselves, we rely on flow to
1126 do it for us. Stamp out useless code (and bug) duplication.
1128 Return nonzero if an irregularity in the cfg is found which would
1129 prevent cross block scheduling. */
1132 build_control_flow (s_preds, s_succs, num_preds, num_succs)
1133 int_list_ptr *s_preds;
1134 int_list_ptr *s_succs;
1142 /* Count the number of edges in the cfg. */
1145 for (i = 0; i < n_basic_blocks; i++)
1147 nr_edges += num_succs[i];
1149 /* Unreachable loops with more than one basic block are detected
1150 during the DFS traversal in find_rgns.
1152 Unreachable loops with a single block are detected here. This
1153 test is redundant with the one in find_rgns, but it's much
1154 cheaper to go ahead and catch the trivial case here. */
1155 if (num_preds[i] == 0
1156 || (num_preds[i] == 1 && INT_LIST_VAL (s_preds[i]) == i))
1160 /* Account for entry/exit edges. */
1163 in_edges = (int *) xmalloc (n_basic_blocks * sizeof (int));
1164 out_edges = (int *) xmalloc (n_basic_blocks * sizeof (int));
1165 bzero ((char *) in_edges, n_basic_blocks * sizeof (int));
1166 bzero ((char *) out_edges, n_basic_blocks * sizeof (int));
1168 edge_table = (edge *) xmalloc ((nr_edges) * sizeof (edge));
1169 bzero ((char *) edge_table, ((nr_edges) * sizeof (edge)));
1172 for (i = 0; i < n_basic_blocks; i++)
1173 for (succ = s_succs[i]; succ; succ = succ->next)
1175 if (INT_LIST_VAL (succ) != EXIT_BLOCK)
1176 new_edge (i, INT_LIST_VAL (succ));
1179 /* increment by 1, since edge 0 is unused. */
1186 /* Record an edge in the control flow graph from SOURCE to TARGET.
1188 In theory, this is redundant with the s_succs computed above, but
1189 we have not converted all of haifa to use information from the
1193 new_edge (source, target)
1197 int curr_edge, fst_edge;
1199 /* check for duplicates */
1200 fst_edge = curr_edge = OUT_EDGES (source);
1203 if (FROM_BLOCK (curr_edge) == source
1204 && TO_BLOCK (curr_edge) == target)
1209 curr_edge = NEXT_OUT (curr_edge);
1211 if (fst_edge == curr_edge)
1217 FROM_BLOCK (e) = source;
1218 TO_BLOCK (e) = target;
1220 if (OUT_EDGES (source))
1222 next_edge = NEXT_OUT (OUT_EDGES (source));
1223 NEXT_OUT (OUT_EDGES (source)) = e;
1224 NEXT_OUT (e) = next_edge;
1228 OUT_EDGES (source) = e;
1232 if (IN_EDGES (target))
1234 next_edge = NEXT_IN (IN_EDGES (target));
1235 NEXT_IN (IN_EDGES (target)) = e;
1236 NEXT_IN (e) = next_edge;
1240 IN_EDGES (target) = e;
1246 /* BITSET macros for operations on the control flow graph. */
1248 /* Compute bitwise union of two bitsets. */
1249 #define BITSET_UNION(set1, set2, len) \
1250 do { register bitset tp = set1, sp = set2; \
1252 for (i = 0; i < len; i++) \
1253 *(tp++) |= *(sp++); } while (0)
1255 /* Compute bitwise intersection of two bitsets. */
1256 #define BITSET_INTER(set1, set2, len) \
1257 do { register bitset tp = set1, sp = set2; \
1259 for (i = 0; i < len; i++) \
1260 *(tp++) &= *(sp++); } while (0)
1262 /* Compute bitwise difference of two bitsets. */
1263 #define BITSET_DIFFER(set1, set2, len) \
1264 do { register bitset tp = set1, sp = set2; \
1266 for (i = 0; i < len; i++) \
1267 *(tp++) &= ~*(sp++); } while (0)
1269 /* Inverts every bit of bitset 'set' */
1270 #define BITSET_INVERT(set, len) \
1271 do { register bitset tmpset = set; \
1273 for (i = 0; i < len; i++, tmpset++) \
1274 *tmpset = ~*tmpset; } while (0)
1276 /* Turn on the index'th bit in bitset set. */
1277 #define BITSET_ADD(set, index, len) \
1279 if (index >= HOST_BITS_PER_WIDE_INT * len) \
1282 set[index/HOST_BITS_PER_WIDE_INT] |= \
1283 1 << (index % HOST_BITS_PER_WIDE_INT); \
1286 /* Turn off the index'th bit in set. */
1287 #define BITSET_REMOVE(set, index, len) \
1289 if (index >= HOST_BITS_PER_WIDE_INT * len) \
1292 set[index/HOST_BITS_PER_WIDE_INT] &= \
1293 ~(1 << (index%HOST_BITS_PER_WIDE_INT)); \
1297 /* Check if the index'th bit in bitset set is on. */
1300 bitset_member (set, index, len)
1304 if (index >= HOST_BITS_PER_WIDE_INT * len)
1306 return (set[index / HOST_BITS_PER_WIDE_INT] &
1307 1 << (index % HOST_BITS_PER_WIDE_INT)) ? 1 : 0;
1311 /* Translate a bit-set SET to a list BL of the bit-set members. */
1314 extract_bitlst (set, len, bl)
1320 unsigned HOST_WIDE_INT word;
1322 /* bblst table space is reused in each call to extract_bitlst */
1323 bitlst_table_last = 0;
1325 bl->first_member = &bitlst_table[bitlst_table_last];
1328 for (i = 0; i < len; i++)
1331 offset = i * HOST_BITS_PER_WIDE_INT;
1332 for (j = 0; word; j++)
1336 bitlst_table[bitlst_table_last++] = offset;
1347 /* functions for the construction of regions */
1349 /* Print the regions, for debugging purposes. Callable from debugger. */
1356 fprintf (dump, "\n;; ------------ REGIONS ----------\n\n");
1357 for (rgn = 0; rgn < nr_regions; rgn++)
1359 fprintf (dump, ";;\trgn %d nr_blocks %d:\n", rgn,
1360 rgn_table[rgn].rgn_nr_blocks);
1361 fprintf (dump, ";;\tbb/block: ");
1363 for (bb = 0; bb < rgn_table[rgn].rgn_nr_blocks; bb++)
1365 current_blocks = RGN_BLOCKS (rgn);
1367 if (bb != BLOCK_TO_BB (BB_TO_BLOCK (bb)))
1370 fprintf (dump, " %d/%d ", bb, BB_TO_BLOCK (bb));
1373 fprintf (dump, "\n\n");
1378 /* Build a single block region for each basic block in the function.
1379 This allows for using the same code for interblock and basic block
1383 find_single_block_region ()
1387 for (i = 0; i < n_basic_blocks; i++)
1389 rgn_bb_table[i] = i;
1390 RGN_NR_BLOCKS (i) = 1;
1392 CONTAINING_RGN (i) = i;
1393 BLOCK_TO_BB (i) = 0;
1395 nr_regions = n_basic_blocks;
1399 /* Update number of blocks and the estimate for number of insns
1400 in the region. Return 1 if the region is "too large" for interblock
1401 scheduling (compile time considerations), otherwise return 0. */
1404 too_large (block, num_bbs, num_insns)
1405 int block, *num_bbs, *num_insns;
1408 (*num_insns) += (INSN_LUID (basic_block_end[block]) -
1409 INSN_LUID (basic_block_head[block]));
1410 if ((*num_bbs > MAX_RGN_BLOCKS) || (*num_insns > MAX_RGN_INSNS))
1417 /* Update_loop_relations(blk, hdr): Check if the loop headed by max_hdr[blk]
1418 is still an inner loop. Put in max_hdr[blk] the header of the most inner
1419 loop containing blk. */
1420 #define UPDATE_LOOP_RELATIONS(blk, hdr) \
1422 if (max_hdr[blk] == -1) \
1423 max_hdr[blk] = hdr; \
1424 else if (dfs_nr[max_hdr[blk]] > dfs_nr[hdr]) \
1425 RESET_BIT (inner, hdr); \
1426 else if (dfs_nr[max_hdr[blk]] < dfs_nr[hdr]) \
1428 RESET_BIT (inner,max_hdr[blk]); \
1429 max_hdr[blk] = hdr; \
1434 /* Find regions for interblock scheduling.
1436 A region for scheduling can be:
1438 * A loop-free procedure, or
1440 * A reducible inner loop, or
1442 * A basic block not contained in any other region.
1445 ?!? In theory we could build other regions based on extended basic
1446 blocks or reverse extended basic blocks. Is it worth the trouble?
1448 Loop blocks that form a region are put into the region's block list
1449 in topological order.
1451 This procedure stores its results into the following global (ick) variables
1460 We use dominator relationships to avoid making regions out of non-reducible
1463 This procedure needs to be converted to work on pred/succ lists instead
1464 of edge tables. That would simplify it somewhat. */
1467 find_rgns (s_preds, s_succs, num_preds, num_succs, dom)
1468 int_list_ptr *s_preds;
1469 int_list_ptr *s_succs;
1474 int *max_hdr, *dfs_nr, *stack, *queue, *degree;
1476 int node, child, loop_head, i, head, tail;
1477 int count = 0, sp, idx = 0, current_edge = out_edges[0];
1478 int num_bbs, num_insns, unreachable;
1479 int too_large_failure;
1481 /* Note if an edge has been passed. */
1484 /* Note if a block is a natural loop header. */
1487 /* Note if a block is an natural inner loop header. */
1490 /* Note if a block is in the block queue. */
1493 /* Note if a block is in the block queue. */
1496 /* Perform a DFS traversal of the cfg. Identify loop headers, inner loops
1497 and a mapping from block to its loop header (if the block is contained
1498 in a loop, else -1).
1500 Store results in HEADER, INNER, and MAX_HDR respectively, these will
1501 be used as inputs to the second traversal.
1503 STACK, SP and DFS_NR are only used during the first traversal. */
1505 /* Allocate and initialize variables for the first traversal. */
1506 max_hdr = (int *) alloca (n_basic_blocks * sizeof (int));
1507 dfs_nr = (int *) alloca (n_basic_blocks * sizeof (int));
1508 bzero ((char *) dfs_nr, n_basic_blocks * sizeof (int));
1509 stack = (int *) alloca (nr_edges * sizeof (int));
1511 inner = sbitmap_alloc (n_basic_blocks);
1512 sbitmap_ones (inner);
1514 header = sbitmap_alloc (n_basic_blocks);
1515 sbitmap_zero (header);
1517 passed = sbitmap_alloc (nr_edges);
1518 sbitmap_zero (passed);
1520 in_queue = sbitmap_alloc (n_basic_blocks);
1521 sbitmap_zero (in_queue);
1523 in_stack = sbitmap_alloc (n_basic_blocks);
1524 sbitmap_zero (in_stack);
1526 for (i = 0; i < n_basic_blocks; i++)
1529 /* DFS traversal to find inner loops in the cfg. */
1534 if (current_edge == 0 || TEST_BIT (passed, current_edge))
1536 /* We have reached a leaf node or a node that was already
1537 processed. Pop edges off the stack until we find
1538 an edge that has not yet been processed. */
1540 && (current_edge == 0 || TEST_BIT (passed, current_edge)))
1542 /* Pop entry off the stack. */
1543 current_edge = stack[sp--];
1544 node = FROM_BLOCK (current_edge);
1545 child = TO_BLOCK (current_edge);
1546 RESET_BIT (in_stack, child);
1547 if (max_hdr[child] >= 0 && TEST_BIT (in_stack, max_hdr[child]))
1548 UPDATE_LOOP_RELATIONS (node, max_hdr[child]);
1549 current_edge = NEXT_OUT (current_edge);
1552 /* See if have finished the DFS tree traversal. */
1553 if (sp < 0 && TEST_BIT (passed, current_edge))
1556 /* Nope, continue the traversal with the popped node. */
1560 /* Process a node. */
1561 node = FROM_BLOCK (current_edge);
1562 child = TO_BLOCK (current_edge);
1563 SET_BIT (in_stack, node);
1564 dfs_nr[node] = ++count;
1566 /* If the successor is in the stack, then we've found a loop.
1567 Mark the loop, if it is not a natural loop, then it will
1568 be rejected during the second traversal. */
1569 if (TEST_BIT (in_stack, child))
1572 SET_BIT (header, child);
1573 UPDATE_LOOP_RELATIONS (node, child);
1574 SET_BIT (passed, current_edge);
1575 current_edge = NEXT_OUT (current_edge);
1579 /* If the child was already visited, then there is no need to visit
1580 it again. Just update the loop relationships and restart
1584 if (max_hdr[child] >= 0 && TEST_BIT (in_stack, max_hdr[child]))
1585 UPDATE_LOOP_RELATIONS (node, max_hdr[child]);
1586 SET_BIT (passed, current_edge);
1587 current_edge = NEXT_OUT (current_edge);
1591 /* Push an entry on the stack and continue DFS traversal. */
1592 stack[++sp] = current_edge;
1593 SET_BIT (passed, current_edge);
1594 current_edge = OUT_EDGES (child);
1597 /* Another check for unreachable blocks. The earlier test in
1598 is_cfg_nonregular only finds unreachable blocks that do not
1601 The DFS traversal will mark every block that is reachable from
1602 the entry node by placing a nonzero value in dfs_nr. Thus if
1603 dfs_nr is zero for any block, then it must be unreachable. */
1605 for (i = 0; i < n_basic_blocks; i++)
1612 /* Gross. To avoid wasting memory, the second pass uses the dfs_nr array
1613 to hold degree counts. */
1616 /* Compute the in-degree of every block in the graph */
1617 for (i = 0; i < n_basic_blocks; i++)
1618 degree[i] = num_preds[i];
1620 /* Do not perform region scheduling if there are any unreachable
1625 SET_BIT (header, 0);
1627 /* Second travsersal:find reducible inner loops and topologically sort
1628 block of each region. */
1630 queue = (int *) alloca (n_basic_blocks * sizeof (int));
1632 /* Find blocks which are inner loop headers. We still have non-reducible
1633 loops to consider at this point. */
1634 for (i = 0; i < n_basic_blocks; i++)
1636 if (TEST_BIT (header, i) && TEST_BIT (inner, i))
1641 /* Now check that the loop is reducible. We do this separate
1642 from finding inner loops so that we do not find a reducible
1643 loop which contains an inner non-reducible loop.
1645 A simple way to find reducible/natrual loops is to verify
1646 that each block in the loop is dominated by the loop
1649 If there exists a block that is not dominated by the loop
1650 header, then the block is reachable from outside the loop
1651 and thus the loop is not a natural loop. */
1652 for (j = 0; j < n_basic_blocks; j++)
1654 /* First identify blocks in the loop, except for the loop
1656 if (i == max_hdr[j] && i != j)
1658 /* Now verify that the block is dominated by the loop
1660 if (!TEST_BIT (dom[j], i))
1665 /* If we exited the loop early, then I is the header of a non
1666 reducible loop and we should quit processing it now. */
1667 if (j != n_basic_blocks)
1670 /* I is a header of an inner loop, or block 0 in a subroutine
1671 with no loops at all. */
1673 too_large_failure = 0;
1674 loop_head = max_hdr[i];
1676 /* Decrease degree of all I's successors for topological
1678 for (ps = s_succs[i]; ps; ps = ps->next)
1679 if (INT_LIST_VAL (ps) != EXIT_BLOCK
1680 && INT_LIST_VAL (ps) != ENTRY_BLOCK)
1681 --degree[INT_LIST_VAL(ps)];
1683 /* Estimate # insns, and count # blocks in the region. */
1685 num_insns = (INSN_LUID (basic_block_end[i])
1686 - INSN_LUID (basic_block_head[i]));
1689 /* Find all loop latches (blocks which back edges to the loop
1690 header) or all the leaf blocks in the cfg has no loops.
1692 Place those blocks into the queue. */
1695 for (j = 0; j < n_basic_blocks; j++)
1696 /* Leaf nodes have only a single successor which must
1698 if (num_succs[j] == 1
1699 && INT_LIST_VAL (s_succs[j]) == EXIT_BLOCK)
1702 SET_BIT (in_queue, j);
1704 if (too_large (j, &num_bbs, &num_insns))
1706 too_large_failure = 1;
1715 for (ps = s_preds[i]; ps; ps = ps->next)
1717 node = INT_LIST_VAL (ps);
1719 if (node == ENTRY_BLOCK || node == EXIT_BLOCK)
1722 if (max_hdr[node] == loop_head && node != i)
1724 /* This is a loop latch. */
1725 queue[++tail] = node;
1726 SET_BIT (in_queue, node);
1728 if (too_large (node, &num_bbs, &num_insns))
1730 too_large_failure = 1;
1738 /* Now add all the blocks in the loop to the queue.
1740 We know the loop is a natural loop; however the algorithm
1741 above will not always mark certain blocks as being in the
1750 The algorithm in the DFS traversal may not mark B & D as part
1751 of the loop (ie they will not have max_hdr set to A).
1753 We know they can not be loop latches (else they would have
1754 had max_hdr set since they'd have a backedge to a dominator
1755 block). So we don't need them on the initial queue.
1757 We know they are part of the loop because they are dominated
1758 by the loop header and can be reached by a backwards walk of
1759 the edges starting with nodes on the initial queue.
1761 It is safe and desirable to include those nodes in the
1762 loop/scheduling region. To do so we would need to decrease
1763 the degree of a node if it is the target of a backedge
1764 within the loop itself as the node is placed in the queue.
1766 We do not do this because I'm not sure that the actual
1767 scheduling code will properly handle this case. ?!? */
1769 while (head < tail && !too_large_failure)
1772 child = queue[++head];
1774 for (ps = s_preds[child]; ps; ps = ps->next)
1776 node = INT_LIST_VAL (ps);
1778 /* See discussion above about nodes not marked as in
1779 this loop during the initial DFS traversal. */
1780 if (node == ENTRY_BLOCK || node == EXIT_BLOCK
1781 || max_hdr[node] != loop_head)
1786 else if (!TEST_BIT (in_queue, node) && node != i)
1788 queue[++tail] = node;
1789 SET_BIT (in_queue, node);
1791 if (too_large (node, &num_bbs, &num_insns))
1793 too_large_failure = 1;
1800 if (tail >= 0 && !too_large_failure)
1802 /* Place the loop header into list of region blocks. */
1804 rgn_bb_table[idx] = i;
1805 RGN_NR_BLOCKS (nr_regions) = num_bbs;
1806 RGN_BLOCKS (nr_regions) = idx++;
1807 CONTAINING_RGN (i) = nr_regions;
1808 BLOCK_TO_BB (i) = count = 0;
1810 /* Remove blocks from queue[] when their in degree becomes
1811 zero. Repeat until no blocks are left on the list. This
1812 produces a topological list of blocks in the region. */
1819 child = queue[head];
1820 if (degree[child] == 0)
1823 rgn_bb_table[idx++] = child;
1824 BLOCK_TO_BB (child) = ++count;
1825 CONTAINING_RGN (child) = nr_regions;
1826 queue[head] = queue[tail--];
1828 for (ps = s_succs[child]; ps; ps = ps->next)
1829 if (INT_LIST_VAL (ps) != ENTRY_BLOCK
1830 && INT_LIST_VAL (ps) != EXIT_BLOCK)
1831 --degree[INT_LIST_VAL (ps)];
1842 /* Any block that did not end up in a region is placed into a region
1844 for (i = 0; i < n_basic_blocks; i++)
1847 rgn_bb_table[idx] = i;
1848 RGN_NR_BLOCKS (nr_regions) = 1;
1849 RGN_BLOCKS (nr_regions) = idx++;
1850 CONTAINING_RGN (i) = nr_regions++;
1851 BLOCK_TO_BB (i) = 0;
1862 /* functions for regions scheduling information */
1864 /* Compute dominators, probability, and potential-split-edges of bb.
1865 Assume that these values were already computed for bb's predecessors. */
1868 compute_dom_prob_ps (bb)
1871 int nxt_in_edge, fst_in_edge, pred;
1872 int fst_out_edge, nxt_out_edge, nr_out_edges, nr_rgn_out_edges;
1875 if (IS_RGN_ENTRY (bb))
1877 BITSET_ADD (dom[bb], 0, bbset_size);
1882 fst_in_edge = nxt_in_edge = IN_EDGES (BB_TO_BLOCK (bb));
1884 /* intialize dom[bb] to '111..1' */
1885 BITSET_INVERT (dom[bb], bbset_size);
1889 pred = FROM_BLOCK (nxt_in_edge);
1890 BITSET_INTER (dom[bb], dom[BLOCK_TO_BB (pred)], bbset_size);
1892 BITSET_UNION (ancestor_edges[bb], ancestor_edges[BLOCK_TO_BB (pred)],
1895 BITSET_ADD (ancestor_edges[bb], EDGE_TO_BIT (nxt_in_edge), edgeset_size);
1898 nr_rgn_out_edges = 0;
1899 fst_out_edge = OUT_EDGES (pred);
1900 nxt_out_edge = NEXT_OUT (fst_out_edge);
1901 BITSET_UNION (pot_split[bb], pot_split[BLOCK_TO_BB (pred)],
1904 BITSET_ADD (pot_split[bb], EDGE_TO_BIT (fst_out_edge), edgeset_size);
1906 /* the successor doesn't belong the region? */
1907 if (CONTAINING_RGN (TO_BLOCK (fst_out_edge)) !=
1908 CONTAINING_RGN (BB_TO_BLOCK (bb)))
1911 while (fst_out_edge != nxt_out_edge)
1914 /* the successor doesn't belong the region? */
1915 if (CONTAINING_RGN (TO_BLOCK (nxt_out_edge)) !=
1916 CONTAINING_RGN (BB_TO_BLOCK (bb)))
1918 BITSET_ADD (pot_split[bb], EDGE_TO_BIT (nxt_out_edge), edgeset_size);
1919 nxt_out_edge = NEXT_OUT (nxt_out_edge);
1923 /* now nr_rgn_out_edges is the number of region-exit edges from pred,
1924 and nr_out_edges will be the number of pred out edges not leaving
1926 nr_out_edges -= nr_rgn_out_edges;
1927 if (nr_rgn_out_edges > 0)
1928 prob[bb] += 0.9 * prob[BLOCK_TO_BB (pred)] / nr_out_edges;
1930 prob[bb] += prob[BLOCK_TO_BB (pred)] / nr_out_edges;
1931 nxt_in_edge = NEXT_IN (nxt_in_edge);
1933 while (fst_in_edge != nxt_in_edge);
1935 BITSET_ADD (dom[bb], bb, bbset_size);
1936 BITSET_DIFFER (pot_split[bb], ancestor_edges[bb], edgeset_size);
1938 if (sched_verbose >= 2)
1939 fprintf (dump, ";; bb_prob(%d, %d) = %3d\n", bb, BB_TO_BLOCK (bb), (int) (100.0 * prob[bb]));
1940 } /* compute_dom_prob_ps */
1942 /* functions for target info */
1944 /* Compute in BL the list of split-edges of bb_src relatively to bb_trg.
1945 Note that bb_trg dominates bb_src. */
1948 split_edges (bb_src, bb_trg, bl)
1953 int es = edgeset_size;
1954 edgeset src = (edgeset) alloca (es * sizeof (HOST_WIDE_INT));
1957 src[es] = (pot_split[bb_src])[es];
1958 BITSET_DIFFER (src, pot_split[bb_trg], edgeset_size);
1959 extract_bitlst (src, edgeset_size, bl);
1963 /* Find the valid candidate-source-blocks for the target block TRG, compute
1964 their probability, and check if they are speculative or not.
1965 For speculative sources, compute their update-blocks and split-blocks. */
1968 compute_trg_info (trg)
1971 register candidate *sp;
1973 int check_block, update_idx;
1974 int i, j, k, fst_edge, nxt_edge;
1976 /* define some of the fields for the target bb as well */
1977 sp = candidate_table + trg;
1979 sp->is_speculative = 0;
1982 for (i = trg + 1; i < current_nr_blocks; i++)
1984 sp = candidate_table + i;
1986 sp->is_valid = IS_DOMINATED (i, trg);
1989 sp->src_prob = GET_SRC_PROB (i, trg);
1990 sp->is_valid = (sp->src_prob >= MIN_PROBABILITY);
1995 split_edges (i, trg, &el);
1996 sp->is_speculative = (el.nr_members) ? 1 : 0;
1997 if (sp->is_speculative && !flag_schedule_speculative)
2003 sp->split_bbs.first_member = &bblst_table[bblst_last];
2004 sp->split_bbs.nr_members = el.nr_members;
2005 for (j = 0; j < el.nr_members; bblst_last++, j++)
2006 bblst_table[bblst_last] =
2007 TO_BLOCK (rgn_edges[el.first_member[j]]);
2008 sp->update_bbs.first_member = &bblst_table[bblst_last];
2010 for (j = 0; j < el.nr_members; j++)
2012 check_block = FROM_BLOCK (rgn_edges[el.first_member[j]]);
2013 fst_edge = nxt_edge = OUT_EDGES (check_block);
2016 for (k = 0; k < el.nr_members; k++)
2017 if (EDGE_TO_BIT (nxt_edge) == el.first_member[k])
2020 if (k >= el.nr_members)
2022 bblst_table[bblst_last++] = TO_BLOCK (nxt_edge);
2026 nxt_edge = NEXT_OUT (nxt_edge);
2028 while (fst_edge != nxt_edge);
2030 sp->update_bbs.nr_members = update_idx;
2035 sp->split_bbs.nr_members = sp->update_bbs.nr_members = 0;
2037 sp->is_speculative = 0;
2041 } /* compute_trg_info */
2044 /* Print candidates info, for debugging purposes. Callable from debugger. */
2050 if (!candidate_table[i].is_valid)
2053 if (candidate_table[i].is_speculative)
2056 fprintf (dump, "src b %d bb %d speculative \n", BB_TO_BLOCK (i), i);
2058 fprintf (dump, "split path: ");
2059 for (j = 0; j < candidate_table[i].split_bbs.nr_members; j++)
2061 int b = candidate_table[i].split_bbs.first_member[j];
2063 fprintf (dump, " %d ", b);
2065 fprintf (dump, "\n");
2067 fprintf (dump, "update path: ");
2068 for (j = 0; j < candidate_table[i].update_bbs.nr_members; j++)
2070 int b = candidate_table[i].update_bbs.first_member[j];
2072 fprintf (dump, " %d ", b);
2074 fprintf (dump, "\n");
2078 fprintf (dump, " src %d equivalent\n", BB_TO_BLOCK (i));
2083 /* Print candidates info, for debugging purposes. Callable from debugger. */
2086 debug_candidates (trg)
2091 fprintf (dump, "----------- candidate table: target: b=%d bb=%d ---\n",
2092 BB_TO_BLOCK (trg), trg);
2093 for (i = trg + 1; i < current_nr_blocks; i++)
2094 debug_candidate (i);
2098 /* functions for speculative scheduing */
2100 /* Return 0 if x is a set of a register alive in the beginning of one
2101 of the split-blocks of src, otherwise return 1. */
2104 check_live_1 (src, x)
2110 register rtx reg = SET_DEST (x);
2115 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
2116 || GET_CODE (reg) == SIGN_EXTRACT
2117 || GET_CODE (reg) == STRICT_LOW_PART)
2118 reg = XEXP (reg, 0);
2120 if (GET_CODE (reg) == PARALLEL
2121 && GET_MODE (reg) == BLKmode)
2124 for (i = XVECLEN (reg, 0) - 1; i >= 0; i--)
2125 if (check_live_1 (src, XVECEXP (reg, 0, i)))
2130 if (GET_CODE (reg) != REG)
2133 regno = REGNO (reg);
2135 if (regno < FIRST_PSEUDO_REGISTER && global_regs[regno])
2137 /* Global registers are assumed live */
2142 if (regno < FIRST_PSEUDO_REGISTER)
2144 /* check for hard registers */
2145 int j = HARD_REGNO_NREGS (regno, GET_MODE (reg));
2148 for (i = 0; i < candidate_table[src].split_bbs.nr_members; i++)
2150 int b = candidate_table[src].split_bbs.first_member[i];
2152 if (REGNO_REG_SET_P (basic_block_live_at_start[b], regno + j))
2161 /* check for psuedo registers */
2162 for (i = 0; i < candidate_table[src].split_bbs.nr_members; i++)
2164 int b = candidate_table[src].split_bbs.first_member[i];
2166 if (REGNO_REG_SET_P (basic_block_live_at_start[b], regno))
2178 /* If x is a set of a register R, mark that R is alive in the beginning
2179 of every update-block of src. */
2182 update_live_1 (src, x)
2188 register rtx reg = SET_DEST (x);
2193 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
2194 || GET_CODE (reg) == SIGN_EXTRACT
2195 || GET_CODE (reg) == STRICT_LOW_PART)
2196 reg = XEXP (reg, 0);
2198 if (GET_CODE (reg) == PARALLEL
2199 && GET_MODE (reg) == BLKmode)
2202 for (i = XVECLEN (reg, 0) - 1; i >= 0; i--)
2203 update_live_1 (src, XVECEXP (reg, 0, i));
2207 if (GET_CODE (reg) != REG)
2210 /* Global registers are always live, so the code below does not apply
2213 regno = REGNO (reg);
2215 if (regno >= FIRST_PSEUDO_REGISTER || !global_regs[regno])
2217 if (regno < FIRST_PSEUDO_REGISTER)
2219 int j = HARD_REGNO_NREGS (regno, GET_MODE (reg));
2222 for (i = 0; i < candidate_table[src].update_bbs.nr_members; i++)
2224 int b = candidate_table[src].update_bbs.first_member[i];
2226 SET_REGNO_REG_SET (basic_block_live_at_start[b], regno + j);
2232 for (i = 0; i < candidate_table[src].update_bbs.nr_members; i++)
2234 int b = candidate_table[src].update_bbs.first_member[i];
2236 SET_REGNO_REG_SET (basic_block_live_at_start[b], regno);
2243 /* Return 1 if insn can be speculatively moved from block src to trg,
2244 otherwise return 0. Called before first insertion of insn to
2245 ready-list or before the scheduling. */
2248 check_live (insn, src)
2252 /* find the registers set by instruction */
2253 if (GET_CODE (PATTERN (insn)) == SET
2254 || GET_CODE (PATTERN (insn)) == CLOBBER)
2255 return check_live_1 (src, PATTERN (insn));
2256 else if (GET_CODE (PATTERN (insn)) == PARALLEL)
2259 for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--)
2260 if ((GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == SET
2261 || GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == CLOBBER)
2262 && !check_live_1 (src, XVECEXP (PATTERN (insn), 0, j)))
2272 /* Update the live registers info after insn was moved speculatively from
2273 block src to trg. */
2276 update_live (insn, src)
2280 /* find the registers set by instruction */
2281 if (GET_CODE (PATTERN (insn)) == SET
2282 || GET_CODE (PATTERN (insn)) == CLOBBER)
2283 update_live_1 (src, PATTERN (insn));
2284 else if (GET_CODE (PATTERN (insn)) == PARALLEL)
2287 for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--)
2288 if (GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == SET
2289 || GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == CLOBBER)
2290 update_live_1 (src, XVECEXP (PATTERN (insn), 0, j));
2294 /* Exception Free Loads:
2296 We define five classes of speculative loads: IFREE, IRISKY,
2297 PFREE, PRISKY, and MFREE.
2299 IFREE loads are loads that are proved to be exception-free, just
2300 by examining the load insn. Examples for such loads are loads
2301 from TOC and loads of global data.
2303 IRISKY loads are loads that are proved to be exception-risky,
2304 just by examining the load insn. Examples for such loads are
2305 volatile loads and loads from shared memory.
2307 PFREE loads are loads for which we can prove, by examining other
2308 insns, that they are exception-free. Currently, this class consists
2309 of loads for which we are able to find a "similar load", either in
2310 the target block, or, if only one split-block exists, in that split
2311 block. Load2 is similar to load1 if both have same single base
2312 register. We identify only part of the similar loads, by finding
2313 an insn upon which both load1 and load2 have a DEF-USE dependence.
2315 PRISKY loads are loads for which we can prove, by examining other
2316 insns, that they are exception-risky. Currently we have two proofs for
2317 such loads. The first proof detects loads that are probably guarded by a
2318 test on the memory address. This proof is based on the
2319 backward and forward data dependence information for the region.
2320 Let load-insn be the examined load.
2321 Load-insn is PRISKY iff ALL the following hold:
2323 - insn1 is not in the same block as load-insn
2324 - there is a DEF-USE dependence chain (insn1, ..., load-insn)
2325 - test-insn is either a compare or a branch, not in the same block as load-insn
2326 - load-insn is reachable from test-insn
2327 - there is a DEF-USE dependence chain (insn1, ..., test-insn)
2329 This proof might fail when the compare and the load are fed
2330 by an insn not in the region. To solve this, we will add to this
2331 group all loads that have no input DEF-USE dependence.
2333 The second proof detects loads that are directly or indirectly
2334 fed by a speculative load. This proof is affected by the
2335 scheduling process. We will use the flag fed_by_spec_load.
2336 Initially, all insns have this flag reset. After a speculative
2337 motion of an insn, if insn is either a load, or marked as
2338 fed_by_spec_load, we will also mark as fed_by_spec_load every
2339 insn1 for which a DEF-USE dependence (insn, insn1) exists. A
2340 load which is fed_by_spec_load is also PRISKY.
2342 MFREE (maybe-free) loads are all the remaining loads. They may be
2343 exception-free, but we cannot prove it.
2345 Now, all loads in IFREE and PFREE classes are considered
2346 exception-free, while all loads in IRISKY and PRISKY classes are
2347 considered exception-risky. As for loads in the MFREE class,
2348 these are considered either exception-free or exception-risky,
2349 depending on whether we are pessimistic or optimistic. We have
2350 to take the pessimistic approach to assure the safety of
2351 speculative scheduling, but we can take the optimistic approach
2352 by invoking the -fsched_spec_load_dangerous option. */
2354 enum INSN_TRAP_CLASS
2356 TRAP_FREE = 0, IFREE = 1, PFREE_CANDIDATE = 2,
2357 PRISKY_CANDIDATE = 3, IRISKY = 4, TRAP_RISKY = 5
2360 #define WORST_CLASS(class1, class2) \
2361 ((class1 > class2) ? class1 : class2)
2363 /* Indexed by INSN_UID, and set if there's DEF-USE dependence between */
2364 /* some speculatively moved load insn and this one. */
2365 char *fed_by_spec_load;
2368 /* Non-zero if block bb_to is equal to, or reachable from block bb_from. */
2369 #define IS_REACHABLE(bb_from, bb_to) \
2371 || IS_RGN_ENTRY (bb_from) \
2372 || (bitset_member (ancestor_edges[bb_to], \
2373 EDGE_TO_BIT (IN_EDGES (BB_TO_BLOCK (bb_from))), \
2375 #define FED_BY_SPEC_LOAD(insn) (fed_by_spec_load[INSN_UID (insn)])
2376 #define IS_LOAD_INSN(insn) (is_load_insn[INSN_UID (insn)])
2378 /* Non-zero iff the address is comprised from at most 1 register */
2379 #define CONST_BASED_ADDRESS_P(x) \
2380 (GET_CODE (x) == REG \
2381 || ((GET_CODE (x) == PLUS || GET_CODE (x) == MINUS \
2382 || (GET_CODE (x) == LO_SUM)) \
2383 && (GET_CODE (XEXP (x, 0)) == CONST_INT \
2384 || GET_CODE (XEXP (x, 1)) == CONST_INT)))
2386 /* Turns on the fed_by_spec_load flag for insns fed by load_insn. */
2389 set_spec_fed (load_insn)
2394 for (link = INSN_DEPEND (load_insn); link; link = XEXP (link, 1))
2395 if (GET_MODE (link) == VOIDmode)
2396 FED_BY_SPEC_LOAD (XEXP (link, 0)) = 1;
2397 } /* set_spec_fed */
2399 /* On the path from the insn to load_insn_bb, find a conditional branch */
2400 /* depending on insn, that guards the speculative load. */
2403 find_conditional_protection (insn, load_insn_bb)
2409 /* iterate through DEF-USE forward dependences */
2410 for (link = INSN_DEPEND (insn); link; link = XEXP (link, 1))
2412 rtx next = XEXP (link, 0);
2413 if ((CONTAINING_RGN (INSN_BLOCK (next)) ==
2414 CONTAINING_RGN (BB_TO_BLOCK (load_insn_bb)))
2415 && IS_REACHABLE (INSN_BB (next), load_insn_bb)
2416 && load_insn_bb != INSN_BB (next)
2417 && GET_MODE (link) == VOIDmode
2418 && (GET_CODE (next) == JUMP_INSN
2419 || find_conditional_protection (next, load_insn_bb)))
2423 } /* find_conditional_protection */
2425 /* Returns 1 if the same insn1 that participates in the computation
2426 of load_insn's address is feeding a conditional branch that is
2427 guarding on load_insn. This is true if we find a the two DEF-USE
2429 insn1 -> ... -> conditional-branch
2430 insn1 -> ... -> load_insn,
2431 and if a flow path exist:
2432 insn1 -> ... -> conditional-branch -> ... -> load_insn,
2433 and if insn1 is on the path
2434 region-entry -> ... -> bb_trg -> ... load_insn.
2436 Locate insn1 by climbing on LOG_LINKS from load_insn.
2437 Locate the branch by following INSN_DEPEND from insn1. */
2440 is_conditionally_protected (load_insn, bb_src, bb_trg)
2446 for (link = LOG_LINKS (load_insn); link; link = XEXP (link, 1))
2448 rtx insn1 = XEXP (link, 0);
2450 /* must be a DEF-USE dependence upon non-branch */
2451 if (GET_MODE (link) != VOIDmode
2452 || GET_CODE (insn1) == JUMP_INSN)
2455 /* must exist a path: region-entry -> ... -> bb_trg -> ... load_insn */
2456 if (INSN_BB (insn1) == bb_src
2457 || (CONTAINING_RGN (INSN_BLOCK (insn1))
2458 != CONTAINING_RGN (BB_TO_BLOCK (bb_src)))
2459 || (!IS_REACHABLE (bb_trg, INSN_BB (insn1))
2460 && !IS_REACHABLE (INSN_BB (insn1), bb_trg)))
2463 /* now search for the conditional-branch */
2464 if (find_conditional_protection (insn1, bb_src))
2467 /* recursive step: search another insn1, "above" current insn1. */
2468 return is_conditionally_protected (insn1, bb_src, bb_trg);
2471 /* the chain does not exsist */
2473 } /* is_conditionally_protected */
2475 /* Returns 1 if a clue for "similar load" 'insn2' is found, and hence
2476 load_insn can move speculatively from bb_src to bb_trg. All the
2477 following must hold:
2479 (1) both loads have 1 base register (PFREE_CANDIDATEs).
2480 (2) load_insn and load1 have a def-use dependence upon
2481 the same insn 'insn1'.
2482 (3) either load2 is in bb_trg, or:
2483 - there's only one split-block, and
2484 - load1 is on the escape path, and
2486 From all these we can conclude that the two loads access memory
2487 addresses that differ at most by a constant, and hence if moving
2488 load_insn would cause an exception, it would have been caused by
2492 is_pfree (load_insn, bb_src, bb_trg)
2497 register candidate *candp = candidate_table + bb_src;
2499 if (candp->split_bbs.nr_members != 1)
2500 /* must have exactly one escape block */
2503 for (back_link = LOG_LINKS (load_insn);
2504 back_link; back_link = XEXP (back_link, 1))
2506 rtx insn1 = XEXP (back_link, 0);
2508 if (GET_MODE (back_link) == VOIDmode)
2510 /* found a DEF-USE dependence (insn1, load_insn) */
2513 for (fore_link = INSN_DEPEND (insn1);
2514 fore_link; fore_link = XEXP (fore_link, 1))
2516 rtx insn2 = XEXP (fore_link, 0);
2517 if (GET_MODE (fore_link) == VOIDmode)
2519 /* found a DEF-USE dependence (insn1, insn2) */
2520 if (haifa_classify_insn (insn2) != PFREE_CANDIDATE)
2521 /* insn2 not guaranteed to be a 1 base reg load */
2524 if (INSN_BB (insn2) == bb_trg)
2525 /* insn2 is the similar load, in the target block */
2528 if (*(candp->split_bbs.first_member) == INSN_BLOCK (insn2))
2529 /* insn2 is a similar load, in a split-block */
2536 /* couldn't find a similar load */
2540 /* Returns a class that insn with GET_DEST(insn)=x may belong to,
2541 as found by analyzing insn's expression. */
2544 may_trap_exp (x, is_store)
2552 code = GET_CODE (x);
2562 /* The insn uses memory */
2563 /* a volatile load */
2564 if (MEM_VOLATILE_P (x))
2566 /* an exception-free load */
2567 if (!may_trap_p (x))
2569 /* a load with 1 base register, to be further checked */
2570 if (CONST_BASED_ADDRESS_P (XEXP (x, 0)))
2571 return PFREE_CANDIDATE;
2572 /* no info on the load, to be further checked */
2573 return PRISKY_CANDIDATE;
2578 int i, insn_class = TRAP_FREE;
2580 /* neither store nor load, check if it may cause a trap */
2583 /* recursive step: walk the insn... */
2584 fmt = GET_RTX_FORMAT (code);
2585 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2589 int tmp_class = may_trap_exp (XEXP (x, i), is_store);
2590 insn_class = WORST_CLASS (insn_class, tmp_class);
2592 else if (fmt[i] == 'E')
2595 for (j = 0; j < XVECLEN (x, i); j++)
2597 int tmp_class = may_trap_exp (XVECEXP (x, i, j), is_store);
2598 insn_class = WORST_CLASS (insn_class, tmp_class);
2599 if (insn_class == TRAP_RISKY || insn_class == IRISKY)
2603 if (insn_class == TRAP_RISKY || insn_class == IRISKY)
2608 } /* may_trap_exp */
2611 /* Classifies insn for the purpose of verifying that it can be
2612 moved speculatively, by examining it's patterns, returning:
2613 TRAP_RISKY: store, or risky non-load insn (e.g. division by variable).
2614 TRAP_FREE: non-load insn.
2615 IFREE: load from a globaly safe location.
2616 IRISKY: volatile load.
2617 PFREE_CANDIDATE, PRISKY_CANDIDATE: load that need to be checked for
2618 being either PFREE or PRISKY. */
2621 haifa_classify_insn (insn)
2624 rtx pat = PATTERN (insn);
2625 int tmp_class = TRAP_FREE;
2626 int insn_class = TRAP_FREE;
2629 if (GET_CODE (pat) == PARALLEL)
2631 int i, len = XVECLEN (pat, 0);
2633 for (i = len - 1; i >= 0; i--)
2635 code = GET_CODE (XVECEXP (pat, 0, i));
2639 /* test if it is a 'store' */
2640 tmp_class = may_trap_exp (XEXP (XVECEXP (pat, 0, i), 0), 1);
2643 /* test if it is a store */
2644 tmp_class = may_trap_exp (SET_DEST (XVECEXP (pat, 0, i)), 1);
2645 if (tmp_class == TRAP_RISKY)
2647 /* test if it is a load */
2649 WORST_CLASS (tmp_class,
2650 may_trap_exp (SET_SRC (XVECEXP (pat, 0, i)), 0));
2653 tmp_class = TRAP_RISKY;
2657 insn_class = WORST_CLASS (insn_class, tmp_class);
2658 if (insn_class == TRAP_RISKY || insn_class == IRISKY)
2664 code = GET_CODE (pat);
2668 /* test if it is a 'store' */
2669 tmp_class = may_trap_exp (XEXP (pat, 0), 1);
2672 /* test if it is a store */
2673 tmp_class = may_trap_exp (SET_DEST (pat), 1);
2674 if (tmp_class == TRAP_RISKY)
2676 /* test if it is a load */
2678 WORST_CLASS (tmp_class,
2679 may_trap_exp (SET_SRC (pat), 0));
2682 tmp_class = TRAP_RISKY;
2686 insn_class = tmp_class;
2691 } /* haifa_classify_insn */
2693 /* Return 1 if load_insn is prisky (i.e. if load_insn is fed by
2694 a load moved speculatively, or if load_insn is protected by
2695 a compare on load_insn's address). */
2698 is_prisky (load_insn, bb_src, bb_trg)
2702 if (FED_BY_SPEC_LOAD (load_insn))
2705 if (LOG_LINKS (load_insn) == NULL)
2706 /* dependence may 'hide' out of the region. */
2709 if (is_conditionally_protected (load_insn, bb_src, bb_trg))
2715 /* Insn is a candidate to be moved speculatively from bb_src to bb_trg.
2716 Return 1 if insn is exception-free (and the motion is valid)
2720 is_exception_free (insn, bb_src, bb_trg)
2724 int insn_class = haifa_classify_insn (insn);
2726 /* handle non-load insns */
2737 if (!flag_schedule_speculative_load)
2739 IS_LOAD_INSN (insn) = 1;
2746 case PFREE_CANDIDATE:
2747 if (is_pfree (insn, bb_src, bb_trg))
2749 /* don't 'break' here: PFREE-candidate is also PRISKY-candidate */
2750 case PRISKY_CANDIDATE:
2751 if (!flag_schedule_speculative_load_dangerous
2752 || is_prisky (insn, bb_src, bb_trg))
2758 return flag_schedule_speculative_load_dangerous;
2759 } /* is_exception_free */
2762 /* Process an insn's memory dependencies. There are four kinds of
2765 (0) read dependence: read follows read
2766 (1) true dependence: read follows write
2767 (2) anti dependence: write follows read
2768 (3) output dependence: write follows write
2770 We are careful to build only dependencies which actually exist, and
2771 use transitivity to avoid building too many links. */
2773 /* Return the INSN_LIST containing INSN in LIST, or NULL
2774 if LIST does not contain INSN. */
2776 HAIFA_INLINE static rtx
2777 find_insn_list (insn, list)
2783 if (XEXP (list, 0) == insn)
2785 list = XEXP (list, 1);
2791 /* Return 1 if the pair (insn, x) is found in (LIST, LIST1), or 0 otherwise. */
2793 HAIFA_INLINE static char
2794 find_insn_mem_list (insn, x, list, list1)
2800 if (XEXP (list, 0) == insn
2801 && XEXP (list1, 0) == x)
2803 list = XEXP (list, 1);
2804 list1 = XEXP (list1, 1);
2810 /* Compute the function units used by INSN. This caches the value
2811 returned by function_units_used. A function unit is encoded as the
2812 unit number if the value is non-negative and the compliment of a
2813 mask if the value is negative. A function unit index is the
2814 non-negative encoding. */
2816 HAIFA_INLINE static int
2820 register int unit = INSN_UNIT (insn);
2824 recog_memoized (insn);
2826 /* A USE insn, or something else we don't need to understand.
2827 We can't pass these directly to function_units_used because it will
2828 trigger a fatal error for unrecognizable insns. */
2829 if (INSN_CODE (insn) < 0)
2833 unit = function_units_used (insn);
2834 /* Increment non-negative values so we can cache zero. */
2838 /* We only cache 16 bits of the result, so if the value is out of
2839 range, don't cache it. */
2840 if (FUNCTION_UNITS_SIZE < HOST_BITS_PER_SHORT
2842 || (~unit & ((1 << (HOST_BITS_PER_SHORT - 1)) - 1)) == 0)
2843 INSN_UNIT (insn) = unit;
2845 return (unit > 0 ? unit - 1 : unit);
2848 /* Compute the blockage range for executing INSN on UNIT. This caches
2849 the value returned by the blockage_range_function for the unit.
2850 These values are encoded in an int where the upper half gives the
2851 minimum value and the lower half gives the maximum value. */
2853 HAIFA_INLINE static unsigned int
2854 blockage_range (unit, insn)
2858 unsigned int blockage = INSN_BLOCKAGE (insn);
2861 if (UNIT_BLOCKED (blockage) != unit + 1)
2863 range = function_units[unit].blockage_range_function (insn);
2864 /* We only cache the blockage range for one unit and then only if
2866 if (HOST_BITS_PER_INT >= UNIT_BITS + 2 * BLOCKAGE_BITS)
2867 INSN_BLOCKAGE (insn) = ENCODE_BLOCKAGE (unit + 1, range);
2870 range = BLOCKAGE_RANGE (blockage);
2875 /* A vector indexed by function unit instance giving the last insn to use
2876 the unit. The value of the function unit instance index for unit U
2877 instance I is (U + I * FUNCTION_UNITS_SIZE). */
2878 static rtx unit_last_insn[FUNCTION_UNITS_SIZE * MAX_MULTIPLICITY];
2880 /* A vector indexed by function unit instance giving the minimum time when
2881 the unit will unblock based on the maximum blockage cost. */
2882 static int unit_tick[FUNCTION_UNITS_SIZE * MAX_MULTIPLICITY];
2884 /* A vector indexed by function unit number giving the number of insns
2885 that remain to use the unit. */
2886 static int unit_n_insns[FUNCTION_UNITS_SIZE];
2888 /* Reset the function unit state to the null state. */
2893 bzero ((char *) unit_last_insn, sizeof (unit_last_insn));
2894 bzero ((char *) unit_tick, sizeof (unit_tick));
2895 bzero ((char *) unit_n_insns, sizeof (unit_n_insns));
2898 /* Return the issue-delay of an insn */
2900 HAIFA_INLINE static int
2901 insn_issue_delay (insn)
2905 int unit = insn_unit (insn);
2907 /* efficiency note: in fact, we are working 'hard' to compute a
2908 value that was available in md file, and is not available in
2909 function_units[] structure. It would be nice to have this
2910 value there, too. */
2913 if (function_units[unit].blockage_range_function &&
2914 function_units[unit].blockage_function)
2915 delay = function_units[unit].blockage_function (insn, insn);
2918 for (i = 0, unit = ~unit; unit; i++, unit >>= 1)
2919 if ((unit & 1) != 0 && function_units[i].blockage_range_function
2920 && function_units[i].blockage_function)
2921 delay = MAX (delay, function_units[i].blockage_function (insn, insn));
2926 /* Return the actual hazard cost of executing INSN on the unit UNIT,
2927 instance INSTANCE at time CLOCK if the previous actual hazard cost
2930 HAIFA_INLINE static int
2931 actual_hazard_this_instance (unit, instance, insn, clock, cost)
2932 int unit, instance, clock, cost;
2935 int tick = unit_tick[instance]; /* issue time of the last issued insn */
2937 if (tick - clock > cost)
2939 /* The scheduler is operating forward, so unit's last insn is the
2940 executing insn and INSN is the candidate insn. We want a
2941 more exact measure of the blockage if we execute INSN at CLOCK
2942 given when we committed the execution of the unit's last insn.
2944 The blockage value is given by either the unit's max blockage
2945 constant, blockage range function, or blockage function. Use
2946 the most exact form for the given unit. */
2948 if (function_units[unit].blockage_range_function)
2950 if (function_units[unit].blockage_function)
2951 tick += (function_units[unit].blockage_function
2952 (unit_last_insn[instance], insn)
2953 - function_units[unit].max_blockage);
2955 tick += ((int) MAX_BLOCKAGE_COST (blockage_range (unit, insn))
2956 - function_units[unit].max_blockage);
2958 if (tick - clock > cost)
2959 cost = tick - clock;
2964 /* Record INSN as having begun execution on the units encoded by UNIT at
2967 HAIFA_INLINE static void
2968 schedule_unit (unit, insn, clock)
2976 int instance = unit;
2977 #if MAX_MULTIPLICITY > 1
2978 /* Find the first free instance of the function unit and use that
2979 one. We assume that one is free. */
2980 for (i = function_units[unit].multiplicity - 1; i > 0; i--)
2982 if (!actual_hazard_this_instance (unit, instance, insn, clock, 0))
2984 instance += FUNCTION_UNITS_SIZE;
2987 unit_last_insn[instance] = insn;
2988 unit_tick[instance] = (clock + function_units[unit].max_blockage);
2991 for (i = 0, unit = ~unit; unit; i++, unit >>= 1)
2992 if ((unit & 1) != 0)
2993 schedule_unit (i, insn, clock);
2996 /* Return the actual hazard cost of executing INSN on the units encoded by
2997 UNIT at time CLOCK if the previous actual hazard cost was COST. */
2999 HAIFA_INLINE static int
3000 actual_hazard (unit, insn, clock, cost)
3001 int unit, clock, cost;
3008 /* Find the instance of the function unit with the minimum hazard. */
3009 int instance = unit;
3010 int best_cost = actual_hazard_this_instance (unit, instance, insn,
3014 #if MAX_MULTIPLICITY > 1
3015 if (best_cost > cost)
3017 for (i = function_units[unit].multiplicity - 1; i > 0; i--)
3019 instance += FUNCTION_UNITS_SIZE;
3020 this_cost = actual_hazard_this_instance (unit, instance, insn,
3022 if (this_cost < best_cost)
3024 best_cost = this_cost;
3025 if (this_cost <= cost)
3031 cost = MAX (cost, best_cost);
3034 for (i = 0, unit = ~unit; unit; i++, unit >>= 1)
3035 if ((unit & 1) != 0)
3036 cost = actual_hazard (i, insn, clock, cost);
3041 /* Return the potential hazard cost of executing an instruction on the
3042 units encoded by UNIT if the previous potential hazard cost was COST.
3043 An insn with a large blockage time is chosen in preference to one
3044 with a smaller time; an insn that uses a unit that is more likely
3045 to be used is chosen in preference to one with a unit that is less
3046 used. We are trying to minimize a subsequent actual hazard. */
3048 HAIFA_INLINE static int
3049 potential_hazard (unit, insn, cost)
3054 unsigned int minb, maxb;
3058 minb = maxb = function_units[unit].max_blockage;
3061 if (function_units[unit].blockage_range_function)
3063 maxb = minb = blockage_range (unit, insn);
3064 maxb = MAX_BLOCKAGE_COST (maxb);
3065 minb = MIN_BLOCKAGE_COST (minb);
3070 /* Make the number of instructions left dominate. Make the
3071 minimum delay dominate the maximum delay. If all these
3072 are the same, use the unit number to add an arbitrary
3073 ordering. Other terms can be added. */
3074 ncost = minb * 0x40 + maxb;
3075 ncost *= (unit_n_insns[unit] - 1) * 0x1000 + unit;
3082 for (i = 0, unit = ~unit; unit; i++, unit >>= 1)
3083 if ((unit & 1) != 0)
3084 cost = potential_hazard (i, insn, cost);
3089 /* Compute cost of executing INSN given the dependence LINK on the insn USED.
3090 This is the number of cycles between instruction issue and
3091 instruction results. */
3093 HAIFA_INLINE static int
3094 insn_cost (insn, link, used)
3095 rtx insn, link, used;
3097 register int cost = INSN_COST (insn);
3101 recog_memoized (insn);
3103 /* A USE insn, or something else we don't need to understand.
3104 We can't pass these directly to result_ready_cost because it will
3105 trigger a fatal error for unrecognizable insns. */
3106 if (INSN_CODE (insn) < 0)
3108 INSN_COST (insn) = 1;
3113 cost = result_ready_cost (insn);
3118 INSN_COST (insn) = cost;
3122 /* in this case estimate cost without caring how insn is used. */
3123 if (link == 0 && used == 0)
3126 /* A USE insn should never require the value used to be computed. This
3127 allows the computation of a function's result and parameter values to
3128 overlap the return and call. */
3129 recog_memoized (used);
3130 if (INSN_CODE (used) < 0)
3131 LINK_COST_FREE (link) = 1;
3133 /* If some dependencies vary the cost, compute the adjustment. Most
3134 commonly, the adjustment is complete: either the cost is ignored
3135 (in the case of an output- or anti-dependence), or the cost is
3136 unchanged. These values are cached in the link as LINK_COST_FREE
3137 and LINK_COST_ZERO. */
3139 if (LINK_COST_FREE (link))
3142 else if (!LINK_COST_ZERO (link))
3146 ADJUST_COST (used, link, insn, ncost);
3148 LINK_COST_FREE (link) = ncost = 1;
3150 LINK_COST_ZERO (link) = 1;
3157 /* Compute the priority number for INSN. */
3166 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
3169 if ((this_priority = INSN_PRIORITY (insn)) == 0)
3171 if (INSN_DEPEND (insn) == 0)
3172 this_priority = insn_cost (insn, 0, 0);
3174 for (link = INSN_DEPEND (insn); link; link = XEXP (link, 1))
3179 if (RTX_INTEGRATED_P (link))
3182 next = XEXP (link, 0);
3184 /* critical path is meaningful in block boundaries only */
3185 if (INSN_BLOCK (next) != INSN_BLOCK (insn))
3188 next_priority = insn_cost (insn, link, next) + priority (next);
3189 if (next_priority > this_priority)
3190 this_priority = next_priority;
3192 INSN_PRIORITY (insn) = this_priority;
3194 return this_priority;
3198 /* Remove all INSN_LISTs and EXPR_LISTs from the pending lists and add
3199 them to the unused_*_list variables, so that they can be reused. */
3202 free_pending_lists ()
3204 if (current_nr_blocks <= 1)
3206 free_list (&pending_read_insns, &unused_insn_list);
3207 free_list (&pending_write_insns, &unused_insn_list);
3208 free_list (&pending_read_mems, &unused_expr_list);
3209 free_list (&pending_write_mems, &unused_expr_list);
3213 /* interblock scheduling */
3216 for (bb = 0; bb < current_nr_blocks; bb++)
3218 free_list (&bb_pending_read_insns[bb], &unused_insn_list);
3219 free_list (&bb_pending_write_insns[bb], &unused_insn_list);
3220 free_list (&bb_pending_read_mems[bb], &unused_expr_list);
3221 free_list (&bb_pending_write_mems[bb], &unused_expr_list);
3226 /* Add an INSN and MEM reference pair to a pending INSN_LIST and MEM_LIST.
3227 The MEM is a memory reference contained within INSN, which we are saving
3228 so that we can do memory aliasing on it. */
3231 add_insn_mem_dependence (insn_list, mem_list, insn, mem)
3232 rtx *insn_list, *mem_list, insn, mem;
3236 link = alloc_INSN_LIST (insn, *insn_list);
3239 link = alloc_EXPR_LIST (VOIDmode, mem, *mem_list);
3242 pending_lists_length++;
3246 /* Make a dependency between every memory reference on the pending lists
3247 and INSN, thus flushing the pending lists. If ONLY_WRITE, don't flush
3251 flush_pending_lists (insn, only_write)
3258 while (pending_read_insns && ! only_write)
3260 add_dependence (insn, XEXP (pending_read_insns, 0), REG_DEP_ANTI);
3262 link = pending_read_insns;
3263 pending_read_insns = XEXP (pending_read_insns, 1);
3264 XEXP (link, 1) = unused_insn_list;
3265 unused_insn_list = link;
3267 link = pending_read_mems;
3268 pending_read_mems = XEXP (pending_read_mems, 1);
3269 XEXP (link, 1) = unused_expr_list;
3270 unused_expr_list = link;
3272 while (pending_write_insns)
3274 add_dependence (insn, XEXP (pending_write_insns, 0), REG_DEP_ANTI);
3276 link = pending_write_insns;
3277 pending_write_insns = XEXP (pending_write_insns, 1);
3278 XEXP (link, 1) = unused_insn_list;
3279 unused_insn_list = link;
3281 link = pending_write_mems;
3282 pending_write_mems = XEXP (pending_write_mems, 1);
3283 XEXP (link, 1) = unused_expr_list;
3284 unused_expr_list = link;
3286 pending_lists_length = 0;
3288 /* last_pending_memory_flush is now a list of insns */
3289 for (u = last_pending_memory_flush; u; u = XEXP (u, 1))
3290 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
3292 free_list (&last_pending_memory_flush, &unused_insn_list);
3293 last_pending_memory_flush = alloc_INSN_LIST (insn, NULL_RTX);
3296 /* Analyze a single SET or CLOBBER rtx, X, creating all dependencies generated
3297 by the write to the destination of X, and reads of everything mentioned. */
3300 sched_analyze_1 (x, insn)
3305 register rtx dest = SET_DEST (x);
3310 if (GET_CODE (dest) == PARALLEL
3311 && GET_MODE (dest) == BLKmode)
3314 for (i = XVECLEN (dest, 0) - 1; i >= 0; i--)
3315 sched_analyze_1 (XVECEXP (dest, 0, i), insn);
3316 if (GET_CODE (x) == SET)
3317 sched_analyze_2 (SET_SRC (x), insn);
3321 while (GET_CODE (dest) == STRICT_LOW_PART || GET_CODE (dest) == SUBREG
3322 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SIGN_EXTRACT)
3324 if (GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SIGN_EXTRACT)
3326 /* The second and third arguments are values read by this insn. */
3327 sched_analyze_2 (XEXP (dest, 1), insn);
3328 sched_analyze_2 (XEXP (dest, 2), insn);
3330 dest = SUBREG_REG (dest);
3333 if (GET_CODE (dest) == REG)
3337 regno = REGNO (dest);
3339 /* A hard reg in a wide mode may really be multiple registers.
3340 If so, mark all of them just like the first. */
3341 if (regno < FIRST_PSEUDO_REGISTER)
3343 i = HARD_REGNO_NREGS (regno, GET_MODE (dest));
3348 for (u = reg_last_uses[regno + i]; u; u = XEXP (u, 1))
3349 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
3350 reg_last_uses[regno + i] = 0;
3352 for (u = reg_last_sets[regno + i]; u; u = XEXP (u, 1))
3353 add_dependence (insn, XEXP (u, 0), REG_DEP_OUTPUT);
3355 SET_REGNO_REG_SET (reg_pending_sets, regno + i);
3357 if ((call_used_regs[regno + i] || global_regs[regno + i]))
3358 /* Function calls clobber all call_used regs. */
3359 for (u = last_function_call; u; u = XEXP (u, 1))
3360 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
3367 for (u = reg_last_uses[regno]; u; u = XEXP (u, 1))
3368 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
3369 reg_last_uses[regno] = 0;
3371 for (u = reg_last_sets[regno]; u; u = XEXP (u, 1))
3372 add_dependence (insn, XEXP (u, 0), REG_DEP_OUTPUT);
3374 SET_REGNO_REG_SET (reg_pending_sets, regno);
3376 /* Pseudos that are REG_EQUIV to something may be replaced
3377 by that during reloading. We need only add dependencies for
3378 the address in the REG_EQUIV note. */
3379 if (!reload_completed
3380 && reg_known_equiv_p[regno]
3381 && GET_CODE (reg_known_value[regno]) == MEM)
3382 sched_analyze_2 (XEXP (reg_known_value[regno], 0), insn);
3384 /* Don't let it cross a call after scheduling if it doesn't
3385 already cross one. */
3387 if (REG_N_CALLS_CROSSED (regno) == 0)
3388 for (u = last_function_call; u; u = XEXP (u, 1))
3389 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
3392 else if (GET_CODE (dest) == MEM)
3394 /* Writing memory. */
3396 if (pending_lists_length > 32)
3398 /* Flush all pending reads and writes to prevent the pending lists
3399 from getting any larger. Insn scheduling runs too slowly when
3400 these lists get long. The number 32 was chosen because it
3401 seems like a reasonable number. When compiling GCC with itself,
3402 this flush occurs 8 times for sparc, and 10 times for m88k using
3404 flush_pending_lists (insn, 0);
3409 rtx pending, pending_mem;
3411 pending = pending_read_insns;
3412 pending_mem = pending_read_mems;
3415 /* If a dependency already exists, don't create a new one. */
3416 if (!find_insn_list (XEXP (pending, 0), LOG_LINKS (insn)))
3417 if (anti_dependence (XEXP (pending_mem, 0), dest))
3418 add_dependence (insn, XEXP (pending, 0), REG_DEP_ANTI);
3420 pending = XEXP (pending, 1);
3421 pending_mem = XEXP (pending_mem, 1);
3424 pending = pending_write_insns;
3425 pending_mem = pending_write_mems;
3428 /* If a dependency already exists, don't create a new one. */
3429 if (!find_insn_list (XEXP (pending, 0), LOG_LINKS (insn)))
3430 if (output_dependence (XEXP (pending_mem, 0), dest))
3431 add_dependence (insn, XEXP (pending, 0), REG_DEP_OUTPUT);
3433 pending = XEXP (pending, 1);
3434 pending_mem = XEXP (pending_mem, 1);
3437 for (u = last_pending_memory_flush; u; u = XEXP (u, 1))
3438 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
3440 add_insn_mem_dependence (&pending_write_insns, &pending_write_mems,
3443 sched_analyze_2 (XEXP (dest, 0), insn);
3446 /* Analyze reads. */
3447 if (GET_CODE (x) == SET)
3448 sched_analyze_2 (SET_SRC (x), insn);
3451 /* Analyze the uses of memory and registers in rtx X in INSN. */
3454 sched_analyze_2 (x, insn)
3460 register enum rtx_code code;
3466 code = GET_CODE (x);
3475 /* Ignore constants. Note that we must handle CONST_DOUBLE here
3476 because it may have a cc0_rtx in its CONST_DOUBLE_CHAIN field, but
3477 this does not mean that this insn is using cc0. */
3485 /* User of CC0 depends on immediately preceding insn. */
3486 SCHED_GROUP_P (insn) = 1;
3488 /* There may be a note before this insn now, but all notes will
3489 be removed before we actually try to schedule the insns, so
3490 it won't cause a problem later. We must avoid it here though. */
3491 prev = prev_nonnote_insn (insn);
3493 /* Make a copy of all dependencies on the immediately previous insn,
3494 and add to this insn. This is so that all the dependencies will
3495 apply to the group. Remove an explicit dependence on this insn
3496 as SCHED_GROUP_P now represents it. */
3498 if (find_insn_list (prev, LOG_LINKS (insn)))
3499 remove_dependence (insn, prev);
3501 for (link = LOG_LINKS (prev); link; link = XEXP (link, 1))
3502 add_dependence (insn, XEXP (link, 0), REG_NOTE_KIND (link));
3511 int regno = REGNO (x);
3512 if (regno < FIRST_PSEUDO_REGISTER)
3516 i = HARD_REGNO_NREGS (regno, GET_MODE (x));
3519 reg_last_uses[regno + i]
3520 = alloc_INSN_LIST (insn, reg_last_uses[regno + i]);
3522 for (u = reg_last_sets[regno + i]; u; u = XEXP (u, 1))
3523 add_dependence (insn, XEXP (u, 0), 0);
3525 if ((call_used_regs[regno + i] || global_regs[regno + i]))
3526 /* Function calls clobber all call_used regs. */
3527 for (u = last_function_call; u; u = XEXP (u, 1))
3528 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
3533 reg_last_uses[regno] = alloc_INSN_LIST (insn, reg_last_uses[regno]);
3535 for (u = reg_last_sets[regno]; u; u = XEXP (u, 1))
3536 add_dependence (insn, XEXP (u, 0), 0);
3538 /* Pseudos that are REG_EQUIV to something may be replaced
3539 by that during reloading. We need only add dependencies for
3540 the address in the REG_EQUIV note. */
3541 if (!reload_completed
3542 && reg_known_equiv_p[regno]
3543 && GET_CODE (reg_known_value[regno]) == MEM)
3544 sched_analyze_2 (XEXP (reg_known_value[regno], 0), insn);
3546 /* If the register does not already cross any calls, then add this
3547 insn to the sched_before_next_call list so that it will still
3548 not cross calls after scheduling. */
3549 if (REG_N_CALLS_CROSSED (regno) == 0)
3550 add_dependence (sched_before_next_call, insn, REG_DEP_ANTI);
3557 /* Reading memory. */
3559 rtx pending, pending_mem;
3561 pending = pending_read_insns;
3562 pending_mem = pending_read_mems;
3565 /* If a dependency already exists, don't create a new one. */
3566 if (!find_insn_list (XEXP (pending, 0), LOG_LINKS (insn)))
3567 if (read_dependence (XEXP (pending_mem, 0), x))
3568 add_dependence (insn, XEXP (pending, 0), REG_DEP_ANTI);
3570 pending = XEXP (pending, 1);
3571 pending_mem = XEXP (pending_mem, 1);
3574 pending = pending_write_insns;
3575 pending_mem = pending_write_mems;
3578 /* If a dependency already exists, don't create a new one. */
3579 if (!find_insn_list (XEXP (pending, 0), LOG_LINKS (insn)))
3580 if (true_dependence (XEXP (pending_mem, 0), VOIDmode,
3582 add_dependence (insn, XEXP (pending, 0), 0);
3584 pending = XEXP (pending, 1);
3585 pending_mem = XEXP (pending_mem, 1);
3588 for (u = last_pending_memory_flush; u; u = XEXP (u, 1))
3589 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
3591 /* Always add these dependencies to pending_reads, since
3592 this insn may be followed by a write. */
3593 add_insn_mem_dependence (&pending_read_insns, &pending_read_mems,
3596 /* Take advantage of tail recursion here. */
3597 sched_analyze_2 (XEXP (x, 0), insn);
3601 /* Force pending stores to memory in case a trap handler needs them. */
3603 flush_pending_lists (insn, 1);
3608 case UNSPEC_VOLATILE:
3612 /* Traditional and volatile asm instructions must be considered to use
3613 and clobber all hard registers, all pseudo-registers and all of
3614 memory. So must TRAP_IF and UNSPEC_VOLATILE operations.
3616 Consider for instance a volatile asm that changes the fpu rounding
3617 mode. An insn should not be moved across this even if it only uses
3618 pseudo-regs because it might give an incorrectly rounded result. */
3619 if (code != ASM_OPERANDS || MEM_VOLATILE_P (x))
3621 int max_reg = max_reg_num ();
3622 for (i = 0; i < max_reg; i++)
3624 for (u = reg_last_uses[i]; u; u = XEXP (u, 1))
3625 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
3626 reg_last_uses[i] = 0;
3628 /* reg_last_sets[r] is now a list of insns */
3629 for (u = reg_last_sets[i]; u; u = XEXP (u, 1))
3630 add_dependence (insn, XEXP (u, 0), 0);
3632 reg_pending_sets_all = 1;
3634 flush_pending_lists (insn, 0);
3637 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
3638 We can not just fall through here since then we would be confused
3639 by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
3640 traditional asms unlike their normal usage. */
3642 if (code == ASM_OPERANDS)
3644 for (j = 0; j < ASM_OPERANDS_INPUT_LENGTH (x); j++)
3645 sched_analyze_2 (ASM_OPERANDS_INPUT (x, j), insn);
3655 /* These both read and modify the result. We must handle them as writes
3656 to get proper dependencies for following instructions. We must handle
3657 them as reads to get proper dependencies from this to previous
3658 instructions. Thus we need to pass them to both sched_analyze_1
3659 and sched_analyze_2. We must call sched_analyze_2 first in order
3660 to get the proper antecedent for the read. */
3661 sched_analyze_2 (XEXP (x, 0), insn);
3662 sched_analyze_1 (x, insn);
3669 /* Other cases: walk the insn. */
3670 fmt = GET_RTX_FORMAT (code);
3671 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3674 sched_analyze_2 (XEXP (x, i), insn);
3675 else if (fmt[i] == 'E')
3676 for (j = 0; j < XVECLEN (x, i); j++)
3677 sched_analyze_2 (XVECEXP (x, i, j), insn);
3681 /* Analyze an INSN with pattern X to find all dependencies. */
3684 sched_analyze_insn (x, insn, loop_notes)
3688 register RTX_CODE code = GET_CODE (x);
3690 int maxreg = max_reg_num ();
3693 if (code == SET || code == CLOBBER)
3694 sched_analyze_1 (x, insn);
3695 else if (code == PARALLEL)
3698 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
3700 code = GET_CODE (XVECEXP (x, 0, i));
3701 if (code == SET || code == CLOBBER)
3702 sched_analyze_1 (XVECEXP (x, 0, i), insn);
3704 sched_analyze_2 (XVECEXP (x, 0, i), insn);
3708 sched_analyze_2 (x, insn);
3710 /* Mark registers CLOBBERED or used by called function. */
3711 if (GET_CODE (insn) == CALL_INSN)
3712 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
3714 if (GET_CODE (XEXP (link, 0)) == CLOBBER)
3715 sched_analyze_1 (XEXP (link, 0), insn);
3717 sched_analyze_2 (XEXP (link, 0), insn);
3720 /* If there is a {LOOP,EHREGION}_{BEG,END} note in the middle of a basic
3721 block, then we must be sure that no instructions are scheduled across it.
3722 Otherwise, the reg_n_refs info (which depends on loop_depth) would
3723 become incorrect. */
3727 int max_reg = max_reg_num ();
3728 int schedule_barrier_found = 0;
3731 /* Update loop_notes with any notes from this insn. Also determine
3732 if any of the notes on the list correspond to instruction scheduling
3733 barriers (loop, eh & setjmp notes, but not range notes. */
3735 while (XEXP (link, 1))
3737 if (INTVAL (XEXP (link, 0)) == NOTE_INSN_LOOP_BEG
3738 || INTVAL (XEXP (link, 0)) == NOTE_INSN_LOOP_END
3739 || INTVAL (XEXP (link, 0)) == NOTE_INSN_EH_REGION_BEG
3740 || INTVAL (XEXP (link, 0)) == NOTE_INSN_EH_REGION_END
3741 || INTVAL (XEXP (link, 0)) == NOTE_INSN_SETJMP)
3742 schedule_barrier_found = 1;
3744 link = XEXP (link, 1);
3746 XEXP (link, 1) = REG_NOTES (insn);
3747 REG_NOTES (insn) = loop_notes;
3749 /* Add dependencies if a scheduling barrier was found. */
3750 if (schedule_barrier_found)
3752 for (i = 0; i < max_reg; i++)
3755 for (u = reg_last_uses[i]; u; u = XEXP (u, 1))
3756 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
3757 reg_last_uses[i] = 0;
3759 /* reg_last_sets[r] is now a list of insns */
3760 for (u = reg_last_sets[i]; u; u = XEXP (u, 1))
3761 add_dependence (insn, XEXP (u, 0), 0);
3763 reg_pending_sets_all = 1;
3765 flush_pending_lists (insn, 0);
3770 EXECUTE_IF_SET_IN_REG_SET (reg_pending_sets, 0, i,
3772 /* reg_last_sets[r] is now a list of insns */
3773 free_list (®_last_sets[i], &unused_insn_list);
3775 = alloc_INSN_LIST (insn, NULL_RTX);
3777 CLEAR_REG_SET (reg_pending_sets);
3779 if (reg_pending_sets_all)
3781 for (i = 0; i < maxreg; i++)
3783 /* reg_last_sets[r] is now a list of insns */
3784 free_list (®_last_sets[i], &unused_insn_list);
3785 reg_last_sets[i] = alloc_INSN_LIST (insn, NULL_RTX);
3788 reg_pending_sets_all = 0;
3791 /* Handle function calls and function returns created by the epilogue
3793 if (GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN)
3798 /* When scheduling instructions, we make sure calls don't lose their
3799 accompanying USE insns by depending them one on another in order.
3801 Also, we must do the same thing for returns created by the epilogue
3802 threading code. Note this code works only in this special case,
3803 because other passes make no guarantee that they will never emit
3804 an instruction between a USE and a RETURN. There is such a guarantee
3805 for USE instructions immediately before a call. */
3807 prev_dep_insn = insn;
3808 dep_insn = PREV_INSN (insn);
3809 while (GET_CODE (dep_insn) == INSN
3810 && GET_CODE (PATTERN (dep_insn)) == USE
3811 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == REG)
3813 SCHED_GROUP_P (prev_dep_insn) = 1;
3815 /* Make a copy of all dependencies on dep_insn, and add to insn.
3816 This is so that all of the dependencies will apply to the
3819 for (link = LOG_LINKS (dep_insn); link; link = XEXP (link, 1))
3820 add_dependence (insn, XEXP (link, 0), REG_NOTE_KIND (link));
3822 prev_dep_insn = dep_insn;
3823 dep_insn = PREV_INSN (dep_insn);
3828 /* Analyze every insn between HEAD and TAIL inclusive, creating LOG_LINKS
3829 for every dependency. */
3832 sched_analyze (head, tail)
3839 for (insn = head;; insn = NEXT_INSN (insn))
3841 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN)
3843 /* Make each JUMP_INSN a scheduling barrier for memory references. */
3844 if (GET_CODE (insn) == JUMP_INSN)
3845 last_pending_memory_flush
3846 = alloc_INSN_LIST (insn, last_pending_memory_flush);
3847 sched_analyze_insn (PATTERN (insn), insn, loop_notes);
3850 else if (GET_CODE (insn) == CALL_INSN)
3855 CANT_MOVE (insn) = 1;
3857 /* Any instruction using a hard register which may get clobbered
3858 by a call needs to be marked as dependent on this call.
3859 This prevents a use of a hard return reg from being moved
3860 past a void call (i.e. it does not explicitly set the hard
3863 /* If this call is followed by a NOTE_INSN_SETJMP, then assume that
3864 all registers, not just hard registers, may be clobbered by this
3867 /* Insn, being a CALL_INSN, magically depends on
3868 `last_function_call' already. */
3870 if (NEXT_INSN (insn) && GET_CODE (NEXT_INSN (insn)) == NOTE
3871 && NOTE_LINE_NUMBER (NEXT_INSN (insn)) == NOTE_INSN_SETJMP)
3873 int max_reg = max_reg_num ();
3874 for (i = 0; i < max_reg; i++)
3876 for (u = reg_last_uses[i]; u; u = XEXP (u, 1))
3877 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
3879 reg_last_uses[i] = 0;
3881 /* reg_last_sets[r] is now a list of insns */
3882 for (u = reg_last_sets[i]; u; u = XEXP (u, 1))
3883 add_dependence (insn, XEXP (u, 0), 0);
3885 reg_pending_sets_all = 1;
3887 /* Add a pair of fake REG_NOTE which we will later
3888 convert back into a NOTE_INSN_SETJMP note. See
3889 reemit_notes for why we use a pair of NOTEs. */
3890 REG_NOTES (insn) = alloc_EXPR_LIST (REG_DEAD,
3893 REG_NOTES (insn) = alloc_EXPR_LIST (REG_DEAD,
3894 GEN_INT (NOTE_INSN_SETJMP),
3899 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3900 if (call_used_regs[i] || global_regs[i])
3902 for (u = reg_last_uses[i]; u; u = XEXP (u, 1))
3903 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
3904 reg_last_uses[i] = 0;
3906 /* reg_last_sets[r] is now a list of insns */
3907 for (u = reg_last_sets[i]; u; u = XEXP (u, 1))
3908 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
3910 SET_REGNO_REG_SET (reg_pending_sets, i);
3914 /* For each insn which shouldn't cross a call, add a dependence
3915 between that insn and this call insn. */
3916 x = LOG_LINKS (sched_before_next_call);
3919 add_dependence (insn, XEXP (x, 0), REG_DEP_ANTI);
3922 LOG_LINKS (sched_before_next_call) = 0;
3924 sched_analyze_insn (PATTERN (insn), insn, loop_notes);
3927 /* In the absence of interprocedural alias analysis, we must flush
3928 all pending reads and writes, and start new dependencies starting
3929 from here. But only flush writes for constant calls (which may
3930 be passed a pointer to something we haven't written yet). */
3931 flush_pending_lists (insn, CONST_CALL_P (insn));
3933 /* Depend this function call (actually, the user of this
3934 function call) on all hard register clobberage. */
3936 /* last_function_call is now a list of insns */
3937 free_list(&last_function_call, &unused_insn_list);
3938 last_function_call = alloc_INSN_LIST (insn, NULL_RTX);
3941 /* See comments on reemit_notes as to why we do this. */
3942 /* ??? Actually, the reemit_notes just say what is done, not why. */
3944 else if (GET_CODE (insn) == NOTE
3945 && (NOTE_LINE_NUMBER (insn) == NOTE_INSN_RANGE_START
3946 || NOTE_LINE_NUMBER (insn) == NOTE_INSN_RANGE_END))
3948 loop_notes = alloc_EXPR_LIST (REG_DEAD, NOTE_RANGE_INFO (insn),
3950 loop_notes = alloc_EXPR_LIST (REG_DEAD,
3951 GEN_INT (NOTE_LINE_NUMBER (insn)),
3954 else if (GET_CODE (insn) == NOTE
3955 && (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG
3956 || NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END
3957 || NOTE_LINE_NUMBER (insn) == NOTE_INSN_EH_REGION_BEG
3958 || NOTE_LINE_NUMBER (insn) == NOTE_INSN_EH_REGION_END
3959 || (NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP
3960 && GET_CODE (PREV_INSN (insn)) != CALL_INSN)))
3962 loop_notes = alloc_EXPR_LIST (REG_DEAD,
3963 GEN_INT (NOTE_BLOCK_NUMBER (insn)),
3965 loop_notes = alloc_EXPR_LIST (REG_DEAD,
3966 GEN_INT (NOTE_LINE_NUMBER (insn)),
3968 CONST_CALL_P (loop_notes) = CONST_CALL_P (insn);
3977 /* Called when we see a set of a register. If death is true, then we are
3978 scanning backwards. Mark that register as unborn. If nobody says
3979 otherwise, that is how things will remain. If death is false, then we
3980 are scanning forwards. Mark that register as being born. */
3983 sched_note_set (x, death)
3988 register rtx reg = SET_DEST (x);
3994 if (GET_CODE (reg) == PARALLEL
3995 && GET_MODE (reg) == BLKmode)
3998 for (i = XVECLEN (reg, 0) - 1; i >= 0; i--)
3999 sched_note_set (XVECEXP (reg, 0, i), death);
4003 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == STRICT_LOW_PART
4004 || GET_CODE (reg) == SIGN_EXTRACT || GET_CODE (reg) == ZERO_EXTRACT)
4006 /* Must treat modification of just one hardware register of a multi-reg
4007 value or just a byte field of a register exactly the same way that
4008 mark_set_1 in flow.c does, i.e. anything except a paradoxical subreg
4009 does not kill the entire register. */
4010 if (GET_CODE (reg) != SUBREG
4011 || REG_SIZE (SUBREG_REG (reg)) > REG_SIZE (reg))
4014 reg = SUBREG_REG (reg);
4017 if (GET_CODE (reg) != REG)
4020 /* Global registers are always live, so the code below does not apply
4023 regno = REGNO (reg);
4024 if (regno >= FIRST_PSEUDO_REGISTER || !global_regs[regno])
4028 /* If we only set part of the register, then this set does not
4033 /* Try killing this register. */
4034 if (regno < FIRST_PSEUDO_REGISTER)
4036 int j = HARD_REGNO_NREGS (regno, GET_MODE (reg));
4039 CLEAR_REGNO_REG_SET (bb_live_regs, regno + j);
4044 /* Recompute REG_BASIC_BLOCK as we update all the other
4045 dataflow information. */
4046 if (sched_reg_basic_block[regno] == REG_BLOCK_UNKNOWN)
4047 sched_reg_basic_block[regno] = current_block_num;
4048 else if (sched_reg_basic_block[regno] != current_block_num)
4049 sched_reg_basic_block[regno] = REG_BLOCK_GLOBAL;
4051 CLEAR_REGNO_REG_SET (bb_live_regs, regno);
4056 /* Make the register live again. */
4057 if (regno < FIRST_PSEUDO_REGISTER)
4059 int j = HARD_REGNO_NREGS (regno, GET_MODE (reg));
4062 SET_REGNO_REG_SET (bb_live_regs, regno + j);
4067 SET_REGNO_REG_SET (bb_live_regs, regno);
4073 /* Macros and functions for keeping the priority queue sorted, and
4074 dealing with queueing and dequeueing of instructions. */
4076 #define SCHED_SORT(READY, N_READY) \
4077 do { if ((N_READY) == 2) \
4078 swap_sort (READY, N_READY); \
4079 else if ((N_READY) > 2) \
4080 qsort (READY, N_READY, sizeof (rtx), rank_for_schedule); } \
4083 /* Returns a positive value if x is preferred; returns a negative value if
4084 y is preferred. Should never return 0, since that will make the sort
4088 rank_for_schedule (x, y)
4089 const GENERIC_PTR x;
4090 const GENERIC_PTR y;
4092 rtx tmp = *(rtx *)y;
4093 rtx tmp2 = *(rtx *)x;
4095 int tmp_class, tmp2_class, depend_count1, depend_count2;
4096 int val, priority_val, spec_val, prob_val, weight_val;
4099 /* prefer insn with higher priority */
4100 priority_val = INSN_PRIORITY (tmp2) - INSN_PRIORITY (tmp);
4102 return priority_val;
4104 /* prefer an insn with smaller contribution to registers-pressure */
4105 if (!reload_completed &&
4106 (weight_val = INSN_REG_WEIGHT (tmp) - INSN_REG_WEIGHT (tmp2)))
4107 return (weight_val);
4109 /* some comparison make sense in interblock scheduling only */
4110 if (INSN_BB (tmp) != INSN_BB (tmp2))
4112 /* prefer an inblock motion on an interblock motion */
4113 if ((INSN_BB (tmp2) == target_bb) && (INSN_BB (tmp) != target_bb))
4115 if ((INSN_BB (tmp) == target_bb) && (INSN_BB (tmp2) != target_bb))
4118 /* prefer a useful motion on a speculative one */
4119 if ((spec_val = IS_SPECULATIVE_INSN (tmp) - IS_SPECULATIVE_INSN (tmp2)))
4122 /* prefer a more probable (speculative) insn */
4123 prob_val = INSN_PROBABILITY (tmp2) - INSN_PROBABILITY (tmp);
4128 /* compare insns based on their relation to the last-scheduled-insn */
4129 if (last_scheduled_insn)
4131 /* Classify the instructions into three classes:
4132 1) Data dependent on last schedule insn.
4133 2) Anti/Output dependent on last scheduled insn.
4134 3) Independent of last scheduled insn, or has latency of one.
4135 Choose the insn from the highest numbered class if different. */
4136 link = find_insn_list (tmp, INSN_DEPEND (last_scheduled_insn));
4137 if (link == 0 || insn_cost (last_scheduled_insn, link, tmp) == 1)
4139 else if (REG_NOTE_KIND (link) == 0) /* Data dependence. */
4144 link = find_insn_list (tmp2, INSN_DEPEND (last_scheduled_insn));
4145 if (link == 0 || insn_cost (last_scheduled_insn, link, tmp2) == 1)
4147 else if (REG_NOTE_KIND (link) == 0) /* Data dependence. */
4152 if ((val = tmp2_class - tmp_class))
4156 /* Prefer the insn which has more later insns that depend on it.
4157 This gives the scheduler more freedom when scheduling later
4158 instructions at the expense of added register pressure. */
4160 for (link = INSN_DEPEND (tmp); link; link = XEXP (link, 1))
4164 for (link = INSN_DEPEND (tmp2); link; link = XEXP (link, 1))
4167 val = depend_count2 - depend_count1;
4171 /* If insns are equally good, sort by INSN_LUID (original insn order),
4172 so that we make the sort stable. This minimizes instruction movement,
4173 thus minimizing sched's effect on debugging and cross-jumping. */
4174 return INSN_LUID (tmp) - INSN_LUID (tmp2);
4177 /* Resort the array A in which only element at index N may be out of order. */
4179 HAIFA_INLINE static void
4184 rtx insn = a[n - 1];
4187 while (i >= 0 && rank_for_schedule (a + i, &insn) >= 0)
4195 static int max_priority;
4197 /* Add INSN to the insn queue so that it can be executed at least
4198 N_CYCLES after the currently executing insn. Preserve insns
4199 chain for debugging purposes. */
4201 HAIFA_INLINE static void
4202 queue_insn (insn, n_cycles)
4206 int next_q = NEXT_Q_AFTER (q_ptr, n_cycles);
4207 rtx link = alloc_INSN_LIST (insn, insn_queue[next_q]);
4208 insn_queue[next_q] = link;
4211 if (sched_verbose >= 2)
4213 fprintf (dump, ";;\t\tReady-->Q: insn %d: ", INSN_UID (insn));
4215 if (INSN_BB (insn) != target_bb)
4216 fprintf (dump, "(b%d) ", INSN_BLOCK (insn));
4218 fprintf (dump, "queued for %d cycles.\n", n_cycles);
4223 /* Return nonzero if PAT is the pattern of an insn which makes a
4226 HAIFA_INLINE static int
4227 birthing_insn_p (pat)
4232 if (reload_completed == 1)
4235 if (GET_CODE (pat) == SET
4236 && (GET_CODE (SET_DEST (pat)) == REG
4237 || (GET_CODE (SET_DEST (pat)) == PARALLEL
4238 && GET_MODE (SET_DEST (pat)) == BLKmode)))
4240 rtx dest = SET_DEST (pat);
4243 /* It would be more accurate to use refers_to_regno_p or
4244 reg_mentioned_p to determine when the dest is not live before this
4246 if (GET_CODE (dest) == REG)
4249 if (REGNO_REG_SET_P (bb_live_regs, i))
4250 return (REG_N_SETS (i) == 1);
4254 for (i = XVECLEN (dest, 0) - 1; i >= 0; i--)
4256 int regno = REGNO (SET_DEST (XVECEXP (dest, 0, i)));
4257 if (REGNO_REG_SET_P (bb_live_regs, regno))
4258 return (REG_N_SETS (regno) == 1);
4263 if (GET_CODE (pat) == PARALLEL)
4265 for (j = 0; j < XVECLEN (pat, 0); j++)
4266 if (birthing_insn_p (XVECEXP (pat, 0, j)))
4272 /* PREV is an insn that is ready to execute. Adjust its priority if that
4273 will help shorten register lifetimes. */
4275 HAIFA_INLINE static void
4276 adjust_priority (prev)
4279 /* Trying to shorten register lives after reload has completed
4280 is useless and wrong. It gives inaccurate schedules. */
4281 if (reload_completed == 0)
4286 /* ??? This code has no effect, because REG_DEAD notes are removed
4287 before we ever get here. */
4288 for (note = REG_NOTES (prev); note; note = XEXP (note, 1))
4289 if (REG_NOTE_KIND (note) == REG_DEAD)
4292 /* Defer scheduling insns which kill registers, since that
4293 shortens register lives. Prefer scheduling insns which
4294 make registers live for the same reason. */
4298 INSN_PRIORITY (prev) >>= 3;
4301 INSN_PRIORITY (prev) >>= 2;
4305 INSN_PRIORITY (prev) >>= 1;
4308 if (birthing_insn_p (PATTERN (prev)))
4310 int max = max_priority;
4312 if (max > INSN_PRIORITY (prev))
4313 INSN_PRIORITY (prev) = max;
4317 #ifdef ADJUST_PRIORITY
4318 ADJUST_PRIORITY (prev);
4323 /* Clock at which the previous instruction was issued. */
4324 static int last_clock_var;
4326 /* INSN is the "currently executing insn". Launch each insn which was
4327 waiting on INSN. READY is a vector of insns which are ready to fire.
4328 N_READY is the number of elements in READY. CLOCK is the current
4332 schedule_insn (insn, ready, n_ready, clock)
4341 unit = insn_unit (insn);
4343 if (sched_verbose >= 2)
4345 fprintf (dump, ";;\t\t--> scheduling insn <<<%d>>> on unit ", INSN_UID (insn));
4346 insn_print_units (insn);
4347 fprintf (dump, "\n");
4350 if (sched_verbose && unit == -1)
4351 visualize_no_unit (insn);
4353 if (MAX_BLOCKAGE > 1 || issue_rate > 1 || sched_verbose)
4354 schedule_unit (unit, insn, clock);
4356 if (INSN_DEPEND (insn) == 0)
4359 /* This is used by the function adjust_priority above. */
4361 max_priority = MAX (INSN_PRIORITY (ready[0]), INSN_PRIORITY (insn));
4363 max_priority = INSN_PRIORITY (insn);
4365 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
4367 rtx next = XEXP (link, 0);
4368 int cost = insn_cost (insn, link, next);
4370 INSN_TICK (next) = MAX (INSN_TICK (next), clock + cost);
4372 if ((INSN_DEP_COUNT (next) -= 1) == 0)
4374 int effective_cost = INSN_TICK (next) - clock;
4376 /* For speculative insns, before inserting to ready/queue,
4377 check live, exception-free, and issue-delay */
4378 if (INSN_BB (next) != target_bb
4379 && (!IS_VALID (INSN_BB (next))
4381 || (IS_SPECULATIVE_INSN (next)
4382 && (insn_issue_delay (next) > 3
4383 || !check_live (next, INSN_BB (next))
4384 || !is_exception_free (next, INSN_BB (next), target_bb)))))
4387 if (sched_verbose >= 2)
4389 fprintf (dump, ";;\t\tdependences resolved: insn %d ", INSN_UID (next));
4391 if (current_nr_blocks > 1 && INSN_BB (next) != target_bb)
4392 fprintf (dump, "/b%d ", INSN_BLOCK (next));
4394 if (effective_cost <= 1)
4395 fprintf (dump, "into ready\n");
4397 fprintf (dump, "into queue with cost=%d\n", effective_cost);
4400 /* Adjust the priority of NEXT and either put it on the ready
4401 list or queue it. */
4402 adjust_priority (next);
4403 if (effective_cost <= 1)
4404 ready[n_ready++] = next;
4406 queue_insn (next, effective_cost);
4410 /* Annotate the instruction with issue information -- TImode
4411 indicates that the instruction is expected not to be able
4412 to issue on the same cycle as the previous insn. A machine
4413 may use this information to decide how the instruction should
4415 if (reload_completed && issue_rate > 1)
4417 PUT_MODE (insn, clock > last_clock_var ? TImode : VOIDmode);
4418 last_clock_var = clock;
4425 /* Add a REG_DEAD note for REG to INSN, reusing a REG_DEAD note from the
4429 create_reg_dead_note (reg, insn)
4434 /* The number of registers killed after scheduling must be the same as the
4435 number of registers killed before scheduling. The number of REG_DEAD
4436 notes may not be conserved, i.e. two SImode hard register REG_DEAD notes
4437 might become one DImode hard register REG_DEAD note, but the number of
4438 registers killed will be conserved.
4440 We carefully remove REG_DEAD notes from the dead_notes list, so that
4441 there will be none left at the end. If we run out early, then there
4442 is a bug somewhere in flow, combine and/or sched. */
4444 if (dead_notes == 0)
4446 if (current_nr_blocks <= 1)
4449 link = alloc_EXPR_LIST (REG_DEAD, NULL_RTX, NULL_RTX);
4453 /* Number of regs killed by REG. */
4454 int regs_killed = (REGNO (reg) >= FIRST_PSEUDO_REGISTER ? 1
4455 : HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)));
4456 /* Number of regs killed by REG_DEAD notes taken off the list. */
4460 reg_note_regs = (REGNO (XEXP (link, 0)) >= FIRST_PSEUDO_REGISTER ? 1
4461 : HARD_REGNO_NREGS (REGNO (XEXP (link, 0)),
4462 GET_MODE (XEXP (link, 0))));
4463 while (reg_note_regs < regs_killed)
4465 link = XEXP (link, 1);
4467 /* LINK might be zero if we killed more registers after scheduling
4468 than before, and the last hard register we kill is actually
4471 This is normal for interblock scheduling, so deal with it in
4472 that case, else abort. */
4473 if (link == NULL_RTX && current_nr_blocks <= 1)
4475 else if (link == NULL_RTX)
4476 link = alloc_EXPR_LIST (REG_DEAD, gen_rtx_REG (word_mode, 0),
4479 reg_note_regs += (REGNO (XEXP (link, 0)) >= FIRST_PSEUDO_REGISTER ? 1
4480 : HARD_REGNO_NREGS (REGNO (XEXP (link, 0)),
4481 GET_MODE (XEXP (link, 0))));
4483 dead_notes = XEXP (link, 1);
4485 /* If we took too many regs kills off, put the extra ones back. */
4486 while (reg_note_regs > regs_killed)
4488 rtx temp_reg, temp_link;
4490 temp_reg = gen_rtx_REG (word_mode, 0);
4491 temp_link = alloc_EXPR_LIST (REG_DEAD, temp_reg, dead_notes);
4492 dead_notes = temp_link;
4497 XEXP (link, 0) = reg;
4498 XEXP (link, 1) = REG_NOTES (insn);
4499 REG_NOTES (insn) = link;
4502 /* Subroutine on attach_deaths_insn--handles the recursive search
4503 through INSN. If SET_P is true, then x is being modified by the insn. */
4506 attach_deaths (x, insn, set_p)
4513 register enum rtx_code code;
4519 code = GET_CODE (x);
4531 /* Get rid of the easy cases first. */
4536 /* If the register dies in this insn, queue that note, and mark
4537 this register as needing to die. */
4538 /* This code is very similar to mark_used_1 (if set_p is false)
4539 and mark_set_1 (if set_p is true) in flow.c. */
4549 all_needed = some_needed = REGNO_REG_SET_P (old_live_regs, regno);
4550 if (regno < FIRST_PSEUDO_REGISTER)
4554 n = HARD_REGNO_NREGS (regno, GET_MODE (x));
4557 int needed = (REGNO_REG_SET_P (old_live_regs, regno + n));
4558 some_needed |= needed;
4559 all_needed &= needed;
4563 /* If it wasn't live before we started, then add a REG_DEAD note.
4564 We must check the previous lifetime info not the current info,
4565 because we may have to execute this code several times, e.g.
4566 once for a clobber (which doesn't add a note) and later
4567 for a use (which does add a note).
4569 Always make the register live. We must do this even if it was
4570 live before, because this may be an insn which sets and uses
4571 the same register, in which case the register has already been
4572 killed, so we must make it live again.
4574 Global registers are always live, and should never have a REG_DEAD
4575 note added for them, so none of the code below applies to them. */
4577 if (regno >= FIRST_PSEUDO_REGISTER || ! global_regs[regno])
4579 /* Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
4580 STACK_POINTER_REGNUM, since these are always considered to be
4581 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
4582 if (regno != FRAME_POINTER_REGNUM
4583 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
4584 && ! (regno == HARD_FRAME_POINTER_REGNUM)
4586 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
4587 && ! (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
4589 && regno != STACK_POINTER_REGNUM)
4591 if (! all_needed && ! dead_or_set_p (insn, x))
4593 /* Check for the case where the register dying partially
4594 overlaps the register set by this insn. */
4595 if (regno < FIRST_PSEUDO_REGISTER
4596 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
4598 int n = HARD_REGNO_NREGS (regno, GET_MODE (x));
4600 some_needed |= dead_or_set_regno_p (insn, regno + n);
4603 /* If none of the words in X is needed, make a REG_DEAD
4604 note. Otherwise, we must make partial REG_DEAD
4607 create_reg_dead_note (x, insn);
4612 /* Don't make a REG_DEAD note for a part of a
4613 register that is set in the insn. */
4614 for (i = HARD_REGNO_NREGS (regno, GET_MODE (x)) - 1;
4616 if (! REGNO_REG_SET_P (old_live_regs, regno+i)
4617 && ! dead_or_set_regno_p (insn, regno + i))
4618 create_reg_dead_note (gen_rtx_REG (reg_raw_mode[regno + i],
4625 if (regno < FIRST_PSEUDO_REGISTER)
4627 int j = HARD_REGNO_NREGS (regno, GET_MODE (x));
4630 SET_REGNO_REG_SET (bb_live_regs, regno + j);
4635 /* Recompute REG_BASIC_BLOCK as we update all the other
4636 dataflow information. */
4637 if (sched_reg_basic_block[regno] == REG_BLOCK_UNKNOWN)
4638 sched_reg_basic_block[regno] = current_block_num;
4639 else if (sched_reg_basic_block[regno] != current_block_num)
4640 sched_reg_basic_block[regno] = REG_BLOCK_GLOBAL;
4642 SET_REGNO_REG_SET (bb_live_regs, regno);
4649 /* Handle tail-recursive case. */
4650 attach_deaths (XEXP (x, 0), insn, 0);
4654 attach_deaths (SUBREG_REG (x), insn,
4655 set_p && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
4657 || (GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
4658 == GET_MODE_SIZE (GET_MODE ((x))))));
4661 case STRICT_LOW_PART:
4662 attach_deaths (XEXP (x, 0), insn, 0);
4667 attach_deaths (XEXP (x, 0), insn, 0);
4668 attach_deaths (XEXP (x, 1), insn, 0);
4669 attach_deaths (XEXP (x, 2), insn, 0);
4674 && GET_MODE (x) == BLKmode)
4676 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
4677 attach_deaths (SET_DEST (XVECEXP (x, 0, i)), insn, 1);
4683 /* Other cases: walk the insn. */
4684 fmt = GET_RTX_FORMAT (code);
4685 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4688 attach_deaths (XEXP (x, i), insn, 0);
4689 else if (fmt[i] == 'E')
4690 for (j = 0; j < XVECLEN (x, i); j++)
4691 attach_deaths (XVECEXP (x, i, j), insn, 0);
4696 /* After INSN has executed, add register death notes for each register
4697 that is dead after INSN. */
4700 attach_deaths_insn (insn)
4703 rtx x = PATTERN (insn);
4704 register RTX_CODE code = GET_CODE (x);
4709 attach_deaths (SET_SRC (x), insn, 0);
4711 /* A register might die here even if it is the destination, e.g.
4712 it is the target of a volatile read and is otherwise unused.
4713 Hence we must always call attach_deaths for the SET_DEST. */
4714 attach_deaths (SET_DEST (x), insn, 1);
4716 else if (code == PARALLEL)
4719 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
4721 code = GET_CODE (XVECEXP (x, 0, i));
4724 attach_deaths (SET_SRC (XVECEXP (x, 0, i)), insn, 0);
4726 attach_deaths (SET_DEST (XVECEXP (x, 0, i)), insn, 1);
4728 /* Flow does not add REG_DEAD notes to registers that die in
4729 clobbers, so we can't either. */
4730 else if (code != CLOBBER)
4731 attach_deaths (XVECEXP (x, 0, i), insn, 0);
4734 /* If this is a CLOBBER, only add REG_DEAD notes to registers inside a
4735 MEM being clobbered, just like flow. */
4736 else if (code == CLOBBER && GET_CODE (XEXP (x, 0)) == MEM)
4737 attach_deaths (XEXP (XEXP (x, 0), 0), insn, 0);
4738 /* Otherwise don't add a death note to things being clobbered. */
4739 else if (code != CLOBBER)
4740 attach_deaths (x, insn, 0);
4742 /* Make death notes for things used in the called function. */
4743 if (GET_CODE (insn) == CALL_INSN)
4744 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
4745 attach_deaths (XEXP (XEXP (link, 0), 0), insn,
4746 GET_CODE (XEXP (link, 0)) == CLOBBER);
4749 /* functions for handlnig of notes */
4751 /* Delete notes beginning with INSN and put them in the chain
4752 of notes ended by NOTE_LIST.
4753 Returns the insn following the notes. */
4756 unlink_other_notes (insn, tail)
4759 rtx prev = PREV_INSN (insn);
4761 while (insn != tail && GET_CODE (insn) == NOTE)
4763 rtx next = NEXT_INSN (insn);
4764 /* Delete the note from its current position. */
4766 NEXT_INSN (prev) = next;
4768 PREV_INSN (next) = prev;
4770 /* Don't save away NOTE_INSN_SETJMPs, because they must remain
4771 immediately after the call they follow. We use a fake
4772 (REG_DEAD (const_int -1)) note to remember them.
4773 Likewise with NOTE_INSN_{LOOP,EHREGION}_{BEG, END}. */
4774 if (NOTE_LINE_NUMBER (insn) != NOTE_INSN_SETJMP
4775 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_LOOP_BEG
4776 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_LOOP_END
4777 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_RANGE_START
4778 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_RANGE_END
4779 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_EH_REGION_BEG
4780 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_EH_REGION_END)
4782 /* Insert the note at the end of the notes list. */
4783 PREV_INSN (insn) = note_list;
4785 NEXT_INSN (note_list) = insn;
4794 /* Delete line notes beginning with INSN. Record line-number notes so
4795 they can be reused. Returns the insn following the notes. */
4798 unlink_line_notes (insn, tail)
4801 rtx prev = PREV_INSN (insn);
4803 while (insn != tail && GET_CODE (insn) == NOTE)
4805 rtx next = NEXT_INSN (insn);
4807 if (write_symbols != NO_DEBUG && NOTE_LINE_NUMBER (insn) > 0)
4809 /* Delete the note from its current position. */
4811 NEXT_INSN (prev) = next;
4813 PREV_INSN (next) = prev;
4815 /* Record line-number notes so they can be reused. */
4816 LINE_NOTE (insn) = insn;
4826 /* Return the head and tail pointers of BB. */
4828 HAIFA_INLINE static void
4829 get_block_head_tail (bb, headp, tailp)
4839 b = BB_TO_BLOCK (bb);
4841 /* HEAD and TAIL delimit the basic block being scheduled. */
4842 head = basic_block_head[b];
4843 tail = basic_block_end[b];
4845 /* Don't include any notes or labels at the beginning of the
4846 basic block, or notes at the ends of basic blocks. */
4847 while (head != tail)
4849 if (GET_CODE (head) == NOTE)
4850 head = NEXT_INSN (head);
4851 else if (GET_CODE (tail) == NOTE)
4852 tail = PREV_INSN (tail);
4853 else if (GET_CODE (head) == CODE_LABEL)
4854 head = NEXT_INSN (head);
4863 /* Delete line notes from bb. Save them so they can be later restored
4864 (in restore_line_notes ()). */
4875 get_block_head_tail (bb, &head, &tail);
4878 && (GET_RTX_CLASS (GET_CODE (head)) != 'i'))
4881 next_tail = NEXT_INSN (tail);
4882 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
4886 /* Farm out notes, and maybe save them in NOTE_LIST.
4887 This is needed to keep the debugger from
4888 getting completely deranged. */
4889 if (GET_CODE (insn) == NOTE)
4892 insn = unlink_line_notes (insn, next_tail);
4898 if (insn == next_tail)
4904 /* Save line number notes for each insn in bb. */
4907 save_line_notes (bb)
4913 /* We must use the true line number for the first insn in the block
4914 that was computed and saved at the start of this pass. We can't
4915 use the current line number, because scheduling of the previous
4916 block may have changed the current line number. */
4918 rtx line = line_note_head[BB_TO_BLOCK (bb)];
4921 get_block_head_tail (bb, &head, &tail);
4922 next_tail = NEXT_INSN (tail);
4924 for (insn = basic_block_head[BB_TO_BLOCK (bb)];
4926 insn = NEXT_INSN (insn))
4927 if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0)
4930 LINE_NOTE (insn) = line;
4934 /* After bb was scheduled, insert line notes into the insns list. */
4937 restore_line_notes (bb)
4940 rtx line, note, prev, new;
4941 int added_notes = 0;
4943 rtx head, next_tail, insn;
4945 b = BB_TO_BLOCK (bb);
4947 head = basic_block_head[b];
4948 next_tail = NEXT_INSN (basic_block_end[b]);
4950 /* Determine the current line-number. We want to know the current
4951 line number of the first insn of the block here, in case it is
4952 different from the true line number that was saved earlier. If
4953 different, then we need a line number note before the first insn
4954 of this block. If it happens to be the same, then we don't want to
4955 emit another line number note here. */
4956 for (line = head; line; line = PREV_INSN (line))
4957 if (GET_CODE (line) == NOTE && NOTE_LINE_NUMBER (line) > 0)
4960 /* Walk the insns keeping track of the current line-number and inserting
4961 the line-number notes as needed. */
4962 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
4963 if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0)
4965 /* This used to emit line number notes before every non-deleted note.
4966 However, this confuses a debugger, because line notes not separated
4967 by real instructions all end up at the same address. I can find no
4968 use for line number notes before other notes, so none are emitted. */
4969 else if (GET_CODE (insn) != NOTE
4970 && (note = LINE_NOTE (insn)) != 0
4973 || NOTE_LINE_NUMBER (note) != NOTE_LINE_NUMBER (line)
4974 || NOTE_SOURCE_FILE (note) != NOTE_SOURCE_FILE (line)))
4977 prev = PREV_INSN (insn);
4978 if (LINE_NOTE (note))
4980 /* Re-use the original line-number note. */
4981 LINE_NOTE (note) = 0;
4982 PREV_INSN (note) = prev;
4983 NEXT_INSN (prev) = note;
4984 PREV_INSN (insn) = note;
4985 NEXT_INSN (note) = insn;
4990 new = emit_note_after (NOTE_LINE_NUMBER (note), prev);
4991 NOTE_SOURCE_FILE (new) = NOTE_SOURCE_FILE (note);
4992 RTX_INTEGRATED_P (new) = RTX_INTEGRATED_P (note);
4995 if (sched_verbose && added_notes)
4996 fprintf (dump, ";; added %d line-number notes\n", added_notes);
4999 /* After scheduling the function, delete redundant line notes from the
5003 rm_redundant_line_notes ()
5006 rtx insn = get_insns ();
5007 int active_insn = 0;
5010 /* Walk the insns deleting redundant line-number notes. Many of these
5011 are already present. The remainder tend to occur at basic
5012 block boundaries. */
5013 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
5014 if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0)
5016 /* If there are no active insns following, INSN is redundant. */
5017 if (active_insn == 0)
5020 NOTE_SOURCE_FILE (insn) = 0;
5021 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
5023 /* If the line number is unchanged, LINE is redundant. */
5025 && NOTE_LINE_NUMBER (line) == NOTE_LINE_NUMBER (insn)
5026 && NOTE_SOURCE_FILE (line) == NOTE_SOURCE_FILE (insn))
5029 NOTE_SOURCE_FILE (line) = 0;
5030 NOTE_LINE_NUMBER (line) = NOTE_INSN_DELETED;
5037 else if (!((GET_CODE (insn) == NOTE
5038 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED)
5039 || (GET_CODE (insn) == INSN
5040 && (GET_CODE (PATTERN (insn)) == USE
5041 || GET_CODE (PATTERN (insn)) == CLOBBER))))
5044 if (sched_verbose && notes)
5045 fprintf (dump, ";; deleted %d line-number notes\n", notes);
5048 /* Delete notes between head and tail and put them in the chain
5049 of notes ended by NOTE_LIST. */
5052 rm_other_notes (head, tail)
5060 && (GET_RTX_CLASS (GET_CODE (head)) != 'i'))
5063 next_tail = NEXT_INSN (tail);
5064 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
5068 /* Farm out notes, and maybe save them in NOTE_LIST.
5069 This is needed to keep the debugger from
5070 getting completely deranged. */
5071 if (GET_CODE (insn) == NOTE)
5075 insn = unlink_other_notes (insn, next_tail);
5081 if (insn == next_tail)
5087 /* Constructor for `sometimes' data structure. */
5090 new_sometimes_live (regs_sometimes_live, regno, sometimes_max)
5091 struct sometimes *regs_sometimes_live;
5095 register struct sometimes *p;
5097 /* There should never be a register greater than max_regno here. If there
5098 is, it means that a define_split has created a new pseudo reg. This
5099 is not allowed, since there will not be flow info available for any
5100 new register, so catch the error here. */
5101 if (regno >= max_regno)
5104 p = ®s_sometimes_live[sometimes_max];
5107 p->calls_crossed = 0;
5109 return sometimes_max;
5112 /* Count lengths of all regs we are currently tracking,
5113 and find new registers no longer live. */
5116 finish_sometimes_live (regs_sometimes_live, sometimes_max)
5117 struct sometimes *regs_sometimes_live;
5122 for (i = 0; i < sometimes_max; i++)
5124 register struct sometimes *p = ®s_sometimes_live[i];
5125 int regno = p->regno;
5127 sched_reg_live_length[regno] += p->live_length;
5128 sched_reg_n_calls_crossed[regno] += p->calls_crossed;
5132 /* functions for computation of registers live/usage info */
5134 /* It is assumed that prior to scheduling basic_block_live_at_start (b)
5135 contains the registers that are alive at the entry to b.
5137 Two passes follow: The first pass is performed before the scheduling
5138 of a region. It scans each block of the region forward, computing
5139 the set of registers alive at the end of the basic block and
5140 discard REG_DEAD notes (done by find_pre_sched_live ()).
5142 The second path is invoked after scheduling all region blocks.
5143 It scans each block of the region backward, a block being traversed
5144 only after its succesors in the region. When the set of registers
5145 live at the end of a basic block may be changed by the scheduling
5146 (this may happen for multiple blocks region), it is computed as
5147 the union of the registers live at the start of its succesors.
5148 The last-use information is updated by inserting REG_DEAD notes.
5149 (done by find_post_sched_live ()) */
5151 /* Scan all the insns to be scheduled, removing register death notes.
5152 Register death notes end up in DEAD_NOTES.
5153 Recreate the register life information for the end of this basic
5157 find_pre_sched_live (bb)
5160 rtx insn, next_tail, head, tail;
5161 int b = BB_TO_BLOCK (bb);
5163 get_block_head_tail (bb, &head, &tail);
5164 COPY_REG_SET (bb_live_regs, basic_block_live_at_start[b]);
5165 next_tail = NEXT_INSN (tail);
5167 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
5169 rtx prev, next, link;
5172 /* Handle register life information. */
5173 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
5175 /* See if the register gets born here. */
5176 /* We must check for registers being born before we check for
5177 registers dying. It is possible for a register to be born and
5178 die in the same insn, e.g. reading from a volatile memory
5179 location into an otherwise unused register. Such a register
5180 must be marked as dead after this insn. */
5181 if (GET_CODE (PATTERN (insn)) == SET
5182 || GET_CODE (PATTERN (insn)) == CLOBBER)
5184 sched_note_set (PATTERN (insn), 0);
5188 else if (GET_CODE (PATTERN (insn)) == PARALLEL)
5191 for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--)
5192 if (GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == SET
5193 || GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == CLOBBER)
5195 sched_note_set (XVECEXP (PATTERN (insn), 0, j), 0);
5199 /* ??? This code is obsolete and should be deleted. It
5200 is harmless though, so we will leave it in for now. */
5201 for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--)
5202 if (GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == USE)
5203 sched_note_set (XVECEXP (PATTERN (insn), 0, j), 0);
5206 /* Each call cobbers (makes live) all call-clobbered regs
5207 that are not global or fixed. Note that the function-value
5208 reg is a call_clobbered reg. */
5209 if (GET_CODE (insn) == CALL_INSN)
5212 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
5213 if (call_used_regs[j] && !global_regs[j]
5216 SET_REGNO_REG_SET (bb_live_regs, j);
5220 /* Need to know what registers this insn kills. */
5221 for (prev = 0, link = REG_NOTES (insn); link; link = next)
5223 next = XEXP (link, 1);
5224 if ((REG_NOTE_KIND (link) == REG_DEAD
5225 || REG_NOTE_KIND (link) == REG_UNUSED)
5226 /* Verify that the REG_NOTE has a valid value. */
5227 && GET_CODE (XEXP (link, 0)) == REG)
5229 register int regno = REGNO (XEXP (link, 0));
5233 /* Only unlink REG_DEAD notes; leave REG_UNUSED notes
5235 if (REG_NOTE_KIND (link) == REG_DEAD)
5238 XEXP (prev, 1) = next;
5240 REG_NOTES (insn) = next;
5241 XEXP (link, 1) = dead_notes;
5247 if (regno < FIRST_PSEUDO_REGISTER)
5249 int j = HARD_REGNO_NREGS (regno,
5250 GET_MODE (XEXP (link, 0)));
5253 CLEAR_REGNO_REG_SET (bb_live_regs, regno+j);
5258 CLEAR_REGNO_REG_SET (bb_live_regs, regno);
5266 INSN_REG_WEIGHT (insn) = reg_weight;
5270 /* Update register life and usage information for block bb
5271 after scheduling. Put register dead notes back in the code. */
5274 find_post_sched_live (bb)
5281 rtx head, tail, prev_head, next_tail;
5283 register struct sometimes *regs_sometimes_live;
5285 b = BB_TO_BLOCK (bb);
5287 /* compute live regs at the end of bb as a function of its successors. */
5288 if (current_nr_blocks > 1)
5293 first_edge = e = OUT_EDGES (b);
5294 CLEAR_REG_SET (bb_live_regs);
5301 b_succ = TO_BLOCK (e);
5302 IOR_REG_SET (bb_live_regs, basic_block_live_at_start[b_succ]);
5305 while (e != first_edge);
5308 get_block_head_tail (bb, &head, &tail);
5309 next_tail = NEXT_INSN (tail);
5310 prev_head = PREV_INSN (head);
5312 EXECUTE_IF_SET_IN_REG_SET (bb_live_regs, FIRST_PSEUDO_REGISTER, i,
5314 sched_reg_basic_block[i] = REG_BLOCK_GLOBAL;
5317 /* if the block is empty, same regs are alive at its end and its start.
5318 since this is not guaranteed after interblock scheduling, make sure they
5319 are truly identical. */
5320 if (NEXT_INSN (prev_head) == tail
5321 && (GET_RTX_CLASS (GET_CODE (tail)) != 'i'))
5323 if (current_nr_blocks > 1)
5324 COPY_REG_SET (basic_block_live_at_start[b], bb_live_regs);
5329 b = BB_TO_BLOCK (bb);
5330 current_block_num = b;
5332 /* Keep track of register lives. */
5333 old_live_regs = ALLOCA_REG_SET ();
5335 = (struct sometimes *) alloca (max_regno * sizeof (struct sometimes));
5338 /* initiate "sometimes" data, starting with registers live at end */
5340 COPY_REG_SET (old_live_regs, bb_live_regs);
5341 EXECUTE_IF_SET_IN_REG_SET (bb_live_regs, 0, j,
5344 = new_sometimes_live (regs_sometimes_live,
5348 /* scan insns back, computing regs live info */
5349 for (insn = tail; insn != prev_head; insn = PREV_INSN (insn))
5351 /* First we kill registers set by this insn, and then we
5352 make registers used by this insn live. This is the opposite
5353 order used above because we are traversing the instructions
5356 /* Strictly speaking, we should scan REG_UNUSED notes and make
5357 every register mentioned there live, however, we will just
5358 kill them again immediately below, so there doesn't seem to
5359 be any reason why we bother to do this. */
5361 /* See if this is the last notice we must take of a register. */
5362 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
5365 if (GET_CODE (PATTERN (insn)) == SET
5366 || GET_CODE (PATTERN (insn)) == CLOBBER)
5367 sched_note_set (PATTERN (insn), 1);
5368 else if (GET_CODE (PATTERN (insn)) == PARALLEL)
5370 for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--)
5371 if (GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == SET
5372 || GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == CLOBBER)
5373 sched_note_set (XVECEXP (PATTERN (insn), 0, j), 1);
5376 /* This code keeps life analysis information up to date. */
5377 if (GET_CODE (insn) == CALL_INSN)
5379 register struct sometimes *p;
5381 /* A call kills all call used registers that are not
5382 global or fixed, except for those mentioned in the call
5383 pattern which will be made live again later. */
5384 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5385 if (call_used_regs[i] && ! global_regs[i]
5388 CLEAR_REGNO_REG_SET (bb_live_regs, i);
5391 /* Regs live at the time of a call instruction must not
5392 go in a register clobbered by calls. Record this for
5393 all regs now live. Note that insns which are born or
5394 die in a call do not cross a call, so this must be done
5395 after the killings (above) and before the births
5397 p = regs_sometimes_live;
5398 for (i = 0; i < sometimes_max; i++, p++)
5399 if (REGNO_REG_SET_P (bb_live_regs, p->regno))
5400 p->calls_crossed += 1;
5403 /* Make every register used live, and add REG_DEAD notes for
5404 registers which were not live before we started. */
5405 attach_deaths_insn (insn);
5407 /* Find registers now made live by that instruction. */
5408 EXECUTE_IF_AND_COMPL_IN_REG_SET (bb_live_regs, old_live_regs, 0, j,
5411 = new_sometimes_live (regs_sometimes_live,
5414 IOR_REG_SET (old_live_regs, bb_live_regs);
5416 /* Count lengths of all regs we are worrying about now,
5417 and handle registers no longer live. */
5419 for (i = 0; i < sometimes_max; i++)
5421 register struct sometimes *p = ®s_sometimes_live[i];
5422 int regno = p->regno;
5424 p->live_length += 1;
5426 if (!REGNO_REG_SET_P (bb_live_regs, regno))
5428 /* This is the end of one of this register's lifetime
5429 segments. Save the lifetime info collected so far,
5430 and clear its bit in the old_live_regs entry. */
5431 sched_reg_live_length[regno] += p->live_length;
5432 sched_reg_n_calls_crossed[regno] += p->calls_crossed;
5433 CLEAR_REGNO_REG_SET (old_live_regs, p->regno);
5435 /* Delete the reg_sometimes_live entry for this reg by
5436 copying the last entry over top of it. */
5437 *p = regs_sometimes_live[--sometimes_max];
5438 /* ...and decrement i so that this newly copied entry
5439 will be processed. */
5445 finish_sometimes_live (regs_sometimes_live, sometimes_max);
5447 /* In interblock scheduling, basic_block_live_at_start may have changed. */
5448 if (current_nr_blocks > 1)
5449 COPY_REG_SET (basic_block_live_at_start[b], bb_live_regs);
5452 FREE_REG_SET (old_live_regs);
5453 } /* find_post_sched_live */
5455 /* After scheduling the subroutine, restore information about uses of
5463 if (n_basic_blocks > 0)
5464 EXECUTE_IF_SET_IN_REG_SET (bb_live_regs, FIRST_PSEUDO_REGISTER, regno,
5466 sched_reg_basic_block[regno]
5470 for (regno = 0; regno < max_regno; regno++)
5471 if (sched_reg_live_length[regno])
5475 if (REG_LIVE_LENGTH (regno) > sched_reg_live_length[regno])
5477 ";; register %d life shortened from %d to %d\n",
5478 regno, REG_LIVE_LENGTH (regno),
5479 sched_reg_live_length[regno]);
5480 /* Negative values are special; don't overwrite the current
5481 reg_live_length value if it is negative. */
5482 else if (REG_LIVE_LENGTH (regno) < sched_reg_live_length[regno]
5483 && REG_LIVE_LENGTH (regno) >= 0)
5485 ";; register %d life extended from %d to %d\n",
5486 regno, REG_LIVE_LENGTH (regno),
5487 sched_reg_live_length[regno]);
5489 if (!REG_N_CALLS_CROSSED (regno)
5490 && sched_reg_n_calls_crossed[regno])
5492 ";; register %d now crosses calls\n", regno);
5493 else if (REG_N_CALLS_CROSSED (regno)
5494 && !sched_reg_n_calls_crossed[regno]
5495 && REG_BASIC_BLOCK (regno) != REG_BLOCK_GLOBAL)
5497 ";; register %d no longer crosses calls\n", regno);
5499 if (REG_BASIC_BLOCK (regno) != sched_reg_basic_block[regno]
5500 && sched_reg_basic_block[regno] != REG_BLOCK_UNKNOWN
5501 && REG_BASIC_BLOCK(regno) != REG_BLOCK_UNKNOWN)
5503 ";; register %d changed basic block from %d to %d\n",
5504 regno, REG_BASIC_BLOCK(regno),
5505 sched_reg_basic_block[regno]);
5508 /* Negative values are special; don't overwrite the current
5509 reg_live_length value if it is negative. */
5510 if (REG_LIVE_LENGTH (regno) >= 0)
5511 REG_LIVE_LENGTH (regno) = sched_reg_live_length[regno];
5513 if (sched_reg_basic_block[regno] != REG_BLOCK_UNKNOWN
5514 && REG_BASIC_BLOCK(regno) != REG_BLOCK_UNKNOWN)
5515 REG_BASIC_BLOCK(regno) = sched_reg_basic_block[regno];
5517 /* We can't change the value of reg_n_calls_crossed to zero for
5518 pseudos which are live in more than one block.
5520 This is because combine might have made an optimization which
5521 invalidated basic_block_live_at_start and reg_n_calls_crossed,
5522 but it does not update them. If we update reg_n_calls_crossed
5523 here, the two variables are now inconsistent, and this might
5524 confuse the caller-save code into saving a register that doesn't
5525 need to be saved. This is only a problem when we zero calls
5526 crossed for a pseudo live in multiple basic blocks.
5528 Alternatively, we could try to correctly update basic block live
5529 at start here in sched, but that seems complicated.
5531 Note: it is possible that a global register became local, as result
5532 of interblock motion, but will remain marked as a global register. */
5533 if (sched_reg_n_calls_crossed[regno]
5534 || REG_BASIC_BLOCK (regno) != REG_BLOCK_GLOBAL)
5535 REG_N_CALLS_CROSSED (regno) = sched_reg_n_calls_crossed[regno];
5540 /* Scheduling clock, modified in schedule_block() and queue_to_ready () */
5541 static int clock_var;
5543 /* Move insns that became ready to fire from queue to ready list. */
5546 queue_to_ready (ready, n_ready)
5553 q_ptr = NEXT_Q (q_ptr);
5555 /* Add all pending insns that can be scheduled without stalls to the
5557 for (link = insn_queue[q_ptr]; link; link = XEXP (link, 1))
5560 insn = XEXP (link, 0);
5563 if (sched_verbose >= 2)
5564 fprintf (dump, ";;\t\tQ-->Ready: insn %d: ", INSN_UID (insn));
5566 if (sched_verbose >= 2 && INSN_BB (insn) != target_bb)
5567 fprintf (dump, "(b%d) ", INSN_BLOCK (insn));
5569 ready[n_ready++] = insn;
5570 if (sched_verbose >= 2)
5571 fprintf (dump, "moving to ready without stalls\n");
5573 insn_queue[q_ptr] = 0;
5575 /* If there are no ready insns, stall until one is ready and add all
5576 of the pending insns at that point to the ready list. */
5579 register int stalls;
5581 for (stalls = 1; stalls < INSN_QUEUE_SIZE; stalls++)
5583 if ((link = insn_queue[NEXT_Q_AFTER (q_ptr, stalls)]))
5585 for (; link; link = XEXP (link, 1))
5587 insn = XEXP (link, 0);
5590 if (sched_verbose >= 2)
5591 fprintf (dump, ";;\t\tQ-->Ready: insn %d: ", INSN_UID (insn));
5593 if (sched_verbose >= 2 && INSN_BB (insn) != target_bb)
5594 fprintf (dump, "(b%d) ", INSN_BLOCK (insn));
5596 ready[n_ready++] = insn;
5597 if (sched_verbose >= 2)
5598 fprintf (dump, "moving to ready with %d stalls\n", stalls);
5600 insn_queue[NEXT_Q_AFTER (q_ptr, stalls)] = 0;
5607 if (sched_verbose && stalls)
5608 visualize_stall_cycles (BB_TO_BLOCK (target_bb), stalls);
5609 q_ptr = NEXT_Q_AFTER (q_ptr, stalls);
5610 clock_var += stalls;
5615 /* Print the ready list for debugging purposes. Callable from debugger. */
5618 debug_ready_list (ready, n_ready)
5624 for (i = 0; i < n_ready; i++)
5626 fprintf (dump, " %d", INSN_UID (ready[i]));
5627 if (current_nr_blocks > 1 && INSN_BB (ready[i]) != target_bb)
5628 fprintf (dump, "/b%d", INSN_BLOCK (ready[i]));
5630 fprintf (dump, "\n");
5633 /* Print names of units on which insn can/should execute, for debugging. */
5636 insn_print_units (insn)
5640 int unit = insn_unit (insn);
5643 fprintf (dump, "none");
5645 fprintf (dump, "%s", function_units[unit].name);
5648 fprintf (dump, "[");
5649 for (i = 0, unit = ~unit; unit; i++, unit >>= 1)
5652 fprintf (dump, "%s", function_units[i].name);
5654 fprintf (dump, " ");
5656 fprintf (dump, "]");
5660 /* MAX_VISUAL_LINES is the maximum number of lines in visualization table
5661 of a basic block. If more lines are needed, table is splitted to two.
5662 n_visual_lines is the number of lines printed so far for a block.
5663 visual_tbl contains the block visualization info.
5664 vis_no_unit holds insns in a cycle that are not mapped to any unit. */
5665 #define MAX_VISUAL_LINES 100
5670 rtx vis_no_unit[10];
5672 /* Finds units that are in use in this fuction. Required only
5673 for visualization. */
5676 init_target_units ()
5681 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
5683 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
5686 unit = insn_unit (insn);
5689 target_units |= ~unit;
5691 target_units |= (1 << unit);
5695 /* Return the length of the visualization table */
5698 get_visual_tbl_length ()
5704 /* compute length of one field in line */
5705 s = (char *) alloca (INSN_LEN + 5);
5706 sprintf (s, " %33s", "uname");
5709 /* compute length of one line */
5712 for (unit = 0; unit < FUNCTION_UNITS_SIZE; unit++)
5713 if (function_units[unit].bitmask & target_units)
5714 for (i = 0; i < function_units[unit].multiplicity; i++)
5717 n += strlen ("\n") + 2;
5719 /* compute length of visualization string */
5720 return (MAX_VISUAL_LINES * n);
5723 /* Init block visualization debugging info */
5726 init_block_visualization ()
5728 strcpy (visual_tbl, "");
5736 safe_concat (buf, cur, str)
5741 char *end = buf + BUF_LEN - 2; /* leave room for null */
5750 while (cur < end && (c = *str++) != '\0')
5757 /* This recognizes rtx, I classified as expressions. These are always */
5758 /* represent some action on values or results of other expression, */
5759 /* that may be stored in objects representing values. */
5762 print_exp (buf, x, verbose)
5770 char *fun = (char *)0;
5775 for (i = 0; i < 4; i++)
5781 switch (GET_CODE (x))
5784 op[0] = XEXP (x, 0);
5786 op[1] = XEXP (x, 1);
5789 op[0] = XEXP (x, 0);
5791 op[1] = XEXP (x, 1);
5795 op[0] = XEXP (x, 0);
5797 op[1] = XEXP (x, 1);
5801 op[0] = XEXP (x, 0);
5802 op[1] = XEXP (x, 1);
5806 op[0] = XEXP (x, 0);
5809 op[0] = XEXP (x, 0);
5811 op[1] = XEXP (x, 1);
5814 op[0] = XEXP (x, 0);
5816 op[1] = XEXP (x, 1);
5820 op[0] = XEXP (x, 0);
5821 op[1] = XEXP (x, 1);
5824 op[0] = XEXP (x, 0);
5826 op[1] = XEXP (x, 1);
5830 op[0] = XEXP (x, 0);
5831 op[1] = XEXP (x, 1);
5835 op[0] = XEXP (x, 0);
5836 op[1] = XEXP (x, 1);
5840 op[0] = XEXP (x, 0);
5841 op[1] = XEXP (x, 1);
5845 op[0] = XEXP (x, 0);
5846 op[1] = XEXP (x, 1);
5850 op[0] = XEXP (x, 0);
5851 op[1] = XEXP (x, 1);
5855 op[0] = XEXP (x, 0);
5858 op[0] = XEXP (x, 0);
5860 op[1] = XEXP (x, 1);
5863 op[0] = XEXP (x, 0);
5865 op[1] = XEXP (x, 1);
5868 op[0] = XEXP (x, 0);
5870 op[1] = XEXP (x, 1);
5873 op[0] = XEXP (x, 0);
5875 op[1] = XEXP (x, 1);
5878 op[0] = XEXP (x, 0);
5880 op[1] = XEXP (x, 1);
5883 op[0] = XEXP (x, 0);
5885 op[1] = XEXP (x, 1);
5888 op[0] = XEXP (x, 0);
5890 op[1] = XEXP (x, 1);
5893 op[0] = XEXP (x, 0);
5895 op[1] = XEXP (x, 1);
5899 op[0] = XEXP (x, 0);
5903 op[0] = XEXP (x, 0);
5907 op[0] = XEXP (x, 0);
5910 op[0] = XEXP (x, 0);
5912 op[1] = XEXP (x, 1);
5915 op[0] = XEXP (x, 0);
5917 op[1] = XEXP (x, 1);
5920 op[0] = XEXP (x, 0);
5922 op[1] = XEXP (x, 1);
5926 op[0] = XEXP (x, 0);
5927 op[1] = XEXP (x, 1);
5930 op[0] = XEXP (x, 0);
5932 op[1] = XEXP (x, 1);
5936 op[0] = XEXP (x, 0);
5937 op[1] = XEXP (x, 1);
5940 op[0] = XEXP (x, 0);
5942 op[1] = XEXP (x, 1);
5946 op[0] = XEXP (x, 0);
5947 op[1] = XEXP (x, 1);
5950 op[0] = XEXP (x, 0);
5952 op[1] = XEXP (x, 1);
5956 op[0] = XEXP (x, 0);
5957 op[1] = XEXP (x, 1);
5960 fun = (verbose) ? "sign_extract" : "sxt";
5961 op[0] = XEXP (x, 0);
5962 op[1] = XEXP (x, 1);
5963 op[2] = XEXP (x, 2);
5966 fun = (verbose) ? "zero_extract" : "zxt";
5967 op[0] = XEXP (x, 0);
5968 op[1] = XEXP (x, 1);
5969 op[2] = XEXP (x, 2);
5972 fun = (verbose) ? "sign_extend" : "sxn";
5973 op[0] = XEXP (x, 0);
5976 fun = (verbose) ? "zero_extend" : "zxn";
5977 op[0] = XEXP (x, 0);
5980 fun = (verbose) ? "float_extend" : "fxn";
5981 op[0] = XEXP (x, 0);
5984 fun = (verbose) ? "trunc" : "trn";
5985 op[0] = XEXP (x, 0);
5987 case FLOAT_TRUNCATE:
5988 fun = (verbose) ? "float_trunc" : "ftr";
5989 op[0] = XEXP (x, 0);
5992 fun = (verbose) ? "float" : "flt";
5993 op[0] = XEXP (x, 0);
5995 case UNSIGNED_FLOAT:
5996 fun = (verbose) ? "uns_float" : "ufl";
5997 op[0] = XEXP (x, 0);
6001 op[0] = XEXP (x, 0);
6004 fun = (verbose) ? "uns_fix" : "ufx";
6005 op[0] = XEXP (x, 0);
6009 op[0] = XEXP (x, 0);
6013 op[0] = XEXP (x, 0);
6016 op[0] = XEXP (x, 0);
6020 op[0] = XEXP (x, 0);
6025 op[0] = XEXP (x, 0);
6029 op[1] = XEXP (x, 1);
6034 op[0] = XEXP (x, 0);
6036 op[1] = XEXP (x, 1);
6038 op[2] = XEXP (x, 2);
6043 op[0] = TRAP_CONDITION (x);
6046 case UNSPEC_VOLATILE:
6048 cur = safe_concat (buf, cur, "unspec");
6049 if (GET_CODE (x) == UNSPEC_VOLATILE)
6050 cur = safe_concat (buf, cur, "/v");
6051 cur = safe_concat (buf, cur, "[");
6053 for (i = 0; i < XVECLEN (x, 0); i++)
6055 print_pattern (tmp, XVECEXP (x, 0, i), verbose);
6056 cur = safe_concat (buf, cur, sep);
6057 cur = safe_concat (buf, cur, tmp);
6060 cur = safe_concat (buf, cur, "] ");
6061 sprintf (tmp, "%d", XINT (x, 1));
6062 cur = safe_concat (buf, cur, tmp);
6066 /* if (verbose) debug_rtx (x); */
6067 st[0] = GET_RTX_NAME (GET_CODE (x));
6071 /* Print this as a function? */
6074 cur = safe_concat (buf, cur, fun);
6075 cur = safe_concat (buf, cur, "(");
6078 for (i = 0; i < 4; i++)
6081 cur = safe_concat (buf, cur, st[i]);
6086 cur = safe_concat (buf, cur, ",");
6088 print_value (tmp, op[i], verbose);
6089 cur = safe_concat (buf, cur, tmp);
6094 cur = safe_concat (buf, cur, ")");
6097 /* Prints rtxes, i customly classified as values. They're constants, */
6098 /* registers, labels, symbols and memory accesses. */
6101 print_value (buf, x, verbose)
6109 switch (GET_CODE (x))
6112 sprintf (t, "0x%lx", (long)INTVAL (x));
6113 cur = safe_concat (buf, cur, t);
6116 sprintf (t, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3));
6117 cur = safe_concat (buf, cur, t);
6120 cur = safe_concat (buf, cur, "\"");
6121 cur = safe_concat (buf, cur, XSTR (x, 0));
6122 cur = safe_concat (buf, cur, "\"");
6125 cur = safe_concat (buf, cur, "`");
6126 cur = safe_concat (buf, cur, XSTR (x, 0));
6127 cur = safe_concat (buf, cur, "'");
6130 sprintf (t, "L%d", INSN_UID (XEXP (x, 0)));
6131 cur = safe_concat (buf, cur, t);
6134 print_value (t, XEXP (x, 0), verbose);
6135 cur = safe_concat (buf, cur, "const(");
6136 cur = safe_concat (buf, cur, t);
6137 cur = safe_concat (buf, cur, ")");
6140 print_value (t, XEXP (x, 0), verbose);
6141 cur = safe_concat (buf, cur, "high(");
6142 cur = safe_concat (buf, cur, t);
6143 cur = safe_concat (buf, cur, ")");
6146 if (REGNO (x) < FIRST_PSEUDO_REGISTER)
6148 int c = reg_names[ REGNO (x) ][0];
6149 if (c >= '0' && c <= '9')
6150 cur = safe_concat (buf, cur, "%");
6152 cur = safe_concat (buf, cur, reg_names[ REGNO (x) ]);
6156 sprintf (t, "r%d", REGNO (x));
6157 cur = safe_concat (buf, cur, t);
6161 print_value (t, SUBREG_REG (x), verbose);
6162 cur = safe_concat (buf, cur, t);
6163 sprintf (t, "#%d", SUBREG_WORD (x));
6164 cur = safe_concat (buf, cur, t);
6167 cur = safe_concat (buf, cur, "scratch");
6170 cur = safe_concat (buf, cur, "cc0");
6173 cur = safe_concat (buf, cur, "pc");
6176 print_value (t, XEXP (x, 0), verbose);
6177 cur = safe_concat (buf, cur, "[");
6178 cur = safe_concat (buf, cur, t);
6179 cur = safe_concat (buf, cur, "]");
6182 print_exp (t, x, verbose);
6183 cur = safe_concat (buf, cur, t);
6188 /* The next step in insn detalization, its pattern recognition */
6191 print_pattern (buf, x, verbose)
6196 char t1[BUF_LEN], t2[BUF_LEN], t3[BUF_LEN];
6198 switch (GET_CODE (x))
6201 print_value (t1, SET_DEST (x), verbose);
6202 print_value (t2, SET_SRC (x), verbose);
6203 sprintf (buf, "%s=%s", t1, t2);
6206 sprintf (buf, "return");
6209 print_exp (buf, x, verbose);
6212 print_value (t1, XEXP (x, 0), verbose);
6213 sprintf (buf, "clobber %s", t1);
6216 print_value (t1, XEXP (x, 0), verbose);
6217 sprintf (buf, "use %s", t1);
6224 for (i = 0; i < XVECLEN (x, 0); i++)
6226 print_pattern (t2, XVECEXP (x, 0, i), verbose);
6227 sprintf (t3, "%s%s;", t1, t2);
6230 sprintf (buf, "%s}", t1);
6237 sprintf (t1, "%%{");
6238 for (i = 0; i < XVECLEN (x, 0); i++)
6240 print_insn (t2, XVECEXP (x, 0, i), verbose);
6241 sprintf (t3, "%s%s;", t1, t2);
6244 sprintf (buf, "%s%%}", t1);
6248 sprintf (buf, "asm {%s}", XSTR (x, 0));
6253 print_value (buf, XEXP (x, 0), verbose);
6256 print_value (t1, TRAP_CONDITION (x), verbose);
6257 sprintf (buf, "trap_if %s", t1);
6263 sprintf (t1, "unspec{");
6264 for (i = 0; i < XVECLEN (x, 0); i++)
6266 print_pattern (t2, XVECEXP (x, 0, i), verbose);
6267 sprintf (t3, "%s%s;", t1, t2);
6270 sprintf (buf, "%s}", t1);
6273 case UNSPEC_VOLATILE:
6277 sprintf (t1, "unspec/v{");
6278 for (i = 0; i < XVECLEN (x, 0); i++)
6280 print_pattern (t2, XVECEXP (x, 0, i), verbose);
6281 sprintf (t3, "%s%s;", t1, t2);
6284 sprintf (buf, "%s}", t1);
6288 print_value (buf, x, verbose);
6290 } /* print_pattern */
6292 /* This is the main function in rtl visualization mechanism. It
6293 accepts an rtx and tries to recognize it as an insn, then prints it
6294 properly in human readable form, resembling assembler mnemonics. */
6295 /* For every insn it prints its UID and BB the insn belongs */
6296 /* too. (probably the last "option" should be extended somehow, since */
6297 /* it depends now on sched.c inner variables ...) */
6300 print_insn (buf, x, verbose)
6308 switch (GET_CODE (x))
6311 print_pattern (t, PATTERN (x), verbose);
6313 sprintf (buf, "b%d: i% 4d: %s", INSN_BB (x),
6316 sprintf (buf, "%-4d %s", INSN_UID (x), t);
6319 print_pattern (t, PATTERN (x), verbose);
6321 sprintf (buf, "b%d: i% 4d: jump %s", INSN_BB (x),
6324 sprintf (buf, "%-4d %s", INSN_UID (x), t);
6328 if (GET_CODE (x) == PARALLEL)
6330 x = XVECEXP (x, 0, 0);
6331 print_pattern (t, x, verbose);
6334 strcpy (t, "call <...>");
6336 sprintf (buf, "b%d: i% 4d: %s", INSN_BB (insn),
6337 INSN_UID (insn), t);
6339 sprintf (buf, "%-4d %s", INSN_UID (insn), t);
6342 sprintf (buf, "L%d:", INSN_UID (x));
6345 sprintf (buf, "i% 4d: barrier", INSN_UID (x));
6348 if (NOTE_LINE_NUMBER (x) > 0)
6349 sprintf (buf, "%4d note \"%s\" %d", INSN_UID (x),
6350 NOTE_SOURCE_FILE (x), NOTE_LINE_NUMBER (x));
6352 sprintf (buf, "%4d %s", INSN_UID (x),
6353 GET_NOTE_INSN_NAME (NOTE_LINE_NUMBER (x)));
6358 sprintf (buf, "Not an INSN at all\n");
6362 sprintf (buf, "i%-4d <What?>", INSN_UID (x));
6366 /* Print visualization debugging info */
6369 print_block_visualization (b, s)
6376 fprintf (dump, "\n;; ==================== scheduling visualization for block %d %s \n", b, s);
6378 /* Print names of units */
6379 fprintf (dump, ";; %-8s", "clock");
6380 for (unit = 0; unit < FUNCTION_UNITS_SIZE; unit++)
6381 if (function_units[unit].bitmask & target_units)
6382 for (i = 0; i < function_units[unit].multiplicity; i++)
6383 fprintf (dump, " %-33s", function_units[unit].name);
6384 fprintf (dump, " %-8s\n", "no-unit");
6386 fprintf (dump, ";; %-8s", "=====");
6387 for (unit = 0; unit < FUNCTION_UNITS_SIZE; unit++)
6388 if (function_units[unit].bitmask & target_units)
6389 for (i = 0; i < function_units[unit].multiplicity; i++)
6390 fprintf (dump, " %-33s", "==============================");
6391 fprintf (dump, " %-8s\n", "=======");
6393 /* Print insns in each cycle */
6394 fprintf (dump, "%s\n", visual_tbl);
6397 /* Print insns in the 'no_unit' column of visualization */
6400 visualize_no_unit (insn)
6403 vis_no_unit[n_vis_no_unit] = insn;
6407 /* Print insns scheduled in clock, for visualization. */
6410 visualize_scheduled_insns (b, clock)
6415 /* if no more room, split table into two */
6416 if (n_visual_lines >= MAX_VISUAL_LINES)
6418 print_block_visualization (b, "(incomplete)");
6419 init_block_visualization ();
6424 sprintf (visual_tbl + strlen (visual_tbl), ";; %-8d", clock);
6425 for (unit = 0; unit < FUNCTION_UNITS_SIZE; unit++)
6426 if (function_units[unit].bitmask & target_units)
6427 for (i = 0; i < function_units[unit].multiplicity; i++)
6429 int instance = unit + i * FUNCTION_UNITS_SIZE;
6430 rtx insn = unit_last_insn[instance];
6432 /* print insns that still keep the unit busy */
6434 actual_hazard_this_instance (unit, instance, insn, clock, 0))
6437 print_insn (str, insn, 0);
6438 str[INSN_LEN] = '\0';
6439 sprintf (visual_tbl + strlen (visual_tbl), " %-33s", str);
6442 sprintf (visual_tbl + strlen (visual_tbl), " %-33s", "------------------------------");
6445 /* print insns that are not assigned to any unit */
6446 for (i = 0; i < n_vis_no_unit; i++)
6447 sprintf (visual_tbl + strlen (visual_tbl), " %-8d",
6448 INSN_UID (vis_no_unit[i]));
6451 sprintf (visual_tbl + strlen (visual_tbl), "\n");
6454 /* Print stalled cycles */
6457 visualize_stall_cycles (b, stalls)
6462 /* if no more room, split table into two */
6463 if (n_visual_lines >= MAX_VISUAL_LINES)
6465 print_block_visualization (b, "(incomplete)");
6466 init_block_visualization ();
6471 sprintf (visual_tbl + strlen (visual_tbl), ";; ");
6472 for (i = 0; i < stalls; i++)
6473 sprintf (visual_tbl + strlen (visual_tbl), ".");
6474 sprintf (visual_tbl + strlen (visual_tbl), "\n");
6477 /* move_insn1: Remove INSN from insn chain, and link it after LAST insn */
6480 move_insn1 (insn, last)
6483 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
6484 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
6486 NEXT_INSN (insn) = NEXT_INSN (last);
6487 PREV_INSN (NEXT_INSN (last)) = insn;
6489 NEXT_INSN (last) = insn;
6490 PREV_INSN (insn) = last;
6495 /* Search INSN for fake REG_DEAD note pairs for NOTE_INSN_SETJMP,
6496 NOTE_INSN_{LOOP,EHREGION}_{BEG,END}; and convert them back into
6497 NOTEs. The REG_DEAD note following first one is contains the saved
6498 value for NOTE_BLOCK_NUMBER which is useful for
6499 NOTE_INSN_EH_REGION_{BEG,END} NOTEs. LAST is the last instruction
6500 output by the instruction scheduler. Return the new value of LAST. */
6503 reemit_notes (insn, last)
6510 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
6512 if (REG_NOTE_KIND (note) == REG_DEAD
6513 && GET_CODE (XEXP (note, 0)) == CONST_INT)
6515 int note_type = INTVAL (XEXP (note, 0));
6516 if (note_type == NOTE_INSN_SETJMP)
6518 retval = emit_note_after (NOTE_INSN_SETJMP, insn);
6519 CONST_CALL_P (retval) = CONST_CALL_P (note);
6520 remove_note (insn, note);
6521 note = XEXP (note, 1);
6523 else if (note_type == NOTE_INSN_RANGE_START
6524 || note_type == NOTE_INSN_RANGE_END)
6526 last = emit_note_before (note_type, last);
6527 remove_note (insn, note);
6528 note = XEXP (note, 1);
6529 NOTE_RANGE_INFO (last) = XEXP (note, 0);
6533 last = emit_note_before (INTVAL (XEXP (note, 0)), last);
6534 remove_note (insn, note);
6535 note = XEXP (note, 1);
6536 NOTE_BLOCK_NUMBER (last) = INTVAL (XEXP (note, 0));
6538 remove_note (insn, note);
6544 /* Move INSN, and all insns which should be issued before it,
6545 due to SCHED_GROUP_P flag. Reemit notes if needed.
6547 Return the last insn emitted by the scheduler, which is the
6548 return value from the first call to reemit_notes. */
6551 move_insn (insn, last)
6556 /* If INSN has SCHED_GROUP_P set, then issue it and any other
6557 insns with SCHED_GROUP_P set first. */
6558 while (SCHED_GROUP_P (insn))
6560 rtx prev = PREV_INSN (insn);
6562 /* Move a SCHED_GROUP_P insn. */
6563 move_insn1 (insn, last);
6564 /* If this is the first call to reemit_notes, then record
6565 its return value. */
6566 if (retval == NULL_RTX)
6567 retval = reemit_notes (insn, insn);
6569 reemit_notes (insn, insn);
6573 /* Now move the first non SCHED_GROUP_P insn. */
6574 move_insn1 (insn, last);
6576 /* If this is the first call to reemit_notes, then record
6577 its return value. */
6578 if (retval == NULL_RTX)
6579 retval = reemit_notes (insn, insn);
6581 reemit_notes (insn, insn);
6586 /* Return an insn which represents a SCHED_GROUP, which is
6587 the last insn in the group. */
6598 insn = next_nonnote_insn (insn);
6600 while (insn && SCHED_GROUP_P (insn) && (GET_CODE (insn) != CODE_LABEL));
6605 /* Use forward list scheduling to rearrange insns of block BB in region RGN,
6606 possibly bringing insns from subsequent blocks in the same region.
6607 Return number of insns scheduled. */
6610 schedule_block (bb, rgn_n_insns)
6614 /* Local variables. */
6621 /* flow block of this bb */
6622 int b = BB_TO_BLOCK (bb);
6624 /* target_n_insns == number of insns in b before scheduling starts.
6625 sched_target_n_insns == how many of b's insns were scheduled.
6626 sched_n_insns == how many insns were scheduled in b */
6627 int target_n_insns = 0;
6628 int sched_target_n_insns = 0;
6629 int sched_n_insns = 0;
6631 #define NEED_NOTHING 0
6636 /* head/tail info for this block */
6643 /* We used to have code to avoid getting parameters moved from hard
6644 argument registers into pseudos.
6646 However, it was removed when it proved to be of marginal benefit
6647 and caused problems because schedule_block and compute_forward_dependences
6648 had different notions of what the "head" insn was. */
6649 get_block_head_tail (bb, &head, &tail);
6651 /* Interblock scheduling could have moved the original head insn from this
6652 block into a proceeding block. This may also cause schedule_block and
6653 compute_forward_dependences to have different notions of what the
6656 If the interblock movement happened to make this block start with
6657 some notes (LOOP, EH or SETJMP) before the first real insn, then
6658 HEAD will have various special notes attached to it which must be
6659 removed so that we don't end up with extra copies of the notes. */
6660 if (GET_RTX_CLASS (GET_CODE (head)) == 'i')
6664 for (note = REG_NOTES (head); note; note = XEXP (note, 1))
6665 if (REG_NOTE_KIND (note) == REG_DEAD
6666 && GET_CODE (XEXP (note, 0)) == CONST_INT)
6667 remove_note (head, note);
6670 next_tail = NEXT_INSN (tail);
6671 prev_head = PREV_INSN (head);
6673 /* If the only insn left is a NOTE or a CODE_LABEL, then there is no need
6674 to schedule this block. */
6676 && (GET_RTX_CLASS (GET_CODE (head)) != 'i'))
6677 return (sched_n_insns);
6682 fprintf (dump, ";; ======================================================\n");
6684 ";; -- basic block %d from %d to %d -- %s reload\n",
6685 b, INSN_UID (basic_block_head[b]),
6686 INSN_UID (basic_block_end[b]),
6687 (reload_completed ? "after" : "before"));
6688 fprintf (dump, ";; ======================================================\n");
6689 fprintf (dump, "\n");
6691 visual_tbl = (char *) alloca (get_visual_tbl_length ());
6692 init_block_visualization ();
6695 /* remove remaining note insns from the block, save them in
6696 note_list. These notes are restored at the end of
6697 schedule_block (). */
6699 rm_other_notes (head, tail);
6703 /* prepare current target block info */
6704 if (current_nr_blocks > 1)
6706 candidate_table = (candidate *) alloca (current_nr_blocks * sizeof (candidate));
6709 /* ??? It is not clear why bblst_size is computed this way. The original
6710 number was clearly too small as it resulted in compiler failures.
6711 Multiplying by the original number by 2 (to account for update_bbs
6712 members) seems to be a reasonable solution. */
6713 /* ??? Or perhaps there is a bug somewhere else in this file? */
6714 bblst_size = (current_nr_blocks - bb) * rgn_nr_edges * 2;
6715 bblst_table = (int *) alloca (bblst_size * sizeof (int));
6717 bitlst_table_last = 0;
6718 bitlst_table_size = rgn_nr_edges;
6719 bitlst_table = (int *) alloca (rgn_nr_edges * sizeof (int));
6721 compute_trg_info (bb);
6726 /* Allocate the ready list */
6727 ready = (rtx *) alloca ((rgn_n_insns + 1) * sizeof (rtx));
6729 /* Print debugging information. */
6730 if (sched_verbose >= 5)
6731 debug_dependencies ();
6734 /* Initialize ready list with all 'ready' insns in target block.
6735 Count number of insns in the target block being scheduled. */
6737 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
6741 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
6743 next = NEXT_INSN (insn);
6745 if (INSN_DEP_COUNT (insn) == 0
6746 && (SCHED_GROUP_P (next) == 0 || GET_RTX_CLASS (GET_CODE (next)) != 'i'))
6747 ready[n_ready++] = insn;
6748 if (!(SCHED_GROUP_P (insn)))
6752 /* Add to ready list all 'ready' insns in valid source blocks.
6753 For speculative insns, check-live, exception-free, and
6755 for (bb_src = bb + 1; bb_src < current_nr_blocks; bb_src++)
6756 if (IS_VALID (bb_src))
6762 get_block_head_tail (bb_src, &head, &tail);
6763 src_next_tail = NEXT_INSN (tail);
6767 && (GET_RTX_CLASS (GET_CODE (head)) != 'i'))
6770 for (insn = src_head; insn != src_next_tail; insn = NEXT_INSN (insn))
6772 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
6775 if (!CANT_MOVE (insn)
6776 && (!IS_SPECULATIVE_INSN (insn)
6777 || (insn_issue_delay (insn) <= 3
6778 && check_live (insn, bb_src)
6779 && is_exception_free (insn, bb_src, target_bb))))
6784 next = NEXT_INSN (insn);
6785 if (INSN_DEP_COUNT (insn) == 0
6786 && (SCHED_GROUP_P (next) == 0
6787 || GET_RTX_CLASS (GET_CODE (next)) != 'i'))
6788 ready[n_ready++] = insn;
6793 #ifdef MD_SCHED_INIT
6794 MD_SCHED_INIT (dump, sched_verbose);
6797 /* no insns scheduled in this block yet */
6798 last_scheduled_insn = 0;
6800 /* Sort the ready list */
6801 SCHED_SORT (ready, n_ready);
6802 #ifdef MD_SCHED_REORDER
6803 MD_SCHED_REORDER (dump, sched_verbose, ready, n_ready);
6806 if (sched_verbose >= 2)
6808 fprintf (dump, ";;\t\tReady list initially: ");
6809 debug_ready_list (ready, n_ready);
6812 /* Q_SIZE is the total number of insns in the queue. */
6817 bzero ((char *) insn_queue, sizeof (insn_queue));
6819 /* We start inserting insns after PREV_HEAD. */
6822 /* Initialize INSN_QUEUE, LIST and NEW_NEEDS. */
6823 new_needs = (NEXT_INSN (prev_head) == basic_block_head[b]
6824 ? NEED_HEAD : NEED_NOTHING);
6825 if (PREV_INSN (next_tail) == basic_block_end[b])
6826 new_needs |= NEED_TAIL;
6828 /* loop until all the insns in BB are scheduled. */
6829 while (sched_target_n_insns < target_n_insns)
6835 /* Add to the ready list all pending insns that can be issued now.
6836 If there are no ready insns, increment clock until one
6837 is ready and add all pending insns at that point to the ready
6839 n_ready = queue_to_ready (ready, n_ready);
6844 if (sched_verbose >= 2)
6846 fprintf (dump, ";;\t\tReady list after queue_to_ready: ");
6847 debug_ready_list (ready, n_ready);
6850 /* Sort the ready list. */
6851 SCHED_SORT (ready, n_ready);
6852 #ifdef MD_SCHED_REORDER
6853 MD_SCHED_REORDER (dump, sched_verbose, ready, n_ready);
6858 fprintf (dump, "\n;;\tReady list (t =%3d): ", clock_var);
6859 debug_ready_list (ready, n_ready);
6862 /* Issue insns from ready list.
6863 It is important to count down from n_ready, because n_ready may change
6864 as insns are issued. */
6865 can_issue_more = issue_rate;
6866 for (i = n_ready - 1; i >= 0 && can_issue_more; i--)
6868 rtx insn = ready[i];
6869 int cost = actual_hazard (insn_unit (insn), insn, clock_var, 0);
6873 queue_insn (insn, cost);
6874 ready[i] = ready[--n_ready]; /* remove insn from ready list */
6878 /* an interblock motion? */
6879 if (INSN_BB (insn) != target_bb)
6883 if (IS_SPECULATIVE_INSN (insn))
6886 if (!check_live (insn, INSN_BB (insn)))
6888 /* speculative motion, live check failed, remove
6889 insn from ready list */
6890 ready[i] = ready[--n_ready];
6893 update_live (insn, INSN_BB (insn));
6895 /* for speculative load, mark insns fed by it. */
6896 if (IS_LOAD_INSN (insn) || FED_BY_SPEC_LOAD (insn))
6897 set_spec_fed (insn);
6904 while (SCHED_GROUP_P (temp))
6905 temp = PREV_INSN (temp);
6907 /* Update source block boundaries. */
6908 b1 = INSN_BLOCK (temp);
6909 if (temp == basic_block_head[b1]
6910 && insn == basic_block_end[b1])
6912 /* We moved all the insns in the basic block.
6913 Emit a note after the last insn and update the
6914 begin/end boundaries to point to the note. */
6915 emit_note_after (NOTE_INSN_DELETED, insn);
6916 basic_block_end[b1] = NEXT_INSN (insn);
6917 basic_block_head[b1] = NEXT_INSN (insn);
6919 else if (insn == basic_block_end[b1])
6921 /* We took insns from the end of the basic block,
6922 so update the end of block boundary so that it
6923 points to the first insn we did not move. */
6924 basic_block_end[b1] = PREV_INSN (temp);
6926 else if (temp == basic_block_head[b1])
6928 /* We took insns from the start of the basic block,
6929 so update the start of block boundary so that
6930 it points to the first insn we did not move. */
6931 basic_block_head[b1] = NEXT_INSN (insn);
6936 /* in block motion */
6937 sched_target_n_insns++;
6940 last_scheduled_insn = insn;
6941 last = move_insn (insn, last);
6944 #ifdef MD_SCHED_VARIABLE_ISSUE
6945 MD_SCHED_VARIABLE_ISSUE (dump, sched_verbose, insn, can_issue_more);
6950 n_ready = schedule_insn (insn, ready, n_ready, clock_var);
6952 /* remove insn from ready list */
6953 ready[i] = ready[--n_ready];
6955 /* close this block after scheduling its jump */
6956 if (GET_CODE (last_scheduled_insn) == JUMP_INSN)
6964 visualize_scheduled_insns (b, clock_var);
6971 fprintf (dump, ";;\tReady list (final): ");
6972 debug_ready_list (ready, n_ready);
6973 print_block_visualization (b, "");
6976 /* Sanity check -- queue must be empty now. Meaningless if region has
6978 if (current_nr_blocks > 1)
6979 if (!flag_schedule_interblock && q_size != 0)
6982 /* update head/tail boundaries. */
6983 head = NEXT_INSN (prev_head);
6986 /* Restore-other-notes: NOTE_LIST is the end of a chain of notes
6987 previously found among the insns. Insert them at the beginning
6991 rtx note_head = note_list;
6993 while (PREV_INSN (note_head))
6995 note_head = PREV_INSN (note_head);
6998 PREV_INSN (note_head) = PREV_INSN (head);
6999 NEXT_INSN (PREV_INSN (head)) = note_head;
7000 PREV_INSN (head) = note_list;
7001 NEXT_INSN (note_list) = head;
7005 /* update target block boundaries. */
7006 if (new_needs & NEED_HEAD)
7007 basic_block_head[b] = head;
7009 if (new_needs & NEED_TAIL)
7010 basic_block_end[b] = tail;
7015 fprintf (dump, ";; total time = %d\n;; new basic block head = %d\n",
7016 clock_var, INSN_UID (basic_block_head[b]));
7017 fprintf (dump, ";; new basic block end = %d\n\n",
7018 INSN_UID (basic_block_end[b]));
7021 return (sched_n_insns);
7022 } /* schedule_block () */
7025 /* print the bit-set of registers, S. callable from debugger */
7028 debug_reg_vector (s)
7033 EXECUTE_IF_SET_IN_REG_SET (s, 0, regno,
7035 fprintf (dump, " %d", regno);
7038 fprintf (dump, "\n");
7041 /* Use the backward dependences from LOG_LINKS to build
7042 forward dependences in INSN_DEPEND. */
7045 compute_block_forward_dependences (bb)
7051 enum reg_note dep_type;
7053 get_block_head_tail (bb, &head, &tail);
7054 next_tail = NEXT_INSN (tail);
7055 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
7057 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
7060 insn = group_leader (insn);
7062 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
7064 rtx x = group_leader (XEXP (link, 0));
7067 if (x != XEXP (link, 0))
7070 /* Ignore dependences upon deleted insn */
7071 if (GET_CODE (x) == NOTE || INSN_DELETED_P (x))
7073 if (find_insn_list (insn, INSN_DEPEND (x)))
7076 new_link = alloc_INSN_LIST (insn, INSN_DEPEND (x));
7078 dep_type = REG_NOTE_KIND (link);
7079 PUT_REG_NOTE_KIND (new_link, dep_type);
7081 INSN_DEPEND (x) = new_link;
7082 INSN_DEP_COUNT (insn) += 1;
7087 /* Initialize variables for region data dependence analysis.
7088 n_bbs is the number of region blocks */
7090 __inline static void
7091 init_rgn_data_dependences (n_bbs)
7096 /* variables for which one copy exists for each block */
7097 bzero ((char *) bb_pending_read_insns, n_bbs * sizeof (rtx));
7098 bzero ((char *) bb_pending_read_mems, n_bbs * sizeof (rtx));
7099 bzero ((char *) bb_pending_write_insns, n_bbs * sizeof (rtx));
7100 bzero ((char *) bb_pending_write_mems, n_bbs * sizeof (rtx));
7101 bzero ((char *) bb_pending_lists_length, n_bbs * sizeof (rtx));
7102 bzero ((char *) bb_last_pending_memory_flush, n_bbs * sizeof (rtx));
7103 bzero ((char *) bb_last_function_call, n_bbs * sizeof (rtx));
7104 bzero ((char *) bb_sched_before_next_call, n_bbs * sizeof (rtx));
7106 /* Create an insn here so that we can hang dependencies off of it later. */
7107 for (bb = 0; bb < n_bbs; bb++)
7109 bb_sched_before_next_call[bb] =
7110 gen_rtx_INSN (VOIDmode, 0, NULL_RTX, NULL_RTX,
7111 NULL_RTX, 0, NULL_RTX, NULL_RTX);
7112 LOG_LINKS (bb_sched_before_next_call[bb]) = 0;
7116 /* Add dependences so that branches are scheduled to run last in their block */
7119 add_branch_dependences (head, tail)
7125 /* For all branches, calls, uses, and cc0 setters, force them to remain
7126 in order at the end of the block by adding dependencies and giving
7127 the last a high priority. There may be notes present, and prev_head
7130 Branches must obviously remain at the end. Calls should remain at the
7131 end since moving them results in worse register allocation. Uses remain
7132 at the end to ensure proper register allocation. cc0 setters remaim
7133 at the end because they can't be moved away from their cc0 user. */
7136 while (GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN
7137 || (GET_CODE (insn) == INSN
7138 && (GET_CODE (PATTERN (insn)) == USE
7140 || sets_cc0_p (PATTERN (insn))
7143 || GET_CODE (insn) == NOTE)
7145 if (GET_CODE (insn) != NOTE)
7148 && !find_insn_list (insn, LOG_LINKS (last)))
7150 add_dependence (last, insn, REG_DEP_ANTI);
7151 INSN_REF_COUNT (insn)++;
7154 CANT_MOVE (insn) = 1;
7157 /* Skip over insns that are part of a group.
7158 Make each insn explicitly depend on the previous insn.
7159 This ensures that only the group header will ever enter
7160 the ready queue (and, when scheduled, will automatically
7161 schedule the SCHED_GROUP_P block). */
7162 while (SCHED_GROUP_P (insn))
7164 rtx temp = prev_nonnote_insn (insn);
7165 add_dependence (insn, temp, REG_DEP_ANTI);
7170 /* Don't overrun the bounds of the basic block. */
7174 insn = PREV_INSN (insn);
7177 /* make sure these insns are scheduled last in their block */
7180 while (insn != head)
7182 insn = prev_nonnote_insn (insn);
7184 if (INSN_REF_COUNT (insn) != 0)
7187 if (!find_insn_list (last, LOG_LINKS (insn)))
7188 add_dependence (last, insn, REG_DEP_ANTI);
7189 INSN_REF_COUNT (insn) = 1;
7191 /* Skip over insns that are part of a group. */
7192 while (SCHED_GROUP_P (insn))
7193 insn = prev_nonnote_insn (insn);
7197 /* Compute bacward dependences inside BB. In a multiple blocks region:
7198 (1) a bb is analyzed after its predecessors, and (2) the lists in
7199 effect at the end of bb (after analyzing for bb) are inherited by
7202 Specifically for reg-reg data dependences, the block insns are
7203 scanned by sched_analyze () top-to-bottom. Two lists are
7204 naintained by sched_analyze (): reg_last_defs[] for register DEFs,
7205 and reg_last_uses[] for register USEs.
7207 When analysis is completed for bb, we update for its successors:
7208 ; - DEFS[succ] = Union (DEFS [succ], DEFS [bb])
7209 ; - USES[succ] = Union (USES [succ], DEFS [bb])
7211 The mechanism for computing mem-mem data dependence is very
7212 similar, and the result is interblock dependences in the region. */
7215 compute_block_backward_dependences (bb)
7221 int max_reg = max_reg_num ();
7223 b = BB_TO_BLOCK (bb);
7225 if (current_nr_blocks == 1)
7227 reg_last_uses = (rtx *) alloca (max_reg * sizeof (rtx));
7228 reg_last_sets = (rtx *) alloca (max_reg * sizeof (rtx));
7230 bzero ((char *) reg_last_uses, max_reg * sizeof (rtx));
7231 bzero ((char *) reg_last_sets, max_reg * sizeof (rtx));
7233 pending_read_insns = 0;
7234 pending_read_mems = 0;
7235 pending_write_insns = 0;
7236 pending_write_mems = 0;
7237 pending_lists_length = 0;
7238 last_function_call = 0;
7239 last_pending_memory_flush = 0;
7240 sched_before_next_call
7241 = gen_rtx_INSN (VOIDmode, 0, NULL_RTX, NULL_RTX,
7242 NULL_RTX, 0, NULL_RTX, NULL_RTX);
7243 LOG_LINKS (sched_before_next_call) = 0;
7247 reg_last_uses = bb_reg_last_uses[bb];
7248 reg_last_sets = bb_reg_last_sets[bb];
7250 pending_read_insns = bb_pending_read_insns[bb];
7251 pending_read_mems = bb_pending_read_mems[bb];
7252 pending_write_insns = bb_pending_write_insns[bb];
7253 pending_write_mems = bb_pending_write_mems[bb];
7254 pending_lists_length = bb_pending_lists_length[bb];
7255 last_function_call = bb_last_function_call[bb];
7256 last_pending_memory_flush = bb_last_pending_memory_flush[bb];
7258 sched_before_next_call = bb_sched_before_next_call[bb];
7261 /* do the analysis for this block */
7262 get_block_head_tail (bb, &head, &tail);
7263 sched_analyze (head, tail);
7264 add_branch_dependences (head, tail);
7266 if (current_nr_blocks > 1)
7269 int b_succ, bb_succ;
7271 rtx link_insn, link_mem;
7274 /* these lists should point to the right place, for correct freeing later. */
7275 bb_pending_read_insns[bb] = pending_read_insns;
7276 bb_pending_read_mems[bb] = pending_read_mems;
7277 bb_pending_write_insns[bb] = pending_write_insns;
7278 bb_pending_write_mems[bb] = pending_write_mems;
7280 /* bb's structures are inherited by it's successors */
7281 first_edge = e = OUT_EDGES (b);
7285 b_succ = TO_BLOCK (e);
7286 bb_succ = BLOCK_TO_BB (b_succ);
7288 /* only bbs "below" bb, in the same region, are interesting */
7289 if (CONTAINING_RGN (b) != CONTAINING_RGN (b_succ)
7296 for (reg = 0; reg < max_reg; reg++)
7299 /* reg-last-uses lists are inherited by bb_succ */
7300 for (u = reg_last_uses[reg]; u; u = XEXP (u, 1))
7302 if (find_insn_list (XEXP (u, 0), (bb_reg_last_uses[bb_succ])[reg]))
7305 (bb_reg_last_uses[bb_succ])[reg]
7306 = alloc_INSN_LIST (XEXP (u, 0),
7307 (bb_reg_last_uses[bb_succ])[reg]);
7310 /* reg-last-defs lists are inherited by bb_succ */
7311 for (u = reg_last_sets[reg]; u; u = XEXP (u, 1))
7313 if (find_insn_list (XEXP (u, 0), (bb_reg_last_sets[bb_succ])[reg]))
7316 (bb_reg_last_sets[bb_succ])[reg]
7317 = alloc_INSN_LIST (XEXP (u, 0),
7318 (bb_reg_last_sets[bb_succ])[reg]);
7322 /* mem read/write lists are inherited by bb_succ */
7323 link_insn = pending_read_insns;
7324 link_mem = pending_read_mems;
7327 if (!(find_insn_mem_list (XEXP (link_insn, 0), XEXP (link_mem, 0),
7328 bb_pending_read_insns[bb_succ],
7329 bb_pending_read_mems[bb_succ])))
7330 add_insn_mem_dependence (&bb_pending_read_insns[bb_succ],
7331 &bb_pending_read_mems[bb_succ],
7332 XEXP (link_insn, 0), XEXP (link_mem, 0));
7333 link_insn = XEXP (link_insn, 1);
7334 link_mem = XEXP (link_mem, 1);
7337 link_insn = pending_write_insns;
7338 link_mem = pending_write_mems;
7341 if (!(find_insn_mem_list (XEXP (link_insn, 0), XEXP (link_mem, 0),
7342 bb_pending_write_insns[bb_succ],
7343 bb_pending_write_mems[bb_succ])))
7344 add_insn_mem_dependence (&bb_pending_write_insns[bb_succ],
7345 &bb_pending_write_mems[bb_succ],
7346 XEXP (link_insn, 0), XEXP (link_mem, 0));
7348 link_insn = XEXP (link_insn, 1);
7349 link_mem = XEXP (link_mem, 1);
7352 /* last_function_call is inherited by bb_succ */
7353 for (u = last_function_call; u; u = XEXP (u, 1))
7355 if (find_insn_list (XEXP (u, 0), bb_last_function_call[bb_succ]))
7358 bb_last_function_call[bb_succ]
7359 = alloc_INSN_LIST (XEXP (u, 0),
7360 bb_last_function_call[bb_succ]);
7363 /* last_pending_memory_flush is inherited by bb_succ */
7364 for (u = last_pending_memory_flush; u; u = XEXP (u, 1))
7366 if (find_insn_list (XEXP (u, 0), bb_last_pending_memory_flush[bb_succ]))
7369 bb_last_pending_memory_flush[bb_succ]
7370 = alloc_INSN_LIST (XEXP (u, 0),
7371 bb_last_pending_memory_flush[bb_succ]);
7374 /* sched_before_next_call is inherited by bb_succ */
7375 x = LOG_LINKS (sched_before_next_call);
7376 for (; x; x = XEXP (x, 1))
7377 add_dependence (bb_sched_before_next_call[bb_succ],
7378 XEXP (x, 0), REG_DEP_ANTI);
7382 while (e != first_edge);
7385 /* Free up the INSN_LISTs
7387 Note this loop is executed max_reg * nr_regions times. It's first
7388 implementation accounted for over 90% of the calls to free_list.
7389 The list was empty for the vast majority of those calls. On the PA,
7390 not calling free_list in those cases improves -O2 compile times by
7392 for (b = 0; b < max_reg; ++b)
7394 if (reg_last_sets[b])
7395 free_list (®_last_sets[b], &unused_insn_list);
7396 if (reg_last_uses[b])
7397 free_list (®_last_uses[b], &unused_insn_list);
7400 /* Assert that we won't need bb_reg_last_* for this block anymore. */
7401 if (current_nr_blocks > 1)
7403 bb_reg_last_uses[bb] = (rtx *) NULL_RTX;
7404 bb_reg_last_sets[bb] = (rtx *) NULL_RTX;
7408 /* Print dependences for debugging, callable from debugger */
7411 debug_dependencies ()
7415 fprintf (dump, ";; --------------- forward dependences: ------------ \n");
7416 for (bb = 0; bb < current_nr_blocks; bb++)
7424 get_block_head_tail (bb, &head, &tail);
7425 next_tail = NEXT_INSN (tail);
7426 fprintf (dump, "\n;; --- Region Dependences --- b %d bb %d \n",
7427 BB_TO_BLOCK (bb), bb);
7429 fprintf (dump, ";; %7s%6s%6s%6s%6s%6s%11s%6s\n",
7430 "insn", "code", "bb", "dep", "prio", "cost", "blockage", "units");
7431 fprintf (dump, ";; %7s%6s%6s%6s%6s%6s%11s%6s\n",
7432 "----", "----", "--", "---", "----", "----", "--------", "-----");
7433 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
7438 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
7441 fprintf (dump, ";; %6d ", INSN_UID (insn));
7442 if (GET_CODE (insn) == NOTE)
7444 n = NOTE_LINE_NUMBER (insn);
7446 fprintf (dump, "%s\n", GET_NOTE_INSN_NAME (n));
7448 fprintf (dump, "line %d, file %s\n", n,
7449 NOTE_SOURCE_FILE (insn));
7452 fprintf (dump, " {%s}\n", GET_RTX_NAME (GET_CODE (insn)));
7456 unit = insn_unit (insn);
7458 || function_units[unit].blockage_range_function == 0) ? 0 :
7459 function_units[unit].blockage_range_function (insn);
7461 ";; %s%5d%6d%6d%6d%6d%6d %3d -%3d ",
7462 (SCHED_GROUP_P (insn) ? "+" : " "),
7466 INSN_DEP_COUNT (insn),
7467 INSN_PRIORITY (insn),
7468 insn_cost (insn, 0, 0),
7469 (int) MIN_BLOCKAGE_COST (range),
7470 (int) MAX_BLOCKAGE_COST (range));
7471 insn_print_units (insn);
7472 fprintf (dump, "\t: ");
7473 for (link = INSN_DEPEND (insn); link; link = XEXP (link, 1))
7474 fprintf (dump, "%d ", INSN_UID (XEXP (link, 0)));
7475 fprintf (dump, "\n");
7479 fprintf (dump, "\n");
7482 /* Set_priorities: compute priority of each insn in the block */
7495 get_block_head_tail (bb, &head, &tail);
7496 prev_head = PREV_INSN (head);
7499 && (GET_RTX_CLASS (GET_CODE (head)) != 'i'))
7503 for (insn = tail; insn != prev_head; insn = PREV_INSN (insn))
7506 if (GET_CODE (insn) == NOTE)
7509 if (!(SCHED_GROUP_P (insn)))
7511 (void) priority (insn);
7517 /* Make each element of VECTOR point at an rtx-vector,
7518 taking the space for all those rtx-vectors from SPACE.
7519 SPACE is of type (rtx *), but it is really as long as NELTS rtx-vectors.
7520 BYTES_PER_ELT is the number of bytes in one rtx-vector.
7521 (this is the same as init_regset_vector () in flow.c) */
7524 init_rtx_vector (vector, space, nelts, bytes_per_elt)
7531 register rtx *p = space;
7533 for (i = 0; i < nelts; i++)
7536 p += bytes_per_elt / sizeof (*p);
7540 /* Schedule a region. A region is either an inner loop, a loop-free
7541 subroutine, or a single basic block. Each bb in the region is
7542 scheduled after its flow predecessors. */
7545 schedule_region (rgn)
7549 int rgn_n_insns = 0;
7550 int sched_rgn_n_insns = 0;
7552 /* set variables for the current region */
7553 current_nr_blocks = RGN_NR_BLOCKS (rgn);
7554 current_blocks = RGN_BLOCKS (rgn);
7556 reg_pending_sets = ALLOCA_REG_SET ();
7557 reg_pending_sets_all = 0;
7559 /* initializations for region data dependence analyisis */
7560 if (current_nr_blocks > 1)
7563 int maxreg = max_reg_num ();
7565 bb_reg_last_uses = (rtx **) alloca (current_nr_blocks * sizeof (rtx *));
7566 space = (rtx *) alloca (current_nr_blocks * maxreg * sizeof (rtx));
7567 bzero ((char *) space, current_nr_blocks * maxreg * sizeof (rtx));
7568 init_rtx_vector (bb_reg_last_uses, space, current_nr_blocks, maxreg * sizeof (rtx *));
7570 bb_reg_last_sets = (rtx **) alloca (current_nr_blocks * sizeof (rtx *));
7571 space = (rtx *) alloca (current_nr_blocks * maxreg * sizeof (rtx));
7572 bzero ((char *) space, current_nr_blocks * maxreg * sizeof (rtx));
7573 init_rtx_vector (bb_reg_last_sets, space, current_nr_blocks, maxreg * sizeof (rtx *));
7575 bb_pending_read_insns = (rtx *) alloca (current_nr_blocks * sizeof (rtx));
7576 bb_pending_read_mems = (rtx *) alloca (current_nr_blocks * sizeof (rtx));
7577 bb_pending_write_insns = (rtx *) alloca (current_nr_blocks * sizeof (rtx));
7578 bb_pending_write_mems = (rtx *) alloca (current_nr_blocks * sizeof (rtx));
7579 bb_pending_lists_length = (int *) alloca (current_nr_blocks * sizeof (int));
7580 bb_last_pending_memory_flush = (rtx *) alloca (current_nr_blocks * sizeof (rtx));
7581 bb_last_function_call = (rtx *) alloca (current_nr_blocks * sizeof (rtx));
7582 bb_sched_before_next_call = (rtx *) alloca (current_nr_blocks * sizeof (rtx));
7584 init_rgn_data_dependences (current_nr_blocks);
7587 /* compute LOG_LINKS */
7588 for (bb = 0; bb < current_nr_blocks; bb++)
7589 compute_block_backward_dependences (bb);
7591 /* compute INSN_DEPEND */
7592 for (bb = current_nr_blocks - 1; bb >= 0; bb--)
7593 compute_block_forward_dependences (bb);
7595 /* Delete line notes, compute live-regs at block end, and set priorities. */
7597 for (bb = 0; bb < current_nr_blocks; bb++)
7599 if (reload_completed == 0)
7600 find_pre_sched_live (bb);
7602 if (write_symbols != NO_DEBUG)
7604 save_line_notes (bb);
7608 rgn_n_insns += set_priorities (bb);
7611 /* compute interblock info: probabilities, split-edges, dominators, etc. */
7612 if (current_nr_blocks > 1)
7616 prob = (float *) alloca ((current_nr_blocks) * sizeof (float));
7618 bbset_size = current_nr_blocks / HOST_BITS_PER_WIDE_INT + 1;
7619 dom = (bbset *) alloca (current_nr_blocks * sizeof (bbset));
7620 for (i = 0; i < current_nr_blocks; i++)
7622 dom[i] = (bbset) alloca (bbset_size * sizeof (HOST_WIDE_INT));
7623 bzero ((char *) dom[i], bbset_size * sizeof (HOST_WIDE_INT));
7628 edge_to_bit = (int *) alloca (nr_edges * sizeof (int));
7629 for (i = 1; i < nr_edges; i++)
7630 if (CONTAINING_RGN (FROM_BLOCK (i)) == rgn)
7631 EDGE_TO_BIT (i) = rgn_nr_edges++;
7632 rgn_edges = (int *) alloca (rgn_nr_edges * sizeof (int));
7635 for (i = 1; i < nr_edges; i++)
7636 if (CONTAINING_RGN (FROM_BLOCK (i)) == (rgn))
7637 rgn_edges[rgn_nr_edges++] = i;
7640 edgeset_size = rgn_nr_edges / HOST_BITS_PER_WIDE_INT + 1;
7641 pot_split = (edgeset *) alloca (current_nr_blocks * sizeof (edgeset));
7642 ancestor_edges = (edgeset *) alloca (current_nr_blocks * sizeof (edgeset));
7643 for (i = 0; i < current_nr_blocks; i++)
7646 (edgeset) alloca (edgeset_size * sizeof (HOST_WIDE_INT));
7647 bzero ((char *) pot_split[i],
7648 edgeset_size * sizeof (HOST_WIDE_INT));
7650 (edgeset) alloca (edgeset_size * sizeof (HOST_WIDE_INT));
7651 bzero ((char *) ancestor_edges[i],
7652 edgeset_size * sizeof (HOST_WIDE_INT));
7655 /* compute probabilities, dominators, split_edges */
7656 for (bb = 0; bb < current_nr_blocks; bb++)
7657 compute_dom_prob_ps (bb);
7660 /* now we can schedule all blocks */
7661 for (bb = 0; bb < current_nr_blocks; bb++)
7663 sched_rgn_n_insns += schedule_block (bb, rgn_n_insns);
7670 /* sanity check: verify that all region insns were scheduled */
7671 if (sched_rgn_n_insns != rgn_n_insns)
7674 /* update register life and usage information */
7675 if (reload_completed == 0)
7677 for (bb = current_nr_blocks - 1; bb >= 0; bb--)
7678 find_post_sched_live (bb);
7680 if (current_nr_blocks <= 1)
7681 /* Sanity check. There should be no REG_DEAD notes leftover at the end.
7682 In practice, this can occur as the result of bugs in flow, combine.c,
7683 and/or sched.c. The values of the REG_DEAD notes remaining are
7684 meaningless, because dead_notes is just used as a free list. */
7685 if (dead_notes != 0)
7689 /* restore line notes. */
7690 if (write_symbols != NO_DEBUG)
7692 for (bb = 0; bb < current_nr_blocks; bb++)
7693 restore_line_notes (bb);
7696 /* Done with this region */
7697 free_pending_lists ();
7699 FREE_REG_SET (reg_pending_sets);
7702 /* Subroutine of split_hard_reg_notes. Searches X for any reference to
7703 REGNO, returning the rtx of the reference found if any. Otherwise,
7707 regno_use_in (regno, x)
7715 if (GET_CODE (x) == REG && REGNO (x) == regno)
7718 fmt = GET_RTX_FORMAT (GET_CODE (x));
7719 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
7723 if ((tem = regno_use_in (regno, XEXP (x, i))))
7726 else if (fmt[i] == 'E')
7727 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7728 if ((tem = regno_use_in (regno, XVECEXP (x, i, j))))
7735 /* Subroutine of update_flow_info. Determines whether any new REG_NOTEs are
7736 needed for the hard register mentioned in the note. This can happen
7737 if the reference to the hard register in the original insn was split into
7738 several smaller hard register references in the split insns. */
7741 split_hard_reg_notes (note, first, last)
7742 rtx note, first, last;
7744 rtx reg, temp, link;
7745 int n_regs, i, new_reg;
7748 /* Assume that this is a REG_DEAD note. */
7749 if (REG_NOTE_KIND (note) != REG_DEAD)
7752 reg = XEXP (note, 0);
7754 n_regs = HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg));
7756 for (i = 0; i < n_regs; i++)
7758 new_reg = REGNO (reg) + i;
7760 /* Check for references to new_reg in the split insns. */
7761 for (insn = last;; insn = PREV_INSN (insn))
7763 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
7764 && (temp = regno_use_in (new_reg, PATTERN (insn))))
7766 /* Create a new reg dead note ere. */
7767 link = alloc_EXPR_LIST (REG_DEAD, temp, REG_NOTES (insn));
7768 REG_NOTES (insn) = link;
7770 /* If killed multiple registers here, then add in the excess. */
7771 i += HARD_REGNO_NREGS (REGNO (temp), GET_MODE (temp)) - 1;
7775 /* It isn't mentioned anywhere, so no new reg note is needed for
7783 /* Subroutine of update_flow_info. Determines whether a SET or CLOBBER in an
7784 insn created by splitting needs a REG_DEAD or REG_UNUSED note added. */
7787 new_insn_dead_notes (pat, insn, last, orig_insn)
7788 rtx pat, insn, last, orig_insn;
7792 /* PAT is either a CLOBBER or a SET here. */
7793 dest = XEXP (pat, 0);
7795 while (GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SUBREG
7796 || GET_CODE (dest) == STRICT_LOW_PART
7797 || GET_CODE (dest) == SIGN_EXTRACT)
7798 dest = XEXP (dest, 0);
7800 if (GET_CODE (dest) == REG)
7802 /* If the original insn already used this register, we may not add new
7803 notes for it. One example for a split that needs this test is
7804 when a multi-word memory access with register-indirect addressing
7805 is split into multiple memory accesses with auto-increment and
7806 one adjusting add instruction for the address register. */
7807 if (reg_referenced_p (dest, PATTERN (orig_insn)))
7809 for (tem = last; tem != insn; tem = PREV_INSN (tem))
7811 if (GET_RTX_CLASS (GET_CODE (tem)) == 'i'
7812 && reg_overlap_mentioned_p (dest, PATTERN (tem))
7813 && (set = single_set (tem)))
7815 rtx tem_dest = SET_DEST (set);
7817 while (GET_CODE (tem_dest) == ZERO_EXTRACT
7818 || GET_CODE (tem_dest) == SUBREG
7819 || GET_CODE (tem_dest) == STRICT_LOW_PART
7820 || GET_CODE (tem_dest) == SIGN_EXTRACT)
7821 tem_dest = XEXP (tem_dest, 0);
7823 if (!rtx_equal_p (tem_dest, dest))
7825 /* Use the same scheme as combine.c, don't put both REG_DEAD
7826 and REG_UNUSED notes on the same insn. */
7827 if (!find_regno_note (tem, REG_UNUSED, REGNO (dest))
7828 && !find_regno_note (tem, REG_DEAD, REGNO (dest)))
7830 rtx note = alloc_EXPR_LIST (REG_DEAD, dest,
7832 REG_NOTES (tem) = note;
7834 /* The reg only dies in one insn, the last one that uses
7838 else if (reg_overlap_mentioned_p (dest, SET_SRC (set)))
7839 /* We found an instruction that both uses the register,
7840 and sets it, so no new REG_NOTE is needed for this set. */
7844 /* If this is a set, it must die somewhere, unless it is the dest of
7845 the original insn, and hence is live after the original insn. Abort
7846 if it isn't supposed to be live after the original insn.
7848 If this is a clobber, then just add a REG_UNUSED note. */
7851 int live_after_orig_insn = 0;
7852 rtx pattern = PATTERN (orig_insn);
7855 if (GET_CODE (pat) == CLOBBER)
7857 rtx note = alloc_EXPR_LIST (REG_UNUSED, dest, REG_NOTES (insn));
7858 REG_NOTES (insn) = note;
7862 /* The original insn could have multiple sets, so search the
7863 insn for all sets. */
7864 if (GET_CODE (pattern) == SET)
7866 if (reg_overlap_mentioned_p (dest, SET_DEST (pattern)))
7867 live_after_orig_insn = 1;
7869 else if (GET_CODE (pattern) == PARALLEL)
7871 for (i = 0; i < XVECLEN (pattern, 0); i++)
7872 if (GET_CODE (XVECEXP (pattern, 0, i)) == SET
7873 && reg_overlap_mentioned_p (dest,
7874 SET_DEST (XVECEXP (pattern,
7876 live_after_orig_insn = 1;
7879 if (!live_after_orig_insn)
7885 /* Subroutine of update_flow_info. Update the value of reg_n_sets for all
7886 registers modified by X. INC is -1 if the containing insn is being deleted,
7887 and is 1 if the containing insn is a newly generated insn. */
7890 update_n_sets (x, inc)
7894 rtx dest = SET_DEST (x);
7896 while (GET_CODE (dest) == STRICT_LOW_PART || GET_CODE (dest) == SUBREG
7897 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SIGN_EXTRACT)
7898 dest = SUBREG_REG (dest);
7900 if (GET_CODE (dest) == REG)
7902 int regno = REGNO (dest);
7904 if (regno < FIRST_PSEUDO_REGISTER)
7907 int endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (dest));
7909 for (i = regno; i < endregno; i++)
7910 REG_N_SETS (i) += inc;
7913 REG_N_SETS (regno) += inc;
7917 /* Updates all flow-analysis related quantities (including REG_NOTES) for
7918 the insns from FIRST to LAST inclusive that were created by splitting
7919 ORIG_INSN. NOTES are the original REG_NOTES. */
7922 update_flow_info (notes, first, last, orig_insn)
7929 rtx orig_dest, temp;
7932 /* Get and save the destination set by the original insn. */
7934 orig_dest = single_set (orig_insn);
7936 orig_dest = SET_DEST (orig_dest);
7938 /* Move REG_NOTES from the original insn to where they now belong. */
7940 for (note = notes; note; note = next)
7942 next = XEXP (note, 1);
7943 switch (REG_NOTE_KIND (note))
7947 /* Move these notes from the original insn to the last new insn where
7948 the register is now set. */
7950 for (insn = last;; insn = PREV_INSN (insn))
7952 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
7953 && reg_mentioned_p (XEXP (note, 0), PATTERN (insn)))
7955 /* If this note refers to a multiple word hard register, it
7956 may have been split into several smaller hard register
7957 references, so handle it specially. */
7958 temp = XEXP (note, 0);
7959 if (REG_NOTE_KIND (note) == REG_DEAD
7960 && GET_CODE (temp) == REG
7961 && REGNO (temp) < FIRST_PSEUDO_REGISTER
7962 && HARD_REGNO_NREGS (REGNO (temp), GET_MODE (temp)) > 1)
7963 split_hard_reg_notes (note, first, last);
7966 XEXP (note, 1) = REG_NOTES (insn);
7967 REG_NOTES (insn) = note;
7970 /* Sometimes need to convert REG_UNUSED notes to REG_DEAD
7972 /* ??? This won't handle multiple word registers correctly,
7973 but should be good enough for now. */
7974 if (REG_NOTE_KIND (note) == REG_UNUSED
7975 && GET_CODE (XEXP (note, 0)) != SCRATCH
7976 && !dead_or_set_p (insn, XEXP (note, 0)))
7977 PUT_REG_NOTE_KIND (note, REG_DEAD);
7979 /* The reg only dies in one insn, the last one that uses
7983 /* It must die somewhere, fail it we couldn't find where it died.
7985 If this is a REG_UNUSED note, then it must be a temporary
7986 register that was not needed by this instantiation of the
7987 pattern, so we can safely ignore it. */
7990 if (REG_NOTE_KIND (note) != REG_UNUSED)
7999 /* If the insn that set the register to 0 was deleted, this
8000 note cannot be relied on any longer. The destination might
8001 even have been moved to memory.
8002 This was observed for SH4 with execute/920501-6.c compilation,
8003 -O2 -fomit-frame-pointer -finline-functions . */
8004 if (GET_CODE (XEXP (note, 0)) == NOTE
8005 || INSN_DELETED_P (XEXP (note, 0)))
8007 /* This note applies to the dest of the original insn. Find the
8008 first new insn that now has the same dest, and move the note
8014 for (insn = first;; insn = NEXT_INSN (insn))
8016 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
8017 && (temp = single_set (insn))
8018 && rtx_equal_p (SET_DEST (temp), orig_dest))
8020 XEXP (note, 1) = REG_NOTES (insn);
8021 REG_NOTES (insn) = note;
8022 /* The reg is only zero before one insn, the first that
8026 /* If this note refers to a multiple word hard
8027 register, it may have been split into several smaller
8028 hard register references. We could split the notes,
8029 but simply dropping them is good enough. */
8030 if (GET_CODE (orig_dest) == REG
8031 && REGNO (orig_dest) < FIRST_PSEUDO_REGISTER
8032 && HARD_REGNO_NREGS (REGNO (orig_dest),
8033 GET_MODE (orig_dest)) > 1)
8035 /* It must be set somewhere, fail if we couldn't find where it
8044 /* A REG_EQUIV or REG_EQUAL note on an insn with more than one
8045 set is meaningless. Just drop the note. */
8049 case REG_NO_CONFLICT:
8050 /* These notes apply to the dest of the original insn. Find the last
8051 new insn that now has the same dest, and move the note there. */
8056 for (insn = last;; insn = PREV_INSN (insn))
8058 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
8059 && (temp = single_set (insn))
8060 && rtx_equal_p (SET_DEST (temp), orig_dest))
8062 XEXP (note, 1) = REG_NOTES (insn);
8063 REG_NOTES (insn) = note;
8064 /* Only put this note on one of the new insns. */
8068 /* The original dest must still be set someplace. Abort if we
8069 couldn't find it. */
8072 /* However, if this note refers to a multiple word hard
8073 register, it may have been split into several smaller
8074 hard register references. We could split the notes,
8075 but simply dropping them is good enough. */
8076 if (GET_CODE (orig_dest) == REG
8077 && REGNO (orig_dest) < FIRST_PSEUDO_REGISTER
8078 && HARD_REGNO_NREGS (REGNO (orig_dest),
8079 GET_MODE (orig_dest)) > 1)
8081 /* Likewise for multi-word memory references. */
8082 if (GET_CODE (orig_dest) == MEM
8083 && SIZE_FOR_MODE (orig_dest) > UNITS_PER_WORD)
8091 /* Move a REG_LIBCALL note to the first insn created, and update
8092 the corresponding REG_RETVAL note. */
8093 XEXP (note, 1) = REG_NOTES (first);
8094 REG_NOTES (first) = note;
8096 insn = XEXP (note, 0);
8097 note = find_reg_note (insn, REG_RETVAL, NULL_RTX);
8099 XEXP (note, 0) = first;
8102 case REG_EXEC_COUNT:
8103 /* Move a REG_EXEC_COUNT note to the first insn created. */
8104 XEXP (note, 1) = REG_NOTES (first);
8105 REG_NOTES (first) = note;
8109 /* Move a REG_RETVAL note to the last insn created, and update
8110 the corresponding REG_LIBCALL note. */
8111 XEXP (note, 1) = REG_NOTES (last);
8112 REG_NOTES (last) = note;
8114 insn = XEXP (note, 0);
8115 note = find_reg_note (insn, REG_LIBCALL, NULL_RTX);
8117 XEXP (note, 0) = last;
8122 /* This should be moved to whichever instruction is a JUMP_INSN. */
8124 for (insn = last;; insn = PREV_INSN (insn))
8126 if (GET_CODE (insn) == JUMP_INSN)
8128 XEXP (note, 1) = REG_NOTES (insn);
8129 REG_NOTES (insn) = note;
8130 /* Only put this note on one of the new insns. */
8133 /* Fail if we couldn't find a JUMP_INSN. */
8140 /* reload sometimes leaves obsolete REG_INC notes around. */
8141 if (reload_completed)
8143 /* This should be moved to whichever instruction now has the
8144 increment operation. */
8148 /* Should be moved to the new insn(s) which use the label. */
8149 for (insn = first; insn != NEXT_INSN (last); insn = NEXT_INSN (insn))
8150 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
8151 && reg_mentioned_p (XEXP (note, 0), PATTERN (insn)))
8153 REG_NOTES (insn) = alloc_EXPR_LIST (REG_LABEL,
8161 /* These two notes will never appear until after reorg, so we don't
8162 have to handle them here. */
8168 /* Each new insn created, except the last, has a new set. If the destination
8169 is a register, then this reg is now live across several insns, whereas
8170 previously the dest reg was born and died within the same insn. To
8171 reflect this, we now need a REG_DEAD note on the insn where this
8174 Similarly, the new insns may have clobbers that need REG_UNUSED notes. */
8176 for (insn = first; insn != last; insn = NEXT_INSN (insn))
8181 pat = PATTERN (insn);
8182 if (GET_CODE (pat) == SET || GET_CODE (pat) == CLOBBER)
8183 new_insn_dead_notes (pat, insn, last, orig_insn);
8184 else if (GET_CODE (pat) == PARALLEL)
8186 for (i = 0; i < XVECLEN (pat, 0); i++)
8187 if (GET_CODE (XVECEXP (pat, 0, i)) == SET
8188 || GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER)
8189 new_insn_dead_notes (XVECEXP (pat, 0, i), insn, last, orig_insn);
8193 /* If any insn, except the last, uses the register set by the last insn,
8194 then we need a new REG_DEAD note on that insn. In this case, there
8195 would not have been a REG_DEAD note for this register in the original
8196 insn because it was used and set within one insn. */
8198 set = single_set (last);
8201 rtx dest = SET_DEST (set);
8203 while (GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SUBREG
8204 || GET_CODE (dest) == STRICT_LOW_PART
8205 || GET_CODE (dest) == SIGN_EXTRACT)
8206 dest = XEXP (dest, 0);
8208 if (GET_CODE (dest) == REG
8209 /* Global registers are always live, so the code below does not
8211 && (REGNO (dest) >= FIRST_PSEUDO_REGISTER
8212 || ! global_regs[REGNO (dest)]))
8214 rtx stop_insn = PREV_INSN (first);
8216 /* If the last insn uses the register that it is setting, then
8217 we don't want to put a REG_DEAD note there. Search backwards
8218 to find the first insn that sets but does not use DEST. */
8221 if (reg_overlap_mentioned_p (dest, SET_SRC (set)))
8223 for (insn = PREV_INSN (insn); insn != first;
8224 insn = PREV_INSN (insn))
8226 if ((set = single_set (insn))
8227 && reg_mentioned_p (dest, SET_DEST (set))
8228 && ! reg_overlap_mentioned_p (dest, SET_SRC (set)))
8233 /* Now find the first insn that uses but does not set DEST. */
8235 for (insn = PREV_INSN (insn); insn != stop_insn;
8236 insn = PREV_INSN (insn))
8238 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
8239 && reg_mentioned_p (dest, PATTERN (insn))
8240 && (set = single_set (insn)))
8242 rtx insn_dest = SET_DEST (set);
8244 while (GET_CODE (insn_dest) == ZERO_EXTRACT
8245 || GET_CODE (insn_dest) == SUBREG
8246 || GET_CODE (insn_dest) == STRICT_LOW_PART
8247 || GET_CODE (insn_dest) == SIGN_EXTRACT)
8248 insn_dest = XEXP (insn_dest, 0);
8250 if (insn_dest != dest)
8252 note = alloc_EXPR_LIST (REG_DEAD, dest, REG_NOTES (insn));
8253 REG_NOTES (insn) = note;
8254 /* The reg only dies in one insn, the last one
8263 /* If the original dest is modifying a multiple register target, and the
8264 original instruction was split such that the original dest is now set
8265 by two or more SUBREG sets, then the split insns no longer kill the
8266 destination of the original insn.
8268 In this case, if there exists an instruction in the same basic block,
8269 before the split insn, which uses the original dest, and this use is
8270 killed by the original insn, then we must remove the REG_DEAD note on
8271 this insn, because it is now superfluous.
8273 This does not apply when a hard register gets split, because the code
8274 knows how to handle overlapping hard registers properly. */
8275 if (orig_dest && GET_CODE (orig_dest) == REG)
8277 int found_orig_dest = 0;
8278 int found_split_dest = 0;
8280 for (insn = first;; insn = NEXT_INSN (insn))
8285 /* I'm not sure if this can happen, but let's be safe. */
8286 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
8289 pat = PATTERN (insn);
8290 i = GET_CODE (pat) == PARALLEL ? XVECLEN (pat, 0) : 0;
8295 if (GET_CODE (set) == SET)
8297 if (GET_CODE (SET_DEST (set)) == REG
8298 && REGNO (SET_DEST (set)) == REGNO (orig_dest))
8300 found_orig_dest = 1;
8303 else if (GET_CODE (SET_DEST (set)) == SUBREG
8304 && SUBREG_REG (SET_DEST (set)) == orig_dest)
8306 found_split_dest = 1;
8312 set = XVECEXP (pat, 0, i);
8319 if (found_split_dest)
8321 /* Search backwards from FIRST, looking for the first insn that uses
8322 the original dest. Stop if we pass a CODE_LABEL or a JUMP_INSN.
8323 If we find an insn, and it has a REG_DEAD note, then delete the
8326 for (insn = first; insn; insn = PREV_INSN (insn))
8328 if (GET_CODE (insn) == CODE_LABEL
8329 || GET_CODE (insn) == JUMP_INSN)
8331 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
8332 && reg_mentioned_p (orig_dest, insn))
8334 note = find_regno_note (insn, REG_DEAD, REGNO (orig_dest));
8336 remove_note (insn, note);
8340 else if (!found_orig_dest)
8342 /* This should never happen. */
8347 /* Update reg_n_sets. This is necessary to prevent local alloc from
8348 converting REG_EQUAL notes to REG_EQUIV when splitting has modified
8349 a reg from set once to set multiple times. */
8352 rtx x = PATTERN (orig_insn);
8353 RTX_CODE code = GET_CODE (x);
8355 if (code == SET || code == CLOBBER)
8356 update_n_sets (x, -1);
8357 else if (code == PARALLEL)
8360 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
8362 code = GET_CODE (XVECEXP (x, 0, i));
8363 if (code == SET || code == CLOBBER)
8364 update_n_sets (XVECEXP (x, 0, i), -1);
8368 for (insn = first;; insn = NEXT_INSN (insn))
8371 code = GET_CODE (x);
8373 if (code == SET || code == CLOBBER)
8374 update_n_sets (x, 1);
8375 else if (code == PARALLEL)
8378 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
8380 code = GET_CODE (XVECEXP (x, 0, i));
8381 if (code == SET || code == CLOBBER)
8382 update_n_sets (XVECEXP (x, 0, i), 1);
8392 /* Do the splitting of insns in the block b. */
8395 split_block_insns (b)
8400 for (insn = basic_block_head[b];; insn = next)
8402 rtx set, last, first, notes;
8404 /* Can't use `next_real_insn' because that
8405 might go across CODE_LABELS and short-out basic blocks. */
8406 next = NEXT_INSN (insn);
8407 if (GET_CODE (insn) != INSN)
8409 if (insn == basic_block_end[b])
8415 /* Don't split no-op move insns. These should silently disappear
8416 later in final. Splitting such insns would break the code
8417 that handles REG_NO_CONFLICT blocks. */
8418 set = single_set (insn);
8419 if (set && rtx_equal_p (SET_SRC (set), SET_DEST (set)))
8421 if (insn == basic_block_end[b])
8424 /* Nops get in the way while scheduling, so delete them now if
8425 register allocation has already been done. It is too risky
8426 to try to do this before register allocation, and there are
8427 unlikely to be very many nops then anyways. */
8428 if (reload_completed)
8430 PUT_CODE (insn, NOTE);
8431 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8432 NOTE_SOURCE_FILE (insn) = 0;
8438 /* Split insns here to get max fine-grain parallelism. */
8439 first = PREV_INSN (insn);
8440 notes = REG_NOTES (insn);
8441 last = try_split (PATTERN (insn), insn, 1);
8444 /* try_split returns the NOTE that INSN became. */
8445 first = NEXT_INSN (first);
8446 update_flow_info (notes, first, last, insn);
8448 PUT_CODE (insn, NOTE);
8449 NOTE_SOURCE_FILE (insn) = 0;
8450 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8451 if (insn == basic_block_head[b])
8452 basic_block_head[b] = first;
8453 if (insn == basic_block_end[b])
8455 basic_block_end[b] = last;
8460 if (insn == basic_block_end[b])
8465 /* The one entry point in this file. DUMP_FILE is the dump file for
8469 schedule_insns (dump_file)
8480 /* disable speculative loads in their presence if cc0 defined */
8482 flag_schedule_speculative_load = 0;
8485 /* Taking care of this degenerate case makes the rest of
8486 this code simpler. */
8487 if (n_basic_blocks == 0)
8490 /* set dump and sched_verbose for the desired debugging output. If no
8491 dump-file was specified, but -fsched-verbose-N (any N), print to stderr.
8492 For -fsched-verbose-N, N>=10, print everything to stderr. */
8493 sched_verbose = sched_verbose_param;
8494 if (sched_verbose_param == 0 && dump_file)
8496 dump = ((sched_verbose_param >= 10 || !dump_file) ? stderr : dump_file);
8501 /* Initialize the unused_*_lists. We can't use the ones left over from
8502 the previous function, because gcc has freed that memory. We can use
8503 the ones left over from the first sched pass in the second pass however,
8504 so only clear them on the first sched pass. The first pass is before
8505 reload if flag_schedule_insns is set, otherwise it is afterwards. */
8507 if (reload_completed == 0 || !flag_schedule_insns)
8509 unused_insn_list = 0;
8510 unused_expr_list = 0;
8513 /* initialize issue_rate */
8514 issue_rate = ISSUE_RATE;
8516 /* do the splitting first for all blocks */
8517 for (b = 0; b < n_basic_blocks; b++)
8518 split_block_insns (b);
8520 max_uid = (get_max_uid () + 1);
8522 cant_move = (char *) xmalloc (max_uid * sizeof (char));
8523 bzero ((char *) cant_move, max_uid * sizeof (char));
8525 fed_by_spec_load = (char *) xmalloc (max_uid * sizeof (char));
8526 bzero ((char *) fed_by_spec_load, max_uid * sizeof (char));
8528 is_load_insn = (char *) xmalloc (max_uid * sizeof (char));
8529 bzero ((char *) is_load_insn, max_uid * sizeof (char));
8531 insn_orig_block = (int *) xmalloc (max_uid * sizeof (int));
8532 insn_luid = (int *) xmalloc (max_uid * sizeof (int));
8535 for (b = 0; b < n_basic_blocks; b++)
8536 for (insn = basic_block_head[b];; insn = NEXT_INSN (insn))
8538 INSN_BLOCK (insn) = b;
8539 INSN_LUID (insn) = luid++;
8541 if (insn == basic_block_end[b])
8545 /* after reload, remove inter-blocks dependences computed before reload. */
8546 if (reload_completed)
8551 for (b = 0; b < n_basic_blocks; b++)
8552 for (insn = basic_block_head[b];; insn = NEXT_INSN (insn))
8556 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
8559 link = LOG_LINKS (insn);
8562 rtx x = XEXP (link, 0);
8564 if (INSN_BLOCK (x) != b)
8566 remove_dependence (insn, x);
8567 link = prev ? XEXP (prev, 1) : LOG_LINKS (insn);
8570 prev = link, link = XEXP (prev, 1);
8574 if (insn == basic_block_end[b])
8580 rgn_table = (region *) alloca ((n_basic_blocks) * sizeof (region));
8581 rgn_bb_table = (int *) alloca ((n_basic_blocks) * sizeof (int));
8582 block_to_bb = (int *) alloca ((n_basic_blocks) * sizeof (int));
8583 containing_rgn = (int *) alloca ((n_basic_blocks) * sizeof (int));
8585 /* compute regions for scheduling */
8586 if (reload_completed
8587 || n_basic_blocks == 1
8588 || !flag_schedule_interblock)
8590 find_single_block_region ();
8594 /* verify that a 'good' control flow graph can be built */
8595 if (is_cfg_nonregular ())
8597 find_single_block_region ();
8601 int_list_ptr *s_preds, *s_succs;
8602 int *num_preds, *num_succs;
8603 sbitmap *dom, *pdom;
8605 s_preds = (int_list_ptr *) alloca (n_basic_blocks
8606 * sizeof (int_list_ptr));
8607 s_succs = (int_list_ptr *) alloca (n_basic_blocks
8608 * sizeof (int_list_ptr));
8609 num_preds = (int *) alloca (n_basic_blocks * sizeof (int));
8610 num_succs = (int *) alloca (n_basic_blocks * sizeof (int));
8611 dom = sbitmap_vector_alloc (n_basic_blocks, n_basic_blocks);
8612 pdom = sbitmap_vector_alloc (n_basic_blocks, n_basic_blocks);
8614 /* The scheduler runs after flow; therefore, we can't blindly call
8615 back into find_basic_blocks since doing so could invalidate the
8616 info in basic_block_live_at_start.
8618 Consider a block consisting entirely of dead stores; after life
8619 analysis it would be a block of NOTE_INSN_DELETED notes. If
8620 we call find_basic_blocks again, then the block would be removed
8621 entirely and invalidate our the register live information.
8623 We could (should?) recompute register live information. Doing
8624 so may even be beneficial. */
8626 compute_preds_succs (s_preds, s_succs, num_preds, num_succs);
8628 /* Compute the dominators and post dominators. We don't currently use
8629 post dominators, but we should for speculative motion analysis. */
8630 compute_dominators (dom, pdom, s_preds, s_succs);
8632 /* build_control_flow will return nonzero if it detects unreachable
8633 blocks or any other irregularity with the cfg which prevents
8634 cross block scheduling. */
8635 if (build_control_flow (s_preds, s_succs, num_preds, num_succs) != 0)
8636 find_single_block_region ();
8638 find_rgns (s_preds, s_succs, num_preds, num_succs, dom);
8640 if (sched_verbose >= 3)
8643 /* For now. This will move as more and more of haifa is converted
8644 to using the cfg code in flow.c */
8651 /* Allocate data for this pass. See comments, above,
8652 for what these vectors do.
8654 We use xmalloc instead of alloca, because max_uid can be very large
8655 when there is a lot of function inlining. If we used alloca, we could
8656 exceed stack limits on some hosts for some inputs. */
8657 insn_priority = (int *) xmalloc (max_uid * sizeof (int));
8658 insn_reg_weight = (int *) xmalloc (max_uid * sizeof (int));
8659 insn_tick = (int *) xmalloc (max_uid * sizeof (int));
8660 insn_costs = (short *) xmalloc (max_uid * sizeof (short));
8661 insn_units = (short *) xmalloc (max_uid * sizeof (short));
8662 insn_blockage = (unsigned int *) xmalloc (max_uid * sizeof (unsigned int));
8663 insn_ref_count = (int *) xmalloc (max_uid * sizeof (int));
8665 /* Allocate for forward dependencies */
8666 insn_dep_count = (int *) xmalloc (max_uid * sizeof (int));
8667 insn_depend = (rtx *) xmalloc (max_uid * sizeof (rtx));
8669 if (reload_completed == 0)
8673 sched_reg_n_calls_crossed = (int *) alloca (max_regno * sizeof (int));
8674 sched_reg_live_length = (int *) alloca (max_regno * sizeof (int));
8675 sched_reg_basic_block = (int *) alloca (max_regno * sizeof (int));
8676 bb_live_regs = ALLOCA_REG_SET ();
8677 bzero ((char *) sched_reg_n_calls_crossed, max_regno * sizeof (int));
8678 bzero ((char *) sched_reg_live_length, max_regno * sizeof (int));
8680 for (i = 0; i < max_regno; i++)
8681 sched_reg_basic_block[i] = REG_BLOCK_UNKNOWN;
8685 sched_reg_n_calls_crossed = 0;
8686 sched_reg_live_length = 0;
8689 init_alias_analysis ();
8691 if (write_symbols != NO_DEBUG)
8695 line_note = (rtx *) xmalloc (max_uid * sizeof (rtx));
8696 bzero ((char *) line_note, max_uid * sizeof (rtx));
8697 line_note_head = (rtx *) alloca (n_basic_blocks * sizeof (rtx));
8698 bzero ((char *) line_note_head, n_basic_blocks * sizeof (rtx));
8700 /* Save-line-note-head:
8701 Determine the line-number at the start of each basic block.
8702 This must be computed and saved now, because after a basic block's
8703 predecessor has been scheduled, it is impossible to accurately
8704 determine the correct line number for the first insn of the block. */
8706 for (b = 0; b < n_basic_blocks; b++)
8707 for (line = basic_block_head[b]; line; line = PREV_INSN (line))
8708 if (GET_CODE (line) == NOTE && NOTE_LINE_NUMBER (line) > 0)
8710 line_note_head[b] = line;
8715 bzero ((char *) insn_priority, max_uid * sizeof (int));
8716 bzero ((char *) insn_reg_weight, max_uid * sizeof (int));
8717 bzero ((char *) insn_tick, max_uid * sizeof (int));
8718 bzero ((char *) insn_costs, max_uid * sizeof (short));
8719 bzero ((char *) insn_units, max_uid * sizeof (short));
8720 bzero ((char *) insn_blockage, max_uid * sizeof (unsigned int));
8721 bzero ((char *) insn_ref_count, max_uid * sizeof (int));
8723 /* Initialize for forward dependencies */
8724 bzero ((char *) insn_depend, max_uid * sizeof (rtx));
8725 bzero ((char *) insn_dep_count, max_uid * sizeof (int));
8727 /* Find units used in this fuction, for visualization */
8729 init_target_units ();
8731 /* ??? Add a NOTE after the last insn of the last basic block. It is not
8732 known why this is done. */
8734 insn = basic_block_end[n_basic_blocks - 1];
8735 if (NEXT_INSN (insn) == 0
8736 || (GET_CODE (insn) != NOTE
8737 && GET_CODE (insn) != CODE_LABEL
8738 /* Don't emit a NOTE if it would end up between an unconditional
8739 jump and a BARRIER. */
8740 && !(GET_CODE (insn) == JUMP_INSN
8741 && GET_CODE (NEXT_INSN (insn)) == BARRIER)))
8742 emit_note_after (NOTE_INSN_DELETED, basic_block_end[n_basic_blocks - 1]);
8744 /* Schedule every region in the subroutine */
8745 for (rgn = 0; rgn < nr_regions; rgn++)
8747 schedule_region (rgn);
8754 /* Reposition the prologue and epilogue notes in case we moved the
8755 prologue/epilogue insns. */
8756 if (reload_completed)
8757 reposition_prologue_and_epilogue_notes (get_insns ());
8759 /* delete redundant line notes. */
8760 if (write_symbols != NO_DEBUG)
8761 rm_redundant_line_notes ();
8763 /* Update information about uses of registers in the subroutine. */
8764 if (reload_completed == 0)
8765 update_reg_usage ();
8769 if (reload_completed == 0 && flag_schedule_interblock)
8771 fprintf (dump, "\n;; Procedure interblock/speculative motions == %d/%d \n",
8779 fprintf (dump, "\n\n");
8783 free (fed_by_spec_load);
8784 free (is_load_insn);
8785 free (insn_orig_block);
8788 free (insn_priority);
8789 free (insn_reg_weight);
8793 free (insn_blockage);
8794 free (insn_ref_count);
8796 free (insn_dep_count);
8799 if (write_symbols != NO_DEBUG)
8803 FREE_REG_SET (bb_live_regs);
8822 #endif /* INSN_SCHEDULING */