1 /* Instruction scheduling pass.
2 Copyright (C) 1992, 93-98, 1999 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com) Enhanced by,
4 and currently maintained by, Jim Wilson (wilson@cygnus.com)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful, but
14 WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to the Free
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 /* Instruction scheduling pass.
26 This pass implements list scheduling within basic blocks. It is
27 run twice: (1) after flow analysis, but before register allocation,
28 and (2) after register allocation.
30 The first run performs interblock scheduling, moving insns between
31 different blocks in the same "region", and the second runs only
32 basic block scheduling.
34 Interblock motions performed are useful motions and speculative
35 motions, including speculative loads. Motions requiring code
36 duplication are not supported. The identification of motion type
37 and the check for validity of speculative motions requires
38 construction and analysis of the function's control flow graph.
39 The scheduler works as follows:
41 We compute insn priorities based on data dependencies. Flow
42 analysis only creates a fraction of the data-dependencies we must
43 observe: namely, only those dependencies which the combiner can be
44 expected to use. For this pass, we must therefore create the
45 remaining dependencies we need to observe: register dependencies,
46 memory dependencies, dependencies to keep function calls in order,
47 and the dependence between a conditional branch and the setting of
48 condition codes are all dealt with here.
50 The scheduler first traverses the data flow graph, starting with
51 the last instruction, and proceeding to the first, assigning values
52 to insn_priority as it goes. This sorts the instructions
53 topologically by data dependence.
55 Once priorities have been established, we order the insns using
56 list scheduling. This works as follows: starting with a list of
57 all the ready insns, and sorted according to priority number, we
58 schedule the insn from the end of the list by placing its
59 predecessors in the list according to their priority order. We
60 consider this insn scheduled by setting the pointer to the "end" of
61 the list to point to the previous insn. When an insn has no
62 predecessors, we either queue it until sufficient time has elapsed
63 or add it to the ready list. As the instructions are scheduled or
64 when stalls are introduced, the queue advances and dumps insns into
65 the ready list. When all insns down to the lowest priority have
66 been scheduled, the critical path of the basic block has been made
67 as short as possible. The remaining insns are then scheduled in
70 Function unit conflicts are resolved during forward list scheduling
71 by tracking the time when each insn is committed to the schedule
72 and from that, the time the function units it uses must be free.
73 As insns on the ready list are considered for scheduling, those
74 that would result in a blockage of the already committed insns are
75 queued until no blockage will result.
77 The following list shows the order in which we want to break ties
78 among insns in the ready list:
80 1. choose insn with the longest path to end of bb, ties
82 2. choose insn with least contribution to register pressure,
84 3. prefer in-block upon interblock motion, ties broken by
85 4. prefer useful upon speculative motion, ties broken by
86 5. choose insn with largest control flow probability, ties
88 6. choose insn with the least dependences upon the previously
89 scheduled insn, or finally
90 7 choose the insn which has the most insns dependent on it.
91 8. choose insn with lowest UID.
93 Memory references complicate matters. Only if we can be certain
94 that memory references are not part of the data dependency graph
95 (via true, anti, or output dependence), can we move operations past
96 memory references. To first approximation, reads can be done
97 independently, while writes introduce dependencies. Better
98 approximations will yield fewer dependencies.
100 Before reload, an extended analysis of interblock data dependences
101 is required for interblock scheduling. This is performed in
102 compute_block_backward_dependences ().
104 Dependencies set up by memory references are treated in exactly the
105 same way as other dependencies, by using LOG_LINKS backward
106 dependences. LOG_LINKS are translated into INSN_DEPEND forward
107 dependences for the purpose of forward list scheduling.
109 Having optimized the critical path, we may have also unduly
110 extended the lifetimes of some registers. If an operation requires
111 that constants be loaded into registers, it is certainly desirable
112 to load those constants as early as necessary, but no earlier.
113 I.e., it will not do to load up a bunch of registers at the
114 beginning of a basic block only to use them at the end, if they
115 could be loaded later, since this may result in excessive register
118 Note that since branches are never in basic blocks, but only end
119 basic blocks, this pass will not move branches. But that is ok,
120 since we can use GNU's delayed branch scheduling pass to take care
123 Also note that no further optimizations based on algebraic
124 identities are performed, so this pass would be a good one to
125 perform instruction splitting, such as breaking up a multiply
126 instruction into shifts and adds where that is profitable.
128 Given the memory aliasing analysis that this pass should perform,
129 it should be possible to remove redundant stores to memory, and to
130 load values from registers instead of hitting memory.
132 Before reload, speculative insns are moved only if a 'proof' exists
133 that no exception will be caused by this, and if no live registers
134 exist that inhibit the motion (live registers constraints are not
135 represented by data dependence edges).
137 This pass must update information that subsequent passes expect to
138 be correct. Namely: reg_n_refs, reg_n_sets, reg_n_deaths,
139 reg_n_calls_crossed, and reg_live_length. Also, BLOCK_HEAD,
142 The information in the line number notes is carefully retained by
143 this pass. Notes that refer to the starting and ending of
144 exception regions are also carefully retained by this pass. All
145 other NOTE insns are grouped in their same relative order at the
146 beginning of basic blocks and regions that have been scheduled.
148 The main entry point for this pass is schedule_insns(), called for
149 each function. The work of the scheduler is organized in three
150 levels: (1) function level: insns are subject to splitting,
151 control-flow-graph is constructed, regions are computed (after
152 reload, each region is of one block), (2) region level: control
153 flow graph attributes required for interblock scheduling are
154 computed (dominators, reachability, etc.), data dependences and
155 priorities are computed, and (3) block level: insns in the block
156 are actually scheduled. */
163 #include "basic-block.h"
165 #include "function.h"
166 #include "hard-reg-set.h"
168 #include "insn-config.h"
169 #include "insn-attr.h"
174 extern char *reg_known_equiv_p;
175 extern rtx *reg_known_value;
177 #ifdef INSN_SCHEDULING
179 /* target_units bitmask has 1 for each unit in the cpu. It should be
180 possible to compute this variable from the machine description.
181 But currently it is computed by examining the insn list. Since
182 this is only needed for visualization, it seems an acceptable
183 solution. (For understanding the mapping of bits to units, see
184 definition of function_units[] in "insn-attrtab.c".) */
186 static int target_units = 0;
188 /* issue_rate is the number of insns that can be scheduled in the same
189 machine cycle. It can be defined in the config/mach/mach.h file,
190 otherwise we set it to 1. */
192 static int issue_rate;
198 /* sched-verbose controls the amount of debugging output the
199 scheduler prints. It is controlled by -fsched-verbose-N:
200 N>0 and no -DSR : the output is directed to stderr.
201 N>=10 will direct the printouts to stderr (regardless of -dSR).
203 N=2: bb's probabilities, detailed ready list info, unit/insn info.
204 N=3: rtl at abort point, control-flow, regions info.
205 N=5: dependences info. */
207 #define MAX_RGN_BLOCKS 10
208 #define MAX_RGN_INSNS 100
210 static int sched_verbose_param = 0;
211 static int sched_verbose = 0;
213 /* nr_inter/spec counts interblock/speculative motion for the function. */
214 static int nr_inter, nr_spec;
217 /* Debugging file. All printouts are sent to dump, which is always set,
218 either to stderr, or to the dump listing file (-dRS). */
219 static FILE *dump = 0;
221 /* fix_sched_param() is called from toplev.c upon detection
222 of the -fsched-***-N options. */
225 fix_sched_param (param, val)
226 const char *param, *val;
228 if (!strcmp (param, "verbose"))
229 sched_verbose_param = atoi (val);
231 warning ("fix_sched_param: unknown param: %s", param);
234 /* Describe state of dependencies used during sched_analyze phase. */
237 /* The *_insns and *_mems are paired lists. Each pending memory operation
238 will have a pointer to the MEM rtx on one list and a pointer to the
239 containing insn on the other list in the same place in the list. */
241 /* We can't use add_dependence like the old code did, because a single insn
242 may have multiple memory accesses, and hence needs to be on the list
243 once for each memory access. Add_dependence won't let you add an insn
244 to a list more than once. */
246 /* An INSN_LIST containing all insns with pending read operations. */
247 rtx pending_read_insns;
249 /* An EXPR_LIST containing all MEM rtx's which are pending reads. */
250 rtx pending_read_mems;
252 /* An INSN_LIST containing all insns with pending write operations. */
253 rtx pending_write_insns;
255 /* An EXPR_LIST containing all MEM rtx's which are pending writes. */
256 rtx pending_write_mems;
258 /* Indicates the combined length of the two pending lists. We must prevent
259 these lists from ever growing too large since the number of dependencies
260 produced is at least O(N*N), and execution time is at least O(4*N*N), as
261 a function of the length of these pending lists. */
262 int pending_lists_length;
264 /* The last insn upon which all memory references must depend.
265 This is an insn which flushed the pending lists, creating a dependency
266 between it and all previously pending memory references. This creates
267 a barrier (or a checkpoint) which no memory reference is allowed to cross.
269 This includes all non constant CALL_INSNs. When we do interprocedural
270 alias analysis, this restriction can be relaxed.
271 This may also be an INSN that writes memory if the pending lists grow
273 rtx last_pending_memory_flush;
275 /* The last function call we have seen. All hard regs, and, of course,
276 the last function call, must depend on this. */
277 rtx last_function_call;
279 /* The LOG_LINKS field of this is a list of insns which use a pseudo register
280 that does not already cross a call. We create dependencies between each
281 of those insn and the next call insn, to ensure that they won't cross a call
282 after scheduling is done. */
283 rtx sched_before_next_call;
285 /* Element N is the next insn that sets (hard or pseudo) register
286 N within the current basic block; or zero, if there is no
287 such insn. Needed for new registers which may be introduced
288 by splitting insns. */
291 rtx *reg_last_clobbers;
294 static regset reg_pending_sets;
295 static regset reg_pending_clobbers;
296 static int reg_pending_sets_all;
298 /* To speed up the test for duplicate dependency links we keep a record
299 of true dependencies created by add_dependence when the average number
300 of instructions in a basic block is very large.
302 Studies have shown that there is typically around 5 instructions between
303 branches for typical C code. So we can make a guess that the average
304 basic block is approximately 5 instructions long; we will choose 100X
305 the average size as a very large basic block.
307 Each insn has an associated bitmap for its dependencies. Each bitmap
308 has enough entries to represent a dependency on any other insn in the
310 static sbitmap *true_dependency_cache;
312 /* Indexed by INSN_UID, the collection of all data associated with
313 a single instruction. */
315 struct haifa_insn_data
317 /* A list of insns which depend on the instruction. Unlike LOG_LINKS,
318 it represents forward dependancies. */
321 /* The line number note in effect for each insn. For line number
322 notes, this indicates whether the note may be reused. */
325 /* Logical uid gives the original ordering of the insns. */
328 /* A priority for each insn. */
331 /* The number of incoming edges in the forward dependency graph.
332 As scheduling proceds, counts are decreased. An insn moves to
333 the ready queue when its counter reaches zero. */
336 /* An encoding of the blockage range function. Both unit and range
338 unsigned int blockage;
340 /* Number of instructions referring to this insn. */
343 /* The minimum clock tick at which the insn becomes ready. This is
344 used to note timing constraints for the insns in the pending list. */
349 /* An encoding of the function units used. */
352 /* This weight is an estimation of the insn's contribution to
353 register pressure. */
356 /* Some insns (e.g. call) are not allowed to move across blocks. */
357 unsigned int cant_move : 1;
359 /* Set if there's DEF-USE dependance between some speculatively
360 moved load insn and this one. */
361 unsigned int fed_by_spec_load : 1;
362 unsigned int is_load_insn : 1;
365 static struct haifa_insn_data *h_i_d;
367 #define INSN_DEPEND(INSN) (h_i_d[INSN_UID (INSN)].depend)
368 #define INSN_LUID(INSN) (h_i_d[INSN_UID (INSN)].luid)
369 #define INSN_PRIORITY(INSN) (h_i_d[INSN_UID (INSN)].priority)
370 #define INSN_DEP_COUNT(INSN) (h_i_d[INSN_UID (INSN)].dep_count)
371 #define INSN_COST(INSN) (h_i_d[INSN_UID (INSN)].cost)
372 #define INSN_UNIT(INSN) (h_i_d[INSN_UID (INSN)].units)
373 #define INSN_REG_WEIGHT(INSN) (h_i_d[INSN_UID (INSN)].reg_weight)
375 #define INSN_BLOCKAGE(INSN) (h_i_d[INSN_UID (INSN)].blockage)
377 #define BLOCKAGE_MASK ((1 << BLOCKAGE_BITS) - 1)
378 #define ENCODE_BLOCKAGE(U, R) \
379 (((U) << BLOCKAGE_BITS \
380 | MIN_BLOCKAGE_COST (R)) << BLOCKAGE_BITS \
381 | MAX_BLOCKAGE_COST (R))
382 #define UNIT_BLOCKED(B) ((B) >> (2 * BLOCKAGE_BITS))
383 #define BLOCKAGE_RANGE(B) \
384 (((((B) >> BLOCKAGE_BITS) & BLOCKAGE_MASK) << (HOST_BITS_PER_INT / 2)) \
385 | ((B) & BLOCKAGE_MASK))
387 /* Encodings of the `<name>_unit_blockage_range' function. */
388 #define MIN_BLOCKAGE_COST(R) ((R) >> (HOST_BITS_PER_INT / 2))
389 #define MAX_BLOCKAGE_COST(R) ((R) & ((1 << (HOST_BITS_PER_INT / 2)) - 1))
391 #define DONE_PRIORITY -1
392 #define MAX_PRIORITY 0x7fffffff
393 #define TAIL_PRIORITY 0x7ffffffe
394 #define LAUNCH_PRIORITY 0x7f000001
395 #define DONE_PRIORITY_P(INSN) (INSN_PRIORITY (INSN) < 0)
396 #define LOW_PRIORITY_P(INSN) ((INSN_PRIORITY (INSN) & 0x7f000000) == 0)
398 #define INSN_REF_COUNT(INSN) (h_i_d[INSN_UID (INSN)].ref_count)
399 #define LINE_NOTE(INSN) (h_i_d[INSN_UID (INSN)].line_note)
400 #define INSN_TICK(INSN) (h_i_d[INSN_UID (INSN)].tick)
401 #define CANT_MOVE(insn) (h_i_d[INSN_UID (insn)].cant_move)
402 #define FED_BY_SPEC_LOAD(insn) (h_i_d[INSN_UID (insn)].fed_by_spec_load)
403 #define IS_LOAD_INSN(insn) (h_i_d[INSN_UID (insn)].is_load_insn)
405 /* Vector indexed by basic block number giving the starting line-number
406 for each basic block. */
407 static rtx *line_note_head;
409 /* List of important notes we must keep around. This is a pointer to the
410 last element in the list. */
411 static rtx note_list;
415 /* An instruction is ready to be scheduled when all insns preceding it
416 have already been scheduled. It is important to ensure that all
417 insns which use its result will not be executed until its result
418 has been computed. An insn is maintained in one of four structures:
420 (P) the "Pending" set of insns which cannot be scheduled until
421 their dependencies have been satisfied.
422 (Q) the "Queued" set of insns that can be scheduled when sufficient
424 (R) the "Ready" list of unscheduled, uncommitted insns.
425 (S) the "Scheduled" list of insns.
427 Initially, all insns are either "Pending" or "Ready" depending on
428 whether their dependencies are satisfied.
430 Insns move from the "Ready" list to the "Scheduled" list as they
431 are committed to the schedule. As this occurs, the insns in the
432 "Pending" list have their dependencies satisfied and move to either
433 the "Ready" list or the "Queued" set depending on whether
434 sufficient time has passed to make them ready. As time passes,
435 insns move from the "Queued" set to the "Ready" list. Insns may
436 move from the "Ready" list to the "Queued" set if they are blocked
437 due to a function unit conflict.
439 The "Pending" list (P) are the insns in the INSN_DEPEND of the unscheduled
440 insns, i.e., those that are ready, queued, and pending.
441 The "Queued" set (Q) is implemented by the variable `insn_queue'.
442 The "Ready" list (R) is implemented by the variables `ready' and
444 The "Scheduled" list (S) is the new insn chain built by this pass.
446 The transition (R->S) is implemented in the scheduling loop in
447 `schedule_block' when the best insn to schedule is chosen.
448 The transition (R->Q) is implemented in `queue_insn' when an
449 insn is found to have a function unit conflict with the already
451 The transitions (P->R and P->Q) are implemented in `schedule_insn' as
452 insns move from the ready list to the scheduled list.
453 The transition (Q->R) is implemented in 'queue_to_insn' as time
454 passes or stalls are introduced. */
456 /* Implement a circular buffer to delay instructions until sufficient
457 time has passed. INSN_QUEUE_SIZE is a power of two larger than
458 MAX_BLOCKAGE and MAX_READY_COST computed by genattr.c. This is the
459 longest time an isnsn may be queued. */
460 static rtx insn_queue[INSN_QUEUE_SIZE];
461 static int q_ptr = 0;
462 static int q_size = 0;
463 #define NEXT_Q(X) (((X)+1) & (INSN_QUEUE_SIZE-1))
464 #define NEXT_Q_AFTER(X, C) (((X)+C) & (INSN_QUEUE_SIZE-1))
466 /* Forward declarations. */
467 static void add_dependence PROTO ((rtx, rtx, enum reg_note));
469 static void remove_dependence PROTO ((rtx, rtx));
471 static rtx find_insn_list PROTO ((rtx, rtx));
472 static int insn_unit PROTO ((rtx));
473 static unsigned int blockage_range PROTO ((int, rtx));
474 static void clear_units PROTO ((void));
475 static int actual_hazard_this_instance PROTO ((int, int, rtx, int, int));
476 static void schedule_unit PROTO ((int, rtx, int));
477 static int actual_hazard PROTO ((int, rtx, int, int));
478 static int potential_hazard PROTO ((int, rtx, int));
479 static int insn_cost PROTO ((rtx, rtx, rtx));
480 static int priority PROTO ((rtx));
481 static void free_pending_lists PROTO ((void));
482 static void add_insn_mem_dependence PROTO ((struct deps *, rtx *, rtx *, rtx,
484 static void flush_pending_lists PROTO ((struct deps *, rtx, int));
485 static void sched_analyze_1 PROTO ((struct deps *, rtx, rtx));
486 static void sched_analyze_2 PROTO ((struct deps *, rtx, rtx));
487 static void sched_analyze_insn PROTO ((struct deps *, rtx, rtx, rtx));
488 static void sched_analyze PROTO ((struct deps *, rtx, rtx));
489 static int rank_for_schedule PROTO ((const PTR, const PTR));
490 static void swap_sort PROTO ((rtx *, int));
491 static void queue_insn PROTO ((rtx, int));
492 static int schedule_insn PROTO ((rtx, rtx *, int, int));
493 static void find_insn_reg_weight PROTO ((int));
494 static int schedule_block PROTO ((int, int));
495 static char *safe_concat PROTO ((char *, char *, const char *));
496 static int insn_issue_delay PROTO ((rtx));
497 static void adjust_priority PROTO ((rtx));
499 /* Control flow graph edges are kept in circular lists. */
508 static haifa_edge *edge_table;
510 #define NEXT_IN(edge) (edge_table[edge].next_in)
511 #define NEXT_OUT(edge) (edge_table[edge].next_out)
512 #define FROM_BLOCK(edge) (edge_table[edge].from_block)
513 #define TO_BLOCK(edge) (edge_table[edge].to_block)
515 /* Number of edges in the control flow graph. (In fact, larger than
516 that by 1, since edge 0 is unused.) */
519 /* Circular list of incoming/outgoing edges of a block. */
520 static int *in_edges;
521 static int *out_edges;
523 #define IN_EDGES(block) (in_edges[block])
524 #define OUT_EDGES(block) (out_edges[block])
528 static int is_cfg_nonregular PROTO ((void));
529 static int build_control_flow PROTO ((struct edge_list *));
530 static void new_edge PROTO ((int, int));
533 /* A region is the main entity for interblock scheduling: insns
534 are allowed to move between blocks in the same region, along
535 control flow graph edges, in the 'up' direction. */
538 int rgn_nr_blocks; /* Number of blocks in region. */
539 int rgn_blocks; /* cblocks in the region (actually index in rgn_bb_table). */
543 /* Number of regions in the procedure. */
544 static int nr_regions;
546 /* Table of region descriptions. */
547 static region *rgn_table;
549 /* Array of lists of regions' blocks. */
550 static int *rgn_bb_table;
552 /* Topological order of blocks in the region (if b2 is reachable from
553 b1, block_to_bb[b2] > block_to_bb[b1]). Note: A basic block is
554 always referred to by either block or b, while its topological
555 order name (in the region) is refered to by bb. */
556 static int *block_to_bb;
558 /* The number of the region containing a block. */
559 static int *containing_rgn;
561 #define RGN_NR_BLOCKS(rgn) (rgn_table[rgn].rgn_nr_blocks)
562 #define RGN_BLOCKS(rgn) (rgn_table[rgn].rgn_blocks)
563 #define BLOCK_TO_BB(block) (block_to_bb[block])
564 #define CONTAINING_RGN(block) (containing_rgn[block])
566 void debug_regions PROTO ((void));
567 static void find_single_block_region PROTO ((void));
568 static void find_rgns PROTO ((struct edge_list *, sbitmap *));
569 static int too_large PROTO ((int, int *, int *));
571 extern void debug_live PROTO ((int, int));
573 /* Blocks of the current region being scheduled. */
574 static int current_nr_blocks;
575 static int current_blocks;
577 /* The mapping from bb to block. */
578 #define BB_TO_BLOCK(bb) (rgn_bb_table[current_blocks + (bb)])
581 /* Bit vectors and bitset operations are needed for computations on
582 the control flow graph. */
584 typedef unsigned HOST_WIDE_INT *bitset;
587 int *first_member; /* Pointer to the list start in bitlst_table. */
588 int nr_members; /* The number of members of the bit list. */
592 static int bitlst_table_last;
593 static int bitlst_table_size;
594 static int *bitlst_table;
596 static char bitset_member PROTO ((bitset, int, int));
597 static void extract_bitlst PROTO ((bitset, int, bitlst *));
599 /* Target info declarations.
601 The block currently being scheduled is referred to as the "target" block,
602 while other blocks in the region from which insns can be moved to the
603 target are called "source" blocks. The candidate structure holds info
604 about such sources: are they valid? Speculative? Etc. */
605 typedef bitlst bblst;
616 static candidate *candidate_table;
618 /* A speculative motion requires checking live information on the path
619 from 'source' to 'target'. The split blocks are those to be checked.
620 After a speculative motion, live information should be modified in
623 Lists of split and update blocks for each candidate of the current
624 target are in array bblst_table. */
625 static int *bblst_table, bblst_size, bblst_last;
627 #define IS_VALID(src) ( candidate_table[src].is_valid )
628 #define IS_SPECULATIVE(src) ( candidate_table[src].is_speculative )
629 #define SRC_PROB(src) ( candidate_table[src].src_prob )
631 /* The bb being currently scheduled. */
632 static int target_bb;
635 typedef bitlst edgelst;
637 /* Target info functions. */
638 static void split_edges PROTO ((int, int, edgelst *));
639 static void compute_trg_info PROTO ((int));
640 void debug_candidate PROTO ((int));
641 void debug_candidates PROTO ((int));
644 /* Bit-set of bbs, where bit 'i' stands for bb 'i'. */
645 typedef bitset bbset;
647 /* Number of words of the bbset. */
648 static int bbset_size;
650 /* Dominators array: dom[i] contains the bbset of dominators of
651 bb i in the region. */
654 /* bb 0 is the only region entry. */
655 #define IS_RGN_ENTRY(bb) (!bb)
657 /* Is bb_src dominated by bb_trg. */
658 #define IS_DOMINATED(bb_src, bb_trg) \
659 ( bitset_member (dom[bb_src], bb_trg, bbset_size) )
661 /* Probability: Prob[i] is a float in [0, 1] which is the probability
662 of bb i relative to the region entry. */
665 /* The probability of bb_src, relative to bb_trg. Note, that while the
666 'prob[bb]' is a float in [0, 1], this macro returns an integer
668 #define GET_SRC_PROB(bb_src, bb_trg) ((int) (100.0 * (prob[bb_src] / \
671 /* Bit-set of edges, where bit i stands for edge i. */
672 typedef bitset edgeset;
674 /* Number of edges in the region. */
675 static int rgn_nr_edges;
677 /* Array of size rgn_nr_edges. */
678 static int *rgn_edges;
680 /* Number of words in an edgeset. */
681 static int edgeset_size;
683 /* Mapping from each edge in the graph to its number in the rgn. */
684 static int *edge_to_bit;
685 #define EDGE_TO_BIT(edge) (edge_to_bit[edge])
687 /* The split edges of a source bb is different for each target
688 bb. In order to compute this efficiently, the 'potential-split edges'
689 are computed for each bb prior to scheduling a region. This is actually
690 the split edges of each bb relative to the region entry.
692 pot_split[bb] is the set of potential split edges of bb. */
693 static edgeset *pot_split;
695 /* For every bb, a set of its ancestor edges. */
696 static edgeset *ancestor_edges;
698 static void compute_dom_prob_ps PROTO ((int));
700 #define ABS_VALUE(x) (((x)<0)?(-(x)):(x))
701 #define INSN_PROBABILITY(INSN) (SRC_PROB (BLOCK_TO_BB (BLOCK_NUM (INSN))))
702 #define IS_SPECULATIVE_INSN(INSN) (IS_SPECULATIVE (BLOCK_TO_BB (BLOCK_NUM (INSN))))
703 #define INSN_BB(INSN) (BLOCK_TO_BB (BLOCK_NUM (INSN)))
705 /* Parameters affecting the decision of rank_for_schedule(). */
706 #define MIN_DIFF_PRIORITY 2
707 #define MIN_PROBABILITY 40
708 #define MIN_PROB_DIFF 10
710 /* Speculative scheduling functions. */
711 static int check_live_1 PROTO ((int, rtx));
712 static void update_live_1 PROTO ((int, rtx));
713 static int check_live PROTO ((rtx, int));
714 static void update_live PROTO ((rtx, int));
715 static void set_spec_fed PROTO ((rtx));
716 static int is_pfree PROTO ((rtx, int, int));
717 static int find_conditional_protection PROTO ((rtx, int));
718 static int is_conditionally_protected PROTO ((rtx, int, int));
719 static int may_trap_exp PROTO ((rtx, int));
720 static int haifa_classify_insn PROTO ((rtx));
721 static int is_prisky PROTO ((rtx, int, int));
722 static int is_exception_free PROTO ((rtx, int, int));
724 static char find_insn_mem_list PROTO ((rtx, rtx, rtx, rtx));
725 static void compute_block_forward_dependences PROTO ((int));
726 static void add_branch_dependences PROTO ((rtx, rtx));
727 static void compute_block_backward_dependences PROTO ((int));
728 void debug_dependencies PROTO ((void));
730 /* Notes handling mechanism:
731 =========================
732 Generally, NOTES are saved before scheduling and restored after scheduling.
733 The scheduler distinguishes between three types of notes:
735 (1) LINE_NUMBER notes, generated and used for debugging. Here,
736 before scheduling a region, a pointer to the LINE_NUMBER note is
737 added to the insn following it (in save_line_notes()), and the note
738 is removed (in rm_line_notes() and unlink_line_notes()). After
739 scheduling the region, this pointer is used for regeneration of
740 the LINE_NUMBER note (in restore_line_notes()).
742 (2) LOOP_BEGIN, LOOP_END, SETJMP, EHREGION_BEG, EHREGION_END notes:
743 Before scheduling a region, a pointer to the note is added to the insn
744 that follows or precedes it. (This happens as part of the data dependence
745 computation). After scheduling an insn, the pointer contained in it is
746 used for regenerating the corresponding note (in reemit_notes).
748 (3) All other notes (e.g. INSN_DELETED): Before scheduling a block,
749 these notes are put in a list (in rm_other_notes() and
750 unlink_other_notes ()). After scheduling the block, these notes are
751 inserted at the beginning of the block (in schedule_block()). */
753 static rtx unlink_other_notes PROTO ((rtx, rtx));
754 static rtx unlink_line_notes PROTO ((rtx, rtx));
755 static void rm_line_notes PROTO ((int));
756 static void save_line_notes PROTO ((int));
757 static void restore_line_notes PROTO ((int));
758 static void rm_redundant_line_notes PROTO ((void));
759 static void rm_other_notes PROTO ((rtx, rtx));
760 static rtx reemit_notes PROTO ((rtx, rtx));
762 static void get_block_head_tail PROTO ((int, rtx *, rtx *));
763 static void get_bb_head_tail PROTO ((int, rtx *, rtx *));
765 static int queue_to_ready PROTO ((rtx [], int));
767 static void debug_ready_list PROTO ((rtx[], int));
768 static void init_target_units PROTO ((void));
769 static void insn_print_units PROTO ((rtx));
770 static int get_visual_tbl_length PROTO ((void));
771 static void init_block_visualization PROTO ((void));
772 static void print_block_visualization PROTO ((int, const char *));
773 static void visualize_scheduled_insns PROTO ((int, int));
774 static void visualize_no_unit PROTO ((rtx));
775 static void visualize_stall_cycles PROTO ((int, int));
776 static void print_exp PROTO ((char *, rtx, int));
777 static void print_value PROTO ((char *, rtx, int));
778 static void print_pattern PROTO ((char *, rtx, int));
779 static void print_insn PROTO ((char *, rtx, int));
780 void debug_reg_vector PROTO ((regset));
782 static rtx move_insn1 PROTO ((rtx, rtx));
783 static rtx move_insn PROTO ((rtx, rtx));
784 static rtx group_leader PROTO ((rtx));
785 static int set_priorities PROTO ((int));
786 static void init_deps PROTO ((struct deps *));
787 static void schedule_region PROTO ((int));
789 #endif /* INSN_SCHEDULING */
791 #define SIZE_FOR_MODE(X) (GET_MODE_SIZE (GET_MODE (X)))
793 /* Add ELEM wrapped in an INSN_LIST with reg note kind DEP_TYPE to the
794 LOG_LINKS of INSN, if not already there. DEP_TYPE indicates the type
795 of dependence that this link represents. */
798 add_dependence (insn, elem, dep_type)
801 enum reg_note dep_type;
805 /* Don't depend an insn on itself. */
809 /* We can get a dependency on deleted insns due to optimizations in
810 the register allocation and reloading or due to splitting. Any
811 such dependency is useless and can be ignored. */
812 if (GET_CODE (elem) == NOTE)
815 /* If elem is part of a sequence that must be scheduled together, then
816 make the dependence point to the last insn of the sequence.
817 When HAVE_cc0, it is possible for NOTEs to exist between users and
818 setters of the condition codes, so we must skip past notes here.
819 Otherwise, NOTEs are impossible here. */
821 next = NEXT_INSN (elem);
824 while (next && GET_CODE (next) == NOTE)
825 next = NEXT_INSN (next);
828 if (next && SCHED_GROUP_P (next)
829 && GET_CODE (next) != CODE_LABEL)
831 /* Notes will never intervene here though, so don't bother checking
833 /* We must reject CODE_LABELs, so that we don't get confused by one
834 that has LABEL_PRESERVE_P set, which is represented by the same
835 bit in the rtl as SCHED_GROUP_P. A CODE_LABEL can never be
837 while (NEXT_INSN (next) && SCHED_GROUP_P (NEXT_INSN (next))
838 && GET_CODE (NEXT_INSN (next)) != CODE_LABEL)
839 next = NEXT_INSN (next);
841 /* Again, don't depend an insn on itself. */
845 /* Make the dependence to NEXT, the last insn of the group, instead
846 of the original ELEM. */
850 #ifdef INSN_SCHEDULING
851 /* (This code is guarded by INSN_SCHEDULING, otherwise INSN_BB is undefined.)
852 No need for interblock dependences with calls, since
853 calls are not moved between blocks. Note: the edge where
854 elem is a CALL is still required. */
855 if (GET_CODE (insn) == CALL_INSN
856 && (INSN_BB (elem) != INSN_BB (insn)))
860 /* If we already have a true dependency for ELEM, then we do not
861 need to do anything. Avoiding the list walk below can cut
862 compile times dramatically for some code. */
863 if (true_dependency_cache
864 && TEST_BIT (true_dependency_cache[INSN_LUID (insn)], INSN_LUID (elem)))
868 /* Check that we don't already have this dependence. */
869 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
870 if (XEXP (link, 0) == elem)
872 /* If this is a more restrictive type of dependence than the existing
873 one, then change the existing dependence to this type. */
874 if ((int) dep_type < (int) REG_NOTE_KIND (link))
875 PUT_REG_NOTE_KIND (link, dep_type);
877 #ifdef INSN_SCHEDULING
878 /* If we are adding a true dependency to INSN's LOG_LINKs, then
879 note that in the bitmap cache of true dependency information. */
880 if ((int)dep_type == 0 && true_dependency_cache)
881 SET_BIT (true_dependency_cache[INSN_LUID (insn)], INSN_LUID (elem));
885 /* Might want to check one level of transitivity to save conses. */
887 link = alloc_INSN_LIST (elem, LOG_LINKS (insn));
888 LOG_LINKS (insn) = link;
890 /* Insn dependency, not data dependency. */
891 PUT_REG_NOTE_KIND (link, dep_type);
893 #ifdef INSN_SCHEDULING
894 /* If we are adding a true dependency to INSN's LOG_LINKs, then
895 note that in the bitmap cache of true dependency information. */
896 if ((int)dep_type == 0 && true_dependency_cache)
897 SET_BIT (true_dependency_cache[INSN_LUID (insn)], INSN_LUID (elem));
902 /* Remove ELEM wrapped in an INSN_LIST from the LOG_LINKS
903 of INSN. Abort if not found. */
906 remove_dependence (insn, elem)
910 rtx prev, link, next;
913 for (prev = 0, link = LOG_LINKS (insn); link; link = next)
915 next = XEXP (link, 1);
916 if (XEXP (link, 0) == elem)
919 XEXP (prev, 1) = next;
921 LOG_LINKS (insn) = next;
923 #ifdef INSN_SCHEDULING
924 /* If we are removing a true dependency from the LOG_LINKS list,
925 make sure to remove it from the cache too. */
926 if (REG_NOTE_KIND (link) == 0 && true_dependency_cache)
927 RESET_BIT (true_dependency_cache[INSN_LUID (insn)],
931 free_INSN_LIST_node (link);
943 #endif /* HAVE_cc0 */
945 #ifndef INSN_SCHEDULING
947 schedule_insns (dump_file)
957 #define HAIFA_INLINE __inline
960 /* Computation of memory dependencies. */
962 /* Data structures for the computation of data dependences in a regions. We
963 keep one mem_deps structure for every basic block. Before analyzing the
964 data dependences for a bb, its variables are initialized as a function of
965 the variables of its predecessors. When the analysis for a bb completes,
966 we save the contents to the corresponding bb_mem_deps[bb] variable. */
968 static struct deps *bb_deps;
970 /* Pointer to the last instruction scheduled. Used by rank_for_schedule,
971 so that insns independent of the last scheduled insn will be preferred
972 over dependent instructions. */
974 static rtx last_scheduled_insn;
976 /* Functions for construction of the control flow graph. */
978 /* Return 1 if control flow graph should not be constructed, 0 otherwise.
980 We decide not to build the control flow graph if there is possibly more
981 than one entry to the function, if computed branches exist, of if we
982 have nonlocal gotos. */
991 /* If we have a label that could be the target of a nonlocal goto, then
992 the cfg is not well structured. */
993 if (nonlocal_goto_handler_labels)
996 /* If we have any forced labels, then the cfg is not well structured. */
1000 /* If this function has a computed jump, then we consider the cfg
1001 not well structured. */
1002 if (current_function_has_computed_jump)
1005 /* If we have exception handlers, then we consider the cfg not well
1006 structured. ?!? We should be able to handle this now that flow.c
1007 computes an accurate cfg for EH. */
1008 if (exception_handler_labels)
1011 /* If we have non-jumping insns which refer to labels, then we consider
1012 the cfg not well structured. */
1013 /* Check for labels referred to other thn by jumps. */
1014 for (b = 0; b < n_basic_blocks; b++)
1015 for (insn = BLOCK_HEAD (b);; insn = NEXT_INSN (insn))
1017 code = GET_CODE (insn);
1018 if (GET_RTX_CLASS (code) == 'i')
1022 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
1023 if (REG_NOTE_KIND (note) == REG_LABEL)
1027 if (insn == BLOCK_END (b))
1031 /* All the tests passed. Consider the cfg well structured. */
1035 /* Build the control flow graph and set nr_edges.
1037 Instead of trying to build a cfg ourselves, we rely on flow to
1038 do it for us. Stamp out useless code (and bug) duplication.
1040 Return nonzero if an irregularity in the cfg is found which would
1041 prevent cross block scheduling. */
1044 build_control_flow (edge_list)
1045 struct edge_list *edge_list;
1047 int i, unreachable, num_edges;
1049 /* This already accounts for entry/exit edges. */
1050 num_edges = NUM_EDGES (edge_list);
1052 /* Unreachable loops with more than one basic block are detected
1053 during the DFS traversal in find_rgns.
1055 Unreachable loops with a single block are detected here. This
1056 test is redundant with the one in find_rgns, but it's much
1057 cheaper to go ahead and catch the trivial case here. */
1059 for (i = 0; i < n_basic_blocks; i++)
1061 basic_block b = BASIC_BLOCK (i);
1064 || (b->pred->src == b
1065 && b->pred->pred_next == NULL))
1069 /* ??? We can kill these soon. */
1070 in_edges = (int *) xcalloc (n_basic_blocks, sizeof (int));
1071 out_edges = (int *) xcalloc (n_basic_blocks, sizeof (int));
1072 edge_table = (haifa_edge *) xcalloc (num_edges, sizeof (haifa_edge));
1075 for (i = 0; i < num_edges; i++)
1077 edge e = INDEX_EDGE (edge_list, i);
1079 if (e->dest != EXIT_BLOCK_PTR
1080 && e->src != ENTRY_BLOCK_PTR)
1081 new_edge (e->src->index, e->dest->index);
1084 /* Increment by 1, since edge 0 is unused. */
1091 /* Record an edge in the control flow graph from SOURCE to TARGET.
1093 In theory, this is redundant with the s_succs computed above, but
1094 we have not converted all of haifa to use information from the
1098 new_edge (source, target)
1102 int curr_edge, fst_edge;
1104 /* Check for duplicates. */
1105 fst_edge = curr_edge = OUT_EDGES (source);
1108 if (FROM_BLOCK (curr_edge) == source
1109 && TO_BLOCK (curr_edge) == target)
1114 curr_edge = NEXT_OUT (curr_edge);
1116 if (fst_edge == curr_edge)
1122 FROM_BLOCK (e) = source;
1123 TO_BLOCK (e) = target;
1125 if (OUT_EDGES (source))
1127 next_edge = NEXT_OUT (OUT_EDGES (source));
1128 NEXT_OUT (OUT_EDGES (source)) = e;
1129 NEXT_OUT (e) = next_edge;
1133 OUT_EDGES (source) = e;
1137 if (IN_EDGES (target))
1139 next_edge = NEXT_IN (IN_EDGES (target));
1140 NEXT_IN (IN_EDGES (target)) = e;
1141 NEXT_IN (e) = next_edge;
1145 IN_EDGES (target) = e;
1151 /* BITSET macros for operations on the control flow graph. */
1153 /* Compute bitwise union of two bitsets. */
1154 #define BITSET_UNION(set1, set2, len) \
1155 do { register bitset tp = set1, sp = set2; \
1157 for (i = 0; i < len; i++) \
1158 *(tp++) |= *(sp++); } while (0)
1160 /* Compute bitwise intersection of two bitsets. */
1161 #define BITSET_INTER(set1, set2, len) \
1162 do { register bitset tp = set1, sp = set2; \
1164 for (i = 0; i < len; i++) \
1165 *(tp++) &= *(sp++); } while (0)
1167 /* Compute bitwise difference of two bitsets. */
1168 #define BITSET_DIFFER(set1, set2, len) \
1169 do { register bitset tp = set1, sp = set2; \
1171 for (i = 0; i < len; i++) \
1172 *(tp++) &= ~*(sp++); } while (0)
1174 /* Inverts every bit of bitset 'set'. */
1175 #define BITSET_INVERT(set, len) \
1176 do { register bitset tmpset = set; \
1178 for (i = 0; i < len; i++, tmpset++) \
1179 *tmpset = ~*tmpset; } while (0)
1181 /* Turn on the index'th bit in bitset set. */
1182 #define BITSET_ADD(set, index, len) \
1184 if (index >= HOST_BITS_PER_WIDE_INT * len) \
1187 set[index/HOST_BITS_PER_WIDE_INT] |= \
1188 1 << (index % HOST_BITS_PER_WIDE_INT); \
1191 /* Turn off the index'th bit in set. */
1192 #define BITSET_REMOVE(set, index, len) \
1194 if (index >= HOST_BITS_PER_WIDE_INT * len) \
1197 set[index/HOST_BITS_PER_WIDE_INT] &= \
1198 ~(1 << (index%HOST_BITS_PER_WIDE_INT)); \
1202 /* Check if the index'th bit in bitset set is on. */
1205 bitset_member (set, index, len)
1209 if (index >= HOST_BITS_PER_WIDE_INT * len)
1211 return (set[index / HOST_BITS_PER_WIDE_INT] &
1212 1 << (index % HOST_BITS_PER_WIDE_INT)) ? 1 : 0;
1216 /* Translate a bit-set SET to a list BL of the bit-set members. */
1219 extract_bitlst (set, len, bl)
1225 unsigned HOST_WIDE_INT word;
1227 /* bblst table space is reused in each call to extract_bitlst. */
1228 bitlst_table_last = 0;
1230 bl->first_member = &bitlst_table[bitlst_table_last];
1233 for (i = 0; i < len; i++)
1236 offset = i * HOST_BITS_PER_WIDE_INT;
1237 for (j = 0; word; j++)
1241 bitlst_table[bitlst_table_last++] = offset;
1252 /* Functions for the construction of regions. */
1254 /* Print the regions, for debugging purposes. Callable from debugger. */
1261 fprintf (dump, "\n;; ------------ REGIONS ----------\n\n");
1262 for (rgn = 0; rgn < nr_regions; rgn++)
1264 fprintf (dump, ";;\trgn %d nr_blocks %d:\n", rgn,
1265 rgn_table[rgn].rgn_nr_blocks);
1266 fprintf (dump, ";;\tbb/block: ");
1268 for (bb = 0; bb < rgn_table[rgn].rgn_nr_blocks; bb++)
1270 current_blocks = RGN_BLOCKS (rgn);
1272 if (bb != BLOCK_TO_BB (BB_TO_BLOCK (bb)))
1275 fprintf (dump, " %d/%d ", bb, BB_TO_BLOCK (bb));
1278 fprintf (dump, "\n\n");
1283 /* Build a single block region for each basic block in the function.
1284 This allows for using the same code for interblock and basic block
1288 find_single_block_region ()
1292 for (i = 0; i < n_basic_blocks; i++)
1294 rgn_bb_table[i] = i;
1295 RGN_NR_BLOCKS (i) = 1;
1297 CONTAINING_RGN (i) = i;
1298 BLOCK_TO_BB (i) = 0;
1300 nr_regions = n_basic_blocks;
1304 /* Update number of blocks and the estimate for number of insns
1305 in the region. Return 1 if the region is "too large" for interblock
1306 scheduling (compile time considerations), otherwise return 0. */
1309 too_large (block, num_bbs, num_insns)
1310 int block, *num_bbs, *num_insns;
1313 (*num_insns) += (INSN_LUID (BLOCK_END (block)) -
1314 INSN_LUID (BLOCK_HEAD (block)));
1315 if ((*num_bbs > MAX_RGN_BLOCKS) || (*num_insns > MAX_RGN_INSNS))
1322 /* Update_loop_relations(blk, hdr): Check if the loop headed by max_hdr[blk]
1323 is still an inner loop. Put in max_hdr[blk] the header of the most inner
1324 loop containing blk. */
1325 #define UPDATE_LOOP_RELATIONS(blk, hdr) \
1327 if (max_hdr[blk] == -1) \
1328 max_hdr[blk] = hdr; \
1329 else if (dfs_nr[max_hdr[blk]] > dfs_nr[hdr]) \
1330 RESET_BIT (inner, hdr); \
1331 else if (dfs_nr[max_hdr[blk]] < dfs_nr[hdr]) \
1333 RESET_BIT (inner,max_hdr[blk]); \
1334 max_hdr[blk] = hdr; \
1339 /* Find regions for interblock scheduling.
1341 A region for scheduling can be:
1343 * A loop-free procedure, or
1345 * A reducible inner loop, or
1347 * A basic block not contained in any other region.
1350 ?!? In theory we could build other regions based on extended basic
1351 blocks or reverse extended basic blocks. Is it worth the trouble?
1353 Loop blocks that form a region are put into the region's block list
1354 in topological order.
1356 This procedure stores its results into the following global (ick) variables
1365 We use dominator relationships to avoid making regions out of non-reducible
1368 This procedure needs to be converted to work on pred/succ lists instead
1369 of edge tables. That would simplify it somewhat. */
1372 find_rgns (edge_list, dom)
1373 struct edge_list *edge_list;
1376 int *max_hdr, *dfs_nr, *stack, *degree;
1378 int node, child, loop_head, i, head, tail;
1379 int count = 0, sp, idx = 0, current_edge = out_edges[0];
1380 int num_bbs, num_insns, unreachable;
1381 int too_large_failure;
1383 /* Note if an edge has been passed. */
1386 /* Note if a block is a natural loop header. */
1389 /* Note if a block is an natural inner loop header. */
1392 /* Note if a block is in the block queue. */
1395 /* Note if a block is in the block queue. */
1398 int num_edges = NUM_EDGES (edge_list);
1400 /* Perform a DFS traversal of the cfg. Identify loop headers, inner loops
1401 and a mapping from block to its loop header (if the block is contained
1402 in a loop, else -1).
1404 Store results in HEADER, INNER, and MAX_HDR respectively, these will
1405 be used as inputs to the second traversal.
1407 STACK, SP and DFS_NR are only used during the first traversal. */
1409 /* Allocate and initialize variables for the first traversal. */
1410 max_hdr = (int *) xmalloc (n_basic_blocks * sizeof (int));
1411 dfs_nr = (int *) xcalloc (n_basic_blocks, sizeof (int));
1412 stack = (int *) xmalloc (nr_edges * sizeof (int));
1414 inner = sbitmap_alloc (n_basic_blocks);
1415 sbitmap_ones (inner);
1417 header = sbitmap_alloc (n_basic_blocks);
1418 sbitmap_zero (header);
1420 passed = sbitmap_alloc (nr_edges);
1421 sbitmap_zero (passed);
1423 in_queue = sbitmap_alloc (n_basic_blocks);
1424 sbitmap_zero (in_queue);
1426 in_stack = sbitmap_alloc (n_basic_blocks);
1427 sbitmap_zero (in_stack);
1429 for (i = 0; i < n_basic_blocks; i++)
1432 /* DFS traversal to find inner loops in the cfg. */
1437 if (current_edge == 0 || TEST_BIT (passed, current_edge))
1439 /* We have reached a leaf node or a node that was already
1440 processed. Pop edges off the stack until we find
1441 an edge that has not yet been processed. */
1443 && (current_edge == 0 || TEST_BIT (passed, current_edge)))
1445 /* Pop entry off the stack. */
1446 current_edge = stack[sp--];
1447 node = FROM_BLOCK (current_edge);
1448 child = TO_BLOCK (current_edge);
1449 RESET_BIT (in_stack, child);
1450 if (max_hdr[child] >= 0 && TEST_BIT (in_stack, max_hdr[child]))
1451 UPDATE_LOOP_RELATIONS (node, max_hdr[child]);
1452 current_edge = NEXT_OUT (current_edge);
1455 /* See if have finished the DFS tree traversal. */
1456 if (sp < 0 && TEST_BIT (passed, current_edge))
1459 /* Nope, continue the traversal with the popped node. */
1463 /* Process a node. */
1464 node = FROM_BLOCK (current_edge);
1465 child = TO_BLOCK (current_edge);
1466 SET_BIT (in_stack, node);
1467 dfs_nr[node] = ++count;
1469 /* If the successor is in the stack, then we've found a loop.
1470 Mark the loop, if it is not a natural loop, then it will
1471 be rejected during the second traversal. */
1472 if (TEST_BIT (in_stack, child))
1475 SET_BIT (header, child);
1476 UPDATE_LOOP_RELATIONS (node, child);
1477 SET_BIT (passed, current_edge);
1478 current_edge = NEXT_OUT (current_edge);
1482 /* If the child was already visited, then there is no need to visit
1483 it again. Just update the loop relationships and restart
1487 if (max_hdr[child] >= 0 && TEST_BIT (in_stack, max_hdr[child]))
1488 UPDATE_LOOP_RELATIONS (node, max_hdr[child]);
1489 SET_BIT (passed, current_edge);
1490 current_edge = NEXT_OUT (current_edge);
1494 /* Push an entry on the stack and continue DFS traversal. */
1495 stack[++sp] = current_edge;
1496 SET_BIT (passed, current_edge);
1497 current_edge = OUT_EDGES (child);
1499 /* This is temporary until haifa is converted to use rth's new
1500 cfg routines which have true entry/exit blocks and the
1501 appropriate edges from/to those blocks.
1503 Generally we update dfs_nr for a node when we process its
1504 out edge. However, if the node has no out edge then we will
1505 not set dfs_nr for that node. This can confuse the scheduler
1506 into thinking that we have unreachable blocks, which in turn
1507 disables cross block scheduling.
1509 So, if we have a node with no out edges, go ahead and mark it
1510 as reachable now. */
1511 if (current_edge == 0)
1512 dfs_nr[child] = ++count;
1515 /* Another check for unreachable blocks. The earlier test in
1516 is_cfg_nonregular only finds unreachable blocks that do not
1519 The DFS traversal will mark every block that is reachable from
1520 the entry node by placing a nonzero value in dfs_nr. Thus if
1521 dfs_nr is zero for any block, then it must be unreachable. */
1523 for (i = 0; i < n_basic_blocks; i++)
1530 /* Gross. To avoid wasting memory, the second pass uses the dfs_nr array
1531 to hold degree counts. */
1534 for (i = 0; i < n_basic_blocks; i++)
1536 for (i = 0; i < num_edges; i++)
1538 edge e = INDEX_EDGE (edge_list, i);
1540 if (e->dest != EXIT_BLOCK_PTR)
1541 degree[e->dest->index]++;
1544 /* Do not perform region scheduling if there are any unreachable
1551 SET_BIT (header, 0);
1553 /* Second travsersal:find reducible inner loops and topologically sort
1554 block of each region. */
1556 queue = (int *) xmalloc (n_basic_blocks * sizeof (int));
1558 /* Find blocks which are inner loop headers. We still have non-reducible
1559 loops to consider at this point. */
1560 for (i = 0; i < n_basic_blocks; i++)
1562 if (TEST_BIT (header, i) && TEST_BIT (inner, i))
1567 /* Now check that the loop is reducible. We do this separate
1568 from finding inner loops so that we do not find a reducible
1569 loop which contains an inner non-reducible loop.
1571 A simple way to find reducible/natural loops is to verify
1572 that each block in the loop is dominated by the loop
1575 If there exists a block that is not dominated by the loop
1576 header, then the block is reachable from outside the loop
1577 and thus the loop is not a natural loop. */
1578 for (j = 0; j < n_basic_blocks; j++)
1580 /* First identify blocks in the loop, except for the loop
1582 if (i == max_hdr[j] && i != j)
1584 /* Now verify that the block is dominated by the loop
1586 if (!TEST_BIT (dom[j], i))
1591 /* If we exited the loop early, then I is the header of
1592 a non-reducible loop and we should quit processing it
1594 if (j != n_basic_blocks)
1597 /* I is a header of an inner loop, or block 0 in a subroutine
1598 with no loops at all. */
1600 too_large_failure = 0;
1601 loop_head = max_hdr[i];
1603 /* Decrease degree of all I's successors for topological
1605 for (e = BASIC_BLOCK (i)->succ; e; e = e->succ_next)
1606 if (e->dest != EXIT_BLOCK_PTR)
1607 --degree[e->dest->index];
1609 /* Estimate # insns, and count # blocks in the region. */
1611 num_insns = (INSN_LUID (BLOCK_END (i))
1612 - INSN_LUID (BLOCK_HEAD (i)));
1615 /* Find all loop latches (blocks with back edges to the loop
1616 header) or all the leaf blocks in the cfg has no loops.
1618 Place those blocks into the queue. */
1621 for (j = 0; j < n_basic_blocks; j++)
1622 /* Leaf nodes have only a single successor which must
1624 if (BASIC_BLOCK (j)->succ
1625 && BASIC_BLOCK (j)->succ->dest == EXIT_BLOCK_PTR
1626 && BASIC_BLOCK (j)->succ->succ_next == NULL)
1629 SET_BIT (in_queue, j);
1631 if (too_large (j, &num_bbs, &num_insns))
1633 too_large_failure = 1;
1642 for (e = BASIC_BLOCK (i)->pred; e; e = e->pred_next)
1644 if (e->src == ENTRY_BLOCK_PTR)
1647 node = e->src->index;
1649 if (max_hdr[node] == loop_head && node != i)
1651 /* This is a loop latch. */
1652 queue[++tail] = node;
1653 SET_BIT (in_queue, node);
1655 if (too_large (node, &num_bbs, &num_insns))
1657 too_large_failure = 1;
1665 /* Now add all the blocks in the loop to the queue.
1667 We know the loop is a natural loop; however the algorithm
1668 above will not always mark certain blocks as being in the
1677 The algorithm in the DFS traversal may not mark B & D as part
1678 of the loop (ie they will not have max_hdr set to A).
1680 We know they can not be loop latches (else they would have
1681 had max_hdr set since they'd have a backedge to a dominator
1682 block). So we don't need them on the initial queue.
1684 We know they are part of the loop because they are dominated
1685 by the loop header and can be reached by a backwards walk of
1686 the edges starting with nodes on the initial queue.
1688 It is safe and desirable to include those nodes in the
1689 loop/scheduling region. To do so we would need to decrease
1690 the degree of a node if it is the target of a backedge
1691 within the loop itself as the node is placed in the queue.
1693 We do not do this because I'm not sure that the actual
1694 scheduling code will properly handle this case. ?!? */
1696 while (head < tail && !too_large_failure)
1699 child = queue[++head];
1701 for (e = BASIC_BLOCK (child)->pred; e; e = e->pred_next)
1703 node = e->src->index;
1705 /* See discussion above about nodes not marked as in
1706 this loop during the initial DFS traversal. */
1707 if (e->src == ENTRY_BLOCK_PTR
1708 || max_hdr[node] != loop_head)
1713 else if (!TEST_BIT (in_queue, node) && node != i)
1715 queue[++tail] = node;
1716 SET_BIT (in_queue, node);
1718 if (too_large (node, &num_bbs, &num_insns))
1720 too_large_failure = 1;
1727 if (tail >= 0 && !too_large_failure)
1729 /* Place the loop header into list of region blocks. */
1731 rgn_bb_table[idx] = i;
1732 RGN_NR_BLOCKS (nr_regions) = num_bbs;
1733 RGN_BLOCKS (nr_regions) = idx++;
1734 CONTAINING_RGN (i) = nr_regions;
1735 BLOCK_TO_BB (i) = count = 0;
1737 /* Remove blocks from queue[] when their in degree
1738 becomes zero. Repeat until no blocks are left on the
1739 list. This produces a topological list of blocks in
1745 child = queue[head];
1746 if (degree[child] == 0)
1751 rgn_bb_table[idx++] = child;
1752 BLOCK_TO_BB (child) = ++count;
1753 CONTAINING_RGN (child) = nr_regions;
1754 queue[head] = queue[tail--];
1756 for (e = BASIC_BLOCK (child)->succ;
1759 if (e->dest != EXIT_BLOCK_PTR)
1760 --degree[e->dest->index];
1772 /* Any block that did not end up in a region is placed into a region
1774 for (i = 0; i < n_basic_blocks; i++)
1777 rgn_bb_table[idx] = i;
1778 RGN_NR_BLOCKS (nr_regions) = 1;
1779 RGN_BLOCKS (nr_regions) = idx++;
1780 CONTAINING_RGN (i) = nr_regions++;
1781 BLOCK_TO_BB (i) = 0;
1795 /* Functions for regions scheduling information. */
1797 /* Compute dominators, probability, and potential-split-edges of bb.
1798 Assume that these values were already computed for bb's predecessors. */
1801 compute_dom_prob_ps (bb)
1804 int nxt_in_edge, fst_in_edge, pred;
1805 int fst_out_edge, nxt_out_edge, nr_out_edges, nr_rgn_out_edges;
1808 if (IS_RGN_ENTRY (bb))
1810 BITSET_ADD (dom[bb], 0, bbset_size);
1815 fst_in_edge = nxt_in_edge = IN_EDGES (BB_TO_BLOCK (bb));
1817 /* Intialize dom[bb] to '111..1'. */
1818 BITSET_INVERT (dom[bb], bbset_size);
1822 pred = FROM_BLOCK (nxt_in_edge);
1823 BITSET_INTER (dom[bb], dom[BLOCK_TO_BB (pred)], bbset_size);
1825 BITSET_UNION (ancestor_edges[bb], ancestor_edges[BLOCK_TO_BB (pred)],
1828 BITSET_ADD (ancestor_edges[bb], EDGE_TO_BIT (nxt_in_edge), edgeset_size);
1831 nr_rgn_out_edges = 0;
1832 fst_out_edge = OUT_EDGES (pred);
1833 nxt_out_edge = NEXT_OUT (fst_out_edge);
1834 BITSET_UNION (pot_split[bb], pot_split[BLOCK_TO_BB (pred)],
1837 BITSET_ADD (pot_split[bb], EDGE_TO_BIT (fst_out_edge), edgeset_size);
1839 /* The successor doesn't belong in the region? */
1840 if (CONTAINING_RGN (TO_BLOCK (fst_out_edge)) !=
1841 CONTAINING_RGN (BB_TO_BLOCK (bb)))
1844 while (fst_out_edge != nxt_out_edge)
1847 /* The successor doesn't belong in the region? */
1848 if (CONTAINING_RGN (TO_BLOCK (nxt_out_edge)) !=
1849 CONTAINING_RGN (BB_TO_BLOCK (bb)))
1851 BITSET_ADD (pot_split[bb], EDGE_TO_BIT (nxt_out_edge), edgeset_size);
1852 nxt_out_edge = NEXT_OUT (nxt_out_edge);
1856 /* Now nr_rgn_out_edges is the number of region-exit edges from
1857 pred, and nr_out_edges will be the number of pred out edges
1858 not leaving the region. */
1859 nr_out_edges -= nr_rgn_out_edges;
1860 if (nr_rgn_out_edges > 0)
1861 prob[bb] += 0.9 * prob[BLOCK_TO_BB (pred)] / nr_out_edges;
1863 prob[bb] += prob[BLOCK_TO_BB (pred)] / nr_out_edges;
1864 nxt_in_edge = NEXT_IN (nxt_in_edge);
1866 while (fst_in_edge != nxt_in_edge);
1868 BITSET_ADD (dom[bb], bb, bbset_size);
1869 BITSET_DIFFER (pot_split[bb], ancestor_edges[bb], edgeset_size);
1871 if (sched_verbose >= 2)
1872 fprintf (dump, ";; bb_prob(%d, %d) = %3d\n", bb, BB_TO_BLOCK (bb), (int) (100.0 * prob[bb]));
1873 } /* compute_dom_prob_ps */
1875 /* Functions for target info. */
1877 /* Compute in BL the list of split-edges of bb_src relatively to bb_trg.
1878 Note that bb_trg dominates bb_src. */
1881 split_edges (bb_src, bb_trg, bl)
1886 int es = edgeset_size;
1887 edgeset src = (edgeset) xmalloc (es * sizeof (HOST_WIDE_INT));
1890 src[es] = (pot_split[bb_src])[es];
1891 BITSET_DIFFER (src, pot_split[bb_trg], edgeset_size);
1892 extract_bitlst (src, edgeset_size, bl);
1897 /* Find the valid candidate-source-blocks for the target block TRG, compute
1898 their probability, and check if they are speculative or not.
1899 For speculative sources, compute their update-blocks and split-blocks. */
1902 compute_trg_info (trg)
1905 register candidate *sp;
1907 int check_block, update_idx;
1908 int i, j, k, fst_edge, nxt_edge;
1910 /* Define some of the fields for the target bb as well. */
1911 sp = candidate_table + trg;
1913 sp->is_speculative = 0;
1916 for (i = trg + 1; i < current_nr_blocks; i++)
1918 sp = candidate_table + i;
1920 sp->is_valid = IS_DOMINATED (i, trg);
1923 sp->src_prob = GET_SRC_PROB (i, trg);
1924 sp->is_valid = (sp->src_prob >= MIN_PROBABILITY);
1929 split_edges (i, trg, &el);
1930 sp->is_speculative = (el.nr_members) ? 1 : 0;
1931 if (sp->is_speculative && !flag_schedule_speculative)
1937 sp->split_bbs.first_member = &bblst_table[bblst_last];
1938 sp->split_bbs.nr_members = el.nr_members;
1939 for (j = 0; j < el.nr_members; bblst_last++, j++)
1940 bblst_table[bblst_last] =
1941 TO_BLOCK (rgn_edges[el.first_member[j]]);
1942 sp->update_bbs.first_member = &bblst_table[bblst_last];
1944 for (j = 0; j < el.nr_members; j++)
1946 check_block = FROM_BLOCK (rgn_edges[el.first_member[j]]);
1947 fst_edge = nxt_edge = OUT_EDGES (check_block);
1950 for (k = 0; k < el.nr_members; k++)
1951 if (EDGE_TO_BIT (nxt_edge) == el.first_member[k])
1954 if (k >= el.nr_members)
1956 bblst_table[bblst_last++] = TO_BLOCK (nxt_edge);
1960 nxt_edge = NEXT_OUT (nxt_edge);
1962 while (fst_edge != nxt_edge);
1964 sp->update_bbs.nr_members = update_idx;
1969 sp->split_bbs.nr_members = sp->update_bbs.nr_members = 0;
1971 sp->is_speculative = 0;
1975 } /* compute_trg_info */
1978 /* Print candidates info, for debugging purposes. Callable from debugger. */
1984 if (!candidate_table[i].is_valid)
1987 if (candidate_table[i].is_speculative)
1990 fprintf (dump, "src b %d bb %d speculative \n", BB_TO_BLOCK (i), i);
1992 fprintf (dump, "split path: ");
1993 for (j = 0; j < candidate_table[i].split_bbs.nr_members; j++)
1995 int b = candidate_table[i].split_bbs.first_member[j];
1997 fprintf (dump, " %d ", b);
1999 fprintf (dump, "\n");
2001 fprintf (dump, "update path: ");
2002 for (j = 0; j < candidate_table[i].update_bbs.nr_members; j++)
2004 int b = candidate_table[i].update_bbs.first_member[j];
2006 fprintf (dump, " %d ", b);
2008 fprintf (dump, "\n");
2012 fprintf (dump, " src %d equivalent\n", BB_TO_BLOCK (i));
2017 /* Print candidates info, for debugging purposes. Callable from debugger. */
2020 debug_candidates (trg)
2025 fprintf (dump, "----------- candidate table: target: b=%d bb=%d ---\n",
2026 BB_TO_BLOCK (trg), trg);
2027 for (i = trg + 1; i < current_nr_blocks; i++)
2028 debug_candidate (i);
2032 /* Functions for speculative scheduing. */
2034 /* Return 0 if x is a set of a register alive in the beginning of one
2035 of the split-blocks of src, otherwise return 1. */
2038 check_live_1 (src, x)
2044 register rtx reg = SET_DEST (x);
2049 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
2050 || GET_CODE (reg) == SIGN_EXTRACT
2051 || GET_CODE (reg) == STRICT_LOW_PART)
2052 reg = XEXP (reg, 0);
2054 if (GET_CODE (reg) == PARALLEL
2055 && GET_MODE (reg) == BLKmode)
2058 for (i = XVECLEN (reg, 0) - 1; i >= 0; i--)
2059 if (check_live_1 (src, XVECEXP (reg, 0, i)))
2064 if (GET_CODE (reg) != REG)
2067 regno = REGNO (reg);
2069 if (regno < FIRST_PSEUDO_REGISTER && global_regs[regno])
2071 /* Global registers are assumed live. */
2076 if (regno < FIRST_PSEUDO_REGISTER)
2078 /* Check for hard registers. */
2079 int j = HARD_REGNO_NREGS (regno, GET_MODE (reg));
2082 for (i = 0; i < candidate_table[src].split_bbs.nr_members; i++)
2084 int b = candidate_table[src].split_bbs.first_member[i];
2086 if (REGNO_REG_SET_P (BASIC_BLOCK (b)->global_live_at_start,
2096 /* Check for psuedo registers. */
2097 for (i = 0; i < candidate_table[src].split_bbs.nr_members; i++)
2099 int b = candidate_table[src].split_bbs.first_member[i];
2101 if (REGNO_REG_SET_P (BASIC_BLOCK (b)->global_live_at_start, regno))
2113 /* If x is a set of a register R, mark that R is alive in the beginning
2114 of every update-block of src. */
2117 update_live_1 (src, x)
2123 register rtx reg = SET_DEST (x);
2128 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
2129 || GET_CODE (reg) == SIGN_EXTRACT
2130 || GET_CODE (reg) == STRICT_LOW_PART)
2131 reg = XEXP (reg, 0);
2133 if (GET_CODE (reg) == PARALLEL
2134 && GET_MODE (reg) == BLKmode)
2137 for (i = XVECLEN (reg, 0) - 1; i >= 0; i--)
2138 update_live_1 (src, XVECEXP (reg, 0, i));
2142 if (GET_CODE (reg) != REG)
2145 /* Global registers are always live, so the code below does not apply
2148 regno = REGNO (reg);
2150 if (regno >= FIRST_PSEUDO_REGISTER || !global_regs[regno])
2152 if (regno < FIRST_PSEUDO_REGISTER)
2154 int j = HARD_REGNO_NREGS (regno, GET_MODE (reg));
2157 for (i = 0; i < candidate_table[src].update_bbs.nr_members; i++)
2159 int b = candidate_table[src].update_bbs.first_member[i];
2161 SET_REGNO_REG_SET (BASIC_BLOCK (b)->global_live_at_start,
2168 for (i = 0; i < candidate_table[src].update_bbs.nr_members; i++)
2170 int b = candidate_table[src].update_bbs.first_member[i];
2172 SET_REGNO_REG_SET (BASIC_BLOCK (b)->global_live_at_start, regno);
2179 /* Return 1 if insn can be speculatively moved from block src to trg,
2180 otherwise return 0. Called before first insertion of insn to
2181 ready-list or before the scheduling. */
2184 check_live (insn, src)
2188 /* Find the registers set by instruction. */
2189 if (GET_CODE (PATTERN (insn)) == SET
2190 || GET_CODE (PATTERN (insn)) == CLOBBER)
2191 return check_live_1 (src, PATTERN (insn));
2192 else if (GET_CODE (PATTERN (insn)) == PARALLEL)
2195 for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--)
2196 if ((GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == SET
2197 || GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == CLOBBER)
2198 && !check_live_1 (src, XVECEXP (PATTERN (insn), 0, j)))
2208 /* Update the live registers info after insn was moved speculatively from
2209 block src to trg. */
2212 update_live (insn, src)
2216 /* Find the registers set by instruction. */
2217 if (GET_CODE (PATTERN (insn)) == SET
2218 || GET_CODE (PATTERN (insn)) == CLOBBER)
2219 update_live_1 (src, PATTERN (insn));
2220 else if (GET_CODE (PATTERN (insn)) == PARALLEL)
2223 for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--)
2224 if (GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == SET
2225 || GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == CLOBBER)
2226 update_live_1 (src, XVECEXP (PATTERN (insn), 0, j));
2230 /* Exception Free Loads:
2232 We define five classes of speculative loads: IFREE, IRISKY,
2233 PFREE, PRISKY, and MFREE.
2235 IFREE loads are loads that are proved to be exception-free, just
2236 by examining the load insn. Examples for such loads are loads
2237 from TOC and loads of global data.
2239 IRISKY loads are loads that are proved to be exception-risky,
2240 just by examining the load insn. Examples for such loads are
2241 volatile loads and loads from shared memory.
2243 PFREE loads are loads for which we can prove, by examining other
2244 insns, that they are exception-free. Currently, this class consists
2245 of loads for which we are able to find a "similar load", either in
2246 the target block, or, if only one split-block exists, in that split
2247 block. Load2 is similar to load1 if both have same single base
2248 register. We identify only part of the similar loads, by finding
2249 an insn upon which both load1 and load2 have a DEF-USE dependence.
2251 PRISKY loads are loads for which we can prove, by examining other
2252 insns, that they are exception-risky. Currently we have two proofs for
2253 such loads. The first proof detects loads that are probably guarded by a
2254 test on the memory address. This proof is based on the
2255 backward and forward data dependence information for the region.
2256 Let load-insn be the examined load.
2257 Load-insn is PRISKY iff ALL the following hold:
2259 - insn1 is not in the same block as load-insn
2260 - there is a DEF-USE dependence chain (insn1, ..., load-insn)
2261 - test-insn is either a compare or a branch, not in the same block
2263 - load-insn is reachable from test-insn
2264 - there is a DEF-USE dependence chain (insn1, ..., test-insn)
2266 This proof might fail when the compare and the load are fed
2267 by an insn not in the region. To solve this, we will add to this
2268 group all loads that have no input DEF-USE dependence.
2270 The second proof detects loads that are directly or indirectly
2271 fed by a speculative load. This proof is affected by the
2272 scheduling process. We will use the flag fed_by_spec_load.
2273 Initially, all insns have this flag reset. After a speculative
2274 motion of an insn, if insn is either a load, or marked as
2275 fed_by_spec_load, we will also mark as fed_by_spec_load every
2276 insn1 for which a DEF-USE dependence (insn, insn1) exists. A
2277 load which is fed_by_spec_load is also PRISKY.
2279 MFREE (maybe-free) loads are all the remaining loads. They may be
2280 exception-free, but we cannot prove it.
2282 Now, all loads in IFREE and PFREE classes are considered
2283 exception-free, while all loads in IRISKY and PRISKY classes are
2284 considered exception-risky. As for loads in the MFREE class,
2285 these are considered either exception-free or exception-risky,
2286 depending on whether we are pessimistic or optimistic. We have
2287 to take the pessimistic approach to assure the safety of
2288 speculative scheduling, but we can take the optimistic approach
2289 by invoking the -fsched_spec_load_dangerous option. */
2291 enum INSN_TRAP_CLASS
2293 TRAP_FREE = 0, IFREE = 1, PFREE_CANDIDATE = 2,
2294 PRISKY_CANDIDATE = 3, IRISKY = 4, TRAP_RISKY = 5
2297 #define WORST_CLASS(class1, class2) \
2298 ((class1 > class2) ? class1 : class2)
2300 /* Non-zero if block bb_to is equal to, or reachable from block bb_from. */
2301 #define IS_REACHABLE(bb_from, bb_to) \
2303 || IS_RGN_ENTRY (bb_from) \
2304 || (bitset_member (ancestor_edges[bb_to], \
2305 EDGE_TO_BIT (IN_EDGES (BB_TO_BLOCK (bb_from))), \
2308 /* Non-zero iff the address is comprised from at most 1 register. */
2309 #define CONST_BASED_ADDRESS_P(x) \
2310 (GET_CODE (x) == REG \
2311 || ((GET_CODE (x) == PLUS || GET_CODE (x) == MINUS \
2312 || (GET_CODE (x) == LO_SUM)) \
2313 && (GET_CODE (XEXP (x, 0)) == CONST_INT \
2314 || GET_CODE (XEXP (x, 1)) == CONST_INT)))
2316 /* Turns on the fed_by_spec_load flag for insns fed by load_insn. */
2319 set_spec_fed (load_insn)
2324 for (link = INSN_DEPEND (load_insn); link; link = XEXP (link, 1))
2325 if (GET_MODE (link) == VOIDmode)
2326 FED_BY_SPEC_LOAD (XEXP (link, 0)) = 1;
2327 } /* set_spec_fed */
2329 /* On the path from the insn to load_insn_bb, find a conditional
2330 branch depending on insn, that guards the speculative load. */
2333 find_conditional_protection (insn, load_insn_bb)
2339 /* Iterate through DEF-USE forward dependences. */
2340 for (link = INSN_DEPEND (insn); link; link = XEXP (link, 1))
2342 rtx next = XEXP (link, 0);
2343 if ((CONTAINING_RGN (BLOCK_NUM (next)) ==
2344 CONTAINING_RGN (BB_TO_BLOCK (load_insn_bb)))
2345 && IS_REACHABLE (INSN_BB (next), load_insn_bb)
2346 && load_insn_bb != INSN_BB (next)
2347 && GET_MODE (link) == VOIDmode
2348 && (GET_CODE (next) == JUMP_INSN
2349 || find_conditional_protection (next, load_insn_bb)))
2353 } /* find_conditional_protection */
2355 /* Returns 1 if the same insn1 that participates in the computation
2356 of load_insn's address is feeding a conditional branch that is
2357 guarding on load_insn. This is true if we find a the two DEF-USE
2359 insn1 -> ... -> conditional-branch
2360 insn1 -> ... -> load_insn,
2361 and if a flow path exist:
2362 insn1 -> ... -> conditional-branch -> ... -> load_insn,
2363 and if insn1 is on the path
2364 region-entry -> ... -> bb_trg -> ... load_insn.
2366 Locate insn1 by climbing on LOG_LINKS from load_insn.
2367 Locate the branch by following INSN_DEPEND from insn1. */
2370 is_conditionally_protected (load_insn, bb_src, bb_trg)
2376 for (link = LOG_LINKS (load_insn); link; link = XEXP (link, 1))
2378 rtx insn1 = XEXP (link, 0);
2380 /* Must be a DEF-USE dependence upon non-branch. */
2381 if (GET_MODE (link) != VOIDmode
2382 || GET_CODE (insn1) == JUMP_INSN)
2385 /* Must exist a path: region-entry -> ... -> bb_trg -> ... load_insn. */
2386 if (INSN_BB (insn1) == bb_src
2387 || (CONTAINING_RGN (BLOCK_NUM (insn1))
2388 != CONTAINING_RGN (BB_TO_BLOCK (bb_src)))
2389 || (!IS_REACHABLE (bb_trg, INSN_BB (insn1))
2390 && !IS_REACHABLE (INSN_BB (insn1), bb_trg)))
2393 /* Now search for the conditional-branch. */
2394 if (find_conditional_protection (insn1, bb_src))
2397 /* Recursive step: search another insn1, "above" current insn1. */
2398 return is_conditionally_protected (insn1, bb_src, bb_trg);
2401 /* The chain does not exist. */
2403 } /* is_conditionally_protected */
2405 /* Returns 1 if a clue for "similar load" 'insn2' is found, and hence
2406 load_insn can move speculatively from bb_src to bb_trg. All the
2407 following must hold:
2409 (1) both loads have 1 base register (PFREE_CANDIDATEs).
2410 (2) load_insn and load1 have a def-use dependence upon
2411 the same insn 'insn1'.
2412 (3) either load2 is in bb_trg, or:
2413 - there's only one split-block, and
2414 - load1 is on the escape path, and
2416 From all these we can conclude that the two loads access memory
2417 addresses that differ at most by a constant, and hence if moving
2418 load_insn would cause an exception, it would have been caused by
2422 is_pfree (load_insn, bb_src, bb_trg)
2427 register candidate *candp = candidate_table + bb_src;
2429 if (candp->split_bbs.nr_members != 1)
2430 /* Must have exactly one escape block. */
2433 for (back_link = LOG_LINKS (load_insn);
2434 back_link; back_link = XEXP (back_link, 1))
2436 rtx insn1 = XEXP (back_link, 0);
2438 if (GET_MODE (back_link) == VOIDmode)
2440 /* Found a DEF-USE dependence (insn1, load_insn). */
2443 for (fore_link = INSN_DEPEND (insn1);
2444 fore_link; fore_link = XEXP (fore_link, 1))
2446 rtx insn2 = XEXP (fore_link, 0);
2447 if (GET_MODE (fore_link) == VOIDmode)
2449 /* Found a DEF-USE dependence (insn1, insn2). */
2450 if (haifa_classify_insn (insn2) != PFREE_CANDIDATE)
2451 /* insn2 not guaranteed to be a 1 base reg load. */
2454 if (INSN_BB (insn2) == bb_trg)
2455 /* insn2 is the similar load, in the target block. */
2458 if (*(candp->split_bbs.first_member) == BLOCK_NUM (insn2))
2459 /* insn2 is a similar load, in a split-block. */
2466 /* Couldn't find a similar load. */
2470 /* Returns a class that insn with GET_DEST(insn)=x may belong to,
2471 as found by analyzing insn's expression. */
2474 may_trap_exp (x, is_store)
2482 code = GET_CODE (x);
2492 /* The insn uses memory: a volatile load. */
2493 if (MEM_VOLATILE_P (x))
2495 /* An exception-free load. */
2496 if (!may_trap_p (x))
2498 /* A load with 1 base register, to be further checked. */
2499 if (CONST_BASED_ADDRESS_P (XEXP (x, 0)))
2500 return PFREE_CANDIDATE;
2501 /* No info on the load, to be further checked. */
2502 return PRISKY_CANDIDATE;
2507 int i, insn_class = TRAP_FREE;
2509 /* Neither store nor load, check if it may cause a trap. */
2512 /* Recursive step: walk the insn... */
2513 fmt = GET_RTX_FORMAT (code);
2514 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2518 int tmp_class = may_trap_exp (XEXP (x, i), is_store);
2519 insn_class = WORST_CLASS (insn_class, tmp_class);
2521 else if (fmt[i] == 'E')
2524 for (j = 0; j < XVECLEN (x, i); j++)
2526 int tmp_class = may_trap_exp (XVECEXP (x, i, j), is_store);
2527 insn_class = WORST_CLASS (insn_class, tmp_class);
2528 if (insn_class == TRAP_RISKY || insn_class == IRISKY)
2532 if (insn_class == TRAP_RISKY || insn_class == IRISKY)
2537 } /* may_trap_exp */
2540 /* Classifies insn for the purpose of verifying that it can be
2541 moved speculatively, by examining it's patterns, returning:
2542 TRAP_RISKY: store, or risky non-load insn (e.g. division by variable).
2543 TRAP_FREE: non-load insn.
2544 IFREE: load from a globaly safe location.
2545 IRISKY: volatile load.
2546 PFREE_CANDIDATE, PRISKY_CANDIDATE: load that need to be checked for
2547 being either PFREE or PRISKY. */
2550 haifa_classify_insn (insn)
2553 rtx pat = PATTERN (insn);
2554 int tmp_class = TRAP_FREE;
2555 int insn_class = TRAP_FREE;
2558 if (GET_CODE (pat) == PARALLEL)
2560 int i, len = XVECLEN (pat, 0);
2562 for (i = len - 1; i >= 0; i--)
2564 code = GET_CODE (XVECEXP (pat, 0, i));
2568 /* Test if it is a 'store'. */
2569 tmp_class = may_trap_exp (XEXP (XVECEXP (pat, 0, i), 0), 1);
2572 /* Test if it is a store. */
2573 tmp_class = may_trap_exp (SET_DEST (XVECEXP (pat, 0, i)), 1);
2574 if (tmp_class == TRAP_RISKY)
2576 /* Test if it is a load. */
2578 WORST_CLASS (tmp_class,
2579 may_trap_exp (SET_SRC (XVECEXP (pat, 0, i)), 0));
2582 tmp_class = TRAP_RISKY;
2586 insn_class = WORST_CLASS (insn_class, tmp_class);
2587 if (insn_class == TRAP_RISKY || insn_class == IRISKY)
2593 code = GET_CODE (pat);
2597 /* Test if it is a 'store'. */
2598 tmp_class = may_trap_exp (XEXP (pat, 0), 1);
2601 /* Test if it is a store. */
2602 tmp_class = may_trap_exp (SET_DEST (pat), 1);
2603 if (tmp_class == TRAP_RISKY)
2605 /* Test if it is a load. */
2607 WORST_CLASS (tmp_class,
2608 may_trap_exp (SET_SRC (pat), 0));
2611 tmp_class = TRAP_RISKY;
2615 insn_class = tmp_class;
2620 } /* haifa_classify_insn */
2622 /* Return 1 if load_insn is prisky (i.e. if load_insn is fed by
2623 a load moved speculatively, or if load_insn is protected by
2624 a compare on load_insn's address). */
2627 is_prisky (load_insn, bb_src, bb_trg)
2631 if (FED_BY_SPEC_LOAD (load_insn))
2634 if (LOG_LINKS (load_insn) == NULL)
2635 /* Dependence may 'hide' out of the region. */
2638 if (is_conditionally_protected (load_insn, bb_src, bb_trg))
2644 /* Insn is a candidate to be moved speculatively from bb_src to bb_trg.
2645 Return 1 if insn is exception-free (and the motion is valid)
2649 is_exception_free (insn, bb_src, bb_trg)
2653 int insn_class = haifa_classify_insn (insn);
2655 /* Handle non-load insns. */
2666 if (!flag_schedule_speculative_load)
2668 IS_LOAD_INSN (insn) = 1;
2675 case PFREE_CANDIDATE:
2676 if (is_pfree (insn, bb_src, bb_trg))
2678 /* Don't 'break' here: PFREE-candidate is also PRISKY-candidate. */
2679 case PRISKY_CANDIDATE:
2680 if (!flag_schedule_speculative_load_dangerous
2681 || is_prisky (insn, bb_src, bb_trg))
2687 return flag_schedule_speculative_load_dangerous;
2688 } /* is_exception_free */
2691 /* Process an insn's memory dependencies. There are four kinds of
2694 (0) read dependence: read follows read
2695 (1) true dependence: read follows write
2696 (2) anti dependence: write follows read
2697 (3) output dependence: write follows write
2699 We are careful to build only dependencies which actually exist, and
2700 use transitivity to avoid building too many links. */
2702 /* Return the INSN_LIST containing INSN in LIST, or NULL
2703 if LIST does not contain INSN. */
2705 HAIFA_INLINE static rtx
2706 find_insn_list (insn, list)
2712 if (XEXP (list, 0) == insn)
2714 list = XEXP (list, 1);
2720 /* Return 1 if the pair (insn, x) is found in (LIST, LIST1), or 0
2723 HAIFA_INLINE static char
2724 find_insn_mem_list (insn, x, list, list1)
2730 if (XEXP (list, 0) == insn
2731 && XEXP (list1, 0) == x)
2733 list = XEXP (list, 1);
2734 list1 = XEXP (list1, 1);
2740 /* Compute the function units used by INSN. This caches the value
2741 returned by function_units_used. A function unit is encoded as the
2742 unit number if the value is non-negative and the compliment of a
2743 mask if the value is negative. A function unit index is the
2744 non-negative encoding. */
2746 HAIFA_INLINE static int
2750 register int unit = INSN_UNIT (insn);
2754 recog_memoized (insn);
2756 /* A USE insn, or something else we don't need to understand.
2757 We can't pass these directly to function_units_used because it will
2758 trigger a fatal error for unrecognizable insns. */
2759 if (INSN_CODE (insn) < 0)
2763 unit = function_units_used (insn);
2764 /* Increment non-negative values so we can cache zero. */
2768 /* We only cache 16 bits of the result, so if the value is out of
2769 range, don't cache it. */
2770 if (FUNCTION_UNITS_SIZE < HOST_BITS_PER_SHORT
2772 || (unit & ~((1 << (HOST_BITS_PER_SHORT - 1)) - 1)) == 0)
2773 INSN_UNIT (insn) = unit;
2775 return (unit > 0 ? unit - 1 : unit);
2778 /* Compute the blockage range for executing INSN on UNIT. This caches
2779 the value returned by the blockage_range_function for the unit.
2780 These values are encoded in an int where the upper half gives the
2781 minimum value and the lower half gives the maximum value. */
2783 HAIFA_INLINE static unsigned int
2784 blockage_range (unit, insn)
2788 unsigned int blockage = INSN_BLOCKAGE (insn);
2791 if ((int) UNIT_BLOCKED (blockage) != unit + 1)
2793 range = function_units[unit].blockage_range_function (insn);
2794 /* We only cache the blockage range for one unit and then only if
2796 if (HOST_BITS_PER_INT >= UNIT_BITS + 2 * BLOCKAGE_BITS)
2797 INSN_BLOCKAGE (insn) = ENCODE_BLOCKAGE (unit + 1, range);
2800 range = BLOCKAGE_RANGE (blockage);
2805 /* A vector indexed by function unit instance giving the last insn to use
2806 the unit. The value of the function unit instance index for unit U
2807 instance I is (U + I * FUNCTION_UNITS_SIZE). */
2808 static rtx unit_last_insn[FUNCTION_UNITS_SIZE * MAX_MULTIPLICITY];
2810 /* A vector indexed by function unit instance giving the minimum time when
2811 the unit will unblock based on the maximum blockage cost. */
2812 static int unit_tick[FUNCTION_UNITS_SIZE * MAX_MULTIPLICITY];
2814 /* A vector indexed by function unit number giving the number of insns
2815 that remain to use the unit. */
2816 static int unit_n_insns[FUNCTION_UNITS_SIZE];
2818 /* Reset the function unit state to the null state. */
2823 bzero ((char *) unit_last_insn, sizeof (unit_last_insn));
2824 bzero ((char *) unit_tick, sizeof (unit_tick));
2825 bzero ((char *) unit_n_insns, sizeof (unit_n_insns));
2828 /* Return the issue-delay of an insn. */
2830 HAIFA_INLINE static int
2831 insn_issue_delay (insn)
2835 int unit = insn_unit (insn);
2837 /* Efficiency note: in fact, we are working 'hard' to compute a
2838 value that was available in md file, and is not available in
2839 function_units[] structure. It would be nice to have this
2840 value there, too. */
2843 if (function_units[unit].blockage_range_function &&
2844 function_units[unit].blockage_function)
2845 delay = function_units[unit].blockage_function (insn, insn);
2848 for (i = 0, unit = ~unit; unit; i++, unit >>= 1)
2849 if ((unit & 1) != 0 && function_units[i].blockage_range_function
2850 && function_units[i].blockage_function)
2851 delay = MAX (delay, function_units[i].blockage_function (insn, insn));
2856 /* Return the actual hazard cost of executing INSN on the unit UNIT,
2857 instance INSTANCE at time CLOCK if the previous actual hazard cost
2860 HAIFA_INLINE static int
2861 actual_hazard_this_instance (unit, instance, insn, clock, cost)
2862 int unit, instance, clock, cost;
2865 int tick = unit_tick[instance]; /* Issue time of the last issued insn. */
2867 if (tick - clock > cost)
2869 /* The scheduler is operating forward, so unit's last insn is the
2870 executing insn and INSN is the candidate insn. We want a
2871 more exact measure of the blockage if we execute INSN at CLOCK
2872 given when we committed the execution of the unit's last insn.
2874 The blockage value is given by either the unit's max blockage
2875 constant, blockage range function, or blockage function. Use
2876 the most exact form for the given unit. */
2878 if (function_units[unit].blockage_range_function)
2880 if (function_units[unit].blockage_function)
2881 tick += (function_units[unit].blockage_function
2882 (unit_last_insn[instance], insn)
2883 - function_units[unit].max_blockage);
2885 tick += ((int) MAX_BLOCKAGE_COST (blockage_range (unit, insn))
2886 - function_units[unit].max_blockage);
2888 if (tick - clock > cost)
2889 cost = tick - clock;
2894 /* Record INSN as having begun execution on the units encoded by UNIT at
2897 HAIFA_INLINE static void
2898 schedule_unit (unit, insn, clock)
2906 int instance = unit;
2907 #if MAX_MULTIPLICITY > 1
2908 /* Find the first free instance of the function unit and use that
2909 one. We assume that one is free. */
2910 for (i = function_units[unit].multiplicity - 1; i > 0; i--)
2912 if (!actual_hazard_this_instance (unit, instance, insn, clock, 0))
2914 instance += FUNCTION_UNITS_SIZE;
2917 unit_last_insn[instance] = insn;
2918 unit_tick[instance] = (clock + function_units[unit].max_blockage);
2921 for (i = 0, unit = ~unit; unit; i++, unit >>= 1)
2922 if ((unit & 1) != 0)
2923 schedule_unit (i, insn, clock);
2926 /* Return the actual hazard cost of executing INSN on the units encoded by
2927 UNIT at time CLOCK if the previous actual hazard cost was COST. */
2929 HAIFA_INLINE static int
2930 actual_hazard (unit, insn, clock, cost)
2931 int unit, clock, cost;
2938 /* Find the instance of the function unit with the minimum hazard. */
2939 int instance = unit;
2940 int best_cost = actual_hazard_this_instance (unit, instance, insn,
2942 #if MAX_MULTIPLICITY > 1
2945 if (best_cost > cost)
2947 for (i = function_units[unit].multiplicity - 1; i > 0; i--)
2949 instance += FUNCTION_UNITS_SIZE;
2950 this_cost = actual_hazard_this_instance (unit, instance, insn,
2952 if (this_cost < best_cost)
2954 best_cost = this_cost;
2955 if (this_cost <= cost)
2961 cost = MAX (cost, best_cost);
2964 for (i = 0, unit = ~unit; unit; i++, unit >>= 1)
2965 if ((unit & 1) != 0)
2966 cost = actual_hazard (i, insn, clock, cost);
2971 /* Return the potential hazard cost of executing an instruction on the
2972 units encoded by UNIT if the previous potential hazard cost was COST.
2973 An insn with a large blockage time is chosen in preference to one
2974 with a smaller time; an insn that uses a unit that is more likely
2975 to be used is chosen in preference to one with a unit that is less
2976 used. We are trying to minimize a subsequent actual hazard. */
2978 HAIFA_INLINE static int
2979 potential_hazard (unit, insn, cost)
2984 unsigned int minb, maxb;
2988 minb = maxb = function_units[unit].max_blockage;
2991 if (function_units[unit].blockage_range_function)
2993 maxb = minb = blockage_range (unit, insn);
2994 maxb = MAX_BLOCKAGE_COST (maxb);
2995 minb = MIN_BLOCKAGE_COST (minb);
3000 /* Make the number of instructions left dominate. Make the
3001 minimum delay dominate the maximum delay. If all these
3002 are the same, use the unit number to add an arbitrary
3003 ordering. Other terms can be added. */
3004 ncost = minb * 0x40 + maxb;
3005 ncost *= (unit_n_insns[unit] - 1) * 0x1000 + unit;
3012 for (i = 0, unit = ~unit; unit; i++, unit >>= 1)
3013 if ((unit & 1) != 0)
3014 cost = potential_hazard (i, insn, cost);
3019 /* Compute cost of executing INSN given the dependence LINK on the insn USED.
3020 This is the number of cycles between instruction issue and
3021 instruction results. */
3023 HAIFA_INLINE static int
3024 insn_cost (insn, link, used)
3025 rtx insn, link, used;
3027 register int cost = INSN_COST (insn);
3031 recog_memoized (insn);
3033 /* A USE insn, or something else we don't need to understand.
3034 We can't pass these directly to result_ready_cost because it will
3035 trigger a fatal error for unrecognizable insns. */
3036 if (INSN_CODE (insn) < 0)
3038 INSN_COST (insn) = 1;
3043 cost = result_ready_cost (insn);
3048 INSN_COST (insn) = cost;
3052 /* In this case estimate cost without caring how insn is used. */
3053 if (link == 0 && used == 0)
3056 /* A USE insn should never require the value used to be computed. This
3057 allows the computation of a function's result and parameter values to
3058 overlap the return and call. */
3059 recog_memoized (used);
3060 if (INSN_CODE (used) < 0)
3061 LINK_COST_FREE (link) = 1;
3063 /* If some dependencies vary the cost, compute the adjustment. Most
3064 commonly, the adjustment is complete: either the cost is ignored
3065 (in the case of an output- or anti-dependence), or the cost is
3066 unchanged. These values are cached in the link as LINK_COST_FREE
3067 and LINK_COST_ZERO. */
3069 if (LINK_COST_FREE (link))
3072 else if (!LINK_COST_ZERO (link))
3076 ADJUST_COST (used, link, insn, ncost);
3079 LINK_COST_FREE (link) = 1;
3083 LINK_COST_ZERO (link) = 1;
3090 /* Compute the priority number for INSN. */
3099 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
3102 if ((this_priority = INSN_PRIORITY (insn)) == 0)
3104 if (INSN_DEPEND (insn) == 0)
3105 this_priority = insn_cost (insn, 0, 0);
3107 for (link = INSN_DEPEND (insn); link; link = XEXP (link, 1))
3112 if (RTX_INTEGRATED_P (link))
3115 next = XEXP (link, 0);
3117 /* Critical path is meaningful in block boundaries only. */
3118 if (BLOCK_NUM (next) != BLOCK_NUM (insn))
3121 next_priority = insn_cost (insn, link, next) + priority (next);
3122 if (next_priority > this_priority)
3123 this_priority = next_priority;
3125 INSN_PRIORITY (insn) = this_priority;
3127 return this_priority;
3131 /* Remove all INSN_LISTs and EXPR_LISTs from the pending lists and add
3132 them to the unused_*_list variables, so that they can be reused. */
3135 free_pending_lists ()
3139 for (bb = 0; bb < current_nr_blocks; bb++)
3141 free_INSN_LIST_list (&bb_deps[bb].pending_read_insns);
3142 free_INSN_LIST_list (&bb_deps[bb].pending_write_insns);
3143 free_EXPR_LIST_list (&bb_deps[bb].pending_read_mems);
3144 free_EXPR_LIST_list (&bb_deps[bb].pending_write_mems);
3148 /* Add an INSN and MEM reference pair to a pending INSN_LIST and MEM_LIST.
3149 The MEM is a memory reference contained within INSN, which we are saving
3150 so that we can do memory aliasing on it. */
3153 add_insn_mem_dependence (deps, insn_list, mem_list, insn, mem)
3155 rtx *insn_list, *mem_list, insn, mem;
3159 link = alloc_INSN_LIST (insn, *insn_list);
3162 link = alloc_EXPR_LIST (VOIDmode, mem, *mem_list);
3165 deps->pending_lists_length++;
3168 /* Make a dependency between every memory reference on the pending lists
3169 and INSN, thus flushing the pending lists. If ONLY_WRITE, don't flush
3173 flush_pending_lists (deps, insn, only_write)
3181 while (deps->pending_read_insns && ! only_write)
3183 add_dependence (insn, XEXP (deps->pending_read_insns, 0),
3186 link = deps->pending_read_insns;
3187 deps->pending_read_insns = XEXP (deps->pending_read_insns, 1);
3188 free_INSN_LIST_node (link);
3190 link = deps->pending_read_mems;
3191 deps->pending_read_mems = XEXP (deps->pending_read_mems, 1);
3192 free_EXPR_LIST_node (link);
3194 while (deps->pending_write_insns)
3196 add_dependence (insn, XEXP (deps->pending_write_insns, 0),
3199 link = deps->pending_write_insns;
3200 deps->pending_write_insns = XEXP (deps->pending_write_insns, 1);
3201 free_INSN_LIST_node (link);
3203 link = deps->pending_write_mems;
3204 deps->pending_write_mems = XEXP (deps->pending_write_mems, 1);
3205 free_EXPR_LIST_node (link);
3207 deps->pending_lists_length = 0;
3209 /* last_pending_memory_flush is now a list of insns. */
3210 for (u = deps->last_pending_memory_flush; u; u = XEXP (u, 1))
3211 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
3213 free_INSN_LIST_list (&deps->last_pending_memory_flush);
3214 deps->last_pending_memory_flush = alloc_INSN_LIST (insn, NULL_RTX);
3217 /* Analyze a single SET, CLOBBER, PRE_DEC, POST_DEC, PRE_INC or POST_INC
3218 rtx, X, creating all dependencies generated by the write to the
3219 destination of X, and reads of everything mentioned. */
3222 sched_analyze_1 (deps, x, insn)
3228 register rtx dest = XEXP (x, 0);
3229 enum rtx_code code = GET_CODE (x);
3234 if (GET_CODE (dest) == PARALLEL
3235 && GET_MODE (dest) == BLKmode)
3238 for (i = XVECLEN (dest, 0) - 1; i >= 0; i--)
3239 sched_analyze_1 (deps, XVECEXP (dest, 0, i), insn);
3240 if (GET_CODE (x) == SET)
3241 sched_analyze_2 (deps, SET_SRC (x), insn);
3245 while (GET_CODE (dest) == STRICT_LOW_PART || GET_CODE (dest) == SUBREG
3246 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SIGN_EXTRACT)
3248 if (GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SIGN_EXTRACT)
3250 /* The second and third arguments are values read by this insn. */
3251 sched_analyze_2 (deps, XEXP (dest, 1), insn);
3252 sched_analyze_2 (deps, XEXP (dest, 2), insn);
3254 dest = XEXP (dest, 0);
3257 if (GET_CODE (dest) == REG)
3261 regno = REGNO (dest);
3263 /* A hard reg in a wide mode may really be multiple registers.
3264 If so, mark all of them just like the first. */
3265 if (regno < FIRST_PSEUDO_REGISTER)
3267 i = HARD_REGNO_NREGS (regno, GET_MODE (dest));
3273 for (u = deps->reg_last_uses[r]; u; u = XEXP (u, 1))
3274 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
3276 for (u = deps->reg_last_sets[r]; u; u = XEXP (u, 1))
3277 add_dependence (insn, XEXP (u, 0), REG_DEP_OUTPUT);
3279 /* Clobbers need not be ordered with respect to one
3280 another, but sets must be ordered with respect to a
3284 free_INSN_LIST_list (&deps->reg_last_uses[r]);
3285 for (u = deps->reg_last_clobbers[r]; u; u = XEXP (u, 1))
3286 add_dependence (insn, XEXP (u, 0), REG_DEP_OUTPUT);
3287 SET_REGNO_REG_SET (reg_pending_sets, r);
3290 SET_REGNO_REG_SET (reg_pending_clobbers, r);
3292 /* Function calls clobber all call_used regs. */
3293 if (global_regs[r] || (code == SET && call_used_regs[r]))
3294 for (u = deps->last_function_call; u; u = XEXP (u, 1))
3295 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
3302 for (u = deps->reg_last_uses[regno]; u; u = XEXP (u, 1))
3303 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
3305 for (u = deps->reg_last_sets[regno]; u; u = XEXP (u, 1))
3306 add_dependence (insn, XEXP (u, 0), REG_DEP_OUTPUT);
3310 free_INSN_LIST_list (&deps->reg_last_uses[regno]);
3311 for (u = deps->reg_last_clobbers[regno]; u; u = XEXP (u, 1))
3312 add_dependence (insn, XEXP (u, 0), REG_DEP_OUTPUT);
3313 SET_REGNO_REG_SET (reg_pending_sets, regno);
3316 SET_REGNO_REG_SET (reg_pending_clobbers, regno);
3318 /* Pseudos that are REG_EQUIV to something may be replaced
3319 by that during reloading. We need only add dependencies for
3320 the address in the REG_EQUIV note. */
3321 if (!reload_completed
3322 && reg_known_equiv_p[regno]
3323 && GET_CODE (reg_known_value[regno]) == MEM)
3324 sched_analyze_2 (deps, XEXP (reg_known_value[regno], 0), insn);
3326 /* Don't let it cross a call after scheduling if it doesn't
3327 already cross one. */
3329 if (REG_N_CALLS_CROSSED (regno) == 0)
3330 for (u = deps->last_function_call; u; u = XEXP (u, 1))
3331 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
3334 else if (GET_CODE (dest) == MEM)
3336 /* Writing memory. */
3338 if (deps->pending_lists_length > 32)
3340 /* Flush all pending reads and writes to prevent the pending lists
3341 from getting any larger. Insn scheduling runs too slowly when
3342 these lists get long. The number 32 was chosen because it
3343 seems like a reasonable number. When compiling GCC with itself,
3344 this flush occurs 8 times for sparc, and 10 times for m88k using
3346 flush_pending_lists (deps, insn, 0);
3351 rtx pending, pending_mem;
3353 pending = deps->pending_read_insns;
3354 pending_mem = deps->pending_read_mems;
3357 if (anti_dependence (XEXP (pending_mem, 0), dest))
3358 add_dependence (insn, XEXP (pending, 0), REG_DEP_ANTI);
3360 pending = XEXP (pending, 1);
3361 pending_mem = XEXP (pending_mem, 1);
3364 pending = deps->pending_write_insns;
3365 pending_mem = deps->pending_write_mems;
3368 if (output_dependence (XEXP (pending_mem, 0), dest))
3369 add_dependence (insn, XEXP (pending, 0), REG_DEP_OUTPUT);
3371 pending = XEXP (pending, 1);
3372 pending_mem = XEXP (pending_mem, 1);
3375 for (u = deps->last_pending_memory_flush; u; u = XEXP (u, 1))
3376 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
3378 add_insn_mem_dependence (deps, &deps->pending_write_insns,
3379 &deps->pending_write_mems, insn, dest);
3381 sched_analyze_2 (deps, XEXP (dest, 0), insn);
3384 /* Analyze reads. */
3385 if (GET_CODE (x) == SET)
3386 sched_analyze_2 (deps, SET_SRC (x), insn);
3389 /* Analyze the uses of memory and registers in rtx X in INSN. */
3392 sched_analyze_2 (deps, x, insn)
3399 register enum rtx_code code;
3400 register const char *fmt;
3405 code = GET_CODE (x);
3414 /* Ignore constants. Note that we must handle CONST_DOUBLE here
3415 because it may have a cc0_rtx in its CONST_DOUBLE_CHAIN field, but
3416 this does not mean that this insn is using cc0. */
3424 /* User of CC0 depends on immediately preceding insn. */
3425 SCHED_GROUP_P (insn) = 1;
3427 /* There may be a note before this insn now, but all notes will
3428 be removed before we actually try to schedule the insns, so
3429 it won't cause a problem later. We must avoid it here though. */
3430 prev = prev_nonnote_insn (insn);
3432 /* Make a copy of all dependencies on the immediately previous insn,
3433 and add to this insn. This is so that all the dependencies will
3434 apply to the group. Remove an explicit dependence on this insn
3435 as SCHED_GROUP_P now represents it. */
3437 if (find_insn_list (prev, LOG_LINKS (insn)))
3438 remove_dependence (insn, prev);
3440 for (link = LOG_LINKS (prev); link; link = XEXP (link, 1))
3441 add_dependence (insn, XEXP (link, 0), REG_NOTE_KIND (link));
3450 int regno = REGNO (x);
3451 if (regno < FIRST_PSEUDO_REGISTER)
3455 i = HARD_REGNO_NREGS (regno, GET_MODE (x));
3459 deps->reg_last_uses[r]
3460 = alloc_INSN_LIST (insn, deps->reg_last_uses[r]);
3462 for (u = deps->reg_last_sets[r]; u; u = XEXP (u, 1))
3463 add_dependence (insn, XEXP (u, 0), 0);
3465 /* ??? This should never happen. */
3466 for (u = deps->reg_last_clobbers[r]; u; u = XEXP (u, 1))
3467 add_dependence (insn, XEXP (u, 0), 0);
3469 if (call_used_regs[r] || global_regs[r])
3470 /* Function calls clobber all call_used regs. */
3471 for (u = deps->last_function_call; u; u = XEXP (u, 1))
3472 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
3477 deps->reg_last_uses[regno]
3478 = alloc_INSN_LIST (insn, deps->reg_last_uses[regno]);
3480 for (u = deps->reg_last_sets[regno]; u; u = XEXP (u, 1))
3481 add_dependence (insn, XEXP (u, 0), 0);
3483 /* ??? This should never happen. */
3484 for (u = deps->reg_last_clobbers[regno]; u; u = XEXP (u, 1))
3485 add_dependence (insn, XEXP (u, 0), 0);
3487 /* Pseudos that are REG_EQUIV to something may be replaced
3488 by that during reloading. We need only add dependencies for
3489 the address in the REG_EQUIV note. */
3490 if (!reload_completed
3491 && reg_known_equiv_p[regno]
3492 && GET_CODE (reg_known_value[regno]) == MEM)
3493 sched_analyze_2 (deps, XEXP (reg_known_value[regno], 0), insn);
3495 /* If the register does not already cross any calls, then add this
3496 insn to the sched_before_next_call list so that it will still
3497 not cross calls after scheduling. */
3498 if (REG_N_CALLS_CROSSED (regno) == 0)
3499 add_dependence (deps->sched_before_next_call, insn,
3507 /* Reading memory. */
3509 rtx pending, pending_mem;
3511 pending = deps->pending_read_insns;
3512 pending_mem = deps->pending_read_mems;
3515 if (read_dependence (XEXP (pending_mem, 0), x))
3516 add_dependence (insn, XEXP (pending, 0), REG_DEP_ANTI);
3518 pending = XEXP (pending, 1);
3519 pending_mem = XEXP (pending_mem, 1);
3522 pending = deps->pending_write_insns;
3523 pending_mem = deps->pending_write_mems;
3526 if (true_dependence (XEXP (pending_mem, 0), VOIDmode,
3528 add_dependence (insn, XEXP (pending, 0), 0);
3530 pending = XEXP (pending, 1);
3531 pending_mem = XEXP (pending_mem, 1);
3534 for (u = deps->last_pending_memory_flush; u; u = XEXP (u, 1))
3535 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
3537 /* Always add these dependencies to pending_reads, since
3538 this insn may be followed by a write. */
3539 add_insn_mem_dependence (deps, &deps->pending_read_insns,
3540 &deps->pending_read_mems, insn, x);
3542 /* Take advantage of tail recursion here. */
3543 sched_analyze_2 (deps, XEXP (x, 0), insn);
3547 /* Force pending stores to memory in case a trap handler needs them. */
3549 flush_pending_lists (deps, insn, 1);
3554 case UNSPEC_VOLATILE:
3558 /* Traditional and volatile asm instructions must be considered to use
3559 and clobber all hard registers, all pseudo-registers and all of
3560 memory. So must TRAP_IF and UNSPEC_VOLATILE operations.
3562 Consider for instance a volatile asm that changes the fpu rounding
3563 mode. An insn should not be moved across this even if it only uses
3564 pseudo-regs because it might give an incorrectly rounded result. */
3565 if (code != ASM_OPERANDS || MEM_VOLATILE_P (x))
3567 int max_reg = max_reg_num ();
3568 for (i = 0; i < max_reg; i++)
3570 for (u = deps->reg_last_uses[i]; u; u = XEXP (u, 1))
3571 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
3572 free_INSN_LIST_list (&deps->reg_last_uses[i]);
3574 for (u = deps->reg_last_sets[i]; u; u = XEXP (u, 1))
3575 add_dependence (insn, XEXP (u, 0), 0);
3577 for (u = deps->reg_last_clobbers[i]; u; u = XEXP (u, 1))
3578 add_dependence (insn, XEXP (u, 0), 0);
3580 reg_pending_sets_all = 1;
3582 flush_pending_lists (deps, insn, 0);
3585 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
3586 We can not just fall through here since then we would be confused
3587 by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
3588 traditional asms unlike their normal usage. */
3590 if (code == ASM_OPERANDS)
3592 for (j = 0; j < ASM_OPERANDS_INPUT_LENGTH (x); j++)
3593 sched_analyze_2 (deps, ASM_OPERANDS_INPUT (x, j), insn);
3603 /* These both read and modify the result. We must handle them as writes
3604 to get proper dependencies for following instructions. We must handle
3605 them as reads to get proper dependencies from this to previous
3606 instructions. Thus we need to pass them to both sched_analyze_1
3607 and sched_analyze_2. We must call sched_analyze_2 first in order
3608 to get the proper antecedent for the read. */
3609 sched_analyze_2 (deps, XEXP (x, 0), insn);
3610 sched_analyze_1 (deps, x, insn);
3617 /* Other cases: walk the insn. */
3618 fmt = GET_RTX_FORMAT (code);
3619 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3622 sched_analyze_2 (deps, XEXP (x, i), insn);
3623 else if (fmt[i] == 'E')
3624 for (j = 0; j < XVECLEN (x, i); j++)
3625 sched_analyze_2 (deps, XVECEXP (x, i, j), insn);
3629 /* Analyze an INSN with pattern X to find all dependencies. */
3632 sched_analyze_insn (deps, x, insn, loop_notes)
3637 register RTX_CODE code = GET_CODE (x);
3639 int maxreg = max_reg_num ();
3642 if (code == SET || code == CLOBBER)
3643 sched_analyze_1 (deps, x, insn);
3644 else if (code == PARALLEL)
3647 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
3649 code = GET_CODE (XVECEXP (x, 0, i));
3650 if (code == SET || code == CLOBBER)
3651 sched_analyze_1 (deps, XVECEXP (x, 0, i), insn);
3653 sched_analyze_2 (deps, XVECEXP (x, 0, i), insn);
3657 sched_analyze_2 (deps, x, insn);
3659 /* Mark registers CLOBBERED or used by called function. */
3660 if (GET_CODE (insn) == CALL_INSN)
3661 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
3663 if (GET_CODE (XEXP (link, 0)) == CLOBBER)
3664 sched_analyze_1 (deps, XEXP (link, 0), insn);
3666 sched_analyze_2 (deps, XEXP (link, 0), insn);
3669 /* If there is a {LOOP,EHREGION}_{BEG,END} note in the middle of a basic
3670 block, then we must be sure that no instructions are scheduled across it.
3671 Otherwise, the reg_n_refs info (which depends on loop_depth) would
3672 become incorrect. */
3676 int max_reg = max_reg_num ();
3677 int schedule_barrier_found = 0;
3680 /* Update loop_notes with any notes from this insn. Also determine
3681 if any of the notes on the list correspond to instruction scheduling
3682 barriers (loop, eh & setjmp notes, but not range notes. */
3684 while (XEXP (link, 1))
3686 if (INTVAL (XEXP (link, 0)) == NOTE_INSN_LOOP_BEG
3687 || INTVAL (XEXP (link, 0)) == NOTE_INSN_LOOP_END
3688 || INTVAL (XEXP (link, 0)) == NOTE_INSN_EH_REGION_BEG
3689 || INTVAL (XEXP (link, 0)) == NOTE_INSN_EH_REGION_END
3690 || INTVAL (XEXP (link, 0)) == NOTE_INSN_SETJMP)
3691 schedule_barrier_found = 1;
3693 link = XEXP (link, 1);
3695 XEXP (link, 1) = REG_NOTES (insn);
3696 REG_NOTES (insn) = loop_notes;
3698 /* Add dependencies if a scheduling barrier was found. */
3699 if (schedule_barrier_found)
3701 for (i = 0; i < max_reg; i++)
3704 for (u = deps->reg_last_uses[i]; u; u = XEXP (u, 1))
3705 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
3706 free_INSN_LIST_list (&deps->reg_last_uses[i]);
3708 for (u = deps->reg_last_sets[i]; u; u = XEXP (u, 1))
3709 add_dependence (insn, XEXP (u, 0), 0);
3711 for (u = deps->reg_last_clobbers[i]; u; u = XEXP (u, 1))
3712 add_dependence (insn, XEXP (u, 0), 0);
3714 reg_pending_sets_all = 1;
3716 flush_pending_lists (deps, insn, 0);
3721 /* Accumulate clobbers until the next set so that it will be output dependent
3722 on all of them. At the next set we can clear the clobber list, since
3723 subsequent sets will be output dependent on it. */
3724 EXECUTE_IF_SET_IN_REG_SET
3725 (reg_pending_sets, 0, i,
3727 free_INSN_LIST_list (&deps->reg_last_sets[i]);
3728 free_INSN_LIST_list (&deps->reg_last_clobbers[i]);
3729 deps->reg_last_sets[i] = alloc_INSN_LIST (insn, NULL_RTX);
3731 EXECUTE_IF_SET_IN_REG_SET
3732 (reg_pending_clobbers, 0, i,
3734 deps->reg_last_clobbers[i]
3735 = alloc_INSN_LIST (insn, deps->reg_last_clobbers[i]);
3737 CLEAR_REG_SET (reg_pending_sets);
3738 CLEAR_REG_SET (reg_pending_clobbers);
3740 if (reg_pending_sets_all)
3742 for (i = 0; i < maxreg; i++)
3744 free_INSN_LIST_list (&deps->reg_last_sets[i]);
3745 free_INSN_LIST_list (&deps->reg_last_clobbers[i]);
3746 deps->reg_last_sets[i] = alloc_INSN_LIST (insn, NULL_RTX);
3749 reg_pending_sets_all = 0;
3752 /* Handle function calls and function returns created by the epilogue
3754 if (GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN)
3759 /* When scheduling instructions, we make sure calls don't lose their
3760 accompanying USE insns by depending them one on another in order.
3762 Also, we must do the same thing for returns created by the epilogue
3763 threading code. Note this code works only in this special case,
3764 because other passes make no guarantee that they will never emit
3765 an instruction between a USE and a RETURN. There is such a guarantee
3766 for USE instructions immediately before a call. */
3768 prev_dep_insn = insn;
3769 dep_insn = PREV_INSN (insn);
3770 while (GET_CODE (dep_insn) == INSN
3771 && GET_CODE (PATTERN (dep_insn)) == USE
3772 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == REG)
3774 SCHED_GROUP_P (prev_dep_insn) = 1;
3776 /* Make a copy of all dependencies on dep_insn, and add to insn.
3777 This is so that all of the dependencies will apply to the
3780 for (link = LOG_LINKS (dep_insn); link; link = XEXP (link, 1))
3781 add_dependence (insn, XEXP (link, 0), REG_NOTE_KIND (link));
3783 prev_dep_insn = dep_insn;
3784 dep_insn = PREV_INSN (dep_insn);
3789 /* Analyze every insn between HEAD and TAIL inclusive, creating LOG_LINKS
3790 for every dependency. */
3793 sched_analyze (deps, head, tail)
3801 for (insn = head;; insn = NEXT_INSN (insn))
3803 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN)
3805 /* Clear out the stale LOG_LINKS from flow. */
3806 free_INSN_LIST_list (&LOG_LINKS (insn));
3808 /* Make each JUMP_INSN a scheduling barrier for memory
3810 if (GET_CODE (insn) == JUMP_INSN)
3811 deps->last_pending_memory_flush
3812 = alloc_INSN_LIST (insn, deps->last_pending_memory_flush);
3813 sched_analyze_insn (deps, PATTERN (insn), insn, loop_notes);
3816 else if (GET_CODE (insn) == CALL_INSN)
3821 CANT_MOVE (insn) = 1;
3823 /* Clear out the stale LOG_LINKS from flow. */
3824 free_INSN_LIST_list (&LOG_LINKS (insn));
3826 /* Any instruction using a hard register which may get clobbered
3827 by a call needs to be marked as dependent on this call.
3828 This prevents a use of a hard return reg from being moved
3829 past a void call (i.e. it does not explicitly set the hard
3832 /* If this call is followed by a NOTE_INSN_SETJMP, then assume that
3833 all registers, not just hard registers, may be clobbered by this
3836 /* Insn, being a CALL_INSN, magically depends on
3837 `last_function_call' already. */
3839 if (NEXT_INSN (insn) && GET_CODE (NEXT_INSN (insn)) == NOTE
3840 && NOTE_LINE_NUMBER (NEXT_INSN (insn)) == NOTE_INSN_SETJMP)
3842 int max_reg = max_reg_num ();
3843 for (i = 0; i < max_reg; i++)
3845 for (u = deps->reg_last_uses[i]; u; u = XEXP (u, 1))
3846 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
3847 free_INSN_LIST_list (&deps->reg_last_uses[i]);
3849 for (u = deps->reg_last_sets[i]; u; u = XEXP (u, 1))
3850 add_dependence (insn, XEXP (u, 0), 0);
3852 for (u = deps->reg_last_clobbers[i]; u; u = XEXP (u, 1))
3853 add_dependence (insn, XEXP (u, 0), 0);
3855 reg_pending_sets_all = 1;
3857 /* Add a pair of REG_SAVE_NOTEs which we will later
3858 convert back into a NOTE_INSN_SETJMP note. See
3859 reemit_notes for why we use a pair of NOTEs. */
3860 REG_NOTES (insn) = alloc_EXPR_LIST (REG_SAVE_NOTE,
3863 REG_NOTES (insn) = alloc_EXPR_LIST (REG_SAVE_NOTE,
3864 GEN_INT (NOTE_INSN_SETJMP),
3869 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3870 if (call_used_regs[i] || global_regs[i])
3872 for (u = deps->reg_last_uses[i]; u; u = XEXP (u, 1))
3873 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
3875 for (u = deps->reg_last_sets[i]; u; u = XEXP (u, 1))
3876 add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI);
3878 SET_REGNO_REG_SET (reg_pending_clobbers, i);
3882 /* For each insn which shouldn't cross a call, add a dependence
3883 between that insn and this call insn. */
3884 x = LOG_LINKS (deps->sched_before_next_call);
3887 add_dependence (insn, XEXP (x, 0), REG_DEP_ANTI);
3890 free_INSN_LIST_list (&LOG_LINKS (deps->sched_before_next_call));
3892 sched_analyze_insn (deps, PATTERN (insn), insn, loop_notes);
3895 /* In the absence of interprocedural alias analysis, we must flush
3896 all pending reads and writes, and start new dependencies starting
3897 from here. But only flush writes for constant calls (which may
3898 be passed a pointer to something we haven't written yet). */
3899 flush_pending_lists (deps, insn, CONST_CALL_P (insn));
3901 /* Depend this function call (actually, the user of this
3902 function call) on all hard register clobberage. */
3904 /* last_function_call is now a list of insns. */
3905 free_INSN_LIST_list (&deps->last_function_call);
3906 deps->last_function_call = alloc_INSN_LIST (insn, NULL_RTX);
3909 /* See comments on reemit_notes as to why we do this.
3910 ??? Actually, the reemit_notes just say what is done, not why. */
3912 else if (GET_CODE (insn) == NOTE
3913 && (NOTE_LINE_NUMBER (insn) == NOTE_INSN_RANGE_START
3914 || NOTE_LINE_NUMBER (insn) == NOTE_INSN_RANGE_END))
3916 loop_notes = alloc_EXPR_LIST (REG_SAVE_NOTE, NOTE_RANGE_INFO (insn),
3918 loop_notes = alloc_EXPR_LIST (REG_SAVE_NOTE,
3919 GEN_INT (NOTE_LINE_NUMBER (insn)),
3922 else if (GET_CODE (insn) == NOTE
3923 && (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG
3924 || NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END
3925 || NOTE_LINE_NUMBER (insn) == NOTE_INSN_EH_REGION_BEG
3926 || NOTE_LINE_NUMBER (insn) == NOTE_INSN_EH_REGION_END
3927 || (NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP
3928 && GET_CODE (PREV_INSN (insn)) != CALL_INSN)))
3932 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_EH_REGION_BEG
3933 || NOTE_LINE_NUMBER (insn) == NOTE_INSN_EH_REGION_END)
3934 rtx_region = GEN_INT (NOTE_EH_HANDLER (insn));
3936 rtx_region = GEN_INT (0);
3938 loop_notes = alloc_EXPR_LIST (REG_SAVE_NOTE,
3941 loop_notes = alloc_EXPR_LIST (REG_SAVE_NOTE,
3942 GEN_INT (NOTE_LINE_NUMBER (insn)),
3944 CONST_CALL_P (loop_notes) = CONST_CALL_P (insn);
3953 /* Macros and functions for keeping the priority queue sorted, and
3954 dealing with queueing and dequeueing of instructions. */
3956 #define SCHED_SORT(READY, N_READY) \
3957 do { if ((N_READY) == 2) \
3958 swap_sort (READY, N_READY); \
3959 else if ((N_READY) > 2) \
3960 qsort (READY, N_READY, sizeof (rtx), rank_for_schedule); } \
3963 /* Returns a positive value if x is preferred; returns a negative value if
3964 y is preferred. Should never return 0, since that will make the sort
3968 rank_for_schedule (x, y)
3972 rtx tmp = *(rtx *)y;
3973 rtx tmp2 = *(rtx *)x;
3975 int tmp_class, tmp2_class, depend_count1, depend_count2;
3976 int val, priority_val, spec_val, prob_val, weight_val;
3979 /* Prefer insn with higher priority. */
3980 priority_val = INSN_PRIORITY (tmp2) - INSN_PRIORITY (tmp);
3982 return priority_val;
3984 /* Prefer an insn with smaller contribution to registers-pressure. */
3985 if (!reload_completed &&
3986 (weight_val = INSN_REG_WEIGHT (tmp) - INSN_REG_WEIGHT (tmp2)))
3987 return (weight_val);
3989 /* Some comparison make sense in interblock scheduling only. */
3990 if (INSN_BB (tmp) != INSN_BB (tmp2))
3992 /* Prefer an inblock motion on an interblock motion. */
3993 if ((INSN_BB (tmp2) == target_bb) && (INSN_BB (tmp) != target_bb))
3995 if ((INSN_BB (tmp) == target_bb) && (INSN_BB (tmp2) != target_bb))
3998 /* Prefer a useful motion on a speculative one. */
3999 if ((spec_val = IS_SPECULATIVE_INSN (tmp) - IS_SPECULATIVE_INSN (tmp2)))
4002 /* Prefer a more probable (speculative) insn. */
4003 prob_val = INSN_PROBABILITY (tmp2) - INSN_PROBABILITY (tmp);
4008 /* Compare insns based on their relation to the last-scheduled-insn. */
4009 if (last_scheduled_insn)
4011 /* Classify the instructions into three classes:
4012 1) Data dependent on last schedule insn.
4013 2) Anti/Output dependent on last scheduled insn.
4014 3) Independent of last scheduled insn, or has latency of one.
4015 Choose the insn from the highest numbered class if different. */
4016 link = find_insn_list (tmp, INSN_DEPEND (last_scheduled_insn));
4017 if (link == 0 || insn_cost (last_scheduled_insn, link, tmp) == 1)
4019 else if (REG_NOTE_KIND (link) == 0) /* Data dependence. */
4024 link = find_insn_list (tmp2, INSN_DEPEND (last_scheduled_insn));
4025 if (link == 0 || insn_cost (last_scheduled_insn, link, tmp2) == 1)
4027 else if (REG_NOTE_KIND (link) == 0) /* Data dependence. */
4032 if ((val = tmp2_class - tmp_class))
4036 /* Prefer the insn which has more later insns that depend on it.
4037 This gives the scheduler more freedom when scheduling later
4038 instructions at the expense of added register pressure. */
4040 for (link = INSN_DEPEND (tmp); link; link = XEXP (link, 1))
4044 for (link = INSN_DEPEND (tmp2); link; link = XEXP (link, 1))
4047 val = depend_count2 - depend_count1;
4051 /* If insns are equally good, sort by INSN_LUID (original insn order),
4052 so that we make the sort stable. This minimizes instruction movement,
4053 thus minimizing sched's effect on debugging and cross-jumping. */
4054 return INSN_LUID (tmp) - INSN_LUID (tmp2);
4057 /* Resort the array A in which only element at index N may be out of order. */
4059 HAIFA_INLINE static void
4064 rtx insn = a[n - 1];
4067 while (i >= 0 && rank_for_schedule (a + i, &insn) >= 0)
4075 static int max_priority;
4077 /* Add INSN to the insn queue so that it can be executed at least
4078 N_CYCLES after the currently executing insn. Preserve insns
4079 chain for debugging purposes. */
4081 HAIFA_INLINE static void
4082 queue_insn (insn, n_cycles)
4086 int next_q = NEXT_Q_AFTER (q_ptr, n_cycles);
4087 rtx link = alloc_INSN_LIST (insn, insn_queue[next_q]);
4088 insn_queue[next_q] = link;
4091 if (sched_verbose >= 2)
4093 fprintf (dump, ";;\t\tReady-->Q: insn %d: ", INSN_UID (insn));
4095 if (INSN_BB (insn) != target_bb)
4096 fprintf (dump, "(b%d) ", BLOCK_NUM (insn));
4098 fprintf (dump, "queued for %d cycles.\n", n_cycles);
4103 /* PREV is an insn that is ready to execute. Adjust its priority if that
4104 will help shorten or lengthen register lifetimes as appropriate. Also
4105 provide a hook for the target to tweek itself. */
4107 HAIFA_INLINE static void
4108 adjust_priority (prev)
4109 rtx prev ATTRIBUTE_UNUSED;
4111 /* ??? There used to be code here to try and estimate how an insn
4112 affected register lifetimes, but it did it by looking at REG_DEAD
4113 notes, which we removed in schedule_region. Nor did it try to
4114 take into account register pressure or anything useful like that.
4116 Revisit when we have a machine model to work with and not before. */
4118 #ifdef ADJUST_PRIORITY
4119 ADJUST_PRIORITY (prev);
4123 /* Clock at which the previous instruction was issued. */
4124 static int last_clock_var;
4126 /* INSN is the "currently executing insn". Launch each insn which was
4127 waiting on INSN. READY is a vector of insns which are ready to fire.
4128 N_READY is the number of elements in READY. CLOCK is the current
4132 schedule_insn (insn, ready, n_ready, clock)
4141 unit = insn_unit (insn);
4143 if (sched_verbose >= 2)
4145 fprintf (dump, ";;\t\t--> scheduling insn <<<%d>>> on unit ",
4147 insn_print_units (insn);
4148 fprintf (dump, "\n");
4151 if (sched_verbose && unit == -1)
4152 visualize_no_unit (insn);
4154 if (MAX_BLOCKAGE > 1 || issue_rate > 1 || sched_verbose)
4155 schedule_unit (unit, insn, clock);
4157 if (INSN_DEPEND (insn) == 0)
4160 /* This is used by the function adjust_priority above. */
4162 max_priority = MAX (INSN_PRIORITY (ready[0]), INSN_PRIORITY (insn));
4164 max_priority = INSN_PRIORITY (insn);
4166 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
4168 rtx next = XEXP (link, 0);
4169 int cost = insn_cost (insn, link, next);
4171 INSN_TICK (next) = MAX (INSN_TICK (next), clock + cost);
4173 if ((INSN_DEP_COUNT (next) -= 1) == 0)
4175 int effective_cost = INSN_TICK (next) - clock;
4177 /* For speculative insns, before inserting to ready/queue,
4178 check live, exception-free, and issue-delay. */
4179 if (INSN_BB (next) != target_bb
4180 && (!IS_VALID (INSN_BB (next))
4182 || (IS_SPECULATIVE_INSN (next)
4183 && (insn_issue_delay (next) > 3
4184 || !check_live (next, INSN_BB (next))
4185 || !is_exception_free (next, INSN_BB (next), target_bb)))))
4188 if (sched_verbose >= 2)
4190 fprintf (dump, ";;\t\tdependences resolved: insn %d ",
4193 if (current_nr_blocks > 1 && INSN_BB (next) != target_bb)
4194 fprintf (dump, "/b%d ", BLOCK_NUM (next));
4196 if (effective_cost < 1)
4197 fprintf (dump, "into ready\n");
4199 fprintf (dump, "into queue with cost=%d\n", effective_cost);
4202 /* Adjust the priority of NEXT and either put it on the ready
4203 list or queue it. */
4204 adjust_priority (next);
4205 if (effective_cost < 1)
4206 ready[n_ready++] = next;
4208 queue_insn (next, effective_cost);
4212 /* Annotate the instruction with issue information -- TImode
4213 indicates that the instruction is expected not to be able
4214 to issue on the same cycle as the previous insn. A machine
4215 may use this information to decide how the instruction should
4217 if (reload_completed && issue_rate > 1)
4219 PUT_MODE (insn, clock > last_clock_var ? TImode : VOIDmode);
4220 last_clock_var = clock;
4226 /* Functions for handling of notes. */
4228 /* Delete notes beginning with INSN and put them in the chain
4229 of notes ended by NOTE_LIST.
4230 Returns the insn following the notes. */
4233 unlink_other_notes (insn, tail)
4236 rtx prev = PREV_INSN (insn);
4238 while (insn != tail && GET_CODE (insn) == NOTE)
4240 rtx next = NEXT_INSN (insn);
4241 /* Delete the note from its current position. */
4243 NEXT_INSN (prev) = next;
4245 PREV_INSN (next) = prev;
4247 /* See sched_analyze to see how these are handled. */
4248 if (NOTE_LINE_NUMBER (insn) != NOTE_INSN_SETJMP
4249 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_LOOP_BEG
4250 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_LOOP_END
4251 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_RANGE_START
4252 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_RANGE_END
4253 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_EH_REGION_BEG
4254 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_EH_REGION_END)
4256 /* Insert the note at the end of the notes list. */
4257 PREV_INSN (insn) = note_list;
4259 NEXT_INSN (note_list) = insn;
4268 /* Delete line notes beginning with INSN. Record line-number notes so
4269 they can be reused. Returns the insn following the notes. */
4272 unlink_line_notes (insn, tail)
4275 rtx prev = PREV_INSN (insn);
4277 while (insn != tail && GET_CODE (insn) == NOTE)
4279 rtx next = NEXT_INSN (insn);
4281 if (write_symbols != NO_DEBUG && NOTE_LINE_NUMBER (insn) > 0)
4283 /* Delete the note from its current position. */
4285 NEXT_INSN (prev) = next;
4287 PREV_INSN (next) = prev;
4289 /* Record line-number notes so they can be reused. */
4290 LINE_NOTE (insn) = insn;
4300 /* Return the head and tail pointers of BB. */
4302 HAIFA_INLINE static void
4303 get_block_head_tail (b, headp, tailp)
4312 /* HEAD and TAIL delimit the basic block being scheduled. */
4313 head = BLOCK_HEAD (b);
4314 tail = BLOCK_END (b);
4316 /* Don't include any notes or labels at the beginning of the
4317 basic block, or notes at the ends of basic blocks. */
4318 while (head != tail)
4320 if (GET_CODE (head) == NOTE)
4321 head = NEXT_INSN (head);
4322 else if (GET_CODE (tail) == NOTE)
4323 tail = PREV_INSN (tail);
4324 else if (GET_CODE (head) == CODE_LABEL)
4325 head = NEXT_INSN (head);
4334 HAIFA_INLINE static void
4335 get_bb_head_tail (bb, headp, tailp)
4340 get_block_head_tail (BB_TO_BLOCK (bb), headp, tailp);
4343 /* Delete line notes from bb. Save them so they can be later restored
4344 (in restore_line_notes ()). */
4355 get_bb_head_tail (bb, &head, &tail);
4358 && (GET_RTX_CLASS (GET_CODE (head)) != 'i'))
4361 next_tail = NEXT_INSN (tail);
4362 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
4366 /* Farm out notes, and maybe save them in NOTE_LIST.
4367 This is needed to keep the debugger from
4368 getting completely deranged. */
4369 if (GET_CODE (insn) == NOTE)
4372 insn = unlink_line_notes (insn, next_tail);
4378 if (insn == next_tail)
4384 /* Save line number notes for each insn in bb. */
4387 save_line_notes (bb)
4393 /* We must use the true line number for the first insn in the block
4394 that was computed and saved at the start of this pass. We can't
4395 use the current line number, because scheduling of the previous
4396 block may have changed the current line number. */
4398 rtx line = line_note_head[BB_TO_BLOCK (bb)];
4401 get_bb_head_tail (bb, &head, &tail);
4402 next_tail = NEXT_INSN (tail);
4404 for (insn = BLOCK_HEAD (BB_TO_BLOCK (bb));
4406 insn = NEXT_INSN (insn))
4407 if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0)
4410 LINE_NOTE (insn) = line;
4414 /* After bb was scheduled, insert line notes into the insns list. */
4417 restore_line_notes (bb)
4420 rtx line, note, prev, new;
4421 int added_notes = 0;
4423 rtx head, next_tail, insn;
4425 b = BB_TO_BLOCK (bb);
4427 head = BLOCK_HEAD (b);
4428 next_tail = NEXT_INSN (BLOCK_END (b));
4430 /* Determine the current line-number. We want to know the current
4431 line number of the first insn of the block here, in case it is
4432 different from the true line number that was saved earlier. If
4433 different, then we need a line number note before the first insn
4434 of this block. If it happens to be the same, then we don't want to
4435 emit another line number note here. */
4436 for (line = head; line; line = PREV_INSN (line))
4437 if (GET_CODE (line) == NOTE && NOTE_LINE_NUMBER (line) > 0)
4440 /* Walk the insns keeping track of the current line-number and inserting
4441 the line-number notes as needed. */
4442 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
4443 if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0)
4445 /* This used to emit line number notes before every non-deleted note.
4446 However, this confuses a debugger, because line notes not separated
4447 by real instructions all end up at the same address. I can find no
4448 use for line number notes before other notes, so none are emitted. */
4449 else if (GET_CODE (insn) != NOTE
4450 && (note = LINE_NOTE (insn)) != 0
4453 || NOTE_LINE_NUMBER (note) != NOTE_LINE_NUMBER (line)
4454 || NOTE_SOURCE_FILE (note) != NOTE_SOURCE_FILE (line)))
4457 prev = PREV_INSN (insn);
4458 if (LINE_NOTE (note))
4460 /* Re-use the original line-number note. */
4461 LINE_NOTE (note) = 0;
4462 PREV_INSN (note) = prev;
4463 NEXT_INSN (prev) = note;
4464 PREV_INSN (insn) = note;
4465 NEXT_INSN (note) = insn;
4470 new = emit_note_after (NOTE_LINE_NUMBER (note), prev);
4471 NOTE_SOURCE_FILE (new) = NOTE_SOURCE_FILE (note);
4472 RTX_INTEGRATED_P (new) = RTX_INTEGRATED_P (note);
4475 if (sched_verbose && added_notes)
4476 fprintf (dump, ";; added %d line-number notes\n", added_notes);
4479 /* After scheduling the function, delete redundant line notes from the
4483 rm_redundant_line_notes ()
4486 rtx insn = get_insns ();
4487 int active_insn = 0;
4490 /* Walk the insns deleting redundant line-number notes. Many of these
4491 are already present. The remainder tend to occur at basic
4492 block boundaries. */
4493 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
4494 if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0)
4496 /* If there are no active insns following, INSN is redundant. */
4497 if (active_insn == 0)
4500 NOTE_SOURCE_FILE (insn) = 0;
4501 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
4503 /* If the line number is unchanged, LINE is redundant. */
4505 && NOTE_LINE_NUMBER (line) == NOTE_LINE_NUMBER (insn)
4506 && NOTE_SOURCE_FILE (line) == NOTE_SOURCE_FILE (insn))
4509 NOTE_SOURCE_FILE (line) = 0;
4510 NOTE_LINE_NUMBER (line) = NOTE_INSN_DELETED;
4517 else if (!((GET_CODE (insn) == NOTE
4518 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED)
4519 || (GET_CODE (insn) == INSN
4520 && (GET_CODE (PATTERN (insn)) == USE
4521 || GET_CODE (PATTERN (insn)) == CLOBBER))))
4524 if (sched_verbose && notes)
4525 fprintf (dump, ";; deleted %d line-number notes\n", notes);
4528 /* Delete notes between head and tail and put them in the chain
4529 of notes ended by NOTE_LIST. */
4532 rm_other_notes (head, tail)
4540 && (GET_RTX_CLASS (GET_CODE (head)) != 'i'))
4543 next_tail = NEXT_INSN (tail);
4544 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
4548 /* Farm out notes, and maybe save them in NOTE_LIST.
4549 This is needed to keep the debugger from
4550 getting completely deranged. */
4551 if (GET_CODE (insn) == NOTE)
4555 insn = unlink_other_notes (insn, next_tail);
4561 if (insn == next_tail)
4567 /* Functions for computation of registers live/usage info. */
4569 /* Calculate INSN_REG_WEIGHT for all insns of a block. */
4572 find_insn_reg_weight (b)
4575 rtx insn, next_tail, head, tail;
4577 get_block_head_tail (b, &head, &tail);
4578 next_tail = NEXT_INSN (tail);
4580 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
4585 /* Handle register life information. */
4586 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
4589 /* Increment weight for each register born here. */
4591 if ((GET_CODE (x) == SET || GET_CODE (x) == CLOBBER)
4592 && register_operand (SET_DEST (x), VOIDmode))
4594 else if (GET_CODE (x) == PARALLEL)
4597 for (j = XVECLEN (x, 0) - 1; j >= 0; j--)
4599 x = XVECEXP (PATTERN (insn), 0, j);
4600 if ((GET_CODE (x) == SET || GET_CODE (x) == CLOBBER)
4601 && register_operand (SET_DEST (x), VOIDmode))
4606 /* Decrement weight for each register that dies here. */
4607 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4609 if (REG_NOTE_KIND (x) == REG_DEAD
4610 || REG_NOTE_KIND (x) == REG_UNUSED)
4614 INSN_REG_WEIGHT (insn) = reg_weight;
4618 /* Scheduling clock, modified in schedule_block() and queue_to_ready (). */
4619 static int clock_var;
4621 /* Move insns that became ready to fire from queue to ready list. */
4624 queue_to_ready (ready, n_ready)
4631 q_ptr = NEXT_Q (q_ptr);
4633 /* Add all pending insns that can be scheduled without stalls to the
4635 for (link = insn_queue[q_ptr]; link; link = XEXP (link, 1))
4638 insn = XEXP (link, 0);
4641 if (sched_verbose >= 2)
4642 fprintf (dump, ";;\t\tQ-->Ready: insn %d: ", INSN_UID (insn));
4644 if (sched_verbose >= 2 && INSN_BB (insn) != target_bb)
4645 fprintf (dump, "(b%d) ", BLOCK_NUM (insn));
4647 ready[n_ready++] = insn;
4648 if (sched_verbose >= 2)
4649 fprintf (dump, "moving to ready without stalls\n");
4651 insn_queue[q_ptr] = 0;
4653 /* If there are no ready insns, stall until one is ready and add all
4654 of the pending insns at that point to the ready list. */
4657 register int stalls;
4659 for (stalls = 1; stalls < INSN_QUEUE_SIZE; stalls++)
4661 if ((link = insn_queue[NEXT_Q_AFTER (q_ptr, stalls)]))
4663 for (; link; link = XEXP (link, 1))
4665 insn = XEXP (link, 0);
4668 if (sched_verbose >= 2)
4669 fprintf (dump, ";;\t\tQ-->Ready: insn %d: ", INSN_UID (insn));
4671 if (sched_verbose >= 2 && INSN_BB (insn) != target_bb)
4672 fprintf (dump, "(b%d) ", BLOCK_NUM (insn));
4674 ready[n_ready++] = insn;
4675 if (sched_verbose >= 2)
4676 fprintf (dump, "moving to ready with %d stalls\n", stalls);
4678 insn_queue[NEXT_Q_AFTER (q_ptr, stalls)] = 0;
4685 if (sched_verbose && stalls)
4686 visualize_stall_cycles (BB_TO_BLOCK (target_bb), stalls);
4687 q_ptr = NEXT_Q_AFTER (q_ptr, stalls);
4688 clock_var += stalls;
4693 /* Print the ready list for debugging purposes. Callable from debugger. */
4696 debug_ready_list (ready, n_ready)
4702 for (i = 0; i < n_ready; i++)
4704 fprintf (dump, " %d", INSN_UID (ready[i]));
4705 if (current_nr_blocks > 1 && INSN_BB (ready[i]) != target_bb)
4706 fprintf (dump, "/b%d", BLOCK_NUM (ready[i]));
4708 fprintf (dump, "\n");
4711 /* Print names of units on which insn can/should execute, for debugging. */
4714 insn_print_units (insn)
4718 int unit = insn_unit (insn);
4721 fprintf (dump, "none");
4723 fprintf (dump, "%s", function_units[unit].name);
4726 fprintf (dump, "[");
4727 for (i = 0, unit = ~unit; unit; i++, unit >>= 1)
4730 fprintf (dump, "%s", function_units[i].name);
4732 fprintf (dump, " ");
4734 fprintf (dump, "]");
4738 /* MAX_VISUAL_LINES is the maximum number of lines in visualization table
4739 of a basic block. If more lines are needed, table is splitted to two.
4740 n_visual_lines is the number of lines printed so far for a block.
4741 visual_tbl contains the block visualization info.
4742 vis_no_unit holds insns in a cycle that are not mapped to any unit. */
4743 #define MAX_VISUAL_LINES 100
4748 rtx vis_no_unit[10];
4750 /* Finds units that are in use in this fuction. Required only
4751 for visualization. */
4754 init_target_units ()
4759 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
4761 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
4764 unit = insn_unit (insn);
4767 target_units |= ~unit;
4769 target_units |= (1 << unit);
4773 /* Return the length of the visualization table. */
4776 get_visual_tbl_length ()
4782 /* Compute length of one field in line. */
4783 s = (char *) alloca (INSN_LEN + 6);
4784 sprintf (s, " %33s", "uname");
4787 /* Compute length of one line. */
4790 for (unit = 0; unit < FUNCTION_UNITS_SIZE; unit++)
4791 if (function_units[unit].bitmask & target_units)
4792 for (i = 0; i < function_units[unit].multiplicity; i++)
4795 n += strlen ("\n") + 2;
4797 /* Compute length of visualization string. */
4798 return (MAX_VISUAL_LINES * n);
4801 /* Init block visualization debugging info. */
4804 init_block_visualization ()
4806 strcpy (visual_tbl, "");
4814 safe_concat (buf, cur, str)
4819 char *end = buf + BUF_LEN - 2; /* Leave room for null. */
4828 while (cur < end && (c = *str++) != '\0')
4835 /* This recognizes rtx, I classified as expressions. These are always
4836 represent some action on values or results of other expression, that
4837 may be stored in objects representing values. */
4840 print_exp (buf, x, verbose)
4848 const char *fun = (char *)0;
4853 for (i = 0; i < 4; i++)
4859 switch (GET_CODE (x))
4862 op[0] = XEXP (x, 0);
4863 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4864 && INTVAL (XEXP (x, 1)) < 0)
4867 op[1] = GEN_INT (-INTVAL (XEXP (x, 1)));
4872 op[1] = XEXP (x, 1);
4876 op[0] = XEXP (x, 0);
4878 op[1] = XEXP (x, 1);
4882 op[0] = XEXP (x, 0);
4884 op[1] = XEXP (x, 1);
4888 op[0] = XEXP (x, 0);
4889 op[1] = XEXP (x, 1);
4893 op[0] = XEXP (x, 0);
4896 op[0] = XEXP (x, 0);
4898 op[1] = XEXP (x, 1);
4901 op[0] = XEXP (x, 0);
4903 op[1] = XEXP (x, 1);
4907 op[0] = XEXP (x, 0);
4908 op[1] = XEXP (x, 1);
4911 op[0] = XEXP (x, 0);
4913 op[1] = XEXP (x, 1);
4917 op[0] = XEXP (x, 0);
4918 op[1] = XEXP (x, 1);
4922 op[0] = XEXP (x, 0);
4923 op[1] = XEXP (x, 1);
4927 op[0] = XEXP (x, 0);
4928 op[1] = XEXP (x, 1);
4932 op[0] = XEXP (x, 0);
4933 op[1] = XEXP (x, 1);
4937 op[0] = XEXP (x, 0);
4938 op[1] = XEXP (x, 1);
4942 op[0] = XEXP (x, 0);
4945 op[0] = XEXP (x, 0);
4947 op[1] = XEXP (x, 1);
4950 op[0] = XEXP (x, 0);
4952 op[1] = XEXP (x, 1);
4955 op[0] = XEXP (x, 0);
4957 op[1] = XEXP (x, 1);
4960 op[0] = XEXP (x, 0);
4962 op[1] = XEXP (x, 1);
4965 op[0] = XEXP (x, 0);
4967 op[1] = XEXP (x, 1);
4970 op[0] = XEXP (x, 0);
4972 op[1] = XEXP (x, 1);
4975 op[0] = XEXP (x, 0);
4977 op[1] = XEXP (x, 1);
4980 op[0] = XEXP (x, 0);
4982 op[1] = XEXP (x, 1);
4986 op[0] = XEXP (x, 0);
4990 op[0] = XEXP (x, 0);
4994 op[0] = XEXP (x, 0);
4997 op[0] = XEXP (x, 0);
4999 op[1] = XEXP (x, 1);
5002 op[0] = XEXP (x, 0);
5004 op[1] = XEXP (x, 1);
5007 op[0] = XEXP (x, 0);
5009 op[1] = XEXP (x, 1);
5013 op[0] = XEXP (x, 0);
5014 op[1] = XEXP (x, 1);
5017 op[0] = XEXP (x, 0);
5019 op[1] = XEXP (x, 1);
5023 op[0] = XEXP (x, 0);
5024 op[1] = XEXP (x, 1);
5027 op[0] = XEXP (x, 0);
5029 op[1] = XEXP (x, 1);
5033 op[0] = XEXP (x, 0);
5034 op[1] = XEXP (x, 1);
5037 op[0] = XEXP (x, 0);
5039 op[1] = XEXP (x, 1);
5043 op[0] = XEXP (x, 0);
5044 op[1] = XEXP (x, 1);
5047 fun = (verbose) ? "sign_extract" : "sxt";
5048 op[0] = XEXP (x, 0);
5049 op[1] = XEXP (x, 1);
5050 op[2] = XEXP (x, 2);
5053 fun = (verbose) ? "zero_extract" : "zxt";
5054 op[0] = XEXP (x, 0);
5055 op[1] = XEXP (x, 1);
5056 op[2] = XEXP (x, 2);
5059 fun = (verbose) ? "sign_extend" : "sxn";
5060 op[0] = XEXP (x, 0);
5063 fun = (verbose) ? "zero_extend" : "zxn";
5064 op[0] = XEXP (x, 0);
5067 fun = (verbose) ? "float_extend" : "fxn";
5068 op[0] = XEXP (x, 0);
5071 fun = (verbose) ? "trunc" : "trn";
5072 op[0] = XEXP (x, 0);
5074 case FLOAT_TRUNCATE:
5075 fun = (verbose) ? "float_trunc" : "ftr";
5076 op[0] = XEXP (x, 0);
5079 fun = (verbose) ? "float" : "flt";
5080 op[0] = XEXP (x, 0);
5082 case UNSIGNED_FLOAT:
5083 fun = (verbose) ? "uns_float" : "ufl";
5084 op[0] = XEXP (x, 0);
5088 op[0] = XEXP (x, 0);
5091 fun = (verbose) ? "uns_fix" : "ufx";
5092 op[0] = XEXP (x, 0);
5096 op[0] = XEXP (x, 0);
5100 op[0] = XEXP (x, 0);
5103 op[0] = XEXP (x, 0);
5107 op[0] = XEXP (x, 0);
5112 op[0] = XEXP (x, 0);
5116 op[1] = XEXP (x, 1);
5121 op[0] = XEXP (x, 0);
5123 op[1] = XEXP (x, 1);
5125 op[2] = XEXP (x, 2);
5130 op[0] = TRAP_CONDITION (x);
5133 case UNSPEC_VOLATILE:
5135 cur = safe_concat (buf, cur, "unspec");
5136 if (GET_CODE (x) == UNSPEC_VOLATILE)
5137 cur = safe_concat (buf, cur, "/v");
5138 cur = safe_concat (buf, cur, "[");
5140 for (i = 0; i < XVECLEN (x, 0); i++)
5142 print_pattern (tmp, XVECEXP (x, 0, i), verbose);
5143 cur = safe_concat (buf, cur, sep);
5144 cur = safe_concat (buf, cur, tmp);
5147 cur = safe_concat (buf, cur, "] ");
5148 sprintf (tmp, "%d", XINT (x, 1));
5149 cur = safe_concat (buf, cur, tmp);
5153 /* If (verbose) debug_rtx (x); */
5154 st[0] = GET_RTX_NAME (GET_CODE (x));
5158 /* Print this as a function? */
5161 cur = safe_concat (buf, cur, fun);
5162 cur = safe_concat (buf, cur, "(");
5165 for (i = 0; i < 4; i++)
5168 cur = safe_concat (buf, cur, st[i]);
5173 cur = safe_concat (buf, cur, ",");
5175 print_value (tmp, op[i], verbose);
5176 cur = safe_concat (buf, cur, tmp);
5181 cur = safe_concat (buf, cur, ")");
5184 /* Prints rtxes, I customly classified as values. They're constants,
5185 registers, labels, symbols and memory accesses. */
5188 print_value (buf, x, verbose)
5196 switch (GET_CODE (x))
5199 sprintf (t, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
5200 cur = safe_concat (buf, cur, t);
5203 sprintf (t, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3));
5204 cur = safe_concat (buf, cur, t);
5207 cur = safe_concat (buf, cur, "\"");
5208 cur = safe_concat (buf, cur, XSTR (x, 0));
5209 cur = safe_concat (buf, cur, "\"");
5212 cur = safe_concat (buf, cur, "`");
5213 cur = safe_concat (buf, cur, XSTR (x, 0));
5214 cur = safe_concat (buf, cur, "'");
5217 sprintf (t, "L%d", INSN_UID (XEXP (x, 0)));
5218 cur = safe_concat (buf, cur, t);
5221 print_value (t, XEXP (x, 0), verbose);
5222 cur = safe_concat (buf, cur, "const(");
5223 cur = safe_concat (buf, cur, t);
5224 cur = safe_concat (buf, cur, ")");
5227 print_value (t, XEXP (x, 0), verbose);
5228 cur = safe_concat (buf, cur, "high(");
5229 cur = safe_concat (buf, cur, t);
5230 cur = safe_concat (buf, cur, ")");
5233 if (REGNO (x) < FIRST_PSEUDO_REGISTER)
5235 int c = reg_names[ REGNO (x) ][0];
5236 if (c >= '0' && c <= '9')
5237 cur = safe_concat (buf, cur, "%");
5239 cur = safe_concat (buf, cur, reg_names[ REGNO (x) ]);
5243 sprintf (t, "r%d", REGNO (x));
5244 cur = safe_concat (buf, cur, t);
5248 print_value (t, SUBREG_REG (x), verbose);
5249 cur = safe_concat (buf, cur, t);
5250 sprintf (t, "#%d", SUBREG_WORD (x));
5251 cur = safe_concat (buf, cur, t);
5254 cur = safe_concat (buf, cur, "scratch");
5257 cur = safe_concat (buf, cur, "cc0");
5260 cur = safe_concat (buf, cur, "pc");
5263 print_value (t, XEXP (x, 0), verbose);
5264 cur = safe_concat (buf, cur, "[");
5265 cur = safe_concat (buf, cur, t);
5266 cur = safe_concat (buf, cur, "]");
5269 print_exp (t, x, verbose);
5270 cur = safe_concat (buf, cur, t);
5275 /* The next step in insn detalization, its pattern recognition. */
5278 print_pattern (buf, x, verbose)
5283 char t1[BUF_LEN], t2[BUF_LEN], t3[BUF_LEN];
5285 switch (GET_CODE (x))
5288 print_value (t1, SET_DEST (x), verbose);
5289 print_value (t2, SET_SRC (x), verbose);
5290 sprintf (buf, "%s=%s", t1, t2);
5293 sprintf (buf, "return");
5296 print_exp (buf, x, verbose);
5299 print_value (t1, XEXP (x, 0), verbose);
5300 sprintf (buf, "clobber %s", t1);
5303 print_value (t1, XEXP (x, 0), verbose);
5304 sprintf (buf, "use %s", t1);
5311 for (i = 0; i < XVECLEN (x, 0); i++)
5313 print_pattern (t2, XVECEXP (x, 0, i), verbose);
5314 sprintf (t3, "%s%s;", t1, t2);
5317 sprintf (buf, "%s}", t1);
5324 sprintf (t1, "%%{");
5325 for (i = 0; i < XVECLEN (x, 0); i++)
5327 print_insn (t2, XVECEXP (x, 0, i), verbose);
5328 sprintf (t3, "%s%s;", t1, t2);
5331 sprintf (buf, "%s%%}", t1);
5335 sprintf (buf, "asm {%s}", XSTR (x, 0));
5340 print_value (buf, XEXP (x, 0), verbose);
5343 print_value (t1, TRAP_CONDITION (x), verbose);
5344 sprintf (buf, "trap_if %s", t1);
5350 sprintf (t1, "unspec{");
5351 for (i = 0; i < XVECLEN (x, 0); i++)
5353 print_pattern (t2, XVECEXP (x, 0, i), verbose);
5354 sprintf (t3, "%s%s;", t1, t2);
5357 sprintf (buf, "%s}", t1);
5360 case UNSPEC_VOLATILE:
5364 sprintf (t1, "unspec/v{");
5365 for (i = 0; i < XVECLEN (x, 0); i++)
5367 print_pattern (t2, XVECEXP (x, 0, i), verbose);
5368 sprintf (t3, "%s%s;", t1, t2);
5371 sprintf (buf, "%s}", t1);
5375 print_value (buf, x, verbose);
5377 } /* print_pattern */
5379 /* This is the main function in rtl visualization mechanism. It
5380 accepts an rtx and tries to recognize it as an insn, then prints it
5381 properly in human readable form, resembling assembler mnemonics.
5382 For every insn it prints its UID and BB the insn belongs too.
5383 (Probably the last "option" should be extended somehow, since it
5384 depends now on sched.c inner variables ...) */
5387 print_insn (buf, x, verbose)
5395 switch (GET_CODE (x))
5398 print_pattern (t, PATTERN (x), verbose);
5400 sprintf (buf, "b%d: i% 4d: %s", INSN_BB (x),
5403 sprintf (buf, "%-4d %s", INSN_UID (x), t);
5406 print_pattern (t, PATTERN (x), verbose);
5408 sprintf (buf, "b%d: i% 4d: jump %s", INSN_BB (x),
5411 sprintf (buf, "%-4d %s", INSN_UID (x), t);
5415 if (GET_CODE (x) == PARALLEL)
5417 x = XVECEXP (x, 0, 0);
5418 print_pattern (t, x, verbose);
5421 strcpy (t, "call <...>");
5423 sprintf (buf, "b%d: i% 4d: %s", INSN_BB (insn),
5424 INSN_UID (insn), t);
5426 sprintf (buf, "%-4d %s", INSN_UID (insn), t);
5429 sprintf (buf, "L%d:", INSN_UID (x));
5432 sprintf (buf, "i% 4d: barrier", INSN_UID (x));
5435 if (NOTE_LINE_NUMBER (x) > 0)
5436 sprintf (buf, "%4d note \"%s\" %d", INSN_UID (x),
5437 NOTE_SOURCE_FILE (x), NOTE_LINE_NUMBER (x));
5439 sprintf (buf, "%4d %s", INSN_UID (x),
5440 GET_NOTE_INSN_NAME (NOTE_LINE_NUMBER (x)));
5445 sprintf (buf, "Not an INSN at all\n");
5449 sprintf (buf, "i%-4d <What?>", INSN_UID (x));
5453 /* Print visualization debugging info. */
5456 print_block_visualization (b, s)
5463 fprintf (dump, "\n;; ==================== scheduling visualization for block %d %s \n", b, s);
5465 /* Print names of units. */
5466 fprintf (dump, ";; %-8s", "clock");
5467 for (unit = 0; unit < FUNCTION_UNITS_SIZE; unit++)
5468 if (function_units[unit].bitmask & target_units)
5469 for (i = 0; i < function_units[unit].multiplicity; i++)
5470 fprintf (dump, " %-33s", function_units[unit].name);
5471 fprintf (dump, " %-8s\n", "no-unit");
5473 fprintf (dump, ";; %-8s", "=====");
5474 for (unit = 0; unit < FUNCTION_UNITS_SIZE; unit++)
5475 if (function_units[unit].bitmask & target_units)
5476 for (i = 0; i < function_units[unit].multiplicity; i++)
5477 fprintf (dump, " %-33s", "==============================");
5478 fprintf (dump, " %-8s\n", "=======");
5480 /* Print insns in each cycle. */
5481 fprintf (dump, "%s\n", visual_tbl);
5484 /* Print insns in the 'no_unit' column of visualization. */
5487 visualize_no_unit (insn)
5490 vis_no_unit[n_vis_no_unit] = insn;
5494 /* Print insns scheduled in clock, for visualization. */
5497 visualize_scheduled_insns (b, clock)
5502 /* If no more room, split table into two. */
5503 if (n_visual_lines >= MAX_VISUAL_LINES)
5505 print_block_visualization (b, "(incomplete)");
5506 init_block_visualization ();
5511 sprintf (visual_tbl + strlen (visual_tbl), ";; %-8d", clock);
5512 for (unit = 0; unit < FUNCTION_UNITS_SIZE; unit++)
5513 if (function_units[unit].bitmask & target_units)
5514 for (i = 0; i < function_units[unit].multiplicity; i++)
5516 int instance = unit + i * FUNCTION_UNITS_SIZE;
5517 rtx insn = unit_last_insn[instance];
5519 /* Print insns that still keep the unit busy. */
5521 actual_hazard_this_instance (unit, instance, insn, clock, 0))
5524 print_insn (str, insn, 0);
5525 str[INSN_LEN] = '\0';
5526 sprintf (visual_tbl + strlen (visual_tbl), " %-33s", str);
5529 sprintf (visual_tbl + strlen (visual_tbl), " %-33s", "------------------------------");
5532 /* Print insns that are not assigned to any unit. */
5533 for (i = 0; i < n_vis_no_unit; i++)
5534 sprintf (visual_tbl + strlen (visual_tbl), " %-8d",
5535 INSN_UID (vis_no_unit[i]));
5538 sprintf (visual_tbl + strlen (visual_tbl), "\n");
5541 /* Print stalled cycles. */
5544 visualize_stall_cycles (b, stalls)
5549 /* If no more room, split table into two. */
5550 if (n_visual_lines >= MAX_VISUAL_LINES)
5552 print_block_visualization (b, "(incomplete)");
5553 init_block_visualization ();
5558 sprintf (visual_tbl + strlen (visual_tbl), ";; ");
5559 for (i = 0; i < stalls; i++)
5560 sprintf (visual_tbl + strlen (visual_tbl), ".");
5561 sprintf (visual_tbl + strlen (visual_tbl), "\n");
5564 /* move_insn1: Remove INSN from insn chain, and link it after LAST insn. */
5567 move_insn1 (insn, last)
5570 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
5571 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
5573 NEXT_INSN (insn) = NEXT_INSN (last);
5574 PREV_INSN (NEXT_INSN (last)) = insn;
5576 NEXT_INSN (last) = insn;
5577 PREV_INSN (insn) = last;
5582 /* Search INSN for REG_SAVE_NOTE note pairs for NOTE_INSN_SETJMP,
5583 NOTE_INSN_{LOOP,EHREGION}_{BEG,END}; and convert them back into
5584 NOTEs. The REG_SAVE_NOTE note following first one is contains the
5585 saved value for NOTE_BLOCK_NUMBER which is useful for
5586 NOTE_INSN_EH_REGION_{BEG,END} NOTEs. LAST is the last instruction
5587 output by the instruction scheduler. Return the new value of LAST. */
5590 reemit_notes (insn, last)
5597 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
5599 if (REG_NOTE_KIND (note) == REG_SAVE_NOTE)
5601 int note_type = INTVAL (XEXP (note, 0));
5602 if (note_type == NOTE_INSN_SETJMP)
5604 retval = emit_note_after (NOTE_INSN_SETJMP, insn);
5605 CONST_CALL_P (retval) = CONST_CALL_P (note);
5606 remove_note (insn, note);
5607 note = XEXP (note, 1);
5609 else if (note_type == NOTE_INSN_RANGE_START
5610 || note_type == NOTE_INSN_RANGE_END)
5612 last = emit_note_before (note_type, last);
5613 remove_note (insn, note);
5614 note = XEXP (note, 1);
5615 NOTE_RANGE_INFO (last) = XEXP (note, 0);
5619 last = emit_note_before (note_type, last);
5620 remove_note (insn, note);
5621 note = XEXP (note, 1);
5622 if (note_type == NOTE_INSN_EH_REGION_BEG
5623 || note_type == NOTE_INSN_EH_REGION_END)
5624 NOTE_EH_HANDLER (last) = INTVAL (XEXP (note, 0));
5626 remove_note (insn, note);
5632 /* Move INSN, and all insns which should be issued before it,
5633 due to SCHED_GROUP_P flag. Reemit notes if needed.
5635 Return the last insn emitted by the scheduler, which is the
5636 return value from the first call to reemit_notes. */
5639 move_insn (insn, last)
5644 /* If INSN has SCHED_GROUP_P set, then issue it and any other
5645 insns with SCHED_GROUP_P set first. */
5646 while (SCHED_GROUP_P (insn))
5648 rtx prev = PREV_INSN (insn);
5650 /* Move a SCHED_GROUP_P insn. */
5651 move_insn1 (insn, last);
5652 /* If this is the first call to reemit_notes, then record
5653 its return value. */
5654 if (retval == NULL_RTX)
5655 retval = reemit_notes (insn, insn);
5657 reemit_notes (insn, insn);
5661 /* Now move the first non SCHED_GROUP_P insn. */
5662 move_insn1 (insn, last);
5664 /* If this is the first call to reemit_notes, then record
5665 its return value. */
5666 if (retval == NULL_RTX)
5667 retval = reemit_notes (insn, insn);
5669 reemit_notes (insn, insn);
5674 /* Return an insn which represents a SCHED_GROUP, which is
5675 the last insn in the group. */
5686 insn = next_nonnote_insn (insn);
5688 while (insn && SCHED_GROUP_P (insn) && (GET_CODE (insn) != CODE_LABEL));
5693 /* Use forward list scheduling to rearrange insns of block BB in region RGN,
5694 possibly bringing insns from subsequent blocks in the same region.
5695 Return number of insns scheduled. */
5698 schedule_block (bb, rgn_n_insns)
5702 /* Local variables. */
5708 /* Flow block of this bb. */
5709 int b = BB_TO_BLOCK (bb);
5711 /* target_n_insns == number of insns in b before scheduling starts.
5712 sched_target_n_insns == how many of b's insns were scheduled.
5713 sched_n_insns == how many insns were scheduled in b. */
5714 int target_n_insns = 0;
5715 int sched_target_n_insns = 0;
5716 int sched_n_insns = 0;
5718 #define NEED_NOTHING 0
5723 /* Head/tail info for this block. */
5730 /* We used to have code to avoid getting parameters moved from hard
5731 argument registers into pseudos.
5733 However, it was removed when it proved to be of marginal benefit
5734 and caused problems because schedule_block and compute_forward_dependences
5735 had different notions of what the "head" insn was. */
5736 get_bb_head_tail (bb, &head, &tail);
5738 /* Interblock scheduling could have moved the original head insn from this
5739 block into a proceeding block. This may also cause schedule_block and
5740 compute_forward_dependences to have different notions of what the
5743 If the interblock movement happened to make this block start with
5744 some notes (LOOP, EH or SETJMP) before the first real insn, then
5745 HEAD will have various special notes attached to it which must be
5746 removed so that we don't end up with extra copies of the notes. */
5747 if (GET_RTX_CLASS (GET_CODE (head)) == 'i')
5751 for (note = REG_NOTES (head); note; note = XEXP (note, 1))
5752 if (REG_NOTE_KIND (note) == REG_SAVE_NOTE)
5753 remove_note (head, note);
5756 next_tail = NEXT_INSN (tail);
5757 prev_head = PREV_INSN (head);
5759 /* If the only insn left is a NOTE or a CODE_LABEL, then there is no need
5760 to schedule this block. */
5762 && (GET_RTX_CLASS (GET_CODE (head)) != 'i'))
5763 return (sched_n_insns);
5768 fprintf (dump, ";; ======================================================\n");
5770 ";; -- basic block %d from %d to %d -- %s reload\n",
5771 b, INSN_UID (BLOCK_HEAD (b)), INSN_UID (BLOCK_END (b)),
5772 (reload_completed ? "after" : "before"));
5773 fprintf (dump, ";; ======================================================\n");
5774 fprintf (dump, "\n");
5776 visual_tbl = (char *) alloca (get_visual_tbl_length ());
5777 init_block_visualization ();
5780 /* Remove remaining note insns from the block, save them in
5781 note_list. These notes are restored at the end of
5782 schedule_block (). */
5784 rm_other_notes (head, tail);
5788 /* Prepare current target block info. */
5789 if (current_nr_blocks > 1)
5791 candidate_table = (candidate *) xmalloc (current_nr_blocks
5792 * sizeof (candidate));
5795 /* ??? It is not clear why bblst_size is computed this way. The original
5796 number was clearly too small as it resulted in compiler failures.
5797 Multiplying by the original number by 2 (to account for update_bbs
5798 members) seems to be a reasonable solution. */
5799 /* ??? Or perhaps there is a bug somewhere else in this file? */
5800 bblst_size = (current_nr_blocks - bb) * rgn_nr_edges * 2;
5801 bblst_table = (int *) xmalloc (bblst_size * sizeof (int));
5803 bitlst_table_last = 0;
5804 bitlst_table_size = rgn_nr_edges;
5805 bitlst_table = (int *) xmalloc (rgn_nr_edges * sizeof (int));
5807 compute_trg_info (bb);
5812 /* Allocate the ready list. */
5813 ready = (rtx *) xmalloc ((rgn_n_insns + 1) * sizeof (rtx));
5815 /* Print debugging information. */
5816 if (sched_verbose >= 5)
5817 debug_dependencies ();
5820 /* Initialize ready list with all 'ready' insns in target block.
5821 Count number of insns in the target block being scheduled. */
5823 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
5827 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
5829 next = NEXT_INSN (insn);
5831 if (INSN_DEP_COUNT (insn) == 0
5832 && (SCHED_GROUP_P (next) == 0 || GET_RTX_CLASS (GET_CODE (next)) != 'i'))
5833 ready[n_ready++] = insn;
5834 if (!(SCHED_GROUP_P (insn)))
5838 /* Add to ready list all 'ready' insns in valid source blocks.
5839 For speculative insns, check-live, exception-free, and
5841 for (bb_src = bb + 1; bb_src < current_nr_blocks; bb_src++)
5842 if (IS_VALID (bb_src))
5848 get_bb_head_tail (bb_src, &head, &tail);
5849 src_next_tail = NEXT_INSN (tail);
5853 && (GET_RTX_CLASS (GET_CODE (head)) != 'i'))
5856 for (insn = src_head; insn != src_next_tail; insn = NEXT_INSN (insn))
5858 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
5861 if (!CANT_MOVE (insn)
5862 && (!IS_SPECULATIVE_INSN (insn)
5863 || (insn_issue_delay (insn) <= 3
5864 && check_live (insn, bb_src)
5865 && is_exception_free (insn, bb_src, target_bb))))
5869 /* Note that we havn't squirrled away the notes for
5870 blocks other than the current. So if this is a
5871 speculative insn, NEXT might otherwise be a note. */
5872 next = next_nonnote_insn (insn);
5873 if (INSN_DEP_COUNT (insn) == 0
5875 || SCHED_GROUP_P (next) == 0
5876 || GET_RTX_CLASS (GET_CODE (next)) != 'i'))
5877 ready[n_ready++] = insn;
5882 #ifdef MD_SCHED_INIT
5883 MD_SCHED_INIT (dump, sched_verbose);
5886 /* No insns scheduled in this block yet. */
5887 last_scheduled_insn = 0;
5889 /* Q_SIZE is the total number of insns in the queue. */
5893 bzero ((char *) insn_queue, sizeof (insn_queue));
5895 /* Start just before the beginning of time. */
5898 /* We start inserting insns after PREV_HEAD. */
5901 /* Initialize INSN_QUEUE, LIST and NEW_NEEDS. */
5902 new_needs = (NEXT_INSN (prev_head) == BLOCK_HEAD (b)
5903 ? NEED_HEAD : NEED_NOTHING);
5904 if (PREV_INSN (next_tail) == BLOCK_END (b))
5905 new_needs |= NEED_TAIL;
5907 /* Loop until all the insns in BB are scheduled. */
5908 while (sched_target_n_insns < target_n_insns)
5912 /* Add to the ready list all pending insns that can be issued now.
5913 If there are no ready insns, increment clock until one
5914 is ready and add all pending insns at that point to the ready
5916 n_ready = queue_to_ready (ready, n_ready);
5921 if (sched_verbose >= 2)
5923 fprintf (dump, ";;\t\tReady list after queue_to_ready: ");
5924 debug_ready_list (ready, n_ready);
5927 /* Sort the ready list based on priority. */
5928 SCHED_SORT (ready, n_ready);
5930 /* Allow the target to reorder the list, typically for
5931 better instruction bundling. */
5932 #ifdef MD_SCHED_REORDER
5933 MD_SCHED_REORDER (dump, sched_verbose, ready, n_ready, clock_var,
5936 can_issue_more = issue_rate;
5941 fprintf (dump, "\n;;\tReady list (t =%3d): ", clock_var);
5942 debug_ready_list (ready, n_ready);
5945 /* Issue insns from ready list. */
5946 while (n_ready != 0 && can_issue_more)
5948 /* Select and remove the insn from the ready list. */
5949 rtx insn = ready[--n_ready];
5950 int cost = actual_hazard (insn_unit (insn), insn, clock_var, 0);
5954 queue_insn (insn, cost);
5958 /* An interblock motion? */
5959 if (INSN_BB (insn) != target_bb)
5964 if (IS_SPECULATIVE_INSN (insn))
5966 if (!check_live (insn, INSN_BB (insn)))
5968 update_live (insn, INSN_BB (insn));
5970 /* For speculative load, mark insns fed by it. */
5971 if (IS_LOAD_INSN (insn) || FED_BY_SPEC_LOAD (insn))
5972 set_spec_fed (insn);
5978 /* Find the beginning of the scheduling group. */
5979 /* ??? Ought to update basic block here, but later bits of
5980 schedule_block assumes the original insn block is
5984 while (SCHED_GROUP_P (temp))
5985 temp = PREV_INSN (temp);
5987 /* Update source block boundaries. */
5988 b1 = BLOCK_FOR_INSN (temp);
5989 if (temp == b1->head && insn == b1->end)
5991 /* We moved all the insns in the basic block.
5992 Emit a note after the last insn and update the
5993 begin/end boundaries to point to the note. */
5994 rtx note = emit_note_after (NOTE_INSN_DELETED, insn);
5998 else if (insn == b1->end)
6000 /* We took insns from the end of the basic block,
6001 so update the end of block boundary so that it
6002 points to the first insn we did not move. */
6003 b1->end = PREV_INSN (temp);
6005 else if (temp == b1->head)
6007 /* We took insns from the start of the basic block,
6008 so update the start of block boundary so that
6009 it points to the first insn we did not move. */
6010 b1->head = NEXT_INSN (insn);
6015 /* In block motion. */
6016 sched_target_n_insns++;
6019 last_scheduled_insn = insn;
6020 last = move_insn (insn, last);
6023 #ifdef MD_SCHED_VARIABLE_ISSUE
6024 MD_SCHED_VARIABLE_ISSUE (dump, sched_verbose, insn,
6030 n_ready = schedule_insn (insn, ready, n_ready, clock_var);
6032 /* Close this block after scheduling its jump. */
6033 if (GET_CODE (last_scheduled_insn) == JUMP_INSN)
6039 visualize_scheduled_insns (b, clock_var);
6045 fprintf (dump, ";;\tReady list (final): ");
6046 debug_ready_list (ready, n_ready);
6047 print_block_visualization (b, "");
6050 /* Sanity check -- queue must be empty now. Meaningless if region has
6052 if (current_nr_blocks > 1)
6053 if (!flag_schedule_interblock && q_size != 0)
6056 /* Update head/tail boundaries. */
6057 head = NEXT_INSN (prev_head);
6060 /* Restore-other-notes: NOTE_LIST is the end of a chain of notes
6061 previously found among the insns. Insert them at the beginning
6065 rtx note_head = note_list;
6067 while (PREV_INSN (note_head))
6069 note_head = PREV_INSN (note_head);
6072 PREV_INSN (note_head) = PREV_INSN (head);
6073 NEXT_INSN (PREV_INSN (head)) = note_head;
6074 PREV_INSN (head) = note_list;
6075 NEXT_INSN (note_list) = head;
6079 /* Update target block boundaries. */
6080 if (new_needs & NEED_HEAD)
6081 BLOCK_HEAD (b) = head;
6083 if (new_needs & NEED_TAIL)
6084 BLOCK_END (b) = tail;
6089 fprintf (dump, ";; total time = %d\n;; new basic block head = %d\n",
6090 clock_var, INSN_UID (BLOCK_HEAD (b)));
6091 fprintf (dump, ";; new basic block end = %d\n\n",
6092 INSN_UID (BLOCK_END (b)));
6096 if (current_nr_blocks > 1)
6098 free (candidate_table);
6100 free (bitlst_table);
6104 return (sched_n_insns);
6105 } /* schedule_block () */
6108 /* Print the bit-set of registers, S, callable from debugger. */
6111 debug_reg_vector (s)
6116 EXECUTE_IF_SET_IN_REG_SET (s, 0, regno,
6118 fprintf (dump, " %d", regno);
6121 fprintf (dump, "\n");
6124 /* Use the backward dependences from LOG_LINKS to build
6125 forward dependences in INSN_DEPEND. */
6128 compute_block_forward_dependences (bb)
6134 enum reg_note dep_type;
6136 get_bb_head_tail (bb, &head, &tail);
6137 next_tail = NEXT_INSN (tail);
6138 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
6140 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
6143 insn = group_leader (insn);
6145 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
6147 rtx x = group_leader (XEXP (link, 0));
6150 if (x != XEXP (link, 0))
6153 #ifdef ENABLE_CHECKING
6154 /* If add_dependence is working properly there should never
6155 be notes, deleted insns or duplicates in the backward
6156 links. Thus we need not check for them here.
6158 However, if we have enabled checking we might as well go
6159 ahead and verify that add_dependence worked properly. */
6160 if (GET_CODE (x) == NOTE
6161 || INSN_DELETED_P (x)
6162 || find_insn_list (insn, INSN_DEPEND (x)))
6166 new_link = alloc_INSN_LIST (insn, INSN_DEPEND (x));
6168 dep_type = REG_NOTE_KIND (link);
6169 PUT_REG_NOTE_KIND (new_link, dep_type);
6171 INSN_DEPEND (x) = new_link;
6172 INSN_DEP_COUNT (insn) += 1;
6177 /* Initialize variables for region data dependence analysis.
6178 n_bbs is the number of region blocks. */
6184 int maxreg = max_reg_num ();
6185 deps->reg_last_uses = (rtx *) xcalloc (maxreg, sizeof (rtx));
6186 deps->reg_last_sets = (rtx *) xcalloc (maxreg, sizeof (rtx));
6187 deps->reg_last_clobbers = (rtx *) xcalloc (maxreg, sizeof (rtx));
6189 deps->pending_read_insns = 0;
6190 deps->pending_read_mems = 0;
6191 deps->pending_write_insns = 0;
6192 deps->pending_write_mems = 0;
6193 deps->pending_lists_length = 0;
6194 deps->last_pending_memory_flush = 0;
6195 deps->last_function_call = 0;
6197 deps->sched_before_next_call
6198 = gen_rtx_INSN (VOIDmode, 0, NULL_RTX, NULL_RTX,
6199 NULL_RTX, 0, NULL_RTX, NULL_RTX);
6200 LOG_LINKS (deps->sched_before_next_call) = 0;
6203 /* Add dependences so that branches are scheduled to run last in their
6207 add_branch_dependences (head, tail)
6212 /* For all branches, calls, uses, clobbers, and cc0 setters, force them
6213 to remain in order at the end of the block by adding dependencies and
6214 giving the last a high priority. There may be notes present, and
6215 prev_head may also be a note.
6217 Branches must obviously remain at the end. Calls should remain at the
6218 end since moving them results in worse register allocation. Uses remain
6219 at the end to ensure proper register allocation. cc0 setters remaim
6220 at the end because they can't be moved away from their cc0 user. */
6223 while (GET_CODE (insn) == CALL_INSN
6224 || GET_CODE (insn) == JUMP_INSN
6225 || (GET_CODE (insn) == INSN
6226 && (GET_CODE (PATTERN (insn)) == USE
6227 || GET_CODE (PATTERN (insn)) == CLOBBER
6229 || sets_cc0_p (PATTERN (insn))
6232 || GET_CODE (insn) == NOTE)
6234 if (GET_CODE (insn) != NOTE)
6237 && !find_insn_list (insn, LOG_LINKS (last)))
6239 add_dependence (last, insn, REG_DEP_ANTI);
6240 INSN_REF_COUNT (insn)++;
6243 CANT_MOVE (insn) = 1;
6246 /* Skip over insns that are part of a group.
6247 Make each insn explicitly depend on the previous insn.
6248 This ensures that only the group header will ever enter
6249 the ready queue (and, when scheduled, will automatically
6250 schedule the SCHED_GROUP_P block). */
6251 while (SCHED_GROUP_P (insn))
6253 rtx temp = prev_nonnote_insn (insn);
6254 add_dependence (insn, temp, REG_DEP_ANTI);
6259 /* Don't overrun the bounds of the basic block. */
6263 insn = PREV_INSN (insn);
6266 /* Make sure these insns are scheduled last in their block. */
6269 while (insn != head)
6271 insn = prev_nonnote_insn (insn);
6273 if (INSN_REF_COUNT (insn) != 0)
6276 add_dependence (last, insn, REG_DEP_ANTI);
6277 INSN_REF_COUNT (insn) = 1;
6279 /* Skip over insns that are part of a group. */
6280 while (SCHED_GROUP_P (insn))
6281 insn = prev_nonnote_insn (insn);
6285 /* After computing the dependencies for block BB, propagate the dependencies
6286 found in TMP_DEPS to the successors of the block. MAX_REG is the number
6289 propagate_deps (bb, tmp_deps, max_reg)
6291 struct deps *tmp_deps;
6294 int b = BB_TO_BLOCK (bb);
6297 rtx link_insn, link_mem;
6300 /* These lists should point to the right place, for correct
6302 bb_deps[bb].pending_read_insns = tmp_deps->pending_read_insns;
6303 bb_deps[bb].pending_read_mems = tmp_deps->pending_read_mems;
6304 bb_deps[bb].pending_write_insns = tmp_deps->pending_write_insns;
6305 bb_deps[bb].pending_write_mems = tmp_deps->pending_write_mems;
6307 /* bb's structures are inherited by its successors. */
6308 first_edge = e = OUT_EDGES (b);
6315 int b_succ = TO_BLOCK (e);
6316 int bb_succ = BLOCK_TO_BB (b_succ);
6317 struct deps *succ_deps = bb_deps + bb_succ;
6319 /* Only bbs "below" bb, in the same region, are interesting. */
6320 if (CONTAINING_RGN (b) != CONTAINING_RGN (b_succ)
6327 for (reg = 0; reg < max_reg; reg++)
6329 /* reg-last-uses lists are inherited by bb_succ. */
6330 for (u = tmp_deps->reg_last_uses[reg]; u; u = XEXP (u, 1))
6332 if (find_insn_list (XEXP (u, 0),
6333 succ_deps->reg_last_uses[reg]))
6336 succ_deps->reg_last_uses[reg]
6337 = alloc_INSN_LIST (XEXP (u, 0),
6338 succ_deps->reg_last_uses[reg]);
6341 /* reg-last-defs lists are inherited by bb_succ. */
6342 for (u = tmp_deps->reg_last_sets[reg]; u; u = XEXP (u, 1))
6344 if (find_insn_list (XEXP (u, 0),
6345 succ_deps->reg_last_sets[reg]))
6348 succ_deps->reg_last_sets[reg]
6349 = alloc_INSN_LIST (XEXP (u, 0),
6350 succ_deps->reg_last_sets[reg]);
6353 for (u = tmp_deps->reg_last_clobbers[reg]; u; u = XEXP (u, 1))
6355 if (find_insn_list (XEXP (u, 0),
6356 succ_deps->reg_last_clobbers[reg]))
6359 succ_deps->reg_last_clobbers[reg]
6360 = alloc_INSN_LIST (XEXP (u, 0),
6361 succ_deps->reg_last_clobbers[reg]);
6365 /* Mem read/write lists are inherited by bb_succ. */
6366 link_insn = tmp_deps->pending_read_insns;
6367 link_mem = tmp_deps->pending_read_mems;
6370 if (!(find_insn_mem_list (XEXP (link_insn, 0),
6372 succ_deps->pending_read_insns,
6373 succ_deps->pending_read_mems)))
6374 add_insn_mem_dependence (succ_deps, &succ_deps->pending_read_insns,
6375 &succ_deps->pending_read_mems,
6376 XEXP (link_insn, 0), XEXP (link_mem, 0));
6377 link_insn = XEXP (link_insn, 1);
6378 link_mem = XEXP (link_mem, 1);
6381 link_insn = tmp_deps->pending_write_insns;
6382 link_mem = tmp_deps->pending_write_mems;
6385 if (!(find_insn_mem_list (XEXP (link_insn, 0),
6387 succ_deps->pending_write_insns,
6388 succ_deps->pending_write_mems)))
6389 add_insn_mem_dependence (succ_deps,
6390 &succ_deps->pending_write_insns,
6391 &succ_deps->pending_write_mems,
6392 XEXP (link_insn, 0), XEXP (link_mem, 0));
6394 link_insn = XEXP (link_insn, 1);
6395 link_mem = XEXP (link_mem, 1);
6398 /* last_function_call is inherited by bb_succ. */
6399 for (u = tmp_deps->last_function_call; u; u = XEXP (u, 1))
6401 if (find_insn_list (XEXP (u, 0),
6402 succ_deps->last_function_call))
6405 succ_deps->last_function_call
6406 = alloc_INSN_LIST (XEXP (u, 0),
6407 succ_deps->last_function_call);
6410 /* last_pending_memory_flush is inherited by bb_succ. */
6411 for (u = tmp_deps->last_pending_memory_flush; u; u = XEXP (u, 1))
6413 if (find_insn_list (XEXP (u, 0),
6414 succ_deps->last_pending_memory_flush))
6417 succ_deps->last_pending_memory_flush
6418 = alloc_INSN_LIST (XEXP (u, 0),
6419 succ_deps->last_pending_memory_flush);
6422 /* sched_before_next_call is inherited by bb_succ. */
6423 x = LOG_LINKS (tmp_deps->sched_before_next_call);
6424 for (; x; x = XEXP (x, 1))
6425 add_dependence (succ_deps->sched_before_next_call,
6426 XEXP (x, 0), REG_DEP_ANTI);
6430 while (e != first_edge);
6433 /* Compute backward dependences inside bb. In a multiple blocks region:
6434 (1) a bb is analyzed after its predecessors, and (2) the lists in
6435 effect at the end of bb (after analyzing for bb) are inherited by
6438 Specifically for reg-reg data dependences, the block insns are
6439 scanned by sched_analyze () top-to-bottom. Two lists are
6440 maintained by sched_analyze (): reg_last_sets[] for register DEFs,
6441 and reg_last_uses[] for register USEs.
6443 When analysis is completed for bb, we update for its successors:
6444 ; - DEFS[succ] = Union (DEFS [succ], DEFS [bb])
6445 ; - USES[succ] = Union (USES [succ], DEFS [bb])
6447 The mechanism for computing mem-mem data dependence is very
6448 similar, and the result is interblock dependences in the region. */
6451 compute_block_backward_dependences (bb)
6456 int max_reg = max_reg_num ();
6457 struct deps tmp_deps;
6459 tmp_deps = bb_deps[bb];
6461 /* Do the analysis for this block. */
6462 get_bb_head_tail (bb, &head, &tail);
6463 sched_analyze (&tmp_deps, head, tail);
6464 add_branch_dependences (head, tail);
6466 if (current_nr_blocks > 1)
6467 propagate_deps (bb, &tmp_deps, max_reg);
6469 /* Free up the INSN_LISTs.
6471 Note this loop is executed max_reg * nr_regions times. It's first
6472 implementation accounted for over 90% of the calls to free_INSN_LIST_list.
6473 The list was empty for the vast majority of those calls. On the PA, not
6474 calling free_INSN_LIST_list in those cases improves -O2 compile times by
6476 for (i = 0; i < max_reg; ++i)
6478 if (tmp_deps.reg_last_clobbers[i])
6479 free_INSN_LIST_list (&tmp_deps.reg_last_clobbers[i]);
6480 if (tmp_deps.reg_last_sets[i])
6481 free_INSN_LIST_list (&tmp_deps.reg_last_sets[i]);
6482 if (tmp_deps.reg_last_uses[i])
6483 free_INSN_LIST_list (&tmp_deps.reg_last_uses[i]);
6486 /* Assert that we won't need bb_reg_last_* for this block anymore. */
6487 free (bb_deps[bb].reg_last_uses);
6488 free (bb_deps[bb].reg_last_sets);
6489 free (bb_deps[bb].reg_last_clobbers);
6490 bb_deps[bb].reg_last_uses = 0;
6491 bb_deps[bb].reg_last_sets = 0;
6492 bb_deps[bb].reg_last_clobbers = 0;
6495 /* Print dependences for debugging, callable from debugger. */
6498 debug_dependencies ()
6502 fprintf (dump, ";; --------------- forward dependences: ------------ \n");
6503 for (bb = 0; bb < current_nr_blocks; bb++)
6511 get_bb_head_tail (bb, &head, &tail);
6512 next_tail = NEXT_INSN (tail);
6513 fprintf (dump, "\n;; --- Region Dependences --- b %d bb %d \n",
6514 BB_TO_BLOCK (bb), bb);
6516 fprintf (dump, ";; %7s%6s%6s%6s%6s%6s%11s%6s\n",
6517 "insn", "code", "bb", "dep", "prio", "cost", "blockage", "units");
6518 fprintf (dump, ";; %7s%6s%6s%6s%6s%6s%11s%6s\n",
6519 "----", "----", "--", "---", "----", "----", "--------", "-----");
6520 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
6525 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
6528 fprintf (dump, ";; %6d ", INSN_UID (insn));
6529 if (GET_CODE (insn) == NOTE)
6531 n = NOTE_LINE_NUMBER (insn);
6533 fprintf (dump, "%s\n", GET_NOTE_INSN_NAME (n));
6535 fprintf (dump, "line %d, file %s\n", n,
6536 NOTE_SOURCE_FILE (insn));
6539 fprintf (dump, " {%s}\n", GET_RTX_NAME (GET_CODE (insn)));
6543 unit = insn_unit (insn);
6545 || function_units[unit].blockage_range_function == 0) ? 0 :
6546 function_units[unit].blockage_range_function (insn);
6548 ";; %s%5d%6d%6d%6d%6d%6d %3d -%3d ",
6549 (SCHED_GROUP_P (insn) ? "+" : " "),
6553 INSN_DEP_COUNT (insn),
6554 INSN_PRIORITY (insn),
6555 insn_cost (insn, 0, 0),
6556 (int) MIN_BLOCKAGE_COST (range),
6557 (int) MAX_BLOCKAGE_COST (range));
6558 insn_print_units (insn);
6559 fprintf (dump, "\t: ");
6560 for (link = INSN_DEPEND (insn); link; link = XEXP (link, 1))
6561 fprintf (dump, "%d ", INSN_UID (XEXP (link, 0)));
6562 fprintf (dump, "\n");
6566 fprintf (dump, "\n");
6569 /* Set_priorities: compute priority of each insn in the block. */
6582 get_bb_head_tail (bb, &head, &tail);
6583 prev_head = PREV_INSN (head);
6586 && (GET_RTX_CLASS (GET_CODE (head)) != 'i'))
6590 for (insn = tail; insn != prev_head; insn = PREV_INSN (insn))
6593 if (GET_CODE (insn) == NOTE)
6596 if (!(SCHED_GROUP_P (insn)))
6598 (void) priority (insn);
6604 /* Schedule a region. A region is either an inner loop, a loop-free
6605 subroutine, or a single basic block. Each bb in the region is
6606 scheduled after its flow predecessors. */
6609 schedule_region (rgn)
6613 int rgn_n_insns = 0;
6614 int sched_rgn_n_insns = 0;
6616 /* Set variables for the current region. */
6617 current_nr_blocks = RGN_NR_BLOCKS (rgn);
6618 current_blocks = RGN_BLOCKS (rgn);
6620 reg_pending_sets = ALLOCA_REG_SET ();
6621 reg_pending_clobbers = ALLOCA_REG_SET ();
6622 reg_pending_sets_all = 0;
6624 /* Initializations for region data dependence analyisis. */
6625 bb_deps = (struct deps *) xmalloc (sizeof (struct deps) * current_nr_blocks);
6626 for (bb = 0; bb < current_nr_blocks; bb++)
6627 init_deps (bb_deps + bb);
6629 /* Compute LOG_LINKS. */
6630 for (bb = 0; bb < current_nr_blocks; bb++)
6631 compute_block_backward_dependences (bb);
6633 /* Compute INSN_DEPEND. */
6634 for (bb = current_nr_blocks - 1; bb >= 0; bb--)
6635 compute_block_forward_dependences (bb);
6637 /* Delete line notes and set priorities. */
6638 for (bb = 0; bb < current_nr_blocks; bb++)
6640 if (write_symbols != NO_DEBUG)
6642 save_line_notes (bb);
6646 rgn_n_insns += set_priorities (bb);
6649 /* Compute interblock info: probabilities, split-edges, dominators, etc. */
6650 if (current_nr_blocks > 1)
6654 prob = (float *) xmalloc ((current_nr_blocks) * sizeof (float));
6656 bbset_size = current_nr_blocks / HOST_BITS_PER_WIDE_INT + 1;
6657 dom = (bbset *) xmalloc (current_nr_blocks * sizeof (bbset));
6658 for (i = 0; i < current_nr_blocks; i++)
6659 dom[i] = (bbset) xcalloc (bbset_size, sizeof (HOST_WIDE_INT));
6663 edge_to_bit = (int *) xmalloc (nr_edges * sizeof (int));
6664 for (i = 1; i < nr_edges; i++)
6665 if (CONTAINING_RGN (FROM_BLOCK (i)) == rgn)
6666 EDGE_TO_BIT (i) = rgn_nr_edges++;
6667 rgn_edges = (int *) xmalloc (rgn_nr_edges * sizeof (int));
6670 for (i = 1; i < nr_edges; i++)
6671 if (CONTAINING_RGN (FROM_BLOCK (i)) == (rgn))
6672 rgn_edges[rgn_nr_edges++] = i;
6675 edgeset_size = rgn_nr_edges / HOST_BITS_PER_WIDE_INT + 1;
6676 pot_split = (edgeset *) xmalloc (current_nr_blocks * sizeof (edgeset));
6678 = (edgeset *) xmalloc (current_nr_blocks * sizeof (edgeset));
6679 for (i = 0; i < current_nr_blocks; i++)
6682 (edgeset) xcalloc (edgeset_size, sizeof (HOST_WIDE_INT));
6684 (edgeset) xcalloc (edgeset_size, sizeof (HOST_WIDE_INT));
6687 /* Compute probabilities, dominators, split_edges. */
6688 for (bb = 0; bb < current_nr_blocks; bb++)
6689 compute_dom_prob_ps (bb);
6692 /* Now we can schedule all blocks. */
6693 for (bb = 0; bb < current_nr_blocks; bb++)
6694 sched_rgn_n_insns += schedule_block (bb, rgn_n_insns);
6696 /* Sanity check: verify that all region insns were scheduled. */
6697 if (sched_rgn_n_insns != rgn_n_insns)
6700 /* Restore line notes. */
6701 if (write_symbols != NO_DEBUG)
6703 for (bb = 0; bb < current_nr_blocks; bb++)
6704 restore_line_notes (bb);
6707 /* Done with this region. */
6708 free_pending_lists ();
6710 FREE_REG_SET (reg_pending_sets);
6711 FREE_REG_SET (reg_pending_clobbers);
6715 if (current_nr_blocks > 1)
6720 for (i = 0; i < current_nr_blocks; ++i)
6723 free (pot_split[i]);
6724 free (ancestor_edges[i]);
6730 free (ancestor_edges);
6734 /* The one entry point in this file. DUMP_FILE is the dump file for
6738 schedule_insns (dump_file)
6741 int *deaths_in_region;
6742 sbitmap blocks, large_region_blocks;
6748 int any_large_regions;
6750 /* Disable speculative loads in their presence if cc0 defined. */
6752 flag_schedule_speculative_load = 0;
6755 /* Taking care of this degenerate case makes the rest of
6756 this code simpler. */
6757 if (n_basic_blocks == 0)
6760 /* Set dump and sched_verbose for the desired debugging output. If no
6761 dump-file was specified, but -fsched-verbose-N (any N), print to stderr.
6762 For -fsched-verbose-N, N>=10, print everything to stderr. */
6763 sched_verbose = sched_verbose_param;
6764 if (sched_verbose_param == 0 && dump_file)
6766 dump = ((sched_verbose_param >= 10 || !dump_file) ? stderr : dump_file);
6771 /* Initialize issue_rate. */
6772 issue_rate = ISSUE_RATE;
6774 split_all_insns (1);
6776 /* We use LUID 0 for the fake insn (UID 0) which holds dependencies for
6777 pseudos which do not cross calls. */
6778 max_uid = get_max_uid () + 1;
6780 h_i_d = (struct haifa_insn_data *) xcalloc (max_uid, sizeof (*h_i_d));
6784 for (b = 0; b < n_basic_blocks; b++)
6785 for (insn = BLOCK_HEAD (b);; insn = NEXT_INSN (insn))
6787 INSN_LUID (insn) = luid;
6789 /* Increment the next luid, unless this is a note. We don't
6790 really need separate IDs for notes and we don't want to
6791 schedule differently depending on whether or not there are
6792 line-number notes, i.e., depending on whether or not we're
6793 generating debugging information. */
6794 if (GET_CODE (insn) != NOTE)
6797 if (insn == BLOCK_END (b))
6801 /* ?!? We could save some memory by computing a per-region luid mapping
6802 which could reduce both the number of vectors in the cache and the size
6803 of each vector. Instead we just avoid the cache entirely unless the
6804 average number of instructions in a basic block is very high. See
6805 the comment before the declaration of true_dependency_cache for
6806 what we consider "very high". */
6807 if (luid / n_basic_blocks > 100 * 5)
6809 true_dependency_cache = sbitmap_vector_alloc (luid, luid);
6810 sbitmap_vector_zero (true_dependency_cache, luid);
6814 rgn_table = (region *) xmalloc ((n_basic_blocks) * sizeof (region));
6815 rgn_bb_table = (int *) xmalloc ((n_basic_blocks) * sizeof (int));
6816 block_to_bb = (int *) xmalloc ((n_basic_blocks) * sizeof (int));
6817 containing_rgn = (int *) xmalloc ((n_basic_blocks) * sizeof (int));
6819 blocks = sbitmap_alloc (n_basic_blocks);
6820 large_region_blocks = sbitmap_alloc (n_basic_blocks);
6822 compute_bb_for_insn (max_uid);
6824 /* Compute regions for scheduling. */
6825 if (reload_completed
6826 || n_basic_blocks == 1
6827 || !flag_schedule_interblock)
6829 find_single_block_region ();
6833 /* Verify that a 'good' control flow graph can be built. */
6834 if (is_cfg_nonregular ())
6836 find_single_block_region ();
6841 struct edge_list *edge_list;
6843 dom = sbitmap_vector_alloc (n_basic_blocks, n_basic_blocks);
6845 /* The scheduler runs after flow; therefore, we can't blindly call
6846 back into find_basic_blocks since doing so could invalidate the
6847 info in global_live_at_start.
6849 Consider a block consisting entirely of dead stores; after life
6850 analysis it would be a block of NOTE_INSN_DELETED notes. If
6851 we call find_basic_blocks again, then the block would be removed
6852 entirely and invalidate our the register live information.
6854 We could (should?) recompute register live information. Doing
6855 so may even be beneficial. */
6856 edge_list = create_edge_list ();
6858 /* Compute the dominators and post dominators. We don't
6859 currently use post dominators, but we should for
6860 speculative motion analysis. */
6861 compute_flow_dominators (dom, NULL);
6863 /* build_control_flow will return nonzero if it detects unreachable
6864 blocks or any other irregularity with the cfg which prevents
6865 cross block scheduling. */
6866 if (build_control_flow (edge_list) != 0)
6867 find_single_block_region ();
6869 find_rgns (edge_list, dom);
6871 if (sched_verbose >= 3)
6874 /* For now. This will move as more and more of haifa is converted
6875 to using the cfg code in flow.c. */
6880 deaths_in_region = (int *) xmalloc (sizeof(int) * nr_regions);
6882 init_alias_analysis ();
6884 if (write_symbols != NO_DEBUG)
6888 line_note_head = (rtx *) xcalloc (n_basic_blocks, sizeof (rtx));
6890 /* Save-line-note-head:
6891 Determine the line-number at the start of each basic block.
6892 This must be computed and saved now, because after a basic block's
6893 predecessor has been scheduled, it is impossible to accurately
6894 determine the correct line number for the first insn of the block. */
6896 for (b = 0; b < n_basic_blocks; b++)
6897 for (line = BLOCK_HEAD (b); line; line = PREV_INSN (line))
6898 if (GET_CODE (line) == NOTE && NOTE_LINE_NUMBER (line) > 0)
6900 line_note_head[b] = line;
6905 /* Find units used in this fuction, for visualization. */
6907 init_target_units ();
6909 /* ??? Add a NOTE after the last insn of the last basic block. It is not
6910 known why this is done. */
6912 insn = BLOCK_END (n_basic_blocks - 1);
6913 if (NEXT_INSN (insn) == 0
6914 || (GET_CODE (insn) != NOTE
6915 && GET_CODE (insn) != CODE_LABEL
6916 /* Don't emit a NOTE if it would end up between an unconditional
6917 jump and a BARRIER. */
6918 && !(GET_CODE (insn) == JUMP_INSN
6919 && GET_CODE (NEXT_INSN (insn)) == BARRIER)))
6920 emit_note_after (NOTE_INSN_DELETED, BLOCK_END (n_basic_blocks - 1));
6922 /* Compute INSN_REG_WEIGHT for all blocks. We must do this before
6923 removing death notes. */
6924 for (b = n_basic_blocks - 1; b >= 0; b--)
6925 find_insn_reg_weight (b);
6927 /* Remove all death notes from the subroutine. */
6928 for (rgn = 0; rgn < nr_regions; rgn++)
6930 sbitmap_zero (blocks);
6931 for (b = RGN_NR_BLOCKS (rgn) - 1; b >= 0; --b)
6932 SET_BIT (blocks, rgn_bb_table [RGN_BLOCKS (rgn) + b]);
6934 deaths_in_region[rgn] = count_or_remove_death_notes (blocks, 1);
6937 /* Schedule every region in the subroutine. */
6938 for (rgn = 0; rgn < nr_regions; rgn++)
6939 schedule_region (rgn);
6941 /* Update life analysis for the subroutine. Do single block regions
6942 first so that we can verify that live_at_start didn't change. Then
6943 do all other blocks. */
6944 /* ??? There is an outside possibility that update_life_info, or more
6945 to the point propagate_block, could get called with non-zero flags
6946 more than once for one basic block. This would be kinda bad if it
6947 were to happen, since REG_INFO would be accumulated twice for the
6948 block, and we'd have twice the REG_DEAD notes.
6950 I'm fairly certain that this _shouldn't_ happen, since I don't think
6951 that live_at_start should change at region heads. Not sure what the
6952 best way to test for this kind of thing... */
6954 allocate_reg_life_data ();
6955 compute_bb_for_insn (max_uid);
6957 any_large_regions = 0;
6958 sbitmap_ones (large_region_blocks);
6960 for (rgn = 0; rgn < nr_regions; rgn++)
6961 if (RGN_NR_BLOCKS (rgn) > 1)
6962 any_large_regions = 1;
6965 sbitmap_zero (blocks);
6966 SET_BIT (blocks, rgn_bb_table[RGN_BLOCKS (rgn)]);
6967 RESET_BIT (large_region_blocks, rgn_bb_table[RGN_BLOCKS (rgn)]);
6969 update_life_info (blocks, UPDATE_LIFE_LOCAL,
6970 PROP_DEATH_NOTES | PROP_REG_INFO);
6972 /* In the single block case, the count of registers that died should
6973 not have changed during the schedule. */
6974 if (count_or_remove_death_notes (blocks, 0) != deaths_in_region[rgn])
6978 if (any_large_regions)
6980 update_life_info (large_region_blocks, UPDATE_LIFE_GLOBAL,
6981 PROP_DEATH_NOTES | PROP_REG_INFO);
6984 /* Reposition the prologue and epilogue notes in case we moved the
6985 prologue/epilogue insns. */
6986 if (reload_completed)
6987 reposition_prologue_and_epilogue_notes (get_insns ());
6989 /* Delete redundant line notes. */
6990 if (write_symbols != NO_DEBUG)
6991 rm_redundant_line_notes ();
6995 if (reload_completed == 0 && flag_schedule_interblock)
6997 fprintf (dump, "\n;; Procedure interblock/speculative motions == %d/%d \n",
7005 fprintf (dump, "\n\n");
7009 end_alias_analysis ();
7011 if (true_dependency_cache)
7013 free (true_dependency_cache);
7014 true_dependency_cache = NULL;
7017 free (rgn_bb_table);
7019 free (containing_rgn);
7023 if (write_symbols != NO_DEBUG)
7024 free (line_note_head);
7043 sbitmap_free (blocks);
7044 sbitmap_free (large_region_blocks);
7046 free (deaths_in_region);
7049 #endif /* INSN_SCHEDULING */