1 /* Instruction scheduling pass.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com) Enhanced by,
5 and currently maintained by, Jim Wilson (wilson@cygnus.com)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it under
10 the terms of the GNU General Public License as published by the Free
11 Software Foundation; either version 2, or (at your option) any later
14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to the Free
21 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
24 /* Instruction scheduling pass. This file, along with sched-deps.c,
25 contains the generic parts. The actual entry point is found for
26 the normal instruction scheduling pass is found in sched-rgn.c.
28 We compute insn priorities based on data dependencies. Flow
29 analysis only creates a fraction of the data-dependencies we must
30 observe: namely, only those dependencies which the combiner can be
31 expected to use. For this pass, we must therefore create the
32 remaining dependencies we need to observe: register dependencies,
33 memory dependencies, dependencies to keep function calls in order,
34 and the dependence between a conditional branch and the setting of
35 condition codes are all dealt with here.
37 The scheduler first traverses the data flow graph, starting with
38 the last instruction, and proceeding to the first, assigning values
39 to insn_priority as it goes. This sorts the instructions
40 topologically by data dependence.
42 Once priorities have been established, we order the insns using
43 list scheduling. This works as follows: starting with a list of
44 all the ready insns, and sorted according to priority number, we
45 schedule the insn from the end of the list by placing its
46 predecessors in the list according to their priority order. We
47 consider this insn scheduled by setting the pointer to the "end" of
48 the list to point to the previous insn. When an insn has no
49 predecessors, we either queue it until sufficient time has elapsed
50 or add it to the ready list. As the instructions are scheduled or
51 when stalls are introduced, the queue advances and dumps insns into
52 the ready list. When all insns down to the lowest priority have
53 been scheduled, the critical path of the basic block has been made
54 as short as possible. The remaining insns are then scheduled in
57 Function unit conflicts are resolved during forward list scheduling
58 by tracking the time when each insn is committed to the schedule
59 and from that, the time the function units it uses must be free.
60 As insns on the ready list are considered for scheduling, those
61 that would result in a blockage of the already committed insns are
62 queued until no blockage will result.
64 The following list shows the order in which we want to break ties
65 among insns in the ready list:
67 1. choose insn with the longest path to end of bb, ties
69 2. choose insn with least contribution to register pressure,
71 3. prefer in-block upon interblock motion, ties broken by
72 4. prefer useful upon speculative motion, ties broken by
73 5. choose insn with largest control flow probability, ties
75 6. choose insn with the least dependences upon the previously
76 scheduled insn, or finally
77 7 choose the insn which has the most insns dependent on it.
78 8. choose insn with lowest UID.
80 Memory references complicate matters. Only if we can be certain
81 that memory references are not part of the data dependency graph
82 (via true, anti, or output dependence), can we move operations past
83 memory references. To first approximation, reads can be done
84 independently, while writes introduce dependencies. Better
85 approximations will yield fewer dependencies.
87 Before reload, an extended analysis of interblock data dependences
88 is required for interblock scheduling. This is performed in
89 compute_block_backward_dependences ().
91 Dependencies set up by memory references are treated in exactly the
92 same way as other dependencies, by using LOG_LINKS backward
93 dependences. LOG_LINKS are translated into INSN_DEPEND forward
94 dependences for the purpose of forward list scheduling.
96 Having optimized the critical path, we may have also unduly
97 extended the lifetimes of some registers. If an operation requires
98 that constants be loaded into registers, it is certainly desirable
99 to load those constants as early as necessary, but no earlier.
100 I.e., it will not do to load up a bunch of registers at the
101 beginning of a basic block only to use them at the end, if they
102 could be loaded later, since this may result in excessive register
105 Note that since branches are never in basic blocks, but only end
106 basic blocks, this pass will not move branches. But that is ok,
107 since we can use GNU's delayed branch scheduling pass to take care
110 Also note that no further optimizations based on algebraic
111 identities are performed, so this pass would be a good one to
112 perform instruction splitting, such as breaking up a multiply
113 instruction into shifts and adds where that is profitable.
115 Given the memory aliasing analysis that this pass should perform,
116 it should be possible to remove redundant stores to memory, and to
117 load values from registers instead of hitting memory.
119 Before reload, speculative insns are moved only if a 'proof' exists
120 that no exception will be caused by this, and if no live registers
121 exist that inhibit the motion (live registers constraints are not
122 represented by data dependence edges).
124 This pass must update information that subsequent passes expect to
125 be correct. Namely: reg_n_refs, reg_n_sets, reg_n_deaths,
126 reg_n_calls_crossed, and reg_live_length. Also, BLOCK_HEAD,
129 The information in the line number notes is carefully retained by
130 this pass. Notes that refer to the starting and ending of
131 exception regions are also carefully retained by this pass. All
132 other NOTE insns are grouped in their same relative order at the
133 beginning of basic blocks and regions that have been scheduled. */
140 #include "hard-reg-set.h"
141 #include "basic-block.h"
143 #include "function.h"
145 #include "insn-config.h"
146 #include "insn-attr.h"
150 #include "sched-int.h"
153 #ifdef INSN_SCHEDULING
155 /* issue_rate is the number of insns that can be scheduled in the same
156 machine cycle. It can be defined in the config/mach/mach.h file,
157 otherwise we set it to 1. */
159 static int issue_rate;
161 /* If the following variable value is non zero, the scheduler inserts
162 bubbles (nop insns). The value of variable affects on scheduler
163 behavior only if automaton pipeline interface with multipass
164 scheduling is used and hook dfa_bubble is defined. */
165 int insert_schedule_bubbles_p = 0;
167 /* sched-verbose controls the amount of debugging output the
168 scheduler prints. It is controlled by -fsched-verbose=N:
169 N>0 and no -DSR : the output is directed to stderr.
170 N>=10 will direct the printouts to stderr (regardless of -dSR).
172 N=2: bb's probabilities, detailed ready list info, unit/insn info.
173 N=3: rtl at abort point, control-flow, regions info.
174 N=5: dependences info. */
176 static int sched_verbose_param = 0;
177 int sched_verbose = 0;
179 /* Debugging file. All printouts are sent to dump, which is always set,
180 either to stderr, or to the dump listing file (-dRS). */
181 FILE *sched_dump = 0;
183 /* Highest uid before scheduling. */
184 static int old_max_uid;
186 /* fix_sched_param() is called from toplev.c upon detection
187 of the -fsched-verbose=N option. */
190 fix_sched_param (param, val)
191 const char *param, *val;
193 if (!strcmp (param, "verbose"))
194 sched_verbose_param = atoi (val);
196 warning ("fix_sched_param: unknown param: %s", param);
199 struct haifa_insn_data *h_i_d;
201 #define DONE_PRIORITY -1
202 #define MAX_PRIORITY 0x7fffffff
203 #define TAIL_PRIORITY 0x7ffffffe
204 #define LAUNCH_PRIORITY 0x7f000001
205 #define DONE_PRIORITY_P(INSN) (INSN_PRIORITY (INSN) < 0)
206 #define LOW_PRIORITY_P(INSN) ((INSN_PRIORITY (INSN) & 0x7f000000) == 0)
208 #define LINE_NOTE(INSN) (h_i_d[INSN_UID (INSN)].line_note)
209 #define INSN_TICK(INSN) (h_i_d[INSN_UID (INSN)].tick)
211 /* Vector indexed by basic block number giving the starting line-number
212 for each basic block. */
213 static rtx *line_note_head;
215 /* List of important notes we must keep around. This is a pointer to the
216 last element in the list. */
217 static rtx note_list;
221 /* An instruction is ready to be scheduled when all insns preceding it
222 have already been scheduled. It is important to ensure that all
223 insns which use its result will not be executed until its result
224 has been computed. An insn is maintained in one of four structures:
226 (P) the "Pending" set of insns which cannot be scheduled until
227 their dependencies have been satisfied.
228 (Q) the "Queued" set of insns that can be scheduled when sufficient
230 (R) the "Ready" list of unscheduled, uncommitted insns.
231 (S) the "Scheduled" list of insns.
233 Initially, all insns are either "Pending" or "Ready" depending on
234 whether their dependencies are satisfied.
236 Insns move from the "Ready" list to the "Scheduled" list as they
237 are committed to the schedule. As this occurs, the insns in the
238 "Pending" list have their dependencies satisfied and move to either
239 the "Ready" list or the "Queued" set depending on whether
240 sufficient time has passed to make them ready. As time passes,
241 insns move from the "Queued" set to the "Ready" list. Insns may
242 move from the "Ready" list to the "Queued" set if they are blocked
243 due to a function unit conflict.
245 The "Pending" list (P) are the insns in the INSN_DEPEND of the unscheduled
246 insns, i.e., those that are ready, queued, and pending.
247 The "Queued" set (Q) is implemented by the variable `insn_queue'.
248 The "Ready" list (R) is implemented by the variables `ready' and
250 The "Scheduled" list (S) is the new insn chain built by this pass.
252 The transition (R->S) is implemented in the scheduling loop in
253 `schedule_block' when the best insn to schedule is chosen.
254 The transition (R->Q) is implemented in `queue_insn' when an
255 insn is found to have a function unit conflict with the already
257 The transitions (P->R and P->Q) are implemented in `schedule_insn' as
258 insns move from the ready list to the scheduled list.
259 The transition (Q->R) is implemented in 'queue_to_insn' as time
260 passes or stalls are introduced. */
262 /* Implement a circular buffer to delay instructions until sufficient
263 time has passed. For the old pipeline description interface,
264 INSN_QUEUE_SIZE is a power of two larger than MAX_BLOCKAGE and
265 MAX_READY_COST computed by genattr.c. For the new pipeline
266 description interface, MAX_INSN_QUEUE_INDEX is a power of two minus
267 one which is larger than maximal time of instruction execution
268 computed by genattr.c on the base maximal time of functional unit
269 reservations and geting a result. This is the longest time an
270 insn may be queued. */
272 #define MAX_INSN_QUEUE_INDEX max_insn_queue_index_macro_value
274 static rtx *insn_queue;
275 static int q_ptr = 0;
276 static int q_size = 0;
277 #define NEXT_Q(X) (((X)+1) & MAX_INSN_QUEUE_INDEX)
278 #define NEXT_Q_AFTER(X, C) (((X)+C) & MAX_INSN_QUEUE_INDEX)
280 /* The following variable defines value for macro
281 MAX_INSN_QUEUE_INDEX. */
282 static int max_insn_queue_index_macro_value;
284 /* The following variable value refers for all current and future
285 reservations of the processor units. */
288 /* The following variable value is size of memory representing all
289 current and future reservations of the processor units. It is used
290 only by DFA based scheduler. */
291 static size_t dfa_state_size;
293 /* The following array is used to find the best insn from ready when
294 the automaton pipeline interface is used. */
295 static char *ready_try;
297 /* Describe the ready list of the scheduler.
298 VEC holds space enough for all insns in the current region. VECLEN
299 says how many exactly.
300 FIRST is the index of the element with the highest priority; i.e. the
301 last one in the ready list, since elements are ordered by ascending
303 N_READY determines how many insns are on the ready list. */
313 /* Forward declarations. */
315 /* The scheduler using only DFA description should never use the
316 following five functions: */
317 static unsigned int blockage_range PARAMS ((int, rtx));
318 static void clear_units PARAMS ((void));
319 static void schedule_unit PARAMS ((int, rtx, int));
320 static int actual_hazard PARAMS ((int, rtx, int, int));
321 static int potential_hazard PARAMS ((int, rtx, int));
323 static int priority PARAMS ((rtx));
324 static int rank_for_schedule PARAMS ((const PTR, const PTR));
325 static void swap_sort PARAMS ((rtx *, int));
326 static void queue_insn PARAMS ((rtx, int));
327 static void schedule_insn PARAMS ((rtx, struct ready_list *, int));
328 static void find_insn_reg_weight PARAMS ((int));
329 static void adjust_priority PARAMS ((rtx));
330 static void advance_one_cycle PARAMS ((void));
332 /* Notes handling mechanism:
333 =========================
334 Generally, NOTES are saved before scheduling and restored after scheduling.
335 The scheduler distinguishes between three types of notes:
337 (1) LINE_NUMBER notes, generated and used for debugging. Here,
338 before scheduling a region, a pointer to the LINE_NUMBER note is
339 added to the insn following it (in save_line_notes()), and the note
340 is removed (in rm_line_notes() and unlink_line_notes()). After
341 scheduling the region, this pointer is used for regeneration of
342 the LINE_NUMBER note (in restore_line_notes()).
344 (2) LOOP_BEGIN, LOOP_END, SETJMP, EHREGION_BEG, EHREGION_END notes:
345 Before scheduling a region, a pointer to the note is added to the insn
346 that follows or precedes it. (This happens as part of the data dependence
347 computation). After scheduling an insn, the pointer contained in it is
348 used for regenerating the corresponding note (in reemit_notes).
350 (3) All other notes (e.g. INSN_DELETED): Before scheduling a block,
351 these notes are put in a list (in rm_other_notes() and
352 unlink_other_notes ()). After scheduling the block, these notes are
353 inserted at the beginning of the block (in schedule_block()). */
355 static rtx unlink_other_notes PARAMS ((rtx, rtx));
356 static rtx unlink_line_notes PARAMS ((rtx, rtx));
357 static rtx reemit_notes PARAMS ((rtx, rtx));
359 static rtx *ready_lastpos PARAMS ((struct ready_list *));
360 static void ready_sort PARAMS ((struct ready_list *));
361 static rtx ready_remove_first PARAMS ((struct ready_list *));
363 static void queue_to_ready PARAMS ((struct ready_list *));
365 static void debug_ready_list PARAMS ((struct ready_list *));
367 static rtx move_insn1 PARAMS ((rtx, rtx));
368 static rtx move_insn PARAMS ((rtx, rtx));
370 /* The following functions are used to implement multi-pass scheduling
371 on the first cycle. It is used only for DFA based scheduler. */
372 static rtx ready_element PARAMS ((struct ready_list *, int));
373 static rtx ready_remove PARAMS ((struct ready_list *, int));
374 static int max_issue PARAMS ((struct ready_list *, state_t, int *));
376 static rtx choose_ready PARAMS ((struct ready_list *));
378 #endif /* INSN_SCHEDULING */
380 /* Point to state used for the current scheduling pass. */
381 struct sched_info *current_sched_info;
383 #ifndef INSN_SCHEDULING
385 schedule_insns (dump_file)
386 FILE *dump_file ATTRIBUTE_UNUSED;
391 /* Pointer to the last instruction scheduled. Used by rank_for_schedule,
392 so that insns independent of the last scheduled insn will be preferred
393 over dependent instructions. */
395 static rtx last_scheduled_insn;
397 /* Compute the function units used by INSN. This caches the value
398 returned by function_units_used. A function unit is encoded as the
399 unit number if the value is non-negative and the compliment of a
400 mask if the value is negative. A function unit index is the
401 non-negative encoding. The scheduler using only DFA description
402 should never use the following function. */
408 int unit = INSN_UNIT (insn);
412 recog_memoized (insn);
414 /* A USE insn, or something else we don't need to understand.
415 We can't pass these directly to function_units_used because it will
416 trigger a fatal error for unrecognizable insns. */
417 if (INSN_CODE (insn) < 0)
421 unit = function_units_used (insn);
422 /* Increment non-negative values so we can cache zero. */
426 /* We only cache 16 bits of the result, so if the value is out of
427 range, don't cache it. */
428 if (FUNCTION_UNITS_SIZE < HOST_BITS_PER_SHORT
430 || (unit & ~((1 << (HOST_BITS_PER_SHORT - 1)) - 1)) == 0)
431 INSN_UNIT (insn) = unit;
433 return (unit > 0 ? unit - 1 : unit);
436 /* Compute the blockage range for executing INSN on UNIT. This caches
437 the value returned by the blockage_range_function for the unit.
438 These values are encoded in an int where the upper half gives the
439 minimum value and the lower half gives the maximum value. The
440 scheduler using only DFA description should never use the following
443 HAIFA_INLINE static unsigned int
444 blockage_range (unit, insn)
448 unsigned int blockage = INSN_BLOCKAGE (insn);
451 if ((int) UNIT_BLOCKED (blockage) != unit + 1)
453 range = function_units[unit].blockage_range_function (insn);
454 /* We only cache the blockage range for one unit and then only if
456 if (HOST_BITS_PER_INT >= UNIT_BITS + 2 * BLOCKAGE_BITS)
457 INSN_BLOCKAGE (insn) = ENCODE_BLOCKAGE (unit + 1, range);
460 range = BLOCKAGE_RANGE (blockage);
465 /* A vector indexed by function unit instance giving the last insn to
466 use the unit. The value of the function unit instance index for
467 unit U instance I is (U + I * FUNCTION_UNITS_SIZE). The scheduler
468 using only DFA description should never use the following variable. */
469 #if FUNCTION_UNITS_SIZE
470 static rtx unit_last_insn[FUNCTION_UNITS_SIZE * MAX_MULTIPLICITY];
472 static rtx unit_last_insn[1];
475 /* A vector indexed by function unit instance giving the minimum time
476 when the unit will unblock based on the maximum blockage cost. The
477 scheduler using only DFA description should never use the following
479 #if FUNCTION_UNITS_SIZE
480 static int unit_tick[FUNCTION_UNITS_SIZE * MAX_MULTIPLICITY];
482 static int unit_tick[1];
485 /* A vector indexed by function unit number giving the number of insns
486 that remain to use the unit. The scheduler using only DFA
487 description should never use the following variable. */
488 #if FUNCTION_UNITS_SIZE
489 static int unit_n_insns[FUNCTION_UNITS_SIZE];
491 static int unit_n_insns[1];
494 /* Access the unit_last_insn array. Used by the visualization code.
495 The scheduler using only DFA description should never use the
496 following function. */
499 get_unit_last_insn (instance)
502 return unit_last_insn[instance];
505 /* Reset the function unit state to the null state. */
510 memset ((char *) unit_last_insn, 0, sizeof (unit_last_insn));
511 memset ((char *) unit_tick, 0, sizeof (unit_tick));
512 memset ((char *) unit_n_insns, 0, sizeof (unit_n_insns));
515 /* Return the issue-delay of an insn. The scheduler using only DFA
516 description should never use the following function. */
519 insn_issue_delay (insn)
523 int unit = insn_unit (insn);
525 /* Efficiency note: in fact, we are working 'hard' to compute a
526 value that was available in md file, and is not available in
527 function_units[] structure. It would be nice to have this
531 if (function_units[unit].blockage_range_function &&
532 function_units[unit].blockage_function)
533 delay = function_units[unit].blockage_function (insn, insn);
536 for (i = 0, unit = ~unit; unit; i++, unit >>= 1)
537 if ((unit & 1) != 0 && function_units[i].blockage_range_function
538 && function_units[i].blockage_function)
539 delay = MAX (delay, function_units[i].blockage_function (insn, insn));
544 /* Return the actual hazard cost of executing INSN on the unit UNIT,
545 instance INSTANCE at time CLOCK if the previous actual hazard cost
546 was COST. The scheduler using only DFA description should never
547 use the following function. */
550 actual_hazard_this_instance (unit, instance, insn, clock, cost)
551 int unit, instance, clock, cost;
554 int tick = unit_tick[instance]; /* Issue time of the last issued insn. */
556 if (tick - clock > cost)
558 /* The scheduler is operating forward, so unit's last insn is the
559 executing insn and INSN is the candidate insn. We want a
560 more exact measure of the blockage if we execute INSN at CLOCK
561 given when we committed the execution of the unit's last insn.
563 The blockage value is given by either the unit's max blockage
564 constant, blockage range function, or blockage function. Use
565 the most exact form for the given unit. */
567 if (function_units[unit].blockage_range_function)
569 if (function_units[unit].blockage_function)
570 tick += (function_units[unit].blockage_function
571 (unit_last_insn[instance], insn)
572 - function_units[unit].max_blockage);
574 tick += ((int) MAX_BLOCKAGE_COST (blockage_range (unit, insn))
575 - function_units[unit].max_blockage);
577 if (tick - clock > cost)
583 /* Record INSN as having begun execution on the units encoded by UNIT
584 at time CLOCK. The scheduler using only DFA description should
585 never use the following function. */
587 HAIFA_INLINE static void
588 schedule_unit (unit, insn, clock)
597 #if MAX_MULTIPLICITY > 1
598 /* Find the first free instance of the function unit and use that
599 one. We assume that one is free. */
600 for (i = function_units[unit].multiplicity - 1; i > 0; i--)
602 if (!actual_hazard_this_instance (unit, instance, insn, clock, 0))
604 instance += FUNCTION_UNITS_SIZE;
607 unit_last_insn[instance] = insn;
608 unit_tick[instance] = (clock + function_units[unit].max_blockage);
611 for (i = 0, unit = ~unit; unit; i++, unit >>= 1)
613 schedule_unit (i, insn, clock);
616 /* Return the actual hazard cost of executing INSN on the units
617 encoded by UNIT at time CLOCK if the previous actual hazard cost
618 was COST. The scheduler using only DFA description should never
619 use the following function. */
621 HAIFA_INLINE static int
622 actual_hazard (unit, insn, clock, cost)
623 int unit, clock, cost;
630 /* Find the instance of the function unit with the minimum hazard. */
632 int best_cost = actual_hazard_this_instance (unit, instance, insn,
634 #if MAX_MULTIPLICITY > 1
637 if (best_cost > cost)
639 for (i = function_units[unit].multiplicity - 1; i > 0; i--)
641 instance += FUNCTION_UNITS_SIZE;
642 this_cost = actual_hazard_this_instance (unit, instance, insn,
644 if (this_cost < best_cost)
646 best_cost = this_cost;
647 if (this_cost <= cost)
653 cost = MAX (cost, best_cost);
656 for (i = 0, unit = ~unit; unit; i++, unit >>= 1)
658 cost = actual_hazard (i, insn, clock, cost);
663 /* Return the potential hazard cost of executing an instruction on the
664 units encoded by UNIT if the previous potential hazard cost was
665 COST. An insn with a large blockage time is chosen in preference
666 to one with a smaller time; an insn that uses a unit that is more
667 likely to be used is chosen in preference to one with a unit that
668 is less used. We are trying to minimize a subsequent actual
669 hazard. The scheduler using only DFA description should never use
670 the following function. */
672 HAIFA_INLINE static int
673 potential_hazard (unit, insn, cost)
678 unsigned int minb, maxb;
682 minb = maxb = function_units[unit].max_blockage;
685 if (function_units[unit].blockage_range_function)
687 maxb = minb = blockage_range (unit, insn);
688 maxb = MAX_BLOCKAGE_COST (maxb);
689 minb = MIN_BLOCKAGE_COST (minb);
694 /* Make the number of instructions left dominate. Make the
695 minimum delay dominate the maximum delay. If all these
696 are the same, use the unit number to add an arbitrary
697 ordering. Other terms can be added. */
698 ncost = minb * 0x40 + maxb;
699 ncost *= (unit_n_insns[unit] - 1) * 0x1000 + unit;
706 for (i = 0, unit = ~unit; unit; i++, unit >>= 1)
708 cost = potential_hazard (i, insn, cost);
713 /* Compute cost of executing INSN given the dependence LINK on the insn USED.
714 This is the number of cycles between instruction issue and
715 instruction results. */
718 insn_cost (insn, link, used)
719 rtx insn, link, used;
721 int cost = INSN_COST (insn);
725 /* A USE insn, or something else we don't need to
726 understand. We can't pass these directly to
727 result_ready_cost or insn_default_latency because it will
728 trigger a fatal error for unrecognizable insns. */
729 if (recog_memoized (insn) < 0)
731 INSN_COST (insn) = 0;
736 if (targetm.sched.use_dfa_pipeline_interface
737 && (*targetm.sched.use_dfa_pipeline_interface) ())
738 cost = insn_default_latency (insn);
740 cost = result_ready_cost (insn);
745 INSN_COST (insn) = cost;
749 /* In this case estimate cost without caring how insn is used. */
750 if (link == 0 || used == 0)
753 /* A USE insn should never require the value used to be computed.
754 This allows the computation of a function's result and parameter
755 values to overlap the return and call. */
756 if (recog_memoized (used) < 0)
760 if (targetm.sched.use_dfa_pipeline_interface
761 && (*targetm.sched.use_dfa_pipeline_interface) ())
763 if (INSN_CODE (insn) >= 0)
765 if (REG_NOTE_KIND (link) == REG_DEP_ANTI)
767 else if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
769 cost = (insn_default_latency (insn)
770 - insn_default_latency (used));
774 else if (bypass_p (insn))
775 cost = insn_latency (insn, used);
779 if (targetm.sched.adjust_cost)
780 cost = (*targetm.sched.adjust_cost) (used, link, insn, cost);
789 /* Compute the priority number for INSN. */
800 if (! INSN_PRIORITY_KNOWN (insn))
802 int this_priority = 0;
804 if (INSN_DEPEND (insn) == 0)
805 this_priority = insn_cost (insn, 0, 0);
808 for (link = INSN_DEPEND (insn); link; link = XEXP (link, 1))
813 if (RTX_INTEGRATED_P (link))
816 next = XEXP (link, 0);
818 /* Critical path is meaningful in block boundaries only. */
819 if (! (*current_sched_info->contributes_to_priority) (next, insn))
822 next_priority = insn_cost (insn, link, next) + priority (next);
823 if (next_priority > this_priority)
824 this_priority = next_priority;
827 INSN_PRIORITY (insn) = this_priority;
828 INSN_PRIORITY_KNOWN (insn) = 1;
831 return INSN_PRIORITY (insn);
834 /* Macros and functions for keeping the priority queue sorted, and
835 dealing with queueing and dequeueing of instructions. */
837 #define SCHED_SORT(READY, N_READY) \
838 do { if ((N_READY) == 2) \
839 swap_sort (READY, N_READY); \
840 else if ((N_READY) > 2) \
841 qsort (READY, N_READY, sizeof (rtx), rank_for_schedule); } \
844 /* Returns a positive value if x is preferred; returns a negative value if
845 y is preferred. Should never return 0, since that will make the sort
849 rank_for_schedule (x, y)
853 rtx tmp = *(const rtx *) y;
854 rtx tmp2 = *(const rtx *) x;
856 int tmp_class, tmp2_class, depend_count1, depend_count2;
857 int val, priority_val, weight_val, info_val;
859 /* Prefer insn with higher priority. */
860 priority_val = INSN_PRIORITY (tmp2) - INSN_PRIORITY (tmp);
864 /* Prefer an insn with smaller contribution to registers-pressure. */
865 if (!reload_completed &&
866 (weight_val = INSN_REG_WEIGHT (tmp) - INSN_REG_WEIGHT (tmp2)))
869 info_val = (*current_sched_info->rank) (tmp, tmp2);
873 /* Compare insns based on their relation to the last-scheduled-insn. */
874 if (last_scheduled_insn)
876 /* Classify the instructions into three classes:
877 1) Data dependent on last schedule insn.
878 2) Anti/Output dependent on last scheduled insn.
879 3) Independent of last scheduled insn, or has latency of one.
880 Choose the insn from the highest numbered class if different. */
881 link = find_insn_list (tmp, INSN_DEPEND (last_scheduled_insn));
882 if (link == 0 || insn_cost (last_scheduled_insn, link, tmp) == 1)
884 else if (REG_NOTE_KIND (link) == 0) /* Data dependence. */
889 link = find_insn_list (tmp2, INSN_DEPEND (last_scheduled_insn));
890 if (link == 0 || insn_cost (last_scheduled_insn, link, tmp2) == 1)
892 else if (REG_NOTE_KIND (link) == 0) /* Data dependence. */
897 if ((val = tmp2_class - tmp_class))
901 /* Prefer the insn which has more later insns that depend on it.
902 This gives the scheduler more freedom when scheduling later
903 instructions at the expense of added register pressure. */
905 for (link = INSN_DEPEND (tmp); link; link = XEXP (link, 1))
909 for (link = INSN_DEPEND (tmp2); link; link = XEXP (link, 1))
912 val = depend_count2 - depend_count1;
916 /* If insns are equally good, sort by INSN_LUID (original insn order),
917 so that we make the sort stable. This minimizes instruction movement,
918 thus minimizing sched's effect on debugging and cross-jumping. */
919 return INSN_LUID (tmp) - INSN_LUID (tmp2);
922 /* Resort the array A in which only element at index N may be out of order. */
924 HAIFA_INLINE static void
932 while (i >= 0 && rank_for_schedule (a + i, &insn) >= 0)
940 /* Add INSN to the insn queue so that it can be executed at least
941 N_CYCLES after the currently executing insn. Preserve insns
942 chain for debugging purposes. */
944 HAIFA_INLINE static void
945 queue_insn (insn, n_cycles)
949 int next_q = NEXT_Q_AFTER (q_ptr, n_cycles);
950 rtx link = alloc_INSN_LIST (insn, insn_queue[next_q]);
951 insn_queue[next_q] = link;
954 if (sched_verbose >= 2)
956 fprintf (sched_dump, ";;\t\tReady-->Q: insn %s: ",
957 (*current_sched_info->print_insn) (insn, 0));
959 fprintf (sched_dump, "queued for %d cycles.\n", n_cycles);
963 /* Return a pointer to the bottom of the ready list, i.e. the insn
964 with the lowest priority. */
966 HAIFA_INLINE static rtx *
967 ready_lastpos (ready)
968 struct ready_list *ready;
970 if (ready->n_ready == 0)
972 return ready->vec + ready->first - ready->n_ready + 1;
975 /* Add an element INSN to the ready list so that it ends up with the lowest
979 ready_add (ready, insn)
980 struct ready_list *ready;
983 if (ready->first == ready->n_ready)
985 memmove (ready->vec + ready->veclen - ready->n_ready,
986 ready_lastpos (ready),
987 ready->n_ready * sizeof (rtx));
988 ready->first = ready->veclen - 1;
990 ready->vec[ready->first - ready->n_ready] = insn;
994 /* Remove the element with the highest priority from the ready list and
997 HAIFA_INLINE static rtx
998 ready_remove_first (ready)
999 struct ready_list *ready;
1002 if (ready->n_ready == 0)
1004 t = ready->vec[ready->first--];
1006 /* If the queue becomes empty, reset it. */
1007 if (ready->n_ready == 0)
1008 ready->first = ready->veclen - 1;
1012 /* The following code implements multi-pass scheduling for the first
1013 cycle. In other words, we will try to choose ready insn which
1014 permits to start maximum number of insns on the same cycle. */
1016 /* Return a pointer to the element INDEX from the ready. INDEX for
1017 insn with the highest priority is 0, and the lowest priority has
1020 HAIFA_INLINE static rtx
1021 ready_element (ready, index)
1022 struct ready_list *ready;
1025 if (ready->n_ready == 0 || index >= ready->n_ready)
1027 return ready->vec[ready->first - index];
1030 /* Remove the element INDEX from the ready list and return it. INDEX
1031 for insn with the highest priority is 0, and the lowest priority
1034 HAIFA_INLINE static rtx
1035 ready_remove (ready, index)
1036 struct ready_list *ready;
1043 return ready_remove_first (ready);
1044 if (ready->n_ready == 0 || index >= ready->n_ready)
1046 t = ready->vec[ready->first - index];
1048 for (i = index; i < ready->n_ready; i++)
1049 ready->vec[ready->first - i] = ready->vec[ready->first - i - 1];
1054 /* Sort the ready list READY by ascending priority, using the SCHED_SORT
1057 HAIFA_INLINE static void
1059 struct ready_list *ready;
1061 rtx *first = ready_lastpos (ready);
1062 SCHED_SORT (first, ready->n_ready);
1065 /* PREV is an insn that is ready to execute. Adjust its priority if that
1066 will help shorten or lengthen register lifetimes as appropriate. Also
1067 provide a hook for the target to tweek itself. */
1069 HAIFA_INLINE static void
1070 adjust_priority (prev)
1073 /* ??? There used to be code here to try and estimate how an insn
1074 affected register lifetimes, but it did it by looking at REG_DEAD
1075 notes, which we removed in schedule_region. Nor did it try to
1076 take into account register pressure or anything useful like that.
1078 Revisit when we have a machine model to work with and not before. */
1080 if (targetm.sched.adjust_priority)
1081 INSN_PRIORITY (prev) =
1082 (*targetm.sched.adjust_priority) (prev, INSN_PRIORITY (prev));
1085 /* Advance time on one cycle. */
1086 HAIFA_INLINE static void
1087 advance_one_cycle ()
1089 if (targetm.sched.use_dfa_pipeline_interface
1090 && (*targetm.sched.use_dfa_pipeline_interface) ())
1092 if (targetm.sched.dfa_pre_cycle_insn)
1093 state_transition (curr_state,
1094 (*targetm.sched.dfa_pre_cycle_insn) ());
1096 state_transition (curr_state, NULL);
1098 if (targetm.sched.dfa_post_cycle_insn)
1099 state_transition (curr_state,
1100 (*targetm.sched.dfa_post_cycle_insn) ());
1104 /* Clock at which the previous instruction was issued. */
1105 static int last_clock_var;
1107 /* INSN is the "currently executing insn". Launch each insn which was
1108 waiting on INSN. READY is the ready list which contains the insns
1109 that are ready to fire. CLOCK is the current cycle.
1113 schedule_insn (insn, ready, clock)
1115 struct ready_list *ready;
1121 if (!targetm.sched.use_dfa_pipeline_interface
1122 || !(*targetm.sched.use_dfa_pipeline_interface) ())
1123 unit = insn_unit (insn);
1125 if (sched_verbose >= 2)
1128 if (targetm.sched.use_dfa_pipeline_interface
1129 && (*targetm.sched.use_dfa_pipeline_interface) ())
1131 fprintf (sched_dump,
1132 ";;\t\t--> scheduling insn <<<%d>>>:reservation ",
1135 if (recog_memoized (insn) < 0)
1136 fprintf (sched_dump, "nothing");
1138 print_reservation (sched_dump, insn);
1142 fprintf (sched_dump, ";;\t\t--> scheduling insn <<<%d>>> on unit ",
1144 insn_print_units (insn);
1147 fprintf (sched_dump, "\n");
1150 if (!targetm.sched.use_dfa_pipeline_interface
1151 || !(*targetm.sched.use_dfa_pipeline_interface) ())
1153 if (sched_verbose && unit == -1)
1154 visualize_no_unit (insn);
1157 if (MAX_BLOCKAGE > 1 || issue_rate > 1 || sched_verbose)
1158 schedule_unit (unit, insn, clock);
1160 if (INSN_DEPEND (insn) == 0)
1164 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
1166 rtx next = XEXP (link, 0);
1167 int cost = insn_cost (insn, link, next);
1169 INSN_TICK (next) = MAX (INSN_TICK (next), clock + cost);
1171 if ((INSN_DEP_COUNT (next) -= 1) == 0)
1173 int effective_cost = INSN_TICK (next) - clock;
1175 if (! (*current_sched_info->new_ready) (next))
1178 if (sched_verbose >= 2)
1180 fprintf (sched_dump, ";;\t\tdependences resolved: insn %s ",
1181 (*current_sched_info->print_insn) (next, 0));
1183 if (effective_cost < 1)
1184 fprintf (sched_dump, "into ready\n");
1186 fprintf (sched_dump, "into queue with cost=%d\n", effective_cost);
1189 /* Adjust the priority of NEXT and either put it on the ready
1190 list or queue it. */
1191 adjust_priority (next);
1192 if (effective_cost < 1)
1193 ready_add (ready, next);
1195 queue_insn (next, effective_cost);
1199 /* Annotate the instruction with issue information -- TImode
1200 indicates that the instruction is expected not to be able
1201 to issue on the same cycle as the previous insn. A machine
1202 may use this information to decide how the instruction should
1204 if (reload_completed && issue_rate > 1
1205 && GET_CODE (PATTERN (insn)) != USE
1206 && GET_CODE (PATTERN (insn)) != CLOBBER)
1208 PUT_MODE (insn, clock > last_clock_var ? TImode : VOIDmode);
1209 last_clock_var = clock;
1213 /* Functions for handling of notes. */
1215 /* Delete notes beginning with INSN and put them in the chain
1216 of notes ended by NOTE_LIST.
1217 Returns the insn following the notes. */
1220 unlink_other_notes (insn, tail)
1223 rtx prev = PREV_INSN (insn);
1225 while (insn != tail && GET_CODE (insn) == NOTE)
1227 rtx next = NEXT_INSN (insn);
1228 /* Delete the note from its current position. */
1230 NEXT_INSN (prev) = next;
1232 PREV_INSN (next) = prev;
1234 /* See sched_analyze to see how these are handled. */
1235 if (NOTE_LINE_NUMBER (insn) != NOTE_INSN_LOOP_BEG
1236 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_LOOP_END
1237 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_RANGE_BEG
1238 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_RANGE_END
1239 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_EH_REGION_BEG
1240 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_EH_REGION_END)
1242 /* Insert the note at the end of the notes list. */
1243 PREV_INSN (insn) = note_list;
1245 NEXT_INSN (note_list) = insn;
1254 /* Delete line notes beginning with INSN. Record line-number notes so
1255 they can be reused. Returns the insn following the notes. */
1258 unlink_line_notes (insn, tail)
1261 rtx prev = PREV_INSN (insn);
1263 while (insn != tail && GET_CODE (insn) == NOTE)
1265 rtx next = NEXT_INSN (insn);
1267 if (write_symbols != NO_DEBUG && NOTE_LINE_NUMBER (insn) > 0)
1269 /* Delete the note from its current position. */
1271 NEXT_INSN (prev) = next;
1273 PREV_INSN (next) = prev;
1275 /* Record line-number notes so they can be reused. */
1276 LINE_NOTE (insn) = insn;
1286 /* Return the head and tail pointers of BB. */
1289 get_block_head_tail (b, headp, tailp)
1294 /* HEAD and TAIL delimit the basic block being scheduled. */
1295 rtx head = BLOCK_HEAD (b);
1296 rtx tail = BLOCK_END (b);
1298 /* Don't include any notes or labels at the beginning of the
1299 basic block, or notes at the ends of basic blocks. */
1300 while (head != tail)
1302 if (GET_CODE (head) == NOTE)
1303 head = NEXT_INSN (head);
1304 else if (GET_CODE (tail) == NOTE)
1305 tail = PREV_INSN (tail);
1306 else if (GET_CODE (head) == CODE_LABEL)
1307 head = NEXT_INSN (head);
1316 /* Return nonzero if there are no real insns in the range [ HEAD, TAIL ]. */
1319 no_real_insns_p (head, tail)
1322 while (head != NEXT_INSN (tail))
1324 if (GET_CODE (head) != NOTE && GET_CODE (head) != CODE_LABEL)
1326 head = NEXT_INSN (head);
1331 /* Delete line notes from one block. Save them so they can be later restored
1332 (in restore_line_notes). HEAD and TAIL are the boundaries of the
1333 block in which notes should be processed. */
1336 rm_line_notes (head, tail)
1342 next_tail = NEXT_INSN (tail);
1343 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
1347 /* Farm out notes, and maybe save them in NOTE_LIST.
1348 This is needed to keep the debugger from
1349 getting completely deranged. */
1350 if (GET_CODE (insn) == NOTE)
1353 insn = unlink_line_notes (insn, next_tail);
1359 if (insn == next_tail)
1365 /* Save line number notes for each insn in block B. HEAD and TAIL are
1366 the boundaries of the block in which notes should be processed. */
1369 save_line_notes (b, head, tail)
1375 /* We must use the true line number for the first insn in the block
1376 that was computed and saved at the start of this pass. We can't
1377 use the current line number, because scheduling of the previous
1378 block may have changed the current line number. */
1380 rtx line = line_note_head[b];
1383 next_tail = NEXT_INSN (tail);
1385 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
1386 if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0)
1389 LINE_NOTE (insn) = line;
1392 /* After a block was scheduled, insert line notes into the insns list.
1393 HEAD and TAIL are the boundaries of the block in which notes should
1397 restore_line_notes (head, tail)
1400 rtx line, note, prev, new;
1401 int added_notes = 0;
1402 rtx next_tail, insn;
1405 next_tail = NEXT_INSN (tail);
1407 /* Determine the current line-number. We want to know the current
1408 line number of the first insn of the block here, in case it is
1409 different from the true line number that was saved earlier. If
1410 different, then we need a line number note before the first insn
1411 of this block. If it happens to be the same, then we don't want to
1412 emit another line number note here. */
1413 for (line = head; line; line = PREV_INSN (line))
1414 if (GET_CODE (line) == NOTE && NOTE_LINE_NUMBER (line) > 0)
1417 /* Walk the insns keeping track of the current line-number and inserting
1418 the line-number notes as needed. */
1419 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
1420 if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0)
1422 /* This used to emit line number notes before every non-deleted note.
1423 However, this confuses a debugger, because line notes not separated
1424 by real instructions all end up at the same address. I can find no
1425 use for line number notes before other notes, so none are emitted. */
1426 else if (GET_CODE (insn) != NOTE
1427 && INSN_UID (insn) < old_max_uid
1428 && (note = LINE_NOTE (insn)) != 0
1431 || NOTE_LINE_NUMBER (note) != NOTE_LINE_NUMBER (line)
1432 || NOTE_SOURCE_FILE (note) != NOTE_SOURCE_FILE (line)))
1435 prev = PREV_INSN (insn);
1436 if (LINE_NOTE (note))
1438 /* Re-use the original line-number note. */
1439 LINE_NOTE (note) = 0;
1440 PREV_INSN (note) = prev;
1441 NEXT_INSN (prev) = note;
1442 PREV_INSN (insn) = note;
1443 NEXT_INSN (note) = insn;
1448 new = emit_note_after (NOTE_LINE_NUMBER (note), prev);
1449 NOTE_SOURCE_FILE (new) = NOTE_SOURCE_FILE (note);
1450 RTX_INTEGRATED_P (new) = RTX_INTEGRATED_P (note);
1453 if (sched_verbose && added_notes)
1454 fprintf (sched_dump, ";; added %d line-number notes\n", added_notes);
1457 /* After scheduling the function, delete redundant line notes from the
1461 rm_redundant_line_notes ()
1464 rtx insn = get_insns ();
1465 int active_insn = 0;
1468 /* Walk the insns deleting redundant line-number notes. Many of these
1469 are already present. The remainder tend to occur at basic
1470 block boundaries. */
1471 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
1472 if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0)
1474 /* If there are no active insns following, INSN is redundant. */
1475 if (active_insn == 0)
1478 NOTE_SOURCE_FILE (insn) = 0;
1479 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1481 /* If the line number is unchanged, LINE is redundant. */
1483 && NOTE_LINE_NUMBER (line) == NOTE_LINE_NUMBER (insn)
1484 && NOTE_SOURCE_FILE (line) == NOTE_SOURCE_FILE (insn))
1487 NOTE_SOURCE_FILE (line) = 0;
1488 NOTE_LINE_NUMBER (line) = NOTE_INSN_DELETED;
1495 else if (!((GET_CODE (insn) == NOTE
1496 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED)
1497 || (GET_CODE (insn) == INSN
1498 && (GET_CODE (PATTERN (insn)) == USE
1499 || GET_CODE (PATTERN (insn)) == CLOBBER))))
1502 if (sched_verbose && notes)
1503 fprintf (sched_dump, ";; deleted %d line-number notes\n", notes);
1506 /* Delete notes between HEAD and TAIL and put them in the chain
1507 of notes ended by NOTE_LIST. */
1510 rm_other_notes (head, tail)
1518 if (head == tail && (! INSN_P (head)))
1521 next_tail = NEXT_INSN (tail);
1522 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
1526 /* Farm out notes, and maybe save them in NOTE_LIST.
1527 This is needed to keep the debugger from
1528 getting completely deranged. */
1529 if (GET_CODE (insn) == NOTE)
1533 insn = unlink_other_notes (insn, next_tail);
1539 if (insn == next_tail)
1545 /* Functions for computation of registers live/usage info. */
1547 /* Calculate INSN_REG_WEIGHT for all insns of a block. */
1550 find_insn_reg_weight (b)
1553 rtx insn, next_tail, head, tail;
1555 get_block_head_tail (b, &head, &tail);
1556 next_tail = NEXT_INSN (tail);
1558 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
1563 /* Handle register life information. */
1564 if (! INSN_P (insn))
1567 /* Increment weight for each register born here. */
1569 if ((GET_CODE (x) == SET || GET_CODE (x) == CLOBBER)
1570 && register_operand (SET_DEST (x), VOIDmode))
1572 else if (GET_CODE (x) == PARALLEL)
1575 for (j = XVECLEN (x, 0) - 1; j >= 0; j--)
1577 x = XVECEXP (PATTERN (insn), 0, j);
1578 if ((GET_CODE (x) == SET || GET_CODE (x) == CLOBBER)
1579 && register_operand (SET_DEST (x), VOIDmode))
1584 /* Decrement weight for each register that dies here. */
1585 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
1587 if (REG_NOTE_KIND (x) == REG_DEAD
1588 || REG_NOTE_KIND (x) == REG_UNUSED)
1592 INSN_REG_WEIGHT (insn) = reg_weight;
1596 /* Scheduling clock, modified in schedule_block() and queue_to_ready (). */
1597 static int clock_var;
1599 /* Move insns that became ready to fire from queue to ready list. */
1602 queue_to_ready (ready)
1603 struct ready_list *ready;
1608 q_ptr = NEXT_Q (q_ptr);
1610 /* Add all pending insns that can be scheduled without stalls to the
1612 for (link = insn_queue[q_ptr]; link; link = XEXP (link, 1))
1614 insn = XEXP (link, 0);
1617 if (sched_verbose >= 2)
1618 fprintf (sched_dump, ";;\t\tQ-->Ready: insn %s: ",
1619 (*current_sched_info->print_insn) (insn, 0));
1621 ready_add (ready, insn);
1622 if (sched_verbose >= 2)
1623 fprintf (sched_dump, "moving to ready without stalls\n");
1625 insn_queue[q_ptr] = 0;
1627 /* If there are no ready insns, stall until one is ready and add all
1628 of the pending insns at that point to the ready list. */
1629 if (ready->n_ready == 0)
1633 for (stalls = 1; stalls <= MAX_INSN_QUEUE_INDEX; stalls++)
1635 if ((link = insn_queue[NEXT_Q_AFTER (q_ptr, stalls)]))
1637 for (; link; link = XEXP (link, 1))
1639 insn = XEXP (link, 0);
1642 if (sched_verbose >= 2)
1643 fprintf (sched_dump, ";;\t\tQ-->Ready: insn %s: ",
1644 (*current_sched_info->print_insn) (insn, 0));
1646 ready_add (ready, insn);
1647 if (sched_verbose >= 2)
1648 fprintf (sched_dump, "moving to ready with %d stalls\n", stalls);
1650 insn_queue[NEXT_Q_AFTER (q_ptr, stalls)] = 0;
1652 advance_one_cycle ();
1657 advance_one_cycle ();
1660 if ((!targetm.sched.use_dfa_pipeline_interface
1661 || !(*targetm.sched.use_dfa_pipeline_interface) ())
1662 && sched_verbose && stalls)
1663 visualize_stall_cycles (stalls);
1665 q_ptr = NEXT_Q_AFTER (q_ptr, stalls);
1666 clock_var += stalls;
1670 /* Print the ready list for debugging purposes. Callable from debugger. */
1673 debug_ready_list (ready)
1674 struct ready_list *ready;
1679 if (ready->n_ready == 0)
1681 fprintf (sched_dump, "\n");
1685 p = ready_lastpos (ready);
1686 for (i = 0; i < ready->n_ready; i++)
1687 fprintf (sched_dump, " %s", (*current_sched_info->print_insn) (p[i], 0));
1688 fprintf (sched_dump, "\n");
1691 /* move_insn1: Remove INSN from insn chain, and link it after LAST insn. */
1694 move_insn1 (insn, last)
1697 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
1698 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
1700 NEXT_INSN (insn) = NEXT_INSN (last);
1701 PREV_INSN (NEXT_INSN (last)) = insn;
1703 NEXT_INSN (last) = insn;
1704 PREV_INSN (insn) = last;
1709 /* Search INSN for REG_SAVE_NOTE note pairs for
1710 NOTE_INSN_{LOOP,EHREGION}_{BEG,END}; and convert them back into
1711 NOTEs. The REG_SAVE_NOTE note following first one is contains the
1712 saved value for NOTE_BLOCK_NUMBER which is useful for
1713 NOTE_INSN_EH_REGION_{BEG,END} NOTEs. LAST is the last instruction
1714 output by the instruction scheduler. Return the new value of LAST. */
1717 reemit_notes (insn, last)
1724 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
1726 if (REG_NOTE_KIND (note) == REG_SAVE_NOTE)
1728 enum insn_note note_type = INTVAL (XEXP (note, 0));
1730 if (note_type == NOTE_INSN_RANGE_BEG
1731 || note_type == NOTE_INSN_RANGE_END)
1733 last = emit_note_before (note_type, last);
1734 remove_note (insn, note);
1735 note = XEXP (note, 1);
1736 NOTE_RANGE_INFO (last) = XEXP (note, 0);
1740 last = emit_note_before (note_type, last);
1741 remove_note (insn, note);
1742 note = XEXP (note, 1);
1743 if (note_type == NOTE_INSN_EH_REGION_BEG
1744 || note_type == NOTE_INSN_EH_REGION_END)
1745 NOTE_EH_HANDLER (last) = INTVAL (XEXP (note, 0));
1747 remove_note (insn, note);
1753 /* Move INSN, and all insns which should be issued before it,
1754 due to SCHED_GROUP_P flag. Reemit notes if needed.
1756 Return the last insn emitted by the scheduler, which is the
1757 return value from the first call to reemit_notes. */
1760 move_insn (insn, last)
1765 /* If INSN has SCHED_GROUP_P set, then issue it and any other
1766 insns with SCHED_GROUP_P set first. */
1767 while (SCHED_GROUP_P (insn))
1769 rtx prev = PREV_INSN (insn);
1771 /* Move a SCHED_GROUP_P insn. */
1772 move_insn1 (insn, last);
1773 /* If this is the first call to reemit_notes, then record
1774 its return value. */
1775 if (retval == NULL_RTX)
1776 retval = reemit_notes (insn, insn);
1778 reemit_notes (insn, insn);
1782 /* Now move the first non SCHED_GROUP_P insn. */
1783 move_insn1 (insn, last);
1785 /* If this is the first call to reemit_notes, then record
1786 its return value. */
1787 if (retval == NULL_RTX)
1788 retval = reemit_notes (insn, insn);
1790 reemit_notes (insn, insn);
1795 /* The following function returns maximal (or close to maximal) number
1796 of insns which can be issued on the same cycle and one of which
1797 insns is insns with the best rank (the last insn in READY). To
1798 make this function tries different samples of ready insns. READY
1799 is current queue `ready'. Global array READY_TRY reflects what
1800 insns are already issued in this try. STATE is current processor
1801 state. If the function returns nonzero, INDEX will contain index
1802 of the best insn in READY. The following function is used only for
1803 first cycle multipass scheduling. */
1806 max_issue (ready, state, index)
1807 struct ready_list *ready;
1811 int i, best, n, temp_index, delay;
1814 int max_lookahead = (*targetm.sched.first_cycle_multipass_dfa_lookahead) ();
1816 if (state_dead_lock_p (state))
1819 temp_state = alloca (dfa_state_size);
1822 for (i = 0; i < ready->n_ready; i++)
1825 insn = ready_element (ready, i);
1827 if (INSN_CODE (insn) < 0)
1830 memcpy (temp_state, state, dfa_state_size);
1832 delay = state_transition (temp_state, insn);
1836 if (!targetm.sched.dfa_bubble)
1844 (bubble = (*targetm.sched.dfa_bubble) (j)) != NULL_RTX;
1846 if (state_transition (temp_state, bubble) < 0
1847 && state_transition (temp_state, insn) < 0)
1850 if (bubble == NULL_RTX)
1859 if (max_lookahead < 0)
1864 n = max_issue (ready, temp_state, &temp_index);
1865 if (n > 0 || ready_try[0])
1879 /* The following function chooses insn from READY and modifies
1880 *N_READY and READY. The following function is used only for first
1881 cycle multipass scheduling. */
1884 choose_ready (ready)
1885 struct ready_list *ready;
1887 if (!targetm.sched.first_cycle_multipass_dfa_lookahead
1888 || (*targetm.sched.first_cycle_multipass_dfa_lookahead) () <= 0)
1889 return ready_remove_first (ready);
1892 /* Try to choose the better insn. */
1895 if (max_issue (ready, curr_state, &index) == 0)
1896 return ready_remove_first (ready);
1898 return ready_remove (ready, index);
1902 /* Called from backends from targetm.sched.reorder to emit stuff into
1903 the instruction stream. */
1906 sched_emit_insn (pat)
1909 rtx insn = emit_insn_after (pat, last_scheduled_insn);
1910 last_scheduled_insn = insn;
1914 /* Use forward list scheduling to rearrange insns of block B in region RGN,
1915 possibly bringing insns from subsequent blocks in the same region. */
1918 schedule_block (b, rgn_n_insns)
1922 struct ready_list ready;
1923 int first_cycle_insn_p;
1925 state_t temp_state = NULL; /* It is used for multipass scheduling. */
1927 /* Head/tail info for this block. */
1928 rtx prev_head = current_sched_info->prev_head;
1929 rtx next_tail = current_sched_info->next_tail;
1930 rtx head = NEXT_INSN (prev_head);
1931 rtx tail = PREV_INSN (next_tail);
1933 /* We used to have code to avoid getting parameters moved from hard
1934 argument registers into pseudos.
1936 However, it was removed when it proved to be of marginal benefit
1937 and caused problems because schedule_block and compute_forward_dependences
1938 had different notions of what the "head" insn was. */
1940 if (head == tail && (! INSN_P (head)))
1946 fprintf (sched_dump, ";; ======================================================\n");
1947 fprintf (sched_dump,
1948 ";; -- basic block %d from %d to %d -- %s reload\n",
1949 b, INSN_UID (head), INSN_UID (tail),
1950 (reload_completed ? "after" : "before"));
1951 fprintf (sched_dump, ";; ======================================================\n");
1952 fprintf (sched_dump, "\n");
1955 init_block_visualization ();
1958 if (targetm.sched.use_dfa_pipeline_interface
1959 && (*targetm.sched.use_dfa_pipeline_interface) ())
1960 state_reset (curr_state);
1964 /* Allocate the ready list. */
1965 ready.veclen = rgn_n_insns + 1 + issue_rate;
1966 ready.first = ready.veclen - 1;
1967 ready.vec = (rtx *) xmalloc (ready.veclen * sizeof (rtx));
1970 if (targetm.sched.use_dfa_pipeline_interface
1971 && (*targetm.sched.use_dfa_pipeline_interface) ())
1973 /* It is used for first cycle multipass scheduling. */
1974 temp_state = alloca (dfa_state_size);
1975 ready_try = (char *) xmalloc ((rgn_n_insns + 1) * sizeof (char));
1976 memset (ready_try, 0, (rgn_n_insns + 1) * sizeof (char));
1979 (*current_sched_info->init_ready_list) (&ready);
1981 if (targetm.sched.md_init)
1982 (*targetm.sched.md_init) (sched_dump, sched_verbose, ready.veclen);
1984 /* We start inserting insns after PREV_HEAD. */
1985 last_scheduled_insn = prev_head;
1987 /* Initialize INSN_QUEUE. Q_SIZE is the total number of insns in the
1992 if (!targetm.sched.use_dfa_pipeline_interface
1993 || !(*targetm.sched.use_dfa_pipeline_interface) ())
1994 max_insn_queue_index_macro_value = INSN_QUEUE_SIZE - 1;
1996 max_insn_queue_index_macro_value = max_insn_queue_index;
1998 insn_queue = (rtx *) alloca ((MAX_INSN_QUEUE_INDEX + 1) * sizeof (rtx));
1999 memset ((char *) insn_queue, 0, (MAX_INSN_QUEUE_INDEX + 1) * sizeof (rtx));
2000 last_clock_var = -1;
2002 /* Start just before the beginning of time. */
2005 /* Loop until all the insns in BB are scheduled. */
2006 while ((*current_sched_info->schedule_more_p) ())
2010 advance_one_cycle ();
2012 /* Add to the ready list all pending insns that can be issued now.
2013 If there are no ready insns, increment clock until one
2014 is ready and add all pending insns at that point to the ready
2016 queue_to_ready (&ready);
2018 if (sched_verbose && targetm.sched.cycle_display)
2020 = (*targetm.sched.cycle_display) (clock_var, last_scheduled_insn);
2022 if (ready.n_ready == 0)
2025 if (sched_verbose >= 2)
2027 fprintf (sched_dump, ";;\t\tReady list after queue_to_ready: ");
2028 debug_ready_list (&ready);
2031 /* Sort the ready list based on priority. */
2032 ready_sort (&ready);
2034 /* Allow the target to reorder the list, typically for
2035 better instruction bundling. */
2036 if (targetm.sched.reorder)
2038 (*targetm.sched.reorder) (sched_dump, sched_verbose,
2039 ready_lastpos (&ready),
2040 &ready.n_ready, clock_var);
2042 can_issue_more = issue_rate;
2044 first_cycle_insn_p = 1;
2052 fprintf (sched_dump, ";;\tReady list (t =%3d): ",
2054 debug_ready_list (&ready);
2057 if (!targetm.sched.use_dfa_pipeline_interface
2058 || !(*targetm.sched.use_dfa_pipeline_interface) ())
2060 if (ready.n_ready == 0 || !can_issue_more
2061 || !(*current_sched_info->schedule_more_p) ())
2063 insn = choose_ready (&ready);
2064 cost = actual_hazard (insn_unit (insn), insn, clock_var, 0);
2068 if (ready.n_ready == 0 || !can_issue_more
2069 || state_dead_lock_p (curr_state)
2070 || !(*current_sched_info->schedule_more_p) ())
2073 /* Select and remove the insn from the ready list. */
2074 insn = choose_ready (&ready);
2076 memcpy (temp_state, curr_state, dfa_state_size);
2077 if (recog_memoized (insn) < 0)
2079 if (!first_cycle_insn_p
2080 && (GET_CODE (PATTERN (insn)) == ASM_INPUT
2081 || asm_noperands (PATTERN (insn)) >= 0))
2082 /* This is asm insn which is tryed to be issued on the
2083 cycle not first. Issue it on the next cycle. */
2086 /* A USE insn, or something else we don't need to
2087 understand. We can't pass these directly to
2088 state_transition because it will trigger a
2089 fatal error for unrecognizable insns. */
2094 cost = state_transition (temp_state, insn);
2096 if (targetm.sched.first_cycle_multipass_dfa_lookahead
2097 && targetm.sched.dfa_bubble)
2105 (bubble = (*targetm.sched.dfa_bubble) (j))
2109 memcpy (temp_state, curr_state, dfa_state_size);
2111 if (state_transition (temp_state, bubble) < 0
2112 && state_transition (temp_state, insn) < 0)
2116 if (bubble != NULL_RTX)
2118 if (insert_schedule_bubbles_p)
2122 copy = copy_rtx (PATTERN (bubble));
2123 emit_insn_after (copy, last_scheduled_insn);
2125 = NEXT_INSN (last_scheduled_insn);
2126 INSN_CODE (last_scheduled_insn)
2127 = INSN_CODE (bubble);
2129 /* Annotate the same for the first insns
2130 scheduling by using mode. */
2131 PUT_MODE (last_scheduled_insn,
2132 (clock_var > last_clock_var
2133 ? clock_var - last_clock_var
2135 last_clock_var = clock_var;
2137 if (sched_verbose >= 2)
2139 fprintf (sched_dump,
2140 ";;\t\t--> scheduling bubble insn <<<%d>>>:reservation ",
2141 INSN_UID (last_scheduled_insn));
2143 if (recog_memoized (last_scheduled_insn)
2145 fprintf (sched_dump, "nothing");
2148 (sched_dump, last_scheduled_insn);
2150 fprintf (sched_dump, "\n");
2168 queue_insn (insn, cost);
2172 if (! (*current_sched_info->can_schedule_ready_p) (insn))
2175 last_scheduled_insn = move_insn (insn, last_scheduled_insn);
2177 if (targetm.sched.use_dfa_pipeline_interface
2178 && (*targetm.sched.use_dfa_pipeline_interface) ())
2179 memcpy (curr_state, temp_state, dfa_state_size);
2181 if (targetm.sched.variable_issue)
2183 (*targetm.sched.variable_issue) (sched_dump, sched_verbose,
2184 insn, can_issue_more);
2188 schedule_insn (insn, &ready, clock_var);
2191 first_cycle_insn_p = 0;
2193 if (targetm.sched.reorder2)
2195 /* Sort the ready list based on priority. */
2196 if (ready.n_ready > 0)
2197 ready_sort (&ready);
2199 (*targetm.sched.reorder2) (sched_dump,sched_verbose,
2201 ? ready_lastpos (&ready) : NULL,
2202 &ready.n_ready, clock_var);
2206 if ((!targetm.sched.use_dfa_pipeline_interface
2207 || !(*targetm.sched.use_dfa_pipeline_interface) ())
2210 visualize_scheduled_insns (clock_var);
2213 if (targetm.sched.md_finish)
2214 (*targetm.sched.md_finish) (sched_dump, sched_verbose);
2219 fprintf (sched_dump, ";;\tReady list (final): ");
2220 debug_ready_list (&ready);
2221 if (!targetm.sched.use_dfa_pipeline_interface
2222 || !(*targetm.sched.use_dfa_pipeline_interface) ())
2223 print_block_visualization ("");
2226 /* Sanity check -- queue must be empty now. Meaningless if region has
2228 if (current_sched_info->queue_must_finish_empty && q_size != 0)
2231 /* Update head/tail boundaries. */
2232 head = NEXT_INSN (prev_head);
2233 tail = last_scheduled_insn;
2235 /* Restore-other-notes: NOTE_LIST is the end of a chain of notes
2236 previously found among the insns. Insert them at the beginning
2240 rtx note_head = note_list;
2242 while (PREV_INSN (note_head))
2244 note_head = PREV_INSN (note_head);
2247 PREV_INSN (note_head) = PREV_INSN (head);
2248 NEXT_INSN (PREV_INSN (head)) = note_head;
2249 PREV_INSN (head) = note_list;
2250 NEXT_INSN (note_list) = head;
2257 fprintf (sched_dump, ";; total time = %d\n;; new head = %d\n",
2258 clock_var, INSN_UID (head));
2259 fprintf (sched_dump, ";; new tail = %d\n\n",
2264 current_sched_info->head = head;
2265 current_sched_info->tail = tail;
2269 if (targetm.sched.use_dfa_pipeline_interface
2270 && (*targetm.sched.use_dfa_pipeline_interface) ())
2274 /* Set_priorities: compute priority of each insn in the block. */
2277 set_priorities (head, tail)
2285 prev_head = PREV_INSN (head);
2287 if (head == tail && (! INSN_P (head)))
2291 for (insn = tail; insn != prev_head; insn = PREV_INSN (insn))
2293 if (GET_CODE (insn) == NOTE)
2296 if (!(SCHED_GROUP_P (insn)))
2298 (void) priority (insn);
2304 /* Initialize some global state for the scheduler. DUMP_FILE is to be used
2305 for debugging output. */
2308 sched_init (dump_file)
2315 /* Disable speculative loads in their presence if cc0 defined. */
2317 flag_schedule_speculative_load = 0;
2320 /* Set dump and sched_verbose for the desired debugging output. If no
2321 dump-file was specified, but -fsched-verbose=N (any N), print to stderr.
2322 For -fsched-verbose=N, N>=10, print everything to stderr. */
2323 sched_verbose = sched_verbose_param;
2324 if (sched_verbose_param == 0 && dump_file)
2326 sched_dump = ((sched_verbose_param >= 10 || !dump_file)
2327 ? stderr : dump_file);
2329 /* Initialize issue_rate. */
2330 if (targetm.sched.issue_rate)
2331 issue_rate = (*targetm.sched.issue_rate) ();
2335 /* We use LUID 0 for the fake insn (UID 0) which holds dependencies for
2336 pseudos which do not cross calls. */
2337 old_max_uid = get_max_uid () + 1;
2339 h_i_d = (struct haifa_insn_data *) xcalloc (old_max_uid, sizeof (*h_i_d));
2341 for (i = 0; i < old_max_uid; i++)
2342 h_i_d [i].cost = -1;
2344 if (targetm.sched.use_dfa_pipeline_interface
2345 && (*targetm.sched.use_dfa_pipeline_interface) ())
2347 if (targetm.sched.init_dfa_pre_cycle_insn)
2348 (*targetm.sched.init_dfa_pre_cycle_insn) ();
2350 if (targetm.sched.init_dfa_post_cycle_insn)
2351 (*targetm.sched.init_dfa_post_cycle_insn) ();
2353 if (targetm.sched.first_cycle_multipass_dfa_lookahead
2354 && targetm.sched.init_dfa_bubbles)
2355 (*targetm.sched.init_dfa_bubbles) ();
2358 dfa_state_size = state_size ();
2359 curr_state = xmalloc (dfa_state_size);
2364 for (b = 0; b < n_basic_blocks; b++)
2365 for (insn = BLOCK_HEAD (b);; insn = NEXT_INSN (insn))
2367 INSN_LUID (insn) = luid;
2369 /* Increment the next luid, unless this is a note. We don't
2370 really need separate IDs for notes and we don't want to
2371 schedule differently depending on whether or not there are
2372 line-number notes, i.e., depending on whether or not we're
2373 generating debugging information. */
2374 if (GET_CODE (insn) != NOTE)
2377 if (insn == BLOCK_END (b))
2381 init_dependency_caches (luid);
2383 compute_bb_for_insn (old_max_uid);
2385 init_alias_analysis ();
2387 if (write_symbols != NO_DEBUG)
2391 line_note_head = (rtx *) xcalloc (n_basic_blocks, sizeof (rtx));
2393 /* Save-line-note-head:
2394 Determine the line-number at the start of each basic block.
2395 This must be computed and saved now, because after a basic block's
2396 predecessor has been scheduled, it is impossible to accurately
2397 determine the correct line number for the first insn of the block. */
2399 for (b = 0; b < n_basic_blocks; b++)
2401 for (line = BLOCK_HEAD (b); line; line = PREV_INSN (line))
2402 if (GET_CODE (line) == NOTE && NOTE_LINE_NUMBER (line) > 0)
2404 line_note_head[b] = line;
2407 /* Do a forward search as well, since we won't get to see the first
2408 notes in a basic block. */
2409 for (line = BLOCK_HEAD (b); line; line = NEXT_INSN (line))
2413 if (GET_CODE (line) == NOTE && NOTE_LINE_NUMBER (line) > 0)
2414 line_note_head[b] = line;
2419 if ((!targetm.sched.use_dfa_pipeline_interface
2420 || !(*targetm.sched.use_dfa_pipeline_interface) ())
2422 /* Find units used in this function, for visualization. */
2423 init_target_units ();
2425 /* ??? Add a NOTE after the last insn of the last basic block. It is not
2426 known why this is done. */
2428 insn = BLOCK_END (n_basic_blocks - 1);
2429 if (NEXT_INSN (insn) == 0
2430 || (GET_CODE (insn) != NOTE
2431 && GET_CODE (insn) != CODE_LABEL
2432 /* Don't emit a NOTE if it would end up before a BARRIER. */
2433 && GET_CODE (NEXT_INSN (insn)) != BARRIER))
2435 emit_note_after (NOTE_INSN_DELETED, BLOCK_END (n_basic_blocks - 1));
2436 /* Make insn to appear outside BB. */
2437 BLOCK_END (n_basic_blocks - 1) = PREV_INSN (BLOCK_END (n_basic_blocks - 1));
2440 /* Compute INSN_REG_WEIGHT for all blocks. We must do this before
2441 removing death notes. */
2442 for (b = n_basic_blocks - 1; b >= 0; b--)
2443 find_insn_reg_weight (b);
2446 /* Free global data used during insn scheduling. */
2453 if (targetm.sched.use_dfa_pipeline_interface
2454 && (*targetm.sched.use_dfa_pipeline_interface) ())
2459 free_dependency_caches ();
2460 end_alias_analysis ();
2461 if (write_symbols != NO_DEBUG)
2462 free (line_note_head);
2464 #endif /* INSN_SCHEDULING */