1 /* Medium-level subroutines: convert bit-field store and extract
2 and shifts, multiplies and divides to rtl instructions.
3 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
4 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 2, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
26 #include "coretypes.h"
33 #include "insn-config.h"
38 #include "langhooks.h"
40 static void store_fixed_bit_field (rtx, unsigned HOST_WIDE_INT,
41 unsigned HOST_WIDE_INT,
42 unsigned HOST_WIDE_INT, rtx);
43 static void store_split_bit_field (rtx, unsigned HOST_WIDE_INT,
44 unsigned HOST_WIDE_INT, rtx);
45 static rtx extract_fixed_bit_field (enum machine_mode, rtx,
46 unsigned HOST_WIDE_INT,
47 unsigned HOST_WIDE_INT,
48 unsigned HOST_WIDE_INT, rtx, int);
49 static rtx mask_rtx (enum machine_mode, int, int, int);
50 static rtx lshift_value (enum machine_mode, rtx, int, int);
51 static rtx extract_split_bit_field (rtx, unsigned HOST_WIDE_INT,
52 unsigned HOST_WIDE_INT, int);
53 static void do_cmp_and_jump (rtx, rtx, enum rtx_code, enum machine_mode, rtx);
55 /* Nonzero means divides or modulus operations are relatively cheap for
56 powers of two, so don't use branches; emit the operation instead.
57 Usually, this will mean that the MD file will emit non-branch
60 static int sdiv_pow2_cheap[NUM_MACHINE_MODES];
61 static int smod_pow2_cheap[NUM_MACHINE_MODES];
63 #ifndef SLOW_UNALIGNED_ACCESS
64 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) STRICT_ALIGNMENT
67 /* For compilers that support multiple targets with different word sizes,
68 MAX_BITS_PER_WORD contains the biggest value of BITS_PER_WORD. An example
69 is the H8/300(H) compiler. */
71 #ifndef MAX_BITS_PER_WORD
72 #define MAX_BITS_PER_WORD BITS_PER_WORD
75 /* Reduce conditional compilation elsewhere. */
78 #define CODE_FOR_insv CODE_FOR_nothing
79 #define gen_insv(a,b,c,d) NULL_RTX
83 #define CODE_FOR_extv CODE_FOR_nothing
84 #define gen_extv(a,b,c,d) NULL_RTX
88 #define CODE_FOR_extzv CODE_FOR_nothing
89 #define gen_extzv(a,b,c,d) NULL_RTX
92 /* Cost of various pieces of RTL. Note that some of these are indexed by
93 shift count and some by mode. */
95 static int add_cost[NUM_MACHINE_MODES];
96 static int neg_cost[NUM_MACHINE_MODES];
97 static int shift_cost[NUM_MACHINE_MODES][MAX_BITS_PER_WORD];
98 static int shiftadd_cost[NUM_MACHINE_MODES][MAX_BITS_PER_WORD];
99 static int shiftsub_cost[NUM_MACHINE_MODES][MAX_BITS_PER_WORD];
100 static int mul_cost[NUM_MACHINE_MODES];
101 static int div_cost[NUM_MACHINE_MODES];
102 static int mul_widen_cost[NUM_MACHINE_MODES];
103 static int mul_highpart_cost[NUM_MACHINE_MODES];
108 rtx reg, shift_insn, shiftadd_insn, shiftsub_insn;
109 rtx shift_pat, shiftadd_pat, shiftsub_pat;
110 rtx pow2[MAX_BITS_PER_WORD];
111 rtx cint[MAX_BITS_PER_WORD];
114 enum machine_mode mode, wider_mode;
118 zero_cost = rtx_cost (const0_rtx, 0);
122 for (m = 1; m < MAX_BITS_PER_WORD; m++)
124 pow2[m] = GEN_INT ((HOST_WIDE_INT) 1 << m);
125 cint[m] = GEN_INT (m);
128 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
130 mode = GET_MODE_WIDER_MODE (mode))
132 reg = gen_rtx_REG (mode, 10000);
133 add_cost[mode] = rtx_cost (gen_rtx_PLUS (mode, reg, reg), SET);
134 neg_cost[mode] = rtx_cost (gen_rtx_NEG (mode, reg), SET);
135 div_cost[mode] = rtx_cost (gen_rtx_UDIV (mode, reg, reg), SET);
136 mul_cost[mode] = rtx_cost (gen_rtx_MULT (mode, reg, reg), SET);
138 sdiv_pow2_cheap[mode]
139 = (rtx_cost (gen_rtx_DIV (mode, reg, GEN_INT (32)), SET)
140 <= 2 * add_cost[mode]);
141 smod_pow2_cheap[mode]
142 = (rtx_cost (gen_rtx_MOD (mode, reg, GEN_INT (32)), SET)
143 <= 2 * add_cost[mode]);
145 wider_mode = GET_MODE_WIDER_MODE (mode);
146 if (wider_mode != VOIDmode)
148 mul_widen_cost[wider_mode]
149 = rtx_cost (gen_rtx_MULT (wider_mode,
150 gen_rtx_ZERO_EXTEND (wider_mode, reg),
151 gen_rtx_ZERO_EXTEND (wider_mode, reg)),
153 mul_highpart_cost[mode]
154 = rtx_cost (gen_rtx_TRUNCATE
156 gen_rtx_LSHIFTRT (wider_mode,
157 gen_rtx_MULT (wider_mode,
162 GEN_INT (GET_MODE_BITSIZE (mode)))),
166 shift_insn = emit_insn (gen_rtx_SET (VOIDmode, reg,
167 gen_rtx_ASHIFT (mode, reg,
171 = emit_insn (gen_rtx_SET (VOIDmode, reg,
179 = emit_insn (gen_rtx_SET (VOIDmode, reg,
186 shift_pat = PATTERN (shift_insn);
187 shiftadd_pat = PATTERN (shiftadd_insn);
188 shiftsub_pat = PATTERN (shiftsub_insn);
190 shift_cost[mode][0] = 0;
191 shiftadd_cost[mode][0] = shiftsub_cost[mode][0] = add_cost[mode];
193 n = MIN (MAX_BITS_PER_WORD, GET_MODE_BITSIZE (mode));
194 for (m = 1; m < n; m++)
196 shift_cost[mode][m] = 32000;
197 XEXP (SET_SRC (shift_pat), 1) = cint[m];
198 if (recog (shift_pat, shift_insn, &dummy) >= 0)
199 shift_cost[mode][m] = rtx_cost (SET_SRC (shift_pat), SET);
201 shiftadd_cost[mode][m] = 32000;
202 XEXP (XEXP (SET_SRC (shiftadd_pat), 0), 1) = pow2[m];
203 if (recog (shiftadd_pat, shiftadd_insn, &dummy) >= 0)
204 shiftadd_cost[mode][m] = rtx_cost (SET_SRC (shiftadd_pat), SET);
206 shiftsub_cost[mode][m] = 32000;
207 XEXP (XEXP (SET_SRC (shiftsub_pat), 0), 1) = pow2[m];
208 if (recog (shiftsub_pat, shiftsub_insn, &dummy) >= 0)
209 shiftsub_cost[mode][m] = rtx_cost (SET_SRC (shiftsub_pat), SET);
216 /* Return an rtx representing minus the value of X.
217 MODE is the intended mode of the result,
218 useful if X is a CONST_INT. */
221 negate_rtx (enum machine_mode mode, rtx x)
223 rtx result = simplify_unary_operation (NEG, mode, x, mode);
226 result = expand_unop (mode, neg_optab, x, NULL_RTX, 0);
231 /* Report on the availability of insv/extv/extzv and the desired mode
232 of each of their operands. Returns MAX_MACHINE_MODE if HAVE_foo
233 is false; else the mode of the specified operand. If OPNO is -1,
234 all the caller cares about is whether the insn is available. */
236 mode_for_extraction (enum extraction_pattern pattern, int opno)
238 const struct insn_data *data;
245 data = &insn_data[CODE_FOR_insv];
248 return MAX_MACHINE_MODE;
253 data = &insn_data[CODE_FOR_extv];
256 return MAX_MACHINE_MODE;
261 data = &insn_data[CODE_FOR_extzv];
264 return MAX_MACHINE_MODE;
273 /* Everyone who uses this function used to follow it with
274 if (result == VOIDmode) result = word_mode; */
275 if (data->operand[opno].mode == VOIDmode)
277 return data->operand[opno].mode;
281 /* Generate code to store value from rtx VALUE
282 into a bit-field within structure STR_RTX
283 containing BITSIZE bits starting at bit BITNUM.
284 FIELDMODE is the machine-mode of the FIELD_DECL node for this field.
285 ALIGN is the alignment that STR_RTX is known to have.
286 TOTAL_SIZE is the size of the structure in bytes, or -1 if varying. */
288 /* ??? Note that there are two different ideas here for how
289 to determine the size to count bits within, for a register.
290 One is BITS_PER_WORD, and the other is the size of operand 3
293 If operand 3 of the insv pattern is VOIDmode, then we will use BITS_PER_WORD
294 else, we use the mode of operand 3. */
297 store_bit_field (rtx str_rtx, unsigned HOST_WIDE_INT bitsize,
298 unsigned HOST_WIDE_INT bitnum, enum machine_mode fieldmode,
299 rtx value, HOST_WIDE_INT total_size)
302 = (GET_CODE (str_rtx) == MEM) ? BITS_PER_UNIT : BITS_PER_WORD;
303 unsigned HOST_WIDE_INT offset = bitnum / unit;
304 unsigned HOST_WIDE_INT bitpos = bitnum % unit;
308 enum machine_mode op_mode = mode_for_extraction (EP_insv, 3);
310 /* Discount the part of the structure before the desired byte.
311 We need to know how many bytes are safe to reference after it. */
313 total_size -= (bitpos / BIGGEST_ALIGNMENT
314 * (BIGGEST_ALIGNMENT / BITS_PER_UNIT));
316 while (GET_CODE (op0) == SUBREG)
318 /* The following line once was done only if WORDS_BIG_ENDIAN,
319 but I think that is a mistake. WORDS_BIG_ENDIAN is
320 meaningful at a much higher level; when structures are copied
321 between memory and regs, the higher-numbered regs
322 always get higher addresses. */
323 offset += (SUBREG_BYTE (op0) / UNITS_PER_WORD);
324 /* We used to adjust BITPOS here, but now we do the whole adjustment
325 right after the loop. */
326 op0 = SUBREG_REG (op0);
329 value = protect_from_queue (value, 0);
331 /* Use vec_extract patterns for extracting parts of vectors whenever
333 if (VECTOR_MODE_P (GET_MODE (op0))
334 && GET_CODE (op0) != MEM
335 && (vec_set_optab->handlers[GET_MODE (op0)].insn_code
337 && fieldmode == GET_MODE_INNER (GET_MODE (op0))
338 && bitsize == GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0)))
339 && !(bitnum % GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0)))))
341 enum machine_mode outermode = GET_MODE (op0);
342 enum machine_mode innermode = GET_MODE_INNER (outermode);
343 int icode = (int) vec_set_optab->handlers[outermode].insn_code;
344 int pos = bitnum / GET_MODE_BITSIZE (innermode);
345 rtx rtxpos = GEN_INT (pos);
349 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
350 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
351 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
355 if (! (*insn_data[icode].operand[1].predicate) (src, mode1))
356 src = copy_to_mode_reg (mode1, src);
358 if (! (*insn_data[icode].operand[2].predicate) (rtxpos, mode2))
359 rtxpos = copy_to_mode_reg (mode1, rtxpos);
361 /* We could handle this, but we should always be called with a pseudo
362 for our targets and all insns should take them as outputs. */
363 if (! (*insn_data[icode].operand[0].predicate) (dest, mode0)
364 || ! (*insn_data[icode].operand[1].predicate) (src, mode1)
365 || ! (*insn_data[icode].operand[2].predicate) (rtxpos, mode2))
367 pat = GEN_FCN (icode) (dest, src, rtxpos);
380 int old_generating_concat_p = generating_concat_p;
381 generating_concat_p = 0;
382 value = force_not_mem (value);
383 generating_concat_p = old_generating_concat_p;
386 /* If the target is a register, overwriting the entire object, or storing
387 a full-word or multi-word field can be done with just a SUBREG.
389 If the target is memory, storing any naturally aligned field can be
390 done with a simple store. For targets that support fast unaligned
391 memory, any naturally sized, unit aligned field can be done directly. */
393 byte_offset = (bitnum % BITS_PER_WORD) / BITS_PER_UNIT
394 + (offset * UNITS_PER_WORD);
397 && bitsize == GET_MODE_BITSIZE (fieldmode)
398 && (GET_CODE (op0) != MEM
399 ? ((GET_MODE_SIZE (fieldmode) >= UNITS_PER_WORD
400 || GET_MODE_SIZE (GET_MODE (op0)) == GET_MODE_SIZE (fieldmode))
401 && byte_offset % GET_MODE_SIZE (fieldmode) == 0)
402 : (! SLOW_UNALIGNED_ACCESS (fieldmode, MEM_ALIGN (op0))
403 || (offset * BITS_PER_UNIT % bitsize == 0
404 && MEM_ALIGN (op0) % GET_MODE_BITSIZE (fieldmode) == 0))))
406 if (GET_MODE (op0) != fieldmode)
408 if (GET_CODE (op0) == SUBREG)
410 if (GET_MODE (SUBREG_REG (op0)) == fieldmode
411 || GET_MODE_CLASS (fieldmode) == MODE_INT
412 || GET_MODE_CLASS (fieldmode) == MODE_PARTIAL_INT)
413 op0 = SUBREG_REG (op0);
415 /* Else we've got some float mode source being extracted into
416 a different float mode destination -- this combination of
417 subregs results in Severe Tire Damage. */
420 if (GET_CODE (op0) == REG)
421 op0 = gen_rtx_SUBREG (fieldmode, op0, byte_offset);
423 op0 = adjust_address (op0, fieldmode, offset);
425 emit_move_insn (op0, value);
429 /* Make sure we are playing with integral modes. Pun with subregs
430 if we aren't. This must come after the entire register case above,
431 since that case is valid for any mode. The following cases are only
432 valid for integral modes. */
434 enum machine_mode imode = int_mode_for_mode (GET_MODE (op0));
435 if (imode != GET_MODE (op0))
437 if (GET_CODE (op0) == MEM)
438 op0 = adjust_address (op0, imode, 0);
439 else if (imode != BLKmode)
440 op0 = gen_lowpart (imode, op0);
446 /* We may be accessing data outside the field, which means
447 we can alias adjacent data. */
448 if (GET_CODE (op0) == MEM)
450 op0 = shallow_copy_rtx (op0);
451 set_mem_alias_set (op0, 0);
452 set_mem_expr (op0, 0);
455 /* If OP0 is a register, BITPOS must count within a word.
456 But as we have it, it counts within whatever size OP0 now has.
457 On a bigendian machine, these are not the same, so convert. */
459 && GET_CODE (op0) != MEM
460 && unit > GET_MODE_BITSIZE (GET_MODE (op0)))
461 bitpos += unit - GET_MODE_BITSIZE (GET_MODE (op0));
463 /* Storing an lsb-aligned field in a register
464 can be done with a movestrict instruction. */
466 if (GET_CODE (op0) != MEM
467 && (BYTES_BIG_ENDIAN ? bitpos + bitsize == unit : bitpos == 0)
468 && bitsize == GET_MODE_BITSIZE (fieldmode)
469 && (movstrict_optab->handlers[fieldmode].insn_code
470 != CODE_FOR_nothing))
472 int icode = movstrict_optab->handlers[fieldmode].insn_code;
474 /* Get appropriate low part of the value being stored. */
475 if (GET_CODE (value) == CONST_INT || GET_CODE (value) == REG)
476 value = gen_lowpart (fieldmode, value);
477 else if (!(GET_CODE (value) == SYMBOL_REF
478 || GET_CODE (value) == LABEL_REF
479 || GET_CODE (value) == CONST))
480 value = convert_to_mode (fieldmode, value, 0);
482 if (! (*insn_data[icode].operand[1].predicate) (value, fieldmode))
483 value = copy_to_mode_reg (fieldmode, value);
485 if (GET_CODE (op0) == SUBREG)
487 if (GET_MODE (SUBREG_REG (op0)) == fieldmode
488 || GET_MODE_CLASS (fieldmode) == MODE_INT
489 || GET_MODE_CLASS (fieldmode) == MODE_PARTIAL_INT)
490 op0 = SUBREG_REG (op0);
492 /* Else we've got some float mode source being extracted into
493 a different float mode destination -- this combination of
494 subregs results in Severe Tire Damage. */
498 emit_insn (GEN_FCN (icode)
499 (gen_rtx_SUBREG (fieldmode, op0,
500 (bitnum % BITS_PER_WORD) / BITS_PER_UNIT
501 + (offset * UNITS_PER_WORD)),
507 /* Handle fields bigger than a word. */
509 if (bitsize > BITS_PER_WORD)
511 /* Here we transfer the words of the field
512 in the order least significant first.
513 This is because the most significant word is the one which may
515 However, only do that if the value is not BLKmode. */
517 unsigned int backwards = WORDS_BIG_ENDIAN && fieldmode != BLKmode;
518 unsigned int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD;
521 /* This is the mode we must force value to, so that there will be enough
522 subwords to extract. Note that fieldmode will often (always?) be
523 VOIDmode, because that is what store_field uses to indicate that this
524 is a bit field, but passing VOIDmode to operand_subword_force will
525 result in an abort. */
526 fieldmode = GET_MODE (value);
527 if (fieldmode == VOIDmode)
528 fieldmode = smallest_mode_for_size (nwords * BITS_PER_WORD, MODE_INT);
530 for (i = 0; i < nwords; i++)
532 /* If I is 0, use the low-order word in both field and target;
533 if I is 1, use the next to lowest word; and so on. */
534 unsigned int wordnum = (backwards ? nwords - i - 1 : i);
535 unsigned int bit_offset = (backwards
536 ? MAX ((int) bitsize - ((int) i + 1)
539 : (int) i * BITS_PER_WORD);
541 store_bit_field (op0, MIN (BITS_PER_WORD,
542 bitsize - i * BITS_PER_WORD),
543 bitnum + bit_offset, word_mode,
544 operand_subword_force (value, wordnum, fieldmode),
550 /* From here on we can assume that the field to be stored in is
551 a full-word (whatever type that is), since it is shorter than a word. */
553 /* OFFSET is the number of words or bytes (UNIT says which)
554 from STR_RTX to the first word or byte containing part of the field. */
556 if (GET_CODE (op0) != MEM)
559 || GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD)
561 if (GET_CODE (op0) != REG)
563 /* Since this is a destination (lvalue), we can't copy it to a
564 pseudo. We can trivially remove a SUBREG that does not
565 change the size of the operand. Such a SUBREG may have been
566 added above. Otherwise, abort. */
567 if (GET_CODE (op0) == SUBREG
568 && (GET_MODE_SIZE (GET_MODE (op0))
569 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0)))))
570 op0 = SUBREG_REG (op0);
574 op0 = gen_rtx_SUBREG (mode_for_size (BITS_PER_WORD, MODE_INT, 0),
575 op0, (offset * UNITS_PER_WORD));
580 op0 = protect_from_queue (op0, 1);
582 /* If VALUE is a floating-point mode, access it as an integer of the
583 corresponding size. This can occur on a machine with 64 bit registers
584 that uses SFmode for float. This can also occur for unaligned float
586 if (GET_MODE_CLASS (GET_MODE (value)) != MODE_INT
587 && GET_MODE_CLASS (GET_MODE (value)) != MODE_PARTIAL_INT)
588 value = gen_lowpart ((GET_MODE (value) == VOIDmode
589 ? word_mode : int_mode_for_mode (GET_MODE (value))),
592 /* Now OFFSET is nonzero only if OP0 is memory
593 and is therefore always measured in bytes. */
596 && GET_MODE (value) != BLKmode
597 && !(bitsize == 1 && GET_CODE (value) == CONST_INT)
598 /* Ensure insv's size is wide enough for this field. */
599 && (GET_MODE_BITSIZE (op_mode) >= bitsize)
600 && ! ((GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
601 && (bitsize + bitpos > GET_MODE_BITSIZE (op_mode))))
603 int xbitpos = bitpos;
606 rtx last = get_last_insn ();
608 enum machine_mode maxmode = mode_for_extraction (EP_insv, 3);
609 int save_volatile_ok = volatile_ok;
613 /* If this machine's insv can only insert into a register, copy OP0
614 into a register and save it back later. */
615 /* This used to check flag_force_mem, but that was a serious
616 de-optimization now that flag_force_mem is enabled by -O2. */
617 if (GET_CODE (op0) == MEM
618 && ! ((*insn_data[(int) CODE_FOR_insv].operand[0].predicate)
622 enum machine_mode bestmode;
624 /* Get the mode to use for inserting into this field. If OP0 is
625 BLKmode, get the smallest mode consistent with the alignment. If
626 OP0 is a non-BLKmode object that is no wider than MAXMODE, use its
627 mode. Otherwise, use the smallest mode containing the field. */
629 if (GET_MODE (op0) == BLKmode
630 || GET_MODE_SIZE (GET_MODE (op0)) > GET_MODE_SIZE (maxmode))
632 = get_best_mode (bitsize, bitnum, MEM_ALIGN (op0), maxmode,
633 MEM_VOLATILE_P (op0));
635 bestmode = GET_MODE (op0);
637 if (bestmode == VOIDmode
638 || (SLOW_UNALIGNED_ACCESS (bestmode, MEM_ALIGN (op0))
639 && GET_MODE_BITSIZE (bestmode) > MEM_ALIGN (op0)))
642 /* Adjust address to point to the containing unit of that mode.
643 Compute offset as multiple of this unit, counting in bytes. */
644 unit = GET_MODE_BITSIZE (bestmode);
645 offset = (bitnum / unit) * GET_MODE_SIZE (bestmode);
646 bitpos = bitnum % unit;
647 op0 = adjust_address (op0, bestmode, offset);
649 /* Fetch that unit, store the bitfield in it, then store
651 tempreg = copy_to_reg (op0);
652 store_bit_field (tempreg, bitsize, bitpos, fieldmode, value,
654 emit_move_insn (op0, tempreg);
657 volatile_ok = save_volatile_ok;
659 /* Add OFFSET into OP0's address. */
660 if (GET_CODE (xop0) == MEM)
661 xop0 = adjust_address (xop0, byte_mode, offset);
663 /* If xop0 is a register, we need it in MAXMODE
664 to make it acceptable to the format of insv. */
665 if (GET_CODE (xop0) == SUBREG)
666 /* We can't just change the mode, because this might clobber op0,
667 and we will need the original value of op0 if insv fails. */
668 xop0 = gen_rtx_SUBREG (maxmode, SUBREG_REG (xop0), SUBREG_BYTE (xop0));
669 if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode)
670 xop0 = gen_rtx_SUBREG (maxmode, xop0, 0);
672 /* On big-endian machines, we count bits from the most significant.
673 If the bit field insn does not, we must invert. */
675 if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
676 xbitpos = unit - bitsize - xbitpos;
678 /* We have been counting XBITPOS within UNIT.
679 Count instead within the size of the register. */
680 if (BITS_BIG_ENDIAN && GET_CODE (xop0) != MEM)
681 xbitpos += GET_MODE_BITSIZE (maxmode) - unit;
683 unit = GET_MODE_BITSIZE (maxmode);
685 /* Convert VALUE to maxmode (which insv insn wants) in VALUE1. */
687 if (GET_MODE (value) != maxmode)
689 if (GET_MODE_BITSIZE (GET_MODE (value)) >= bitsize)
691 /* Optimization: Don't bother really extending VALUE
692 if it has all the bits we will actually use. However,
693 if we must narrow it, be sure we do it correctly. */
695 if (GET_MODE_SIZE (GET_MODE (value)) < GET_MODE_SIZE (maxmode))
699 tmp = simplify_subreg (maxmode, value1, GET_MODE (value), 0);
701 tmp = simplify_gen_subreg (maxmode,
702 force_reg (GET_MODE (value),
704 GET_MODE (value), 0);
708 value1 = gen_lowpart (maxmode, value1);
710 else if (GET_CODE (value) == CONST_INT)
711 value1 = gen_int_mode (INTVAL (value), maxmode);
712 else if (!CONSTANT_P (value))
713 /* Parse phase is supposed to make VALUE's data type
714 match that of the component reference, which is a type
715 at least as wide as the field; so VALUE should have
716 a mode that corresponds to that type. */
720 /* If this machine's insv insists on a register,
721 get VALUE1 into a register. */
722 if (! ((*insn_data[(int) CODE_FOR_insv].operand[3].predicate)
724 value1 = force_reg (maxmode, value1);
726 pat = gen_insv (xop0, GEN_INT (bitsize), GEN_INT (xbitpos), value1);
731 delete_insns_since (last);
732 store_fixed_bit_field (op0, offset, bitsize, bitpos, value);
737 /* Insv is not available; store using shifts and boolean ops. */
738 store_fixed_bit_field (op0, offset, bitsize, bitpos, value);
742 /* Use shifts and boolean operations to store VALUE
743 into a bit field of width BITSIZE
744 in a memory location specified by OP0 except offset by OFFSET bytes.
745 (OFFSET must be 0 if OP0 is a register.)
746 The field starts at position BITPOS within the byte.
747 (If OP0 is a register, it may be a full word or a narrower mode,
748 but BITPOS still counts within a full word,
749 which is significant on bigendian machines.)
751 Note that protect_from_queue has already been done on OP0 and VALUE. */
754 store_fixed_bit_field (rtx op0, unsigned HOST_WIDE_INT offset,
755 unsigned HOST_WIDE_INT bitsize,
756 unsigned HOST_WIDE_INT bitpos, rtx value)
758 enum machine_mode mode;
759 unsigned int total_bits = BITS_PER_WORD;
764 /* There is a case not handled here:
765 a structure with a known alignment of just a halfword
766 and a field split across two aligned halfwords within the structure.
767 Or likewise a structure with a known alignment of just a byte
768 and a field split across two bytes.
769 Such cases are not supposed to be able to occur. */
771 if (GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
775 /* Special treatment for a bit field split across two registers. */
776 if (bitsize + bitpos > BITS_PER_WORD)
778 store_split_bit_field (op0, bitsize, bitpos, value);
784 /* Get the proper mode to use for this field. We want a mode that
785 includes the entire field. If such a mode would be larger than
786 a word, we won't be doing the extraction the normal way.
787 We don't want a mode bigger than the destination. */
789 mode = GET_MODE (op0);
790 if (GET_MODE_BITSIZE (mode) == 0
791 || GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (word_mode))
793 mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT,
794 MEM_ALIGN (op0), mode, MEM_VOLATILE_P (op0));
796 if (mode == VOIDmode)
798 /* The only way this should occur is if the field spans word
800 store_split_bit_field (op0, bitsize, bitpos + offset * BITS_PER_UNIT,
805 total_bits = GET_MODE_BITSIZE (mode);
807 /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to
808 be in the range 0 to total_bits-1, and put any excess bytes in
810 if (bitpos >= total_bits)
812 offset += (bitpos / total_bits) * (total_bits / BITS_PER_UNIT);
813 bitpos -= ((bitpos / total_bits) * (total_bits / BITS_PER_UNIT)
817 /* Get ref to an aligned byte, halfword, or word containing the field.
818 Adjust BITPOS to be position within a word,
819 and OFFSET to be the offset of that word.
820 Then alter OP0 to refer to that word. */
821 bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT;
822 offset -= (offset % (total_bits / BITS_PER_UNIT));
823 op0 = adjust_address (op0, mode, offset);
826 mode = GET_MODE (op0);
828 /* Now MODE is either some integral mode for a MEM as OP0,
829 or is a full-word for a REG as OP0. TOTAL_BITS corresponds.
830 The bit field is contained entirely within OP0.
831 BITPOS is the starting bit number within OP0.
832 (OP0's mode may actually be narrower than MODE.) */
834 if (BYTES_BIG_ENDIAN)
835 /* BITPOS is the distance between our msb
836 and that of the containing datum.
837 Convert it to the distance from the lsb. */
838 bitpos = total_bits - bitsize - bitpos;
840 /* Now BITPOS is always the distance between our lsb
843 /* Shift VALUE left by BITPOS bits. If VALUE is not constant,
844 we must first convert its mode to MODE. */
846 if (GET_CODE (value) == CONST_INT)
848 HOST_WIDE_INT v = INTVAL (value);
850 if (bitsize < HOST_BITS_PER_WIDE_INT)
851 v &= ((HOST_WIDE_INT) 1 << bitsize) - 1;
855 else if ((bitsize < HOST_BITS_PER_WIDE_INT
856 && v == ((HOST_WIDE_INT) 1 << bitsize) - 1)
857 || (bitsize == HOST_BITS_PER_WIDE_INT && v == -1))
860 value = lshift_value (mode, value, bitpos, bitsize);
864 int must_and = (GET_MODE_BITSIZE (GET_MODE (value)) != bitsize
865 && bitpos + bitsize != GET_MODE_BITSIZE (mode));
867 if (GET_MODE (value) != mode)
869 if ((GET_CODE (value) == REG || GET_CODE (value) == SUBREG)
870 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (value)))
871 value = gen_lowpart (mode, value);
873 value = convert_to_mode (mode, value, 1);
877 value = expand_binop (mode, and_optab, value,
878 mask_rtx (mode, 0, bitsize, 0),
879 NULL_RTX, 1, OPTAB_LIB_WIDEN);
881 value = expand_shift (LSHIFT_EXPR, mode, value,
882 build_int_2 (bitpos, 0), NULL_RTX, 1);
885 /* Now clear the chosen bits in OP0,
886 except that if VALUE is -1 we need not bother. */
888 subtarget = (GET_CODE (op0) == REG || ! flag_force_mem) ? op0 : 0;
892 temp = expand_binop (mode, and_optab, op0,
893 mask_rtx (mode, bitpos, bitsize, 1),
894 subtarget, 1, OPTAB_LIB_WIDEN);
900 /* Now logical-or VALUE into OP0, unless it is zero. */
903 temp = expand_binop (mode, ior_optab, temp, value,
904 subtarget, 1, OPTAB_LIB_WIDEN);
906 emit_move_insn (op0, temp);
909 /* Store a bit field that is split across multiple accessible memory objects.
911 OP0 is the REG, SUBREG or MEM rtx for the first of the objects.
912 BITSIZE is the field width; BITPOS the position of its first bit
914 VALUE is the value to store.
916 This does not yet handle fields wider than BITS_PER_WORD. */
919 store_split_bit_field (rtx op0, unsigned HOST_WIDE_INT bitsize,
920 unsigned HOST_WIDE_INT bitpos, rtx value)
923 unsigned int bitsdone = 0;
925 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
927 if (GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
928 unit = BITS_PER_WORD;
930 unit = MIN (MEM_ALIGN (op0), BITS_PER_WORD);
932 /* If VALUE is a constant other than a CONST_INT, get it into a register in
933 WORD_MODE. If we can do this using gen_lowpart_common, do so. Note
934 that VALUE might be a floating-point constant. */
935 if (CONSTANT_P (value) && GET_CODE (value) != CONST_INT)
937 rtx word = gen_lowpart_common (word_mode, value);
939 if (word && (value != word))
942 value = gen_lowpart_common (word_mode,
943 force_reg (GET_MODE (value) != VOIDmode
945 : word_mode, value));
947 else if (GET_CODE (value) == ADDRESSOF)
948 value = copy_to_reg (value);
950 while (bitsdone < bitsize)
952 unsigned HOST_WIDE_INT thissize;
954 unsigned HOST_WIDE_INT thispos;
955 unsigned HOST_WIDE_INT offset;
957 offset = (bitpos + bitsdone) / unit;
958 thispos = (bitpos + bitsdone) % unit;
960 /* THISSIZE must not overrun a word boundary. Otherwise,
961 store_fixed_bit_field will call us again, and we will mutually
963 thissize = MIN (bitsize - bitsdone, BITS_PER_WORD);
964 thissize = MIN (thissize, unit - thispos);
966 if (BYTES_BIG_ENDIAN)
970 /* We must do an endian conversion exactly the same way as it is
971 done in extract_bit_field, so that the two calls to
972 extract_fixed_bit_field will have comparable arguments. */
973 if (GET_CODE (value) != MEM || GET_MODE (value) == BLKmode)
974 total_bits = BITS_PER_WORD;
976 total_bits = GET_MODE_BITSIZE (GET_MODE (value));
978 /* Fetch successively less significant portions. */
979 if (GET_CODE (value) == CONST_INT)
980 part = GEN_INT (((unsigned HOST_WIDE_INT) (INTVAL (value))
981 >> (bitsize - bitsdone - thissize))
982 & (((HOST_WIDE_INT) 1 << thissize) - 1));
984 /* The args are chosen so that the last part includes the
985 lsb. Give extract_bit_field the value it needs (with
986 endianness compensation) to fetch the piece we want. */
987 part = extract_fixed_bit_field (word_mode, value, 0, thissize,
988 total_bits - bitsize + bitsdone,
993 /* Fetch successively more significant portions. */
994 if (GET_CODE (value) == CONST_INT)
995 part = GEN_INT (((unsigned HOST_WIDE_INT) (INTVAL (value))
997 & (((HOST_WIDE_INT) 1 << thissize) - 1));
999 part = extract_fixed_bit_field (word_mode, value, 0, thissize,
1000 bitsdone, NULL_RTX, 1);
1003 /* If OP0 is a register, then handle OFFSET here.
1005 When handling multiword bitfields, extract_bit_field may pass
1006 down a word_mode SUBREG of a larger REG for a bitfield that actually
1007 crosses a word boundary. Thus, for a SUBREG, we must find
1008 the current word starting from the base register. */
1009 if (GET_CODE (op0) == SUBREG)
1011 int word_offset = (SUBREG_BYTE (op0) / UNITS_PER_WORD) + offset;
1012 word = operand_subword_force (SUBREG_REG (op0), word_offset,
1013 GET_MODE (SUBREG_REG (op0)));
1016 else if (GET_CODE (op0) == REG)
1018 word = operand_subword_force (op0, offset, GET_MODE (op0));
1024 /* OFFSET is in UNITs, and UNIT is in bits.
1025 store_fixed_bit_field wants offset in bytes. */
1026 store_fixed_bit_field (word, offset * unit / BITS_PER_UNIT, thissize,
1028 bitsdone += thissize;
1032 /* Generate code to extract a byte-field from STR_RTX
1033 containing BITSIZE bits, starting at BITNUM,
1034 and put it in TARGET if possible (if TARGET is nonzero).
1035 Regardless of TARGET, we return the rtx for where the value is placed.
1038 STR_RTX is the structure containing the byte (a REG or MEM).
1039 UNSIGNEDP is nonzero if this is an unsigned bit field.
1040 MODE is the natural mode of the field value once extracted.
1041 TMODE is the mode the caller would like the value to have;
1042 but the value may be returned with type MODE instead.
1044 TOTAL_SIZE is the size in bytes of the containing structure,
1047 If a TARGET is specified and we can store in it at no extra cost,
1048 we do so, and return TARGET.
1049 Otherwise, we return a REG of mode TMODE or MODE, with TMODE preferred
1050 if they are equally easy. */
1053 extract_bit_field (rtx str_rtx, unsigned HOST_WIDE_INT bitsize,
1054 unsigned HOST_WIDE_INT bitnum, int unsignedp, rtx target,
1055 enum machine_mode mode, enum machine_mode tmode,
1056 HOST_WIDE_INT total_size)
1059 = (GET_CODE (str_rtx) == MEM) ? BITS_PER_UNIT : BITS_PER_WORD;
1060 unsigned HOST_WIDE_INT offset = bitnum / unit;
1061 unsigned HOST_WIDE_INT bitpos = bitnum % unit;
1063 rtx spec_target = target;
1064 rtx spec_target_subreg = 0;
1065 enum machine_mode int_mode;
1066 enum machine_mode extv_mode = mode_for_extraction (EP_extv, 0);
1067 enum machine_mode extzv_mode = mode_for_extraction (EP_extzv, 0);
1068 enum machine_mode mode1;
1071 /* Discount the part of the structure before the desired byte.
1072 We need to know how many bytes are safe to reference after it. */
1073 if (total_size >= 0)
1074 total_size -= (bitpos / BIGGEST_ALIGNMENT
1075 * (BIGGEST_ALIGNMENT / BITS_PER_UNIT));
1077 if (tmode == VOIDmode)
1080 while (GET_CODE (op0) == SUBREG)
1082 bitpos += SUBREG_BYTE (op0) * BITS_PER_UNIT;
1085 offset += (bitpos / unit);
1088 op0 = SUBREG_REG (op0);
1091 if (GET_CODE (op0) == REG
1092 && mode == GET_MODE (op0)
1094 && bitsize == GET_MODE_BITSIZE (GET_MODE (op0)))
1096 /* We're trying to extract a full register from itself. */
1100 /* Use vec_extract patterns for extracting parts of vectors whenever
1102 if (VECTOR_MODE_P (GET_MODE (op0))
1103 && GET_CODE (op0) != MEM
1104 && (vec_extract_optab->handlers[GET_MODE (op0)].insn_code
1105 != CODE_FOR_nothing)
1106 && ((bitsize + bitnum) / GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0)))
1107 == bitsize / GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0)))))
1109 enum machine_mode outermode = GET_MODE (op0);
1110 enum machine_mode innermode = GET_MODE_INNER (outermode);
1111 int icode = (int) vec_extract_optab->handlers[outermode].insn_code;
1112 int pos = bitnum / GET_MODE_BITSIZE (innermode);
1113 rtx rtxpos = GEN_INT (pos);
1115 rtx dest = NULL, pat, seq;
1116 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
1117 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
1118 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
1120 if (innermode == tmode || innermode == mode)
1124 dest = gen_reg_rtx (innermode);
1128 if (! (*insn_data[icode].operand[0].predicate) (dest, mode0))
1129 dest = copy_to_mode_reg (mode0, dest);
1131 if (! (*insn_data[icode].operand[1].predicate) (src, mode1))
1132 src = copy_to_mode_reg (mode1, src);
1134 if (! (*insn_data[icode].operand[2].predicate) (rtxpos, mode2))
1135 rtxpos = copy_to_mode_reg (mode1, rtxpos);
1137 /* We could handle this, but we should always be called with a pseudo
1138 for our targets and all insns should take them as outputs. */
1139 if (! (*insn_data[icode].operand[0].predicate) (dest, mode0)
1140 || ! (*insn_data[icode].operand[1].predicate) (src, mode1)
1141 || ! (*insn_data[icode].operand[2].predicate) (rtxpos, mode2))
1144 pat = GEN_FCN (icode) (dest, src, rtxpos);
1155 /* Make sure we are playing with integral modes. Pun with subregs
1158 enum machine_mode imode = int_mode_for_mode (GET_MODE (op0));
1159 if (imode != GET_MODE (op0))
1161 if (GET_CODE (op0) == MEM)
1162 op0 = adjust_address (op0, imode, 0);
1163 else if (imode != BLKmode)
1164 op0 = gen_lowpart (imode, op0);
1170 /* We may be accessing data outside the field, which means
1171 we can alias adjacent data. */
1172 if (GET_CODE (op0) == MEM)
1174 op0 = shallow_copy_rtx (op0);
1175 set_mem_alias_set (op0, 0);
1176 set_mem_expr (op0, 0);
1179 /* Extraction of a full-word or multi-word value from a structure
1180 in a register or aligned memory can be done with just a SUBREG.
1181 A subword value in the least significant part of a register
1182 can also be extracted with a SUBREG. For this, we need the
1183 byte offset of the value in op0. */
1185 byte_offset = bitpos / BITS_PER_UNIT + offset * UNITS_PER_WORD;
1187 /* If OP0 is a register, BITPOS must count within a word.
1188 But as we have it, it counts within whatever size OP0 now has.
1189 On a bigendian machine, these are not the same, so convert. */
1190 if (BYTES_BIG_ENDIAN
1191 && GET_CODE (op0) != MEM
1192 && unit > GET_MODE_BITSIZE (GET_MODE (op0)))
1193 bitpos += unit - GET_MODE_BITSIZE (GET_MODE (op0));
1195 /* ??? We currently assume TARGET is at least as big as BITSIZE.
1196 If that's wrong, the solution is to test for it and set TARGET to 0
1199 /* Only scalar integer modes can be converted via subregs. There is an
1200 additional problem for FP modes here in that they can have a precision
1201 which is different from the size. mode_for_size uses precision, but
1202 we want a mode based on the size, so we must avoid calling it for FP
1204 mode1 = (SCALAR_INT_MODE_P (tmode)
1205 ? mode_for_size (bitsize, GET_MODE_CLASS (tmode), 0)
1208 if (((bitsize >= BITS_PER_WORD && bitsize == GET_MODE_BITSIZE (mode)
1209 && bitpos % BITS_PER_WORD == 0)
1210 || (mode1 != BLKmode
1211 /* ??? The big endian test here is wrong. This is correct
1212 if the value is in a register, and if mode_for_size is not
1213 the same mode as op0. This causes us to get unnecessarily
1214 inefficient code from the Thumb port when -mbig-endian. */
1215 && (BYTES_BIG_ENDIAN
1216 ? bitpos + bitsize == BITS_PER_WORD
1218 && ((GET_CODE (op0) != MEM
1219 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
1220 GET_MODE_BITSIZE (GET_MODE (op0)))
1221 && GET_MODE_SIZE (mode1) != 0
1222 && byte_offset % GET_MODE_SIZE (mode1) == 0)
1223 || (GET_CODE (op0) == MEM
1224 && (! SLOW_UNALIGNED_ACCESS (mode, MEM_ALIGN (op0))
1225 || (offset * BITS_PER_UNIT % bitsize == 0
1226 && MEM_ALIGN (op0) % bitsize == 0)))))
1228 if (mode1 != GET_MODE (op0))
1230 if (GET_CODE (op0) == SUBREG)
1232 if (GET_MODE (SUBREG_REG (op0)) == mode1
1233 || GET_MODE_CLASS (mode1) == MODE_INT
1234 || GET_MODE_CLASS (mode1) == MODE_PARTIAL_INT)
1235 op0 = SUBREG_REG (op0);
1237 /* Else we've got some float mode source being extracted into
1238 a different float mode destination -- this combination of
1239 subregs results in Severe Tire Damage. */
1240 goto no_subreg_mode_swap;
1242 if (GET_CODE (op0) == REG)
1243 op0 = gen_rtx_SUBREG (mode1, op0, byte_offset);
1245 op0 = adjust_address (op0, mode1, offset);
1248 return convert_to_mode (tmode, op0, unsignedp);
1251 no_subreg_mode_swap:
1253 /* Handle fields bigger than a word. */
1255 if (bitsize > BITS_PER_WORD)
1257 /* Here we transfer the words of the field
1258 in the order least significant first.
1259 This is because the most significant word is the one which may
1260 be less than full. */
1262 unsigned int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD;
1265 if (target == 0 || GET_CODE (target) != REG)
1266 target = gen_reg_rtx (mode);
1268 /* Indicate for flow that the entire target reg is being set. */
1269 emit_insn (gen_rtx_CLOBBER (VOIDmode, target));
1271 for (i = 0; i < nwords; i++)
1273 /* If I is 0, use the low-order word in both field and target;
1274 if I is 1, use the next to lowest word; and so on. */
1275 /* Word number in TARGET to use. */
1276 unsigned int wordnum
1278 ? GET_MODE_SIZE (GET_MODE (target)) / UNITS_PER_WORD - i - 1
1280 /* Offset from start of field in OP0. */
1281 unsigned int bit_offset = (WORDS_BIG_ENDIAN
1282 ? MAX (0, ((int) bitsize - ((int) i + 1)
1283 * (int) BITS_PER_WORD))
1284 : (int) i * BITS_PER_WORD);
1285 rtx target_part = operand_subword (target, wordnum, 1, VOIDmode);
1287 = extract_bit_field (op0, MIN (BITS_PER_WORD,
1288 bitsize - i * BITS_PER_WORD),
1289 bitnum + bit_offset, 1, target_part, mode,
1290 word_mode, total_size);
1292 if (target_part == 0)
1295 if (result_part != target_part)
1296 emit_move_insn (target_part, result_part);
1301 /* Unless we've filled TARGET, the upper regs in a multi-reg value
1302 need to be zero'd out. */
1303 if (GET_MODE_SIZE (GET_MODE (target)) > nwords * UNITS_PER_WORD)
1305 unsigned int i, total_words;
1307 total_words = GET_MODE_SIZE (GET_MODE (target)) / UNITS_PER_WORD;
1308 for (i = nwords; i < total_words; i++)
1310 (operand_subword (target,
1311 WORDS_BIG_ENDIAN ? total_words - i - 1 : i,
1318 /* Signed bit field: sign-extend with two arithmetic shifts. */
1319 target = expand_shift (LSHIFT_EXPR, mode, target,
1320 build_int_2 (GET_MODE_BITSIZE (mode) - bitsize, 0),
1322 return expand_shift (RSHIFT_EXPR, mode, target,
1323 build_int_2 (GET_MODE_BITSIZE (mode) - bitsize, 0),
1327 /* From here on we know the desired field is smaller than a word. */
1329 /* Check if there is a correspondingly-sized integer field, so we can
1330 safely extract it as one size of integer, if necessary; then
1331 truncate or extend to the size that is wanted; then use SUBREGs or
1332 convert_to_mode to get one of the modes we really wanted. */
1334 int_mode = int_mode_for_mode (tmode);
1335 if (int_mode == BLKmode)
1336 int_mode = int_mode_for_mode (mode);
1337 if (int_mode == BLKmode)
1338 abort (); /* Should probably push op0 out to memory and then
1341 /* OFFSET is the number of words or bytes (UNIT says which)
1342 from STR_RTX to the first word or byte containing part of the field. */
1344 if (GET_CODE (op0) != MEM)
1347 || GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD)
1349 if (GET_CODE (op0) != REG)
1350 op0 = copy_to_reg (op0);
1351 op0 = gen_rtx_SUBREG (mode_for_size (BITS_PER_WORD, MODE_INT, 0),
1352 op0, (offset * UNITS_PER_WORD));
1357 op0 = protect_from_queue (str_rtx, 1);
1359 /* Now OFFSET is nonzero only for memory operands. */
1364 && (GET_MODE_BITSIZE (extzv_mode) >= bitsize)
1365 && ! ((GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
1366 && (bitsize + bitpos > GET_MODE_BITSIZE (extzv_mode))))
1368 unsigned HOST_WIDE_INT xbitpos = bitpos, xoffset = offset;
1369 rtx bitsize_rtx, bitpos_rtx;
1370 rtx last = get_last_insn ();
1372 rtx xtarget = target;
1373 rtx xspec_target = spec_target;
1374 rtx xspec_target_subreg = spec_target_subreg;
1376 enum machine_mode maxmode = mode_for_extraction (EP_extzv, 0);
1378 if (GET_CODE (xop0) == MEM)
1380 int save_volatile_ok = volatile_ok;
1383 /* Is the memory operand acceptable? */
1384 if (! ((*insn_data[(int) CODE_FOR_extzv].operand[1].predicate)
1385 (xop0, GET_MODE (xop0))))
1387 /* No, load into a reg and extract from there. */
1388 enum machine_mode bestmode;
1390 /* Get the mode to use for inserting into this field. If
1391 OP0 is BLKmode, get the smallest mode consistent with the
1392 alignment. If OP0 is a non-BLKmode object that is no
1393 wider than MAXMODE, use its mode. Otherwise, use the
1394 smallest mode containing the field. */
1396 if (GET_MODE (xop0) == BLKmode
1397 || (GET_MODE_SIZE (GET_MODE (op0))
1398 > GET_MODE_SIZE (maxmode)))
1399 bestmode = get_best_mode (bitsize, bitnum,
1400 MEM_ALIGN (xop0), maxmode,
1401 MEM_VOLATILE_P (xop0));
1403 bestmode = GET_MODE (xop0);
1405 if (bestmode == VOIDmode
1406 || (SLOW_UNALIGNED_ACCESS (bestmode, MEM_ALIGN (xop0))
1407 && GET_MODE_BITSIZE (bestmode) > MEM_ALIGN (xop0)))
1410 /* Compute offset as multiple of this unit,
1411 counting in bytes. */
1412 unit = GET_MODE_BITSIZE (bestmode);
1413 xoffset = (bitnum / unit) * GET_MODE_SIZE (bestmode);
1414 xbitpos = bitnum % unit;
1415 xop0 = adjust_address (xop0, bestmode, xoffset);
1417 /* Fetch it to a register in that size. */
1418 xop0 = force_reg (bestmode, xop0);
1420 /* XBITPOS counts within UNIT, which is what is expected. */
1423 /* Get ref to first byte containing part of the field. */
1424 xop0 = adjust_address (xop0, byte_mode, xoffset);
1426 volatile_ok = save_volatile_ok;
1429 /* If op0 is a register, we need it in MAXMODE (which is usually
1430 SImode). to make it acceptable to the format of extzv. */
1431 if (GET_CODE (xop0) == SUBREG && GET_MODE (xop0) != maxmode)
1433 if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode)
1434 xop0 = gen_rtx_SUBREG (maxmode, xop0, 0);
1436 /* On big-endian machines, we count bits from the most significant.
1437 If the bit field insn does not, we must invert. */
1438 if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
1439 xbitpos = unit - bitsize - xbitpos;
1441 /* Now convert from counting within UNIT to counting in MAXMODE. */
1442 if (BITS_BIG_ENDIAN && GET_CODE (xop0) != MEM)
1443 xbitpos += GET_MODE_BITSIZE (maxmode) - unit;
1445 unit = GET_MODE_BITSIZE (maxmode);
1448 || (flag_force_mem && GET_CODE (xtarget) == MEM))
1449 xtarget = xspec_target = gen_reg_rtx (tmode);
1451 if (GET_MODE (xtarget) != maxmode)
1453 if (GET_CODE (xtarget) == REG)
1455 int wider = (GET_MODE_SIZE (maxmode)
1456 > GET_MODE_SIZE (GET_MODE (xtarget)));
1457 xtarget = gen_lowpart (maxmode, xtarget);
1459 xspec_target_subreg = xtarget;
1462 xtarget = gen_reg_rtx (maxmode);
1465 /* If this machine's extzv insists on a register target,
1466 make sure we have one. */
1467 if (! ((*insn_data[(int) CODE_FOR_extzv].operand[0].predicate)
1468 (xtarget, maxmode)))
1469 xtarget = gen_reg_rtx (maxmode);
1471 bitsize_rtx = GEN_INT (bitsize);
1472 bitpos_rtx = GEN_INT (xbitpos);
1474 pat = gen_extzv (protect_from_queue (xtarget, 1),
1475 xop0, bitsize_rtx, bitpos_rtx);
1480 spec_target = xspec_target;
1481 spec_target_subreg = xspec_target_subreg;
1485 delete_insns_since (last);
1486 target = extract_fixed_bit_field (int_mode, op0, offset, bitsize,
1492 target = extract_fixed_bit_field (int_mode, op0, offset, bitsize,
1498 && (GET_MODE_BITSIZE (extv_mode) >= bitsize)
1499 && ! ((GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
1500 && (bitsize + bitpos > GET_MODE_BITSIZE (extv_mode))))
1502 int xbitpos = bitpos, xoffset = offset;
1503 rtx bitsize_rtx, bitpos_rtx;
1504 rtx last = get_last_insn ();
1505 rtx xop0 = op0, xtarget = target;
1506 rtx xspec_target = spec_target;
1507 rtx xspec_target_subreg = spec_target_subreg;
1509 enum machine_mode maxmode = mode_for_extraction (EP_extv, 0);
1511 if (GET_CODE (xop0) == MEM)
1513 /* Is the memory operand acceptable? */
1514 if (! ((*insn_data[(int) CODE_FOR_extv].operand[1].predicate)
1515 (xop0, GET_MODE (xop0))))
1517 /* No, load into a reg and extract from there. */
1518 enum machine_mode bestmode;
1520 /* Get the mode to use for inserting into this field. If
1521 OP0 is BLKmode, get the smallest mode consistent with the
1522 alignment. If OP0 is a non-BLKmode object that is no
1523 wider than MAXMODE, use its mode. Otherwise, use the
1524 smallest mode containing the field. */
1526 if (GET_MODE (xop0) == BLKmode
1527 || (GET_MODE_SIZE (GET_MODE (op0))
1528 > GET_MODE_SIZE (maxmode)))
1529 bestmode = get_best_mode (bitsize, bitnum,
1530 MEM_ALIGN (xop0), maxmode,
1531 MEM_VOLATILE_P (xop0));
1533 bestmode = GET_MODE (xop0);
1535 if (bestmode == VOIDmode
1536 || (SLOW_UNALIGNED_ACCESS (bestmode, MEM_ALIGN (xop0))
1537 && GET_MODE_BITSIZE (bestmode) > MEM_ALIGN (xop0)))
1540 /* Compute offset as multiple of this unit,
1541 counting in bytes. */
1542 unit = GET_MODE_BITSIZE (bestmode);
1543 xoffset = (bitnum / unit) * GET_MODE_SIZE (bestmode);
1544 xbitpos = bitnum % unit;
1545 xop0 = adjust_address (xop0, bestmode, xoffset);
1547 /* Fetch it to a register in that size. */
1548 xop0 = force_reg (bestmode, xop0);
1550 /* XBITPOS counts within UNIT, which is what is expected. */
1553 /* Get ref to first byte containing part of the field. */
1554 xop0 = adjust_address (xop0, byte_mode, xoffset);
1557 /* If op0 is a register, we need it in MAXMODE (which is usually
1558 SImode) to make it acceptable to the format of extv. */
1559 if (GET_CODE (xop0) == SUBREG && GET_MODE (xop0) != maxmode)
1561 if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode)
1562 xop0 = gen_rtx_SUBREG (maxmode, xop0, 0);
1564 /* On big-endian machines, we count bits from the most significant.
1565 If the bit field insn does not, we must invert. */
1566 if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
1567 xbitpos = unit - bitsize - xbitpos;
1569 /* XBITPOS counts within a size of UNIT.
1570 Adjust to count within a size of MAXMODE. */
1571 if (BITS_BIG_ENDIAN && GET_CODE (xop0) != MEM)
1572 xbitpos += (GET_MODE_BITSIZE (maxmode) - unit);
1574 unit = GET_MODE_BITSIZE (maxmode);
1577 || (flag_force_mem && GET_CODE (xtarget) == MEM))
1578 xtarget = xspec_target = gen_reg_rtx (tmode);
1580 if (GET_MODE (xtarget) != maxmode)
1582 if (GET_CODE (xtarget) == REG)
1584 int wider = (GET_MODE_SIZE (maxmode)
1585 > GET_MODE_SIZE (GET_MODE (xtarget)));
1586 xtarget = gen_lowpart (maxmode, xtarget);
1588 xspec_target_subreg = xtarget;
1591 xtarget = gen_reg_rtx (maxmode);
1594 /* If this machine's extv insists on a register target,
1595 make sure we have one. */
1596 if (! ((*insn_data[(int) CODE_FOR_extv].operand[0].predicate)
1597 (xtarget, maxmode)))
1598 xtarget = gen_reg_rtx (maxmode);
1600 bitsize_rtx = GEN_INT (bitsize);
1601 bitpos_rtx = GEN_INT (xbitpos);
1603 pat = gen_extv (protect_from_queue (xtarget, 1),
1604 xop0, bitsize_rtx, bitpos_rtx);
1609 spec_target = xspec_target;
1610 spec_target_subreg = xspec_target_subreg;
1614 delete_insns_since (last);
1615 target = extract_fixed_bit_field (int_mode, op0, offset, bitsize,
1621 target = extract_fixed_bit_field (int_mode, op0, offset, bitsize,
1624 if (target == spec_target)
1626 if (target == spec_target_subreg)
1628 if (GET_MODE (target) != tmode && GET_MODE (target) != mode)
1630 /* If the target mode is floating-point, first convert to the
1631 integer mode of that size and then access it as a floating-point
1632 value via a SUBREG. */
1633 if (GET_MODE_CLASS (tmode) != MODE_INT
1634 && GET_MODE_CLASS (tmode) != MODE_PARTIAL_INT)
1636 target = convert_to_mode (mode_for_size (GET_MODE_BITSIZE (tmode),
1639 return gen_lowpart (tmode, target);
1642 return convert_to_mode (tmode, target, unsignedp);
1647 /* Extract a bit field using shifts and boolean operations
1648 Returns an rtx to represent the value.
1649 OP0 addresses a register (word) or memory (byte).
1650 BITPOS says which bit within the word or byte the bit field starts in.
1651 OFFSET says how many bytes farther the bit field starts;
1652 it is 0 if OP0 is a register.
1653 BITSIZE says how many bits long the bit field is.
1654 (If OP0 is a register, it may be narrower than a full word,
1655 but BITPOS still counts within a full word,
1656 which is significant on bigendian machines.)
1658 UNSIGNEDP is nonzero for an unsigned bit field (don't sign-extend value).
1659 If TARGET is nonzero, attempts to store the value there
1660 and return TARGET, but this is not guaranteed.
1661 If TARGET is not used, create a pseudo-reg of mode TMODE for the value. */
1664 extract_fixed_bit_field (enum machine_mode tmode, rtx op0,
1665 unsigned HOST_WIDE_INT offset,
1666 unsigned HOST_WIDE_INT bitsize,
1667 unsigned HOST_WIDE_INT bitpos, rtx target,
1670 unsigned int total_bits = BITS_PER_WORD;
1671 enum machine_mode mode;
1673 if (GET_CODE (op0) == SUBREG || GET_CODE (op0) == REG)
1675 /* Special treatment for a bit field split across two registers. */
1676 if (bitsize + bitpos > BITS_PER_WORD)
1677 return extract_split_bit_field (op0, bitsize, bitpos, unsignedp);
1681 /* Get the proper mode to use for this field. We want a mode that
1682 includes the entire field. If such a mode would be larger than
1683 a word, we won't be doing the extraction the normal way. */
1685 mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT,
1686 MEM_ALIGN (op0), word_mode, MEM_VOLATILE_P (op0));
1688 if (mode == VOIDmode)
1689 /* The only way this should occur is if the field spans word
1691 return extract_split_bit_field (op0, bitsize,
1692 bitpos + offset * BITS_PER_UNIT,
1695 total_bits = GET_MODE_BITSIZE (mode);
1697 /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to
1698 be in the range 0 to total_bits-1, and put any excess bytes in
1700 if (bitpos >= total_bits)
1702 offset += (bitpos / total_bits) * (total_bits / BITS_PER_UNIT);
1703 bitpos -= ((bitpos / total_bits) * (total_bits / BITS_PER_UNIT)
1707 /* Get ref to an aligned byte, halfword, or word containing the field.
1708 Adjust BITPOS to be position within a word,
1709 and OFFSET to be the offset of that word.
1710 Then alter OP0 to refer to that word. */
1711 bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT;
1712 offset -= (offset % (total_bits / BITS_PER_UNIT));
1713 op0 = adjust_address (op0, mode, offset);
1716 mode = GET_MODE (op0);
1718 if (BYTES_BIG_ENDIAN)
1719 /* BITPOS is the distance between our msb and that of OP0.
1720 Convert it to the distance from the lsb. */
1721 bitpos = total_bits - bitsize - bitpos;
1723 /* Now BITPOS is always the distance between the field's lsb and that of OP0.
1724 We have reduced the big-endian case to the little-endian case. */
1730 /* If the field does not already start at the lsb,
1731 shift it so it does. */
1732 tree amount = build_int_2 (bitpos, 0);
1733 /* Maybe propagate the target for the shift. */
1734 /* But not if we will return it--could confuse integrate.c. */
1735 rtx subtarget = (target != 0 && GET_CODE (target) == REG ? target : 0);
1736 if (tmode != mode) subtarget = 0;
1737 op0 = expand_shift (RSHIFT_EXPR, mode, op0, amount, subtarget, 1);
1739 /* Convert the value to the desired mode. */
1741 op0 = convert_to_mode (tmode, op0, 1);
1743 /* Unless the msb of the field used to be the msb when we shifted,
1744 mask out the upper bits. */
1746 if (GET_MODE_BITSIZE (mode) != bitpos + bitsize)
1747 return expand_binop (GET_MODE (op0), and_optab, op0,
1748 mask_rtx (GET_MODE (op0), 0, bitsize, 0),
1749 target, 1, OPTAB_LIB_WIDEN);
1753 /* To extract a signed bit-field, first shift its msb to the msb of the word,
1754 then arithmetic-shift its lsb to the lsb of the word. */
1755 op0 = force_reg (mode, op0);
1759 /* Find the narrowest integer mode that contains the field. */
1761 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode;
1762 mode = GET_MODE_WIDER_MODE (mode))
1763 if (GET_MODE_BITSIZE (mode) >= bitsize + bitpos)
1765 op0 = convert_to_mode (mode, op0, 0);
1769 if (GET_MODE_BITSIZE (mode) != (bitsize + bitpos))
1772 = build_int_2 (GET_MODE_BITSIZE (mode) - (bitsize + bitpos), 0);
1773 /* Maybe propagate the target for the shift. */
1774 rtx subtarget = (target != 0 && GET_CODE (target) == REG ? target : 0);
1775 op0 = expand_shift (LSHIFT_EXPR, mode, op0, amount, subtarget, 1);
1778 return expand_shift (RSHIFT_EXPR, mode, op0,
1779 build_int_2 (GET_MODE_BITSIZE (mode) - bitsize, 0),
1783 /* Return a constant integer (CONST_INT or CONST_DOUBLE) mask value
1784 of mode MODE with BITSIZE ones followed by BITPOS zeros, or the
1785 complement of that if COMPLEMENT. The mask is truncated if
1786 necessary to the width of mode MODE. The mask is zero-extended if
1787 BITSIZE+BITPOS is too small for MODE. */
1790 mask_rtx (enum machine_mode mode, int bitpos, int bitsize, int complement)
1792 HOST_WIDE_INT masklow, maskhigh;
1796 else if (bitpos < HOST_BITS_PER_WIDE_INT)
1797 masklow = (HOST_WIDE_INT) -1 << bitpos;
1801 if (bitpos + bitsize < HOST_BITS_PER_WIDE_INT)
1802 masklow &= ((unsigned HOST_WIDE_INT) -1
1803 >> (HOST_BITS_PER_WIDE_INT - bitpos - bitsize));
1805 if (bitpos <= HOST_BITS_PER_WIDE_INT)
1808 maskhigh = (HOST_WIDE_INT) -1 << (bitpos - HOST_BITS_PER_WIDE_INT);
1812 else if (bitpos + bitsize > HOST_BITS_PER_WIDE_INT)
1813 maskhigh &= ((unsigned HOST_WIDE_INT) -1
1814 >> (2 * HOST_BITS_PER_WIDE_INT - bitpos - bitsize));
1820 maskhigh = ~maskhigh;
1824 return immed_double_const (masklow, maskhigh, mode);
1827 /* Return a constant integer (CONST_INT or CONST_DOUBLE) rtx with the value
1828 VALUE truncated to BITSIZE bits and then shifted left BITPOS bits. */
1831 lshift_value (enum machine_mode mode, rtx value, int bitpos, int bitsize)
1833 unsigned HOST_WIDE_INT v = INTVAL (value);
1834 HOST_WIDE_INT low, high;
1836 if (bitsize < HOST_BITS_PER_WIDE_INT)
1837 v &= ~((HOST_WIDE_INT) -1 << bitsize);
1839 if (bitpos < HOST_BITS_PER_WIDE_INT)
1842 high = (bitpos > 0 ? (v >> (HOST_BITS_PER_WIDE_INT - bitpos)) : 0);
1847 high = v << (bitpos - HOST_BITS_PER_WIDE_INT);
1850 return immed_double_const (low, high, mode);
1853 /* Extract a bit field that is split across two words
1854 and return an RTX for the result.
1856 OP0 is the REG, SUBREG or MEM rtx for the first of the two words.
1857 BITSIZE is the field width; BITPOS, position of its first bit, in the word.
1858 UNSIGNEDP is 1 if should zero-extend the contents; else sign-extend. */
1861 extract_split_bit_field (rtx op0, unsigned HOST_WIDE_INT bitsize,
1862 unsigned HOST_WIDE_INT bitpos, int unsignedp)
1865 unsigned int bitsdone = 0;
1866 rtx result = NULL_RTX;
1869 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
1871 if (GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
1872 unit = BITS_PER_WORD;
1874 unit = MIN (MEM_ALIGN (op0), BITS_PER_WORD);
1876 while (bitsdone < bitsize)
1878 unsigned HOST_WIDE_INT thissize;
1880 unsigned HOST_WIDE_INT thispos;
1881 unsigned HOST_WIDE_INT offset;
1883 offset = (bitpos + bitsdone) / unit;
1884 thispos = (bitpos + bitsdone) % unit;
1886 /* THISSIZE must not overrun a word boundary. Otherwise,
1887 extract_fixed_bit_field will call us again, and we will mutually
1889 thissize = MIN (bitsize - bitsdone, BITS_PER_WORD);
1890 thissize = MIN (thissize, unit - thispos);
1892 /* If OP0 is a register, then handle OFFSET here.
1894 When handling multiword bitfields, extract_bit_field may pass
1895 down a word_mode SUBREG of a larger REG for a bitfield that actually
1896 crosses a word boundary. Thus, for a SUBREG, we must find
1897 the current word starting from the base register. */
1898 if (GET_CODE (op0) == SUBREG)
1900 int word_offset = (SUBREG_BYTE (op0) / UNITS_PER_WORD) + offset;
1901 word = operand_subword_force (SUBREG_REG (op0), word_offset,
1902 GET_MODE (SUBREG_REG (op0)));
1905 else if (GET_CODE (op0) == REG)
1907 word = operand_subword_force (op0, offset, GET_MODE (op0));
1913 /* Extract the parts in bit-counting order,
1914 whose meaning is determined by BYTES_PER_UNIT.
1915 OFFSET is in UNITs, and UNIT is in bits.
1916 extract_fixed_bit_field wants offset in bytes. */
1917 part = extract_fixed_bit_field (word_mode, word,
1918 offset * unit / BITS_PER_UNIT,
1919 thissize, thispos, 0, 1);
1920 bitsdone += thissize;
1922 /* Shift this part into place for the result. */
1923 if (BYTES_BIG_ENDIAN)
1925 if (bitsize != bitsdone)
1926 part = expand_shift (LSHIFT_EXPR, word_mode, part,
1927 build_int_2 (bitsize - bitsdone, 0), 0, 1);
1931 if (bitsdone != thissize)
1932 part = expand_shift (LSHIFT_EXPR, word_mode, part,
1933 build_int_2 (bitsdone - thissize, 0), 0, 1);
1939 /* Combine the parts with bitwise or. This works
1940 because we extracted each part as an unsigned bit field. */
1941 result = expand_binop (word_mode, ior_optab, part, result, NULL_RTX, 1,
1947 /* Unsigned bit field: we are done. */
1950 /* Signed bit field: sign-extend with two arithmetic shifts. */
1951 result = expand_shift (LSHIFT_EXPR, word_mode, result,
1952 build_int_2 (BITS_PER_WORD - bitsize, 0),
1954 return expand_shift (RSHIFT_EXPR, word_mode, result,
1955 build_int_2 (BITS_PER_WORD - bitsize, 0), NULL_RTX, 0);
1958 /* Add INC into TARGET. */
1961 expand_inc (rtx target, rtx inc)
1963 rtx value = expand_binop (GET_MODE (target), add_optab,
1965 target, 0, OPTAB_LIB_WIDEN);
1966 if (value != target)
1967 emit_move_insn (target, value);
1970 /* Subtract DEC from TARGET. */
1973 expand_dec (rtx target, rtx dec)
1975 rtx value = expand_binop (GET_MODE (target), sub_optab,
1977 target, 0, OPTAB_LIB_WIDEN);
1978 if (value != target)
1979 emit_move_insn (target, value);
1982 /* Output a shift instruction for expression code CODE,
1983 with SHIFTED being the rtx for the value to shift,
1984 and AMOUNT the tree for the amount to shift by.
1985 Store the result in the rtx TARGET, if that is convenient.
1986 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
1987 Return the rtx for where the value is. */
1990 expand_shift (enum tree_code code, enum machine_mode mode, rtx shifted,
1991 tree amount, rtx target, int unsignedp)
1994 int left = (code == LSHIFT_EXPR || code == LROTATE_EXPR);
1995 int rotate = (code == LROTATE_EXPR || code == RROTATE_EXPR);
1998 /* Previously detected shift-counts computed by NEGATE_EXPR
1999 and shifted in the other direction; but that does not work
2002 op1 = expand_expr (amount, NULL_RTX, VOIDmode, 0);
2004 if (SHIFT_COUNT_TRUNCATED)
2006 if (GET_CODE (op1) == CONST_INT
2007 && ((unsigned HOST_WIDE_INT) INTVAL (op1) >=
2008 (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode)))
2009 op1 = GEN_INT ((unsigned HOST_WIDE_INT) INTVAL (op1)
2010 % GET_MODE_BITSIZE (mode));
2011 else if (GET_CODE (op1) == SUBREG
2012 && subreg_lowpart_p (op1))
2013 op1 = SUBREG_REG (op1);
2016 if (op1 == const0_rtx)
2019 for (try = 0; temp == 0 && try < 3; try++)
2021 enum optab_methods methods;
2024 methods = OPTAB_DIRECT;
2026 methods = OPTAB_WIDEN;
2028 methods = OPTAB_LIB_WIDEN;
2032 /* Widening does not work for rotation. */
2033 if (methods == OPTAB_WIDEN)
2035 else if (methods == OPTAB_LIB_WIDEN)
2037 /* If we have been unable to open-code this by a rotation,
2038 do it as the IOR of two shifts. I.e., to rotate A
2039 by N bits, compute (A << N) | ((unsigned) A >> (C - N))
2040 where C is the bitsize of A.
2042 It is theoretically possible that the target machine might
2043 not be able to perform either shift and hence we would
2044 be making two libcalls rather than just the one for the
2045 shift (similarly if IOR could not be done). We will allow
2046 this extremely unlikely lossage to avoid complicating the
2049 rtx subtarget = target == shifted ? 0 : target;
2051 tree type = TREE_TYPE (amount);
2052 tree new_amount = make_tree (type, op1);
2054 = fold (build (MINUS_EXPR, type,
2056 build_int_2 (GET_MODE_BITSIZE (mode),
2060 shifted = force_reg (mode, shifted);
2062 temp = expand_shift (left ? LSHIFT_EXPR : RSHIFT_EXPR,
2063 mode, shifted, new_amount, subtarget, 1);
2064 temp1 = expand_shift (left ? RSHIFT_EXPR : LSHIFT_EXPR,
2065 mode, shifted, other_amount, 0, 1);
2066 return expand_binop (mode, ior_optab, temp, temp1, target,
2067 unsignedp, methods);
2070 temp = expand_binop (mode,
2071 left ? rotl_optab : rotr_optab,
2072 shifted, op1, target, unsignedp, methods);
2074 /* If we don't have the rotate, but we are rotating by a constant
2075 that is in range, try a rotate in the opposite direction. */
2077 if (temp == 0 && GET_CODE (op1) == CONST_INT
2079 && (unsigned int) INTVAL (op1) < GET_MODE_BITSIZE (mode))
2080 temp = expand_binop (mode,
2081 left ? rotr_optab : rotl_optab,
2083 GEN_INT (GET_MODE_BITSIZE (mode)
2085 target, unsignedp, methods);
2088 temp = expand_binop (mode,
2089 left ? ashl_optab : lshr_optab,
2090 shifted, op1, target, unsignedp, methods);
2092 /* Do arithmetic shifts.
2093 Also, if we are going to widen the operand, we can just as well
2094 use an arithmetic right-shift instead of a logical one. */
2095 if (temp == 0 && ! rotate
2096 && (! unsignedp || (! left && methods == OPTAB_WIDEN)))
2098 enum optab_methods methods1 = methods;
2100 /* If trying to widen a log shift to an arithmetic shift,
2101 don't accept an arithmetic shift of the same size. */
2103 methods1 = OPTAB_MUST_WIDEN;
2105 /* Arithmetic shift */
2107 temp = expand_binop (mode,
2108 left ? ashl_optab : ashr_optab,
2109 shifted, op1, target, unsignedp, methods1);
2112 /* We used to try extzv here for logical right shifts, but that was
2113 only useful for one machine, the VAX, and caused poor code
2114 generation there for lshrdi3, so the code was deleted and a
2115 define_expand for lshrsi3 was added to vax.md. */
2123 enum alg_code { alg_zero, alg_m, alg_shift,
2124 alg_add_t_m2, alg_sub_t_m2,
2125 alg_add_factor, alg_sub_factor,
2126 alg_add_t2_m, alg_sub_t2_m,
2127 alg_add, alg_subtract, alg_factor, alg_shiftop };
2129 /* This structure records a sequence of operations.
2130 `ops' is the number of operations recorded.
2131 `cost' is their total cost.
2132 The operations are stored in `op' and the corresponding
2133 logarithms of the integer coefficients in `log'.
2135 These are the operations:
2136 alg_zero total := 0;
2137 alg_m total := multiplicand;
2138 alg_shift total := total * coeff
2139 alg_add_t_m2 total := total + multiplicand * coeff;
2140 alg_sub_t_m2 total := total - multiplicand * coeff;
2141 alg_add_factor total := total * coeff + total;
2142 alg_sub_factor total := total * coeff - total;
2143 alg_add_t2_m total := total * coeff + multiplicand;
2144 alg_sub_t2_m total := total * coeff - multiplicand;
2146 The first operand must be either alg_zero or alg_m. */
2152 /* The size of the OP and LOG fields are not directly related to the
2153 word size, but the worst-case algorithms will be if we have few
2154 consecutive ones or zeros, i.e., a multiplicand like 10101010101...
2155 In that case we will generate shift-by-2, add, shift-by-2, add,...,
2156 in total wordsize operations. */
2157 enum alg_code op[MAX_BITS_PER_WORD];
2158 char log[MAX_BITS_PER_WORD];
2161 /* Indicates the type of fixup needed after a constant multiplication.
2162 BASIC_VARIANT means no fixup is needed, NEGATE_VARIANT means that
2163 the result should be negated, and ADD_VARIANT means that the
2164 multiplicand should be added to the result. */
2165 enum mult_variant {basic_variant, negate_variant, add_variant};
2167 static void synth_mult (struct algorithm *, unsigned HOST_WIDE_INT,
2168 int, enum machine_mode mode);
2169 static bool choose_mult_variant (enum machine_mode, HOST_WIDE_INT,
2170 struct algorithm *, enum mult_variant *, int);
2171 static rtx expand_mult_const (enum machine_mode, rtx, HOST_WIDE_INT, rtx,
2172 const struct algorithm *, enum mult_variant);
2173 static unsigned HOST_WIDE_INT choose_multiplier (unsigned HOST_WIDE_INT, int,
2174 int, unsigned HOST_WIDE_INT *,
2176 static unsigned HOST_WIDE_INT invert_mod2n (unsigned HOST_WIDE_INT, int);
2177 static rtx extract_high_half (enum machine_mode, rtx);
2178 static rtx expand_mult_highpart_optab (enum machine_mode, rtx, rtx, rtx,
2180 /* Compute and return the best algorithm for multiplying by T.
2181 The algorithm must cost less than cost_limit
2182 If retval.cost >= COST_LIMIT, no algorithm was found and all
2183 other field of the returned struct are undefined.
2184 MODE is the machine mode of the multiplication. */
2187 synth_mult (struct algorithm *alg_out, unsigned HOST_WIDE_INT t,
2188 int cost_limit, enum machine_mode mode)
2191 struct algorithm *alg_in, *best_alg;
2193 unsigned HOST_WIDE_INT q;
2195 /* Indicate that no algorithm is yet found. If no algorithm
2196 is found, this value will be returned and indicate failure. */
2197 alg_out->cost = cost_limit;
2199 if (cost_limit <= 0)
2202 /* t == 1 can be done in zero cost. */
2207 alg_out->op[0] = alg_m;
2211 /* t == 0 sometimes has a cost. If it does and it exceeds our limit,
2215 if (zero_cost >= cost_limit)
2220 alg_out->cost = zero_cost;
2221 alg_out->op[0] = alg_zero;
2226 /* We'll be needing a couple extra algorithm structures now. */
2228 alg_in = alloca (sizeof (struct algorithm));
2229 best_alg = alloca (sizeof (struct algorithm));
2231 /* If we have a group of zero bits at the low-order part of T, try
2232 multiplying by the remaining bits and then doing a shift. */
2236 m = floor_log2 (t & -t); /* m = number of low zero bits */
2237 if (m < BITS_PER_WORD)
2240 cost = shift_cost[mode][m];
2241 synth_mult (alg_in, q, cost_limit - cost, mode);
2243 cost += alg_in->cost;
2244 if (cost < cost_limit)
2246 struct algorithm *x;
2247 x = alg_in, alg_in = best_alg, best_alg = x;
2248 best_alg->log[best_alg->ops] = m;
2249 best_alg->op[best_alg->ops] = alg_shift;
2255 /* If we have an odd number, add or subtract one. */
2258 unsigned HOST_WIDE_INT w;
2260 for (w = 1; (w & t) != 0; w <<= 1)
2262 /* If T was -1, then W will be zero after the loop. This is another
2263 case where T ends with ...111. Handling this with (T + 1) and
2264 subtract 1 produces slightly better code and results in algorithm
2265 selection much faster than treating it like the ...0111 case
2269 /* Reject the case where t is 3.
2270 Thus we prefer addition in that case. */
2273 /* T ends with ...111. Multiply by (T + 1) and subtract 1. */
2275 cost = add_cost[mode];
2276 synth_mult (alg_in, t + 1, cost_limit - cost, mode);
2278 cost += alg_in->cost;
2279 if (cost < cost_limit)
2281 struct algorithm *x;
2282 x = alg_in, alg_in = best_alg, best_alg = x;
2283 best_alg->log[best_alg->ops] = 0;
2284 best_alg->op[best_alg->ops] = alg_sub_t_m2;
2290 /* T ends with ...01 or ...011. Multiply by (T - 1) and add 1. */
2292 cost = add_cost[mode];
2293 synth_mult (alg_in, t - 1, cost_limit - cost, mode);
2295 cost += alg_in->cost;
2296 if (cost < cost_limit)
2298 struct algorithm *x;
2299 x = alg_in, alg_in = best_alg, best_alg = x;
2300 best_alg->log[best_alg->ops] = 0;
2301 best_alg->op[best_alg->ops] = alg_add_t_m2;
2307 /* Look for factors of t of the form
2308 t = q(2**m +- 1), 2 <= m <= floor(log2(t - 1)).
2309 If we find such a factor, we can multiply by t using an algorithm that
2310 multiplies by q, shift the result by m and add/subtract it to itself.
2312 We search for large factors first and loop down, even if large factors
2313 are less probable than small; if we find a large factor we will find a
2314 good sequence quickly, and therefore be able to prune (by decreasing
2315 COST_LIMIT) the search. */
2317 for (m = floor_log2 (t - 1); m >= 2; m--)
2319 unsigned HOST_WIDE_INT d;
2321 d = ((unsigned HOST_WIDE_INT) 1 << m) + 1;
2322 if (t % d == 0 && t > d && m < BITS_PER_WORD)
2324 cost = add_cost[mode] + shift_cost[mode][m];
2325 if (shiftadd_cost[mode][m] < cost)
2326 cost = shiftadd_cost[mode][m];
2327 synth_mult (alg_in, t / d, cost_limit - cost, mode);
2329 cost += alg_in->cost;
2330 if (cost < cost_limit)
2332 struct algorithm *x;
2333 x = alg_in, alg_in = best_alg, best_alg = x;
2334 best_alg->log[best_alg->ops] = m;
2335 best_alg->op[best_alg->ops] = alg_add_factor;
2338 /* Other factors will have been taken care of in the recursion. */
2342 d = ((unsigned HOST_WIDE_INT) 1 << m) - 1;
2343 if (t % d == 0 && t > d && m < BITS_PER_WORD)
2345 cost = add_cost[mode] + shift_cost[mode][m];
2346 if (shiftsub_cost[mode][m] < cost)
2347 cost = shiftsub_cost[mode][m];
2348 synth_mult (alg_in, t / d, cost_limit - cost, mode);
2350 cost += alg_in->cost;
2351 if (cost < cost_limit)
2353 struct algorithm *x;
2354 x = alg_in, alg_in = best_alg, best_alg = x;
2355 best_alg->log[best_alg->ops] = m;
2356 best_alg->op[best_alg->ops] = alg_sub_factor;
2363 /* Try shift-and-add (load effective address) instructions,
2364 i.e. do a*3, a*5, a*9. */
2370 if (m >= 0 && m < BITS_PER_WORD)
2372 cost = shiftadd_cost[mode][m];
2373 synth_mult (alg_in, (t - 1) >> m, cost_limit - cost, mode);
2375 cost += alg_in->cost;
2376 if (cost < cost_limit)
2378 struct algorithm *x;
2379 x = alg_in, alg_in = best_alg, best_alg = x;
2380 best_alg->log[best_alg->ops] = m;
2381 best_alg->op[best_alg->ops] = alg_add_t2_m;
2389 if (m >= 0 && m < BITS_PER_WORD)
2391 cost = shiftsub_cost[mode][m];
2392 synth_mult (alg_in, (t + 1) >> m, cost_limit - cost, mode);
2394 cost += alg_in->cost;
2395 if (cost < cost_limit)
2397 struct algorithm *x;
2398 x = alg_in, alg_in = best_alg, best_alg = x;
2399 best_alg->log[best_alg->ops] = m;
2400 best_alg->op[best_alg->ops] = alg_sub_t2_m;
2406 /* If cost_limit has not decreased since we stored it in alg_out->cost,
2407 we have not found any algorithm. */
2408 if (cost_limit == alg_out->cost)
2411 /* If we are getting a too long sequence for `struct algorithm'
2412 to record, make this search fail. */
2413 if (best_alg->ops == MAX_BITS_PER_WORD)
2416 /* Copy the algorithm from temporary space to the space at alg_out.
2417 We avoid using structure assignment because the majority of
2418 best_alg is normally undefined, and this is a critical function. */
2419 alg_out->ops = best_alg->ops + 1;
2420 alg_out->cost = cost_limit;
2421 memcpy (alg_out->op, best_alg->op,
2422 alg_out->ops * sizeof *alg_out->op);
2423 memcpy (alg_out->log, best_alg->log,
2424 alg_out->ops * sizeof *alg_out->log);
2427 /* Find the cheapest way of multiplying a value of mode MODE by VAL.
2428 Try three variations:
2430 - a shift/add sequence based on VAL itself
2431 - a shift/add sequence based on -VAL, followed by a negation
2432 - a shift/add sequence based on VAL - 1, followed by an addition.
2434 Return true if the cheapest of these cost less than MULT_COST,
2435 describing the algorithm in *ALG and final fixup in *VARIANT. */
2438 choose_mult_variant (enum machine_mode mode, HOST_WIDE_INT val,
2439 struct algorithm *alg, enum mult_variant *variant,
2442 struct algorithm alg2;
2444 *variant = basic_variant;
2445 synth_mult (alg, val, mult_cost, mode);
2447 /* This works only if the inverted value actually fits in an
2449 if (HOST_BITS_PER_INT >= GET_MODE_BITSIZE (mode))
2451 synth_mult (&alg2, -val, MIN (alg->cost, mult_cost) - neg_cost[mode],
2453 alg2.cost += neg_cost[mode];
2454 if (alg2.cost < alg->cost)
2455 *alg = alg2, *variant = negate_variant;
2458 /* This proves very useful for division-by-constant. */
2459 synth_mult (&alg2, val - 1, MIN (alg->cost, mult_cost) - add_cost[mode],
2461 alg2.cost += add_cost[mode];
2462 if (alg2.cost < alg->cost)
2463 *alg = alg2, *variant = add_variant;
2465 return alg->cost < mult_cost;
2468 /* A subroutine of expand_mult, used for constant multiplications.
2469 Multiply OP0 by VAL in mode MODE, storing the result in TARGET if
2470 convenient. Use the shift/add sequence described by ALG and apply
2471 the final fixup specified by VARIANT. */
2474 expand_mult_const (enum machine_mode mode, rtx op0, HOST_WIDE_INT val,
2475 rtx target, const struct algorithm *alg,
2476 enum mult_variant variant)
2478 HOST_WIDE_INT val_so_far;
2479 rtx insn, accum, tem;
2481 enum machine_mode nmode;
2483 /* op0 must be register to make mult_cost match the precomputed
2484 shiftadd_cost array. */
2485 op0 = protect_from_queue (op0, 0);
2487 /* Avoid referencing memory over and over.
2488 For speed, but also for correctness when mem is volatile. */
2489 if (GET_CODE (op0) == MEM)
2490 op0 = force_reg (mode, op0);
2492 /* ACCUM starts out either as OP0 or as a zero, depending on
2493 the first operation. */
2495 if (alg->op[0] == alg_zero)
2497 accum = copy_to_mode_reg (mode, const0_rtx);
2500 else if (alg->op[0] == alg_m)
2502 accum = copy_to_mode_reg (mode, op0);
2508 for (opno = 1; opno < alg->ops; opno++)
2510 int log = alg->log[opno];
2511 int preserve = preserve_subexpressions_p ();
2512 rtx shift_subtarget = preserve ? 0 : accum;
2514 = (opno == alg->ops - 1 && target != 0 && variant != add_variant
2517 rtx accum_target = preserve ? 0 : accum;
2519 switch (alg->op[opno])
2522 accum = expand_shift (LSHIFT_EXPR, mode, accum,
2523 build_int_2 (log, 0), NULL_RTX, 0);
2528 tem = expand_shift (LSHIFT_EXPR, mode, op0,
2529 build_int_2 (log, 0), NULL_RTX, 0);
2530 accum = force_operand (gen_rtx_PLUS (mode, accum, tem),
2531 add_target ? add_target : accum_target);
2532 val_so_far += (HOST_WIDE_INT) 1 << log;
2536 tem = expand_shift (LSHIFT_EXPR, mode, op0,
2537 build_int_2 (log, 0), NULL_RTX, 0);
2538 accum = force_operand (gen_rtx_MINUS (mode, accum, tem),
2539 add_target ? add_target : accum_target);
2540 val_so_far -= (HOST_WIDE_INT) 1 << log;
2544 accum = expand_shift (LSHIFT_EXPR, mode, accum,
2545 build_int_2 (log, 0), shift_subtarget,
2547 accum = force_operand (gen_rtx_PLUS (mode, accum, op0),
2548 add_target ? add_target : accum_target);
2549 val_so_far = (val_so_far << log) + 1;
2553 accum = expand_shift (LSHIFT_EXPR, mode, accum,
2554 build_int_2 (log, 0), shift_subtarget, 0);
2555 accum = force_operand (gen_rtx_MINUS (mode, accum, op0),
2556 add_target ? add_target : accum_target);
2557 val_so_far = (val_so_far << log) - 1;
2560 case alg_add_factor:
2561 tem = expand_shift (LSHIFT_EXPR, mode, accum,
2562 build_int_2 (log, 0), NULL_RTX, 0);
2563 accum = force_operand (gen_rtx_PLUS (mode, accum, tem),
2564 add_target ? add_target : accum_target);
2565 val_so_far += val_so_far << log;
2568 case alg_sub_factor:
2569 tem = expand_shift (LSHIFT_EXPR, mode, accum,
2570 build_int_2 (log, 0), NULL_RTX, 0);
2571 accum = force_operand (gen_rtx_MINUS (mode, tem, accum),
2572 (add_target ? add_target
2573 : preserve ? 0 : tem));
2574 val_so_far = (val_so_far << log) - val_so_far;
2581 /* Write a REG_EQUAL note on the last insn so that we can cse
2582 multiplication sequences. Note that if ACCUM is a SUBREG,
2583 we've set the inner register and must properly indicate
2586 tem = op0, nmode = mode;
2587 if (GET_CODE (accum) == SUBREG)
2589 nmode = GET_MODE (SUBREG_REG (accum));
2590 tem = gen_lowpart (nmode, op0);
2593 insn = get_last_insn ();
2594 set_unique_reg_note (insn, REG_EQUAL,
2595 gen_rtx_MULT (nmode, tem, GEN_INT (val_so_far)));
2598 if (variant == negate_variant)
2600 val_so_far = -val_so_far;
2601 accum = expand_unop (mode, neg_optab, accum, target, 0);
2603 else if (variant == add_variant)
2605 val_so_far = val_so_far + 1;
2606 accum = force_operand (gen_rtx_PLUS (mode, accum, op0), target);
2609 if (val != val_so_far)
2615 /* Perform a multiplication and return an rtx for the result.
2616 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
2617 TARGET is a suggestion for where to store the result (an rtx).
2619 We check specially for a constant integer as OP1.
2620 If you want this check for OP0 as well, then before calling
2621 you should swap the two operands if OP0 would be constant. */
2624 expand_mult (enum machine_mode mode, rtx op0, rtx op1, rtx target,
2627 rtx const_op1 = op1;
2628 enum mult_variant variant;
2629 struct algorithm algorithm;
2631 /* synth_mult does an `unsigned int' multiply. As long as the mode is
2632 less than or equal in size to `unsigned int' this doesn't matter.
2633 If the mode is larger than `unsigned int', then synth_mult works only
2634 if the constant value exactly fits in an `unsigned int' without any
2635 truncation. This means that multiplying by negative values does
2636 not work; results are off by 2^32 on a 32 bit machine. */
2638 /* If we are multiplying in DImode, it may still be a win
2639 to try to work with shifts and adds. */
2640 if (GET_CODE (op1) == CONST_DOUBLE
2641 && GET_MODE_CLASS (GET_MODE (op1)) == MODE_INT
2642 && HOST_BITS_PER_INT >= BITS_PER_WORD
2643 && CONST_DOUBLE_HIGH (op1) == 0)
2644 const_op1 = GEN_INT (CONST_DOUBLE_LOW (op1));
2645 else if (HOST_BITS_PER_INT < GET_MODE_BITSIZE (mode)
2646 && GET_CODE (op1) == CONST_INT
2647 && INTVAL (op1) < 0)
2650 /* We used to test optimize here, on the grounds that it's better to
2651 produce a smaller program when -O is not used.
2652 But this causes such a terrible slowdown sometimes
2653 that it seems better to use synth_mult always. */
2655 if (const_op1 && GET_CODE (const_op1) == CONST_INT
2656 && (unsignedp || !flag_trapv))
2658 int mult_cost = rtx_cost (gen_rtx_MULT (mode, op0, op1), SET);
2659 mult_cost = MIN (12 * add_cost[mode], mult_cost);
2661 if (choose_mult_variant (mode, INTVAL (const_op1), &algorithm, &variant,
2663 return expand_mult_const (mode, op0, INTVAL (const_op1), target,
2664 &algorithm, variant);
2667 if (GET_CODE (op0) == CONST_DOUBLE)
2674 /* Expand x*2.0 as x+x. */
2675 if (GET_CODE (op1) == CONST_DOUBLE
2676 && GET_MODE_CLASS (mode) == MODE_FLOAT)
2679 REAL_VALUE_FROM_CONST_DOUBLE (d, op1);
2681 if (REAL_VALUES_EQUAL (d, dconst2))
2683 op0 = force_reg (GET_MODE (op0), op0);
2684 return expand_binop (mode, add_optab, op0, op0,
2685 target, unsignedp, OPTAB_LIB_WIDEN);
2689 /* This used to use umul_optab if unsigned, but for non-widening multiply
2690 there is no difference between signed and unsigned. */
2691 op0 = expand_binop (mode,
2693 && flag_trapv && (GET_MODE_CLASS(mode) == MODE_INT)
2694 ? smulv_optab : smul_optab,
2695 op0, op1, target, unsignedp, OPTAB_LIB_WIDEN);
2701 /* Return the smallest n such that 2**n >= X. */
2704 ceil_log2 (unsigned HOST_WIDE_INT x)
2706 return floor_log2 (x - 1) + 1;
2709 /* Choose a minimal N + 1 bit approximation to 1/D that can be used to
2710 replace division by D, and put the least significant N bits of the result
2711 in *MULTIPLIER_PTR and return the most significant bit.
2713 The width of operations is N (should be <= HOST_BITS_PER_WIDE_INT), the
2714 needed precision is in PRECISION (should be <= N).
2716 PRECISION should be as small as possible so this function can choose
2717 multiplier more freely.
2719 The rounded-up logarithm of D is placed in *lgup_ptr. A shift count that
2720 is to be used for a final right shift is placed in *POST_SHIFT_PTR.
2722 Using this function, x/D will be equal to (x * m) >> (*POST_SHIFT_PTR),
2723 where m is the full HOST_BITS_PER_WIDE_INT + 1 bit multiplier. */
2726 unsigned HOST_WIDE_INT
2727 choose_multiplier (unsigned HOST_WIDE_INT d, int n, int precision,
2728 unsigned HOST_WIDE_INT *multiplier_ptr,
2729 int *post_shift_ptr, int *lgup_ptr)
2731 HOST_WIDE_INT mhigh_hi, mlow_hi;
2732 unsigned HOST_WIDE_INT mhigh_lo, mlow_lo;
2733 int lgup, post_shift;
2735 unsigned HOST_WIDE_INT nl, dummy1;
2736 HOST_WIDE_INT nh, dummy2;
2738 /* lgup = ceil(log2(divisor)); */
2739 lgup = ceil_log2 (d);
2745 pow2 = n + lgup - precision;
2747 if (pow == 2 * HOST_BITS_PER_WIDE_INT)
2749 /* We could handle this with some effort, but this case is much better
2750 handled directly with a scc insn, so rely on caller using that. */
2754 /* mlow = 2^(N + lgup)/d */
2755 if (pow >= HOST_BITS_PER_WIDE_INT)
2757 nh = (HOST_WIDE_INT) 1 << (pow - HOST_BITS_PER_WIDE_INT);
2763 nl = (unsigned HOST_WIDE_INT) 1 << pow;
2765 div_and_round_double (TRUNC_DIV_EXPR, 1, nl, nh, d, (HOST_WIDE_INT) 0,
2766 &mlow_lo, &mlow_hi, &dummy1, &dummy2);
2768 /* mhigh = (2^(N + lgup) + 2^N + lgup - precision)/d */
2769 if (pow2 >= HOST_BITS_PER_WIDE_INT)
2770 nh |= (HOST_WIDE_INT) 1 << (pow2 - HOST_BITS_PER_WIDE_INT);
2772 nl |= (unsigned HOST_WIDE_INT) 1 << pow2;
2773 div_and_round_double (TRUNC_DIV_EXPR, 1, nl, nh, d, (HOST_WIDE_INT) 0,
2774 &mhigh_lo, &mhigh_hi, &dummy1, &dummy2);
2776 if (mhigh_hi && nh - d >= d)
2778 if (mhigh_hi > 1 || mlow_hi > 1)
2780 /* Assert that mlow < mhigh. */
2781 if (! (mlow_hi < mhigh_hi || (mlow_hi == mhigh_hi && mlow_lo < mhigh_lo)))
2784 /* If precision == N, then mlow, mhigh exceed 2^N
2785 (but they do not exceed 2^(N+1)). */
2787 /* Reduce to lowest terms. */
2788 for (post_shift = lgup; post_shift > 0; post_shift--)
2790 unsigned HOST_WIDE_INT ml_lo = (mlow_hi << (HOST_BITS_PER_WIDE_INT - 1)) | (mlow_lo >> 1);
2791 unsigned HOST_WIDE_INT mh_lo = (mhigh_hi << (HOST_BITS_PER_WIDE_INT - 1)) | (mhigh_lo >> 1);
2801 *post_shift_ptr = post_shift;
2803 if (n < HOST_BITS_PER_WIDE_INT)
2805 unsigned HOST_WIDE_INT mask = ((unsigned HOST_WIDE_INT) 1 << n) - 1;
2806 *multiplier_ptr = mhigh_lo & mask;
2807 return mhigh_lo >= mask;
2811 *multiplier_ptr = mhigh_lo;
2816 /* Compute the inverse of X mod 2**n, i.e., find Y such that X * Y is
2817 congruent to 1 (mod 2**N). */
2819 static unsigned HOST_WIDE_INT
2820 invert_mod2n (unsigned HOST_WIDE_INT x, int n)
2822 /* Solve x*y == 1 (mod 2^n), where x is odd. Return y. */
2824 /* The algorithm notes that the choice y = x satisfies
2825 x*y == 1 mod 2^3, since x is assumed odd.
2826 Each iteration doubles the number of bits of significance in y. */
2828 unsigned HOST_WIDE_INT mask;
2829 unsigned HOST_WIDE_INT y = x;
2832 mask = (n == HOST_BITS_PER_WIDE_INT
2833 ? ~(unsigned HOST_WIDE_INT) 0
2834 : ((unsigned HOST_WIDE_INT) 1 << n) - 1);
2838 y = y * (2 - x*y) & mask; /* Modulo 2^N */
2844 /* Emit code to adjust ADJ_OPERAND after multiplication of wrong signedness
2845 flavor of OP0 and OP1. ADJ_OPERAND is already the high half of the
2846 product OP0 x OP1. If UNSIGNEDP is nonzero, adjust the signed product
2847 to become unsigned, if UNSIGNEDP is zero, adjust the unsigned product to
2850 The result is put in TARGET if that is convenient.
2852 MODE is the mode of operation. */
2855 expand_mult_highpart_adjust (enum machine_mode mode, rtx adj_operand, rtx op0,
2856 rtx op1, rtx target, int unsignedp)
2859 enum rtx_code adj_code = unsignedp ? PLUS : MINUS;
2861 tem = expand_shift (RSHIFT_EXPR, mode, op0,
2862 build_int_2 (GET_MODE_BITSIZE (mode) - 1, 0),
2864 tem = expand_and (mode, tem, op1, NULL_RTX);
2866 = force_operand (gen_rtx_fmt_ee (adj_code, mode, adj_operand, tem),
2869 tem = expand_shift (RSHIFT_EXPR, mode, op1,
2870 build_int_2 (GET_MODE_BITSIZE (mode) - 1, 0),
2872 tem = expand_and (mode, tem, op0, NULL_RTX);
2873 target = force_operand (gen_rtx_fmt_ee (adj_code, mode, adj_operand, tem),
2879 /* Subroutine of expand_mult_highpart. Return the MODE high part of OP. */
2882 extract_high_half (enum machine_mode mode, rtx op)
2884 enum machine_mode wider_mode;
2886 if (mode == word_mode)
2887 return gen_highpart (mode, op);
2889 wider_mode = GET_MODE_WIDER_MODE (mode);
2890 op = expand_shift (RSHIFT_EXPR, wider_mode, op,
2891 build_int_2 (GET_MODE_BITSIZE (mode), 0), 0, 1);
2892 return convert_modes (mode, wider_mode, op, 0);
2895 /* Like expand_mult_highpart, but only consider using a multiplication
2896 optab. OP1 is an rtx for the constant operand. */
2899 expand_mult_highpart_optab (enum machine_mode mode, rtx op0, rtx op1,
2900 rtx target, int unsignedp, int max_cost)
2902 rtx narrow_op1 = gen_int_mode (INTVAL (op1), mode);
2903 enum machine_mode wider_mode;
2908 wider_mode = GET_MODE_WIDER_MODE (mode);
2909 size = GET_MODE_BITSIZE (mode);
2911 /* Firstly, try using a multiplication insn that only generates the needed
2912 high part of the product, and in the sign flavor of unsignedp. */
2913 if (mul_highpart_cost[mode] < max_cost)
2915 moptab = unsignedp ? umul_highpart_optab : smul_highpart_optab;
2916 tem = expand_binop (mode, moptab, op0, narrow_op1, target,
2917 unsignedp, OPTAB_DIRECT);
2922 /* Secondly, same as above, but use sign flavor opposite of unsignedp.
2923 Need to adjust the result after the multiplication. */
2924 if (size - 1 < BITS_PER_WORD
2925 && (mul_highpart_cost[mode] + 2 * shift_cost[mode][size-1]
2926 + 4 * add_cost[mode] < max_cost))
2928 moptab = unsignedp ? smul_highpart_optab : umul_highpart_optab;
2929 tem = expand_binop (mode, moptab, op0, narrow_op1, target,
2930 unsignedp, OPTAB_DIRECT);
2932 /* We used the wrong signedness. Adjust the result. */
2933 return expand_mult_highpart_adjust (mode, tem, op0, narrow_op1,
2937 /* Try widening multiplication. */
2938 moptab = unsignedp ? umul_widen_optab : smul_widen_optab;
2939 if (moptab->handlers[wider_mode].insn_code != CODE_FOR_nothing
2940 && mul_widen_cost[wider_mode] < max_cost)
2942 tem = expand_binop (wider_mode, moptab, op0, narrow_op1, 0,
2943 unsignedp, OPTAB_WIDEN);
2945 return extract_high_half (mode, tem);
2948 /* Try widening the mode and perform a non-widening multiplication. */
2949 moptab = smul_optab;
2950 if (smul_optab->handlers[wider_mode].insn_code != CODE_FOR_nothing
2951 && size - 1 < BITS_PER_WORD
2952 && mul_cost[wider_mode] + shift_cost[mode][size-1] < max_cost)
2954 tem = expand_binop (wider_mode, moptab, op0, op1, 0,
2955 unsignedp, OPTAB_WIDEN);
2957 return extract_high_half (mode, tem);
2960 /* Try widening multiplication of opposite signedness, and adjust. */
2961 moptab = unsignedp ? smul_widen_optab : umul_widen_optab;
2962 if (moptab->handlers[wider_mode].insn_code != CODE_FOR_nothing
2963 && size - 1 < BITS_PER_WORD
2964 && (mul_widen_cost[wider_mode] + 2 * shift_cost[mode][size-1]
2965 + 4 * add_cost[mode] < max_cost))
2967 tem = expand_binop (wider_mode, moptab, op0, narrow_op1,
2968 NULL_RTX, ! unsignedp, OPTAB_WIDEN);
2971 tem = extract_high_half (mode, tem);
2972 /* We used the wrong signedness. Adjust the result. */
2973 return expand_mult_highpart_adjust (mode, tem, op0, narrow_op1,
2981 /* Emit code to multiply OP0 and CNST1, putting the high half of the result
2982 in TARGET if that is convenient, and return where the result is. If the
2983 operation can not be performed, 0 is returned.
2985 MODE is the mode of operation and result.
2987 UNSIGNEDP nonzero means unsigned multiply.
2989 MAX_COST is the total allowed cost for the expanded RTL. */
2992 expand_mult_highpart (enum machine_mode mode, rtx op0,
2993 unsigned HOST_WIDE_INT cnst1, rtx target,
2994 int unsignedp, int max_cost)
2996 enum machine_mode wider_mode = GET_MODE_WIDER_MODE (mode);
2998 bool sign_adjust = false;
2999 enum mult_variant variant;
3000 struct algorithm alg;
3003 /* We can't support modes wider than HOST_BITS_PER_INT. */
3004 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
3007 op1 = gen_int_mode (cnst1, wider_mode);
3008 cnst1 &= GET_MODE_MASK (mode);
3010 /* We can't optimize modes wider than BITS_PER_WORD.
3011 ??? We might be able to perform double-word arithmetic if
3012 mode == word_mode, however all the cost calculations in
3013 synth_mult etc. assume single-word operations. */
3014 if (GET_MODE_BITSIZE (wider_mode) > BITS_PER_WORD)
3015 return expand_mult_highpart_optab (mode, op0, op1, target,
3016 unsignedp, max_cost);
3018 extra_cost = shift_cost[mode][GET_MODE_BITSIZE (mode) - 1];
3020 /* Check whether we try to multiply by a negative constant. */
3021 if (!unsignedp && ((cnst1 >> (GET_MODE_BITSIZE (mode) - 1)) & 1))
3024 extra_cost += add_cost[mode];
3027 /* See whether shift/add multiplication is cheap enough. */
3028 if (choose_mult_variant (wider_mode, cnst1, &alg, &variant,
3029 max_cost - extra_cost))
3031 /* See whether the specialized multiplication optabs are
3032 cheaper than the shift/add version. */
3033 tem = expand_mult_highpart_optab (mode, op0, op1, target,
3034 unsignedp, alg.cost + extra_cost);
3038 tem = convert_to_mode (wider_mode, op0, unsignedp);
3039 tem = expand_mult_const (wider_mode, tem, cnst1, 0, &alg, variant);
3040 tem = extract_high_half (mode, tem);
3042 /* Adjust result for signedness. */
3044 tem = force_operand (gen_rtx_MINUS (mode, tem, op0), tem);
3048 return expand_mult_highpart_optab (mode, op0, op1, target,
3049 unsignedp, max_cost);
3052 /* Emit the code to divide OP0 by OP1, putting the result in TARGET
3053 if that is convenient, and returning where the result is.
3054 You may request either the quotient or the remainder as the result;
3055 specify REM_FLAG nonzero to get the remainder.
3057 CODE is the expression code for which kind of division this is;
3058 it controls how rounding is done. MODE is the machine mode to use.
3059 UNSIGNEDP nonzero means do unsigned division. */
3061 /* ??? For CEIL_MOD_EXPR, can compute incorrect remainder with ANDI
3062 and then correct it by or'ing in missing high bits
3063 if result of ANDI is nonzero.
3064 For ROUND_MOD_EXPR, can use ANDI and then sign-extend the result.
3065 This could optimize to a bfexts instruction.
3066 But C doesn't use these operations, so their optimizations are
3068 /* ??? For modulo, we don't actually need the highpart of the first product,
3069 the low part will do nicely. And for small divisors, the second multiply
3070 can also be a low-part only multiply or even be completely left out.
3071 E.g. to calculate the remainder of a division by 3 with a 32 bit
3072 multiply, multiply with 0x55555556 and extract the upper two bits;
3073 the result is exact for inputs up to 0x1fffffff.
3074 The input range can be reduced by using cross-sum rules.
3075 For odd divisors >= 3, the following table gives right shift counts
3076 so that if a number is shifted by an integer multiple of the given
3077 amount, the remainder stays the same:
3078 2, 4, 3, 6, 10, 12, 4, 8, 18, 6, 11, 20, 18, 0, 5, 10, 12, 0, 12, 20,
3079 14, 12, 23, 21, 8, 0, 20, 18, 0, 0, 6, 12, 0, 22, 0, 18, 20, 30, 0, 0,
3080 0, 8, 0, 11, 12, 10, 36, 0, 30, 0, 0, 12, 0, 0, 0, 0, 44, 12, 24, 0,
3081 20, 0, 7, 14, 0, 18, 36, 0, 0, 46, 60, 0, 42, 0, 15, 24, 20, 0, 0, 33,
3082 0, 20, 0, 0, 18, 0, 60, 0, 0, 0, 0, 0, 40, 18, 0, 0, 12
3084 Cross-sum rules for even numbers can be derived by leaving as many bits
3085 to the right alone as the divisor has zeros to the right.
3086 E.g. if x is an unsigned 32 bit number:
3087 (x mod 12) == (((x & 1023) + ((x >> 8) & ~3)) * 0x15555558 >> 2 * 3) >> 28
3090 #define EXACT_POWER_OF_2_OR_ZERO_P(x) (((x) & ((x) - 1)) == 0)
3093 expand_divmod (int rem_flag, enum tree_code code, enum machine_mode mode,
3094 rtx op0, rtx op1, rtx target, int unsignedp)
3096 enum machine_mode compute_mode;
3098 rtx quotient = 0, remainder = 0;
3102 optab optab1, optab2;
3103 int op1_is_constant, op1_is_pow2 = 0;
3104 int max_cost, extra_cost;
3105 static HOST_WIDE_INT last_div_const = 0;
3106 static HOST_WIDE_INT ext_op1;
3108 op1_is_constant = GET_CODE (op1) == CONST_INT;
3109 if (op1_is_constant)
3111 ext_op1 = INTVAL (op1);
3113 ext_op1 &= GET_MODE_MASK (mode);
3114 op1_is_pow2 = ((EXACT_POWER_OF_2_OR_ZERO_P (ext_op1)
3115 || (! unsignedp && EXACT_POWER_OF_2_OR_ZERO_P (-ext_op1))));
3119 This is the structure of expand_divmod:
3121 First comes code to fix up the operands so we can perform the operations
3122 correctly and efficiently.
3124 Second comes a switch statement with code specific for each rounding mode.
3125 For some special operands this code emits all RTL for the desired
3126 operation, for other cases, it generates only a quotient and stores it in
3127 QUOTIENT. The case for trunc division/remainder might leave quotient = 0,
3128 to indicate that it has not done anything.
3130 Last comes code that finishes the operation. If QUOTIENT is set and
3131 REM_FLAG is set, the remainder is computed as OP0 - QUOTIENT * OP1. If
3132 QUOTIENT is not set, it is computed using trunc rounding.
3134 We try to generate special code for division and remainder when OP1 is a
3135 constant. If |OP1| = 2**n we can use shifts and some other fast
3136 operations. For other values of OP1, we compute a carefully selected
3137 fixed-point approximation m = 1/OP1, and generate code that multiplies OP0
3140 In all cases but EXACT_DIV_EXPR, this multiplication requires the upper
3141 half of the product. Different strategies for generating the product are
3142 implemented in expand_mult_highpart.
3144 If what we actually want is the remainder, we generate that by another
3145 by-constant multiplication and a subtraction. */
3147 /* We shouldn't be called with OP1 == const1_rtx, but some of the
3148 code below will malfunction if we are, so check here and handle
3149 the special case if so. */
3150 if (op1 == const1_rtx)
3151 return rem_flag ? const0_rtx : op0;
3153 /* When dividing by -1, we could get an overflow.
3154 negv_optab can handle overflows. */
3155 if (! unsignedp && op1 == constm1_rtx)
3159 return expand_unop (mode, flag_trapv && GET_MODE_CLASS(mode) == MODE_INT
3160 ? negv_optab : neg_optab, op0, target, 0);
3164 /* Don't use the function value register as a target
3165 since we have to read it as well as write it,
3166 and function-inlining gets confused by this. */
3167 && ((REG_P (target) && REG_FUNCTION_VALUE_P (target))
3168 /* Don't clobber an operand while doing a multi-step calculation. */
3169 || ((rem_flag || op1_is_constant)
3170 && (reg_mentioned_p (target, op0)
3171 || (GET_CODE (op0) == MEM && GET_CODE (target) == MEM)))
3172 || reg_mentioned_p (target, op1)
3173 || (GET_CODE (op1) == MEM && GET_CODE (target) == MEM)))
3176 /* Get the mode in which to perform this computation. Normally it will
3177 be MODE, but sometimes we can't do the desired operation in MODE.
3178 If so, pick a wider mode in which we can do the operation. Convert
3179 to that mode at the start to avoid repeated conversions.
3181 First see what operations we need. These depend on the expression
3182 we are evaluating. (We assume that divxx3 insns exist under the
3183 same conditions that modxx3 insns and that these insns don't normally
3184 fail. If these assumptions are not correct, we may generate less
3185 efficient code in some cases.)
3187 Then see if we find a mode in which we can open-code that operation
3188 (either a division, modulus, or shift). Finally, check for the smallest
3189 mode for which we can do the operation with a library call. */
3191 /* We might want to refine this now that we have division-by-constant
3192 optimization. Since expand_mult_highpart tries so many variants, it is
3193 not straightforward to generalize this. Maybe we should make an array
3194 of possible modes in init_expmed? Save this for GCC 2.7. */
3196 optab1 = ((op1_is_pow2 && op1 != const0_rtx)
3197 ? (unsignedp ? lshr_optab : ashr_optab)
3198 : (unsignedp ? udiv_optab : sdiv_optab));
3199 optab2 = ((op1_is_pow2 && op1 != const0_rtx)
3201 : (unsignedp ? udivmod_optab : sdivmod_optab));
3203 for (compute_mode = mode; compute_mode != VOIDmode;
3204 compute_mode = GET_MODE_WIDER_MODE (compute_mode))
3205 if (optab1->handlers[compute_mode].insn_code != CODE_FOR_nothing
3206 || optab2->handlers[compute_mode].insn_code != CODE_FOR_nothing)
3209 if (compute_mode == VOIDmode)
3210 for (compute_mode = mode; compute_mode != VOIDmode;
3211 compute_mode = GET_MODE_WIDER_MODE (compute_mode))
3212 if (optab1->handlers[compute_mode].libfunc
3213 || optab2->handlers[compute_mode].libfunc)
3216 /* If we still couldn't find a mode, use MODE, but we'll probably abort
3218 if (compute_mode == VOIDmode)
3219 compute_mode = mode;
3221 if (target && GET_MODE (target) == compute_mode)
3224 tquotient = gen_reg_rtx (compute_mode);
3226 size = GET_MODE_BITSIZE (compute_mode);
3228 /* It should be possible to restrict the precision to GET_MODE_BITSIZE
3229 (mode), and thereby get better code when OP1 is a constant. Do that
3230 later. It will require going over all usages of SIZE below. */
3231 size = GET_MODE_BITSIZE (mode);
3234 /* Only deduct something for a REM if the last divide done was
3235 for a different constant. Then set the constant of the last
3237 max_cost = div_cost[compute_mode]
3238 - (rem_flag && ! (last_div_const != 0 && op1_is_constant
3239 && INTVAL (op1) == last_div_const)
3240 ? mul_cost[compute_mode] + add_cost[compute_mode]
3243 last_div_const = ! rem_flag && op1_is_constant ? INTVAL (op1) : 0;
3245 /* Now convert to the best mode to use. */
3246 if (compute_mode != mode)
3248 op0 = convert_modes (compute_mode, mode, op0, unsignedp);
3249 op1 = convert_modes (compute_mode, mode, op1, unsignedp);
3251 /* convert_modes may have placed op1 into a register, so we
3252 must recompute the following. */
3253 op1_is_constant = GET_CODE (op1) == CONST_INT;
3254 op1_is_pow2 = (op1_is_constant
3255 && ((EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1))
3257 && EXACT_POWER_OF_2_OR_ZERO_P (-INTVAL (op1)))))) ;
3260 /* If one of the operands is a volatile MEM, copy it into a register. */
3262 if (GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0))
3263 op0 = force_reg (compute_mode, op0);
3264 if (GET_CODE (op1) == MEM && MEM_VOLATILE_P (op1))
3265 op1 = force_reg (compute_mode, op1);
3267 /* If we need the remainder or if OP1 is constant, we need to
3268 put OP0 in a register in case it has any queued subexpressions. */
3269 if (rem_flag || op1_is_constant)
3270 op0 = force_reg (compute_mode, op0);
3272 last = get_last_insn ();
3274 /* Promote floor rounding to trunc rounding for unsigned operations. */
3277 if (code == FLOOR_DIV_EXPR)
3278 code = TRUNC_DIV_EXPR;
3279 if (code == FLOOR_MOD_EXPR)
3280 code = TRUNC_MOD_EXPR;
3281 if (code == EXACT_DIV_EXPR && op1_is_pow2)
3282 code = TRUNC_DIV_EXPR;
3285 if (op1 != const0_rtx)
3288 case TRUNC_MOD_EXPR:
3289 case TRUNC_DIV_EXPR:
3290 if (op1_is_constant)
3294 unsigned HOST_WIDE_INT mh, ml;
3295 int pre_shift, post_shift;
3297 unsigned HOST_WIDE_INT d = (INTVAL (op1)
3298 & GET_MODE_MASK (compute_mode));
3300 if (EXACT_POWER_OF_2_OR_ZERO_P (d))
3302 pre_shift = floor_log2 (d);
3306 = expand_binop (compute_mode, and_optab, op0,
3307 GEN_INT (((HOST_WIDE_INT) 1 << pre_shift) - 1),
3311 return gen_lowpart (mode, remainder);
3313 quotient = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3314 build_int_2 (pre_shift, 0),
3317 else if (size <= HOST_BITS_PER_WIDE_INT)
3319 if (d >= ((unsigned HOST_WIDE_INT) 1 << (size - 1)))
3321 /* Most significant bit of divisor is set; emit an scc
3323 quotient = emit_store_flag (tquotient, GEU, op0, op1,
3324 compute_mode, 1, 1);
3330 /* Find a suitable multiplier and right shift count
3331 instead of multiplying with D. */
3333 mh = choose_multiplier (d, size, size,
3334 &ml, &post_shift, &dummy);
3336 /* If the suggested multiplier is more than SIZE bits,
3337 we can do better for even divisors, using an
3338 initial right shift. */
3339 if (mh != 0 && (d & 1) == 0)
3341 pre_shift = floor_log2 (d & -d);
3342 mh = choose_multiplier (d >> pre_shift, size,
3344 &ml, &post_shift, &dummy);
3355 if (post_shift - 1 >= BITS_PER_WORD)
3359 = (shift_cost[compute_mode][post_shift - 1]
3360 + shift_cost[compute_mode][1]
3361 + 2 * add_cost[compute_mode]);
3362 t1 = expand_mult_highpart (compute_mode, op0, ml,
3364 max_cost - extra_cost);
3367 t2 = force_operand (gen_rtx_MINUS (compute_mode,
3370 t3 = expand_shift (RSHIFT_EXPR, compute_mode, t2,
3371 build_int_2 (1, 0), NULL_RTX,1);
3372 t4 = force_operand (gen_rtx_PLUS (compute_mode,
3376 = expand_shift (RSHIFT_EXPR, compute_mode, t4,
3377 build_int_2 (post_shift - 1, 0),
3384 if (pre_shift >= BITS_PER_WORD
3385 || post_shift >= BITS_PER_WORD)
3388 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3389 build_int_2 (pre_shift, 0),
3392 = (shift_cost[compute_mode][pre_shift]
3393 + shift_cost[compute_mode][post_shift]);
3394 t2 = expand_mult_highpart (compute_mode, t1, ml,
3396 max_cost - extra_cost);
3400 = expand_shift (RSHIFT_EXPR, compute_mode, t2,
3401 build_int_2 (post_shift, 0),
3406 else /* Too wide mode to use tricky code */
3409 insn = get_last_insn ();
3411 && (set = single_set (insn)) != 0
3412 && SET_DEST (set) == quotient)
3413 set_unique_reg_note (insn,
3415 gen_rtx_UDIV (compute_mode, op0, op1));
3417 else /* TRUNC_DIV, signed */
3419 unsigned HOST_WIDE_INT ml;
3420 int lgup, post_shift;
3421 HOST_WIDE_INT d = INTVAL (op1);
3422 unsigned HOST_WIDE_INT abs_d = d >= 0 ? d : -d;
3424 /* n rem d = n rem -d */
3425 if (rem_flag && d < 0)
3428 op1 = gen_int_mode (abs_d, compute_mode);
3434 quotient = expand_unop (compute_mode, neg_optab, op0,
3436 else if (abs_d == (unsigned HOST_WIDE_INT) 1 << (size - 1))
3438 /* This case is not handled correctly below. */
3439 quotient = emit_store_flag (tquotient, EQ, op0, op1,
3440 compute_mode, 1, 1);
3444 else if (EXACT_POWER_OF_2_OR_ZERO_P (d)
3445 && (rem_flag ? smod_pow2_cheap[compute_mode]
3446 : sdiv_pow2_cheap[compute_mode])
3447 /* ??? The cheap metric is computed only for
3448 word_mode. If this operation is wider, this may
3449 not be so. Assume true if the optab has an
3450 expander for this mode. */
3451 && (((rem_flag ? smod_optab : sdiv_optab)
3452 ->handlers[compute_mode].insn_code
3453 != CODE_FOR_nothing)
3454 || (sdivmod_optab->handlers[compute_mode]
3455 .insn_code != CODE_FOR_nothing)))
3457 else if (EXACT_POWER_OF_2_OR_ZERO_P (abs_d))
3459 lgup = floor_log2 (abs_d);
3460 if (BRANCH_COST < 1 || (abs_d != 2 && BRANCH_COST < 3))
3462 rtx label = gen_label_rtx ();
3465 t1 = copy_to_mode_reg (compute_mode, op0);
3466 do_cmp_and_jump (t1, const0_rtx, GE,
3467 compute_mode, label);
3468 expand_inc (t1, gen_int_mode (abs_d - 1,
3471 quotient = expand_shift (RSHIFT_EXPR, compute_mode, t1,
3472 build_int_2 (lgup, 0),
3478 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3479 build_int_2 (size - 1, 0),
3481 t2 = expand_shift (RSHIFT_EXPR, compute_mode, t1,
3482 build_int_2 (size - lgup, 0),
3484 t3 = force_operand (gen_rtx_PLUS (compute_mode,
3487 quotient = expand_shift (RSHIFT_EXPR, compute_mode, t3,
3488 build_int_2 (lgup, 0),
3492 /* We have computed OP0 / abs(OP1). If OP1 is negative, negate
3496 insn = get_last_insn ();
3498 && (set = single_set (insn)) != 0
3499 && SET_DEST (set) == quotient
3500 && abs_d < ((unsigned HOST_WIDE_INT) 1
3501 << (HOST_BITS_PER_WIDE_INT - 1)))
3502 set_unique_reg_note (insn,
3504 gen_rtx_DIV (compute_mode,
3511 quotient = expand_unop (compute_mode, neg_optab,
3512 quotient, quotient, 0);
3515 else if (size <= HOST_BITS_PER_WIDE_INT)
3517 choose_multiplier (abs_d, size, size - 1,
3518 &ml, &post_shift, &lgup);
3519 if (ml < (unsigned HOST_WIDE_INT) 1 << (size - 1))
3523 if (post_shift >= BITS_PER_WORD
3524 || size - 1 >= BITS_PER_WORD)
3527 extra_cost = (shift_cost[compute_mode][post_shift]
3528 + shift_cost[compute_mode][size - 1]
3529 + add_cost[compute_mode]);
3530 t1 = expand_mult_highpart (compute_mode, op0, ml,
3532 max_cost - extra_cost);
3535 t2 = expand_shift (RSHIFT_EXPR, compute_mode, t1,
3536 build_int_2 (post_shift, 0), NULL_RTX, 0);
3537 t3 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3538 build_int_2 (size - 1, 0), NULL_RTX, 0);
3541 = force_operand (gen_rtx_MINUS (compute_mode,
3546 = force_operand (gen_rtx_MINUS (compute_mode,
3554 if (post_shift >= BITS_PER_WORD
3555 || size - 1 >= BITS_PER_WORD)
3558 ml |= (~(unsigned HOST_WIDE_INT) 0) << (size - 1);
3559 extra_cost = (shift_cost[compute_mode][post_shift]
3560 + shift_cost[compute_mode][size - 1]
3561 + 2 * add_cost[compute_mode]);
3562 t1 = expand_mult_highpart (compute_mode, op0, ml,
3564 max_cost - extra_cost);
3567 t2 = force_operand (gen_rtx_PLUS (compute_mode,
3570 t3 = expand_shift (RSHIFT_EXPR, compute_mode, t2,
3571 build_int_2 (post_shift, 0),
3573 t4 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3574 build_int_2 (size - 1, 0),
3578 = force_operand (gen_rtx_MINUS (compute_mode,
3583 = force_operand (gen_rtx_MINUS (compute_mode,
3588 else /* Too wide mode to use tricky code */
3591 insn = get_last_insn ();
3593 && (set = single_set (insn)) != 0
3594 && SET_DEST (set) == quotient)
3595 set_unique_reg_note (insn,
3597 gen_rtx_DIV (compute_mode, op0, op1));
3602 delete_insns_since (last);
3605 case FLOOR_DIV_EXPR:
3606 case FLOOR_MOD_EXPR:
3607 /* We will come here only for signed operations. */
3608 if (op1_is_constant && HOST_BITS_PER_WIDE_INT >= size)
3610 unsigned HOST_WIDE_INT mh, ml;
3611 int pre_shift, lgup, post_shift;
3612 HOST_WIDE_INT d = INTVAL (op1);
3616 /* We could just as easily deal with negative constants here,
3617 but it does not seem worth the trouble for GCC 2.6. */
3618 if (EXACT_POWER_OF_2_OR_ZERO_P (d))
3620 pre_shift = floor_log2 (d);
3623 remainder = expand_binop (compute_mode, and_optab, op0,
3624 GEN_INT (((HOST_WIDE_INT) 1 << pre_shift) - 1),
3625 remainder, 0, OPTAB_LIB_WIDEN);
3627 return gen_lowpart (mode, remainder);
3629 quotient = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3630 build_int_2 (pre_shift, 0),
3637 mh = choose_multiplier (d, size, size - 1,
3638 &ml, &post_shift, &lgup);
3642 if (post_shift < BITS_PER_WORD
3643 && size - 1 < BITS_PER_WORD)
3645 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3646 build_int_2 (size - 1, 0),
3648 t2 = expand_binop (compute_mode, xor_optab, op0, t1,
3649 NULL_RTX, 0, OPTAB_WIDEN);
3650 extra_cost = (shift_cost[compute_mode][post_shift]
3651 + shift_cost[compute_mode][size - 1]
3652 + 2 * add_cost[compute_mode]);
3653 t3 = expand_mult_highpart (compute_mode, t2, ml,
3655 max_cost - extra_cost);
3658 t4 = expand_shift (RSHIFT_EXPR, compute_mode, t3,
3659 build_int_2 (post_shift, 0),
3661 quotient = expand_binop (compute_mode, xor_optab,
3662 t4, t1, tquotient, 0,
3670 rtx nsign, t1, t2, t3, t4;
3671 t1 = force_operand (gen_rtx_PLUS (compute_mode,
3672 op0, constm1_rtx), NULL_RTX);
3673 t2 = expand_binop (compute_mode, ior_optab, op0, t1, NULL_RTX,
3675 nsign = expand_shift (RSHIFT_EXPR, compute_mode, t2,
3676 build_int_2 (size - 1, 0), NULL_RTX, 0);
3677 t3 = force_operand (gen_rtx_MINUS (compute_mode, t1, nsign),
3679 t4 = expand_divmod (0, TRUNC_DIV_EXPR, compute_mode, t3, op1,
3684 t5 = expand_unop (compute_mode, one_cmpl_optab, nsign,
3686 quotient = force_operand (gen_rtx_PLUS (compute_mode,
3695 delete_insns_since (last);
3697 /* Try using an instruction that produces both the quotient and
3698 remainder, using truncation. We can easily compensate the quotient
3699 or remainder to get floor rounding, once we have the remainder.
3700 Notice that we compute also the final remainder value here,
3701 and return the result right away. */
3702 if (target == 0 || GET_MODE (target) != compute_mode)
3703 target = gen_reg_rtx (compute_mode);
3708 = GET_CODE (target) == REG ? target : gen_reg_rtx (compute_mode);
3709 quotient = gen_reg_rtx (compute_mode);
3714 = GET_CODE (target) == REG ? target : gen_reg_rtx (compute_mode);
3715 remainder = gen_reg_rtx (compute_mode);
3718 if (expand_twoval_binop (sdivmod_optab, op0, op1,
3719 quotient, remainder, 0))
3721 /* This could be computed with a branch-less sequence.
3722 Save that for later. */
3724 rtx label = gen_label_rtx ();
3725 do_cmp_and_jump (remainder, const0_rtx, EQ, compute_mode, label);
3726 tem = expand_binop (compute_mode, xor_optab, op0, op1,
3727 NULL_RTX, 0, OPTAB_WIDEN);
3728 do_cmp_and_jump (tem, const0_rtx, GE, compute_mode, label);
3729 expand_dec (quotient, const1_rtx);
3730 expand_inc (remainder, op1);
3732 return gen_lowpart (mode, rem_flag ? remainder : quotient);
3735 /* No luck with division elimination or divmod. Have to do it
3736 by conditionally adjusting op0 *and* the result. */
3738 rtx label1, label2, label3, label4, label5;
3742 quotient = gen_reg_rtx (compute_mode);
3743 adjusted_op0 = copy_to_mode_reg (compute_mode, op0);
3744 label1 = gen_label_rtx ();
3745 label2 = gen_label_rtx ();
3746 label3 = gen_label_rtx ();
3747 label4 = gen_label_rtx ();
3748 label5 = gen_label_rtx ();
3749 do_cmp_and_jump (op1, const0_rtx, LT, compute_mode, label2);
3750 do_cmp_and_jump (adjusted_op0, const0_rtx, LT, compute_mode, label1);
3751 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
3752 quotient, 0, OPTAB_LIB_WIDEN);
3753 if (tem != quotient)
3754 emit_move_insn (quotient, tem);
3755 emit_jump_insn (gen_jump (label5));
3757 emit_label (label1);
3758 expand_inc (adjusted_op0, const1_rtx);
3759 emit_jump_insn (gen_jump (label4));
3761 emit_label (label2);
3762 do_cmp_and_jump (adjusted_op0, const0_rtx, GT, compute_mode, label3);
3763 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
3764 quotient, 0, OPTAB_LIB_WIDEN);
3765 if (tem != quotient)
3766 emit_move_insn (quotient, tem);
3767 emit_jump_insn (gen_jump (label5));
3769 emit_label (label3);
3770 expand_dec (adjusted_op0, const1_rtx);
3771 emit_label (label4);
3772 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
3773 quotient, 0, OPTAB_LIB_WIDEN);
3774 if (tem != quotient)
3775 emit_move_insn (quotient, tem);
3776 expand_dec (quotient, const1_rtx);
3777 emit_label (label5);
3785 if (op1_is_constant && EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1)))
3788 unsigned HOST_WIDE_INT d = INTVAL (op1);
3789 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3790 build_int_2 (floor_log2 (d), 0),
3792 t2 = expand_binop (compute_mode, and_optab, op0,
3794 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3795 t3 = gen_reg_rtx (compute_mode);
3796 t3 = emit_store_flag (t3, NE, t2, const0_rtx,
3797 compute_mode, 1, 1);
3801 lab = gen_label_rtx ();
3802 do_cmp_and_jump (t2, const0_rtx, EQ, compute_mode, lab);
3803 expand_inc (t1, const1_rtx);
3808 quotient = force_operand (gen_rtx_PLUS (compute_mode,
3814 /* Try using an instruction that produces both the quotient and
3815 remainder, using truncation. We can easily compensate the
3816 quotient or remainder to get ceiling rounding, once we have the
3817 remainder. Notice that we compute also the final remainder
3818 value here, and return the result right away. */
3819 if (target == 0 || GET_MODE (target) != compute_mode)
3820 target = gen_reg_rtx (compute_mode);
3824 remainder = (GET_CODE (target) == REG
3825 ? target : gen_reg_rtx (compute_mode));
3826 quotient = gen_reg_rtx (compute_mode);
3830 quotient = (GET_CODE (target) == REG
3831 ? target : gen_reg_rtx (compute_mode));
3832 remainder = gen_reg_rtx (compute_mode);
3835 if (expand_twoval_binop (udivmod_optab, op0, op1, quotient,
3838 /* This could be computed with a branch-less sequence.
3839 Save that for later. */
3840 rtx label = gen_label_rtx ();
3841 do_cmp_and_jump (remainder, const0_rtx, EQ,
3842 compute_mode, label);
3843 expand_inc (quotient, const1_rtx);
3844 expand_dec (remainder, op1);
3846 return gen_lowpart (mode, rem_flag ? remainder : quotient);
3849 /* No luck with division elimination or divmod. Have to do it
3850 by conditionally adjusting op0 *and* the result. */
3853 rtx adjusted_op0, tem;
3855 quotient = gen_reg_rtx (compute_mode);
3856 adjusted_op0 = copy_to_mode_reg (compute_mode, op0);
3857 label1 = gen_label_rtx ();
3858 label2 = gen_label_rtx ();
3859 do_cmp_and_jump (adjusted_op0, const0_rtx, NE,
3860 compute_mode, label1);
3861 emit_move_insn (quotient, const0_rtx);
3862 emit_jump_insn (gen_jump (label2));
3864 emit_label (label1);
3865 expand_dec (adjusted_op0, const1_rtx);
3866 tem = expand_binop (compute_mode, udiv_optab, adjusted_op0, op1,
3867 quotient, 1, OPTAB_LIB_WIDEN);
3868 if (tem != quotient)
3869 emit_move_insn (quotient, tem);
3870 expand_inc (quotient, const1_rtx);
3871 emit_label (label2);
3876 if (op1_is_constant && EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1))
3877 && INTVAL (op1) >= 0)
3879 /* This is extremely similar to the code for the unsigned case
3880 above. For 2.7 we should merge these variants, but for
3881 2.6.1 I don't want to touch the code for unsigned since that
3882 get used in C. The signed case will only be used by other
3886 unsigned HOST_WIDE_INT d = INTVAL (op1);
3887 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3888 build_int_2 (floor_log2 (d), 0),
3890 t2 = expand_binop (compute_mode, and_optab, op0,
3892 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3893 t3 = gen_reg_rtx (compute_mode);
3894 t3 = emit_store_flag (t3, NE, t2, const0_rtx,
3895 compute_mode, 1, 1);
3899 lab = gen_label_rtx ();
3900 do_cmp_and_jump (t2, const0_rtx, EQ, compute_mode, lab);
3901 expand_inc (t1, const1_rtx);
3906 quotient = force_operand (gen_rtx_PLUS (compute_mode,
3912 /* Try using an instruction that produces both the quotient and
3913 remainder, using truncation. We can easily compensate the
3914 quotient or remainder to get ceiling rounding, once we have the
3915 remainder. Notice that we compute also the final remainder
3916 value here, and return the result right away. */
3917 if (target == 0 || GET_MODE (target) != compute_mode)
3918 target = gen_reg_rtx (compute_mode);
3921 remainder= (GET_CODE (target) == REG
3922 ? target : gen_reg_rtx (compute_mode));
3923 quotient = gen_reg_rtx (compute_mode);
3927 quotient = (GET_CODE (target) == REG
3928 ? target : gen_reg_rtx (compute_mode));
3929 remainder = gen_reg_rtx (compute_mode);
3932 if (expand_twoval_binop (sdivmod_optab, op0, op1, quotient,
3935 /* This could be computed with a branch-less sequence.
3936 Save that for later. */
3938 rtx label = gen_label_rtx ();
3939 do_cmp_and_jump (remainder, const0_rtx, EQ,
3940 compute_mode, label);
3941 tem = expand_binop (compute_mode, xor_optab, op0, op1,
3942 NULL_RTX, 0, OPTAB_WIDEN);
3943 do_cmp_and_jump (tem, const0_rtx, LT, compute_mode, label);
3944 expand_inc (quotient, const1_rtx);
3945 expand_dec (remainder, op1);
3947 return gen_lowpart (mode, rem_flag ? remainder : quotient);
3950 /* No luck with division elimination or divmod. Have to do it
3951 by conditionally adjusting op0 *and* the result. */
3953 rtx label1, label2, label3, label4, label5;
3957 quotient = gen_reg_rtx (compute_mode);
3958 adjusted_op0 = copy_to_mode_reg (compute_mode, op0);
3959 label1 = gen_label_rtx ();
3960 label2 = gen_label_rtx ();
3961 label3 = gen_label_rtx ();
3962 label4 = gen_label_rtx ();
3963 label5 = gen_label_rtx ();
3964 do_cmp_and_jump (op1, const0_rtx, LT, compute_mode, label2);
3965 do_cmp_and_jump (adjusted_op0, const0_rtx, GT,
3966 compute_mode, label1);
3967 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
3968 quotient, 0, OPTAB_LIB_WIDEN);
3969 if (tem != quotient)
3970 emit_move_insn (quotient, tem);
3971 emit_jump_insn (gen_jump (label5));
3973 emit_label (label1);
3974 expand_dec (adjusted_op0, const1_rtx);
3975 emit_jump_insn (gen_jump (label4));
3977 emit_label (label2);
3978 do_cmp_and_jump (adjusted_op0, const0_rtx, LT,
3979 compute_mode, label3);
3980 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
3981 quotient, 0, OPTAB_LIB_WIDEN);
3982 if (tem != quotient)
3983 emit_move_insn (quotient, tem);
3984 emit_jump_insn (gen_jump (label5));
3986 emit_label (label3);
3987 expand_inc (adjusted_op0, const1_rtx);
3988 emit_label (label4);
3989 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
3990 quotient, 0, OPTAB_LIB_WIDEN);
3991 if (tem != quotient)
3992 emit_move_insn (quotient, tem);
3993 expand_inc (quotient, const1_rtx);
3994 emit_label (label5);
3999 case EXACT_DIV_EXPR:
4000 if (op1_is_constant && HOST_BITS_PER_WIDE_INT >= size)
4002 HOST_WIDE_INT d = INTVAL (op1);
4003 unsigned HOST_WIDE_INT ml;
4007 pre_shift = floor_log2 (d & -d);
4008 ml = invert_mod2n (d >> pre_shift, size);
4009 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
4010 build_int_2 (pre_shift, 0), NULL_RTX, unsignedp);
4011 quotient = expand_mult (compute_mode, t1,
4012 gen_int_mode (ml, compute_mode),
4015 insn = get_last_insn ();
4016 set_unique_reg_note (insn,
4018 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
4024 case ROUND_DIV_EXPR:
4025 case ROUND_MOD_EXPR:
4030 label = gen_label_rtx ();
4031 quotient = gen_reg_rtx (compute_mode);
4032 remainder = gen_reg_rtx (compute_mode);
4033 if (expand_twoval_binop (udivmod_optab, op0, op1, quotient, remainder, 1) == 0)
4036 quotient = expand_binop (compute_mode, udiv_optab, op0, op1,
4037 quotient, 1, OPTAB_LIB_WIDEN);
4038 tem = expand_mult (compute_mode, quotient, op1, NULL_RTX, 1);
4039 remainder = expand_binop (compute_mode, sub_optab, op0, tem,
4040 remainder, 1, OPTAB_LIB_WIDEN);
4042 tem = plus_constant (op1, -1);
4043 tem = expand_shift (RSHIFT_EXPR, compute_mode, tem,
4044 build_int_2 (1, 0), NULL_RTX, 1);
4045 do_cmp_and_jump (remainder, tem, LEU, compute_mode, label);
4046 expand_inc (quotient, const1_rtx);
4047 expand_dec (remainder, op1);
4052 rtx abs_rem, abs_op1, tem, mask;
4054 label = gen_label_rtx ();
4055 quotient = gen_reg_rtx (compute_mode);
4056 remainder = gen_reg_rtx (compute_mode);
4057 if (expand_twoval_binop (sdivmod_optab, op0, op1, quotient, remainder, 0) == 0)
4060 quotient = expand_binop (compute_mode, sdiv_optab, op0, op1,
4061 quotient, 0, OPTAB_LIB_WIDEN);
4062 tem = expand_mult (compute_mode, quotient, op1, NULL_RTX, 0);
4063 remainder = expand_binop (compute_mode, sub_optab, op0, tem,
4064 remainder, 0, OPTAB_LIB_WIDEN);
4066 abs_rem = expand_abs (compute_mode, remainder, NULL_RTX, 1, 0);
4067 abs_op1 = expand_abs (compute_mode, op1, NULL_RTX, 1, 0);
4068 tem = expand_shift (LSHIFT_EXPR, compute_mode, abs_rem,
4069 build_int_2 (1, 0), NULL_RTX, 1);
4070 do_cmp_and_jump (tem, abs_op1, LTU, compute_mode, label);
4071 tem = expand_binop (compute_mode, xor_optab, op0, op1,
4072 NULL_RTX, 0, OPTAB_WIDEN);
4073 mask = expand_shift (RSHIFT_EXPR, compute_mode, tem,
4074 build_int_2 (size - 1, 0), NULL_RTX, 0);
4075 tem = expand_binop (compute_mode, xor_optab, mask, const1_rtx,
4076 NULL_RTX, 0, OPTAB_WIDEN);
4077 tem = expand_binop (compute_mode, sub_optab, tem, mask,
4078 NULL_RTX, 0, OPTAB_WIDEN);
4079 expand_inc (quotient, tem);
4080 tem = expand_binop (compute_mode, xor_optab, mask, op1,
4081 NULL_RTX, 0, OPTAB_WIDEN);
4082 tem = expand_binop (compute_mode, sub_optab, tem, mask,
4083 NULL_RTX, 0, OPTAB_WIDEN);
4084 expand_dec (remainder, tem);
4087 return gen_lowpart (mode, rem_flag ? remainder : quotient);
4095 if (target && GET_MODE (target) != compute_mode)
4100 /* Try to produce the remainder without producing the quotient.
4101 If we seem to have a divmod pattern that does not require widening,
4102 don't try widening here. We should really have a WIDEN argument
4103 to expand_twoval_binop, since what we'd really like to do here is
4104 1) try a mod insn in compute_mode
4105 2) try a divmod insn in compute_mode
4106 3) try a div insn in compute_mode and multiply-subtract to get
4108 4) try the same things with widening allowed. */
4110 = sign_expand_binop (compute_mode, umod_optab, smod_optab,
4113 ((optab2->handlers[compute_mode].insn_code
4114 != CODE_FOR_nothing)
4115 ? OPTAB_DIRECT : OPTAB_WIDEN));
4118 /* No luck there. Can we do remainder and divide at once
4119 without a library call? */
4120 remainder = gen_reg_rtx (compute_mode);
4121 if (! expand_twoval_binop ((unsignedp
4125 NULL_RTX, remainder, unsignedp))
4130 return gen_lowpart (mode, remainder);
4133 /* Produce the quotient. Try a quotient insn, but not a library call.
4134 If we have a divmod in this mode, use it in preference to widening
4135 the div (for this test we assume it will not fail). Note that optab2
4136 is set to the one of the two optabs that the call below will use. */
4138 = sign_expand_binop (compute_mode, udiv_optab, sdiv_optab,
4139 op0, op1, rem_flag ? NULL_RTX : target,
4141 ((optab2->handlers[compute_mode].insn_code
4142 != CODE_FOR_nothing)
4143 ? OPTAB_DIRECT : OPTAB_WIDEN));
4147 /* No luck there. Try a quotient-and-remainder insn,
4148 keeping the quotient alone. */
4149 quotient = gen_reg_rtx (compute_mode);
4150 if (! expand_twoval_binop (unsignedp ? udivmod_optab : sdivmod_optab,
4152 quotient, NULL_RTX, unsignedp))
4156 /* Still no luck. If we are not computing the remainder,
4157 use a library call for the quotient. */
4158 quotient = sign_expand_binop (compute_mode,
4159 udiv_optab, sdiv_optab,
4161 unsignedp, OPTAB_LIB_WIDEN);
4168 if (target && GET_MODE (target) != compute_mode)
4172 /* No divide instruction either. Use library for remainder. */
4173 remainder = sign_expand_binop (compute_mode, umod_optab, smod_optab,
4175 unsignedp, OPTAB_LIB_WIDEN);
4178 /* We divided. Now finish doing X - Y * (X / Y). */
4179 remainder = expand_mult (compute_mode, quotient, op1,
4180 NULL_RTX, unsignedp);
4181 remainder = expand_binop (compute_mode, sub_optab, op0,
4182 remainder, target, unsignedp,
4187 return gen_lowpart (mode, rem_flag ? remainder : quotient);
4190 /* Return a tree node with data type TYPE, describing the value of X.
4191 Usually this is an RTL_EXPR, if there is no obvious better choice.
4192 X may be an expression, however we only support those expressions
4193 generated by loop.c. */
4196 make_tree (tree type, rtx x)
4200 switch (GET_CODE (x))
4203 t = build_int_2 (INTVAL (x),
4204 (TYPE_UNSIGNED (type)
4205 && (GET_MODE_BITSIZE (TYPE_MODE (type))
4206 < HOST_BITS_PER_WIDE_INT))
4207 || INTVAL (x) >= 0 ? 0 : -1);
4208 TREE_TYPE (t) = type;
4212 if (GET_MODE (x) == VOIDmode)
4214 t = build_int_2 (CONST_DOUBLE_LOW (x), CONST_DOUBLE_HIGH (x));
4215 TREE_TYPE (t) = type;
4221 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
4222 t = build_real (type, d);
4233 units = CONST_VECTOR_NUNITS (x);
4235 /* Build a tree with vector elements. */
4236 for (i = units - 1; i >= 0; --i)
4238 elt = CONST_VECTOR_ELT (x, i);
4239 t = tree_cons (NULL_TREE, make_tree (type, elt), t);
4242 return build_vector (type, t);
4246 return fold (build (PLUS_EXPR, type, make_tree (type, XEXP (x, 0)),
4247 make_tree (type, XEXP (x, 1))));
4250 return fold (build (MINUS_EXPR, type, make_tree (type, XEXP (x, 0)),
4251 make_tree (type, XEXP (x, 1))));
4254 return fold (build1 (NEGATE_EXPR, type, make_tree (type, XEXP (x, 0))));
4257 return fold (build (MULT_EXPR, type, make_tree (type, XEXP (x, 0)),
4258 make_tree (type, XEXP (x, 1))));
4261 return fold (build (LSHIFT_EXPR, type, make_tree (type, XEXP (x, 0)),
4262 make_tree (type, XEXP (x, 1))));
4265 t = lang_hooks.types.unsigned_type (type);
4266 return fold (convert (type,
4267 build (RSHIFT_EXPR, t,
4268 make_tree (t, XEXP (x, 0)),
4269 make_tree (type, XEXP (x, 1)))));
4272 t = lang_hooks.types.signed_type (type);
4273 return fold (convert (type,
4274 build (RSHIFT_EXPR, t,
4275 make_tree (t, XEXP (x, 0)),
4276 make_tree (type, XEXP (x, 1)))));
4279 if (TREE_CODE (type) != REAL_TYPE)
4280 t = lang_hooks.types.signed_type (type);
4284 return fold (convert (type,
4285 build (TRUNC_DIV_EXPR, t,
4286 make_tree (t, XEXP (x, 0)),
4287 make_tree (t, XEXP (x, 1)))));
4289 t = lang_hooks.types.unsigned_type (type);
4290 return fold (convert (type,
4291 build (TRUNC_DIV_EXPR, t,
4292 make_tree (t, XEXP (x, 0)),
4293 make_tree (t, XEXP (x, 1)))));
4297 t = lang_hooks.types.type_for_mode (GET_MODE (XEXP (x, 0)),
4298 GET_CODE (x) == ZERO_EXTEND);
4299 return fold (convert (type, make_tree (t, XEXP (x, 0))));
4302 t = make_node (RTL_EXPR);
4303 TREE_TYPE (t) = type;
4305 /* If TYPE is a POINTER_TYPE, X might be Pmode with TYPE_MODE being
4306 ptr_mode. So convert. */
4307 if (POINTER_TYPE_P (type))
4308 x = convert_memory_address (TYPE_MODE (type), x);
4310 RTL_EXPR_RTL (t) = x;
4311 /* There are no insns to be output
4312 when this rtl_expr is used. */
4313 RTL_EXPR_SEQUENCE (t) = 0;
4318 /* Check whether the multiplication X * MULT + ADD overflows.
4319 X, MULT and ADD must be CONST_*.
4320 MODE is the machine mode for the computation.
4321 X and MULT must have mode MODE. ADD may have a different mode.
4322 So can X (defaults to same as MODE).
4323 UNSIGNEDP is nonzero to do unsigned multiplication. */
4326 const_mult_add_overflow_p (rtx x, rtx mult, rtx add, enum machine_mode mode, int unsignedp)
4328 tree type, mult_type, add_type, result;
4330 type = lang_hooks.types.type_for_mode (mode, unsignedp);
4332 /* In order to get a proper overflow indication from an unsigned
4333 type, we have to pretend that it's a sizetype. */
4337 mult_type = copy_node (type);
4338 TYPE_IS_SIZETYPE (mult_type) = 1;
4341 add_type = (GET_MODE (add) == VOIDmode ? mult_type
4342 : lang_hooks.types.type_for_mode (GET_MODE (add), unsignedp));
4344 result = fold (build (PLUS_EXPR, mult_type,
4345 fold (build (MULT_EXPR, mult_type,
4346 make_tree (mult_type, x),
4347 make_tree (mult_type, mult))),
4348 make_tree (add_type, add)));
4350 return TREE_CONSTANT_OVERFLOW (result);
4353 /* Return an rtx representing the value of X * MULT + ADD.
4354 TARGET is a suggestion for where to store the result (an rtx).
4355 MODE is the machine mode for the computation.
4356 X and MULT must have mode MODE. ADD may have a different mode.
4357 So can X (defaults to same as MODE).
4358 UNSIGNEDP is nonzero to do unsigned multiplication.
4359 This may emit insns. */
4362 expand_mult_add (rtx x, rtx target, rtx mult, rtx add, enum machine_mode mode,
4365 tree type = lang_hooks.types.type_for_mode (mode, unsignedp);
4366 tree add_type = (GET_MODE (add) == VOIDmode
4367 ? type: lang_hooks.types.type_for_mode (GET_MODE (add),
4369 tree result = fold (build (PLUS_EXPR, type,
4370 fold (build (MULT_EXPR, type,
4371 make_tree (type, x),
4372 make_tree (type, mult))),
4373 make_tree (add_type, add)));
4375 return expand_expr (result, target, VOIDmode, 0);
4378 /* Compute the logical-and of OP0 and OP1, storing it in TARGET
4379 and returning TARGET.
4381 If TARGET is 0, a pseudo-register or constant is returned. */
4384 expand_and (enum machine_mode mode, rtx op0, rtx op1, rtx target)
4388 if (GET_MODE (op0) == VOIDmode && GET_MODE (op1) == VOIDmode)
4389 tem = simplify_binary_operation (AND, mode, op0, op1);
4391 tem = expand_binop (mode, and_optab, op0, op1, target, 0, OPTAB_LIB_WIDEN);
4395 else if (tem != target)
4396 emit_move_insn (target, tem);
4400 /* Emit a store-flags instruction for comparison CODE on OP0 and OP1
4401 and storing in TARGET. Normally return TARGET.
4402 Return 0 if that cannot be done.
4404 MODE is the mode to use for OP0 and OP1 should they be CONST_INTs. If
4405 it is VOIDmode, they cannot both be CONST_INT.
4407 UNSIGNEDP is for the case where we have to widen the operands
4408 to perform the operation. It says to use zero-extension.
4410 NORMALIZEP is 1 if we should convert the result to be either zero
4411 or one. Normalize is -1 if we should convert the result to be
4412 either zero or -1. If NORMALIZEP is zero, the result will be left
4413 "raw" out of the scc insn. */
4416 emit_store_flag (rtx target, enum rtx_code code, rtx op0, rtx op1,
4417 enum machine_mode mode, int unsignedp, int normalizep)
4420 enum insn_code icode;
4421 enum machine_mode compare_mode;
4422 enum machine_mode target_mode = GET_MODE (target);
4424 rtx last = get_last_insn ();
4425 rtx pattern, comparison;
4427 /* ??? Ok to do this and then fail? */
4428 op0 = protect_from_queue (op0, 0);
4429 op1 = protect_from_queue (op1, 0);
4432 code = unsigned_condition (code);
4434 /* If one operand is constant, make it the second one. Only do this
4435 if the other operand is not constant as well. */
4437 if (swap_commutative_operands_p (op0, op1))
4442 code = swap_condition (code);
4445 if (mode == VOIDmode)
4446 mode = GET_MODE (op0);
4448 /* For some comparisons with 1 and -1, we can convert this to
4449 comparisons with zero. This will often produce more opportunities for
4450 store-flag insns. */
4455 if (op1 == const1_rtx)
4456 op1 = const0_rtx, code = LE;
4459 if (op1 == constm1_rtx)
4460 op1 = const0_rtx, code = LT;
4463 if (op1 == const1_rtx)
4464 op1 = const0_rtx, code = GT;
4467 if (op1 == constm1_rtx)
4468 op1 = const0_rtx, code = GE;
4471 if (op1 == const1_rtx)
4472 op1 = const0_rtx, code = NE;
4475 if (op1 == const1_rtx)
4476 op1 = const0_rtx, code = EQ;
4482 /* If we are comparing a double-word integer with zero, we can convert
4483 the comparison into one involving a single word. */
4484 if (GET_MODE_BITSIZE (mode) == BITS_PER_WORD * 2
4485 && GET_MODE_CLASS (mode) == MODE_INT
4486 && op1 == const0_rtx
4487 && (GET_CODE (op0) != MEM || ! MEM_VOLATILE_P (op0)))
4489 if (code == EQ || code == NE)
4491 rtx op00, op01, op0both;
4493 /* Do a logical OR of the two words and compare the result. */
4494 op00 = simplify_gen_subreg (word_mode, op0, mode, 0);
4495 op01 = simplify_gen_subreg (word_mode, op0, mode, UNITS_PER_WORD);
4496 op0both = expand_binop (word_mode, ior_optab, op00, op01,
4497 NULL_RTX, unsignedp, OPTAB_DIRECT);
4499 return emit_store_flag (target, code, op0both, op1, word_mode,
4500 unsignedp, normalizep);
4502 else if (code == LT || code == GE)
4506 /* If testing the sign bit, can just test on high word. */
4507 op0h = simplify_gen_subreg (word_mode, op0, mode,
4508 subreg_highpart_offset (word_mode, mode));
4509 return emit_store_flag (target, code, op0h, op1, word_mode,
4510 unsignedp, normalizep);
4514 /* From now on, we won't change CODE, so set ICODE now. */
4515 icode = setcc_gen_code[(int) code];
4517 /* If this is A < 0 or A >= 0, we can do this by taking the ones
4518 complement of A (for GE) and shifting the sign bit to the low bit. */
4519 if (op1 == const0_rtx && (code == LT || code == GE)
4520 && GET_MODE_CLASS (mode) == MODE_INT
4521 && (normalizep || STORE_FLAG_VALUE == 1
4522 || (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4523 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4524 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1)))))
4528 /* If the result is to be wider than OP0, it is best to convert it
4529 first. If it is to be narrower, it is *incorrect* to convert it
4531 if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (mode))
4533 op0 = protect_from_queue (op0, 0);
4534 op0 = convert_modes (target_mode, mode, op0, 0);
4538 if (target_mode != mode)
4542 op0 = expand_unop (mode, one_cmpl_optab, op0,
4543 ((STORE_FLAG_VALUE == 1 || normalizep)
4544 ? 0 : subtarget), 0);
4546 if (STORE_FLAG_VALUE == 1 || normalizep)
4547 /* If we are supposed to produce a 0/1 value, we want to do
4548 a logical shift from the sign bit to the low-order bit; for
4549 a -1/0 value, we do an arithmetic shift. */
4550 op0 = expand_shift (RSHIFT_EXPR, mode, op0,
4551 size_int (GET_MODE_BITSIZE (mode) - 1),
4552 subtarget, normalizep != -1);
4554 if (mode != target_mode)
4555 op0 = convert_modes (target_mode, mode, op0, 0);
4560 if (icode != CODE_FOR_nothing)
4562 insn_operand_predicate_fn pred;
4564 /* We think we may be able to do this with a scc insn. Emit the
4565 comparison and then the scc insn.
4567 compare_from_rtx may call emit_queue, which would be deleted below
4568 if the scc insn fails. So call it ourselves before setting LAST.
4569 Likewise for do_pending_stack_adjust. */
4572 do_pending_stack_adjust ();
4573 last = get_last_insn ();
4576 = compare_from_rtx (op0, op1, code, unsignedp, mode, NULL_RTX);
4577 if (CONSTANT_P (comparison))
4579 if (GET_CODE (comparison) == CONST_INT)
4581 if (comparison == const0_rtx)
4584 #ifdef FLOAT_STORE_FLAG_VALUE
4585 else if (GET_CODE (comparison) == CONST_DOUBLE)
4587 if (comparison == CONST0_RTX (GET_MODE (comparison)))
4593 if (normalizep == 1)
4595 if (normalizep == -1)
4597 return const_true_rtx;
4600 /* The code of COMPARISON may not match CODE if compare_from_rtx
4601 decided to swap its operands and reverse the original code.
4603 We know that compare_from_rtx returns either a CONST_INT or
4604 a new comparison code, so it is safe to just extract the
4605 code from COMPARISON. */
4606 code = GET_CODE (comparison);
4608 /* Get a reference to the target in the proper mode for this insn. */
4609 compare_mode = insn_data[(int) icode].operand[0].mode;
4611 pred = insn_data[(int) icode].operand[0].predicate;
4612 if (preserve_subexpressions_p ()
4613 || ! (*pred) (subtarget, compare_mode))
4614 subtarget = gen_reg_rtx (compare_mode);
4616 pattern = GEN_FCN (icode) (subtarget);
4619 emit_insn (pattern);
4621 /* If we are converting to a wider mode, first convert to
4622 TARGET_MODE, then normalize. This produces better combining
4623 opportunities on machines that have a SIGN_EXTRACT when we are
4624 testing a single bit. This mostly benefits the 68k.
4626 If STORE_FLAG_VALUE does not have the sign bit set when
4627 interpreted in COMPARE_MODE, we can do this conversion as
4628 unsigned, which is usually more efficient. */
4629 if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (compare_mode))
4631 convert_move (target, subtarget,
4632 (GET_MODE_BITSIZE (compare_mode)
4633 <= HOST_BITS_PER_WIDE_INT)
4634 && 0 == (STORE_FLAG_VALUE
4635 & ((HOST_WIDE_INT) 1
4636 << (GET_MODE_BITSIZE (compare_mode) -1))));
4638 compare_mode = target_mode;
4643 /* If we want to keep subexpressions around, don't reuse our
4646 if (preserve_subexpressions_p ())
4649 /* Now normalize to the proper value in COMPARE_MODE. Sometimes
4650 we don't have to do anything. */
4651 if (normalizep == 0 || normalizep == STORE_FLAG_VALUE)
4653 /* STORE_FLAG_VALUE might be the most negative number, so write
4654 the comparison this way to avoid a compiler-time warning. */
4655 else if (- normalizep == STORE_FLAG_VALUE)
4656 op0 = expand_unop (compare_mode, neg_optab, op0, subtarget, 0);
4658 /* We don't want to use STORE_FLAG_VALUE < 0 below since this
4659 makes it hard to use a value of just the sign bit due to
4660 ANSI integer constant typing rules. */
4661 else if (GET_MODE_BITSIZE (compare_mode) <= HOST_BITS_PER_WIDE_INT
4662 && (STORE_FLAG_VALUE
4663 & ((HOST_WIDE_INT) 1
4664 << (GET_MODE_BITSIZE (compare_mode) - 1))))
4665 op0 = expand_shift (RSHIFT_EXPR, compare_mode, op0,
4666 size_int (GET_MODE_BITSIZE (compare_mode) - 1),
4667 subtarget, normalizep == 1);
4668 else if (STORE_FLAG_VALUE & 1)
4670 op0 = expand_and (compare_mode, op0, const1_rtx, subtarget);
4671 if (normalizep == -1)
4672 op0 = expand_unop (compare_mode, neg_optab, op0, op0, 0);
4677 /* If we were converting to a smaller mode, do the
4679 if (target_mode != compare_mode)
4681 convert_move (target, op0, 0);
4689 delete_insns_since (last);
4691 /* If expensive optimizations, use different pseudo registers for each
4692 insn, instead of reusing the same pseudo. This leads to better CSE,
4693 but slows down the compiler, since there are more pseudos */
4694 subtarget = (!flag_expensive_optimizations
4695 && (target_mode == mode)) ? target : NULL_RTX;
4697 /* If we reached here, we can't do this with a scc insn. However, there
4698 are some comparisons that can be done directly. For example, if
4699 this is an equality comparison of integers, we can try to exclusive-or
4700 (or subtract) the two operands and use a recursive call to try the
4701 comparison with zero. Don't do any of these cases if branches are
4705 && GET_MODE_CLASS (mode) == MODE_INT && (code == EQ || code == NE)
4706 && op1 != const0_rtx)
4708 tem = expand_binop (mode, xor_optab, op0, op1, subtarget, 1,
4712 tem = expand_binop (mode, sub_optab, op0, op1, subtarget, 1,
4715 tem = emit_store_flag (target, code, tem, const0_rtx,
4716 mode, unsignedp, normalizep);
4718 delete_insns_since (last);
4722 /* Some other cases we can do are EQ, NE, LE, and GT comparisons with
4723 the constant zero. Reject all other comparisons at this point. Only
4724 do LE and GT if branches are expensive since they are expensive on
4725 2-operand machines. */
4727 if (BRANCH_COST == 0
4728 || GET_MODE_CLASS (mode) != MODE_INT || op1 != const0_rtx
4729 || (code != EQ && code != NE
4730 && (BRANCH_COST <= 1 || (code != LE && code != GT))))
4733 /* See what we need to return. We can only return a 1, -1, or the
4736 if (normalizep == 0)
4738 if (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4739 normalizep = STORE_FLAG_VALUE;
4741 else if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4742 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4743 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1)))
4749 /* Try to put the result of the comparison in the sign bit. Assume we can't
4750 do the necessary operation below. */
4754 /* To see if A <= 0, compute (A | (A - 1)). A <= 0 iff that result has
4755 the sign bit set. */
4759 /* This is destructive, so SUBTARGET can't be OP0. */
4760 if (rtx_equal_p (subtarget, op0))
4763 tem = expand_binop (mode, sub_optab, op0, const1_rtx, subtarget, 0,
4766 tem = expand_binop (mode, ior_optab, op0, tem, subtarget, 0,
4770 /* To see if A > 0, compute (((signed) A) << BITS) - A, where BITS is the
4771 number of bits in the mode of OP0, minus one. */
4775 if (rtx_equal_p (subtarget, op0))
4778 tem = expand_shift (RSHIFT_EXPR, mode, op0,
4779 size_int (GET_MODE_BITSIZE (mode) - 1),
4781 tem = expand_binop (mode, sub_optab, tem, op0, subtarget, 0,
4785 if (code == EQ || code == NE)
4787 /* For EQ or NE, one way to do the comparison is to apply an operation
4788 that converts the operand into a positive number if it is nonzero
4789 or zero if it was originally zero. Then, for EQ, we subtract 1 and
4790 for NE we negate. This puts the result in the sign bit. Then we
4791 normalize with a shift, if needed.
4793 Two operations that can do the above actions are ABS and FFS, so try
4794 them. If that doesn't work, and MODE is smaller than a full word,
4795 we can use zero-extension to the wider mode (an unsigned conversion)
4796 as the operation. */
4798 /* Note that ABS doesn't yield a positive number for INT_MIN, but
4799 that is compensated by the subsequent overflow when subtracting
4802 if (abs_optab->handlers[mode].insn_code != CODE_FOR_nothing)
4803 tem = expand_unop (mode, abs_optab, op0, subtarget, 1);
4804 else if (ffs_optab->handlers[mode].insn_code != CODE_FOR_nothing)
4805 tem = expand_unop (mode, ffs_optab, op0, subtarget, 1);
4806 else if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
4808 op0 = protect_from_queue (op0, 0);
4809 tem = convert_modes (word_mode, mode, op0, 1);
4816 tem = expand_binop (mode, sub_optab, tem, const1_rtx, subtarget,
4819 tem = expand_unop (mode, neg_optab, tem, subtarget, 0);
4822 /* If we couldn't do it that way, for NE we can "or" the two's complement
4823 of the value with itself. For EQ, we take the one's complement of
4824 that "or", which is an extra insn, so we only handle EQ if branches
4827 if (tem == 0 && (code == NE || BRANCH_COST > 1))
4829 if (rtx_equal_p (subtarget, op0))
4832 tem = expand_unop (mode, neg_optab, op0, subtarget, 0);
4833 tem = expand_binop (mode, ior_optab, tem, op0, subtarget, 0,
4836 if (tem && code == EQ)
4837 tem = expand_unop (mode, one_cmpl_optab, tem, subtarget, 0);
4841 if (tem && normalizep)
4842 tem = expand_shift (RSHIFT_EXPR, mode, tem,
4843 size_int (GET_MODE_BITSIZE (mode) - 1),
4844 subtarget, normalizep == 1);
4848 if (GET_MODE (tem) != target_mode)
4850 convert_move (target, tem, 0);
4853 else if (!subtarget)
4855 emit_move_insn (target, tem);
4860 delete_insns_since (last);
4865 /* Like emit_store_flag, but always succeeds. */
4868 emit_store_flag_force (rtx target, enum rtx_code code, rtx op0, rtx op1,
4869 enum machine_mode mode, int unsignedp, int normalizep)
4873 /* First see if emit_store_flag can do the job. */
4874 tem = emit_store_flag (target, code, op0, op1, mode, unsignedp, normalizep);
4878 if (normalizep == 0)
4881 /* If this failed, we have to do this with set/compare/jump/set code. */
4883 if (GET_CODE (target) != REG
4884 || reg_mentioned_p (target, op0) || reg_mentioned_p (target, op1))
4885 target = gen_reg_rtx (GET_MODE (target));
4887 emit_move_insn (target, const1_rtx);
4888 label = gen_label_rtx ();
4889 do_compare_rtx_and_jump (op0, op1, code, unsignedp, mode, NULL_RTX,
4892 emit_move_insn (target, const0_rtx);
4898 /* Perform possibly multi-word comparison and conditional jump to LABEL
4899 if ARG1 OP ARG2 true where ARG1 and ARG2 are of mode MODE
4901 The algorithm is based on the code in expr.c:do_jump.
4903 Note that this does not perform a general comparison. Only variants
4904 generated within expmed.c are correctly handled, others abort (but could
4905 be handled if needed). */
4908 do_cmp_and_jump (rtx arg1, rtx arg2, enum rtx_code op, enum machine_mode mode,
4911 /* If this mode is an integer too wide to compare properly,
4912 compare word by word. Rely on cse to optimize constant cases. */
4914 if (GET_MODE_CLASS (mode) == MODE_INT
4915 && ! can_compare_p (op, mode, ccp_jump))
4917 rtx label2 = gen_label_rtx ();
4922 do_jump_by_parts_greater_rtx (mode, 1, arg2, arg1, label2, label);
4926 do_jump_by_parts_greater_rtx (mode, 1, arg1, arg2, label, label2);
4930 do_jump_by_parts_greater_rtx (mode, 0, arg2, arg1, label2, label);
4934 do_jump_by_parts_greater_rtx (mode, 0, arg1, arg2, label2, label);
4938 do_jump_by_parts_greater_rtx (mode, 0, arg2, arg1, label, label2);
4941 /* do_jump_by_parts_equality_rtx compares with zero. Luckily
4942 that's the only equality operations we do */
4944 if (arg2 != const0_rtx || mode != GET_MODE(arg1))
4946 do_jump_by_parts_equality_rtx (arg1, label2, label);
4950 if (arg2 != const0_rtx || mode != GET_MODE(arg1))
4952 do_jump_by_parts_equality_rtx (arg1, label, label2);
4959 emit_label (label2);
4962 emit_cmp_and_jump_insns (arg1, arg2, op, NULL_RTX, mode, 0, label);