1 /* Medium-level subroutines: convert bit-field store and extract
2 and shifts, multiplies and divides to rtl instructions.
3 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
4 1999, 2000, 2001 Free Software Foundation, Inc.
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
31 #include "insn-config.h"
37 static void store_fixed_bit_field PARAMS ((rtx, unsigned HOST_WIDE_INT,
38 unsigned HOST_WIDE_INT,
39 unsigned HOST_WIDE_INT, rtx,
41 static void store_split_bit_field PARAMS ((rtx, unsigned HOST_WIDE_INT,
42 unsigned HOST_WIDE_INT, rtx,
44 static rtx extract_fixed_bit_field PARAMS ((enum machine_mode, rtx,
45 unsigned HOST_WIDE_INT,
46 unsigned HOST_WIDE_INT,
47 unsigned HOST_WIDE_INT,
48 rtx, int, unsigned int));
49 static rtx mask_rtx PARAMS ((enum machine_mode, int,
51 static rtx lshift_value PARAMS ((enum machine_mode, rtx,
53 static rtx extract_split_bit_field PARAMS ((rtx, unsigned HOST_WIDE_INT,
54 unsigned HOST_WIDE_INT, int,
56 static void do_cmp_and_jump PARAMS ((rtx, rtx, enum rtx_code,
57 enum machine_mode, rtx));
59 /* Non-zero means divides or modulus operations are relatively cheap for
60 powers of two, so don't use branches; emit the operation instead.
61 Usually, this will mean that the MD file will emit non-branch
64 static int sdiv_pow2_cheap, smod_pow2_cheap;
66 #ifndef SLOW_UNALIGNED_ACCESS
67 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) STRICT_ALIGNMENT
70 /* For compilers that support multiple targets with different word sizes,
71 MAX_BITS_PER_WORD contains the biggest value of BITS_PER_WORD. An example
72 is the H8/300(H) compiler. */
74 #ifndef MAX_BITS_PER_WORD
75 #define MAX_BITS_PER_WORD BITS_PER_WORD
78 /* Reduce conditional compilation elsewhere. */
80 #define CODE_FOR_insv CODE_FOR_nothing
81 #define gen_insv(a,b,c,d) NULL_RTX
84 #define CODE_FOR_extv CODE_FOR_nothing
85 #define gen_extv(a,b,c,d) NULL_RTX
88 #define CODE_FOR_extzv CODE_FOR_nothing
89 #define gen_extzv(a,b,c,d) NULL_RTX
92 /* Cost of various pieces of RTL. Note that some of these are indexed by
93 shift count and some by mode. */
94 static int add_cost, negate_cost, zero_cost;
95 static int shift_cost[MAX_BITS_PER_WORD];
96 static int shiftadd_cost[MAX_BITS_PER_WORD];
97 static int shiftsub_cost[MAX_BITS_PER_WORD];
98 static int mul_cost[NUM_MACHINE_MODES];
99 static int div_cost[NUM_MACHINE_MODES];
100 static int mul_widen_cost[NUM_MACHINE_MODES];
101 static int mul_highpart_cost[NUM_MACHINE_MODES];
106 /* This is "some random pseudo register" for purposes of calling recog
107 to see what insns exist. */
108 rtx reg = gen_rtx_REG (word_mode, 10000);
109 rtx shift_insn, shiftadd_insn, shiftsub_insn;
112 enum machine_mode mode, wider_mode;
116 reg = gen_rtx_REG (word_mode, 10000);
118 zero_cost = rtx_cost (const0_rtx, 0);
119 add_cost = rtx_cost (gen_rtx_PLUS (word_mode, reg, reg), SET);
121 shift_insn = emit_insn (gen_rtx_SET (VOIDmode, reg,
122 gen_rtx_ASHIFT (word_mode, reg,
126 = emit_insn (gen_rtx_SET (VOIDmode, reg,
127 gen_rtx_PLUS (word_mode,
128 gen_rtx_MULT (word_mode,
133 = emit_insn (gen_rtx_SET (VOIDmode, reg,
134 gen_rtx_MINUS (word_mode,
135 gen_rtx_MULT (word_mode,
142 shiftadd_cost[0] = shiftsub_cost[0] = add_cost;
144 for (m = 1; m < MAX_BITS_PER_WORD; m++)
146 shift_cost[m] = shiftadd_cost[m] = shiftsub_cost[m] = 32000;
148 XEXP (SET_SRC (PATTERN (shift_insn)), 1) = GEN_INT (m);
149 if (recog (PATTERN (shift_insn), shift_insn, &dummy) >= 0)
150 shift_cost[m] = rtx_cost (SET_SRC (PATTERN (shift_insn)), SET);
152 XEXP (XEXP (SET_SRC (PATTERN (shiftadd_insn)), 0), 1)
153 = GEN_INT ((HOST_WIDE_INT) 1 << m);
154 if (recog (PATTERN (shiftadd_insn), shiftadd_insn, &dummy) >= 0)
155 shiftadd_cost[m] = rtx_cost (SET_SRC (PATTERN (shiftadd_insn)), SET);
157 XEXP (XEXP (SET_SRC (PATTERN (shiftsub_insn)), 0), 1)
158 = GEN_INT ((HOST_WIDE_INT) 1 << m);
159 if (recog (PATTERN (shiftsub_insn), shiftsub_insn, &dummy) >= 0)
160 shiftsub_cost[m] = rtx_cost (SET_SRC (PATTERN (shiftsub_insn)), SET);
163 negate_cost = rtx_cost (gen_rtx_NEG (word_mode, reg), SET);
166 = (rtx_cost (gen_rtx_DIV (word_mode, reg, GEN_INT (32)), SET)
169 = (rtx_cost (gen_rtx_MOD (word_mode, reg, GEN_INT (32)), SET)
172 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
174 mode = GET_MODE_WIDER_MODE (mode))
176 reg = gen_rtx_REG (mode, 10000);
177 div_cost[(int) mode] = rtx_cost (gen_rtx_UDIV (mode, reg, reg), SET);
178 mul_cost[(int) mode] = rtx_cost (gen_rtx_MULT (mode, reg, reg), SET);
179 wider_mode = GET_MODE_WIDER_MODE (mode);
180 if (wider_mode != VOIDmode)
182 mul_widen_cost[(int) wider_mode]
183 = rtx_cost (gen_rtx_MULT (wider_mode,
184 gen_rtx_ZERO_EXTEND (wider_mode, reg),
185 gen_rtx_ZERO_EXTEND (wider_mode, reg)),
187 mul_highpart_cost[(int) mode]
188 = rtx_cost (gen_rtx_TRUNCATE
190 gen_rtx_LSHIFTRT (wider_mode,
191 gen_rtx_MULT (wider_mode,
196 GEN_INT (GET_MODE_BITSIZE (mode)))),
204 /* Return an rtx representing minus the value of X.
205 MODE is the intended mode of the result,
206 useful if X is a CONST_INT. */
210 enum machine_mode mode;
213 rtx result = simplify_unary_operation (NEG, mode, x, mode);
216 result = expand_unop (mode, neg_optab, x, NULL_RTX, 0);
221 /* Report on the availability of insv/extv/extzv and the desired mode
222 of each of their operands. Returns MAX_MACHINE_MODE if HAVE_foo
223 is false; else the mode of the specified operand. If OPNO is -1,
224 all the caller cares about is whether the insn is available. */
226 mode_for_extraction (pattern, opno)
227 enum extraction_pattern pattern;
230 const struct insn_data *data;
238 data = &insn_data[CODE_FOR_insv];
242 return MAX_MACHINE_MODE;
248 data = &insn_data[CODE_FOR_extv];
252 return MAX_MACHINE_MODE;
258 data = &insn_data[CODE_FOR_extzv];
262 return MAX_MACHINE_MODE;
268 /* Everyone who uses this function used to follow it with
269 if (result == VOIDmode) result = word_mode; */
270 if (data->operand[opno].mode == VOIDmode)
272 return data->operand[opno].mode;
276 /* Generate code to store value from rtx VALUE
277 into a bit-field within structure STR_RTX
278 containing BITSIZE bits starting at bit BITNUM.
279 FIELDMODE is the machine-mode of the FIELD_DECL node for this field.
280 ALIGN is the alignment that STR_RTX is known to have.
281 TOTAL_SIZE is the size of the structure in bytes, or -1 if varying. */
283 /* ??? Note that there are two different ideas here for how
284 to determine the size to count bits within, for a register.
285 One is BITS_PER_WORD, and the other is the size of operand 3
288 If operand 3 of the insv pattern is VOIDmode, then we will use BITS_PER_WORD
289 else, we use the mode of operand 3. */
292 store_bit_field (str_rtx, bitsize, bitnum, fieldmode, value, align, total_size)
294 unsigned HOST_WIDE_INT bitsize;
295 unsigned HOST_WIDE_INT bitnum;
296 enum machine_mode fieldmode;
299 HOST_WIDE_INT total_size;
302 = (GET_CODE (str_rtx) == MEM) ? BITS_PER_UNIT : BITS_PER_WORD;
303 unsigned HOST_WIDE_INT offset = bitnum / unit;
304 unsigned HOST_WIDE_INT bitpos = bitnum % unit;
305 register rtx op0 = str_rtx;
307 unsigned HOST_WIDE_INT insv_bitsize;
308 enum machine_mode op_mode;
310 op_mode = mode_for_extraction (EP_insv, 3);
311 if (op_mode != MAX_MACHINE_MODE)
312 insv_bitsize = GET_MODE_BITSIZE (op_mode);
314 /* It is wrong to have align==0, since every object is aligned at
315 least at a bit boundary. This usually means a bug elsewhere. */
319 /* Discount the part of the structure before the desired byte.
320 We need to know how many bytes are safe to reference after it. */
322 total_size -= (bitpos / BIGGEST_ALIGNMENT
323 * (BIGGEST_ALIGNMENT / BITS_PER_UNIT));
325 while (GET_CODE (op0) == SUBREG)
327 /* The following line once was done only if WORDS_BIG_ENDIAN,
328 but I think that is a mistake. WORDS_BIG_ENDIAN is
329 meaningful at a much higher level; when structures are copied
330 between memory and regs, the higher-numbered regs
331 always get higher addresses. */
332 offset += (SUBREG_BYTE (op0) / UNITS_PER_WORD);
333 /* We used to adjust BITPOS here, but now we do the whole adjustment
334 right after the loop. */
335 op0 = SUBREG_REG (op0);
338 /* If OP0 is a register, BITPOS must count within a word.
339 But as we have it, it counts within whatever size OP0 now has.
340 On a bigendian machine, these are not the same, so convert. */
342 && GET_CODE (op0) != MEM
343 && unit > GET_MODE_BITSIZE (GET_MODE (op0)))
344 bitpos += unit - GET_MODE_BITSIZE (GET_MODE (op0));
346 value = protect_from_queue (value, 0);
349 value = force_not_mem (value);
351 /* If the target is a register, overwriting the entire object, or storing
352 a full-word or multi-word field can be done with just a SUBREG.
354 If the target is memory, storing any naturally aligned field can be
355 done with a simple store. For targets that support fast unaligned
356 memory, any naturally sized, unit aligned field can be done directly. */
358 if (bitsize == GET_MODE_BITSIZE (fieldmode)
359 && (GET_CODE (op0) != MEM
360 ? (GET_MODE_SIZE (fieldmode) >= UNITS_PER_WORD
361 || GET_MODE_SIZE (GET_MODE (op0)) == GET_MODE_SIZE (fieldmode))
362 : (! SLOW_UNALIGNED_ACCESS (fieldmode, align)
363 || (offset * BITS_PER_UNIT % bitsize == 0
364 && align % GET_MODE_BITSIZE (fieldmode) == 0)))
365 && (BYTES_BIG_ENDIAN ? bitpos + bitsize == unit : bitpos == 0))
367 if (GET_MODE (op0) != fieldmode)
369 if (GET_CODE (op0) == SUBREG)
371 if (GET_MODE (SUBREG_REG (op0)) == fieldmode
372 || GET_MODE_CLASS (fieldmode) == MODE_INT
373 || GET_MODE_CLASS (fieldmode) == MODE_PARTIAL_INT)
374 op0 = SUBREG_REG (op0);
376 /* Else we've got some float mode source being extracted into
377 a different float mode destination -- this combination of
378 subregs results in Severe Tire Damage. */
381 if (GET_CODE (op0) == REG)
382 op0 = gen_rtx_SUBREG (fieldmode, op0,
383 (bitnum % BITS_PER_WORD) / BITS_PER_UNIT
384 + (offset * UNITS_PER_WORD));
386 op0 = adjust_address (op0, fieldmode, offset);
388 emit_move_insn (op0, value);
392 /* Make sure we are playing with integral modes. Pun with subregs
393 if we aren't. This must come after the entire register case above,
394 since that case is valid for any mode. The following cases are only
395 valid for integral modes. */
397 enum machine_mode imode = int_mode_for_mode (GET_MODE (op0));
398 if (imode != GET_MODE (op0))
400 if (GET_CODE (op0) == MEM)
401 op0 = adjust_address (op0, imode, 0);
402 else if (imode != BLKmode)
403 op0 = gen_lowpart (imode, op0);
409 /* Storing an lsb-aligned field in a register
410 can be done with a movestrict instruction. */
412 if (GET_CODE (op0) != MEM
413 && (BYTES_BIG_ENDIAN ? bitpos + bitsize == unit : bitpos == 0)
414 && bitsize == GET_MODE_BITSIZE (fieldmode)
415 && (movstrict_optab->handlers[(int) fieldmode].insn_code
416 != CODE_FOR_nothing))
418 int icode = movstrict_optab->handlers[(int) fieldmode].insn_code;
420 /* Get appropriate low part of the value being stored. */
421 if (GET_CODE (value) == CONST_INT || GET_CODE (value) == REG)
422 value = gen_lowpart (fieldmode, value);
423 else if (!(GET_CODE (value) == SYMBOL_REF
424 || GET_CODE (value) == LABEL_REF
425 || GET_CODE (value) == CONST))
426 value = convert_to_mode (fieldmode, value, 0);
428 if (! (*insn_data[icode].operand[1].predicate) (value, fieldmode))
429 value = copy_to_mode_reg (fieldmode, value);
431 if (GET_CODE (op0) == SUBREG)
433 if (GET_MODE (SUBREG_REG (op0)) == fieldmode
434 || GET_MODE_CLASS (fieldmode) == MODE_INT
435 || GET_MODE_CLASS (fieldmode) == MODE_PARTIAL_INT)
436 op0 = SUBREG_REG (op0);
438 /* Else we've got some float mode source being extracted into
439 a different float mode destination -- this combination of
440 subregs results in Severe Tire Damage. */
444 emit_insn (GEN_FCN (icode)
445 (gen_rtx_SUBREG (fieldmode, op0,
446 (bitnum % BITS_PER_WORD) / BITS_PER_UNIT
447 + (offset * UNITS_PER_WORD)),
453 /* Handle fields bigger than a word. */
455 if (bitsize > BITS_PER_WORD)
457 /* Here we transfer the words of the field
458 in the order least significant first.
459 This is because the most significant word is the one which may
461 However, only do that if the value is not BLKmode. */
463 unsigned int backwards = WORDS_BIG_ENDIAN && fieldmode != BLKmode;
464 unsigned int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD;
467 /* This is the mode we must force value to, so that there will be enough
468 subwords to extract. Note that fieldmode will often (always?) be
469 VOIDmode, because that is what store_field uses to indicate that this
470 is a bit field, but passing VOIDmode to operand_subword_force will
471 result in an abort. */
472 fieldmode = smallest_mode_for_size (nwords * BITS_PER_WORD, MODE_INT);
474 for (i = 0; i < nwords; i++)
476 /* If I is 0, use the low-order word in both field and target;
477 if I is 1, use the next to lowest word; and so on. */
478 unsigned int wordnum = (backwards ? nwords - i - 1 : i);
479 unsigned int bit_offset = (backwards
480 ? MAX ((int) bitsize - ((int) i + 1)
483 : (int) i * BITS_PER_WORD);
485 store_bit_field (op0, MIN (BITS_PER_WORD,
486 bitsize - i * BITS_PER_WORD),
487 bitnum + bit_offset, word_mode,
488 operand_subword_force (value, wordnum,
489 (GET_MODE (value) == VOIDmode
491 : GET_MODE (value))),
497 /* From here on we can assume that the field to be stored in is
498 a full-word (whatever type that is), since it is shorter than a word. */
500 /* OFFSET is the number of words or bytes (UNIT says which)
501 from STR_RTX to the first word or byte containing part of the field. */
503 if (GET_CODE (op0) != MEM)
506 || GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD)
508 if (GET_CODE (op0) != REG)
510 /* Since this is a destination (lvalue), we can't copy it to a
511 pseudo. We can trivially remove a SUBREG that does not
512 change the size of the operand. Such a SUBREG may have been
513 added above. Otherwise, abort. */
514 if (GET_CODE (op0) == SUBREG
515 && (GET_MODE_SIZE (GET_MODE (op0))
516 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0)))))
517 op0 = SUBREG_REG (op0);
521 op0 = gen_rtx_SUBREG (mode_for_size (BITS_PER_WORD, MODE_INT, 0),
522 op0, (offset * UNITS_PER_WORD));
528 op0 = protect_from_queue (op0, 1);
531 /* If VALUE is a floating-point mode, access it as an integer of the
532 corresponding size. This can occur on a machine with 64 bit registers
533 that uses SFmode for float. This can also occur for unaligned float
535 if (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT)
537 if (GET_CODE (value) != REG)
538 value = copy_to_reg (value);
539 value = gen_rtx_SUBREG (word_mode, value, 0);
542 /* Now OFFSET is nonzero only if OP0 is memory
543 and is therefore always measured in bytes. */
545 if (op_mode != MAX_MACHINE_MODE
546 && GET_MODE (value) != BLKmode
547 && !(bitsize == 1 && GET_CODE (value) == CONST_INT)
548 /* Ensure insv's size is wide enough for this field. */
549 && (insv_bitsize >= bitsize)
550 && ! ((GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
551 && (bitsize + bitpos > insv_bitsize)))
553 int xbitpos = bitpos;
556 rtx last = get_last_insn ();
558 enum machine_mode maxmode = mode_for_extraction (EP_insv, 3);
559 int save_volatile_ok = volatile_ok;
563 /* If this machine's insv can only insert into a register, copy OP0
564 into a register and save it back later. */
565 /* This used to check flag_force_mem, but that was a serious
566 de-optimization now that flag_force_mem is enabled by -O2. */
567 if (GET_CODE (op0) == MEM
568 && ! ((*insn_data[(int) CODE_FOR_insv].operand[0].predicate)
572 enum machine_mode bestmode;
574 /* Get the mode to use for inserting into this field. If OP0 is
575 BLKmode, get the smallest mode consistent with the alignment. If
576 OP0 is a non-BLKmode object that is no wider than MAXMODE, use its
577 mode. Otherwise, use the smallest mode containing the field. */
579 if (GET_MODE (op0) == BLKmode
580 || GET_MODE_SIZE (GET_MODE (op0)) > GET_MODE_SIZE (maxmode))
582 = get_best_mode (bitsize, bitnum, align, maxmode,
583 MEM_VOLATILE_P (op0));
585 bestmode = GET_MODE (op0);
587 if (bestmode == VOIDmode
588 || (SLOW_UNALIGNED_ACCESS (bestmode, align)
589 && GET_MODE_BITSIZE (bestmode) > align))
592 /* Adjust address to point to the containing unit of that mode. */
593 unit = GET_MODE_BITSIZE (bestmode);
594 /* Compute offset as multiple of this unit, counting in bytes. */
595 offset = (bitnum / unit) * GET_MODE_SIZE (bestmode);
596 bitpos = bitnum % unit;
597 op0 = adjust_address (op0, bestmode, offset);
599 /* Fetch that unit, store the bitfield in it, then store
601 tempreg = copy_to_reg (op0);
602 store_bit_field (tempreg, bitsize, bitpos, fieldmode, value,
604 emit_move_insn (op0, tempreg);
607 volatile_ok = save_volatile_ok;
609 /* Add OFFSET into OP0's address. */
610 if (GET_CODE (xop0) == MEM)
611 xop0 = adjust_address (xop0, byte_mode, offset);
613 /* If xop0 is a register, we need it in MAXMODE
614 to make it acceptable to the format of insv. */
615 if (GET_CODE (xop0) == SUBREG)
616 /* We can't just change the mode, because this might clobber op0,
617 and we will need the original value of op0 if insv fails. */
618 xop0 = gen_rtx_SUBREG (maxmode, SUBREG_REG (xop0), SUBREG_BYTE (xop0));
619 if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode)
620 xop0 = gen_rtx_SUBREG (maxmode, xop0, 0);
622 /* On big-endian machines, we count bits from the most significant.
623 If the bit field insn does not, we must invert. */
625 if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
626 xbitpos = unit - bitsize - xbitpos;
628 /* We have been counting XBITPOS within UNIT.
629 Count instead within the size of the register. */
630 if (BITS_BIG_ENDIAN && GET_CODE (xop0) != MEM)
631 xbitpos += GET_MODE_BITSIZE (maxmode) - unit;
633 unit = GET_MODE_BITSIZE (maxmode);
635 /* Convert VALUE to maxmode (which insv insn wants) in VALUE1. */
637 if (GET_MODE (value) != maxmode)
639 if (GET_MODE_BITSIZE (GET_MODE (value)) >= bitsize)
641 /* Optimization: Don't bother really extending VALUE
642 if it has all the bits we will actually use. However,
643 if we must narrow it, be sure we do it correctly. */
645 if (GET_MODE_SIZE (GET_MODE (value)) < GET_MODE_SIZE (maxmode))
647 /* Avoid making subreg of a subreg, or of a mem. */
648 if (GET_CODE (value1) != REG)
649 value1 = copy_to_reg (value1);
650 value1 = gen_rtx_SUBREG (maxmode, value1, 0);
653 value1 = gen_lowpart (maxmode, value1);
655 else if (GET_CODE (value) == CONST_INT)
656 value1 = GEN_INT (trunc_int_for_mode (INTVAL (value), maxmode));
657 else if (!CONSTANT_P (value))
658 /* Parse phase is supposed to make VALUE's data type
659 match that of the component reference, which is a type
660 at least as wide as the field; so VALUE should have
661 a mode that corresponds to that type. */
665 /* If this machine's insv insists on a register,
666 get VALUE1 into a register. */
667 if (! ((*insn_data[(int) CODE_FOR_insv].operand[3].predicate)
669 value1 = force_reg (maxmode, value1);
671 pat = gen_insv (xop0, GEN_INT (bitsize), GEN_INT (xbitpos), value1);
676 delete_insns_since (last);
677 store_fixed_bit_field (op0, offset, bitsize, bitpos, value, align);
682 /* Insv is not available; store using shifts and boolean ops. */
683 store_fixed_bit_field (op0, offset, bitsize, bitpos, value, align);
687 /* Use shifts and boolean operations to store VALUE
688 into a bit field of width BITSIZE
689 in a memory location specified by OP0 except offset by OFFSET bytes.
690 (OFFSET must be 0 if OP0 is a register.)
691 The field starts at position BITPOS within the byte.
692 (If OP0 is a register, it may be a full word or a narrower mode,
693 but BITPOS still counts within a full word,
694 which is significant on bigendian machines.)
695 STRUCT_ALIGN is the alignment the structure is known to have.
697 Note that protect_from_queue has already been done on OP0 and VALUE. */
700 store_fixed_bit_field (op0, offset, bitsize, bitpos, value, struct_align)
702 unsigned HOST_WIDE_INT offset, bitsize, bitpos;
704 unsigned int struct_align;
706 register enum machine_mode mode;
707 unsigned int total_bits = BITS_PER_WORD;
712 if (! SLOW_UNALIGNED_ACCESS (word_mode, struct_align))
713 struct_align = BIGGEST_ALIGNMENT;
715 /* There is a case not handled here:
716 a structure with a known alignment of just a halfword
717 and a field split across two aligned halfwords within the structure.
718 Or likewise a structure with a known alignment of just a byte
719 and a field split across two bytes.
720 Such cases are not supposed to be able to occur. */
722 if (GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
726 /* Special treatment for a bit field split across two registers. */
727 if (bitsize + bitpos > BITS_PER_WORD)
729 store_split_bit_field (op0, bitsize, bitpos,
730 value, BITS_PER_WORD);
736 /* Get the proper mode to use for this field. We want a mode that
737 includes the entire field. If such a mode would be larger than
738 a word, we won't be doing the extraction the normal way.
739 We don't want a mode bigger than the destination. */
741 mode = GET_MODE (op0);
742 if (GET_MODE_BITSIZE (mode) == 0
743 || GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (word_mode))
745 mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT,
747 GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0));
749 if (mode == VOIDmode)
751 /* The only way this should occur is if the field spans word
753 store_split_bit_field (op0,
754 bitsize, bitpos + offset * BITS_PER_UNIT,
755 value, struct_align);
759 total_bits = GET_MODE_BITSIZE (mode);
761 /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to
762 be in the range 0 to total_bits-1, and put any excess bytes in
764 if (bitpos >= total_bits)
766 offset += (bitpos / total_bits) * (total_bits / BITS_PER_UNIT);
767 bitpos -= ((bitpos / total_bits) * (total_bits / BITS_PER_UNIT)
771 /* Get ref to an aligned byte, halfword, or word containing the field.
772 Adjust BITPOS to be position within a word,
773 and OFFSET to be the offset of that word.
774 Then alter OP0 to refer to that word. */
775 bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT;
776 offset -= (offset % (total_bits / BITS_PER_UNIT));
777 op0 = adjust_address (op0, mode, offset);
780 mode = GET_MODE (op0);
782 /* Now MODE is either some integral mode for a MEM as OP0,
783 or is a full-word for a REG as OP0. TOTAL_BITS corresponds.
784 The bit field is contained entirely within OP0.
785 BITPOS is the starting bit number within OP0.
786 (OP0's mode may actually be narrower than MODE.) */
788 if (BYTES_BIG_ENDIAN)
789 /* BITPOS is the distance between our msb
790 and that of the containing datum.
791 Convert it to the distance from the lsb. */
792 bitpos = total_bits - bitsize - bitpos;
794 /* Now BITPOS is always the distance between our lsb
797 /* Shift VALUE left by BITPOS bits. If VALUE is not constant,
798 we must first convert its mode to MODE. */
800 if (GET_CODE (value) == CONST_INT)
802 register HOST_WIDE_INT v = INTVAL (value);
804 if (bitsize < HOST_BITS_PER_WIDE_INT)
805 v &= ((HOST_WIDE_INT) 1 << bitsize) - 1;
809 else if ((bitsize < HOST_BITS_PER_WIDE_INT
810 && v == ((HOST_WIDE_INT) 1 << bitsize) - 1)
811 || (bitsize == HOST_BITS_PER_WIDE_INT && v == -1))
814 value = lshift_value (mode, value, bitpos, bitsize);
818 int must_and = (GET_MODE_BITSIZE (GET_MODE (value)) != bitsize
819 && bitpos + bitsize != GET_MODE_BITSIZE (mode));
821 if (GET_MODE (value) != mode)
823 if ((GET_CODE (value) == REG || GET_CODE (value) == SUBREG)
824 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (value)))
825 value = gen_lowpart (mode, value);
827 value = convert_to_mode (mode, value, 1);
831 value = expand_binop (mode, and_optab, value,
832 mask_rtx (mode, 0, bitsize, 0),
833 NULL_RTX, 1, OPTAB_LIB_WIDEN);
835 value = expand_shift (LSHIFT_EXPR, mode, value,
836 build_int_2 (bitpos, 0), NULL_RTX, 1);
839 /* Now clear the chosen bits in OP0,
840 except that if VALUE is -1 we need not bother. */
842 subtarget = (GET_CODE (op0) == REG || ! flag_force_mem) ? op0 : 0;
846 temp = expand_binop (mode, and_optab, op0,
847 mask_rtx (mode, bitpos, bitsize, 1),
848 subtarget, 1, OPTAB_LIB_WIDEN);
854 /* Now logical-or VALUE into OP0, unless it is zero. */
857 temp = expand_binop (mode, ior_optab, temp, value,
858 subtarget, 1, OPTAB_LIB_WIDEN);
860 emit_move_insn (op0, temp);
863 /* Store a bit field that is split across multiple accessible memory objects.
865 OP0 is the REG, SUBREG or MEM rtx for the first of the objects.
866 BITSIZE is the field width; BITPOS the position of its first bit
868 VALUE is the value to store.
869 ALIGN is the known alignment of OP0.
870 This is also the size of the memory objects to be used.
872 This does not yet handle fields wider than BITS_PER_WORD. */
875 store_split_bit_field (op0, bitsize, bitpos, value, align)
877 unsigned HOST_WIDE_INT bitsize, bitpos;
882 unsigned int bitsdone = 0;
884 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
886 if (GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
887 unit = BITS_PER_WORD;
889 unit = MIN (align, BITS_PER_WORD);
891 /* If VALUE is a constant other than a CONST_INT, get it into a register in
892 WORD_MODE. If we can do this using gen_lowpart_common, do so. Note
893 that VALUE might be a floating-point constant. */
894 if (CONSTANT_P (value) && GET_CODE (value) != CONST_INT)
896 rtx word = gen_lowpart_common (word_mode, value);
898 if (word && (value != word))
901 value = gen_lowpart_common (word_mode,
902 force_reg (GET_MODE (value) != VOIDmode
904 : word_mode, value));
906 else if (GET_CODE (value) == ADDRESSOF)
907 value = copy_to_reg (value);
909 while (bitsdone < bitsize)
911 unsigned HOST_WIDE_INT thissize;
913 unsigned HOST_WIDE_INT thispos;
914 unsigned HOST_WIDE_INT offset;
916 offset = (bitpos + bitsdone) / unit;
917 thispos = (bitpos + bitsdone) % unit;
919 /* THISSIZE must not overrun a word boundary. Otherwise,
920 store_fixed_bit_field will call us again, and we will mutually
922 thissize = MIN (bitsize - bitsdone, BITS_PER_WORD);
923 thissize = MIN (thissize, unit - thispos);
925 if (BYTES_BIG_ENDIAN)
929 /* We must do an endian conversion exactly the same way as it is
930 done in extract_bit_field, so that the two calls to
931 extract_fixed_bit_field will have comparable arguments. */
932 if (GET_CODE (value) != MEM || GET_MODE (value) == BLKmode)
933 total_bits = BITS_PER_WORD;
935 total_bits = GET_MODE_BITSIZE (GET_MODE (value));
937 /* Fetch successively less significant portions. */
938 if (GET_CODE (value) == CONST_INT)
939 part = GEN_INT (((unsigned HOST_WIDE_INT) (INTVAL (value))
940 >> (bitsize - bitsdone - thissize))
941 & (((HOST_WIDE_INT) 1 << thissize) - 1));
943 /* The args are chosen so that the last part includes the
944 lsb. Give extract_bit_field the value it needs (with
945 endianness compensation) to fetch the piece we want.
947 ??? We have no idea what the alignment of VALUE is, so
948 we have to use a guess. */
950 = extract_fixed_bit_field
951 (word_mode, value, 0, thissize,
952 total_bits - bitsize + bitsdone, NULL_RTX, 1,
953 GET_MODE (value) == VOIDmode
955 : (GET_MODE (value) == BLKmode
956 ? 1 : GET_MODE_ALIGNMENT (GET_MODE (value))));
960 /* Fetch successively more significant portions. */
961 if (GET_CODE (value) == CONST_INT)
962 part = GEN_INT (((unsigned HOST_WIDE_INT) (INTVAL (value))
964 & (((HOST_WIDE_INT) 1 << thissize) - 1));
967 = extract_fixed_bit_field
968 (word_mode, value, 0, thissize, bitsdone, NULL_RTX, 1,
969 GET_MODE (value) == VOIDmode
971 : (GET_MODE (value) == BLKmode
972 ? 1 : GET_MODE_ALIGNMENT (GET_MODE (value))));
975 /* If OP0 is a register, then handle OFFSET here.
977 When handling multiword bitfields, extract_bit_field may pass
978 down a word_mode SUBREG of a larger REG for a bitfield that actually
979 crosses a word boundary. Thus, for a SUBREG, we must find
980 the current word starting from the base register. */
981 if (GET_CODE (op0) == SUBREG)
983 int word_offset = (SUBREG_BYTE (op0) / UNITS_PER_WORD) + offset;
984 word = operand_subword_force (SUBREG_REG (op0), word_offset,
985 GET_MODE (SUBREG_REG (op0)));
988 else if (GET_CODE (op0) == REG)
990 word = operand_subword_force (op0, offset, GET_MODE (op0));
996 /* OFFSET is in UNITs, and UNIT is in bits.
997 store_fixed_bit_field wants offset in bytes. */
998 store_fixed_bit_field (word, offset * unit / BITS_PER_UNIT,
999 thissize, thispos, part, align);
1000 bitsdone += thissize;
1004 /* Generate code to extract a byte-field from STR_RTX
1005 containing BITSIZE bits, starting at BITNUM,
1006 and put it in TARGET if possible (if TARGET is nonzero).
1007 Regardless of TARGET, we return the rtx for where the value is placed.
1010 STR_RTX is the structure containing the byte (a REG or MEM).
1011 UNSIGNEDP is nonzero if this is an unsigned bit field.
1012 MODE is the natural mode of the field value once extracted.
1013 TMODE is the mode the caller would like the value to have;
1014 but the value may be returned with type MODE instead.
1016 ALIGN is the alignment that STR_RTX is known to have.
1017 TOTAL_SIZE is the size in bytes of the containing structure,
1020 If a TARGET is specified and we can store in it at no extra cost,
1021 we do so, and return TARGET.
1022 Otherwise, we return a REG of mode TMODE or MODE, with TMODE preferred
1023 if they are equally easy. */
1026 extract_bit_field (str_rtx, bitsize, bitnum, unsignedp,
1027 target, mode, tmode, align, total_size)
1029 unsigned HOST_WIDE_INT bitsize;
1030 unsigned HOST_WIDE_INT bitnum;
1033 enum machine_mode mode, tmode;
1035 HOST_WIDE_INT total_size;
1038 = (GET_CODE (str_rtx) == MEM) ? BITS_PER_UNIT : BITS_PER_WORD;
1039 unsigned HOST_WIDE_INT offset = bitnum / unit;
1040 unsigned HOST_WIDE_INT bitpos = bitnum % unit;
1041 register rtx op0 = str_rtx;
1042 rtx spec_target = target;
1043 rtx spec_target_subreg = 0;
1044 enum machine_mode int_mode;
1045 unsigned HOST_WIDE_INT extv_bitsize;
1046 enum machine_mode extv_mode;
1047 unsigned HOST_WIDE_INT extzv_bitsize;
1048 enum machine_mode extzv_mode;
1050 extv_mode = mode_for_extraction (EP_extv, 0);
1051 if (extv_mode != MAX_MACHINE_MODE)
1052 extv_bitsize = GET_MODE_BITSIZE (extv_mode);
1054 extzv_mode = mode_for_extraction (EP_extzv, 0);
1055 if (extzv_mode != MAX_MACHINE_MODE)
1056 extzv_bitsize = GET_MODE_BITSIZE (extzv_mode);
1058 /* Discount the part of the structure before the desired byte.
1059 We need to know how many bytes are safe to reference after it. */
1060 if (total_size >= 0)
1061 total_size -= (bitpos / BIGGEST_ALIGNMENT
1062 * (BIGGEST_ALIGNMENT / BITS_PER_UNIT));
1064 if (tmode == VOIDmode)
1066 while (GET_CODE (op0) == SUBREG)
1068 int outer_size = GET_MODE_BITSIZE (GET_MODE (op0));
1069 int inner_size = GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)));
1071 offset += SUBREG_BYTE (op0) / UNITS_PER_WORD;
1073 inner_size = MIN (inner_size, BITS_PER_WORD);
1075 if (BYTES_BIG_ENDIAN && (outer_size < inner_size))
1077 bitpos += inner_size - outer_size;
1080 offset += (bitpos / unit);
1085 op0 = SUBREG_REG (op0);
1088 if (GET_CODE (op0) == REG
1089 && mode == GET_MODE (op0)
1091 && bitsize == GET_MODE_BITSIZE (GET_MODE (op0)))
1093 /* We're trying to extract a full register from itself. */
1097 /* Make sure we are playing with integral modes. Pun with subregs
1100 enum machine_mode imode = int_mode_for_mode (GET_MODE (op0));
1101 if (imode != GET_MODE (op0))
1103 if (GET_CODE (op0) == MEM)
1104 op0 = adjust_address (op0, imode, 0);
1105 else if (imode != BLKmode)
1106 op0 = gen_lowpart (imode, op0);
1112 /* ??? We currently assume TARGET is at least as big as BITSIZE.
1113 If that's wrong, the solution is to test for it and set TARGET to 0
1116 /* If OP0 is a register, BITPOS must count within a word.
1117 But as we have it, it counts within whatever size OP0 now has.
1118 On a bigendian machine, these are not the same, so convert. */
1119 if (BYTES_BIG_ENDIAN
1120 && GET_CODE (op0) != MEM
1121 && unit > GET_MODE_BITSIZE (GET_MODE (op0)))
1122 bitpos += unit - GET_MODE_BITSIZE (GET_MODE (op0));
1124 /* Extracting a full-word or multi-word value
1125 from a structure in a register or aligned memory.
1126 This can be done with just SUBREG.
1127 So too extracting a subword value in
1128 the least significant part of the register. */
1130 if (((GET_CODE (op0) != MEM
1131 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
1132 GET_MODE_BITSIZE (GET_MODE (op0))))
1133 || (GET_CODE (op0) == MEM
1134 && (! SLOW_UNALIGNED_ACCESS (mode, align)
1135 || (offset * BITS_PER_UNIT % bitsize == 0
1136 && align % bitsize == 0))))
1137 && ((bitsize >= BITS_PER_WORD && bitsize == GET_MODE_BITSIZE (mode)
1138 && bitpos % BITS_PER_WORD == 0)
1139 || (mode_for_size (bitsize, GET_MODE_CLASS (tmode), 0) != BLKmode
1140 /* ??? The big endian test here is wrong. This is correct
1141 if the value is in a register, and if mode_for_size is not
1142 the same mode as op0. This causes us to get unnecessarily
1143 inefficient code from the Thumb port when -mbig-endian. */
1144 && (BYTES_BIG_ENDIAN
1145 ? bitpos + bitsize == BITS_PER_WORD
1148 enum machine_mode mode1
1149 = (VECTOR_MODE_P (tmode) ? mode
1150 : mode_for_size (bitsize, GET_MODE_CLASS (tmode), 0));
1152 if (mode1 != GET_MODE (op0))
1154 if (GET_CODE (op0) == SUBREG)
1156 if (GET_MODE (SUBREG_REG (op0)) == mode1
1157 || GET_MODE_CLASS (mode1) == MODE_INT
1158 || GET_MODE_CLASS (mode1) == MODE_PARTIAL_INT)
1159 op0 = SUBREG_REG (op0);
1161 /* Else we've got some float mode source being extracted into
1162 a different float mode destination -- this combination of
1163 subregs results in Severe Tire Damage. */
1166 if (GET_CODE (op0) == REG)
1167 op0 = gen_rtx_SUBREG (mode1, op0,
1168 (bitnum % BITS_PER_WORD) / BITS_PER_UNIT
1169 + (offset * UNITS_PER_WORD));
1171 op0 = adjust_address (op0, mode1, offset);
1174 return convert_to_mode (tmode, op0, unsignedp);
1178 /* Handle fields bigger than a word. */
1180 if (bitsize > BITS_PER_WORD)
1182 /* Here we transfer the words of the field
1183 in the order least significant first.
1184 This is because the most significant word is the one which may
1185 be less than full. */
1187 unsigned int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD;
1190 if (target == 0 || GET_CODE (target) != REG)
1191 target = gen_reg_rtx (mode);
1193 /* Indicate for flow that the entire target reg is being set. */
1194 emit_insn (gen_rtx_CLOBBER (VOIDmode, target));
1196 for (i = 0; i < nwords; i++)
1198 /* If I is 0, use the low-order word in both field and target;
1199 if I is 1, use the next to lowest word; and so on. */
1200 /* Word number in TARGET to use. */
1201 unsigned int wordnum
1203 ? GET_MODE_SIZE (GET_MODE (target)) / UNITS_PER_WORD - i - 1
1205 /* Offset from start of field in OP0. */
1206 unsigned int bit_offset = (WORDS_BIG_ENDIAN
1207 ? MAX (0, ((int) bitsize - ((int) i + 1)
1208 * (int) BITS_PER_WORD))
1209 : (int) i * BITS_PER_WORD);
1210 rtx target_part = operand_subword (target, wordnum, 1, VOIDmode);
1212 = extract_bit_field (op0, MIN (BITS_PER_WORD,
1213 bitsize - i * BITS_PER_WORD),
1214 bitnum + bit_offset, 1, target_part, mode,
1215 word_mode, align, total_size);
1217 if (target_part == 0)
1220 if (result_part != target_part)
1221 emit_move_insn (target_part, result_part);
1226 /* Unless we've filled TARGET, the upper regs in a multi-reg value
1227 need to be zero'd out. */
1228 if (GET_MODE_SIZE (GET_MODE (target)) > nwords * UNITS_PER_WORD)
1230 unsigned int i, total_words;
1232 total_words = GET_MODE_SIZE (GET_MODE (target)) / UNITS_PER_WORD;
1233 for (i = nwords; i < total_words; i++)
1235 int wordnum = WORDS_BIG_ENDIAN ? total_words - i - 1 : i;
1236 rtx target_part = operand_subword (target, wordnum, 1, VOIDmode);
1237 emit_move_insn (target_part, const0_rtx);
1243 /* Signed bit field: sign-extend with two arithmetic shifts. */
1244 target = expand_shift (LSHIFT_EXPR, mode, target,
1245 build_int_2 (GET_MODE_BITSIZE (mode) - bitsize, 0),
1247 return expand_shift (RSHIFT_EXPR, mode, target,
1248 build_int_2 (GET_MODE_BITSIZE (mode) - bitsize, 0),
1252 /* From here on we know the desired field is smaller than a word. */
1254 /* Check if there is a correspondingly-sized integer field, so we can
1255 safely extract it as one size of integer, if necessary; then
1256 truncate or extend to the size that is wanted; then use SUBREGs or
1257 convert_to_mode to get one of the modes we really wanted. */
1259 int_mode = int_mode_for_mode (tmode);
1260 if (int_mode == BLKmode)
1261 int_mode = int_mode_for_mode (mode);
1262 if (int_mode == BLKmode)
1263 abort(); /* Should probably push op0 out to memory and then
1266 /* OFFSET is the number of words or bytes (UNIT says which)
1267 from STR_RTX to the first word or byte containing part of the field. */
1269 if (GET_CODE (op0) != MEM)
1272 || GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD)
1274 if (GET_CODE (op0) != REG)
1275 op0 = copy_to_reg (op0);
1276 op0 = gen_rtx_SUBREG (mode_for_size (BITS_PER_WORD, MODE_INT, 0),
1277 op0, (offset * UNITS_PER_WORD));
1283 op0 = protect_from_queue (str_rtx, 1);
1286 /* Now OFFSET is nonzero only for memory operands. */
1290 if (extzv_mode != MAX_MACHINE_MODE
1291 && (extzv_bitsize >= bitsize)
1292 && ! ((GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
1293 && (bitsize + bitpos > extzv_bitsize)))
1295 unsigned HOST_WIDE_INT xbitpos = bitpos, xoffset = offset;
1296 rtx bitsize_rtx, bitpos_rtx;
1297 rtx last = get_last_insn ();
1299 rtx xtarget = target;
1300 rtx xspec_target = spec_target;
1301 rtx xspec_target_subreg = spec_target_subreg;
1303 enum machine_mode maxmode = mode_for_extraction (EP_extzv, 0);
1305 if (GET_CODE (xop0) == MEM)
1307 int save_volatile_ok = volatile_ok;
1310 /* Is the memory operand acceptable? */
1311 if (! ((*insn_data[(int) CODE_FOR_extzv].operand[1].predicate)
1312 (xop0, GET_MODE (xop0))))
1314 /* No, load into a reg and extract from there. */
1315 enum machine_mode bestmode;
1317 /* Get the mode to use for inserting into this field. If
1318 OP0 is BLKmode, get the smallest mode consistent with the
1319 alignment. If OP0 is a non-BLKmode object that is no
1320 wider than MAXMODE, use its mode. Otherwise, use the
1321 smallest mode containing the field. */
1323 if (GET_MODE (xop0) == BLKmode
1324 || (GET_MODE_SIZE (GET_MODE (op0))
1325 > GET_MODE_SIZE (maxmode)))
1326 bestmode = get_best_mode (bitsize, bitnum, align, maxmode,
1327 MEM_VOLATILE_P (xop0));
1329 bestmode = GET_MODE (xop0);
1331 if (bestmode == VOIDmode
1332 || (SLOW_UNALIGNED_ACCESS (bestmode, align)
1333 && GET_MODE_BITSIZE (bestmode) > align))
1336 /* Compute offset as multiple of this unit,
1337 counting in bytes. */
1338 unit = GET_MODE_BITSIZE (bestmode);
1339 xoffset = (bitnum / unit) * GET_MODE_SIZE (bestmode);
1340 xbitpos = bitnum % unit;
1341 xop0 = adjust_address (xop0, bestmode, xoffset);
1343 /* Fetch it to a register in that size. */
1344 xop0 = force_reg (bestmode, xop0);
1346 /* XBITPOS counts within UNIT, which is what is expected. */
1349 /* Get ref to first byte containing part of the field. */
1350 xop0 = adjust_address (xop0, byte_mode, xoffset);
1352 volatile_ok = save_volatile_ok;
1355 /* If op0 is a register, we need it in MAXMODE (which is usually
1356 SImode). to make it acceptable to the format of extzv. */
1357 if (GET_CODE (xop0) == SUBREG && GET_MODE (xop0) != maxmode)
1359 if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode)
1360 xop0 = gen_rtx_SUBREG (maxmode, xop0, 0);
1362 /* On big-endian machines, we count bits from the most significant.
1363 If the bit field insn does not, we must invert. */
1364 if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
1365 xbitpos = unit - bitsize - xbitpos;
1367 /* Now convert from counting within UNIT to counting in MAXMODE. */
1368 if (BITS_BIG_ENDIAN && GET_CODE (xop0) != MEM)
1369 xbitpos += GET_MODE_BITSIZE (maxmode) - unit;
1371 unit = GET_MODE_BITSIZE (maxmode);
1374 || (flag_force_mem && GET_CODE (xtarget) == MEM))
1375 xtarget = xspec_target = gen_reg_rtx (tmode);
1377 if (GET_MODE (xtarget) != maxmode)
1379 if (GET_CODE (xtarget) == REG)
1381 int wider = (GET_MODE_SIZE (maxmode)
1382 > GET_MODE_SIZE (GET_MODE (xtarget)));
1383 xtarget = gen_lowpart (maxmode, xtarget);
1385 xspec_target_subreg = xtarget;
1388 xtarget = gen_reg_rtx (maxmode);
1391 /* If this machine's extzv insists on a register target,
1392 make sure we have one. */
1393 if (! ((*insn_data[(int) CODE_FOR_extzv].operand[0].predicate)
1394 (xtarget, maxmode)))
1395 xtarget = gen_reg_rtx (maxmode);
1397 bitsize_rtx = GEN_INT (bitsize);
1398 bitpos_rtx = GEN_INT (xbitpos);
1400 pat = gen_extzv (protect_from_queue (xtarget, 1),
1401 xop0, bitsize_rtx, bitpos_rtx);
1406 spec_target = xspec_target;
1407 spec_target_subreg = xspec_target_subreg;
1411 delete_insns_since (last);
1412 target = extract_fixed_bit_field (int_mode, op0, offset, bitsize,
1413 bitpos, target, 1, align);
1418 target = extract_fixed_bit_field (int_mode, op0, offset, bitsize,
1419 bitpos, target, 1, align);
1423 if (extv_mode != MAX_MACHINE_MODE
1424 && (extv_bitsize >= bitsize)
1425 && ! ((GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
1426 && (bitsize + bitpos > extv_bitsize)))
1428 int xbitpos = bitpos, xoffset = offset;
1429 rtx bitsize_rtx, bitpos_rtx;
1430 rtx last = get_last_insn ();
1431 rtx xop0 = op0, xtarget = target;
1432 rtx xspec_target = spec_target;
1433 rtx xspec_target_subreg = spec_target_subreg;
1435 enum machine_mode maxmode = mode_for_extraction (EP_extv, 0);
1437 if (GET_CODE (xop0) == MEM)
1439 /* Is the memory operand acceptable? */
1440 if (! ((*insn_data[(int) CODE_FOR_extv].operand[1].predicate)
1441 (xop0, GET_MODE (xop0))))
1443 /* No, load into a reg and extract from there. */
1444 enum machine_mode bestmode;
1446 /* Get the mode to use for inserting into this field. If
1447 OP0 is BLKmode, get the smallest mode consistent with the
1448 alignment. If OP0 is a non-BLKmode object that is no
1449 wider than MAXMODE, use its mode. Otherwise, use the
1450 smallest mode containing the field. */
1452 if (GET_MODE (xop0) == BLKmode
1453 || (GET_MODE_SIZE (GET_MODE (op0))
1454 > GET_MODE_SIZE (maxmode)))
1455 bestmode = get_best_mode (bitsize, bitnum, align, maxmode,
1456 MEM_VOLATILE_P (xop0));
1458 bestmode = GET_MODE (xop0);
1460 if (bestmode == VOIDmode
1461 || (SLOW_UNALIGNED_ACCESS (bestmode, align)
1462 && GET_MODE_BITSIZE (bestmode) > align))
1465 /* Compute offset as multiple of this unit,
1466 counting in bytes. */
1467 unit = GET_MODE_BITSIZE (bestmode);
1468 xoffset = (bitnum / unit) * GET_MODE_SIZE (bestmode);
1469 xbitpos = bitnum % unit;
1470 xop0 = adjust_address (xop0, bestmode, xoffset);
1472 /* Fetch it to a register in that size. */
1473 xop0 = force_reg (bestmode, xop0);
1475 /* XBITPOS counts within UNIT, which is what is expected. */
1478 /* Get ref to first byte containing part of the field. */
1479 xop0 = adjust_address (xop0, byte_mode, xoffset);
1482 /* If op0 is a register, we need it in MAXMODE (which is usually
1483 SImode) to make it acceptable to the format of extv. */
1484 if (GET_CODE (xop0) == SUBREG && GET_MODE (xop0) != maxmode)
1486 if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode)
1487 xop0 = gen_rtx_SUBREG (maxmode, xop0, 0);
1489 /* On big-endian machines, we count bits from the most significant.
1490 If the bit field insn does not, we must invert. */
1491 if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
1492 xbitpos = unit - bitsize - xbitpos;
1494 /* XBITPOS counts within a size of UNIT.
1495 Adjust to count within a size of MAXMODE. */
1496 if (BITS_BIG_ENDIAN && GET_CODE (xop0) != MEM)
1497 xbitpos += (GET_MODE_BITSIZE (maxmode) - unit);
1499 unit = GET_MODE_BITSIZE (maxmode);
1502 || (flag_force_mem && GET_CODE (xtarget) == MEM))
1503 xtarget = xspec_target = gen_reg_rtx (tmode);
1505 if (GET_MODE (xtarget) != maxmode)
1507 if (GET_CODE (xtarget) == REG)
1509 int wider = (GET_MODE_SIZE (maxmode)
1510 > GET_MODE_SIZE (GET_MODE (xtarget)));
1511 xtarget = gen_lowpart (maxmode, xtarget);
1513 xspec_target_subreg = xtarget;
1516 xtarget = gen_reg_rtx (maxmode);
1519 /* If this machine's extv insists on a register target,
1520 make sure we have one. */
1521 if (! ((*insn_data[(int) CODE_FOR_extv].operand[0].predicate)
1522 (xtarget, maxmode)))
1523 xtarget = gen_reg_rtx (maxmode);
1525 bitsize_rtx = GEN_INT (bitsize);
1526 bitpos_rtx = GEN_INT (xbitpos);
1528 pat = gen_extv (protect_from_queue (xtarget, 1),
1529 xop0, bitsize_rtx, bitpos_rtx);
1534 spec_target = xspec_target;
1535 spec_target_subreg = xspec_target_subreg;
1539 delete_insns_since (last);
1540 target = extract_fixed_bit_field (int_mode, op0, offset, bitsize,
1541 bitpos, target, 0, align);
1546 target = extract_fixed_bit_field (int_mode, op0, offset, bitsize,
1547 bitpos, target, 0, align);
1549 if (target == spec_target)
1551 if (target == spec_target_subreg)
1553 if (GET_MODE (target) != tmode && GET_MODE (target) != mode)
1555 /* If the target mode is floating-point, first convert to the
1556 integer mode of that size and then access it as a floating-point
1557 value via a SUBREG. */
1558 if (GET_MODE_CLASS (tmode) == MODE_FLOAT)
1560 target = convert_to_mode (mode_for_size (GET_MODE_BITSIZE (tmode),
1563 if (GET_CODE (target) != REG)
1564 target = copy_to_reg (target);
1565 return gen_rtx_SUBREG (tmode, target, 0);
1568 return convert_to_mode (tmode, target, unsignedp);
1573 /* Extract a bit field using shifts and boolean operations
1574 Returns an rtx to represent the value.
1575 OP0 addresses a register (word) or memory (byte).
1576 BITPOS says which bit within the word or byte the bit field starts in.
1577 OFFSET says how many bytes farther the bit field starts;
1578 it is 0 if OP0 is a register.
1579 BITSIZE says how many bits long the bit field is.
1580 (If OP0 is a register, it may be narrower than a full word,
1581 but BITPOS still counts within a full word,
1582 which is significant on bigendian machines.)
1584 UNSIGNEDP is nonzero for an unsigned bit field (don't sign-extend value).
1585 If TARGET is nonzero, attempts to store the value there
1586 and return TARGET, but this is not guaranteed.
1587 If TARGET is not used, create a pseudo-reg of mode TMODE for the value.
1589 ALIGN is the alignment that STR_RTX is known to have. */
1592 extract_fixed_bit_field (tmode, op0, offset, bitsize, bitpos,
1593 target, unsignedp, align)
1594 enum machine_mode tmode;
1595 register rtx op0, target;
1596 unsigned HOST_WIDE_INT offset, bitsize, bitpos;
1600 unsigned int total_bits = BITS_PER_WORD;
1601 enum machine_mode mode;
1603 if (GET_CODE (op0) == SUBREG || GET_CODE (op0) == REG)
1605 /* Special treatment for a bit field split across two registers. */
1606 if (bitsize + bitpos > BITS_PER_WORD)
1607 return extract_split_bit_field (op0, bitsize, bitpos,
1612 /* Get the proper mode to use for this field. We want a mode that
1613 includes the entire field. If such a mode would be larger than
1614 a word, we won't be doing the extraction the normal way. */
1616 mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT, align,
1618 GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0));
1620 if (mode == VOIDmode)
1621 /* The only way this should occur is if the field spans word
1623 return extract_split_bit_field (op0, bitsize,
1624 bitpos + offset * BITS_PER_UNIT,
1627 total_bits = GET_MODE_BITSIZE (mode);
1629 /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to
1630 be in the range 0 to total_bits-1, and put any excess bytes in
1632 if (bitpos >= total_bits)
1634 offset += (bitpos / total_bits) * (total_bits / BITS_PER_UNIT);
1635 bitpos -= ((bitpos / total_bits) * (total_bits / BITS_PER_UNIT)
1639 /* Get ref to an aligned byte, halfword, or word containing the field.
1640 Adjust BITPOS to be position within a word,
1641 and OFFSET to be the offset of that word.
1642 Then alter OP0 to refer to that word. */
1643 bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT;
1644 offset -= (offset % (total_bits / BITS_PER_UNIT));
1645 op0 = adjust_address (op0, mode, offset);
1648 mode = GET_MODE (op0);
1650 if (BYTES_BIG_ENDIAN)
1652 /* BITPOS is the distance between our msb and that of OP0.
1653 Convert it to the distance from the lsb. */
1655 bitpos = total_bits - bitsize - bitpos;
1658 /* Now BITPOS is always the distance between the field's lsb and that of OP0.
1659 We have reduced the big-endian case to the little-endian case. */
1665 /* If the field does not already start at the lsb,
1666 shift it so it does. */
1667 tree amount = build_int_2 (bitpos, 0);
1668 /* Maybe propagate the target for the shift. */
1669 /* But not if we will return it--could confuse integrate.c. */
1670 rtx subtarget = (target != 0 && GET_CODE (target) == REG
1671 && !REG_FUNCTION_VALUE_P (target)
1673 if (tmode != mode) subtarget = 0;
1674 op0 = expand_shift (RSHIFT_EXPR, mode, op0, amount, subtarget, 1);
1676 /* Convert the value to the desired mode. */
1678 op0 = convert_to_mode (tmode, op0, 1);
1680 /* Unless the msb of the field used to be the msb when we shifted,
1681 mask out the upper bits. */
1683 if (GET_MODE_BITSIZE (mode) != bitpos + bitsize
1685 #ifdef SLOW_ZERO_EXTEND
1686 /* Always generate an `and' if
1687 we just zero-extended op0 and SLOW_ZERO_EXTEND, since it
1688 will combine fruitfully with the zero-extend. */
1693 return expand_binop (GET_MODE (op0), and_optab, op0,
1694 mask_rtx (GET_MODE (op0), 0, bitsize, 0),
1695 target, 1, OPTAB_LIB_WIDEN);
1699 /* To extract a signed bit-field, first shift its msb to the msb of the word,
1700 then arithmetic-shift its lsb to the lsb of the word. */
1701 op0 = force_reg (mode, op0);
1705 /* Find the narrowest integer mode that contains the field. */
1707 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode;
1708 mode = GET_MODE_WIDER_MODE (mode))
1709 if (GET_MODE_BITSIZE (mode) >= bitsize + bitpos)
1711 op0 = convert_to_mode (mode, op0, 0);
1715 if (GET_MODE_BITSIZE (mode) != (bitsize + bitpos))
1717 tree amount = build_int_2 (GET_MODE_BITSIZE (mode) - (bitsize + bitpos), 0);
1718 /* Maybe propagate the target for the shift. */
1719 /* But not if we will return the result--could confuse integrate.c. */
1720 rtx subtarget = (target != 0 && GET_CODE (target) == REG
1721 && ! REG_FUNCTION_VALUE_P (target)
1723 op0 = expand_shift (LSHIFT_EXPR, mode, op0, amount, subtarget, 1);
1726 return expand_shift (RSHIFT_EXPR, mode, op0,
1727 build_int_2 (GET_MODE_BITSIZE (mode) - bitsize, 0),
1731 /* Return a constant integer (CONST_INT or CONST_DOUBLE) mask value
1732 of mode MODE with BITSIZE ones followed by BITPOS zeros, or the
1733 complement of that if COMPLEMENT. The mask is truncated if
1734 necessary to the width of mode MODE. The mask is zero-extended if
1735 BITSIZE+BITPOS is too small for MODE. */
1738 mask_rtx (mode, bitpos, bitsize, complement)
1739 enum machine_mode mode;
1740 int bitpos, bitsize, complement;
1742 HOST_WIDE_INT masklow, maskhigh;
1744 if (bitpos < HOST_BITS_PER_WIDE_INT)
1745 masklow = (HOST_WIDE_INT) -1 << bitpos;
1749 if (bitpos + bitsize < HOST_BITS_PER_WIDE_INT)
1750 masklow &= ((unsigned HOST_WIDE_INT) -1
1751 >> (HOST_BITS_PER_WIDE_INT - bitpos - bitsize));
1753 if (bitpos <= HOST_BITS_PER_WIDE_INT)
1756 maskhigh = (HOST_WIDE_INT) -1 << (bitpos - HOST_BITS_PER_WIDE_INT);
1758 if (bitpos + bitsize > HOST_BITS_PER_WIDE_INT)
1759 maskhigh &= ((unsigned HOST_WIDE_INT) -1
1760 >> (2 * HOST_BITS_PER_WIDE_INT - bitpos - bitsize));
1766 maskhigh = ~maskhigh;
1770 return immed_double_const (masklow, maskhigh, mode);
1773 /* Return a constant integer (CONST_INT or CONST_DOUBLE) rtx with the value
1774 VALUE truncated to BITSIZE bits and then shifted left BITPOS bits. */
1777 lshift_value (mode, value, bitpos, bitsize)
1778 enum machine_mode mode;
1780 int bitpos, bitsize;
1782 unsigned HOST_WIDE_INT v = INTVAL (value);
1783 HOST_WIDE_INT low, high;
1785 if (bitsize < HOST_BITS_PER_WIDE_INT)
1786 v &= ~((HOST_WIDE_INT) -1 << bitsize);
1788 if (bitpos < HOST_BITS_PER_WIDE_INT)
1791 high = (bitpos > 0 ? (v >> (HOST_BITS_PER_WIDE_INT - bitpos)) : 0);
1796 high = v << (bitpos - HOST_BITS_PER_WIDE_INT);
1799 return immed_double_const (low, high, mode);
1802 /* Extract a bit field that is split across two words
1803 and return an RTX for the result.
1805 OP0 is the REG, SUBREG or MEM rtx for the first of the two words.
1806 BITSIZE is the field width; BITPOS, position of its first bit, in the word.
1807 UNSIGNEDP is 1 if should zero-extend the contents; else sign-extend.
1809 ALIGN is the known alignment of OP0. This is also the size of the
1810 memory objects to be used. */
1813 extract_split_bit_field (op0, bitsize, bitpos, unsignedp, align)
1815 unsigned HOST_WIDE_INT bitsize, bitpos;
1820 unsigned int bitsdone = 0;
1821 rtx result = NULL_RTX;
1824 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
1826 if (GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
1827 unit = BITS_PER_WORD;
1829 unit = MIN (align, BITS_PER_WORD);
1831 while (bitsdone < bitsize)
1833 unsigned HOST_WIDE_INT thissize;
1835 unsigned HOST_WIDE_INT thispos;
1836 unsigned HOST_WIDE_INT offset;
1838 offset = (bitpos + bitsdone) / unit;
1839 thispos = (bitpos + bitsdone) % unit;
1841 /* THISSIZE must not overrun a word boundary. Otherwise,
1842 extract_fixed_bit_field will call us again, and we will mutually
1844 thissize = MIN (bitsize - bitsdone, BITS_PER_WORD);
1845 thissize = MIN (thissize, unit - thispos);
1847 /* If OP0 is a register, then handle OFFSET here.
1849 When handling multiword bitfields, extract_bit_field may pass
1850 down a word_mode SUBREG of a larger REG for a bitfield that actually
1851 crosses a word boundary. Thus, for a SUBREG, we must find
1852 the current word starting from the base register. */
1853 if (GET_CODE (op0) == SUBREG)
1855 int word_offset = (SUBREG_BYTE (op0) / UNITS_PER_WORD) + offset;
1856 word = operand_subword_force (SUBREG_REG (op0), word_offset,
1857 GET_MODE (SUBREG_REG (op0)));
1860 else if (GET_CODE (op0) == REG)
1862 word = operand_subword_force (op0, offset, GET_MODE (op0));
1868 /* Extract the parts in bit-counting order,
1869 whose meaning is determined by BYTES_PER_UNIT.
1870 OFFSET is in UNITs, and UNIT is in bits.
1871 extract_fixed_bit_field wants offset in bytes. */
1872 part = extract_fixed_bit_field (word_mode, word,
1873 offset * unit / BITS_PER_UNIT,
1874 thissize, thispos, 0, 1, align);
1875 bitsdone += thissize;
1877 /* Shift this part into place for the result. */
1878 if (BYTES_BIG_ENDIAN)
1880 if (bitsize != bitsdone)
1881 part = expand_shift (LSHIFT_EXPR, word_mode, part,
1882 build_int_2 (bitsize - bitsdone, 0), 0, 1);
1886 if (bitsdone != thissize)
1887 part = expand_shift (LSHIFT_EXPR, word_mode, part,
1888 build_int_2 (bitsdone - thissize, 0), 0, 1);
1894 /* Combine the parts with bitwise or. This works
1895 because we extracted each part as an unsigned bit field. */
1896 result = expand_binop (word_mode, ior_optab, part, result, NULL_RTX, 1,
1902 /* Unsigned bit field: we are done. */
1905 /* Signed bit field: sign-extend with two arithmetic shifts. */
1906 result = expand_shift (LSHIFT_EXPR, word_mode, result,
1907 build_int_2 (BITS_PER_WORD - bitsize, 0),
1909 return expand_shift (RSHIFT_EXPR, word_mode, result,
1910 build_int_2 (BITS_PER_WORD - bitsize, 0), NULL_RTX, 0);
1913 /* Add INC into TARGET. */
1916 expand_inc (target, inc)
1919 rtx value = expand_binop (GET_MODE (target), add_optab,
1921 target, 0, OPTAB_LIB_WIDEN);
1922 if (value != target)
1923 emit_move_insn (target, value);
1926 /* Subtract DEC from TARGET. */
1929 expand_dec (target, dec)
1932 rtx value = expand_binop (GET_MODE (target), sub_optab,
1934 target, 0, OPTAB_LIB_WIDEN);
1935 if (value != target)
1936 emit_move_insn (target, value);
1939 /* Output a shift instruction for expression code CODE,
1940 with SHIFTED being the rtx for the value to shift,
1941 and AMOUNT the tree for the amount to shift by.
1942 Store the result in the rtx TARGET, if that is convenient.
1943 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
1944 Return the rtx for where the value is. */
1947 expand_shift (code, mode, shifted, amount, target, unsignedp)
1948 enum tree_code code;
1949 register enum machine_mode mode;
1952 register rtx target;
1955 register rtx op1, temp = 0;
1956 register int left = (code == LSHIFT_EXPR || code == LROTATE_EXPR);
1957 register int rotate = (code == LROTATE_EXPR || code == RROTATE_EXPR);
1960 /* Previously detected shift-counts computed by NEGATE_EXPR
1961 and shifted in the other direction; but that does not work
1964 op1 = expand_expr (amount, NULL_RTX, VOIDmode, 0);
1966 #ifdef SHIFT_COUNT_TRUNCATED
1967 if (SHIFT_COUNT_TRUNCATED)
1969 if (GET_CODE (op1) == CONST_INT
1970 && ((unsigned HOST_WIDE_INT) INTVAL (op1) >=
1971 (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode)))
1972 op1 = GEN_INT ((unsigned HOST_WIDE_INT) INTVAL (op1)
1973 % GET_MODE_BITSIZE (mode));
1974 else if (GET_CODE (op1) == SUBREG
1975 && SUBREG_BYTE (op1) == 0)
1976 op1 = SUBREG_REG (op1);
1980 if (op1 == const0_rtx)
1983 for (try = 0; temp == 0 && try < 3; try++)
1985 enum optab_methods methods;
1988 methods = OPTAB_DIRECT;
1990 methods = OPTAB_WIDEN;
1992 methods = OPTAB_LIB_WIDEN;
1996 /* Widening does not work for rotation. */
1997 if (methods == OPTAB_WIDEN)
1999 else if (methods == OPTAB_LIB_WIDEN)
2001 /* If we have been unable to open-code this by a rotation,
2002 do it as the IOR of two shifts. I.e., to rotate A
2003 by N bits, compute (A << N) | ((unsigned) A >> (C - N))
2004 where C is the bitsize of A.
2006 It is theoretically possible that the target machine might
2007 not be able to perform either shift and hence we would
2008 be making two libcalls rather than just the one for the
2009 shift (similarly if IOR could not be done). We will allow
2010 this extremely unlikely lossage to avoid complicating the
2013 rtx subtarget = target == shifted ? 0 : target;
2015 tree type = TREE_TYPE (amount);
2016 tree new_amount = make_tree (type, op1);
2018 = fold (build (MINUS_EXPR, type,
2020 build_int_2 (GET_MODE_BITSIZE (mode),
2024 shifted = force_reg (mode, shifted);
2026 temp = expand_shift (left ? LSHIFT_EXPR : RSHIFT_EXPR,
2027 mode, shifted, new_amount, subtarget, 1);
2028 temp1 = expand_shift (left ? RSHIFT_EXPR : LSHIFT_EXPR,
2029 mode, shifted, other_amount, 0, 1);
2030 return expand_binop (mode, ior_optab, temp, temp1, target,
2031 unsignedp, methods);
2034 temp = expand_binop (mode,
2035 left ? rotl_optab : rotr_optab,
2036 shifted, op1, target, unsignedp, methods);
2038 /* If we don't have the rotate, but we are rotating by a constant
2039 that is in range, try a rotate in the opposite direction. */
2041 if (temp == 0 && GET_CODE (op1) == CONST_INT
2043 && (unsigned int) INTVAL (op1) < GET_MODE_BITSIZE (mode))
2044 temp = expand_binop (mode,
2045 left ? rotr_optab : rotl_optab,
2047 GEN_INT (GET_MODE_BITSIZE (mode)
2049 target, unsignedp, methods);
2052 temp = expand_binop (mode,
2053 left ? ashl_optab : lshr_optab,
2054 shifted, op1, target, unsignedp, methods);
2056 /* Do arithmetic shifts.
2057 Also, if we are going to widen the operand, we can just as well
2058 use an arithmetic right-shift instead of a logical one. */
2059 if (temp == 0 && ! rotate
2060 && (! unsignedp || (! left && methods == OPTAB_WIDEN)))
2062 enum optab_methods methods1 = methods;
2064 /* If trying to widen a log shift to an arithmetic shift,
2065 don't accept an arithmetic shift of the same size. */
2067 methods1 = OPTAB_MUST_WIDEN;
2069 /* Arithmetic shift */
2071 temp = expand_binop (mode,
2072 left ? ashl_optab : ashr_optab,
2073 shifted, op1, target, unsignedp, methods1);
2076 /* We used to try extzv here for logical right shifts, but that was
2077 only useful for one machine, the VAX, and caused poor code
2078 generation there for lshrdi3, so the code was deleted and a
2079 define_expand for lshrsi3 was added to vax.md. */
2087 enum alg_code { alg_zero, alg_m, alg_shift,
2088 alg_add_t_m2, alg_sub_t_m2,
2089 alg_add_factor, alg_sub_factor,
2090 alg_add_t2_m, alg_sub_t2_m,
2091 alg_add, alg_subtract, alg_factor, alg_shiftop };
2093 /* This structure records a sequence of operations.
2094 `ops' is the number of operations recorded.
2095 `cost' is their total cost.
2096 The operations are stored in `op' and the corresponding
2097 logarithms of the integer coefficients in `log'.
2099 These are the operations:
2100 alg_zero total := 0;
2101 alg_m total := multiplicand;
2102 alg_shift total := total * coeff
2103 alg_add_t_m2 total := total + multiplicand * coeff;
2104 alg_sub_t_m2 total := total - multiplicand * coeff;
2105 alg_add_factor total := total * coeff + total;
2106 alg_sub_factor total := total * coeff - total;
2107 alg_add_t2_m total := total * coeff + multiplicand;
2108 alg_sub_t2_m total := total * coeff - multiplicand;
2110 The first operand must be either alg_zero or alg_m. */
2116 /* The size of the OP and LOG fields are not directly related to the
2117 word size, but the worst-case algorithms will be if we have few
2118 consecutive ones or zeros, i.e., a multiplicand like 10101010101...
2119 In that case we will generate shift-by-2, add, shift-by-2, add,...,
2120 in total wordsize operations. */
2121 enum alg_code op[MAX_BITS_PER_WORD];
2122 char log[MAX_BITS_PER_WORD];
2125 static void synth_mult PARAMS ((struct algorithm *,
2126 unsigned HOST_WIDE_INT,
2128 static unsigned HOST_WIDE_INT choose_multiplier PARAMS ((unsigned HOST_WIDE_INT,
2130 unsigned HOST_WIDE_INT *,
2132 static unsigned HOST_WIDE_INT invert_mod2n PARAMS ((unsigned HOST_WIDE_INT,
2134 /* Compute and return the best algorithm for multiplying by T.
2135 The algorithm must cost less than cost_limit
2136 If retval.cost >= COST_LIMIT, no algorithm was found and all
2137 other field of the returned struct are undefined. */
2140 synth_mult (alg_out, t, cost_limit)
2141 struct algorithm *alg_out;
2142 unsigned HOST_WIDE_INT t;
2146 struct algorithm *alg_in, *best_alg;
2148 unsigned HOST_WIDE_INT q;
2150 /* Indicate that no algorithm is yet found. If no algorithm
2151 is found, this value will be returned and indicate failure. */
2152 alg_out->cost = cost_limit;
2154 if (cost_limit <= 0)
2157 /* t == 1 can be done in zero cost. */
2162 alg_out->op[0] = alg_m;
2166 /* t == 0 sometimes has a cost. If it does and it exceeds our limit,
2170 if (zero_cost >= cost_limit)
2175 alg_out->cost = zero_cost;
2176 alg_out->op[0] = alg_zero;
2181 /* We'll be needing a couple extra algorithm structures now. */
2183 alg_in = (struct algorithm *)alloca (sizeof (struct algorithm));
2184 best_alg = (struct algorithm *)alloca (sizeof (struct algorithm));
2186 /* If we have a group of zero bits at the low-order part of T, try
2187 multiplying by the remaining bits and then doing a shift. */
2191 m = floor_log2 (t & -t); /* m = number of low zero bits */
2192 if (m < BITS_PER_WORD)
2195 cost = shift_cost[m];
2196 synth_mult (alg_in, q, cost_limit - cost);
2198 cost += alg_in->cost;
2199 if (cost < cost_limit)
2201 struct algorithm *x;
2202 x = alg_in, alg_in = best_alg, best_alg = x;
2203 best_alg->log[best_alg->ops] = m;
2204 best_alg->op[best_alg->ops] = alg_shift;
2210 /* If we have an odd number, add or subtract one. */
2213 unsigned HOST_WIDE_INT w;
2215 for (w = 1; (w & t) != 0; w <<= 1)
2217 /* If T was -1, then W will be zero after the loop. This is another
2218 case where T ends with ...111. Handling this with (T + 1) and
2219 subtract 1 produces slightly better code and results in algorithm
2220 selection much faster than treating it like the ...0111 case
2224 /* Reject the case where t is 3.
2225 Thus we prefer addition in that case. */
2228 /* T ends with ...111. Multiply by (T + 1) and subtract 1. */
2231 synth_mult (alg_in, t + 1, cost_limit - cost);
2233 cost += alg_in->cost;
2234 if (cost < cost_limit)
2236 struct algorithm *x;
2237 x = alg_in, alg_in = best_alg, best_alg = x;
2238 best_alg->log[best_alg->ops] = 0;
2239 best_alg->op[best_alg->ops] = alg_sub_t_m2;
2245 /* T ends with ...01 or ...011. Multiply by (T - 1) and add 1. */
2248 synth_mult (alg_in, t - 1, cost_limit - cost);
2250 cost += alg_in->cost;
2251 if (cost < cost_limit)
2253 struct algorithm *x;
2254 x = alg_in, alg_in = best_alg, best_alg = x;
2255 best_alg->log[best_alg->ops] = 0;
2256 best_alg->op[best_alg->ops] = alg_add_t_m2;
2262 /* Look for factors of t of the form
2263 t = q(2**m +- 1), 2 <= m <= floor(log2(t - 1)).
2264 If we find such a factor, we can multiply by t using an algorithm that
2265 multiplies by q, shift the result by m and add/subtract it to itself.
2267 We search for large factors first and loop down, even if large factors
2268 are less probable than small; if we find a large factor we will find a
2269 good sequence quickly, and therefore be able to prune (by decreasing
2270 COST_LIMIT) the search. */
2272 for (m = floor_log2 (t - 1); m >= 2; m--)
2274 unsigned HOST_WIDE_INT d;
2276 d = ((unsigned HOST_WIDE_INT) 1 << m) + 1;
2277 if (t % d == 0 && t > d && m < BITS_PER_WORD)
2279 cost = MIN (shiftadd_cost[m], add_cost + shift_cost[m]);
2280 synth_mult (alg_in, t / d, cost_limit - cost);
2282 cost += alg_in->cost;
2283 if (cost < cost_limit)
2285 struct algorithm *x;
2286 x = alg_in, alg_in = best_alg, best_alg = x;
2287 best_alg->log[best_alg->ops] = m;
2288 best_alg->op[best_alg->ops] = alg_add_factor;
2291 /* Other factors will have been taken care of in the recursion. */
2295 d = ((unsigned HOST_WIDE_INT) 1 << m) - 1;
2296 if (t % d == 0 && t > d && m < BITS_PER_WORD)
2298 cost = MIN (shiftsub_cost[m], add_cost + shift_cost[m]);
2299 synth_mult (alg_in, t / d, cost_limit - cost);
2301 cost += alg_in->cost;
2302 if (cost < cost_limit)
2304 struct algorithm *x;
2305 x = alg_in, alg_in = best_alg, best_alg = x;
2306 best_alg->log[best_alg->ops] = m;
2307 best_alg->op[best_alg->ops] = alg_sub_factor;
2314 /* Try shift-and-add (load effective address) instructions,
2315 i.e. do a*3, a*5, a*9. */
2321 if (m >= 0 && m < BITS_PER_WORD)
2323 cost = shiftadd_cost[m];
2324 synth_mult (alg_in, (t - 1) >> m, cost_limit - cost);
2326 cost += alg_in->cost;
2327 if (cost < cost_limit)
2329 struct algorithm *x;
2330 x = alg_in, alg_in = best_alg, best_alg = x;
2331 best_alg->log[best_alg->ops] = m;
2332 best_alg->op[best_alg->ops] = alg_add_t2_m;
2340 if (m >= 0 && m < BITS_PER_WORD)
2342 cost = shiftsub_cost[m];
2343 synth_mult (alg_in, (t + 1) >> m, cost_limit - cost);
2345 cost += alg_in->cost;
2346 if (cost < cost_limit)
2348 struct algorithm *x;
2349 x = alg_in, alg_in = best_alg, best_alg = x;
2350 best_alg->log[best_alg->ops] = m;
2351 best_alg->op[best_alg->ops] = alg_sub_t2_m;
2357 /* If cost_limit has not decreased since we stored it in alg_out->cost,
2358 we have not found any algorithm. */
2359 if (cost_limit == alg_out->cost)
2362 /* If we are getting a too long sequence for `struct algorithm'
2363 to record, make this search fail. */
2364 if (best_alg->ops == MAX_BITS_PER_WORD)
2367 /* Copy the algorithm from temporary space to the space at alg_out.
2368 We avoid using structure assignment because the majority of
2369 best_alg is normally undefined, and this is a critical function. */
2370 alg_out->ops = best_alg->ops + 1;
2371 alg_out->cost = cost_limit;
2372 memcpy (alg_out->op, best_alg->op,
2373 alg_out->ops * sizeof *alg_out->op);
2374 memcpy (alg_out->log, best_alg->log,
2375 alg_out->ops * sizeof *alg_out->log);
2378 /* Perform a multiplication and return an rtx for the result.
2379 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
2380 TARGET is a suggestion for where to store the result (an rtx).
2382 We check specially for a constant integer as OP1.
2383 If you want this check for OP0 as well, then before calling
2384 you should swap the two operands if OP0 would be constant. */
2387 expand_mult (mode, op0, op1, target, unsignedp)
2388 enum machine_mode mode;
2389 register rtx op0, op1, target;
2392 rtx const_op1 = op1;
2394 /* synth_mult does an `unsigned int' multiply. As long as the mode is
2395 less than or equal in size to `unsigned int' this doesn't matter.
2396 If the mode is larger than `unsigned int', then synth_mult works only
2397 if the constant value exactly fits in an `unsigned int' without any
2398 truncation. This means that multiplying by negative values does
2399 not work; results are off by 2^32 on a 32 bit machine. */
2401 /* If we are multiplying in DImode, it may still be a win
2402 to try to work with shifts and adds. */
2403 if (GET_CODE (op1) == CONST_DOUBLE
2404 && GET_MODE_CLASS (GET_MODE (op1)) == MODE_INT
2405 && HOST_BITS_PER_INT >= BITS_PER_WORD
2406 && CONST_DOUBLE_HIGH (op1) == 0)
2407 const_op1 = GEN_INT (CONST_DOUBLE_LOW (op1));
2408 else if (HOST_BITS_PER_INT < GET_MODE_BITSIZE (mode)
2409 && GET_CODE (op1) == CONST_INT
2410 && INTVAL (op1) < 0)
2413 /* We used to test optimize here, on the grounds that it's better to
2414 produce a smaller program when -O is not used.
2415 But this causes such a terrible slowdown sometimes
2416 that it seems better to use synth_mult always. */
2418 if (const_op1 && GET_CODE (const_op1) == CONST_INT
2419 && (unsignedp || ! flag_trapv))
2421 struct algorithm alg;
2422 struct algorithm alg2;
2423 HOST_WIDE_INT val = INTVAL (op1);
2424 HOST_WIDE_INT val_so_far;
2427 enum {basic_variant, negate_variant, add_variant} variant = basic_variant;
2429 /* Try to do the computation three ways: multiply by the negative of OP1
2430 and then negate, do the multiplication directly, or do multiplication
2433 mult_cost = rtx_cost (gen_rtx_MULT (mode, op0, op1), SET);
2434 mult_cost = MIN (12 * add_cost, mult_cost);
2436 synth_mult (&alg, val, mult_cost);
2438 /* This works only if the inverted value actually fits in an
2440 if (HOST_BITS_PER_INT >= GET_MODE_BITSIZE (mode))
2442 synth_mult (&alg2, - val,
2443 (alg.cost < mult_cost ? alg.cost : mult_cost) - negate_cost);
2444 if (alg2.cost + negate_cost < alg.cost)
2445 alg = alg2, variant = negate_variant;
2448 /* This proves very useful for division-by-constant. */
2449 synth_mult (&alg2, val - 1,
2450 (alg.cost < mult_cost ? alg.cost : mult_cost) - add_cost);
2451 if (alg2.cost + add_cost < alg.cost)
2452 alg = alg2, variant = add_variant;
2454 if (alg.cost < mult_cost)
2456 /* We found something cheaper than a multiply insn. */
2459 enum machine_mode nmode;
2461 op0 = protect_from_queue (op0, 0);
2463 /* Avoid referencing memory over and over.
2464 For speed, but also for correctness when mem is volatile. */
2465 if (GET_CODE (op0) == MEM)
2466 op0 = force_reg (mode, op0);
2468 /* ACCUM starts out either as OP0 or as a zero, depending on
2469 the first operation. */
2471 if (alg.op[0] == alg_zero)
2473 accum = copy_to_mode_reg (mode, const0_rtx);
2476 else if (alg.op[0] == alg_m)
2478 accum = copy_to_mode_reg (mode, op0);
2484 for (opno = 1; opno < alg.ops; opno++)
2486 int log = alg.log[opno];
2487 int preserve = preserve_subexpressions_p ();
2488 rtx shift_subtarget = preserve ? 0 : accum;
2490 = (opno == alg.ops - 1 && target != 0 && variant != add_variant
2493 rtx accum_target = preserve ? 0 : accum;
2495 switch (alg.op[opno])
2498 accum = expand_shift (LSHIFT_EXPR, mode, accum,
2499 build_int_2 (log, 0), NULL_RTX, 0);
2504 tem = expand_shift (LSHIFT_EXPR, mode, op0,
2505 build_int_2 (log, 0), NULL_RTX, 0);
2506 accum = force_operand (gen_rtx_PLUS (mode, accum, tem),
2508 ? add_target : accum_target);
2509 val_so_far += (HOST_WIDE_INT) 1 << log;
2513 tem = expand_shift (LSHIFT_EXPR, mode, op0,
2514 build_int_2 (log, 0), NULL_RTX, 0);
2515 accum = force_operand (gen_rtx_MINUS (mode, accum, tem),
2517 ? add_target : accum_target);
2518 val_so_far -= (HOST_WIDE_INT) 1 << log;
2522 accum = expand_shift (LSHIFT_EXPR, mode, accum,
2523 build_int_2 (log, 0), shift_subtarget,
2525 accum = force_operand (gen_rtx_PLUS (mode, accum, op0),
2527 ? add_target : accum_target);
2528 val_so_far = (val_so_far << log) + 1;
2532 accum = expand_shift (LSHIFT_EXPR, mode, accum,
2533 build_int_2 (log, 0), shift_subtarget,
2535 accum = force_operand (gen_rtx_MINUS (mode, accum, op0),
2537 ? add_target : accum_target);
2538 val_so_far = (val_so_far << log) - 1;
2541 case alg_add_factor:
2542 tem = expand_shift (LSHIFT_EXPR, mode, accum,
2543 build_int_2 (log, 0), NULL_RTX, 0);
2544 accum = force_operand (gen_rtx_PLUS (mode, accum, tem),
2546 ? add_target : accum_target);
2547 val_so_far += val_so_far << log;
2550 case alg_sub_factor:
2551 tem = expand_shift (LSHIFT_EXPR, mode, accum,
2552 build_int_2 (log, 0), NULL_RTX, 0);
2553 accum = force_operand (gen_rtx_MINUS (mode, tem, accum),
2554 (add_target ? add_target
2555 : preserve ? 0 : tem));
2556 val_so_far = (val_so_far << log) - val_so_far;
2563 /* Write a REG_EQUAL note on the last insn so that we can cse
2564 multiplication sequences. Note that if ACCUM is a SUBREG,
2565 we've set the inner register and must properly indicate
2568 tem = op0, nmode = mode;
2569 if (GET_CODE (accum) == SUBREG)
2571 nmode = GET_MODE (SUBREG_REG (accum));
2572 tem = gen_lowpart (nmode, op0);
2575 insn = get_last_insn ();
2576 set_unique_reg_note (insn,
2578 gen_rtx_MULT (nmode, tem,
2579 GEN_INT (val_so_far)));
2582 if (variant == negate_variant)
2584 val_so_far = - val_so_far;
2585 accum = expand_unop (mode, neg_optab, accum, target, 0);
2587 else if (variant == add_variant)
2589 val_so_far = val_so_far + 1;
2590 accum = force_operand (gen_rtx_PLUS (mode, accum, op0), target);
2593 if (val != val_so_far)
2600 /* This used to use umul_optab if unsigned, but for non-widening multiply
2601 there is no difference between signed and unsigned. */
2602 op0 = expand_binop (mode,
2604 && flag_trapv && (GET_MODE_CLASS(mode) == MODE_INT)
2605 ? smulv_optab : smul_optab,
2606 op0, op1, target, unsignedp, OPTAB_LIB_WIDEN);
2612 /* Return the smallest n such that 2**n >= X. */
2616 unsigned HOST_WIDE_INT x;
2618 return floor_log2 (x - 1) + 1;
2621 /* Choose a minimal N + 1 bit approximation to 1/D that can be used to
2622 replace division by D, and put the least significant N bits of the result
2623 in *MULTIPLIER_PTR and return the most significant bit.
2625 The width of operations is N (should be <= HOST_BITS_PER_WIDE_INT), the
2626 needed precision is in PRECISION (should be <= N).
2628 PRECISION should be as small as possible so this function can choose
2629 multiplier more freely.
2631 The rounded-up logarithm of D is placed in *lgup_ptr. A shift count that
2632 is to be used for a final right shift is placed in *POST_SHIFT_PTR.
2634 Using this function, x/D will be equal to (x * m) >> (*POST_SHIFT_PTR),
2635 where m is the full HOST_BITS_PER_WIDE_INT + 1 bit multiplier. */
2638 unsigned HOST_WIDE_INT
2639 choose_multiplier (d, n, precision, multiplier_ptr, post_shift_ptr, lgup_ptr)
2640 unsigned HOST_WIDE_INT d;
2643 unsigned HOST_WIDE_INT *multiplier_ptr;
2644 int *post_shift_ptr;
2647 HOST_WIDE_INT mhigh_hi, mlow_hi;
2648 unsigned HOST_WIDE_INT mhigh_lo, mlow_lo;
2649 int lgup, post_shift;
2651 unsigned HOST_WIDE_INT nl, dummy1;
2652 HOST_WIDE_INT nh, dummy2;
2654 /* lgup = ceil(log2(divisor)); */
2655 lgup = ceil_log2 (d);
2661 pow2 = n + lgup - precision;
2663 if (pow == 2 * HOST_BITS_PER_WIDE_INT)
2665 /* We could handle this with some effort, but this case is much better
2666 handled directly with a scc insn, so rely on caller using that. */
2670 /* mlow = 2^(N + lgup)/d */
2671 if (pow >= HOST_BITS_PER_WIDE_INT)
2673 nh = (HOST_WIDE_INT) 1 << (pow - HOST_BITS_PER_WIDE_INT);
2679 nl = (unsigned HOST_WIDE_INT) 1 << pow;
2681 div_and_round_double (TRUNC_DIV_EXPR, 1, nl, nh, d, (HOST_WIDE_INT) 0,
2682 &mlow_lo, &mlow_hi, &dummy1, &dummy2);
2684 /* mhigh = (2^(N + lgup) + 2^N + lgup - precision)/d */
2685 if (pow2 >= HOST_BITS_PER_WIDE_INT)
2686 nh |= (HOST_WIDE_INT) 1 << (pow2 - HOST_BITS_PER_WIDE_INT);
2688 nl |= (unsigned HOST_WIDE_INT) 1 << pow2;
2689 div_and_round_double (TRUNC_DIV_EXPR, 1, nl, nh, d, (HOST_WIDE_INT) 0,
2690 &mhigh_lo, &mhigh_hi, &dummy1, &dummy2);
2692 if (mhigh_hi && nh - d >= d)
2694 if (mhigh_hi > 1 || mlow_hi > 1)
2696 /* assert that mlow < mhigh. */
2697 if (! (mlow_hi < mhigh_hi || (mlow_hi == mhigh_hi && mlow_lo < mhigh_lo)))
2700 /* If precision == N, then mlow, mhigh exceed 2^N
2701 (but they do not exceed 2^(N+1)). */
2703 /* Reduce to lowest terms */
2704 for (post_shift = lgup; post_shift > 0; post_shift--)
2706 unsigned HOST_WIDE_INT ml_lo = (mlow_hi << (HOST_BITS_PER_WIDE_INT - 1)) | (mlow_lo >> 1);
2707 unsigned HOST_WIDE_INT mh_lo = (mhigh_hi << (HOST_BITS_PER_WIDE_INT - 1)) | (mhigh_lo >> 1);
2717 *post_shift_ptr = post_shift;
2719 if (n < HOST_BITS_PER_WIDE_INT)
2721 unsigned HOST_WIDE_INT mask = ((unsigned HOST_WIDE_INT) 1 << n) - 1;
2722 *multiplier_ptr = mhigh_lo & mask;
2723 return mhigh_lo >= mask;
2727 *multiplier_ptr = mhigh_lo;
2732 /* Compute the inverse of X mod 2**n, i.e., find Y such that X * Y is
2733 congruent to 1 (mod 2**N). */
2735 static unsigned HOST_WIDE_INT
2737 unsigned HOST_WIDE_INT x;
2740 /* Solve x*y == 1 (mod 2^n), where x is odd. Return y. */
2742 /* The algorithm notes that the choice y = x satisfies
2743 x*y == 1 mod 2^3, since x is assumed odd.
2744 Each iteration doubles the number of bits of significance in y. */
2746 unsigned HOST_WIDE_INT mask;
2747 unsigned HOST_WIDE_INT y = x;
2750 mask = (n == HOST_BITS_PER_WIDE_INT
2751 ? ~(unsigned HOST_WIDE_INT) 0
2752 : ((unsigned HOST_WIDE_INT) 1 << n) - 1);
2756 y = y * (2 - x*y) & mask; /* Modulo 2^N */
2762 /* Emit code to adjust ADJ_OPERAND after multiplication of wrong signedness
2763 flavor of OP0 and OP1. ADJ_OPERAND is already the high half of the
2764 product OP0 x OP1. If UNSIGNEDP is nonzero, adjust the signed product
2765 to become unsigned, if UNSIGNEDP is zero, adjust the unsigned product to
2768 The result is put in TARGET if that is convenient.
2770 MODE is the mode of operation. */
2773 expand_mult_highpart_adjust (mode, adj_operand, op0, op1, target, unsignedp)
2774 enum machine_mode mode;
2775 register rtx adj_operand, op0, op1, target;
2779 enum rtx_code adj_code = unsignedp ? PLUS : MINUS;
2781 tem = expand_shift (RSHIFT_EXPR, mode, op0,
2782 build_int_2 (GET_MODE_BITSIZE (mode) - 1, 0),
2784 tem = expand_and (tem, op1, NULL_RTX);
2786 = force_operand (gen_rtx_fmt_ee (adj_code, mode, adj_operand, tem),
2789 tem = expand_shift (RSHIFT_EXPR, mode, op1,
2790 build_int_2 (GET_MODE_BITSIZE (mode) - 1, 0),
2792 tem = expand_and (tem, op0, NULL_RTX);
2793 target = force_operand (gen_rtx_fmt_ee (adj_code, mode, adj_operand, tem),
2799 /* Emit code to multiply OP0 and CNST1, putting the high half of the result
2800 in TARGET if that is convenient, and return where the result is. If the
2801 operation can not be performed, 0 is returned.
2803 MODE is the mode of operation and result.
2805 UNSIGNEDP nonzero means unsigned multiply.
2807 MAX_COST is the total allowed cost for the expanded RTL. */
2810 expand_mult_highpart (mode, op0, cnst1, target, unsignedp, max_cost)
2811 enum machine_mode mode;
2812 register rtx op0, target;
2813 unsigned HOST_WIDE_INT cnst1;
2817 enum machine_mode wider_mode = GET_MODE_WIDER_MODE (mode);
2818 optab mul_highpart_optab;
2821 int size = GET_MODE_BITSIZE (mode);
2824 /* We can't support modes wider than HOST_BITS_PER_INT. */
2825 if (size > HOST_BITS_PER_WIDE_INT)
2828 op1 = GEN_INT (trunc_int_for_mode (cnst1, mode));
2830 if (GET_MODE_BITSIZE (wider_mode) <= HOST_BITS_PER_INT)
2834 = immed_double_const (cnst1,
2837 : -(cnst1 >> (HOST_BITS_PER_WIDE_INT - 1))),
2840 /* expand_mult handles constant multiplication of word_mode
2841 or narrower. It does a poor job for large modes. */
2842 if (size < BITS_PER_WORD
2843 && mul_cost[(int) wider_mode] + shift_cost[size-1] < max_cost)
2845 /* We have to do this, since expand_binop doesn't do conversion for
2846 multiply. Maybe change expand_binop to handle widening multiply? */
2847 op0 = convert_to_mode (wider_mode, op0, unsignedp);
2849 /* We know that this can't have signed overflow, so pretend this is
2850 an unsigned multiply. */
2851 tem = expand_mult (wider_mode, op0, wide_op1, NULL_RTX, 0);
2852 tem = expand_shift (RSHIFT_EXPR, wider_mode, tem,
2853 build_int_2 (size, 0), NULL_RTX, 1);
2854 return convert_modes (mode, wider_mode, tem, unsignedp);
2858 target = gen_reg_rtx (mode);
2860 /* Firstly, try using a multiplication insn that only generates the needed
2861 high part of the product, and in the sign flavor of unsignedp. */
2862 if (mul_highpart_cost[(int) mode] < max_cost)
2864 mul_highpart_optab = unsignedp ? umul_highpart_optab : smul_highpart_optab;
2865 target = expand_binop (mode, mul_highpart_optab,
2866 op0, op1, target, unsignedp, OPTAB_DIRECT);
2871 /* Secondly, same as above, but use sign flavor opposite of unsignedp.
2872 Need to adjust the result after the multiplication. */
2873 if (size - 1 < BITS_PER_WORD
2874 && (mul_highpart_cost[(int) mode] + 2 * shift_cost[size-1] + 4 * add_cost
2877 mul_highpart_optab = unsignedp ? smul_highpart_optab : umul_highpart_optab;
2878 target = expand_binop (mode, mul_highpart_optab,
2879 op0, op1, target, unsignedp, OPTAB_DIRECT);
2881 /* We used the wrong signedness. Adjust the result. */
2882 return expand_mult_highpart_adjust (mode, target, op0,
2883 op1, target, unsignedp);
2886 /* Try widening multiplication. */
2887 moptab = unsignedp ? umul_widen_optab : smul_widen_optab;
2888 if (moptab->handlers[(int) wider_mode].insn_code != CODE_FOR_nothing
2889 && mul_widen_cost[(int) wider_mode] < max_cost)
2891 op1 = force_reg (mode, op1);
2895 /* Try widening the mode and perform a non-widening multiplication. */
2896 moptab = smul_optab;
2897 if (smul_optab->handlers[(int) wider_mode].insn_code != CODE_FOR_nothing
2898 && size - 1 < BITS_PER_WORD
2899 && mul_cost[(int) wider_mode] + shift_cost[size-1] < max_cost)
2905 /* Try widening multiplication of opposite signedness, and adjust. */
2906 moptab = unsignedp ? smul_widen_optab : umul_widen_optab;
2907 if (moptab->handlers[(int) wider_mode].insn_code != CODE_FOR_nothing
2908 && size - 1 < BITS_PER_WORD
2909 && (mul_widen_cost[(int) wider_mode]
2910 + 2 * shift_cost[size-1] + 4 * add_cost < max_cost))
2912 rtx regop1 = force_reg (mode, op1);
2913 tem = expand_binop (wider_mode, moptab, op0, regop1,
2914 NULL_RTX, ! unsignedp, OPTAB_WIDEN);
2917 /* Extract the high half of the just generated product. */
2918 tem = expand_shift (RSHIFT_EXPR, wider_mode, tem,
2919 build_int_2 (size, 0), NULL_RTX, 1);
2920 tem = convert_modes (mode, wider_mode, tem, unsignedp);
2921 /* We used the wrong signedness. Adjust the result. */
2922 return expand_mult_highpart_adjust (mode, tem, op0, op1,
2930 /* Pass NULL_RTX as target since TARGET has wrong mode. */
2931 tem = expand_binop (wider_mode, moptab, op0, op1,
2932 NULL_RTX, unsignedp, OPTAB_WIDEN);
2936 /* Extract the high half of the just generated product. */
2937 if (mode == word_mode)
2939 return gen_highpart (mode, tem);
2943 tem = expand_shift (RSHIFT_EXPR, wider_mode, tem,
2944 build_int_2 (size, 0), NULL_RTX, 1);
2945 return convert_modes (mode, wider_mode, tem, unsignedp);
2949 /* Emit the code to divide OP0 by OP1, putting the result in TARGET
2950 if that is convenient, and returning where the result is.
2951 You may request either the quotient or the remainder as the result;
2952 specify REM_FLAG nonzero to get the remainder.
2954 CODE is the expression code for which kind of division this is;
2955 it controls how rounding is done. MODE is the machine mode to use.
2956 UNSIGNEDP nonzero means do unsigned division. */
2958 /* ??? For CEIL_MOD_EXPR, can compute incorrect remainder with ANDI
2959 and then correct it by or'ing in missing high bits
2960 if result of ANDI is nonzero.
2961 For ROUND_MOD_EXPR, can use ANDI and then sign-extend the result.
2962 This could optimize to a bfexts instruction.
2963 But C doesn't use these operations, so their optimizations are
2965 /* ??? For modulo, we don't actually need the highpart of the first product,
2966 the low part will do nicely. And for small divisors, the second multiply
2967 can also be a low-part only multiply or even be completely left out.
2968 E.g. to calculate the remainder of a division by 3 with a 32 bit
2969 multiply, multiply with 0x55555556 and extract the upper two bits;
2970 the result is exact for inputs up to 0x1fffffff.
2971 The input range can be reduced by using cross-sum rules.
2972 For odd divisors >= 3, the following table gives right shift counts
2973 so that if an number is shifted by an integer multiple of the given
2974 amount, the remainder stays the same:
2975 2, 4, 3, 6, 10, 12, 4, 8, 18, 6, 11, 20, 18, 0, 5, 10, 12, 0, 12, 20,
2976 14, 12, 23, 21, 8, 0, 20, 18, 0, 0, 6, 12, 0, 22, 0, 18, 20, 30, 0, 0,
2977 0, 8, 0, 11, 12, 10, 36, 0, 30, 0, 0, 12, 0, 0, 0, 0, 44, 12, 24, 0,
2978 20, 0, 7, 14, 0, 18, 36, 0, 0, 46, 60, 0, 42, 0, 15, 24, 20, 0, 0, 33,
2979 0, 20, 0, 0, 18, 0, 60, 0, 0, 0, 0, 0, 40, 18, 0, 0, 12
2981 Cross-sum rules for even numbers can be derived by leaving as many bits
2982 to the right alone as the divisor has zeros to the right.
2983 E.g. if x is an unsigned 32 bit number:
2984 (x mod 12) == (((x & 1023) + ((x >> 8) & ~3)) * 0x15555558 >> 2 * 3) >> 28
2987 #define EXACT_POWER_OF_2_OR_ZERO_P(x) (((x) & ((x) - 1)) == 0)
2990 expand_divmod (rem_flag, code, mode, op0, op1, target, unsignedp)
2992 enum tree_code code;
2993 enum machine_mode mode;
2994 register rtx op0, op1, target;
2997 enum machine_mode compute_mode;
2998 register rtx tquotient;
2999 rtx quotient = 0, remainder = 0;
3003 optab optab1, optab2;
3004 int op1_is_constant, op1_is_pow2;
3005 int max_cost, extra_cost;
3006 static HOST_WIDE_INT last_div_const = 0;
3008 op1_is_constant = GET_CODE (op1) == CONST_INT;
3009 op1_is_pow2 = (op1_is_constant
3010 && ((EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1))
3011 || (! unsignedp && EXACT_POWER_OF_2_OR_ZERO_P (-INTVAL (op1))))));
3014 This is the structure of expand_divmod:
3016 First comes code to fix up the operands so we can perform the operations
3017 correctly and efficiently.
3019 Second comes a switch statement with code specific for each rounding mode.
3020 For some special operands this code emits all RTL for the desired
3021 operation, for other cases, it generates only a quotient and stores it in
3022 QUOTIENT. The case for trunc division/remainder might leave quotient = 0,
3023 to indicate that it has not done anything.
3025 Last comes code that finishes the operation. If QUOTIENT is set and
3026 REM_FLAG is set, the remainder is computed as OP0 - QUOTIENT * OP1. If
3027 QUOTIENT is not set, it is computed using trunc rounding.
3029 We try to generate special code for division and remainder when OP1 is a
3030 constant. If |OP1| = 2**n we can use shifts and some other fast
3031 operations. For other values of OP1, we compute a carefully selected
3032 fixed-point approximation m = 1/OP1, and generate code that multiplies OP0
3035 In all cases but EXACT_DIV_EXPR, this multiplication requires the upper
3036 half of the product. Different strategies for generating the product are
3037 implemented in expand_mult_highpart.
3039 If what we actually want is the remainder, we generate that by another
3040 by-constant multiplication and a subtraction. */
3042 /* We shouldn't be called with OP1 == const1_rtx, but some of the
3043 code below will malfunction if we are, so check here and handle
3044 the special case if so. */
3045 if (op1 == const1_rtx)
3046 return rem_flag ? const0_rtx : op0;
3048 /* When dividing by -1, we could get an overflow.
3049 negv_optab can handle overflows. */
3050 if (! unsignedp && op1 == constm1_rtx)
3054 return expand_unop (mode, flag_trapv && GET_MODE_CLASS(mode) == MODE_INT
3055 ? negv_optab : neg_optab, op0, target, 0);
3059 /* Don't use the function value register as a target
3060 since we have to read it as well as write it,
3061 and function-inlining gets confused by this. */
3062 && ((REG_P (target) && REG_FUNCTION_VALUE_P (target))
3063 /* Don't clobber an operand while doing a multi-step calculation. */
3064 || ((rem_flag || op1_is_constant)
3065 && (reg_mentioned_p (target, op0)
3066 || (GET_CODE (op0) == MEM && GET_CODE (target) == MEM)))
3067 || reg_mentioned_p (target, op1)
3068 || (GET_CODE (op1) == MEM && GET_CODE (target) == MEM)))
3071 /* Get the mode in which to perform this computation. Normally it will
3072 be MODE, but sometimes we can't do the desired operation in MODE.
3073 If so, pick a wider mode in which we can do the operation. Convert
3074 to that mode at the start to avoid repeated conversions.
3076 First see what operations we need. These depend on the expression
3077 we are evaluating. (We assume that divxx3 insns exist under the
3078 same conditions that modxx3 insns and that these insns don't normally
3079 fail. If these assumptions are not correct, we may generate less
3080 efficient code in some cases.)
3082 Then see if we find a mode in which we can open-code that operation
3083 (either a division, modulus, or shift). Finally, check for the smallest
3084 mode for which we can do the operation with a library call. */
3086 /* We might want to refine this now that we have division-by-constant
3087 optimization. Since expand_mult_highpart tries so many variants, it is
3088 not straightforward to generalize this. Maybe we should make an array
3089 of possible modes in init_expmed? Save this for GCC 2.7. */
3091 optab1 = (op1_is_pow2 ? (unsignedp ? lshr_optab : ashr_optab)
3092 : (unsignedp ? udiv_optab : sdiv_optab));
3093 optab2 = (op1_is_pow2 ? optab1 : (unsignedp ? udivmod_optab : sdivmod_optab));
3095 for (compute_mode = mode; compute_mode != VOIDmode;
3096 compute_mode = GET_MODE_WIDER_MODE (compute_mode))
3097 if (optab1->handlers[(int) compute_mode].insn_code != CODE_FOR_nothing
3098 || optab2->handlers[(int) compute_mode].insn_code != CODE_FOR_nothing)
3101 if (compute_mode == VOIDmode)
3102 for (compute_mode = mode; compute_mode != VOIDmode;
3103 compute_mode = GET_MODE_WIDER_MODE (compute_mode))
3104 if (optab1->handlers[(int) compute_mode].libfunc
3105 || optab2->handlers[(int) compute_mode].libfunc)
3108 /* If we still couldn't find a mode, use MODE, but we'll probably abort
3110 if (compute_mode == VOIDmode)
3111 compute_mode = mode;
3113 if (target && GET_MODE (target) == compute_mode)
3116 tquotient = gen_reg_rtx (compute_mode);
3118 size = GET_MODE_BITSIZE (compute_mode);
3120 /* It should be possible to restrict the precision to GET_MODE_BITSIZE
3121 (mode), and thereby get better code when OP1 is a constant. Do that
3122 later. It will require going over all usages of SIZE below. */
3123 size = GET_MODE_BITSIZE (mode);
3126 /* Only deduct something for a REM if the last divide done was
3127 for a different constant. Then set the constant of the last
3129 max_cost = div_cost[(int) compute_mode]
3130 - (rem_flag && ! (last_div_const != 0 && op1_is_constant
3131 && INTVAL (op1) == last_div_const)
3132 ? mul_cost[(int) compute_mode] + add_cost : 0);
3134 last_div_const = ! rem_flag && op1_is_constant ? INTVAL (op1) : 0;
3136 /* Now convert to the best mode to use. */
3137 if (compute_mode != mode)
3139 op0 = convert_modes (compute_mode, mode, op0, unsignedp);
3140 op1 = convert_modes (compute_mode, mode, op1, unsignedp);
3142 /* convert_modes may have placed op1 into a register, so we
3143 must recompute the following. */
3144 op1_is_constant = GET_CODE (op1) == CONST_INT;
3145 op1_is_pow2 = (op1_is_constant
3146 && ((EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1))
3148 && EXACT_POWER_OF_2_OR_ZERO_P (-INTVAL (op1)))))) ;
3151 /* If one of the operands is a volatile MEM, copy it into a register. */
3153 if (GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0))
3154 op0 = force_reg (compute_mode, op0);
3155 if (GET_CODE (op1) == MEM && MEM_VOLATILE_P (op1))
3156 op1 = force_reg (compute_mode, op1);
3158 /* If we need the remainder or if OP1 is constant, we need to
3159 put OP0 in a register in case it has any queued subexpressions. */
3160 if (rem_flag || op1_is_constant)
3161 op0 = force_reg (compute_mode, op0);
3163 last = get_last_insn ();
3165 /* Promote floor rounding to trunc rounding for unsigned operations. */
3168 if (code == FLOOR_DIV_EXPR)
3169 code = TRUNC_DIV_EXPR;
3170 if (code == FLOOR_MOD_EXPR)
3171 code = TRUNC_MOD_EXPR;
3172 if (code == EXACT_DIV_EXPR && op1_is_pow2)
3173 code = TRUNC_DIV_EXPR;
3176 if (op1 != const0_rtx)
3179 case TRUNC_MOD_EXPR:
3180 case TRUNC_DIV_EXPR:
3181 if (op1_is_constant)
3185 unsigned HOST_WIDE_INT mh, ml;
3186 int pre_shift, post_shift;
3188 unsigned HOST_WIDE_INT d = INTVAL (op1);
3190 if (EXACT_POWER_OF_2_OR_ZERO_P (d))
3192 pre_shift = floor_log2 (d);
3196 = expand_binop (compute_mode, and_optab, op0,
3197 GEN_INT (((HOST_WIDE_INT) 1 << pre_shift) - 1),
3201 return gen_lowpart (mode, remainder);
3203 quotient = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3204 build_int_2 (pre_shift, 0),
3207 else if (size <= HOST_BITS_PER_WIDE_INT)
3209 if (d >= ((unsigned HOST_WIDE_INT) 1 << (size - 1)))
3211 /* Most significant bit of divisor is set; emit an scc
3213 quotient = emit_store_flag (tquotient, GEU, op0, op1,
3214 compute_mode, 1, 1);
3220 /* Find a suitable multiplier and right shift count
3221 instead of multiplying with D. */
3223 mh = choose_multiplier (d, size, size,
3224 &ml, &post_shift, &dummy);
3226 /* If the suggested multiplier is more than SIZE bits,
3227 we can do better for even divisors, using an
3228 initial right shift. */
3229 if (mh != 0 && (d & 1) == 0)
3231 pre_shift = floor_log2 (d & -d);
3232 mh = choose_multiplier (d >> pre_shift, size,
3234 &ml, &post_shift, &dummy);
3245 if (post_shift - 1 >= BITS_PER_WORD)
3248 extra_cost = (shift_cost[post_shift - 1]
3249 + shift_cost[1] + 2 * add_cost);
3250 t1 = expand_mult_highpart (compute_mode, op0, ml,
3252 max_cost - extra_cost);
3255 t2 = force_operand (gen_rtx_MINUS (compute_mode,
3258 t3 = expand_shift (RSHIFT_EXPR, compute_mode, t2,
3259 build_int_2 (1, 0), NULL_RTX,1);
3260 t4 = force_operand (gen_rtx_PLUS (compute_mode,
3264 = expand_shift (RSHIFT_EXPR, compute_mode, t4,
3265 build_int_2 (post_shift - 1, 0),
3272 if (pre_shift >= BITS_PER_WORD
3273 || post_shift >= BITS_PER_WORD)
3276 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3277 build_int_2 (pre_shift, 0),
3279 extra_cost = (shift_cost[pre_shift]
3280 + shift_cost[post_shift]);
3281 t2 = expand_mult_highpart (compute_mode, t1, ml,
3283 max_cost - extra_cost);
3287 = expand_shift (RSHIFT_EXPR, compute_mode, t2,
3288 build_int_2 (post_shift, 0),
3293 else /* Too wide mode to use tricky code */
3296 insn = get_last_insn ();
3298 && (set = single_set (insn)) != 0
3299 && SET_DEST (set) == quotient)
3300 set_unique_reg_note (insn,
3302 gen_rtx_UDIV (compute_mode, op0, op1));
3304 else /* TRUNC_DIV, signed */
3306 unsigned HOST_WIDE_INT ml;
3307 int lgup, post_shift;
3308 HOST_WIDE_INT d = INTVAL (op1);
3309 unsigned HOST_WIDE_INT abs_d = d >= 0 ? d : -d;
3311 /* n rem d = n rem -d */
3312 if (rem_flag && d < 0)
3315 op1 = GEN_INT (trunc_int_for_mode (abs_d, compute_mode));
3321 quotient = expand_unop (compute_mode, neg_optab, op0,
3323 else if (abs_d == (unsigned HOST_WIDE_INT) 1 << (size - 1))
3325 /* This case is not handled correctly below. */
3326 quotient = emit_store_flag (tquotient, EQ, op0, op1,
3327 compute_mode, 1, 1);
3331 else if (EXACT_POWER_OF_2_OR_ZERO_P (d)
3332 && (rem_flag ? smod_pow2_cheap : sdiv_pow2_cheap))
3334 else if (EXACT_POWER_OF_2_OR_ZERO_P (abs_d))
3336 lgup = floor_log2 (abs_d);
3337 if (BRANCH_COST < 1 || (abs_d != 2 && BRANCH_COST < 3))
3339 rtx label = gen_label_rtx ();
3342 t1 = copy_to_mode_reg (compute_mode, op0);
3343 do_cmp_and_jump (t1, const0_rtx, GE,
3344 compute_mode, label);
3345 expand_inc (t1, GEN_INT (trunc_int_for_mode
3346 (abs_d - 1, compute_mode)));
3348 quotient = expand_shift (RSHIFT_EXPR, compute_mode, t1,
3349 build_int_2 (lgup, 0),
3355 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3356 build_int_2 (size - 1, 0),
3358 t2 = expand_shift (RSHIFT_EXPR, compute_mode, t1,
3359 build_int_2 (size - lgup, 0),
3361 t3 = force_operand (gen_rtx_PLUS (compute_mode,
3364 quotient = expand_shift (RSHIFT_EXPR, compute_mode, t3,
3365 build_int_2 (lgup, 0),
3369 /* We have computed OP0 / abs(OP1). If OP1 is negative, negate
3373 insn = get_last_insn ();
3375 && (set = single_set (insn)) != 0
3376 && SET_DEST (set) == quotient
3377 && abs_d < ((unsigned HOST_WIDE_INT) 1
3378 << (HOST_BITS_PER_WIDE_INT - 1)))
3379 set_unique_reg_note (insn,
3381 gen_rtx_DIV (compute_mode,
3388 quotient = expand_unop (compute_mode, neg_optab,
3389 quotient, quotient, 0);
3392 else if (size <= HOST_BITS_PER_WIDE_INT)
3394 choose_multiplier (abs_d, size, size - 1,
3395 &ml, &post_shift, &lgup);
3396 if (ml < (unsigned HOST_WIDE_INT) 1 << (size - 1))
3400 if (post_shift >= BITS_PER_WORD
3401 || size - 1 >= BITS_PER_WORD)
3404 extra_cost = (shift_cost[post_shift]
3405 + shift_cost[size - 1] + add_cost);
3406 t1 = expand_mult_highpart (compute_mode, op0, ml,
3408 max_cost - extra_cost);
3411 t2 = expand_shift (RSHIFT_EXPR, compute_mode, t1,
3412 build_int_2 (post_shift, 0), NULL_RTX, 0);
3413 t3 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3414 build_int_2 (size - 1, 0), NULL_RTX, 0);
3417 = force_operand (gen_rtx_MINUS (compute_mode,
3422 = force_operand (gen_rtx_MINUS (compute_mode,
3430 if (post_shift >= BITS_PER_WORD
3431 || size - 1 >= BITS_PER_WORD)
3434 ml |= (~(unsigned HOST_WIDE_INT) 0) << (size - 1);
3435 extra_cost = (shift_cost[post_shift]
3436 + shift_cost[size - 1] + 2 * add_cost);
3437 t1 = expand_mult_highpart (compute_mode, op0, ml,
3439 max_cost - extra_cost);
3442 t2 = force_operand (gen_rtx_PLUS (compute_mode,
3445 t3 = expand_shift (RSHIFT_EXPR, compute_mode, t2,
3446 build_int_2 (post_shift, 0),
3448 t4 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3449 build_int_2 (size - 1, 0),
3453 = force_operand (gen_rtx_MINUS (compute_mode,
3458 = force_operand (gen_rtx_MINUS (compute_mode,
3463 else /* Too wide mode to use tricky code */
3466 insn = get_last_insn ();
3468 && (set = single_set (insn)) != 0
3469 && SET_DEST (set) == quotient)
3470 set_unique_reg_note (insn,
3472 gen_rtx_DIV (compute_mode, op0, op1));
3477 delete_insns_since (last);
3480 case FLOOR_DIV_EXPR:
3481 case FLOOR_MOD_EXPR:
3482 /* We will come here only for signed operations. */
3483 if (op1_is_constant && HOST_BITS_PER_WIDE_INT >= size)
3485 unsigned HOST_WIDE_INT mh, ml;
3486 int pre_shift, lgup, post_shift;
3487 HOST_WIDE_INT d = INTVAL (op1);
3491 /* We could just as easily deal with negative constants here,
3492 but it does not seem worth the trouble for GCC 2.6. */
3493 if (EXACT_POWER_OF_2_OR_ZERO_P (d))
3495 pre_shift = floor_log2 (d);
3498 remainder = expand_binop (compute_mode, and_optab, op0,
3499 GEN_INT (((HOST_WIDE_INT) 1 << pre_shift) - 1),
3500 remainder, 0, OPTAB_LIB_WIDEN);
3502 return gen_lowpart (mode, remainder);
3504 quotient = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3505 build_int_2 (pre_shift, 0),
3512 mh = choose_multiplier (d, size, size - 1,
3513 &ml, &post_shift, &lgup);
3517 if (post_shift < BITS_PER_WORD
3518 && size - 1 < BITS_PER_WORD)
3520 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3521 build_int_2 (size - 1, 0),
3523 t2 = expand_binop (compute_mode, xor_optab, op0, t1,
3524 NULL_RTX, 0, OPTAB_WIDEN);
3525 extra_cost = (shift_cost[post_shift]
3526 + shift_cost[size - 1] + 2 * add_cost);
3527 t3 = expand_mult_highpart (compute_mode, t2, ml,
3529 max_cost - extra_cost);
3532 t4 = expand_shift (RSHIFT_EXPR, compute_mode, t3,
3533 build_int_2 (post_shift, 0),
3535 quotient = expand_binop (compute_mode, xor_optab,
3536 t4, t1, tquotient, 0,
3544 rtx nsign, t1, t2, t3, t4;
3545 t1 = force_operand (gen_rtx_PLUS (compute_mode,
3546 op0, constm1_rtx), NULL_RTX);
3547 t2 = expand_binop (compute_mode, ior_optab, op0, t1, NULL_RTX,
3549 nsign = expand_shift (RSHIFT_EXPR, compute_mode, t2,
3550 build_int_2 (size - 1, 0), NULL_RTX, 0);
3551 t3 = force_operand (gen_rtx_MINUS (compute_mode, t1, nsign),
3553 t4 = expand_divmod (0, TRUNC_DIV_EXPR, compute_mode, t3, op1,
3558 t5 = expand_unop (compute_mode, one_cmpl_optab, nsign,
3560 quotient = force_operand (gen_rtx_PLUS (compute_mode,
3569 delete_insns_since (last);
3571 /* Try using an instruction that produces both the quotient and
3572 remainder, using truncation. We can easily compensate the quotient
3573 or remainder to get floor rounding, once we have the remainder.
3574 Notice that we compute also the final remainder value here,
3575 and return the result right away. */
3576 if (target == 0 || GET_MODE (target) != compute_mode)
3577 target = gen_reg_rtx (compute_mode);
3582 = GET_CODE (target) == REG ? target : gen_reg_rtx (compute_mode);
3583 quotient = gen_reg_rtx (compute_mode);
3588 = GET_CODE (target) == REG ? target : gen_reg_rtx (compute_mode);
3589 remainder = gen_reg_rtx (compute_mode);
3592 if (expand_twoval_binop (sdivmod_optab, op0, op1,
3593 quotient, remainder, 0))
3595 /* This could be computed with a branch-less sequence.
3596 Save that for later. */
3598 rtx label = gen_label_rtx ();
3599 do_cmp_and_jump (remainder, const0_rtx, EQ, compute_mode, label);
3600 tem = expand_binop (compute_mode, xor_optab, op0, op1,
3601 NULL_RTX, 0, OPTAB_WIDEN);
3602 do_cmp_and_jump (tem, const0_rtx, GE, compute_mode, label);
3603 expand_dec (quotient, const1_rtx);
3604 expand_inc (remainder, op1);
3606 return gen_lowpart (mode, rem_flag ? remainder : quotient);
3609 /* No luck with division elimination or divmod. Have to do it
3610 by conditionally adjusting op0 *and* the result. */
3612 rtx label1, label2, label3, label4, label5;
3616 quotient = gen_reg_rtx (compute_mode);
3617 adjusted_op0 = copy_to_mode_reg (compute_mode, op0);
3618 label1 = gen_label_rtx ();
3619 label2 = gen_label_rtx ();
3620 label3 = gen_label_rtx ();
3621 label4 = gen_label_rtx ();
3622 label5 = gen_label_rtx ();
3623 do_cmp_and_jump (op1, const0_rtx, LT, compute_mode, label2);
3624 do_cmp_and_jump (adjusted_op0, const0_rtx, LT, compute_mode, label1);
3625 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
3626 quotient, 0, OPTAB_LIB_WIDEN);
3627 if (tem != quotient)
3628 emit_move_insn (quotient, tem);
3629 emit_jump_insn (gen_jump (label5));
3631 emit_label (label1);
3632 expand_inc (adjusted_op0, const1_rtx);
3633 emit_jump_insn (gen_jump (label4));
3635 emit_label (label2);
3636 do_cmp_and_jump (adjusted_op0, const0_rtx, GT, compute_mode, label3);
3637 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
3638 quotient, 0, OPTAB_LIB_WIDEN);
3639 if (tem != quotient)
3640 emit_move_insn (quotient, tem);
3641 emit_jump_insn (gen_jump (label5));
3643 emit_label (label3);
3644 expand_dec (adjusted_op0, const1_rtx);
3645 emit_label (label4);
3646 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
3647 quotient, 0, OPTAB_LIB_WIDEN);
3648 if (tem != quotient)
3649 emit_move_insn (quotient, tem);
3650 expand_dec (quotient, const1_rtx);
3651 emit_label (label5);
3659 if (op1_is_constant && EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1)))
3662 unsigned HOST_WIDE_INT d = INTVAL (op1);
3663 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3664 build_int_2 (floor_log2 (d), 0),
3666 t2 = expand_binop (compute_mode, and_optab, op0,
3668 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3669 t3 = gen_reg_rtx (compute_mode);
3670 t3 = emit_store_flag (t3, NE, t2, const0_rtx,
3671 compute_mode, 1, 1);
3675 lab = gen_label_rtx ();
3676 do_cmp_and_jump (t2, const0_rtx, EQ, compute_mode, lab);
3677 expand_inc (t1, const1_rtx);
3682 quotient = force_operand (gen_rtx_PLUS (compute_mode,
3688 /* Try using an instruction that produces both the quotient and
3689 remainder, using truncation. We can easily compensate the
3690 quotient or remainder to get ceiling rounding, once we have the
3691 remainder. Notice that we compute also the final remainder
3692 value here, and return the result right away. */
3693 if (target == 0 || GET_MODE (target) != compute_mode)
3694 target = gen_reg_rtx (compute_mode);
3698 remainder = (GET_CODE (target) == REG
3699 ? target : gen_reg_rtx (compute_mode));
3700 quotient = gen_reg_rtx (compute_mode);
3704 quotient = (GET_CODE (target) == REG
3705 ? target : gen_reg_rtx (compute_mode));
3706 remainder = gen_reg_rtx (compute_mode);
3709 if (expand_twoval_binop (udivmod_optab, op0, op1, quotient,
3712 /* This could be computed with a branch-less sequence.
3713 Save that for later. */
3714 rtx label = gen_label_rtx ();
3715 do_cmp_and_jump (remainder, const0_rtx, EQ,
3716 compute_mode, label);
3717 expand_inc (quotient, const1_rtx);
3718 expand_dec (remainder, op1);
3720 return gen_lowpart (mode, rem_flag ? remainder : quotient);
3723 /* No luck with division elimination or divmod. Have to do it
3724 by conditionally adjusting op0 *and* the result. */
3727 rtx adjusted_op0, tem;
3729 quotient = gen_reg_rtx (compute_mode);
3730 adjusted_op0 = copy_to_mode_reg (compute_mode, op0);
3731 label1 = gen_label_rtx ();
3732 label2 = gen_label_rtx ();
3733 do_cmp_and_jump (adjusted_op0, const0_rtx, NE,
3734 compute_mode, label1);
3735 emit_move_insn (quotient, const0_rtx);
3736 emit_jump_insn (gen_jump (label2));
3738 emit_label (label1);
3739 expand_dec (adjusted_op0, const1_rtx);
3740 tem = expand_binop (compute_mode, udiv_optab, adjusted_op0, op1,
3741 quotient, 1, OPTAB_LIB_WIDEN);
3742 if (tem != quotient)
3743 emit_move_insn (quotient, tem);
3744 expand_inc (quotient, const1_rtx);
3745 emit_label (label2);
3750 if (op1_is_constant && EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1))
3751 && INTVAL (op1) >= 0)
3753 /* This is extremely similar to the code for the unsigned case
3754 above. For 2.7 we should merge these variants, but for
3755 2.6.1 I don't want to touch the code for unsigned since that
3756 get used in C. The signed case will only be used by other
3760 unsigned HOST_WIDE_INT d = INTVAL (op1);
3761 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3762 build_int_2 (floor_log2 (d), 0),
3764 t2 = expand_binop (compute_mode, and_optab, op0,
3766 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3767 t3 = gen_reg_rtx (compute_mode);
3768 t3 = emit_store_flag (t3, NE, t2, const0_rtx,
3769 compute_mode, 1, 1);
3773 lab = gen_label_rtx ();
3774 do_cmp_and_jump (t2, const0_rtx, EQ, compute_mode, lab);
3775 expand_inc (t1, const1_rtx);
3780 quotient = force_operand (gen_rtx_PLUS (compute_mode,
3786 /* Try using an instruction that produces both the quotient and
3787 remainder, using truncation. We can easily compensate the
3788 quotient or remainder to get ceiling rounding, once we have the
3789 remainder. Notice that we compute also the final remainder
3790 value here, and return the result right away. */
3791 if (target == 0 || GET_MODE (target) != compute_mode)
3792 target = gen_reg_rtx (compute_mode);
3795 remainder= (GET_CODE (target) == REG
3796 ? target : gen_reg_rtx (compute_mode));
3797 quotient = gen_reg_rtx (compute_mode);
3801 quotient = (GET_CODE (target) == REG
3802 ? target : gen_reg_rtx (compute_mode));
3803 remainder = gen_reg_rtx (compute_mode);
3806 if (expand_twoval_binop (sdivmod_optab, op0, op1, quotient,
3809 /* This could be computed with a branch-less sequence.
3810 Save that for later. */
3812 rtx label = gen_label_rtx ();
3813 do_cmp_and_jump (remainder, const0_rtx, EQ,
3814 compute_mode, label);
3815 tem = expand_binop (compute_mode, xor_optab, op0, op1,
3816 NULL_RTX, 0, OPTAB_WIDEN);
3817 do_cmp_and_jump (tem, const0_rtx, LT, compute_mode, label);
3818 expand_inc (quotient, const1_rtx);
3819 expand_dec (remainder, op1);
3821 return gen_lowpart (mode, rem_flag ? remainder : quotient);
3824 /* No luck with division elimination or divmod. Have to do it
3825 by conditionally adjusting op0 *and* the result. */
3827 rtx label1, label2, label3, label4, label5;
3831 quotient = gen_reg_rtx (compute_mode);
3832 adjusted_op0 = copy_to_mode_reg (compute_mode, op0);
3833 label1 = gen_label_rtx ();
3834 label2 = gen_label_rtx ();
3835 label3 = gen_label_rtx ();
3836 label4 = gen_label_rtx ();
3837 label5 = gen_label_rtx ();
3838 do_cmp_and_jump (op1, const0_rtx, LT, compute_mode, label2);
3839 do_cmp_and_jump (adjusted_op0, const0_rtx, GT,
3840 compute_mode, label1);
3841 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
3842 quotient, 0, OPTAB_LIB_WIDEN);
3843 if (tem != quotient)
3844 emit_move_insn (quotient, tem);
3845 emit_jump_insn (gen_jump (label5));
3847 emit_label (label1);
3848 expand_dec (adjusted_op0, const1_rtx);
3849 emit_jump_insn (gen_jump (label4));
3851 emit_label (label2);
3852 do_cmp_and_jump (adjusted_op0, const0_rtx, LT,
3853 compute_mode, label3);
3854 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
3855 quotient, 0, OPTAB_LIB_WIDEN);
3856 if (tem != quotient)
3857 emit_move_insn (quotient, tem);
3858 emit_jump_insn (gen_jump (label5));
3860 emit_label (label3);
3861 expand_inc (adjusted_op0, const1_rtx);
3862 emit_label (label4);
3863 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
3864 quotient, 0, OPTAB_LIB_WIDEN);
3865 if (tem != quotient)
3866 emit_move_insn (quotient, tem);
3867 expand_inc (quotient, const1_rtx);
3868 emit_label (label5);
3873 case EXACT_DIV_EXPR:
3874 if (op1_is_constant && HOST_BITS_PER_WIDE_INT >= size)
3876 HOST_WIDE_INT d = INTVAL (op1);
3877 unsigned HOST_WIDE_INT ml;
3881 pre_shift = floor_log2 (d & -d);
3882 ml = invert_mod2n (d >> pre_shift, size);
3883 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3884 build_int_2 (pre_shift, 0), NULL_RTX, unsignedp);
3885 quotient = expand_mult (compute_mode, t1,
3886 GEN_INT (trunc_int_for_mode
3887 (ml, compute_mode)),
3890 insn = get_last_insn ();
3891 set_unique_reg_note (insn,
3893 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
3899 case ROUND_DIV_EXPR:
3900 case ROUND_MOD_EXPR:
3905 label = gen_label_rtx ();
3906 quotient = gen_reg_rtx (compute_mode);
3907 remainder = gen_reg_rtx (compute_mode);
3908 if (expand_twoval_binop (udivmod_optab, op0, op1, quotient, remainder, 1) == 0)
3911 quotient = expand_binop (compute_mode, udiv_optab, op0, op1,
3912 quotient, 1, OPTAB_LIB_WIDEN);
3913 tem = expand_mult (compute_mode, quotient, op1, NULL_RTX, 1);
3914 remainder = expand_binop (compute_mode, sub_optab, op0, tem,
3915 remainder, 1, OPTAB_LIB_WIDEN);
3917 tem = plus_constant (op1, -1);
3918 tem = expand_shift (RSHIFT_EXPR, compute_mode, tem,
3919 build_int_2 (1, 0), NULL_RTX, 1);
3920 do_cmp_and_jump (remainder, tem, LEU, compute_mode, label);
3921 expand_inc (quotient, const1_rtx);
3922 expand_dec (remainder, op1);
3927 rtx abs_rem, abs_op1, tem, mask;
3929 label = gen_label_rtx ();
3930 quotient = gen_reg_rtx (compute_mode);
3931 remainder = gen_reg_rtx (compute_mode);
3932 if (expand_twoval_binop (sdivmod_optab, op0, op1, quotient, remainder, 0) == 0)
3935 quotient = expand_binop (compute_mode, sdiv_optab, op0, op1,
3936 quotient, 0, OPTAB_LIB_WIDEN);
3937 tem = expand_mult (compute_mode, quotient, op1, NULL_RTX, 0);
3938 remainder = expand_binop (compute_mode, sub_optab, op0, tem,
3939 remainder, 0, OPTAB_LIB_WIDEN);
3941 abs_rem = expand_abs (compute_mode, remainder, NULL_RTX, 1, 0);
3942 abs_op1 = expand_abs (compute_mode, op1, NULL_RTX, 1, 0);
3943 tem = expand_shift (LSHIFT_EXPR, compute_mode, abs_rem,
3944 build_int_2 (1, 0), NULL_RTX, 1);
3945 do_cmp_and_jump (tem, abs_op1, LTU, compute_mode, label);
3946 tem = expand_binop (compute_mode, xor_optab, op0, op1,
3947 NULL_RTX, 0, OPTAB_WIDEN);
3948 mask = expand_shift (RSHIFT_EXPR, compute_mode, tem,
3949 build_int_2 (size - 1, 0), NULL_RTX, 0);
3950 tem = expand_binop (compute_mode, xor_optab, mask, const1_rtx,
3951 NULL_RTX, 0, OPTAB_WIDEN);
3952 tem = expand_binop (compute_mode, sub_optab, tem, mask,
3953 NULL_RTX, 0, OPTAB_WIDEN);
3954 expand_inc (quotient, tem);
3955 tem = expand_binop (compute_mode, xor_optab, mask, op1,
3956 NULL_RTX, 0, OPTAB_WIDEN);
3957 tem = expand_binop (compute_mode, sub_optab, tem, mask,
3958 NULL_RTX, 0, OPTAB_WIDEN);
3959 expand_dec (remainder, tem);
3962 return gen_lowpart (mode, rem_flag ? remainder : quotient);
3970 if (target && GET_MODE (target) != compute_mode)
3975 /* Try to produce the remainder without producing the quotient.
3976 If we seem to have a divmod patten that does not require widening,
3977 don't try windening here. We should really have an WIDEN argument
3978 to expand_twoval_binop, since what we'd really like to do here is
3979 1) try a mod insn in compute_mode
3980 2) try a divmod insn in compute_mode
3981 3) try a div insn in compute_mode and multiply-subtract to get
3983 4) try the same things with widening allowed. */
3985 = sign_expand_binop (compute_mode, umod_optab, smod_optab,
3988 ((optab2->handlers[(int) compute_mode].insn_code
3989 != CODE_FOR_nothing)
3990 ? OPTAB_DIRECT : OPTAB_WIDEN));
3993 /* No luck there. Can we do remainder and divide at once
3994 without a library call? */
3995 remainder = gen_reg_rtx (compute_mode);
3996 if (! expand_twoval_binop ((unsignedp
4000 NULL_RTX, remainder, unsignedp))
4005 return gen_lowpart (mode, remainder);
4008 /* Produce the quotient. Try a quotient insn, but not a library call.
4009 If we have a divmod in this mode, use it in preference to widening
4010 the div (for this test we assume it will not fail). Note that optab2
4011 is set to the one of the two optabs that the call below will use. */
4013 = sign_expand_binop (compute_mode, udiv_optab, sdiv_optab,
4014 op0, op1, rem_flag ? NULL_RTX : target,
4016 ((optab2->handlers[(int) compute_mode].insn_code
4017 != CODE_FOR_nothing)
4018 ? OPTAB_DIRECT : OPTAB_WIDEN));
4022 /* No luck there. Try a quotient-and-remainder insn,
4023 keeping the quotient alone. */
4024 quotient = gen_reg_rtx (compute_mode);
4025 if (! expand_twoval_binop (unsignedp ? udivmod_optab : sdivmod_optab,
4027 quotient, NULL_RTX, unsignedp))
4031 /* Still no luck. If we are not computing the remainder,
4032 use a library call for the quotient. */
4033 quotient = sign_expand_binop (compute_mode,
4034 udiv_optab, sdiv_optab,
4036 unsignedp, OPTAB_LIB_WIDEN);
4043 if (target && GET_MODE (target) != compute_mode)
4047 /* No divide instruction either. Use library for remainder. */
4048 remainder = sign_expand_binop (compute_mode, umod_optab, smod_optab,
4050 unsignedp, OPTAB_LIB_WIDEN);
4053 /* We divided. Now finish doing X - Y * (X / Y). */
4054 remainder = expand_mult (compute_mode, quotient, op1,
4055 NULL_RTX, unsignedp);
4056 remainder = expand_binop (compute_mode, sub_optab, op0,
4057 remainder, target, unsignedp,
4062 return gen_lowpart (mode, rem_flag ? remainder : quotient);
4065 /* Return a tree node with data type TYPE, describing the value of X.
4066 Usually this is an RTL_EXPR, if there is no obvious better choice.
4067 X may be an expression, however we only support those expressions
4068 generated by loop.c. */
4077 switch (GET_CODE (x))
4080 t = build_int_2 (INTVAL (x),
4081 (TREE_UNSIGNED (type)
4082 && (GET_MODE_BITSIZE (TYPE_MODE (type)) < HOST_BITS_PER_WIDE_INT))
4083 || INTVAL (x) >= 0 ? 0 : -1);
4084 TREE_TYPE (t) = type;
4088 if (GET_MODE (x) == VOIDmode)
4090 t = build_int_2 (CONST_DOUBLE_LOW (x), CONST_DOUBLE_HIGH (x));
4091 TREE_TYPE (t) = type;
4097 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
4098 t = build_real (type, d);
4104 return fold (build (PLUS_EXPR, type, make_tree (type, XEXP (x, 0)),
4105 make_tree (type, XEXP (x, 1))));
4108 return fold (build (MINUS_EXPR, type, make_tree (type, XEXP (x, 0)),
4109 make_tree (type, XEXP (x, 1))));
4112 return fold (build1 (NEGATE_EXPR, type, make_tree (type, XEXP (x, 0))));
4115 return fold (build (MULT_EXPR, type, make_tree (type, XEXP (x, 0)),
4116 make_tree (type, XEXP (x, 1))));
4119 return fold (build (LSHIFT_EXPR, type, make_tree (type, XEXP (x, 0)),
4120 make_tree (type, XEXP (x, 1))));
4123 return fold (convert (type,
4124 build (RSHIFT_EXPR, unsigned_type (type),
4125 make_tree (unsigned_type (type),
4127 make_tree (type, XEXP (x, 1)))));
4130 return fold (convert (type,
4131 build (RSHIFT_EXPR, signed_type (type),
4132 make_tree (signed_type (type), XEXP (x, 0)),
4133 make_tree (type, XEXP (x, 1)))));
4136 if (TREE_CODE (type) != REAL_TYPE)
4137 t = signed_type (type);
4141 return fold (convert (type,
4142 build (TRUNC_DIV_EXPR, t,
4143 make_tree (t, XEXP (x, 0)),
4144 make_tree (t, XEXP (x, 1)))));
4146 t = unsigned_type (type);
4147 return fold (convert (type,
4148 build (TRUNC_DIV_EXPR, t,
4149 make_tree (t, XEXP (x, 0)),
4150 make_tree (t, XEXP (x, 1)))));
4152 t = make_node (RTL_EXPR);
4153 TREE_TYPE (t) = type;
4155 #ifdef POINTERS_EXTEND_UNSIGNED
4156 /* If TYPE is a POINTER_TYPE, X might be Pmode with TYPE_MODE being
4157 ptr_mode. So convert. */
4158 if (POINTER_TYPE_P (type) && GET_MODE (x) != TYPE_MODE (type))
4159 x = convert_memory_address (TYPE_MODE (type), x);
4162 RTL_EXPR_RTL (t) = x;
4163 /* There are no insns to be output
4164 when this rtl_expr is used. */
4165 RTL_EXPR_SEQUENCE (t) = 0;
4170 /* Return an rtx representing the value of X * MULT + ADD.
4171 TARGET is a suggestion for where to store the result (an rtx).
4172 MODE is the machine mode for the computation.
4173 X and MULT must have mode MODE. ADD may have a different mode.
4174 So can X (defaults to same as MODE).
4175 UNSIGNEDP is non-zero to do unsigned multiplication.
4176 This may emit insns. */
4179 expand_mult_add (x, target, mult, add, mode, unsignedp)
4180 rtx x, target, mult, add;
4181 enum machine_mode mode;
4184 tree type = type_for_mode (mode, unsignedp);
4185 tree add_type = (GET_MODE (add) == VOIDmode
4186 ? type : type_for_mode (GET_MODE (add), unsignedp));
4187 tree result = fold (build (PLUS_EXPR, type,
4188 fold (build (MULT_EXPR, type,
4189 make_tree (type, x),
4190 make_tree (type, mult))),
4191 make_tree (add_type, add)));
4193 return expand_expr (result, target, VOIDmode, 0);
4196 /* Compute the logical-and of OP0 and OP1, storing it in TARGET
4197 and returning TARGET.
4199 If TARGET is 0, a pseudo-register or constant is returned. */
4202 expand_and (op0, op1, target)
4203 rtx op0, op1, target;
4205 enum machine_mode mode = VOIDmode;
4208 if (GET_MODE (op0) != VOIDmode)
4209 mode = GET_MODE (op0);
4210 else if (GET_MODE (op1) != VOIDmode)
4211 mode = GET_MODE (op1);
4213 if (mode != VOIDmode)
4214 tem = expand_binop (mode, and_optab, op0, op1, target, 0, OPTAB_LIB_WIDEN);
4215 else if (GET_CODE (op0) == CONST_INT && GET_CODE (op1) == CONST_INT)
4216 tem = GEN_INT (INTVAL (op0) & INTVAL (op1));
4222 else if (tem != target)
4223 emit_move_insn (target, tem);
4227 /* Emit a store-flags instruction for comparison CODE on OP0 and OP1
4228 and storing in TARGET. Normally return TARGET.
4229 Return 0 if that cannot be done.
4231 MODE is the mode to use for OP0 and OP1 should they be CONST_INTs. If
4232 it is VOIDmode, they cannot both be CONST_INT.
4234 UNSIGNEDP is for the case where we have to widen the operands
4235 to perform the operation. It says to use zero-extension.
4237 NORMALIZEP is 1 if we should convert the result to be either zero
4238 or one. Normalize is -1 if we should convert the result to be
4239 either zero or -1. If NORMALIZEP is zero, the result will be left
4240 "raw" out of the scc insn. */
4243 emit_store_flag (target, code, op0, op1, mode, unsignedp, normalizep)
4247 enum machine_mode mode;
4252 enum insn_code icode;
4253 enum machine_mode compare_mode;
4254 enum machine_mode target_mode = GET_MODE (target);
4256 rtx last = get_last_insn ();
4257 rtx pattern, comparison;
4260 code = unsigned_condition (code);
4262 /* If one operand is constant, make it the second one. Only do this
4263 if the other operand is not constant as well. */
4265 if (swap_commutative_operands_p (op0, op1))
4270 code = swap_condition (code);
4273 if (mode == VOIDmode)
4274 mode = GET_MODE (op0);
4276 /* For some comparisons with 1 and -1, we can convert this to
4277 comparisons with zero. This will often produce more opportunities for
4278 store-flag insns. */
4283 if (op1 == const1_rtx)
4284 op1 = const0_rtx, code = LE;
4287 if (op1 == constm1_rtx)
4288 op1 = const0_rtx, code = LT;
4291 if (op1 == const1_rtx)
4292 op1 = const0_rtx, code = GT;
4295 if (op1 == constm1_rtx)
4296 op1 = const0_rtx, code = GE;
4299 if (op1 == const1_rtx)
4300 op1 = const0_rtx, code = NE;
4303 if (op1 == const1_rtx)
4304 op1 = const0_rtx, code = EQ;
4310 /* If we are comparing a double-word integer with zero, we can convert
4311 the comparison into one involving a single word. */
4312 if (GET_MODE_BITSIZE (mode) == BITS_PER_WORD * 2
4313 && GET_MODE_CLASS (mode) == MODE_INT
4314 && op1 == const0_rtx)
4316 if (code == EQ || code == NE)
4318 /* Do a logical OR of the two words and compare the result. */
4319 rtx op0h = gen_highpart (word_mode, op0);
4320 rtx op0l = gen_lowpart (word_mode, op0);
4321 rtx op0both = expand_binop (word_mode, ior_optab, op0h, op0l,
4322 NULL_RTX, unsignedp, OPTAB_DIRECT);
4324 return emit_store_flag (target, code, op0both, op1, word_mode,
4325 unsignedp, normalizep);
4327 else if (code == LT || code == GE)
4328 /* If testing the sign bit, can just test on high word. */
4329 return emit_store_flag (target, code, gen_highpart (word_mode, op0),
4330 op1, word_mode, unsignedp, normalizep);
4333 /* From now on, we won't change CODE, so set ICODE now. */
4334 icode = setcc_gen_code[(int) code];
4336 /* If this is A < 0 or A >= 0, we can do this by taking the ones
4337 complement of A (for GE) and shifting the sign bit to the low bit. */
4338 if (op1 == const0_rtx && (code == LT || code == GE)
4339 && GET_MODE_CLASS (mode) == MODE_INT
4340 && (normalizep || STORE_FLAG_VALUE == 1
4341 || (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4342 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4343 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1)))))
4347 /* If the result is to be wider than OP0, it is best to convert it
4348 first. If it is to be narrower, it is *incorrect* to convert it
4350 if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (mode))
4352 op0 = protect_from_queue (op0, 0);
4353 op0 = convert_modes (target_mode, mode, op0, 0);
4357 if (target_mode != mode)
4361 op0 = expand_unop (mode, one_cmpl_optab, op0,
4362 ((STORE_FLAG_VALUE == 1 || normalizep)
4363 ? 0 : subtarget), 0);
4365 if (STORE_FLAG_VALUE == 1 || normalizep)
4366 /* If we are supposed to produce a 0/1 value, we want to do
4367 a logical shift from the sign bit to the low-order bit; for
4368 a -1/0 value, we do an arithmetic shift. */
4369 op0 = expand_shift (RSHIFT_EXPR, mode, op0,
4370 size_int (GET_MODE_BITSIZE (mode) - 1),
4371 subtarget, normalizep != -1);
4373 if (mode != target_mode)
4374 op0 = convert_modes (target_mode, mode, op0, 0);
4379 if (icode != CODE_FOR_nothing)
4381 insn_operand_predicate_fn pred;
4383 /* We think we may be able to do this with a scc insn. Emit the
4384 comparison and then the scc insn.
4386 compare_from_rtx may call emit_queue, which would be deleted below
4387 if the scc insn fails. So call it ourselves before setting LAST.
4388 Likewise for do_pending_stack_adjust. */
4391 do_pending_stack_adjust ();
4392 last = get_last_insn ();
4395 = compare_from_rtx (op0, op1, code, unsignedp, mode, NULL_RTX, 0);
4396 if (GET_CODE (comparison) == CONST_INT)
4397 return (comparison == const0_rtx ? const0_rtx
4398 : normalizep == 1 ? const1_rtx
4399 : normalizep == -1 ? constm1_rtx
4402 /* If the code of COMPARISON doesn't match CODE, something is
4403 wrong; we can no longer be sure that we have the operation.
4404 We could handle this case, but it should not happen. */
4406 if (GET_CODE (comparison) != code)
4409 /* Get a reference to the target in the proper mode for this insn. */
4410 compare_mode = insn_data[(int) icode].operand[0].mode;
4412 pred = insn_data[(int) icode].operand[0].predicate;
4413 if (preserve_subexpressions_p ()
4414 || ! (*pred) (subtarget, compare_mode))
4415 subtarget = gen_reg_rtx (compare_mode);
4417 pattern = GEN_FCN (icode) (subtarget);
4420 emit_insn (pattern);
4422 /* If we are converting to a wider mode, first convert to
4423 TARGET_MODE, then normalize. This produces better combining
4424 opportunities on machines that have a SIGN_EXTRACT when we are
4425 testing a single bit. This mostly benefits the 68k.
4427 If STORE_FLAG_VALUE does not have the sign bit set when
4428 interpreted in COMPARE_MODE, we can do this conversion as
4429 unsigned, which is usually more efficient. */
4430 if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (compare_mode))
4432 convert_move (target, subtarget,
4433 (GET_MODE_BITSIZE (compare_mode)
4434 <= HOST_BITS_PER_WIDE_INT)
4435 && 0 == (STORE_FLAG_VALUE
4436 & ((HOST_WIDE_INT) 1
4437 << (GET_MODE_BITSIZE (compare_mode) -1))));
4439 compare_mode = target_mode;
4444 /* If we want to keep subexpressions around, don't reuse our
4447 if (preserve_subexpressions_p ())
4450 /* Now normalize to the proper value in COMPARE_MODE. Sometimes
4451 we don't have to do anything. */
4452 if (normalizep == 0 || normalizep == STORE_FLAG_VALUE)
4454 /* STORE_FLAG_VALUE might be the most negative number, so write
4455 the comparison this way to avoid a compiler-time warning. */
4456 else if (- normalizep == STORE_FLAG_VALUE)
4457 op0 = expand_unop (compare_mode, neg_optab, op0, subtarget, 0);
4459 /* We don't want to use STORE_FLAG_VALUE < 0 below since this
4460 makes it hard to use a value of just the sign bit due to
4461 ANSI integer constant typing rules. */
4462 else if (GET_MODE_BITSIZE (compare_mode) <= HOST_BITS_PER_WIDE_INT
4463 && (STORE_FLAG_VALUE
4464 & ((HOST_WIDE_INT) 1
4465 << (GET_MODE_BITSIZE (compare_mode) - 1))))
4466 op0 = expand_shift (RSHIFT_EXPR, compare_mode, op0,
4467 size_int (GET_MODE_BITSIZE (compare_mode) - 1),
4468 subtarget, normalizep == 1);
4469 else if (STORE_FLAG_VALUE & 1)
4471 op0 = expand_and (op0, const1_rtx, subtarget);
4472 if (normalizep == -1)
4473 op0 = expand_unop (compare_mode, neg_optab, op0, op0, 0);
4478 /* If we were converting to a smaller mode, do the
4480 if (target_mode != compare_mode)
4482 convert_move (target, op0, 0);
4490 delete_insns_since (last);
4492 /* If expensive optimizations, use different pseudo registers for each
4493 insn, instead of reusing the same pseudo. This leads to better CSE,
4494 but slows down the compiler, since there are more pseudos */
4495 subtarget = (!flag_expensive_optimizations
4496 && (target_mode == mode)) ? target : NULL_RTX;
4498 /* If we reached here, we can't do this with a scc insn. However, there
4499 are some comparisons that can be done directly. For example, if
4500 this is an equality comparison of integers, we can try to exclusive-or
4501 (or subtract) the two operands and use a recursive call to try the
4502 comparison with zero. Don't do any of these cases if branches are
4506 && GET_MODE_CLASS (mode) == MODE_INT && (code == EQ || code == NE)
4507 && op1 != const0_rtx)
4509 tem = expand_binop (mode, xor_optab, op0, op1, subtarget, 1,
4513 tem = expand_binop (mode, sub_optab, op0, op1, subtarget, 1,
4516 tem = emit_store_flag (target, code, tem, const0_rtx,
4517 mode, unsignedp, normalizep);
4519 delete_insns_since (last);
4523 /* Some other cases we can do are EQ, NE, LE, and GT comparisons with
4524 the constant zero. Reject all other comparisons at this point. Only
4525 do LE and GT if branches are expensive since they are expensive on
4526 2-operand machines. */
4528 if (BRANCH_COST == 0
4529 || GET_MODE_CLASS (mode) != MODE_INT || op1 != const0_rtx
4530 || (code != EQ && code != NE
4531 && (BRANCH_COST <= 1 || (code != LE && code != GT))))
4534 /* See what we need to return. We can only return a 1, -1, or the
4537 if (normalizep == 0)
4539 if (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4540 normalizep = STORE_FLAG_VALUE;
4542 else if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4543 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4544 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1)))
4550 /* Try to put the result of the comparison in the sign bit. Assume we can't
4551 do the necessary operation below. */
4555 /* To see if A <= 0, compute (A | (A - 1)). A <= 0 iff that result has
4556 the sign bit set. */
4560 /* This is destructive, so SUBTARGET can't be OP0. */
4561 if (rtx_equal_p (subtarget, op0))
4564 tem = expand_binop (mode, sub_optab, op0, const1_rtx, subtarget, 0,
4567 tem = expand_binop (mode, ior_optab, op0, tem, subtarget, 0,
4571 /* To see if A > 0, compute (((signed) A) << BITS) - A, where BITS is the
4572 number of bits in the mode of OP0, minus one. */
4576 if (rtx_equal_p (subtarget, op0))
4579 tem = expand_shift (RSHIFT_EXPR, mode, op0,
4580 size_int (GET_MODE_BITSIZE (mode) - 1),
4582 tem = expand_binop (mode, sub_optab, tem, op0, subtarget, 0,
4586 if (code == EQ || code == NE)
4588 /* For EQ or NE, one way to do the comparison is to apply an operation
4589 that converts the operand into a positive number if it is non-zero
4590 or zero if it was originally zero. Then, for EQ, we subtract 1 and
4591 for NE we negate. This puts the result in the sign bit. Then we
4592 normalize with a shift, if needed.
4594 Two operations that can do the above actions are ABS and FFS, so try
4595 them. If that doesn't work, and MODE is smaller than a full word,
4596 we can use zero-extension to the wider mode (an unsigned conversion)
4597 as the operation. */
4599 /* Note that ABS doesn't yield a positive number for INT_MIN, but
4600 that is compensated by the subsequent overflow when subtracting
4603 if (abs_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
4604 tem = expand_unop (mode, abs_optab, op0, subtarget, 1);
4605 else if (ffs_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
4606 tem = expand_unop (mode, ffs_optab, op0, subtarget, 1);
4607 else if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
4609 op0 = protect_from_queue (op0, 0);
4610 tem = convert_modes (word_mode, mode, op0, 1);
4617 tem = expand_binop (mode, sub_optab, tem, const1_rtx, subtarget,
4620 tem = expand_unop (mode, neg_optab, tem, subtarget, 0);
4623 /* If we couldn't do it that way, for NE we can "or" the two's complement
4624 of the value with itself. For EQ, we take the one's complement of
4625 that "or", which is an extra insn, so we only handle EQ if branches
4628 if (tem == 0 && (code == NE || BRANCH_COST > 1))
4630 if (rtx_equal_p (subtarget, op0))
4633 tem = expand_unop (mode, neg_optab, op0, subtarget, 0);
4634 tem = expand_binop (mode, ior_optab, tem, op0, subtarget, 0,
4637 if (tem && code == EQ)
4638 tem = expand_unop (mode, one_cmpl_optab, tem, subtarget, 0);
4642 if (tem && normalizep)
4643 tem = expand_shift (RSHIFT_EXPR, mode, tem,
4644 size_int (GET_MODE_BITSIZE (mode) - 1),
4645 subtarget, normalizep == 1);
4649 if (GET_MODE (tem) != target_mode)
4651 convert_move (target, tem, 0);
4654 else if (!subtarget)
4656 emit_move_insn (target, tem);
4661 delete_insns_since (last);
4666 /* Like emit_store_flag, but always succeeds. */
4669 emit_store_flag_force (target, code, op0, op1, mode, unsignedp, normalizep)
4673 enum machine_mode mode;
4679 /* First see if emit_store_flag can do the job. */
4680 tem = emit_store_flag (target, code, op0, op1, mode, unsignedp, normalizep);
4684 if (normalizep == 0)
4687 /* If this failed, we have to do this with set/compare/jump/set code. */
4689 if (GET_CODE (target) != REG
4690 || reg_mentioned_p (target, op0) || reg_mentioned_p (target, op1))
4691 target = gen_reg_rtx (GET_MODE (target));
4693 emit_move_insn (target, const1_rtx);
4694 label = gen_label_rtx ();
4695 do_compare_rtx_and_jump (op0, op1, code, unsignedp, mode, NULL_RTX, 0,
4698 emit_move_insn (target, const0_rtx);
4704 /* Perform possibly multi-word comparison and conditional jump to LABEL
4705 if ARG1 OP ARG2 true where ARG1 and ARG2 are of mode MODE
4707 The algorithm is based on the code in expr.c:do_jump.
4709 Note that this does not perform a general comparison. Only variants
4710 generated within expmed.c are correctly handled, others abort (but could
4711 be handled if needed). */
4714 do_cmp_and_jump (arg1, arg2, op, mode, label)
4715 rtx arg1, arg2, label;
4717 enum machine_mode mode;
4719 /* If this mode is an integer too wide to compare properly,
4720 compare word by word. Rely on cse to optimize constant cases. */
4722 if (GET_MODE_CLASS (mode) == MODE_INT
4723 && ! can_compare_p (op, mode, ccp_jump))
4725 rtx label2 = gen_label_rtx ();
4730 do_jump_by_parts_greater_rtx (mode, 1, arg2, arg1, label2, label);
4734 do_jump_by_parts_greater_rtx (mode, 1, arg1, arg2, label, label2);
4738 do_jump_by_parts_greater_rtx (mode, 0, arg2, arg1, label2, label);
4742 do_jump_by_parts_greater_rtx (mode, 0, arg1, arg2, label2, label);
4746 do_jump_by_parts_greater_rtx (mode, 0, arg2, arg1, label, label2);
4749 /* do_jump_by_parts_equality_rtx compares with zero. Luckily
4750 that's the only equality operations we do */
4752 if (arg2 != const0_rtx || mode != GET_MODE(arg1))
4754 do_jump_by_parts_equality_rtx (arg1, label2, label);
4758 if (arg2 != const0_rtx || mode != GET_MODE(arg1))
4760 do_jump_by_parts_equality_rtx (arg1, label, label2);
4767 emit_label (label2);
4771 emit_cmp_and_jump_insns (arg1, arg2, op, NULL_RTX, mode, 0, 0, label);