1 /* Medium-level subroutines: convert bit-field store and extract
2 and shifts, multiplies and divides to rtl instructions.
3 Copyright (C) 1987, 1988, 1989, 1992 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
26 #include "insn-flags.h"
27 #include "insn-codes.h"
28 #include "insn-config.h"
33 static rtx extract_split_bit_field ();
34 static rtx extract_fixed_bit_field ();
35 static void store_split_bit_field ();
36 static void store_fixed_bit_field ();
37 static rtx mask_rtx ();
38 static rtx lshift_value ();
40 #define CEIL(x,y) (((x) + (y) - 1) / (y))
42 /* Non-zero means multiply instructions are cheaper than shifts. */
43 int mult_is_very_cheap;
45 /* Non-zero means divides or modulus operations are relatively cheap for
46 powers of two, so don't use branches; emit the operation instead.
47 Usually, this will mean that the MD file will emit non-branch
50 static int sdiv_pow2_cheap, smod_pow2_cheap;
52 /* Cost of various pieces of RTL. */
53 static int add_cost, shift_cost, mult_cost, negate_cost, lea_cost;
55 /* Max scale factor for scaled address in lea instruction. */
56 static int lea_max_mul;
61 char *free_point = (char *) oballoc (1);
62 /* This is "some random pseudo register" for purposes of calling recog
63 to see what insns exist. */
64 rtx reg = gen_rtx (REG, word_mode, FIRST_PSEUDO_REGISTER);
65 rtx pow2 = gen_rtx (CONST_INT, VOIDmode, 32);
69 add_cost = rtx_cost (gen_rtx (PLUS, word_mode, reg, reg), SET);
70 shift_cost = rtx_cost (gen_rtx (LSHIFT, word_mode, reg,
71 /* Using a constant gives better
72 estimate of typical costs.
73 1 or 2 might have quirks. */
74 gen_rtx (CONST_INT, VOIDmode, 3)), SET);
75 mult_cost = rtx_cost (gen_rtx (MULT, word_mode, reg, reg), SET);
76 negate_cost = rtx_cost (gen_rtx (NEG, word_mode, reg), SET);
78 /* 999999 is chosen to avoid any plausible faster special case. */
80 = (rtx_cost (gen_rtx (MULT, word_mode, reg,
81 gen_rtx (CONST_INT, VOIDmode, 999999)), SET)
82 < rtx_cost (gen_rtx (LSHIFT, word_mode, reg,
83 gen_rtx (CONST_INT, VOIDmode, 7)), SET));
86 = rtx_cost (gen_rtx (DIV, word_mode, reg, pow2), SET) <= 2 * add_cost;
88 = rtx_cost (gen_rtx (MOD, word_mode, reg, pow2), SET) <= 2 * add_cost;
93 lea = gen_rtx (SET, VOIDmode, reg,
94 gen_rtx (PLUS, word_mode,
95 gen_rtx (MULT, word_mode, reg,
96 gen_rtx (CONST_INT, VOIDmode, i)),
98 /* Using 0 as second argument is not quite right,
99 but what else is there to do? */
100 if (recog (lea, 0, &dummy) < 0)
103 lea_cost = rtx_cost (SET_SRC (lea), SET);
106 /* Free the objects we just allocated. */
110 /* Return an rtx representing minus the value of X.
111 MODE is the intended mode of the result,
112 useful if X is a CONST_INT. */
116 enum machine_mode mode;
119 if (GET_CODE (x) == CONST_INT)
121 int val = - INTVAL (x);
122 if (GET_MODE_BITSIZE (mode) < HOST_BITS_PER_INT)
124 /* Sign extend the value from the bits that are significant. */
125 if (val & (1 << (GET_MODE_BITSIZE (mode) - 1)))
126 val |= (-1) << GET_MODE_BITSIZE (mode);
128 val &= (1 << GET_MODE_BITSIZE (mode)) - 1;
130 return gen_rtx (CONST_INT, VOIDmode, val);
133 return expand_unop (GET_MODE (x), neg_optab, x, 0, 0);
136 /* Generate code to store value from rtx VALUE
137 into a bit-field within structure STR_RTX
138 containing BITSIZE bits starting at bit BITNUM.
139 FIELDMODE is the machine-mode of the FIELD_DECL node for this field.
140 ALIGN is the alignment that STR_RTX is known to have, measured in bytes.
141 TOTAL_SIZE is the size of the structure in bytes, or -1 if varying. */
143 /* ??? Note that there are two different ideas here for how
144 to determine the size to count bits within, for a register.
145 One is BITS_PER_WORD, and the other is the size of operand 3
146 of the insv pattern. (The latter assumes that an n-bit machine
147 will be able to insert bit fields up to n bits wide.)
148 It isn't certain that either of these is right.
149 extract_bit_field has the same quandary. */
152 store_bit_field (str_rtx, bitsize, bitnum, fieldmode, value, align, total_size)
154 register int bitsize;
156 enum machine_mode fieldmode;
161 int unit = (GET_CODE (str_rtx) == MEM) ? BITS_PER_UNIT : BITS_PER_WORD;
162 register int offset = bitnum / unit;
163 register int bitpos = bitnum % unit;
164 register rtx op0 = str_rtx;
166 if (GET_CODE (str_rtx) == MEM && ! MEM_IN_STRUCT_P (str_rtx))
169 /* Discount the part of the structure before the desired byte.
170 We need to know how many bytes are safe to reference after it. */
172 total_size -= (bitpos / BIGGEST_ALIGNMENT
173 * (BIGGEST_ALIGNMENT / BITS_PER_UNIT));
175 while (GET_CODE (op0) == SUBREG)
177 /* The following line once was done only if WORDS_BIG_ENDIAN,
178 but I think that is a mistake. WORDS_BIG_ENDIAN is
179 meaningful at a much higher level; when structures are copied
180 between memory and regs, the higher-numbered regs
181 always get higher addresses. */
182 offset += SUBREG_WORD (op0);
183 /* We used to adjust BITPOS here, but now we do the whole adjustment
184 right after the loop. */
185 op0 = SUBREG_REG (op0);
189 /* If OP0 is a register, BITPOS must count within a word.
190 But as we have it, it counts within whatever size OP0 now has.
191 On a bigendian machine, these are not the same, so convert. */
192 if (GET_CODE (op0) != MEM && unit > GET_MODE_BITSIZE (GET_MODE (op0)))
193 bitpos += unit - GET_MODE_BITSIZE (GET_MODE (op0));
196 value = protect_from_queue (value, 0);
199 value = force_not_mem (value);
201 /* Note that the adjustment of BITPOS above has no effect on whether
202 BITPOS is 0 in a REG bigger than a word. */
203 if (GET_MODE_SIZE (fieldmode) >= UNITS_PER_WORD
204 && (! STRICT_ALIGNMENT || GET_CODE (op0) != MEM)
205 && bitpos == 0 && bitsize == GET_MODE_BITSIZE (fieldmode))
207 /* Storing in a full-word or multi-word field in a register
208 can be done with just SUBREG. */
209 if (GET_MODE (op0) != fieldmode)
210 if (GET_CODE (op0) == REG)
211 op0 = gen_rtx (SUBREG, fieldmode, op0, offset);
213 op0 = change_address (op0, fieldmode,
214 plus_constant (XEXP (op0, 0), offset));
215 emit_move_insn (op0, value);
219 /* Storing an lsb-aligned field in a register
220 can be done with a movestrict instruction. */
222 if (GET_CODE (op0) != MEM
224 && bitpos + bitsize == unit
228 && bitsize == GET_MODE_BITSIZE (fieldmode)
229 && (GET_MODE (op0) == fieldmode
230 || (movstrict_optab->handlers[(int) fieldmode].insn_code
231 != CODE_FOR_nothing)))
233 /* Get appropriate low part of the value being stored. */
234 if (GET_CODE (value) == CONST_INT || GET_CODE (value) == REG)
235 value = gen_lowpart (fieldmode, value);
236 else if (!(GET_CODE (value) == SYMBOL_REF
237 || GET_CODE (value) == LABEL_REF
238 || GET_CODE (value) == CONST))
239 value = convert_to_mode (fieldmode, value, 0);
241 if (GET_MODE (op0) == fieldmode)
242 emit_move_insn (op0, value);
245 int icode = movstrict_optab->handlers[(int) fieldmode].insn_code;
246 if(! (*insn_operand_predicate[icode][1]) (value, fieldmode))
247 value = copy_to_mode_reg (fieldmode, value);
248 emit_insn (GEN_FCN (icode)
249 (gen_rtx (SUBREG, fieldmode, op0, offset), value));
254 /* Handle fields bigger than a word. */
256 if (bitsize > BITS_PER_WORD)
258 /* Here we transfer the words of the field
259 in the order least significant first.
260 This is because the most significant word is the one which may
261 be less than full. */
263 int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD;
266 /* This is the mode we must force value to, so that there will be enough
267 subwords to extract. Note that fieldmode will often (always?) be
268 VOIDmode, because that is what store_field uses to indicate that this
269 is a bit field, but passing VOIDmode to operand_subword_force will
270 result in an abort. */
271 fieldmode = mode_for_size (nwords * BITS_PER_WORD, MODE_INT, 0);
273 for (i = 0; i < nwords; i++)
275 /* If I is 0, use the low-order word in both field and target;
276 if I is 1, use the next to lowest word; and so on. */
277 int wordnum = (WORDS_BIG_ENDIAN ? nwords - i - 1 : i);
278 int bit_offset = (WORDS_BIG_ENDIAN
279 ? MAX (bitsize - (i + 1) * BITS_PER_WORD, 0)
280 : i * BITS_PER_WORD);
281 store_bit_field (op0, MIN (BITS_PER_WORD,
282 bitsize - i * BITS_PER_WORD),
283 bitnum + bit_offset, word_mode,
284 operand_subword_force (value, wordnum, fieldmode),
290 /* From here on we can assume that the field to be stored in is
291 a full-word (whatever type that is), since it is shorter than a word. */
293 /* OFFSET is the number of words or bytes (UNIT says which)
294 from STR_RTX to the first word or byte containing part of the field. */
296 if (GET_CODE (op0) == REG)
299 || GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD)
300 op0 = gen_rtx (SUBREG, TYPE_MODE (type_for_size (BITS_PER_WORD, 0)),
306 op0 = protect_from_queue (op0, 1);
309 /* Now OFFSET is nonzero only if OP0 is memory
310 and is therefore always measured in bytes. */
314 && !(bitsize == 1 && GET_CODE (value) == CONST_INT)
315 /* Ensure insv's size is wide enough for this field. */
316 && (GET_MODE_BITSIZE (insn_operand_mode[(int) CODE_FOR_insv][3])
319 int xbitpos = bitpos;
322 rtx last = get_last_insn ();
324 enum machine_mode maxmode
325 = insn_operand_mode[(int) CODE_FOR_insv][3];
327 int save_volatile_ok = volatile_ok;
330 /* If this machine's insv can only insert into a register, or if we
331 are to force MEMs into a register, copy OP0 into a register and
332 save it back later. */
333 if (GET_CODE (op0) == MEM
335 || ! ((*insn_operand_predicate[(int) CODE_FOR_insv][0])
339 enum machine_mode bestmode;
341 /* Get the mode to use for inserting into this field. If OP0 is
342 BLKmode, get the smallest mode consistent with the alignment. If
343 OP0 is a non-BLKmode object that is no wider than MAXMODE, use its
344 mode. Otherwise, use the smallest mode containing the field. */
346 if (GET_MODE (op0) == BLKmode
347 || GET_MODE_SIZE (GET_MODE (op0)) > GET_MODE_SIZE (maxmode))
349 = get_best_mode (bitsize, bitnum, align * BITS_PER_UNIT, maxmode,
350 MEM_VOLATILE_P (op0));
352 bestmode = GET_MODE (op0);
354 if (bestmode == VOIDmode)
357 /* Adjust address to point to the containing unit of that mode. */
358 unit = GET_MODE_BITSIZE (bestmode);
359 /* Compute offset as multiple of this unit, counting in bytes. */
360 offset = (bitnum / unit) * GET_MODE_SIZE (bestmode);
361 bitpos = bitnum % unit;
362 op0 = change_address (op0, bestmode,
363 plus_constant (XEXP (op0, 0), offset));
365 /* Fetch that unit, store the bitfield in it, then store the unit. */
366 tempreg = copy_to_reg (op0);
367 store_bit_field (tempreg, bitsize, bitpos, fieldmode, value,
369 emit_move_insn (op0, tempreg);
372 volatile_ok = save_volatile_ok;
374 /* Add OFFSET into OP0's address. */
375 if (GET_CODE (xop0) == MEM)
376 xop0 = change_address (xop0, byte_mode,
377 plus_constant (XEXP (xop0, 0), offset));
379 /* If xop0 is a register, we need it in MAXMODE
380 to make it acceptable to the format of insv. */
381 if (GET_CODE (xop0) == SUBREG)
382 PUT_MODE (xop0, maxmode);
383 if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode)
384 xop0 = gen_rtx (SUBREG, maxmode, xop0, 0);
386 /* On big-endian machines, we count bits from the most significant.
387 If the bit field insn does not, we must invert. */
389 #if BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN
390 xbitpos = unit - bitsize - xbitpos;
392 /* We have been counting XBITPOS within UNIT.
393 Count instead within the size of the register. */
395 if (GET_CODE (xop0) != MEM)
396 xbitpos += GET_MODE_BITSIZE (maxmode) - unit;
398 unit = GET_MODE_BITSIZE (maxmode);
400 /* Convert VALUE to maxmode (which insv insn wants) in VALUE1. */
402 if (GET_MODE (value) != maxmode)
404 if (GET_MODE_BITSIZE (GET_MODE (value)) >= bitsize)
406 /* Optimization: Don't bother really extending VALUE
407 if it has all the bits we will actually use. */
409 /* Avoid making subreg of a subreg, or of a mem. */
410 if (GET_CODE (value1) != REG)
411 value1 = copy_to_reg (value1);
412 value1 = gen_rtx (SUBREG, maxmode, value1, 0);
414 else if (!CONSTANT_P (value))
415 /* Parse phase is supposed to make VALUE's data type
416 match that of the component reference, which is a type
417 at least as wide as the field; so VALUE should have
418 a mode that corresponds to that type. */
422 /* If this machine's insv insists on a register,
423 get VALUE1 into a register. */
424 if (! ((*insn_operand_predicate[(int) CODE_FOR_insv][3])
426 value1 = force_reg (maxmode, value1);
428 pat = gen_insv (xop0,
429 gen_rtx (CONST_INT, VOIDmode, bitsize),
430 gen_rtx (CONST_INT, VOIDmode, xbitpos),
436 delete_insns_since (last);
437 store_fixed_bit_field (op0, offset, bitsize, bitpos, value, align);
443 /* Insv is not available; store using shifts and boolean ops. */
444 store_fixed_bit_field (op0, offset, bitsize, bitpos, value, align);
448 /* Use shifts and boolean operations to store VALUE
449 into a bit field of width BITSIZE
450 in a memory location specified by OP0 except offset by OFFSET bytes.
451 (OFFSET must be 0 if OP0 is a register.)
452 The field starts at position BITPOS within the byte.
453 (If OP0 is a register, it may be a full word or a narrower mode,
454 but BITPOS still counts within a full word,
455 which is significant on bigendian machines.)
456 STRUCT_ALIGN is the alignment the structure is known to have (in bytes).
458 Note that protect_from_queue has already been done on OP0 and VALUE. */
461 store_fixed_bit_field (op0, offset, bitsize, bitpos, value, struct_align)
463 register int offset, bitsize, bitpos;
467 register enum machine_mode mode;
468 int total_bits = BITS_PER_WORD;
473 /* Add OFFSET to OP0's address (if it is in memory)
474 and if a single byte contains the whole bit field
475 change OP0 to a byte. */
477 /* There is a case not handled here:
478 a structure with a known alignment of just a halfword
479 and a field split across two aligned halfwords within the structure.
480 Or likewise a structure with a known alignment of just a byte
481 and a field split across two bytes.
482 Such cases are not supposed to be able to occur. */
484 if (GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
488 /* Special treatment for a bit field split across two registers. */
489 if (bitsize + bitpos > BITS_PER_WORD)
491 store_split_bit_field (op0, bitsize, bitpos, value, BITS_PER_WORD);
497 /* Get the proper mode to use for this field. We want a mode that
498 includes the entire field. If such a mode would be larger than
499 a word, we won't be doing the extraction the normal way. */
501 mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT,
502 struct_align * BITS_PER_UNIT, word_mode,
503 GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0));
505 if (mode == VOIDmode)
507 /* The only way this should occur is if the field spans word
509 store_split_bit_field (op0, bitsize, bitpos + offset * BITS_PER_UNIT,
510 value, struct_align);
514 total_bits = GET_MODE_BITSIZE (mode);
516 /* Get ref to an aligned byte, halfword, or word containing the field.
517 Adjust BITPOS to be position within a word,
518 and OFFSET to be the offset of that word.
519 Then alter OP0 to refer to that word. */
520 bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT;
521 offset -= (offset % (total_bits / BITS_PER_UNIT));
522 op0 = change_address (op0, mode,
523 plus_constant (XEXP (op0, 0), offset));
526 mode = GET_MODE (op0);
528 /* Now MODE is either some integral mode for a MEM as OP0,
529 or is a full-word for a REG as OP0. TOTAL_BITS corresponds.
530 The bit field is contained entirely within OP0.
531 BITPOS is the starting bit number within OP0.
532 (OP0's mode may actually be narrower than MODE.) */
535 /* BITPOS is the distance between our msb
536 and that of the containing datum.
537 Convert it to the distance from the lsb. */
539 bitpos = total_bits - bitsize - bitpos;
541 /* Now BITPOS is always the distance between our lsb
544 /* Shift VALUE left by BITPOS bits. If VALUE is not constant,
545 we must first convert its mode to MODE. */
547 if (GET_CODE (value) == CONST_INT)
549 register int v = INTVAL (value);
551 if (bitsize < HOST_BITS_PER_INT)
552 v &= (1 << bitsize) - 1;
556 else if ((bitsize < HOST_BITS_PER_INT && v == (1 << bitsize) - 1)
557 || (bitsize == HOST_BITS_PER_INT && v == -1))
560 value = lshift_value (mode, value, bitpos, bitsize);
564 int must_and = (GET_MODE_BITSIZE (GET_MODE (value)) != bitsize
565 && bitpos + bitsize != GET_MODE_BITSIZE (mode));
567 if (GET_MODE (value) != mode)
569 /* If VALUE is a floating-point mode, access it as an integer
570 of the corresponding size, then convert it. This can occur on
571 a machine with 64 bit registers that uses SFmode for float. */
572 if (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT)
574 if (GET_CODE (value) != REG)
575 value = copy_to_reg (value);
577 = gen_rtx (SUBREG, word_mode, value, 0);
580 if ((GET_CODE (value) == REG || GET_CODE (value) == SUBREG)
581 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (value)))
582 value = gen_lowpart (mode, value);
584 value = convert_to_mode (mode, value, 1);
588 value = expand_binop (mode, and_optab, value,
589 mask_rtx (mode, 0, bitsize, 0),
590 0, 1, OPTAB_LIB_WIDEN);
592 value = expand_shift (LSHIFT_EXPR, mode, value,
593 build_int_2 (bitpos, 0), 0, 1);
596 /* Now clear the chosen bits in OP0,
597 except that if VALUE is -1 we need not bother. */
599 subtarget = (GET_CODE (op0) == REG || ! flag_force_mem) ? op0 : 0;
603 temp = expand_binop (mode, and_optab, op0,
604 mask_rtx (mode, bitpos, bitsize, 1),
605 subtarget, 1, OPTAB_LIB_WIDEN);
611 /* Now logical-or VALUE into OP0, unless it is zero. */
614 temp = expand_binop (mode, ior_optab, temp, value,
615 subtarget, 1, OPTAB_LIB_WIDEN);
617 emit_move_insn (op0, temp);
620 /* Store a bit field that is split across two words.
622 OP0 is the REG, SUBREG or MEM rtx for the first of the two words.
623 BITSIZE is the field width; BITPOS the position of its first bit
625 VALUE is the value to store. */
628 store_split_bit_field (op0, bitsize, bitpos, value, align)
634 /* BITSIZE_1 is size of the part in the first word. */
635 int bitsize_1 = BITS_PER_WORD - bitpos % BITS_PER_WORD;
636 /* BITSIZE_2 is size of the rest (in the following word). */
637 int bitsize_2 = bitsize - bitsize_1;
639 int unit = GET_CODE (op0) == MEM ? BITS_PER_UNIT : BITS_PER_WORD;
640 int offset = bitpos / unit;
643 /* The field must span exactly one word boundary. */
644 if (bitpos / BITS_PER_WORD != (bitpos + bitsize - 1) / BITS_PER_WORD - 1)
647 if (GET_MODE (value) != VOIDmode)
648 value = convert_to_mode (word_mode, value, 1);
649 if (CONSTANT_P (value) && GET_CODE (value) != CONST_INT)
650 value = copy_to_reg (value);
652 /* Split the value into two parts:
653 PART1 gets that which goes in the first word; PART2 the other. */
655 /* PART1 gets the more significant part. */
656 if (GET_CODE (value) == CONST_INT)
658 part1 = gen_rtx (CONST_INT, VOIDmode,
659 (unsigned) (INTVAL (value)) >> bitsize_2);
660 part2 = gen_rtx (CONST_INT, VOIDmode,
661 (unsigned) (INTVAL (value)) & ((1 << bitsize_2) - 1));
665 part1 = extract_fixed_bit_field (word_mode, value, 0, bitsize_1,
666 BITS_PER_WORD - bitsize, 0, 1,
668 part2 = extract_fixed_bit_field (word_mode, value, 0, bitsize_2,
669 BITS_PER_WORD - bitsize_2, 0, 1,
673 /* PART1 gets the less significant part. */
674 if (GET_CODE (value) == CONST_INT)
676 part1 = gen_rtx (CONST_INT, VOIDmode,
677 (unsigned) (INTVAL (value)) & ((1 << bitsize_1) - 1));
678 part2 = gen_rtx (CONST_INT, VOIDmode,
679 (unsigned) (INTVAL (value)) >> bitsize_1);
683 part1 = extract_fixed_bit_field (word_mode, value, 0, bitsize_1, 0,
684 0, 1, BITS_PER_WORD);
685 part2 = extract_fixed_bit_field (word_mode, value, 0, bitsize_2,
686 bitsize_1, 0, 1, BITS_PER_WORD);
690 /* Store PART1 into the first word. If OP0 is a MEM, pass OP0 and the
691 offset computed above. Otherwise, get the proper word and pass an
693 word = (GET_CODE (op0) == MEM ? op0
694 : operand_subword (op0, offset, 1, GET_MODE (op0)));
698 store_fixed_bit_field (word, GET_CODE (op0) == MEM ? offset : 0,
699 bitsize_1, bitpos % unit, part1, align);
701 /* Offset op0 by 1 word to get to the following one. */
702 if (GET_CODE (op0) == SUBREG)
703 word = operand_subword (SUBREG_REG (op0), SUBREG_WORD (op0) + offset + 1,
705 else if (GET_CODE (op0) == MEM)
708 word = operand_subword (op0, offset + 1, 1, GET_MODE (op0));
713 /* Store PART2 into the second word. */
714 store_fixed_bit_field (word,
715 (GET_CODE (op0) == MEM
716 ? CEIL (offset + 1, UNITS_PER_WORD) * UNITS_PER_WORD
718 bitsize_2, 0, part2, align);
721 /* Generate code to extract a byte-field from STR_RTX
722 containing BITSIZE bits, starting at BITNUM,
723 and put it in TARGET if possible (if TARGET is nonzero).
724 Regardless of TARGET, we return the rtx for where the value is placed.
727 STR_RTX is the structure containing the byte (a REG or MEM).
728 UNSIGNEDP is nonzero if this is an unsigned bit field.
729 MODE is the natural mode of the field value once extracted.
730 TMODE is the mode the caller would like the value to have;
731 but the value may be returned with type MODE instead.
733 ALIGN is the alignment that STR_RTX is known to have, measured in bytes.
734 TOTAL_SIZE is the size in bytes of the containing structure,
737 If a TARGET is specified and we can store in it at no extra cost,
738 we do so, and return TARGET.
739 Otherwise, we return a REG of mode TMODE or MODE, with TMODE preferred
740 if they are equally easy. */
743 extract_bit_field (str_rtx, bitsize, bitnum, unsignedp,
744 target, mode, tmode, align, total_size)
746 register int bitsize;
750 enum machine_mode mode, tmode;
754 int unit = (GET_CODE (str_rtx) == MEM) ? BITS_PER_UNIT : BITS_PER_WORD;
755 register int offset = bitnum / unit;
756 register int bitpos = bitnum % unit;
757 register rtx op0 = str_rtx;
758 rtx spec_target = target;
759 rtx spec_target_subreg = 0;
761 if (GET_CODE (str_rtx) == MEM && ! MEM_IN_STRUCT_P (str_rtx))
764 /* Discount the part of the structure before the desired byte.
765 We need to know how many bytes are safe to reference after it. */
767 total_size -= (bitpos / BIGGEST_ALIGNMENT
768 * (BIGGEST_ALIGNMENT / BITS_PER_UNIT));
770 if (tmode == VOIDmode)
773 while (GET_CODE (op0) == SUBREG)
775 offset += SUBREG_WORD (op0);
776 op0 = SUBREG_REG (op0);
780 /* If OP0 is a register, BITPOS must count within a word.
781 But as we have it, it counts within whatever size OP0 now has.
782 On a bigendian machine, these are not the same, so convert. */
783 if (GET_CODE (op0) != MEM && unit > GET_MODE_BITSIZE (GET_MODE (op0)))
784 bitpos += unit - GET_MODE_BITSIZE (GET_MODE (op0));
787 /* Extracting a full-word or multi-word value
788 from a structure in a register.
789 This can be done with just SUBREG.
790 So too extracting a subword value in
791 the least significant part of the register. */
793 if (GET_CODE (op0) == REG
794 && ((bitsize >= BITS_PER_WORD && bitsize == GET_MODE_BITSIZE (mode)
795 && bitpos % BITS_PER_WORD == 0)
796 || (mode_for_size (bitsize, GET_MODE_CLASS (tmode), 0) != BLKmode
798 && bitpos + bitsize == BITS_PER_WORD
804 enum machine_mode mode1
805 = mode_for_size (bitsize, GET_MODE_CLASS (tmode), 0);
807 if (mode1 != GET_MODE (op0))
808 op0 = gen_rtx (SUBREG, mode1, op0, offset);
811 return convert_to_mode (tmode, op0, unsignedp);
815 /* Handle fields bigger than a word. */
817 if (bitsize > BITS_PER_WORD)
819 /* Here we transfer the words of the field
820 in the order least significant first.
821 This is because the most significant word is the one which may
822 be less than full. */
824 int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD;
827 if (target == 0 || GET_CODE (target) != REG)
828 target = gen_reg_rtx (mode);
830 for (i = 0; i < nwords; i++)
832 /* If I is 0, use the low-order word in both field and target;
833 if I is 1, use the next to lowest word; and so on. */
834 int wordnum = (WORDS_BIG_ENDIAN ? nwords - i - 1 : i);
835 int bit_offset = (WORDS_BIG_ENDIAN
836 ? MAX (0, bitsize - (i + 1) * BITS_PER_WORD)
837 : i * BITS_PER_WORD);
838 rtx target_part = operand_subword (target, wordnum, 1, VOIDmode);
840 = extract_bit_field (op0, MIN (BITS_PER_WORD,
841 bitsize - i * BITS_PER_WORD),
843 1, target_part, mode, word_mode,
846 if (target_part == 0)
849 if (result_part != target_part)
850 emit_move_insn (target_part, result_part);
856 /* From here on we know the desired field is smaller than a word
857 so we can assume it is an integer. So we can safely extract it as one
858 size of integer, if necessary, and then truncate or extend
859 to the size that is wanted. */
861 /* OFFSET is the number of words or bytes (UNIT says which)
862 from STR_RTX to the first word or byte containing part of the field. */
864 if (GET_CODE (op0) == REG)
867 || GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD)
868 op0 = gen_rtx (SUBREG, TYPE_MODE (type_for_size (BITS_PER_WORD, 0)),
874 op0 = protect_from_queue (str_rtx, 1);
877 /* Now OFFSET is nonzero only for memory operands. */
883 && (GET_MODE_BITSIZE (insn_operand_mode[(int) CODE_FOR_extzv][0])
886 int xbitpos = bitpos, xoffset = offset;
887 rtx bitsize_rtx, bitpos_rtx;
888 rtx last = get_last_insn();
890 rtx xtarget = target;
891 rtx xspec_target = spec_target;
892 rtx xspec_target_subreg = spec_target_subreg;
894 enum machine_mode maxmode
895 = insn_operand_mode[(int) CODE_FOR_extzv][0];
897 if (GET_CODE (xop0) == MEM)
899 int save_volatile_ok = volatile_ok;
902 /* Is the memory operand acceptable? */
904 || ! ((*insn_operand_predicate[(int) CODE_FOR_extzv][1])
905 (xop0, GET_MODE (xop0))))
907 /* No, load into a reg and extract from there. */
908 enum machine_mode bestmode;
910 /* Get the mode to use for inserting into this field. If
911 OP0 is BLKmode, get the smallest mode consistent with the
912 alignment. If OP0 is a non-BLKmode object that is no
913 wider than MAXMODE, use its mode. Otherwise, use the
914 smallest mode containing the field. */
916 if (GET_MODE (xop0) == BLKmode
917 || (GET_MODE_SIZE (GET_MODE (op0))
918 > GET_MODE_SIZE (maxmode)))
919 bestmode = get_best_mode (bitsize, bitnum,
920 align * BITS_PER_UNIT, maxmode,
921 MEM_VOLATILE_P (xop0));
923 bestmode = GET_MODE (xop0);
925 if (bestmode == VOIDmode)
928 /* Compute offset as multiple of this unit,
929 counting in bytes. */
930 unit = GET_MODE_BITSIZE (bestmode);
931 xoffset = (bitnum / unit) * GET_MODE_SIZE (bestmode);
932 xbitpos = bitnum % unit;
933 xop0 = change_address (xop0, bestmode,
934 plus_constant (XEXP (xop0, 0),
936 /* Fetch it to a register in that size. */
937 xop0 = force_reg (bestmode, xop0);
939 /* XBITPOS counts within UNIT, which is what is expected. */
942 /* Get ref to first byte containing part of the field. */
943 xop0 = change_address (xop0, byte_mode,
944 plus_constant (XEXP (xop0, 0), xoffset));
946 volatile_ok = save_volatile_ok;
949 /* If op0 is a register, we need it in MAXMODE (which is usually
950 SImode). to make it acceptable to the format of extzv. */
951 if (GET_CODE (xop0) == SUBREG && GET_MODE (xop0) != maxmode)
953 if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode)
954 xop0 = gen_rtx (SUBREG, maxmode, xop0, 0);
956 /* On big-endian machines, we count bits from the most significant.
957 If the bit field insn does not, we must invert. */
958 #if BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN
959 xbitpos = unit - bitsize - xbitpos;
961 /* Now convert from counting within UNIT to counting in MAXMODE. */
963 if (GET_CODE (xop0) != MEM)
964 xbitpos += GET_MODE_BITSIZE (maxmode) - unit;
966 unit = GET_MODE_BITSIZE (maxmode);
969 || (flag_force_mem && GET_CODE (xtarget) == MEM))
970 xtarget = xspec_target = gen_reg_rtx (tmode);
972 if (GET_MODE (xtarget) != maxmode)
974 if (GET_CODE (xtarget) == REG)
976 int wider = (GET_MODE_SIZE (maxmode)
977 > GET_MODE_SIZE (GET_MODE (xtarget)));
978 xtarget = gen_lowpart (maxmode, xtarget);
980 xspec_target_subreg = xtarget;
983 xtarget = gen_reg_rtx (maxmode);
986 /* If this machine's extzv insists on a register target,
987 make sure we have one. */
988 if (! ((*insn_operand_predicate[(int) CODE_FOR_extzv][0])
990 xtarget = gen_reg_rtx (maxmode);
992 bitsize_rtx = gen_rtx (CONST_INT, VOIDmode, bitsize);
993 bitpos_rtx = gen_rtx (CONST_INT, VOIDmode, xbitpos);
995 pat = gen_extzv (protect_from_queue (xtarget, 1),
996 xop0, bitsize_rtx, bitpos_rtx);
1001 spec_target = xspec_target;
1002 spec_target_subreg = xspec_target_subreg;
1006 delete_insns_since (last);
1007 target = extract_fixed_bit_field (tmode, op0, offset, bitsize,
1008 bitpos, target, 1, align);
1014 target = extract_fixed_bit_field (tmode, op0, offset, bitsize, bitpos,
1021 && (GET_MODE_BITSIZE (insn_operand_mode[(int) CODE_FOR_extv][0])
1024 int xbitpos = bitpos, xoffset = offset;
1025 rtx bitsize_rtx, bitpos_rtx;
1026 rtx last = get_last_insn();
1027 rtx xop0 = op0, xtarget = target;
1028 rtx xspec_target = spec_target;
1029 rtx xspec_target_subreg = spec_target_subreg;
1031 enum machine_mode maxmode
1032 = insn_operand_mode[(int) CODE_FOR_extv][0];
1034 if (GET_CODE (xop0) == MEM)
1036 /* Is the memory operand acceptable? */
1037 if (! ((*insn_operand_predicate[(int) CODE_FOR_extv][1])
1038 (xop0, GET_MODE (xop0))))
1040 /* No, load into a reg and extract from there. */
1041 enum machine_mode bestmode;
1043 /* Get the mode to use for inserting into this field. If
1044 OP0 is BLKmode, get the smallest mode consistent with the
1045 alignment. If OP0 is a non-BLKmode object that is no
1046 wider than MAXMODE, use its mode. Otherwise, use the
1047 smallest mode containing the field. */
1049 if (GET_MODE (xop0) == BLKmode
1050 || (GET_MODE_SIZE (GET_MODE (op0))
1051 > GET_MODE_SIZE (maxmode)))
1052 bestmode = get_best_mode (bitsize, bitnum,
1053 align * BITS_PER_UNIT, maxmode,
1054 MEM_VOLATILE_P (xop0));
1056 bestmode = GET_MODE (xop0);
1058 if (bestmode == VOIDmode)
1061 /* Compute offset as multiple of this unit,
1062 counting in bytes. */
1063 unit = GET_MODE_BITSIZE (bestmode);
1064 xoffset = (bitnum / unit) * GET_MODE_SIZE (bestmode);
1065 xbitpos = bitnum % unit;
1066 xop0 = change_address (xop0, bestmode,
1067 plus_constant (XEXP (xop0, 0),
1069 /* Fetch it to a register in that size. */
1070 xop0 = force_reg (bestmode, xop0);
1072 /* XBITPOS counts within UNIT, which is what is expected. */
1075 /* Get ref to first byte containing part of the field. */
1076 xop0 = change_address (xop0, byte_mode,
1077 plus_constant (XEXP (xop0, 0), xoffset));
1080 /* If op0 is a register, we need it in MAXMODE (which is usually
1081 SImode) to make it acceptable to the format of extv. */
1082 if (GET_CODE (xop0) == SUBREG && GET_MODE (xop0) != maxmode)
1084 if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode)
1085 xop0 = gen_rtx (SUBREG, maxmode, xop0, 0);
1087 /* On big-endian machines, we count bits from the most significant.
1088 If the bit field insn does not, we must invert. */
1089 #if BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN
1090 xbitpos = unit - bitsize - xbitpos;
1092 /* XBITPOS counts within a size of UNIT.
1093 Adjust to count within a size of MAXMODE. */
1095 if (GET_CODE (xop0) != MEM)
1096 xbitpos += (GET_MODE_BITSIZE (maxmode) - unit);
1098 unit = GET_MODE_BITSIZE (maxmode);
1101 || (flag_force_mem && GET_CODE (xtarget) == MEM))
1102 xtarget = xspec_target = gen_reg_rtx (tmode);
1104 if (GET_MODE (xtarget) != maxmode)
1106 if (GET_CODE (xtarget) == REG)
1108 int wider = (GET_MODE_SIZE (maxmode)
1109 > GET_MODE_SIZE (GET_MODE (xtarget)));
1110 xtarget = gen_lowpart (maxmode, xtarget);
1112 xspec_target_subreg = xtarget;
1115 xtarget = gen_reg_rtx (maxmode);
1118 /* If this machine's extv insists on a register target,
1119 make sure we have one. */
1120 if (! ((*insn_operand_predicate[(int) CODE_FOR_extv][0])
1121 (xtarget, maxmode)))
1122 xtarget = gen_reg_rtx (maxmode);
1124 bitsize_rtx = gen_rtx (CONST_INT, VOIDmode, bitsize);
1125 bitpos_rtx = gen_rtx (CONST_INT, VOIDmode, xbitpos);
1127 pat = gen_extv (protect_from_queue (xtarget, 1),
1128 xop0, bitsize_rtx, bitpos_rtx);
1133 spec_target = xspec_target;
1134 spec_target_subreg = xspec_target_subreg;
1138 delete_insns_since (last);
1139 target = extract_fixed_bit_field (tmode, op0, offset, bitsize,
1140 bitpos, target, 0, align);
1146 target = extract_fixed_bit_field (tmode, op0, offset, bitsize, bitpos,
1149 if (target == spec_target)
1151 if (target == spec_target_subreg)
1153 if (GET_MODE (target) != tmode && GET_MODE (target) != mode)
1155 /* If the target mode is floating-point, first convert to the
1156 integer mode of that size and then access it as a floating-point
1157 value via a SUBREG. */
1158 if (GET_MODE_CLASS (tmode) == MODE_FLOAT)
1160 target = convert_to_mode (mode_for_size (GET_MODE_BITSIZE (tmode),
1163 if (GET_CODE (target) != REG)
1164 target = copy_to_reg (target);
1165 return gen_rtx (SUBREG, tmode, target, 0);
1168 return convert_to_mode (tmode, target, unsignedp);
1173 /* Extract a bit field using shifts and boolean operations
1174 Returns an rtx to represent the value.
1175 OP0 addresses a register (word) or memory (byte).
1176 BITPOS says which bit within the word or byte the bit field starts in.
1177 OFFSET says how many bytes farther the bit field starts;
1178 it is 0 if OP0 is a register.
1179 BITSIZE says how many bits long the bit field is.
1180 (If OP0 is a register, it may be narrower than a full word,
1181 but BITPOS still counts within a full word,
1182 which is significant on bigendian machines.)
1184 UNSIGNEDP is nonzero for an unsigned bit field (don't sign-extend value).
1185 If TARGET is nonzero, attempts to store the value there
1186 and return TARGET, but this is not guaranteed.
1187 If TARGET is not used, create a pseudo-reg of mode TMODE for the value.
1189 ALIGN is the alignment that STR_RTX is known to have, measured in bytes. */
1192 extract_fixed_bit_field (tmode, op0, offset, bitsize, bitpos,
1193 target, unsignedp, align)
1194 enum machine_mode tmode;
1195 register rtx op0, target;
1196 register int offset, bitsize, bitpos;
1200 int total_bits = BITS_PER_WORD;
1201 enum machine_mode mode;
1203 if (GET_CODE (op0) == SUBREG || GET_CODE (op0) == REG)
1205 /* Special treatment for a bit field split across two registers. */
1206 if (bitsize + bitpos > BITS_PER_WORD)
1207 return extract_split_bit_field (op0, bitsize, bitpos,
1212 /* Get the proper mode to use for this field. We want a mode that
1213 includes the entire field. If such a mode would be larger than
1214 a word, we won't be doing the extraction the normal way. */
1216 mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT,
1217 align * BITS_PER_UNIT, word_mode,
1218 GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0));
1220 if (mode == VOIDmode)
1221 /* The only way this should occur is if the field spans word
1223 return extract_split_bit_field (op0, bitsize,
1224 bitpos + offset * BITS_PER_UNIT,
1227 total_bits = GET_MODE_BITSIZE (mode);
1229 /* Get ref to an aligned byte, halfword, or word containing the field.
1230 Adjust BITPOS to be position within a word,
1231 and OFFSET to be the offset of that word.
1232 Then alter OP0 to refer to that word. */
1233 bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT;
1234 offset -= (offset % (total_bits / BITS_PER_UNIT));
1235 op0 = change_address (op0, mode,
1236 plus_constant (XEXP (op0, 0), offset));
1239 mode = GET_MODE (op0);
1241 #if BYTES_BIG_ENDIAN
1242 /* BITPOS is the distance between our msb and that of OP0.
1243 Convert it to the distance from the lsb. */
1245 bitpos = total_bits - bitsize - bitpos;
1247 /* Now BITPOS is always the distance between the field's lsb and that of OP0.
1248 We have reduced the big-endian case to the little-endian case. */
1254 /* If the field does not already start at the lsb,
1255 shift it so it does. */
1256 tree amount = build_int_2 (bitpos, 0);
1257 /* Maybe propagate the target for the shift. */
1258 /* But not if we will return it--could confuse integrate.c. */
1259 rtx subtarget = (target != 0 && GET_CODE (target) == REG
1260 && !REG_FUNCTION_VALUE_P (target)
1262 if (tmode != mode) subtarget = 0;
1263 op0 = expand_shift (RSHIFT_EXPR, mode, op0, amount, subtarget, 1);
1265 /* Convert the value to the desired mode. */
1267 op0 = convert_to_mode (tmode, op0, 1);
1269 /* Unless the msb of the field used to be the msb when we shifted,
1270 mask out the upper bits. */
1272 if (GET_MODE_BITSIZE (mode) != bitpos + bitsize
1274 #ifdef SLOW_ZERO_EXTEND
1275 /* Always generate an `and' if
1276 we just zero-extended op0 and SLOW_ZERO_EXTEND, since it
1277 will combine fruitfully with the zero-extend. */
1282 return expand_binop (GET_MODE (op0), and_optab, op0,
1283 mask_rtx (GET_MODE (op0), 0, bitsize, 0),
1284 target, 1, OPTAB_LIB_WIDEN);
1288 /* To extract a signed bit-field, first shift its msb to the msb of the word,
1289 then arithmetic-shift its lsb to the lsb of the word. */
1290 op0 = force_reg (mode, op0);
1294 /* Find the narrowest integer mode that contains the field. */
1296 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode;
1297 mode = GET_MODE_WIDER_MODE (mode))
1298 if (GET_MODE_BITSIZE (mode) >= bitsize + bitpos)
1300 op0 = convert_to_mode (mode, op0, 0);
1304 if (GET_MODE_BITSIZE (mode) != (bitsize + bitpos))
1306 tree amount = build_int_2 (GET_MODE_BITSIZE (mode) - (bitsize + bitpos), 0);
1307 /* Maybe propagate the target for the shift. */
1308 /* But not if we will return the result--could confuse integrate.c. */
1309 rtx subtarget = (target != 0 && GET_CODE (target) == REG
1310 && ! REG_FUNCTION_VALUE_P (target)
1312 op0 = expand_shift (LSHIFT_EXPR, mode, op0, amount, subtarget, 1);
1315 return expand_shift (RSHIFT_EXPR, mode, op0,
1316 build_int_2 (GET_MODE_BITSIZE (mode) - bitsize, 0),
1320 /* Return a constant integer (CONST_INT or CONST_DOUBLE) mask value
1321 of mode MODE with BITSIZE ones followed by BITPOS zeros, or the
1322 complement of that if COMPLEMENT. The mask is truncated if
1323 necessary to the width of mode MODE. */
1326 mask_rtx (mode, bitpos, bitsize, complement)
1327 enum machine_mode mode;
1328 int bitpos, bitsize, complement;
1330 int masklow, maskhigh;
1332 if (bitpos < HOST_BITS_PER_INT)
1333 masklow = -1 << bitpos;
1337 if (bitpos + bitsize < HOST_BITS_PER_INT)
1338 masklow &= (unsigned) -1 >> (HOST_BITS_PER_INT - bitpos - bitsize);
1340 if (bitpos <= HOST_BITS_PER_INT)
1343 maskhigh = -1 << (bitpos - HOST_BITS_PER_INT);
1345 if (bitpos + bitsize > HOST_BITS_PER_INT)
1346 maskhigh &= (unsigned) -1 >> (2 * HOST_BITS_PER_INT - bitpos - bitsize);
1352 maskhigh = ~maskhigh;
1356 return immed_double_const (masklow, maskhigh, mode);
1359 /* Return a constant integer (CONST_INT or CONST_DOUBLE) rtx with the value
1360 VALUE truncated to BITSIZE bits and then shifted left BITPOS bits. */
1363 lshift_value (mode, value, bitpos, bitsize)
1364 enum machine_mode mode;
1366 int bitpos, bitsize;
1368 unsigned v = INTVAL (value);
1371 if (bitsize < HOST_BITS_PER_INT)
1372 v &= ~(-1 << bitsize);
1374 if (bitpos < HOST_BITS_PER_INT)
1377 high = (bitpos > 0 ? (v >> (HOST_BITS_PER_INT - bitpos)) : 0);
1382 high = v << (bitpos - HOST_BITS_PER_INT);
1385 return immed_double_const (low, high, mode);
1388 /* Extract a bit field that is split across two words
1389 and return an RTX for the result.
1391 OP0 is the REG, SUBREG or MEM rtx for the first of the two words.
1392 BITSIZE is the field width; BITPOS, position of its first bit, in the word.
1393 UNSIGNEDP is 1 if should zero-extend the contents; else sign-extend. */
1396 extract_split_bit_field (op0, bitsize, bitpos, unsignedp, align)
1398 int bitsize, bitpos, unsignedp, align;
1400 /* BITSIZE_1 is size of the part in the first word. */
1401 int bitsize_1 = BITS_PER_WORD - bitpos % BITS_PER_WORD;
1402 /* BITSIZE_2 is size of the rest (in the following word). */
1403 int bitsize_2 = bitsize - bitsize_1;
1404 rtx part1, part2, result;
1405 int unit = GET_CODE (op0) == MEM ? BITS_PER_UNIT : BITS_PER_WORD;
1406 int offset = bitpos / unit;
1409 /* The field must span exactly one word boundary. */
1410 if (bitpos / BITS_PER_WORD != (bitpos + bitsize - 1) / BITS_PER_WORD - 1)
1413 /* Get the part of the bit field from the first word. If OP0 is a MEM,
1414 pass OP0 and the offset computed above. Otherwise, get the proper
1415 word and pass an offset of zero. */
1416 word = (GET_CODE (op0) == MEM ? op0
1417 : operand_subword_force (op0, offset, GET_MODE (op0)));
1418 part1 = extract_fixed_bit_field (word_mode, word,
1419 GET_CODE (op0) == MEM ? offset : 0,
1420 bitsize_1, bitpos % unit, 0, 1, align);
1422 /* Offset op0 by 1 word to get to the following one. */
1423 if (GET_CODE (op0) == SUBREG)
1424 word = operand_subword_force (SUBREG_REG (op0),
1425 SUBREG_WORD (op0) + offset + 1, VOIDmode);
1426 else if (GET_CODE (op0) == MEM)
1429 word = operand_subword_force (op0, offset + 1, GET_MODE (op0));
1431 /* Get the part of the bit field from the second word. */
1432 part2 = extract_fixed_bit_field (word_mode, word,
1433 (GET_CODE (op0) == MEM
1434 ? CEIL (offset + 1, UNITS_PER_WORD) * UNITS_PER_WORD
1436 bitsize_2, 0, 0, 1, align);
1438 /* Shift the more significant part up to fit above the other part. */
1439 #if BYTES_BIG_ENDIAN
1440 part1 = expand_shift (LSHIFT_EXPR, word_mode, part1,
1441 build_int_2 (bitsize_2, 0), 0, 1);
1443 part2 = expand_shift (LSHIFT_EXPR, word_mode, part2,
1444 build_int_2 (bitsize_1, 0), 0, 1);
1447 /* Combine the two parts with bitwise or. This works
1448 because we extracted both parts as unsigned bit fields. */
1449 result = expand_binop (word_mode, ior_optab, part1, part2, 0, 1,
1452 /* Unsigned bit field: we are done. */
1455 /* Signed bit field: sign-extend with two arithmetic shifts. */
1456 result = expand_shift (LSHIFT_EXPR, word_mode, result,
1457 build_int_2 (BITS_PER_WORD - bitsize, 0), 0, 0);
1458 return expand_shift (RSHIFT_EXPR, word_mode, result,
1459 build_int_2 (BITS_PER_WORD - bitsize, 0), 0, 0);
1462 /* Add INC into TARGET. */
1465 expand_inc (target, inc)
1468 rtx value = expand_binop (GET_MODE (target), add_optab,
1470 target, 0, OPTAB_LIB_WIDEN);
1471 if (value != target)
1472 emit_move_insn (target, value);
1475 /* Subtract DEC from TARGET. */
1478 expand_dec (target, dec)
1481 rtx value = expand_binop (GET_MODE (target), sub_optab,
1483 target, 0, OPTAB_LIB_WIDEN);
1484 if (value != target)
1485 emit_move_insn (target, value);
1488 /* Output a shift instruction for expression code CODE,
1489 with SHIFTED being the rtx for the value to shift,
1490 and AMOUNT the tree for the amount to shift by.
1491 Store the result in the rtx TARGET, if that is convenient.
1492 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
1493 Return the rtx for where the value is. */
1496 expand_shift (code, mode, shifted, amount, target, unsignedp)
1497 enum tree_code code;
1498 register enum machine_mode mode;
1501 register rtx target;
1504 register rtx op1, temp = 0;
1505 register int left = (code == LSHIFT_EXPR || code == LROTATE_EXPR);
1506 register int rotate = (code == LROTATE_EXPR || code == RROTATE_EXPR);
1509 /* Previously detected shift-counts computed by NEGATE_EXPR
1510 and shifted in the other direction; but that does not work
1513 op1 = expand_expr (amount, 0, VOIDmode, 0);
1515 if (op1 == const0_rtx)
1518 for (try = 0; temp == 0 && try < 3; try++)
1520 enum optab_methods methods;
1523 methods = OPTAB_DIRECT;
1525 methods = OPTAB_WIDEN;
1527 methods = OPTAB_LIB_WIDEN;
1531 /* Widening does not work for rotation. */
1532 if (methods == OPTAB_WIDEN)
1534 else if (methods == OPTAB_LIB_WIDEN)
1535 methods = OPTAB_LIB;
1537 temp = expand_binop (mode,
1538 left ? rotl_optab : rotr_optab,
1539 shifted, op1, target, unsignedp, methods);
1543 temp = expand_binop (mode,
1544 left ? lshl_optab : lshr_optab,
1545 shifted, op1, target, unsignedp, methods);
1546 if (temp == 0 && left)
1547 temp = expand_binop (mode, ashl_optab,
1548 shifted, op1, target, unsignedp, methods);
1551 /* Do arithmetic shifts.
1552 Also, if we are going to widen the operand, we can just as well
1553 use an arithmetic right-shift instead of a logical one. */
1554 if (temp == 0 && ! rotate
1555 && (! unsignedp || (! left && methods == OPTAB_WIDEN)))
1557 enum optab_methods methods1 = methods;
1559 /* If trying to widen a log shift to an arithmetic shift,
1560 don't accept an arithmetic shift of the same size. */
1562 methods1 = OPTAB_MUST_WIDEN;
1564 /* Arithmetic shift */
1566 temp = expand_binop (mode,
1567 left ? ashl_optab : ashr_optab,
1568 shifted, op1, target, unsignedp, methods1);
1572 /* We can do a logical (unsigned) right shift with a bit-field
1573 extract insn. But first check if one of the above methods worked. */
1577 if (unsignedp && code == RSHIFT_EXPR && ! BITS_BIG_ENDIAN && HAVE_extzv)
1579 enum machine_mode output_mode
1580 = insn_operand_mode[(int) CODE_FOR_extzv][0];
1582 if ((methods == OPTAB_DIRECT && mode == output_mode)
1583 || (methods == OPTAB_WIDEN
1584 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (output_mode)))
1586 /* Note convert_to_mode does protect_from_queue. */
1587 rtx shifted1 = convert_to_mode (output_mode, shifted, 1);
1588 enum machine_mode length_mode
1589 = insn_operand_mode[(int) CODE_FOR_extzv][2];
1590 enum machine_mode pos_mode
1591 = insn_operand_mode[(int) CODE_FOR_extzv][3];
1593 rtx last = get_last_insn ();
1599 target1 = protect_from_queue (target, 1);
1601 /* We define extract insns as having OUTPUT_MODE in a register
1602 and the mode of operand 1 in memory. Since we want
1603 OUTPUT_MODE, we will always force the operand into a
1604 register. At some point we might want to support MEM
1606 shifted1 = force_reg (output_mode, shifted1);
1608 /* If we don't have or cannot use a suggested target,
1609 make a place for the result, in the proper mode. */
1610 if (methods == OPTAB_WIDEN || target1 == 0
1611 || ! ((*insn_operand_predicate[(int) CODE_FOR_extzv][0])
1612 (target1, output_mode)))
1613 target1 = gen_reg_rtx (output_mode);
1615 xop1 = convert_to_mode (pos_mode, xop1,
1616 TREE_UNSIGNED (TREE_TYPE (amount)));
1618 /* If this machine's extzv insists on a register for
1619 operand 3 (position), arrange for that. */
1620 if (! ((*insn_operand_predicate[(int) CODE_FOR_extzv][3])
1622 xop1 = force_reg (pos_mode, xop1);
1624 /* WIDTH gets the width of the bit field to extract:
1625 wordsize minus # bits to shift by. */
1626 if (GET_CODE (xop1) == CONST_INT)
1627 width = gen_rtx (CONST_INT, VOIDmode,
1628 (GET_MODE_BITSIZE (mode) - INTVAL (op1)));
1631 /* Now get the width in the proper mode. */
1632 width = convert_to_mode (length_mode, op1,
1633 TREE_UNSIGNED (TREE_TYPE (amount)));
1635 width = expand_binop (length_mode, sub_optab,
1636 gen_rtx (CONST_INT, VOIDmode,
1637 GET_MODE_BITSIZE (mode)),
1638 width, 0, 0, OPTAB_LIB_WIDEN);
1641 /* If this machine's extzv insists on a register for
1642 operand 2 (length), arrange for that. */
1643 if (! ((*insn_operand_predicate[(int) CODE_FOR_extzv][2])
1644 (width, length_mode)))
1645 width = force_reg (length_mode, width);
1647 /* Now extract with WIDTH, omitting OP1 least sig bits. */
1648 pat = gen_extzv (target1, shifted1, width, xop1);
1652 temp = convert_to_mode (mode, target1, 1);
1655 delete_insns_since (last);
1658 /* Can also do logical shift with signed bit-field extract
1659 followed by inserting the bit-field at a different position.
1660 That strategy is not yet implemented. */
1662 #endif /* HAVE_extzv */
1670 enum alg_code { alg_add, alg_subtract, alg_compound };
1672 /* This structure records a sequence of operations.
1673 `ops' is the number of operations recorded.
1674 `cost' is their total cost.
1675 The operations are stored in `op' and the corresponding
1676 integer coefficients in `coeff'.
1677 These are the operations:
1678 alg_add Add to the total the multiplicand times the coefficient.
1679 alg_subtract Subtract the multiplicand times the coefficient.
1680 alg_compound This coefficient plus or minus the following one
1681 is multiplied into the total. The following operation
1682 is alg_add or alg_subtract to indicate whether to add
1683 or subtract the two coefficients. */
1685 #ifndef MAX_BITS_PER_WORD
1686 #define MAX_BITS_PER_WORD BITS_PER_WORD
1693 enum alg_code op[MAX_BITS_PER_WORD];
1694 unsigned int coeff[MAX_BITS_PER_WORD];
1697 /* Compute and return the best algorithm for multiplying by T.
1698 Assume that add insns cost ADD_COST and shifts cost SHIFT_COST.
1699 Return cost -1 if would cost more than MAX_COST. */
1701 static struct algorithm
1702 synth_mult (t, add_cost, shift_cost, max_cost)
1704 int add_cost, shift_cost;
1708 struct algorithm *best_alg = (struct algorithm *)alloca (sizeof (struct algorithm));
1709 struct algorithm *alg_in = (struct algorithm *)alloca (sizeof (struct algorithm));
1712 /* No matter what happens, we want to return a valid algorithm. */
1713 best_alg->cost = max_cost;
1716 /* Is t an exponent of 2, so we can just do a shift? */
1722 if (max_cost >= shift_cost)
1724 best_alg->cost = shift_cost;
1726 best_alg->op[0] = alg_add;
1727 best_alg->coeff[0] = t;
1730 best_alg->cost = -1;
1743 /* If MAX_COST just permits as little as an addition (or less), we won't
1744 succeed in synthesizing an algorithm for t. Return immediately with
1745 an indication of failure. */
1746 if (max_cost <= add_cost)
1748 best_alg->cost = -1;
1752 /* Look for factors of t of the form
1753 t = q(2**m +- 1), 2 <= m <= floor(log2(t)) - 1.
1754 If we find such a factor, we can multiply by t using an algorithm that
1755 multiplies by q, shift the result by m and add/subtract it to itself. */
1757 for (m = floor_log2 (t) - 1; m >= 2; m--)
1759 int m_exp_2 = 1 << m;
1767 cost = add_cost + shift_cost * 2;
1769 *alg_in = synth_mult (q, add_cost, shift_cost,
1770 MIN (max_cost, best_alg->cost) - cost);
1772 if (alg_in->cost >= 0)
1774 cost += alg_in->cost;
1776 if (cost < best_alg->cost)
1778 struct algorithm *x;
1782 best_alg->coeff[best_alg->ops] = m_exp_2;
1783 best_alg->op[best_alg->ops++] = alg_compound;
1784 best_alg->coeff[best_alg->ops] = 1;
1785 best_alg->op[best_alg->ops++] = alg_add;
1786 best_alg->cost = cost;
1796 cost = add_cost + shift_cost * 2;
1798 *alg_in = synth_mult (q, add_cost, shift_cost,
1799 MIN (max_cost, best_alg->cost) - cost);
1801 if (alg_in->cost >= 0)
1803 cost += alg_in->cost;
1805 if (cost < best_alg->cost)
1807 struct algorithm *x;
1811 best_alg->coeff[best_alg->ops] = m_exp_2;
1812 best_alg->op[best_alg->ops++] = alg_compound;
1813 best_alg->coeff[best_alg->ops] = 1;
1814 best_alg->op[best_alg->ops++] = alg_subtract;
1815 best_alg->cost = cost;
1821 /* Try load effective address instructions, i.e. do a*3, a*5, a*9. */
1827 q = t & -t; /* get out lsb */
1828 w = (t - q) & -(t - q); /* get out next lsb */
1830 if (w / q <= lea_max_mul)
1832 cost = lea_cost + (q != 1 ? shift_cost : 0);
1834 *alg_in = synth_mult (t - q - w, add_cost, shift_cost,
1835 MIN (max_cost, best_alg->cost) - cost);
1837 if (alg_in->cost >= 0)
1839 cost += alg_in->cost;
1841 /* Use <= to prefer this method to the factoring method
1842 when the cost appears the same, because this method
1843 uses fewer temporary registers. */
1844 if (cost <= best_alg->cost)
1846 struct algorithm *x;
1850 best_alg->coeff[best_alg->ops] = w;
1851 best_alg->op[best_alg->ops++] = alg_add;
1852 best_alg->coeff[best_alg->ops] = q;
1853 best_alg->op[best_alg->ops++] = alg_add;
1854 best_alg->cost = cost;
1860 /* Now, use the good old method to add or subtract at the leftmost
1867 q = t & -t; /* get out lsb */
1868 for (w = q; (w & t) != 0; w <<= 1)
1871 /* Reject the case where t has only two bits.
1872 Thus we prefer addition in that case. */
1873 && !(t < w && w == q << 2))
1875 /* There are many bits in a row. Make 'em by subtraction. */
1881 *alg_in = synth_mult (t + q, add_cost, shift_cost,
1882 MIN (max_cost, best_alg->cost) - cost);
1884 if (alg_in->cost >= 0)
1886 cost += alg_in->cost;
1888 /* Use <= to prefer this method to the factoring method
1889 when the cost appears the same, because this method
1890 uses fewer temporary registers. */
1891 if (cost <= best_alg->cost)
1893 struct algorithm *x;
1897 best_alg->coeff[best_alg->ops] = q;
1898 best_alg->op[best_alg->ops++] = alg_subtract;
1899 best_alg->cost = cost;
1905 /* There's only one bit at the left. Make it by addition. */
1911 *alg_in = synth_mult (t - q, add_cost, shift_cost,
1912 MIN (max_cost, best_alg->cost) - cost);
1914 if (alg_in->cost >= 0)
1916 cost += alg_in->cost;
1918 if (cost <= best_alg->cost)
1920 struct algorithm *x;
1924 best_alg->coeff[best_alg->ops] = q;
1925 best_alg->op[best_alg->ops++] = alg_add;
1926 best_alg->cost = cost;
1932 if (best_alg->cost >= max_cost)
1933 best_alg->cost = -1;
1937 /* Perform a multiplication and return an rtx for the result.
1938 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
1939 TARGET is a suggestion for where to store the result (an rtx).
1941 We check specially for a constant integer as OP1.
1942 If you want this check for OP0 as well, then before calling
1943 you should swap the two operands if OP0 would be constant. */
1946 expand_mult (mode, op0, op1, target, unsignedp)
1947 enum machine_mode mode;
1948 register rtx op0, op1, target;
1951 rtx const_op1 = op1;
1953 /* If we are multiplying in DImode, it may still be a win
1954 to try to work with shifts and adds. */
1955 if (GET_CODE (op1) == CONST_DOUBLE
1956 && GET_MODE_CLASS (GET_MODE (op1)) == MODE_INT
1957 && HOST_BITS_PER_INT <= BITS_PER_WORD)
1959 if ((CONST_DOUBLE_HIGH (op1) == 0 && CONST_DOUBLE_LOW (op1) >= 0)
1960 || (CONST_DOUBLE_HIGH (op1) == -1 && CONST_DOUBLE_LOW (op1) < 0))
1961 const_op1 = gen_rtx (CONST_INT, VOIDmode, CONST_DOUBLE_LOW (op1));
1964 /* We used to test optimize here, on the grounds that it's better to
1965 produce a smaller program when -O is not used.
1966 But this causes such a terrible slowdown sometimes
1967 that it seems better to use synth_mult always. */
1968 if (GET_CODE (const_op1) == CONST_INT && ! mult_is_very_cheap)
1970 struct algorithm alg;
1971 struct algorithm neg_alg;
1973 int absval = INTVAL (op1);
1976 /* Try to do the computation two ways: multiply by the negative of OP1
1977 and then negate, or do the multiplication directly. The latter is
1978 usually faster for positive numbers and the former for negative
1979 numbers, but the opposite can be faster if the original value
1980 has a factor of 2**m +/- 1, while the negated value does not or
1983 alg = synth_mult (absval, add_cost, shift_cost, mult_cost);
1984 neg_alg = synth_mult (- absval, add_cost, shift_cost,
1985 mult_cost - negate_cost);
1987 if (neg_alg.cost >= 0 && neg_alg.cost + negate_cost < alg.cost)
1988 alg = neg_alg, negate = 1, absval = - absval;
1992 /* If we found something, it must be cheaper than multiply.
1996 int factors_seen = 0;
1998 op0 = protect_from_queue (op0, 0);
2000 /* Avoid referencing memory over and over.
2001 For speed, but also for correctness when mem is volatile. */
2002 if (GET_CODE (op0) == MEM)
2003 op0 = force_reg (mode, op0);
2006 accum = copy_to_mode_reg (mode, op0);
2009 /* 1 if this is the last in a series of adds and subtracts. */
2010 int last = (1 == alg.ops || alg.op[1] == alg_compound);
2011 int log = floor_log2 (alg.coeff[0]);
2012 if (! factors_seen && ! last)
2013 log -= floor_log2 (alg.coeff[1]);
2015 if (alg.op[0] != alg_add)
2017 accum = expand_shift (LSHIFT_EXPR, mode, op0,
2018 build_int_2 (log, 0),
2022 while (++opno < alg.ops)
2024 int log = floor_log2 (alg.coeff[opno]);
2025 /* 1 if this is the last in a series of adds and subtracts. */
2026 int last = (opno + 1 == alg.ops
2027 || alg.op[opno + 1] == alg_compound);
2029 /* If we have not yet seen any separate factors (alg_compound)
2030 then turn op0<<a1 + op0<<a2 + op0<<a3... into
2031 (op0<<(a1-a2) + op0)<<(a2-a3) + op0... */
2032 switch (alg.op[opno])
2037 tem = expand_shift (LSHIFT_EXPR, mode, op0,
2038 build_int_2 (log, 0), 0, 0);
2039 accum = force_operand (gen_rtx (PLUS, mode, accum, tem),
2045 log -= floor_log2 (alg.coeff[opno + 1]);
2046 accum = force_operand (gen_rtx (PLUS, mode, accum, op0),
2048 accum = expand_shift (LSHIFT_EXPR, mode, accum,
2049 build_int_2 (log, 0), accum, 0);
2056 tem = expand_shift (LSHIFT_EXPR, mode, op0,
2057 build_int_2 (log, 0), 0, 0);
2058 accum = force_operand (gen_rtx (MINUS, mode, accum, tem),
2064 log -= floor_log2 (alg.coeff[opno + 1]);
2065 accum = force_operand (gen_rtx (MINUS, mode, accum, op0),
2067 accum = expand_shift (LSHIFT_EXPR, mode, accum,
2068 build_int_2 (log, 0), accum, 0);
2075 tem = expand_shift (LSHIFT_EXPR, mode, accum,
2076 build_int_2 (log, 0), 0, 0);
2078 log = floor_log2 (alg.coeff[opno + 1]);
2079 accum = expand_shift (LSHIFT_EXPR, mode, accum,
2080 build_int_2 (log, 0), 0, 0);
2082 if (alg.op[opno] == alg_add)
2083 accum = force_operand (gen_rtx (PLUS, mode, tem, accum),
2086 accum = force_operand (gen_rtx (MINUS, mode, tem, accum),
2091 /* Write a REG_EQUAL note on the last insn so that we can cse
2092 multiplication sequences. We need not do this if we were
2093 multiplying by a power of two, since only one insn would have
2096 ??? We could also write REG_EQUAL notes on the last insn of
2097 each sequence that uses a single temporary, but it is not
2098 clear how to calculate the partial product so far.
2100 Torbjorn: Can you do this? */
2102 if (exact_log2 (absval) < 0)
2104 last = get_last_insn ();
2106 = gen_rtx (EXPR_LIST, REG_EQUAL,
2107 gen_rtx (MULT, mode, op0,
2108 negate ? gen_rtx (CONST_INT,
2114 return (negate ? expand_unop (mode, neg_optab, accum, target, 0)
2119 /* This used to use umul_optab if unsigned,
2120 but I think that for non-widening multiply there is no difference
2121 between signed and unsigned. */
2122 op0 = expand_binop (mode, smul_optab,
2123 op0, op1, target, unsignedp, OPTAB_LIB_WIDEN);
2129 /* Emit the code to divide OP0 by OP1, putting the result in TARGET
2130 if that is convenient, and returning where the result is.
2131 You may request either the quotient or the remainder as the result;
2132 specify REM_FLAG nonzero to get the remainder.
2134 CODE is the expression code for which kind of division this is;
2135 it controls how rounding is done. MODE is the machine mode to use.
2136 UNSIGNEDP nonzero means do unsigned division. */
2138 /* ??? For CEIL_MOD_EXPR, can compute incorrect remainder with ANDI
2139 and then correct it by or'ing in missing high bits
2140 if result of ANDI is nonzero.
2141 For ROUND_MOD_EXPR, can use ANDI and then sign-extend the result.
2142 This could optimize to a bfexts instruction.
2143 But C doesn't use these operations, so their optimizations are
2147 expand_divmod (rem_flag, code, mode, op0, op1, target, unsignedp)
2149 enum tree_code code;
2150 enum machine_mode mode;
2151 register rtx op0, op1, target;
2154 register rtx result = 0;
2155 enum machine_mode compute_mode;
2157 int can_clobber_op0;
2158 int mod_insn_no_good = 0;
2159 rtx adjusted_op0 = op0;
2160 optab optab1, optab2;
2162 /* Don't use the function value register as a target
2163 since we have to read it as well as write it,
2164 and function-inlining gets confused by this. */
2165 if (target && REG_P (target) && REG_FUNCTION_VALUE_P (target))
2168 /* Don't clobber an operand while doing a multi-step calculation. */
2170 if ((rem_flag && (reg_mentioned_p (target, op0)
2171 || (GET_CODE (op0) == MEM && GET_CODE (target) == MEM)))
2172 || reg_mentioned_p (target, op1)
2173 || (GET_CODE (op1) == MEM && GET_CODE (target) == MEM))
2176 can_clobber_op0 = (GET_CODE (op0) == REG && op0 == target);
2178 if (GET_CODE (op1) == CONST_INT)
2179 log = exact_log2 (INTVAL (op1));
2181 /* If log is >= 0, we are dividing by 2**log, and will do it by shifting,
2182 which is really floor-division. Otherwise we will really do a divide,
2183 and we assume that is trunc-division.
2185 We must correct the dividend by adding or subtracting something
2186 based on the divisor, in order to do the kind of rounding specified
2187 by CODE. The correction depends on what kind of rounding is actually
2188 available, and that depends on whether we will shift or divide.
2190 In many of these cases it is possible to perform the operation by a
2191 clever series of logical operations (shifts and/or exclusive-ors).
2192 Although avoiding the jump has the advantage that it extends the basic
2193 block and allows further optimization, the branch-free code is normally
2194 at least one instruction longer in the (most common) case where the
2195 dividend is non-negative. Performance measurements of the two
2196 alternatives show that the branch-free code is slightly faster on the
2197 IBM ROMP but slower on CISC processors (significantly slower on the
2198 VAX). Accordingly, the jump code has been retained.
2200 On machines where the jump code is slower, the cost of a DIV or MOD
2201 operation can be set small (less than twice that of an addition); in
2202 that case, we pretend that we don't have a power of two and perform
2203 a normal division or modulus operation. */
2205 if ((code == TRUNC_MOD_EXPR || code == TRUNC_DIV_EXPR)
2207 && (rem_flag ? smod_pow2_cheap : sdiv_pow2_cheap))
2210 /* Get the mode in which to perform this computation. Normally it will
2211 be MODE, but sometimes we can't do the desired operation in MODE.
2212 If so, pick a wider mode in which we can do the operation. Convert
2213 to that mode at the start to avoid repeated conversions.
2215 First see what operations we need. These depend on the expression
2216 we are evaluating. (We assume that divxx3 insns exist under the
2217 same conditions that modxx3 insns and that these insns don't normally
2218 fail. If these assumptions are not correct, we may generate less
2219 efficient code in some cases.)
2221 Then see if we find a mode in which we can open-code that operation
2222 (either a division, modulus, or shift). Finally, check for the smallest
2223 mode for which we can do the operation with a library call. */
2225 optab1 = (log >= 0 ? (unsignedp ? lshr_optab : ashr_optab)
2226 : (unsignedp ? udiv_optab : sdiv_optab));
2227 optab2 = (log >= 0 ? optab1 : (unsignedp ? udivmod_optab : sdivmod_optab));
2229 for (compute_mode = mode; compute_mode != VOIDmode;
2230 compute_mode = GET_MODE_WIDER_MODE (compute_mode))
2231 if (optab1->handlers[(int) compute_mode].insn_code != CODE_FOR_nothing
2232 || optab2->handlers[(int) compute_mode].insn_code != CODE_FOR_nothing)
2235 if (compute_mode == VOIDmode)
2236 for (compute_mode = mode; compute_mode != VOIDmode;
2237 compute_mode = GET_MODE_WIDER_MODE (compute_mode))
2238 if (optab1->handlers[(int) compute_mode].libfunc
2239 || optab2->handlers[(int) compute_mode].libfunc)
2242 /* If we still couldn't find a mode, use MODE; we'll probably abort in
2244 if (compute_mode == VOIDmode)
2245 compute_mode = mode;
2247 /* Now convert to the best mode to use. Show we made a copy of OP0
2248 and hence we can clobber it (we cannot use a SUBREG to widen
2250 if (compute_mode != mode)
2252 adjusted_op0 = op0 = convert_to_mode (compute_mode, op0, unsignedp);
2253 can_clobber_op0 = 1;
2254 op1 = convert_to_mode (compute_mode, op1, unsignedp);
2257 /* If we are computing the remainder and one of the operands is a volatile
2258 MEM, copy it into a register. */
2260 if (rem_flag && GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0))
2261 adjusted_op0 = op0 = force_reg (compute_mode, op0), can_clobber_op0 = 1;
2262 if (rem_flag && GET_CODE (op1) == MEM && MEM_VOLATILE_P (op1))
2263 op1 = force_reg (compute_mode, op1);
2265 if (target == 0 || GET_MODE (target) != compute_mode)
2266 target = gen_reg_rtx (compute_mode);
2270 case TRUNC_MOD_EXPR:
2271 case TRUNC_DIV_EXPR:
2272 if (log >= 0 && ! unsignedp)
2274 rtx label = gen_label_rtx ();
2275 if (! can_clobber_op0)
2277 adjusted_op0 = copy_to_suggested_reg (adjusted_op0, target,
2279 /* Copy op0 to a reg, since emit_cmp_insn will call emit_queue
2280 which will screw up mem refs for autoincrements. */
2281 op0 = force_reg (compute_mode, op0);
2283 emit_cmp_insn (adjusted_op0, const0_rtx, GE, 0, compute_mode, 0, 0);
2284 emit_jump_insn (gen_bge (label));
2285 expand_inc (adjusted_op0, plus_constant (op1, -1));
2287 mod_insn_no_good = 1;
2291 case FLOOR_DIV_EXPR:
2292 case FLOOR_MOD_EXPR:
2293 if (log < 0 && ! unsignedp)
2295 rtx label = gen_label_rtx ();
2296 if (! can_clobber_op0)
2298 adjusted_op0 = copy_to_suggested_reg (adjusted_op0, target,
2300 /* Copy op0 to a reg, since emit_cmp_insn will call emit_queue
2301 which will screw up mem refs for autoincrements. */
2302 op0 = force_reg (compute_mode, op0);
2304 emit_cmp_insn (adjusted_op0, const0_rtx, GE, 0, compute_mode, 0, 0);
2305 emit_jump_insn (gen_bge (label));
2306 expand_dec (adjusted_op0, op1);
2307 expand_inc (adjusted_op0, const1_rtx);
2309 mod_insn_no_good = 1;
2315 if (! can_clobber_op0)
2317 adjusted_op0 = copy_to_suggested_reg (adjusted_op0, target,
2319 /* Copy op0 to a reg, since emit_cmp_insn will call emit_queue
2320 which will screw up mem refs for autoincrements. */
2321 op0 = force_reg (compute_mode, op0);
2328 label = gen_label_rtx ();
2329 emit_cmp_insn (adjusted_op0, const0_rtx, LE, 0, compute_mode, 0, 0);
2330 emit_jump_insn (gen_ble (label));
2332 expand_inc (adjusted_op0, op1);
2333 expand_dec (adjusted_op0, const1_rtx);
2339 adjusted_op0 = expand_binop (compute_mode, add_optab,
2340 adjusted_op0, plus_constant (op1, -1),
2341 0, 0, OPTAB_LIB_WIDEN);
2343 mod_insn_no_good = 1;
2346 case ROUND_DIV_EXPR:
2347 case ROUND_MOD_EXPR:
2348 if (! can_clobber_op0)
2350 adjusted_op0 = copy_to_suggested_reg (adjusted_op0, target,
2352 /* Copy op0 to a reg, since emit_cmp_insn will call emit_queue
2353 which will screw up mem refs for autoincrements. */
2354 op0 = force_reg (compute_mode, op0);
2358 op1 = expand_shift (RSHIFT_EXPR, compute_mode, op1,
2359 integer_one_node, 0, 0);
2362 rtx label = gen_label_rtx ();
2363 emit_cmp_insn (adjusted_op0, const0_rtx, GE, 0, compute_mode, 0, 0);
2364 emit_jump_insn (gen_bge (label));
2365 expand_unop (compute_mode, neg_optab, op1, op1, 0);
2368 expand_inc (adjusted_op0, op1);
2372 op1 = gen_rtx (CONST_INT, VOIDmode, (1 << log) / 2);
2373 expand_inc (adjusted_op0, op1);
2375 mod_insn_no_good = 1;
2379 if (rem_flag && !mod_insn_no_good)
2381 /* Try to produce the remainder directly */
2383 result = expand_binop (compute_mode, and_optab, adjusted_op0,
2384 gen_rtx (CONST_INT, VOIDmode,
2386 target, 1, OPTAB_LIB_WIDEN);
2389 /* See if we can do remainder without a library call. */
2390 result = sign_expand_binop (mode, umod_optab, smod_optab,
2391 adjusted_op0, op1, target,
2392 unsignedp, OPTAB_WIDEN);
2395 /* No luck there. Can we do remainder and divide at once
2396 without a library call? */
2397 result = gen_reg_rtx (compute_mode);
2398 if (! expand_twoval_binop (unsignedp
2399 ? udivmod_optab : sdivmod_optab,
2401 0, result, unsignedp))
2408 return gen_lowpart (mode, result);
2410 /* Produce the quotient. */
2412 result = expand_shift (RSHIFT_EXPR, compute_mode, adjusted_op0,
2413 build_int_2 (log, 0), target, unsignedp);
2414 else if (rem_flag && !mod_insn_no_good)
2415 /* If producing quotient in order to subtract for remainder,
2416 and a remainder subroutine would be ok,
2417 don't use a divide subroutine. */
2418 result = sign_expand_binop (compute_mode, udiv_optab, sdiv_optab,
2419 adjusted_op0, op1, 0, unsignedp, OPTAB_WIDEN);
2422 /* Try a quotient insn, but not a library call. */
2423 result = sign_expand_binop (compute_mode, udiv_optab, sdiv_optab,
2424 adjusted_op0, op1, rem_flag ? 0 : target,
2425 unsignedp, OPTAB_WIDEN);
2428 /* No luck there. Try a quotient-and-remainder insn,
2429 keeping the quotient alone. */
2430 result = gen_reg_rtx (mode);
2431 if (! expand_twoval_binop (unsignedp ? udivmod_optab : sdivmod_optab,
2433 result, 0, unsignedp))
2437 /* If still no luck, use a library call. */
2439 result = sign_expand_binop (compute_mode, udiv_optab, sdiv_optab,
2440 adjusted_op0, op1, rem_flag ? 0 : target,
2441 unsignedp, OPTAB_LIB_WIDEN);
2444 /* If we really want the remainder, get it by subtraction. */
2448 /* No divide instruction either. Use library for remainder. */
2449 result = sign_expand_binop (compute_mode, umod_optab, smod_optab,
2451 unsignedp, OPTAB_LIB_WIDEN);
2454 /* We divided. Now finish doing X - Y * (X / Y). */
2455 result = expand_mult (compute_mode, result, op1, target, unsignedp);
2456 if (! result) abort ();
2457 result = expand_binop (compute_mode, sub_optab, op0,
2458 result, target, unsignedp, OPTAB_LIB_WIDEN);
2465 return gen_lowpart (mode, result);
2468 /* Return a tree node with data type TYPE, describing the value of X.
2469 Usually this is an RTL_EXPR, if there is no obvious better choice.
2470 X may be an expression, however we only support those expressions
2471 generated by loop.c. */
2480 switch (GET_CODE (x))
2483 t = build_int_2 (INTVAL (x),
2484 ! TREE_UNSIGNED (type) && INTVAL (x) >= 0 ? 0 : -1);
2485 TREE_TYPE (t) = type;
2489 if (GET_MODE (x) == VOIDmode)
2491 t = build_int_2 (CONST_DOUBLE_LOW (x), CONST_DOUBLE_HIGH (x));
2492 TREE_TYPE (t) = type;
2498 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
2499 t = build_real (type, d);
2505 return fold (build (PLUS_EXPR, type, make_tree (type, XEXP (x, 0)),
2506 make_tree (type, XEXP (x, 1))));
2509 return fold (build (MINUS_EXPR, type, make_tree (type, XEXP (x, 0)),
2510 make_tree (type, XEXP (x, 1))));
2513 return fold (build1 (NEGATE_EXPR, type, make_tree (type, XEXP (x, 0))));
2516 return fold (build (MULT_EXPR, type, make_tree (type, XEXP (x, 0)),
2517 make_tree (type, XEXP (x, 1))));
2520 return fold (build (LSHIFT_EXPR, type, make_tree (type, XEXP (x, 0)),
2521 make_tree (type, XEXP (x, 1))));
2524 return fold (convert (type,
2525 build (RSHIFT_EXPR, unsigned_type (type),
2526 make_tree (unsigned_type (type),
2528 make_tree (type, XEXP (x, 1)))));
2531 return fold (convert (type,
2532 build (RSHIFT_EXPR, signed_type (type),
2533 make_tree (signed_type (type), XEXP (x, 0)),
2534 make_tree (type, XEXP (x, 1)))));
2537 if (TREE_CODE (type) != REAL_TYPE)
2538 t = signed_type (type);
2542 return fold (convert (type,
2543 build (TRUNC_DIV_EXPR, t,
2544 make_tree (t, XEXP (x, 0)),
2545 make_tree (t, XEXP (x, 1)))));
2547 t = unsigned_type (type);
2548 return fold (convert (type,
2549 build (TRUNC_DIV_EXPR, t,
2550 make_tree (t, XEXP (x, 0)),
2551 make_tree (t, XEXP (x, 1)))));
2553 t = make_node (RTL_EXPR);
2554 TREE_TYPE (t) = type;
2555 RTL_EXPR_RTL (t) = x;
2556 /* There are no insns to be output
2557 when this rtl_expr is used. */
2558 RTL_EXPR_SEQUENCE (t) = 0;
2563 /* Return an rtx representing the value of X * MULT + ADD.
2564 TARGET is a suggestion for where to store the result (an rtx).
2565 MODE is the machine mode for the computation.
2566 X and MULT must have mode MODE. ADD may have a different mode.
2567 So can X (defaults to same as MODE).
2568 UNSIGNEDP is non-zero to do unsigned multiplication.
2569 This may emit insns. */
2572 expand_mult_add (x, target, mult, add, mode, unsignedp)
2573 rtx x, target, mult, add;
2574 enum machine_mode mode;
2577 tree type = type_for_mode (mode, unsignedp);
2578 tree add_type = (GET_MODE (add) == VOIDmode
2579 ? type : type_for_mode (GET_MODE (add), unsignedp));
2580 tree result = fold (build (PLUS_EXPR, type,
2581 fold (build (MULT_EXPR, type,
2582 make_tree (type, x),
2583 make_tree (type, mult))),
2584 make_tree (add_type, add)));
2586 return expand_expr (result, target, VOIDmode, 0);
2589 /* Compute the logical-and of OP0 and OP1, storing it in TARGET
2590 and returning TARGET.
2592 If TARGET is 0, a pseudo-register or constant is returned. */
2595 expand_and (op0, op1, target)
2596 rtx op0, op1, target;
2598 enum machine_mode mode = VOIDmode;
2601 if (GET_MODE (op0) != VOIDmode)
2602 mode = GET_MODE (op0);
2603 else if (GET_MODE (op1) != VOIDmode)
2604 mode = GET_MODE (op1);
2606 if (mode != VOIDmode)
2607 tem = expand_binop (mode, and_optab, op0, op1, target, 0, OPTAB_LIB_WIDEN);
2608 else if (GET_CODE (op0) == CONST_INT && GET_CODE (op1) == CONST_INT)
2609 tem = gen_rtx (CONST_INT, VOIDmode, INTVAL (op0) & INTVAL (op1));
2615 else if (tem != target)
2616 emit_move_insn (target, tem);
2620 /* Emit a store-flags instruction for comparison CODE on OP0 and OP1
2621 and storing in TARGET. Normally return TARGET.
2622 Return 0 if that cannot be done.
2624 MODE is the mode to use for OP0 and OP1 should they be CONST_INTs. If
2625 it is VOIDmode, they cannot both be CONST_INT.
2627 UNSIGNEDP is for the case where we have to widen the operands
2628 to perform the operation. It says to use zero-extension.
2630 NORMALIZEP is 1 if we should convert the result to be either zero
2631 or one one. Normalize is -1 if we should convert the result to be
2632 either zero or -1. If NORMALIZEP is zero, the result will be left
2633 "raw" out of the scc insn. */
2636 emit_store_flag (target, code, op0, op1, mode, unsignedp, normalizep)
2640 enum machine_mode mode;
2645 enum insn_code icode;
2646 enum machine_mode compare_mode;
2647 enum machine_mode target_mode = GET_MODE (target);
2650 rtx pattern, comparison;
2652 if (mode == VOIDmode)
2653 mode = GET_MODE (op0);
2655 /* For some comparisons with 1 and -1, we can convert this to
2656 comparisons with zero. This will often produce more opportunities for
2657 store-flag insns. */
2662 if (op1 == const1_rtx)
2663 op1 = const0_rtx, code = LE;
2666 if (op1 == constm1_rtx)
2667 op1 = const0_rtx, code = LT;
2670 if (op1 == const1_rtx)
2671 op1 = const0_rtx, code = GT;
2674 if (op1 == constm1_rtx)
2675 op1 = const0_rtx, code = GE;
2678 if (op1 == const1_rtx)
2679 op1 = const0_rtx, code = NE;
2682 if (op1 == const1_rtx)
2683 op1 = const0_rtx, code = EQ;
2687 /* From now on, we won't change CODE, so set ICODE now. */
2688 icode = setcc_gen_code[(int) code];
2690 /* If this is A < 0 or A >= 0, we can do this by taking the ones
2691 complement of A (for GE) and shifting the sign bit to the low bit. */
2692 if (op1 == const0_rtx && (code == LT || code == GE)
2693 && GET_MODE_CLASS (mode) == MODE_INT
2694 && (normalizep || STORE_FLAG_VALUE == 1
2695 || (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_INT
2696 && STORE_FLAG_VALUE == 1 << (GET_MODE_BITSIZE (mode) - 1))))
2698 rtx subtarget = target;
2700 /* If the result is to be wider than OP0, it is best to convert it
2701 first. If it is to be narrower, it is *incorrect* to convert it
2703 if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (mode))
2705 op0 = convert_to_mode (target_mode, op0, 0);
2709 if (target_mode != mode)
2713 op0 = expand_unop (mode, one_cmpl_optab, op0, subtarget, 0);
2715 if (normalizep || STORE_FLAG_VALUE == 1)
2716 /* If we are supposed to produce a 0/1 value, we want to do
2717 a logical shift from the sign bit to the low-order bit; for
2718 a -1/0 value, we do an arithmetic shift. */
2719 op0 = expand_shift (RSHIFT_EXPR, mode, op0,
2720 size_int (GET_MODE_BITSIZE (mode) - 1),
2721 subtarget, normalizep != -1);
2723 if (mode != target_mode)
2724 op0 = convert_to_mode (target_mode, op0, 0);
2729 if (icode != CODE_FOR_nothing)
2731 /* We think we may be able to do this with a scc insn. Emit the
2732 comparison and then the scc insn.
2734 compare_from_rtx may call emit_queue, which would be deleted below
2735 if the scc insn fails. So call it ourselves before setting LAST. */
2738 last = get_last_insn ();
2740 comparison = compare_from_rtx (op0, op1, code, unsignedp, mode, 0, 0);
2741 if (GET_CODE (comparison) == CONST_INT)
2742 return (comparison == const0_rtx ? const0_rtx
2743 : normalizep == 1 ? const1_rtx
2744 : normalizep == -1 ? constm1_rtx
2747 /* Get a reference to the target in the proper mode for this insn. */
2748 compare_mode = insn_operand_mode[(int) icode][0];
2750 if (preserve_subexpressions_p ()
2751 || ! (*insn_operand_predicate[(int) icode][0]) (subtarget, compare_mode))
2752 subtarget = gen_reg_rtx (compare_mode);
2754 pattern = GEN_FCN (icode) (subtarget);
2757 emit_insn (pattern);
2759 /* If we are converting to a wider mode, first convert to
2760 TARGET_MODE, then normalize. This produces better combining
2761 opportunities on machines that have a SIGN_EXTRACT when we are
2762 testing a single bit. This mostly benefits the 68k.
2764 If STORE_FLAG_VALUE does not have the sign bit set when
2765 interpreted in COMPARE_MODE, we can do this conversion as
2766 unsigned, which is usually more efficient. */
2767 if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (compare_mode))
2769 convert_move (target, subtarget,
2770 (GET_MODE_BITSIZE (compare_mode)
2771 <= HOST_BITS_PER_INT)
2772 && 0 == (STORE_FLAG_VALUE
2773 & (1 << (GET_MODE_BITSIZE (compare_mode) -1))));
2775 compare_mode = target_mode;
2780 /* Now normalize to the proper value in COMPARE_MODE. Sometimes
2781 we don't have to do anything. */
2782 if (normalizep == 0 || normalizep == STORE_FLAG_VALUE)
2784 else if (normalizep == - STORE_FLAG_VALUE)
2785 op0 = expand_unop (compare_mode, neg_optab, op0, subtarget, 0);
2787 /* We don't want to use STORE_FLAG_VALUE < 0 below since this
2788 makes it hard to use a value of just the sign bit due to
2789 ANSI integer constant typing rules. */
2790 else if (GET_MODE_BITSIZE (compare_mode) <= HOST_BITS_PER_INT
2791 && (STORE_FLAG_VALUE
2792 & (1 << (GET_MODE_BITSIZE (compare_mode) - 1))))
2793 op0 = expand_shift (RSHIFT_EXPR, compare_mode, op0,
2794 size_int (GET_MODE_BITSIZE (compare_mode) - 1),
2795 subtarget, normalizep == 1);
2796 else if (STORE_FLAG_VALUE & 1)
2798 op0 = expand_and (op0, const1_rtx, subtarget);
2799 if (normalizep == -1)
2800 op0 = expand_unop (compare_mode, neg_optab, op0, op0, 0);
2805 /* If we were converting to a smaller mode, do the
2807 if (target_mode != compare_mode)
2809 convert_move (target, op0);
2818 delete_insns_since (last);
2820 subtarget = target_mode == mode ? target : 0;
2822 /* If we reached here, we can't do this with a scc insn. However, there
2823 are some comparisons that can be done directly. For example, if
2824 this is an equality comparison of integers, we can try to exclusive-or
2825 (or subtract) the two operands and use a recursive call to try the
2826 comparison with zero. Don't do any of these cases if branches are
2829 if (BRANCH_COST >= 0
2830 && GET_MODE_CLASS (mode) == MODE_INT && (code == EQ || code == NE)
2831 && op1 != const0_rtx)
2833 tem = expand_binop (mode, xor_optab, op0, op1, subtarget, 1,
2837 tem = expand_binop (mode, sub_optab, op0, op1, subtarget, 1,
2840 tem = emit_store_flag (target, code, tem, const0_rtx,
2841 mode, unsignedp, normalizep);
2843 delete_insns_since (last);
2847 /* Some other cases we can do are EQ, NE, LE, and GT comparisons with
2848 the constant zero. Reject all other comparisons at this point. Only
2849 do LE and GT if branches are expensive since they are expensive on
2850 2-operand machines. */
2852 if (BRANCH_COST == 0
2853 || GET_MODE_CLASS (mode) != MODE_INT || op1 != const0_rtx
2854 || (code != EQ && code != NE
2855 && (BRANCH_COST <= 1 || (code != LE && code != GT))))
2858 /* See what we need to return. We can only return a 1, -1, or the
2861 if (normalizep == 0)
2863 if (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
2864 normalizep = STORE_FLAG_VALUE;
2866 else if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_INT
2867 && STORE_FLAG_VALUE == 1 << (GET_MODE_BITSIZE (mode) - 1))
2873 /* Try to put the result of the comparison in the sign bit. Assume we can't
2874 do the necessary operation below. */
2878 /* To see if A <= 0, compute (A | (A - 1)). A <= 0 iff that result has
2879 the sign bit set. */
2883 /* This is destructive, so SUBTARGET can't be OP0. */
2884 if (rtx_equal_p (subtarget, op0))
2887 tem = expand_binop (mode, sub_optab, op0, const1_rtx, subtarget, 0,
2890 tem = expand_binop (mode, ior_optab, op0, tem, subtarget, 0,
2894 /* To see if A > 0, compute (((signed) A) << BITS) - A, where BITS is the
2895 number of bits in the mode of OP0, minus one. */
2899 if (rtx_equal_p (subtarget, op0))
2902 tem = expand_shift (RSHIFT_EXPR, mode, op0,
2903 size_int (GET_MODE_BITSIZE (mode) - 1),
2905 tem = expand_binop (mode, sub_optab, tem, op0, subtarget, 0,
2909 if (code == EQ || code == NE)
2911 /* For EQ or NE, one way to do the comparison is to apply an operation
2912 that converts the operand into a positive number if it is non-zero
2913 or zero if it was originally zero. Then, for EQ, we subtract 1 and
2914 for NE we negate. This puts the result in the sign bit. Then we
2915 normalize with a shift, if needed.
2917 Two operations that can do the above actions are ABS and FFS, so try
2918 them. If that doesn't work, and MODE is smaller than a full word,
2919 we can use zero-extension to the wider mode (an unsigned conversion)
2920 as the operation. */
2922 if (abs_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
2923 tem = expand_unop (mode, abs_optab, op0, subtarget, 1);
2924 else if (ffs_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
2925 tem = expand_unop (mode, ffs_optab, op0, subtarget, 1);
2926 else if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
2929 tem = convert_to_mode (mode, op0, 1);
2935 tem = expand_binop (mode, sub_optab, tem, const1_rtx, subtarget,
2938 tem = expand_unop (mode, neg_optab, tem, subtarget, 0);
2941 /* If we couldn't do it that way, for NE we can "or" the two's complement
2942 of the value with itself. For EQ, we take the one's complement of
2943 that "or", which is an extra insn, so we only handle EQ if branches
2946 if (tem == 0 && (code == NE || BRANCH_COST > 1))
2948 if (rtx_equal_p (subtarget, op0))
2951 tem = expand_unop (mode, neg_optab, op0, subtarget, 0);
2952 tem = expand_binop (mode, ior_optab, tem, op0, subtarget, 0,
2955 if (tem && code == EQ)
2956 tem = expand_unop (mode, one_cmpl_optab, tem, subtarget, 0);
2960 if (tem && normalizep)
2961 tem = expand_shift (RSHIFT_EXPR, mode, tem,
2962 size_int (GET_MODE_BITSIZE (mode) - 1),
2963 tem, normalizep == 1);
2965 if (tem && GET_MODE (tem) != target_mode)
2967 convert_move (target, tem, 0);
2972 delete_insns_since (last);
2976 emit_jump_insn ((*bcc_gen_fctn[(int) code]) (label));
2977 emit_move_insn (target, const1_rtx);