1 /* Medium-level subroutines: convert bit-field store and extract
2 and shifts, multiplies and divides to rtl instructions.
3 Copyright (C) 1987, 1988, 1989, 1992 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
26 #include "insn-flags.h"
27 #include "insn-codes.h"
28 #include "insn-config.h"
33 static rtx extract_split_bit_field ();
34 static rtx extract_fixed_bit_field ();
35 static void store_split_bit_field ();
36 static void store_fixed_bit_field ();
37 static rtx mask_rtx ();
38 static rtx lshift_value ();
40 #define CEIL(x,y) (((x) + (y) - 1) / (y))
42 /* Non-zero means multiply instructions are cheaper than shifts. */
43 int mult_is_very_cheap;
45 /* Non-zero means divides or modulus operations are relatively cheap for
46 powers of two, so don't use branches; emit the operation instead.
47 Usually, this will mean that the MD file will emit non-branch
50 static int sdiv_pow2_cheap, smod_pow2_cheap;
52 /* Cost of various pieces of RTL. */
53 static int add_cost, mult_cost, negate_cost, zero_cost;
54 static int shift_cost[BITS_PER_WORD];
55 static int shiftadd_cost[BITS_PER_WORD];
56 static int shiftsub_cost[BITS_PER_WORD];
62 /* This is "some random pseudo register" for purposes of calling recog
63 to see what insns exist. */
64 rtx reg = gen_rtx (REG, word_mode, FIRST_PSEUDO_REGISTER);
65 rtx shift_insn, shiftadd_insn, shiftsub_insn;
71 /* Since we are on the permanent obstack, we must be sure we save this
72 spot AFTER we call start_sequence, since it will reuse the rtl it
75 free_point = (char *) oballoc (0);
77 zero_cost = rtx_cost (const0_rtx);
78 add_cost = rtx_cost (gen_rtx (PLUS, word_mode, reg, reg), SET);
80 shift_insn = emit_insn (gen_rtx (SET, VOIDmode, reg,
81 gen_rtx (ASHIFT, word_mode, reg,
84 shiftadd_insn = emit_insn (gen_rtx (SET, VOIDmode, reg,
85 gen_rtx (PLUS, word_mode,
86 gen_rtx (MULT, word_mode,
90 shiftsub_insn = emit_insn (gen_rtx (SET, VOIDmode, reg,
91 gen_rtx (MINUS, word_mode,
92 gen_rtx (MULT, word_mode,
99 shiftadd_cost[0] = shiftsub_cost[0] = add_cost;
101 for (m = 1; m < BITS_PER_WORD; m++)
103 shift_cost[m] = shiftadd_cost[m] = shiftsub_cost[m] = 32000;
105 XEXP (SET_SRC (PATTERN (shift_insn)), 1) = GEN_INT (m);
106 if (recog (PATTERN (shift_insn), shift_insn, &dummy) >= 0)
107 shift_cost[m] = rtx_cost (SET_SRC (PATTERN (shift_insn)), SET);
109 XEXP (XEXP (SET_SRC (PATTERN (shiftadd_insn)), 0), 1)
110 = GEN_INT ((HOST_WIDE_INT) 1 << m);
111 if (recog (PATTERN (shiftadd_insn), shiftadd_insn, &dummy) >= 0)
112 shiftadd_cost[m] = rtx_cost (PATTERN (SET_SRC (shiftadd_insn)), SET);
114 XEXP (XEXP (SET_SRC (PATTERN (shiftsub_insn)), 0), 1)
115 = GEN_INT ((HOST_WIDE_INT) 1 << m);
116 if (recog (PATTERN (shiftsub_insn), shiftsub_insn, &dummy) >= 0)
117 shiftsub_cost[m] = rtx_cost (PATTERN (SET_SRC (shiftsub_insn)), SET);
120 mult_cost = rtx_cost (gen_rtx (MULT, word_mode, reg, reg), SET);
121 negate_cost = rtx_cost (gen_rtx (NEG, word_mode, reg), SET);
123 /* 999999 is chosen to avoid any plausible faster special case. */
125 = (rtx_cost (gen_rtx (MULT, word_mode, reg, GEN_INT (999999)), SET)
126 < rtx_cost (gen_rtx (ASHIFT, word_mode, reg, GEN_INT (7)), SET));
129 = (rtx_cost (gen_rtx (DIV, word_mode, reg, GEN_INT (32)), SET)
132 = (rtx_cost (gen_rtx (MOD, word_mode, reg, GEN_INT (32)), SET)
135 /* Free the objects we just allocated. */
140 /* Return an rtx representing minus the value of X.
141 MODE is the intended mode of the result,
142 useful if X is a CONST_INT. */
146 enum machine_mode mode;
149 if (GET_CODE (x) == CONST_INT)
151 HOST_WIDE_INT val = - INTVAL (x);
152 if (GET_MODE_BITSIZE (mode) < HOST_BITS_PER_WIDE_INT)
154 /* Sign extend the value from the bits that are significant. */
155 if (val & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1)))
156 val |= (HOST_WIDE_INT) (-1) << GET_MODE_BITSIZE (mode);
158 val &= ((HOST_WIDE_INT) 1 << GET_MODE_BITSIZE (mode)) - 1;
160 return GEN_INT (val);
163 return expand_unop (GET_MODE (x), neg_optab, x, NULL_RTX, 0);
166 /* Generate code to store value from rtx VALUE
167 into a bit-field within structure STR_RTX
168 containing BITSIZE bits starting at bit BITNUM.
169 FIELDMODE is the machine-mode of the FIELD_DECL node for this field.
170 ALIGN is the alignment that STR_RTX is known to have, measured in bytes.
171 TOTAL_SIZE is the size of the structure in bytes, or -1 if varying. */
173 /* ??? Note that there are two different ideas here for how
174 to determine the size to count bits within, for a register.
175 One is BITS_PER_WORD, and the other is the size of operand 3
176 of the insv pattern. (The latter assumes that an n-bit machine
177 will be able to insert bit fields up to n bits wide.)
178 It isn't certain that either of these is right.
179 extract_bit_field has the same quandary. */
182 store_bit_field (str_rtx, bitsize, bitnum, fieldmode, value, align, total_size)
184 register int bitsize;
186 enum machine_mode fieldmode;
191 int unit = (GET_CODE (str_rtx) == MEM) ? BITS_PER_UNIT : BITS_PER_WORD;
192 register int offset = bitnum / unit;
193 register int bitpos = bitnum % unit;
194 register rtx op0 = str_rtx;
196 if (GET_CODE (str_rtx) == MEM && ! MEM_IN_STRUCT_P (str_rtx))
199 /* Discount the part of the structure before the desired byte.
200 We need to know how many bytes are safe to reference after it. */
202 total_size -= (bitpos / BIGGEST_ALIGNMENT
203 * (BIGGEST_ALIGNMENT / BITS_PER_UNIT));
205 while (GET_CODE (op0) == SUBREG)
207 /* The following line once was done only if WORDS_BIG_ENDIAN,
208 but I think that is a mistake. WORDS_BIG_ENDIAN is
209 meaningful at a much higher level; when structures are copied
210 between memory and regs, the higher-numbered regs
211 always get higher addresses. */
212 offset += SUBREG_WORD (op0);
213 /* We used to adjust BITPOS here, but now we do the whole adjustment
214 right after the loop. */
215 op0 = SUBREG_REG (op0);
219 /* If OP0 is a register, BITPOS must count within a word.
220 But as we have it, it counts within whatever size OP0 now has.
221 On a bigendian machine, these are not the same, so convert. */
222 if (GET_CODE (op0) != MEM && unit > GET_MODE_BITSIZE (GET_MODE (op0)))
223 bitpos += unit - GET_MODE_BITSIZE (GET_MODE (op0));
226 value = protect_from_queue (value, 0);
229 value = force_not_mem (value);
231 /* Note that the adjustment of BITPOS above has no effect on whether
232 BITPOS is 0 in a REG bigger than a word. */
233 if (GET_MODE_SIZE (fieldmode) >= UNITS_PER_WORD
234 && (! STRICT_ALIGNMENT || GET_CODE (op0) != MEM)
235 && bitpos == 0 && bitsize == GET_MODE_BITSIZE (fieldmode))
237 /* Storing in a full-word or multi-word field in a register
238 can be done with just SUBREG. */
239 if (GET_MODE (op0) != fieldmode)
240 if (GET_CODE (op0) == REG)
241 op0 = gen_rtx (SUBREG, fieldmode, op0, offset);
243 op0 = change_address (op0, fieldmode,
244 plus_constant (XEXP (op0, 0), offset));
245 emit_move_insn (op0, value);
249 /* Storing an lsb-aligned field in a register
250 can be done with a movestrict instruction. */
252 if (GET_CODE (op0) != MEM
254 && bitpos + bitsize == unit
258 && bitsize == GET_MODE_BITSIZE (fieldmode)
259 && (GET_MODE (op0) == fieldmode
260 || (movstrict_optab->handlers[(int) fieldmode].insn_code
261 != CODE_FOR_nothing)))
263 /* Get appropriate low part of the value being stored. */
264 if (GET_CODE (value) == CONST_INT || GET_CODE (value) == REG)
265 value = gen_lowpart (fieldmode, value);
266 else if (!(GET_CODE (value) == SYMBOL_REF
267 || GET_CODE (value) == LABEL_REF
268 || GET_CODE (value) == CONST))
269 value = convert_to_mode (fieldmode, value, 0);
271 if (GET_MODE (op0) == fieldmode)
272 emit_move_insn (op0, value);
275 int icode = movstrict_optab->handlers[(int) fieldmode].insn_code;
276 if(! (*insn_operand_predicate[icode][1]) (value, fieldmode))
277 value = copy_to_mode_reg (fieldmode, value);
278 emit_insn (GEN_FCN (icode)
279 (gen_rtx (SUBREG, fieldmode, op0, offset), value));
284 /* Handle fields bigger than a word. */
286 if (bitsize > BITS_PER_WORD)
288 /* Here we transfer the words of the field
289 in the order least significant first.
290 This is because the most significant word is the one which may
291 be less than full. */
293 int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD;
296 /* This is the mode we must force value to, so that there will be enough
297 subwords to extract. Note that fieldmode will often (always?) be
298 VOIDmode, because that is what store_field uses to indicate that this
299 is a bit field, but passing VOIDmode to operand_subword_force will
300 result in an abort. */
301 fieldmode = mode_for_size (nwords * BITS_PER_WORD, MODE_INT, 0);
303 for (i = 0; i < nwords; i++)
305 /* If I is 0, use the low-order word in both field and target;
306 if I is 1, use the next to lowest word; and so on. */
307 int wordnum = (WORDS_BIG_ENDIAN ? nwords - i - 1 : i);
308 int bit_offset = (WORDS_BIG_ENDIAN
309 ? MAX (bitsize - (i + 1) * BITS_PER_WORD, 0)
310 : i * BITS_PER_WORD);
311 store_bit_field (op0, MIN (BITS_PER_WORD,
312 bitsize - i * BITS_PER_WORD),
313 bitnum + bit_offset, word_mode,
314 operand_subword_force (value, wordnum, fieldmode),
320 /* From here on we can assume that the field to be stored in is
321 a full-word (whatever type that is), since it is shorter than a word. */
323 /* OFFSET is the number of words or bytes (UNIT says which)
324 from STR_RTX to the first word or byte containing part of the field. */
326 if (GET_CODE (op0) == REG)
329 || GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD)
330 op0 = gen_rtx (SUBREG, TYPE_MODE (type_for_size (BITS_PER_WORD, 0)),
336 op0 = protect_from_queue (op0, 1);
339 /* Now OFFSET is nonzero only if OP0 is memory
340 and is therefore always measured in bytes. */
344 && !(bitsize == 1 && GET_CODE (value) == CONST_INT)
345 /* Ensure insv's size is wide enough for this field. */
346 && (GET_MODE_BITSIZE (insn_operand_mode[(int) CODE_FOR_insv][3])
349 int xbitpos = bitpos;
352 rtx last = get_last_insn ();
354 enum machine_mode maxmode
355 = insn_operand_mode[(int) CODE_FOR_insv][3];
357 int save_volatile_ok = volatile_ok;
360 /* If this machine's insv can only insert into a register, or if we
361 are to force MEMs into a register, copy OP0 into a register and
362 save it back later. */
363 if (GET_CODE (op0) == MEM
365 || ! ((*insn_operand_predicate[(int) CODE_FOR_insv][0])
369 enum machine_mode bestmode;
371 /* Get the mode to use for inserting into this field. If OP0 is
372 BLKmode, get the smallest mode consistent with the alignment. If
373 OP0 is a non-BLKmode object that is no wider than MAXMODE, use its
374 mode. Otherwise, use the smallest mode containing the field. */
376 if (GET_MODE (op0) == BLKmode
377 || GET_MODE_SIZE (GET_MODE (op0)) > GET_MODE_SIZE (maxmode))
379 = get_best_mode (bitsize, bitnum, align * BITS_PER_UNIT, maxmode,
380 MEM_VOLATILE_P (op0));
382 bestmode = GET_MODE (op0);
384 if (bestmode == VOIDmode)
387 /* Adjust address to point to the containing unit of that mode. */
388 unit = GET_MODE_BITSIZE (bestmode);
389 /* Compute offset as multiple of this unit, counting in bytes. */
390 offset = (bitnum / unit) * GET_MODE_SIZE (bestmode);
391 bitpos = bitnum % unit;
392 op0 = change_address (op0, bestmode,
393 plus_constant (XEXP (op0, 0), offset));
395 /* Fetch that unit, store the bitfield in it, then store the unit. */
396 tempreg = copy_to_reg (op0);
397 store_bit_field (tempreg, bitsize, bitpos, fieldmode, value,
399 emit_move_insn (op0, tempreg);
402 volatile_ok = save_volatile_ok;
404 /* Add OFFSET into OP0's address. */
405 if (GET_CODE (xop0) == MEM)
406 xop0 = change_address (xop0, byte_mode,
407 plus_constant (XEXP (xop0, 0), offset));
409 /* If xop0 is a register, we need it in MAXMODE
410 to make it acceptable to the format of insv. */
411 if (GET_CODE (xop0) == SUBREG)
412 PUT_MODE (xop0, maxmode);
413 if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode)
414 xop0 = gen_rtx (SUBREG, maxmode, xop0, 0);
416 /* On big-endian machines, we count bits from the most significant.
417 If the bit field insn does not, we must invert. */
419 #if BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN
420 xbitpos = unit - bitsize - xbitpos;
422 /* We have been counting XBITPOS within UNIT.
423 Count instead within the size of the register. */
425 if (GET_CODE (xop0) != MEM)
426 xbitpos += GET_MODE_BITSIZE (maxmode) - unit;
428 unit = GET_MODE_BITSIZE (maxmode);
430 /* Convert VALUE to maxmode (which insv insn wants) in VALUE1. */
432 if (GET_MODE (value) != maxmode)
434 if (GET_MODE_BITSIZE (GET_MODE (value)) >= bitsize)
436 /* Optimization: Don't bother really extending VALUE
437 if it has all the bits we will actually use. However,
438 if we must narrow it, be sure we do it correctly. */
440 if (GET_MODE_SIZE (GET_MODE (value)) < GET_MODE_SIZE (maxmode))
442 /* Avoid making subreg of a subreg, or of a mem. */
443 if (GET_CODE (value1) != REG)
444 value1 = copy_to_reg (value1);
445 value1 = gen_rtx (SUBREG, maxmode, value1, 0);
448 value1 = gen_lowpart (maxmode, value1);
450 else if (!CONSTANT_P (value))
451 /* Parse phase is supposed to make VALUE's data type
452 match that of the component reference, which is a type
453 at least as wide as the field; so VALUE should have
454 a mode that corresponds to that type. */
458 /* If this machine's insv insists on a register,
459 get VALUE1 into a register. */
460 if (! ((*insn_operand_predicate[(int) CODE_FOR_insv][3])
462 value1 = force_reg (maxmode, value1);
464 pat = gen_insv (xop0, GEN_INT (bitsize), GEN_INT (xbitpos), value1);
469 delete_insns_since (last);
470 store_fixed_bit_field (op0, offset, bitsize, bitpos, value, align);
476 /* Insv is not available; store using shifts and boolean ops. */
477 store_fixed_bit_field (op0, offset, bitsize, bitpos, value, align);
481 /* Use shifts and boolean operations to store VALUE
482 into a bit field of width BITSIZE
483 in a memory location specified by OP0 except offset by OFFSET bytes.
484 (OFFSET must be 0 if OP0 is a register.)
485 The field starts at position BITPOS within the byte.
486 (If OP0 is a register, it may be a full word or a narrower mode,
487 but BITPOS still counts within a full word,
488 which is significant on bigendian machines.)
489 STRUCT_ALIGN is the alignment the structure is known to have (in bytes).
491 Note that protect_from_queue has already been done on OP0 and VALUE. */
494 store_fixed_bit_field (op0, offset, bitsize, bitpos, value, struct_align)
496 register int offset, bitsize, bitpos;
500 register enum machine_mode mode;
501 int total_bits = BITS_PER_WORD;
506 /* Add OFFSET to OP0's address (if it is in memory)
507 and if a single byte contains the whole bit field
508 change OP0 to a byte. */
510 /* There is a case not handled here:
511 a structure with a known alignment of just a halfword
512 and a field split across two aligned halfwords within the structure.
513 Or likewise a structure with a known alignment of just a byte
514 and a field split across two bytes.
515 Such cases are not supposed to be able to occur. */
517 if (GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
521 /* Special treatment for a bit field split across two registers. */
522 if (bitsize + bitpos > BITS_PER_WORD)
524 store_split_bit_field (op0, bitsize, bitpos, value, BITS_PER_WORD);
530 /* Get the proper mode to use for this field. We want a mode that
531 includes the entire field. If such a mode would be larger than
532 a word, we won't be doing the extraction the normal way. */
534 mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT,
535 struct_align * BITS_PER_UNIT, word_mode,
536 GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0));
538 if (mode == VOIDmode)
540 /* The only way this should occur is if the field spans word
542 store_split_bit_field (op0, bitsize, bitpos + offset * BITS_PER_UNIT,
543 value, struct_align);
547 total_bits = GET_MODE_BITSIZE (mode);
549 /* Get ref to an aligned byte, halfword, or word containing the field.
550 Adjust BITPOS to be position within a word,
551 and OFFSET to be the offset of that word.
552 Then alter OP0 to refer to that word. */
553 bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT;
554 offset -= (offset % (total_bits / BITS_PER_UNIT));
555 op0 = change_address (op0, mode,
556 plus_constant (XEXP (op0, 0), offset));
559 mode = GET_MODE (op0);
561 /* Now MODE is either some integral mode for a MEM as OP0,
562 or is a full-word for a REG as OP0. TOTAL_BITS corresponds.
563 The bit field is contained entirely within OP0.
564 BITPOS is the starting bit number within OP0.
565 (OP0's mode may actually be narrower than MODE.) */
568 /* BITPOS is the distance between our msb
569 and that of the containing datum.
570 Convert it to the distance from the lsb. */
572 bitpos = total_bits - bitsize - bitpos;
574 /* Now BITPOS is always the distance between our lsb
577 /* Shift VALUE left by BITPOS bits. If VALUE is not constant,
578 we must first convert its mode to MODE. */
580 if (GET_CODE (value) == CONST_INT)
582 register HOST_WIDE_INT v = INTVAL (value);
584 if (bitsize < HOST_BITS_PER_WIDE_INT)
585 v &= ((HOST_WIDE_INT) 1 << bitsize) - 1;
589 else if ((bitsize < HOST_BITS_PER_WIDE_INT
590 && v == ((HOST_WIDE_INT) 1 << bitsize) - 1)
591 || (bitsize == HOST_BITS_PER_WIDE_INT && v == -1))
594 value = lshift_value (mode, value, bitpos, bitsize);
598 int must_and = (GET_MODE_BITSIZE (GET_MODE (value)) != bitsize
599 && bitpos + bitsize != GET_MODE_BITSIZE (mode));
601 if (GET_MODE (value) != mode)
603 /* If VALUE is a floating-point mode, access it as an integer
604 of the corresponding size, then convert it. This can occur on
605 a machine with 64 bit registers that uses SFmode for float. */
606 if (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT)
608 if (GET_CODE (value) != REG)
609 value = copy_to_reg (value);
611 = gen_rtx (SUBREG, word_mode, value, 0);
614 if ((GET_CODE (value) == REG || GET_CODE (value) == SUBREG)
615 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (value)))
616 value = gen_lowpart (mode, value);
618 value = convert_to_mode (mode, value, 1);
622 value = expand_binop (mode, and_optab, value,
623 mask_rtx (mode, 0, bitsize, 0),
624 NULL_RTX, 1, OPTAB_LIB_WIDEN);
626 value = expand_shift (LSHIFT_EXPR, mode, value,
627 build_int_2 (bitpos, 0), NULL_RTX, 1);
630 /* Now clear the chosen bits in OP0,
631 except that if VALUE is -1 we need not bother. */
633 subtarget = (GET_CODE (op0) == REG || ! flag_force_mem) ? op0 : 0;
637 temp = expand_binop (mode, and_optab, op0,
638 mask_rtx (mode, bitpos, bitsize, 1),
639 subtarget, 1, OPTAB_LIB_WIDEN);
645 /* Now logical-or VALUE into OP0, unless it is zero. */
648 temp = expand_binop (mode, ior_optab, temp, value,
649 subtarget, 1, OPTAB_LIB_WIDEN);
651 emit_move_insn (op0, temp);
654 /* Store a bit field that is split across two words.
656 OP0 is the REG, SUBREG or MEM rtx for the first of the two words.
657 BITSIZE is the field width; BITPOS the position of its first bit
659 VALUE is the value to store. */
662 store_split_bit_field (op0, bitsize, bitpos, value, align)
668 /* BITSIZE_1 is size of the part in the first word. */
669 int bitsize_1 = BITS_PER_WORD - bitpos % BITS_PER_WORD;
670 /* BITSIZE_2 is size of the rest (in the following word). */
671 int bitsize_2 = bitsize - bitsize_1;
673 int unit = GET_CODE (op0) == MEM ? BITS_PER_UNIT : BITS_PER_WORD;
674 int offset = bitpos / unit;
677 /* The field must span exactly one word boundary. */
678 if (bitpos / BITS_PER_WORD != (bitpos + bitsize - 1) / BITS_PER_WORD - 1)
681 if (GET_MODE (value) != VOIDmode)
682 value = convert_to_mode (word_mode, value, 1);
683 if (CONSTANT_P (value) && GET_CODE (value) != CONST_INT)
684 value = copy_to_reg (value);
686 /* Split the value into two parts:
687 PART1 gets that which goes in the first word; PART2 the other. */
689 /* PART1 gets the more significant part. */
690 if (GET_CODE (value) == CONST_INT)
692 part1 = GEN_INT ((unsigned HOST_WIDE_INT) (INTVAL (value)) >> bitsize_2);
693 part2 = GEN_INT ((unsigned HOST_WIDE_INT) (INTVAL (value))
694 & (((HOST_WIDE_INT) 1 << bitsize_2) - 1));
698 part1 = extract_fixed_bit_field (word_mode, value, 0, bitsize_1,
699 BITS_PER_WORD - bitsize, NULL_RTX, 1,
701 part2 = extract_fixed_bit_field (word_mode, value, 0, bitsize_2,
702 BITS_PER_WORD - bitsize_2, NULL_RTX, 1,
706 /* PART1 gets the less significant part. */
707 if (GET_CODE (value) == CONST_INT)
709 part1 = GEN_INT ((unsigned HOST_WIDE_INT) (INTVAL (value))
710 & (((HOST_WIDE_INT) 1 << bitsize_1) - 1));
711 part2 = GEN_INT ((unsigned HOST_WIDE_INT) (INTVAL (value)) >> bitsize_1);
715 part1 = extract_fixed_bit_field (word_mode, value, 0, bitsize_1, 0,
716 NULL_RTX, 1, BITS_PER_WORD);
717 part2 = extract_fixed_bit_field (word_mode, value, 0, bitsize_2,
718 bitsize_1, NULL_RTX, 1, BITS_PER_WORD);
722 /* Store PART1 into the first word. If OP0 is a MEM, pass OP0 and the
723 offset computed above. Otherwise, get the proper word and pass an
725 word = (GET_CODE (op0) == MEM ? op0
726 : operand_subword (op0, offset, 1, GET_MODE (op0)));
730 store_fixed_bit_field (word, GET_CODE (op0) == MEM ? offset : 0,
731 bitsize_1, bitpos % unit, part1, align);
733 /* Offset op0 by 1 word to get to the following one. */
734 if (GET_CODE (op0) == SUBREG)
735 word = operand_subword (SUBREG_REG (op0), SUBREG_WORD (op0) + offset + 1,
737 else if (GET_CODE (op0) == MEM)
740 word = operand_subword (op0, offset + 1, 1, GET_MODE (op0));
745 /* Store PART2 into the second word. */
746 store_fixed_bit_field (word,
747 (GET_CODE (op0) == MEM
748 ? CEIL (offset + 1, UNITS_PER_WORD) * UNITS_PER_WORD
750 bitsize_2, 0, part2, align);
753 /* Generate code to extract a byte-field from STR_RTX
754 containing BITSIZE bits, starting at BITNUM,
755 and put it in TARGET if possible (if TARGET is nonzero).
756 Regardless of TARGET, we return the rtx for where the value is placed.
759 STR_RTX is the structure containing the byte (a REG or MEM).
760 UNSIGNEDP is nonzero if this is an unsigned bit field.
761 MODE is the natural mode of the field value once extracted.
762 TMODE is the mode the caller would like the value to have;
763 but the value may be returned with type MODE instead.
765 ALIGN is the alignment that STR_RTX is known to have, measured in bytes.
766 TOTAL_SIZE is the size in bytes of the containing structure,
769 If a TARGET is specified and we can store in it at no extra cost,
770 we do so, and return TARGET.
771 Otherwise, we return a REG of mode TMODE or MODE, with TMODE preferred
772 if they are equally easy. */
775 extract_bit_field (str_rtx, bitsize, bitnum, unsignedp,
776 target, mode, tmode, align, total_size)
778 register int bitsize;
782 enum machine_mode mode, tmode;
786 int unit = (GET_CODE (str_rtx) == MEM) ? BITS_PER_UNIT : BITS_PER_WORD;
787 register int offset = bitnum / unit;
788 register int bitpos = bitnum % unit;
789 register rtx op0 = str_rtx;
790 rtx spec_target = target;
791 rtx spec_target_subreg = 0;
793 if (GET_CODE (str_rtx) == MEM && ! MEM_IN_STRUCT_P (str_rtx))
796 /* Discount the part of the structure before the desired byte.
797 We need to know how many bytes are safe to reference after it. */
799 total_size -= (bitpos / BIGGEST_ALIGNMENT
800 * (BIGGEST_ALIGNMENT / BITS_PER_UNIT));
802 if (tmode == VOIDmode)
804 while (GET_CODE (op0) == SUBREG)
806 offset += SUBREG_WORD (op0);
807 op0 = SUBREG_REG (op0);
811 /* If OP0 is a register, BITPOS must count within a word.
812 But as we have it, it counts within whatever size OP0 now has.
813 On a bigendian machine, these are not the same, so convert. */
814 if (GET_CODE (op0) != MEM && unit > GET_MODE_BITSIZE (GET_MODE (op0)))
815 bitpos += unit - GET_MODE_BITSIZE (GET_MODE (op0));
818 /* Extracting a full-word or multi-word value
819 from a structure in a register.
820 This can be done with just SUBREG.
821 So too extracting a subword value in
822 the least significant part of the register. */
824 if (GET_CODE (op0) == REG
825 && ((bitsize >= BITS_PER_WORD && bitsize == GET_MODE_BITSIZE (mode)
826 && bitpos % BITS_PER_WORD == 0)
827 || (mode_for_size (bitsize, GET_MODE_CLASS (tmode), 0) != BLKmode
829 && bitpos + bitsize == BITS_PER_WORD
835 enum machine_mode mode1
836 = mode_for_size (bitsize, GET_MODE_CLASS (tmode), 0);
838 if (mode1 != GET_MODE (op0))
839 op0 = gen_rtx (SUBREG, mode1, op0, offset);
842 return convert_to_mode (tmode, op0, unsignedp);
846 /* Handle fields bigger than a word. */
848 if (bitsize > BITS_PER_WORD)
850 /* Here we transfer the words of the field
851 in the order least significant first.
852 This is because the most significant word is the one which may
853 be less than full. */
855 int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD;
858 if (target == 0 || GET_CODE (target) != REG)
859 target = gen_reg_rtx (mode);
861 for (i = 0; i < nwords; i++)
863 /* If I is 0, use the low-order word in both field and target;
864 if I is 1, use the next to lowest word; and so on. */
865 int wordnum = (WORDS_BIG_ENDIAN ? nwords - i - 1 : i);
866 int bit_offset = (WORDS_BIG_ENDIAN
867 ? MAX (0, bitsize - (i + 1) * BITS_PER_WORD)
868 : i * BITS_PER_WORD);
869 rtx target_part = operand_subword (target, wordnum, 1, VOIDmode);
871 = extract_bit_field (op0, MIN (BITS_PER_WORD,
872 bitsize - i * BITS_PER_WORD),
874 1, target_part, mode, word_mode,
877 if (target_part == 0)
880 if (result_part != target_part)
881 emit_move_insn (target_part, result_part);
887 /* From here on we know the desired field is smaller than a word
888 so we can assume it is an integer. So we can safely extract it as one
889 size of integer, if necessary, and then truncate or extend
890 to the size that is wanted. */
892 /* OFFSET is the number of words or bytes (UNIT says which)
893 from STR_RTX to the first word or byte containing part of the field. */
895 if (GET_CODE (op0) == REG)
898 || GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD)
899 op0 = gen_rtx (SUBREG, TYPE_MODE (type_for_size (BITS_PER_WORD, 0)),
905 op0 = protect_from_queue (str_rtx, 1);
908 /* Now OFFSET is nonzero only for memory operands. */
914 && (GET_MODE_BITSIZE (insn_operand_mode[(int) CODE_FOR_extzv][0])
917 int xbitpos = bitpos, xoffset = offset;
918 rtx bitsize_rtx, bitpos_rtx;
919 rtx last = get_last_insn();
921 rtx xtarget = target;
922 rtx xspec_target = spec_target;
923 rtx xspec_target_subreg = spec_target_subreg;
925 enum machine_mode maxmode
926 = insn_operand_mode[(int) CODE_FOR_extzv][0];
928 if (GET_CODE (xop0) == MEM)
930 int save_volatile_ok = volatile_ok;
933 /* Is the memory operand acceptable? */
935 || ! ((*insn_operand_predicate[(int) CODE_FOR_extzv][1])
936 (xop0, GET_MODE (xop0))))
938 /* No, load into a reg and extract from there. */
939 enum machine_mode bestmode;
941 /* Get the mode to use for inserting into this field. If
942 OP0 is BLKmode, get the smallest mode consistent with the
943 alignment. If OP0 is a non-BLKmode object that is no
944 wider than MAXMODE, use its mode. Otherwise, use the
945 smallest mode containing the field. */
947 if (GET_MODE (xop0) == BLKmode
948 || (GET_MODE_SIZE (GET_MODE (op0))
949 > GET_MODE_SIZE (maxmode)))
950 bestmode = get_best_mode (bitsize, bitnum,
951 align * BITS_PER_UNIT, maxmode,
952 MEM_VOLATILE_P (xop0));
954 bestmode = GET_MODE (xop0);
956 if (bestmode == VOIDmode)
959 /* Compute offset as multiple of this unit,
960 counting in bytes. */
961 unit = GET_MODE_BITSIZE (bestmode);
962 xoffset = (bitnum / unit) * GET_MODE_SIZE (bestmode);
963 xbitpos = bitnum % unit;
964 xop0 = change_address (xop0, bestmode,
965 plus_constant (XEXP (xop0, 0),
967 /* Fetch it to a register in that size. */
968 xop0 = force_reg (bestmode, xop0);
970 /* XBITPOS counts within UNIT, which is what is expected. */
973 /* Get ref to first byte containing part of the field. */
974 xop0 = change_address (xop0, byte_mode,
975 plus_constant (XEXP (xop0, 0), xoffset));
977 volatile_ok = save_volatile_ok;
980 /* If op0 is a register, we need it in MAXMODE (which is usually
981 SImode). to make it acceptable to the format of extzv. */
982 if (GET_CODE (xop0) == SUBREG && GET_MODE (xop0) != maxmode)
984 if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode)
985 xop0 = gen_rtx (SUBREG, maxmode, xop0, 0);
987 /* On big-endian machines, we count bits from the most significant.
988 If the bit field insn does not, we must invert. */
989 #if BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN
990 xbitpos = unit - bitsize - xbitpos;
992 /* Now convert from counting within UNIT to counting in MAXMODE. */
994 if (GET_CODE (xop0) != MEM)
995 xbitpos += GET_MODE_BITSIZE (maxmode) - unit;
997 unit = GET_MODE_BITSIZE (maxmode);
1000 || (flag_force_mem && GET_CODE (xtarget) == MEM))
1001 xtarget = xspec_target = gen_reg_rtx (tmode);
1003 if (GET_MODE (xtarget) != maxmode)
1005 if (GET_CODE (xtarget) == REG)
1007 int wider = (GET_MODE_SIZE (maxmode)
1008 > GET_MODE_SIZE (GET_MODE (xtarget)));
1009 xtarget = gen_lowpart (maxmode, xtarget);
1011 xspec_target_subreg = xtarget;
1014 xtarget = gen_reg_rtx (maxmode);
1017 /* If this machine's extzv insists on a register target,
1018 make sure we have one. */
1019 if (! ((*insn_operand_predicate[(int) CODE_FOR_extzv][0])
1020 (xtarget, maxmode)))
1021 xtarget = gen_reg_rtx (maxmode);
1023 bitsize_rtx = GEN_INT (bitsize);
1024 bitpos_rtx = GEN_INT (xbitpos);
1026 pat = gen_extzv (protect_from_queue (xtarget, 1),
1027 xop0, bitsize_rtx, bitpos_rtx);
1032 spec_target = xspec_target;
1033 spec_target_subreg = xspec_target_subreg;
1037 delete_insns_since (last);
1038 target = extract_fixed_bit_field (tmode, op0, offset, bitsize,
1039 bitpos, target, 1, align);
1045 target = extract_fixed_bit_field (tmode, op0, offset, bitsize, bitpos,
1052 && (GET_MODE_BITSIZE (insn_operand_mode[(int) CODE_FOR_extv][0])
1055 int xbitpos = bitpos, xoffset = offset;
1056 rtx bitsize_rtx, bitpos_rtx;
1057 rtx last = get_last_insn();
1058 rtx xop0 = op0, xtarget = target;
1059 rtx xspec_target = spec_target;
1060 rtx xspec_target_subreg = spec_target_subreg;
1062 enum machine_mode maxmode
1063 = insn_operand_mode[(int) CODE_FOR_extv][0];
1065 if (GET_CODE (xop0) == MEM)
1067 /* Is the memory operand acceptable? */
1068 if (! ((*insn_operand_predicate[(int) CODE_FOR_extv][1])
1069 (xop0, GET_MODE (xop0))))
1071 /* No, load into a reg and extract from there. */
1072 enum machine_mode bestmode;
1074 /* Get the mode to use for inserting into this field. If
1075 OP0 is BLKmode, get the smallest mode consistent with the
1076 alignment. If OP0 is a non-BLKmode object that is no
1077 wider than MAXMODE, use its mode. Otherwise, use the
1078 smallest mode containing the field. */
1080 if (GET_MODE (xop0) == BLKmode
1081 || (GET_MODE_SIZE (GET_MODE (op0))
1082 > GET_MODE_SIZE (maxmode)))
1083 bestmode = get_best_mode (bitsize, bitnum,
1084 align * BITS_PER_UNIT, maxmode,
1085 MEM_VOLATILE_P (xop0));
1087 bestmode = GET_MODE (xop0);
1089 if (bestmode == VOIDmode)
1092 /* Compute offset as multiple of this unit,
1093 counting in bytes. */
1094 unit = GET_MODE_BITSIZE (bestmode);
1095 xoffset = (bitnum / unit) * GET_MODE_SIZE (bestmode);
1096 xbitpos = bitnum % unit;
1097 xop0 = change_address (xop0, bestmode,
1098 plus_constant (XEXP (xop0, 0),
1100 /* Fetch it to a register in that size. */
1101 xop0 = force_reg (bestmode, xop0);
1103 /* XBITPOS counts within UNIT, which is what is expected. */
1106 /* Get ref to first byte containing part of the field. */
1107 xop0 = change_address (xop0, byte_mode,
1108 plus_constant (XEXP (xop0, 0), xoffset));
1111 /* If op0 is a register, we need it in MAXMODE (which is usually
1112 SImode) to make it acceptable to the format of extv. */
1113 if (GET_CODE (xop0) == SUBREG && GET_MODE (xop0) != maxmode)
1115 if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode)
1116 xop0 = gen_rtx (SUBREG, maxmode, xop0, 0);
1118 /* On big-endian machines, we count bits from the most significant.
1119 If the bit field insn does not, we must invert. */
1120 #if BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN
1121 xbitpos = unit - bitsize - xbitpos;
1123 /* XBITPOS counts within a size of UNIT.
1124 Adjust to count within a size of MAXMODE. */
1126 if (GET_CODE (xop0) != MEM)
1127 xbitpos += (GET_MODE_BITSIZE (maxmode) - unit);
1129 unit = GET_MODE_BITSIZE (maxmode);
1132 || (flag_force_mem && GET_CODE (xtarget) == MEM))
1133 xtarget = xspec_target = gen_reg_rtx (tmode);
1135 if (GET_MODE (xtarget) != maxmode)
1137 if (GET_CODE (xtarget) == REG)
1139 int wider = (GET_MODE_SIZE (maxmode)
1140 > GET_MODE_SIZE (GET_MODE (xtarget)));
1141 xtarget = gen_lowpart (maxmode, xtarget);
1143 xspec_target_subreg = xtarget;
1146 xtarget = gen_reg_rtx (maxmode);
1149 /* If this machine's extv insists on a register target,
1150 make sure we have one. */
1151 if (! ((*insn_operand_predicate[(int) CODE_FOR_extv][0])
1152 (xtarget, maxmode)))
1153 xtarget = gen_reg_rtx (maxmode);
1155 bitsize_rtx = GEN_INT (bitsize);
1156 bitpos_rtx = GEN_INT (xbitpos);
1158 pat = gen_extv (protect_from_queue (xtarget, 1),
1159 xop0, bitsize_rtx, bitpos_rtx);
1164 spec_target = xspec_target;
1165 spec_target_subreg = xspec_target_subreg;
1169 delete_insns_since (last);
1170 target = extract_fixed_bit_field (tmode, op0, offset, bitsize,
1171 bitpos, target, 0, align);
1177 target = extract_fixed_bit_field (tmode, op0, offset, bitsize, bitpos,
1180 if (target == spec_target)
1182 if (target == spec_target_subreg)
1184 if (GET_MODE (target) != tmode && GET_MODE (target) != mode)
1186 /* If the target mode is floating-point, first convert to the
1187 integer mode of that size and then access it as a floating-point
1188 value via a SUBREG. */
1189 if (GET_MODE_CLASS (tmode) == MODE_FLOAT)
1191 target = convert_to_mode (mode_for_size (GET_MODE_BITSIZE (tmode),
1194 if (GET_CODE (target) != REG)
1195 target = copy_to_reg (target);
1196 return gen_rtx (SUBREG, tmode, target, 0);
1199 return convert_to_mode (tmode, target, unsignedp);
1204 /* Extract a bit field using shifts and boolean operations
1205 Returns an rtx to represent the value.
1206 OP0 addresses a register (word) or memory (byte).
1207 BITPOS says which bit within the word or byte the bit field starts in.
1208 OFFSET says how many bytes farther the bit field starts;
1209 it is 0 if OP0 is a register.
1210 BITSIZE says how many bits long the bit field is.
1211 (If OP0 is a register, it may be narrower than a full word,
1212 but BITPOS still counts within a full word,
1213 which is significant on bigendian machines.)
1215 UNSIGNEDP is nonzero for an unsigned bit field (don't sign-extend value).
1216 If TARGET is nonzero, attempts to store the value there
1217 and return TARGET, but this is not guaranteed.
1218 If TARGET is not used, create a pseudo-reg of mode TMODE for the value.
1220 ALIGN is the alignment that STR_RTX is known to have, measured in bytes. */
1223 extract_fixed_bit_field (tmode, op0, offset, bitsize, bitpos,
1224 target, unsignedp, align)
1225 enum machine_mode tmode;
1226 register rtx op0, target;
1227 register int offset, bitsize, bitpos;
1231 int total_bits = BITS_PER_WORD;
1232 enum machine_mode mode;
1234 if (GET_CODE (op0) == SUBREG || GET_CODE (op0) == REG)
1236 /* Special treatment for a bit field split across two registers. */
1237 if (bitsize + bitpos > BITS_PER_WORD)
1238 return extract_split_bit_field (op0, bitsize, bitpos,
1243 /* Get the proper mode to use for this field. We want a mode that
1244 includes the entire field. If such a mode would be larger than
1245 a word, we won't be doing the extraction the normal way. */
1247 mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT,
1248 align * BITS_PER_UNIT, word_mode,
1249 GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0));
1251 if (mode == VOIDmode)
1252 /* The only way this should occur is if the field spans word
1254 return extract_split_bit_field (op0, bitsize,
1255 bitpos + offset * BITS_PER_UNIT,
1258 total_bits = GET_MODE_BITSIZE (mode);
1260 /* Get ref to an aligned byte, halfword, or word containing the field.
1261 Adjust BITPOS to be position within a word,
1262 and OFFSET to be the offset of that word.
1263 Then alter OP0 to refer to that word. */
1264 bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT;
1265 offset -= (offset % (total_bits / BITS_PER_UNIT));
1266 op0 = change_address (op0, mode,
1267 plus_constant (XEXP (op0, 0), offset));
1270 mode = GET_MODE (op0);
1272 #if BYTES_BIG_ENDIAN
1273 /* BITPOS is the distance between our msb and that of OP0.
1274 Convert it to the distance from the lsb. */
1276 bitpos = total_bits - bitsize - bitpos;
1278 /* Now BITPOS is always the distance between the field's lsb and that of OP0.
1279 We have reduced the big-endian case to the little-endian case. */
1285 /* If the field does not already start at the lsb,
1286 shift it so it does. */
1287 tree amount = build_int_2 (bitpos, 0);
1288 /* Maybe propagate the target for the shift. */
1289 /* But not if we will return it--could confuse integrate.c. */
1290 rtx subtarget = (target != 0 && GET_CODE (target) == REG
1291 && !REG_FUNCTION_VALUE_P (target)
1293 if (tmode != mode) subtarget = 0;
1294 op0 = expand_shift (RSHIFT_EXPR, mode, op0, amount, subtarget, 1);
1296 /* Convert the value to the desired mode. */
1298 op0 = convert_to_mode (tmode, op0, 1);
1300 /* Unless the msb of the field used to be the msb when we shifted,
1301 mask out the upper bits. */
1303 if (GET_MODE_BITSIZE (mode) != bitpos + bitsize
1305 #ifdef SLOW_ZERO_EXTEND
1306 /* Always generate an `and' if
1307 we just zero-extended op0 and SLOW_ZERO_EXTEND, since it
1308 will combine fruitfully with the zero-extend. */
1313 return expand_binop (GET_MODE (op0), and_optab, op0,
1314 mask_rtx (GET_MODE (op0), 0, bitsize, 0),
1315 target, 1, OPTAB_LIB_WIDEN);
1319 /* To extract a signed bit-field, first shift its msb to the msb of the word,
1320 then arithmetic-shift its lsb to the lsb of the word. */
1321 op0 = force_reg (mode, op0);
1325 /* Find the narrowest integer mode that contains the field. */
1327 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode;
1328 mode = GET_MODE_WIDER_MODE (mode))
1329 if (GET_MODE_BITSIZE (mode) >= bitsize + bitpos)
1331 op0 = convert_to_mode (mode, op0, 0);
1335 if (GET_MODE_BITSIZE (mode) != (bitsize + bitpos))
1337 tree amount = build_int_2 (GET_MODE_BITSIZE (mode) - (bitsize + bitpos), 0);
1338 /* Maybe propagate the target for the shift. */
1339 /* But not if we will return the result--could confuse integrate.c. */
1340 rtx subtarget = (target != 0 && GET_CODE (target) == REG
1341 && ! REG_FUNCTION_VALUE_P (target)
1343 op0 = expand_shift (LSHIFT_EXPR, mode, op0, amount, subtarget, 1);
1346 return expand_shift (RSHIFT_EXPR, mode, op0,
1347 build_int_2 (GET_MODE_BITSIZE (mode) - bitsize, 0),
1351 /* Return a constant integer (CONST_INT or CONST_DOUBLE) mask value
1352 of mode MODE with BITSIZE ones followed by BITPOS zeros, or the
1353 complement of that if COMPLEMENT. The mask is truncated if
1354 necessary to the width of mode MODE. */
1357 mask_rtx (mode, bitpos, bitsize, complement)
1358 enum machine_mode mode;
1359 int bitpos, bitsize, complement;
1361 HOST_WIDE_INT masklow, maskhigh;
1363 if (bitpos < HOST_BITS_PER_WIDE_INT)
1364 masklow = (HOST_WIDE_INT) -1 << bitpos;
1368 if (bitpos + bitsize < HOST_BITS_PER_WIDE_INT)
1369 masklow &= ((unsigned HOST_WIDE_INT) -1
1370 >> (HOST_BITS_PER_WIDE_INT - bitpos - bitsize));
1372 if (bitpos <= HOST_BITS_PER_WIDE_INT)
1375 maskhigh = (HOST_WIDE_INT) -1 << (bitpos - HOST_BITS_PER_WIDE_INT);
1377 if (bitpos + bitsize > HOST_BITS_PER_WIDE_INT)
1378 maskhigh &= ((unsigned HOST_WIDE_INT) -1
1379 >> (2 * HOST_BITS_PER_WIDE_INT - bitpos - bitsize));
1385 maskhigh = ~maskhigh;
1389 return immed_double_const (masklow, maskhigh, mode);
1392 /* Return a constant integer (CONST_INT or CONST_DOUBLE) rtx with the value
1393 VALUE truncated to BITSIZE bits and then shifted left BITPOS bits. */
1396 lshift_value (mode, value, bitpos, bitsize)
1397 enum machine_mode mode;
1399 int bitpos, bitsize;
1401 unsigned HOST_WIDE_INT v = INTVAL (value);
1402 HOST_WIDE_INT low, high;
1404 if (bitsize < HOST_BITS_PER_WIDE_INT)
1405 v &= ~((HOST_WIDE_INT) -1 << bitsize);
1407 if (bitpos < HOST_BITS_PER_WIDE_INT)
1410 high = (bitpos > 0 ? (v >> (HOST_BITS_PER_WIDE_INT - bitpos)) : 0);
1415 high = v << (bitpos - HOST_BITS_PER_WIDE_INT);
1418 return immed_double_const (low, high, mode);
1421 /* Extract a bit field that is split across two words
1422 and return an RTX for the result.
1424 OP0 is the REG, SUBREG or MEM rtx for the first of the two words.
1425 BITSIZE is the field width; BITPOS, position of its first bit, in the word.
1426 UNSIGNEDP is 1 if should zero-extend the contents; else sign-extend. */
1429 extract_split_bit_field (op0, bitsize, bitpos, unsignedp, align)
1431 int bitsize, bitpos, unsignedp, align;
1433 /* BITSIZE_1 is size of the part in the first word. */
1434 int bitsize_1 = BITS_PER_WORD - bitpos % BITS_PER_WORD;
1435 /* BITSIZE_2 is size of the rest (in the following word). */
1436 int bitsize_2 = bitsize - bitsize_1;
1437 rtx part1, part2, result;
1438 int unit = GET_CODE (op0) == MEM ? BITS_PER_UNIT : BITS_PER_WORD;
1439 int offset = bitpos / unit;
1442 /* The field must span exactly one word boundary. */
1443 if (bitpos / BITS_PER_WORD != (bitpos + bitsize - 1) / BITS_PER_WORD - 1)
1446 /* Get the part of the bit field from the first word. If OP0 is a MEM,
1447 pass OP0 and the offset computed above. Otherwise, get the proper
1448 word and pass an offset of zero. */
1449 word = (GET_CODE (op0) == MEM ? op0
1450 : operand_subword_force (op0, offset, GET_MODE (op0)));
1451 part1 = extract_fixed_bit_field (word_mode, word,
1452 GET_CODE (op0) == MEM ? offset : 0,
1453 bitsize_1, bitpos % unit, NULL_RTX,
1456 /* Offset op0 by 1 word to get to the following one. */
1457 if (GET_CODE (op0) == SUBREG)
1458 word = operand_subword_force (SUBREG_REG (op0),
1459 SUBREG_WORD (op0) + offset + 1, VOIDmode);
1460 else if (GET_CODE (op0) == MEM)
1463 word = operand_subword_force (op0, offset + 1, GET_MODE (op0));
1465 /* Get the part of the bit field from the second word. */
1466 part2 = extract_fixed_bit_field (word_mode, word,
1467 (GET_CODE (op0) == MEM
1468 ? CEIL (offset + 1, UNITS_PER_WORD) * UNITS_PER_WORD
1470 bitsize_2, 0, NULL_RTX, 1, align);
1472 /* Shift the more significant part up to fit above the other part. */
1473 #if BYTES_BIG_ENDIAN
1474 part1 = expand_shift (LSHIFT_EXPR, word_mode, part1,
1475 build_int_2 (bitsize_2, 0), 0, 1);
1477 part2 = expand_shift (LSHIFT_EXPR, word_mode, part2,
1478 build_int_2 (bitsize_1, 0), 0, 1);
1481 /* Combine the two parts with bitwise or. This works
1482 because we extracted both parts as unsigned bit fields. */
1483 result = expand_binop (word_mode, ior_optab, part1, part2, NULL_RTX, 1,
1486 /* Unsigned bit field: we are done. */
1489 /* Signed bit field: sign-extend with two arithmetic shifts. */
1490 result = expand_shift (LSHIFT_EXPR, word_mode, result,
1491 build_int_2 (BITS_PER_WORD - bitsize, 0),
1493 return expand_shift (RSHIFT_EXPR, word_mode, result,
1494 build_int_2 (BITS_PER_WORD - bitsize, 0), NULL_RTX, 0);
1497 /* Add INC into TARGET. */
1500 expand_inc (target, inc)
1503 rtx value = expand_binop (GET_MODE (target), add_optab,
1505 target, 0, OPTAB_LIB_WIDEN);
1506 if (value != target)
1507 emit_move_insn (target, value);
1510 /* Subtract DEC from TARGET. */
1513 expand_dec (target, dec)
1516 rtx value = expand_binop (GET_MODE (target), sub_optab,
1518 target, 0, OPTAB_LIB_WIDEN);
1519 if (value != target)
1520 emit_move_insn (target, value);
1523 /* Output a shift instruction for expression code CODE,
1524 with SHIFTED being the rtx for the value to shift,
1525 and AMOUNT the tree for the amount to shift by.
1526 Store the result in the rtx TARGET, if that is convenient.
1527 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
1528 Return the rtx for where the value is. */
1531 expand_shift (code, mode, shifted, amount, target, unsignedp)
1532 enum tree_code code;
1533 register enum machine_mode mode;
1536 register rtx target;
1539 register rtx op1, temp = 0;
1540 register int left = (code == LSHIFT_EXPR || code == LROTATE_EXPR);
1541 register int rotate = (code == LROTATE_EXPR || code == RROTATE_EXPR);
1544 /* Previously detected shift-counts computed by NEGATE_EXPR
1545 and shifted in the other direction; but that does not work
1548 op1 = expand_expr (amount, NULL_RTX, VOIDmode, 0);
1550 if (op1 == const0_rtx)
1553 for (try = 0; temp == 0 && try < 3; try++)
1555 enum optab_methods methods;
1558 methods = OPTAB_DIRECT;
1560 methods = OPTAB_WIDEN;
1562 methods = OPTAB_LIB_WIDEN;
1566 /* Widening does not work for rotation. */
1567 if (methods == OPTAB_WIDEN)
1569 else if (methods == OPTAB_LIB_WIDEN)
1571 /* If we are rotating by a constant that is valid and
1572 we have been unable to open-code this by a rotation,
1573 do it as the IOR of two shifts. I.e., to rotate A
1574 by N bits, compute (A << N) | ((unsigned) A >> (C - N))
1575 where C is the bitsize of A.
1577 It is theoretically possible that the target machine might
1578 not be able to perform either shift and hence we would
1579 be making two libcalls rather than just the one for the
1580 shift (similarly if IOR could not be done). We will allow
1581 this extremely unlikely lossage to avoid complicating the
1584 if (GET_CODE (op1) == CONST_INT && INTVAL (op1) > 0
1585 && INTVAL (op1) < GET_MODE_BITSIZE (mode))
1587 rtx subtarget = target == shifted ? 0 : target;
1590 = build_int_2 (GET_MODE_BITSIZE (mode) - INTVAL (op1), 0);
1592 shifted = force_reg (mode, shifted);
1594 temp = expand_shift (left ? LSHIFT_EXPR : RSHIFT_EXPR,
1595 mode, shifted, amount, subtarget, 1);
1596 temp1 = expand_shift (left ? RSHIFT_EXPR : LSHIFT_EXPR,
1597 mode, shifted, other_amount, 0, 1);
1598 return expand_binop (mode, ior_optab, temp, temp1, target,
1599 unsignedp, methods);
1602 methods = OPTAB_LIB;
1605 temp = expand_binop (mode,
1606 left ? rotl_optab : rotr_optab,
1607 shifted, op1, target, unsignedp, methods);
1609 /* If we don't have the rotate, but we are rotating by a constant
1610 that is in range, try a rotate in the opposite direction. */
1612 if (temp == 0 && GET_CODE (op1) == CONST_INT
1613 && INTVAL (op1) > 0 && INTVAL (op1) < GET_MODE_BITSIZE (mode))
1614 temp = expand_binop (mode,
1615 left ? rotr_optab : rotl_optab,
1617 GEN_INT (GET_MODE_BITSIZE (mode)
1619 target, unsignedp, methods);
1623 temp = expand_binop (mode,
1624 left ? lshl_optab : lshr_optab,
1625 shifted, op1, target, unsignedp, methods);
1626 if (temp == 0 && left)
1627 temp = expand_binop (mode, ashl_optab,
1628 shifted, op1, target, unsignedp, methods);
1631 /* Do arithmetic shifts.
1632 Also, if we are going to widen the operand, we can just as well
1633 use an arithmetic right-shift instead of a logical one. */
1634 if (temp == 0 && ! rotate
1635 && (! unsignedp || (! left && methods == OPTAB_WIDEN)))
1637 enum optab_methods methods1 = methods;
1639 /* If trying to widen a log shift to an arithmetic shift,
1640 don't accept an arithmetic shift of the same size. */
1642 methods1 = OPTAB_MUST_WIDEN;
1644 /* Arithmetic shift */
1646 temp = expand_binop (mode,
1647 left ? ashl_optab : ashr_optab,
1648 shifted, op1, target, unsignedp, methods1);
1652 /* We can do a logical (unsigned) right shift with a bit-field
1653 extract insn. But first check if one of the above methods worked. */
1657 if (unsignedp && code == RSHIFT_EXPR && ! BITS_BIG_ENDIAN && HAVE_extzv)
1659 enum machine_mode output_mode
1660 = insn_operand_mode[(int) CODE_FOR_extzv][0];
1662 if ((methods == OPTAB_DIRECT && mode == output_mode)
1663 || (methods == OPTAB_WIDEN
1664 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (output_mode)))
1666 rtx shifted1 = convert_to_mode (output_mode,
1667 protect_from_queue (shifted, 0),
1669 enum machine_mode length_mode
1670 = insn_operand_mode[(int) CODE_FOR_extzv][2];
1671 enum machine_mode pos_mode
1672 = insn_operand_mode[(int) CODE_FOR_extzv][3];
1674 rtx last = get_last_insn ();
1680 target1 = protect_from_queue (target, 1);
1682 /* We define extract insns as having OUTPUT_MODE in a register
1683 and the mode of operand 1 in memory. Since we want
1684 OUTPUT_MODE, we will always force the operand into a
1685 register. At some point we might want to support MEM
1687 shifted1 = force_reg (output_mode, shifted1);
1689 /* If we don't have or cannot use a suggested target,
1690 make a place for the result, in the proper mode. */
1691 if (methods == OPTAB_WIDEN || target1 == 0
1692 || ! ((*insn_operand_predicate[(int) CODE_FOR_extzv][0])
1693 (target1, output_mode)))
1694 target1 = gen_reg_rtx (output_mode);
1696 xop1 = protect_from_queue (xop1, 0);
1697 xop1 = convert_to_mode (pos_mode, xop1,
1698 TREE_UNSIGNED (TREE_TYPE (amount)));
1700 /* If this machine's extzv insists on a register for
1701 operand 3 (position), arrange for that. */
1702 if (! ((*insn_operand_predicate[(int) CODE_FOR_extzv][3])
1704 xop1 = force_reg (pos_mode, xop1);
1706 /* WIDTH gets the width of the bit field to extract:
1707 wordsize minus # bits to shift by. */
1708 if (GET_CODE (xop1) == CONST_INT)
1709 width = GEN_INT (GET_MODE_BITSIZE (mode) - INTVAL (op1));
1712 /* Now get the width in the proper mode. */
1713 op1 = protect_from_queue (op1, 0);
1714 width = convert_to_mode (length_mode, op1,
1715 TREE_UNSIGNED (TREE_TYPE (amount)));
1717 width = expand_binop (length_mode, sub_optab,
1718 GEN_INT (GET_MODE_BITSIZE (mode)),
1719 width, NULL_RTX, 0, OPTAB_LIB_WIDEN);
1722 /* If this machine's extzv insists on a register for
1723 operand 2 (length), arrange for that. */
1724 if (! ((*insn_operand_predicate[(int) CODE_FOR_extzv][2])
1725 (width, length_mode)))
1726 width = force_reg (length_mode, width);
1728 /* Now extract with WIDTH, omitting OP1 least sig bits. */
1729 pat = gen_extzv (target1, shifted1, width, xop1);
1733 temp = convert_to_mode (mode, target1, 1);
1736 delete_insns_since (last);
1739 /* Can also do logical shift with signed bit-field extract
1740 followed by inserting the bit-field at a different position.
1741 That strategy is not yet implemented. */
1743 #endif /* HAVE_extzv */
1751 enum alg_code { alg_zero, alg_m, alg_shift,
1752 alg_add_t_m2, alg_sub_t_m2,
1753 alg_add_factor, alg_sub_factor,
1754 alg_add_t2_m, alg_sub_t2_m,
1755 alg_add, alg_subtract, alg_factor, alg_shiftop };
1757 /* This structure records a sequence of operations.
1758 `ops' is the number of operations recorded.
1759 `cost' is their total cost.
1760 The operations are stored in `op' and the corresponding
1761 logarithms of the integer coefficients in `log'.
1763 These are the operations:
1764 alg_zero total := 0;
1765 alg_m total := multiplicand;
1766 alg_shift total := total * coeff
1767 alg_add_t_m2 total := total + multiplicand * coeff;
1768 alg_sub_t_m2 total := total - multiplicand * coeff;
1769 alg_add_factor total := total * coeff + total;
1770 alg_sub_factor total := total * coeff - total;
1771 alg_add_t2_m total := total * coeff + multiplicand;
1772 alg_sub_t2_m total := total * coeff - multiplicand;
1774 The first operand must be either alg_zero or alg_m. */
1776 #ifndef MAX_BITS_PER_WORD
1777 #define MAX_BITS_PER_WORD BITS_PER_WORD
1784 /* The size of the OP and LOG fields are not directly related to the
1785 word size, but the worst-case algorithms will be if we have few
1786 consecutive ones or zeros, i.e., a multiplicand like 10101010101...
1787 In that case we will generate shift-by-2, add, shift-by-2, add,...,
1788 in total wordsize operations. */
1789 enum alg_code op[MAX_BITS_PER_WORD];
1790 char log[MAX_BITS_PER_WORD];
1793 /* Compute and return the best algorithm for multiplying by T.
1794 The algorithm must cost less than cost_limit
1795 If retval.cost >= COST_LIMIT, no algorithm was found and all
1796 other field of the returned struct are undefined. */
1798 static struct algorithm
1799 synth_mult (t, cost_limit)
1800 unsigned HOST_WIDE_INT t;
1804 struct algorithm *best_alg
1805 = (struct algorithm *)alloca (sizeof (struct algorithm));
1806 struct algorithm *alg_in
1807 = (struct algorithm *)alloca (sizeof (struct algorithm));
1809 unsigned HOST_WIDE_INT q;
1811 /* Indicate that no algorithm is yet found. If no algorithm
1812 is found, this value will be returned and indicate failure. */
1813 best_alg->cost = cost_limit;
1815 if (cost_limit <= 0)
1818 /* t == 1 can be done in zero cost. */
1823 best_alg->op[0] = alg_m;
1827 /* t == 0 sometimes has a cost. If it does and it exceeds our limit,
1832 if (zero_cost >= cost_limit)
1837 best_alg->cost = zero_cost;
1838 best_alg->op[0] = alg_zero;
1843 /* If we have a group of zero bits at the low-order part of T, try
1844 multiplying by the remaining bits and then doing a shift. */
1848 m = floor_log2 (t & -t); /* m = number of low zero bits */
1850 cost = shift_cost[m];
1851 if (cost < cost_limit)
1853 *alg_in = synth_mult (q, cost_limit - cost);
1855 cost += alg_in->cost;
1856 if (cost < best_alg->cost)
1858 struct algorithm *x;
1859 x = alg_in, alg_in = best_alg, best_alg = x;
1860 best_alg->log[best_alg->ops] = m;
1861 best_alg->op[best_alg->ops++] = alg_shift;
1862 best_alg->cost = cost_limit = cost;
1867 /* Look for factors of t of the form
1868 t = q(2**m +- 1), 2 <= m <= floor(log2(t - 1)).
1869 If we find such a factor, we can multiply by t using an algorithm that
1870 multiplies by q, shift the result by m and add/subtract it to itself.
1872 We search for large factors first and loop down, even if large factors
1873 are less probable than small; if we find a large factor we will find a
1874 good sequence quickly, and therefore be able to prune (by decreasing
1875 COST_LIMIT) the search. */
1877 for (m = floor_log2 (t - 1); m >= 2; m--)
1879 unsigned HOST_WIDE_INT d;
1881 d = ((unsigned HOST_WIDE_INT) 1 << m) + 1;
1882 if (t % d == 0 && t > d)
1884 cost = MIN (shiftadd_cost[m], add_cost + shift_cost[m]);
1885 *alg_in = synth_mult (t / d, cost_limit - cost);
1887 cost += alg_in->cost;
1888 if (cost < best_alg->cost)
1890 struct algorithm *x;
1891 x = alg_in, alg_in = best_alg, best_alg = x;
1892 best_alg->log[best_alg->ops] = m;
1893 best_alg->op[best_alg->ops++] = alg_add_factor;
1894 best_alg->cost = cost_limit = cost;
1898 d = ((unsigned HOST_WIDE_INT) 1 << m) - 1;
1899 if (t % d == 0 && t > d)
1901 cost = MIN (shiftsub_cost[m], add_cost + shift_cost[m]);
1902 *alg_in = synth_mult (t / d, cost_limit - cost);
1904 cost += alg_in->cost;
1905 if (cost < best_alg->cost)
1907 struct algorithm *x;
1908 x = alg_in, alg_in = best_alg, best_alg = x;
1909 best_alg->log[best_alg->ops] = m;
1910 best_alg->op[best_alg->ops++] = alg_sub_factor;
1911 best_alg->cost = cost_limit = cost;
1916 /* Try shift-and-add (load effective address) instructions,
1917 i.e. do a*3, a*5, a*9. */
1923 cost = shiftadd_cost[m];
1924 *alg_in = synth_mult ((t - 1) >> m, cost_limit - cost);
1926 cost += alg_in->cost;
1927 if (cost < best_alg->cost)
1929 struct algorithm *x;
1930 x = alg_in, alg_in = best_alg, best_alg = x;
1931 best_alg->log[best_alg->ops] = m;
1932 best_alg->op[best_alg->ops++] = alg_add_t2_m;
1933 best_alg->cost = cost_limit = cost;
1939 cost = shiftsub_cost[m];
1940 *alg_in = synth_mult ((t + 1) >> m, cost_limit - cost);
1942 cost += alg_in->cost;
1943 if (cost < best_alg->cost)
1945 struct algorithm *x;
1946 x = alg_in, alg_in = best_alg, best_alg = x;
1947 best_alg->log[best_alg->ops] = m;
1948 best_alg->op[best_alg->ops++] = alg_sub_t2_m;
1949 best_alg->cost = cost_limit = cost;
1953 /* Now, use the simple method of adding or subtracting at the leftmost
1956 unsigned HOST_WIDE_INT w;
1958 q = t & -t; /* get out lsb */
1959 for (w = q; (w & t) != 0; w <<= 1)
1962 /* Reject the case where t has only two bits.
1963 Thus we prefer addition in that case. */
1964 && !(t < w && w == q << 2))
1966 /* There are many bits in a row. Make 'em by subtraction. */
1970 /* Don't use shiftsub_cost here, this operation
1971 scales wrong operand. */
1972 cost = add_cost + shift_cost[m];
1973 *alg_in = synth_mult (t + q, cost_limit - cost);
1975 cost += alg_in->cost;
1976 if (cost < best_alg->cost)
1978 struct algorithm *x;
1979 x = alg_in, alg_in = best_alg, best_alg = x;
1980 best_alg->log[best_alg->ops] = m;
1981 best_alg->op[best_alg->ops++] = alg_sub_t_m2;
1982 best_alg->cost = cost_limit = cost;
1987 /* There's only one or two bit at the left. Make it by addition. */
1990 cost = MIN (shiftadd_cost[m], add_cost + shift_cost[m]);
1991 *alg_in = synth_mult (t - q, cost_limit - cost);
1993 cost += alg_in->cost;
1994 if (cost < best_alg->cost)
1996 struct algorithm *x;
1997 x = alg_in, alg_in = best_alg, best_alg = x;
1998 best_alg->log[best_alg->ops] = m;
1999 best_alg->op[best_alg->ops++] = alg_add_t_m2;
2000 best_alg->cost = cost_limit = cost;
2005 /* If we are getting a too long sequence for `struct algorithm'
2006 to record, store a fake cost to make this search fail. */
2007 if (best_alg->ops == MAX_BITS_PER_WORD)
2008 best_alg->cost = cost_limit;
2013 /* Perform a multiplication and return an rtx for the result.
2014 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
2015 TARGET is a suggestion for where to store the result (an rtx).
2017 We check specially for a constant integer as OP1.
2018 If you want this check for OP0 as well, then before calling
2019 you should swap the two operands if OP0 would be constant. */
2022 expand_mult (mode, op0, op1, target, unsignedp)
2023 enum machine_mode mode;
2024 register rtx op0, op1, target;
2027 rtx const_op1 = op1;
2029 /* If we are multiplying in DImode, it may still be a win
2030 to try to work with shifts and adds. */
2031 if (GET_CODE (op1) == CONST_DOUBLE
2032 && GET_MODE_CLASS (GET_MODE (op1)) == MODE_INT
2033 && HOST_BITS_PER_INT <= BITS_PER_WORD)
2035 if ((CONST_DOUBLE_HIGH (op1) == 0 && CONST_DOUBLE_LOW (op1) >= 0)
2036 || (CONST_DOUBLE_HIGH (op1) == -1 && CONST_DOUBLE_LOW (op1) < 0))
2037 const_op1 = GEN_INT (CONST_DOUBLE_LOW (op1));
2040 /* We used to test optimize here, on the grounds that it's better to
2041 produce a smaller program when -O is not used.
2042 But this causes such a terrible slowdown sometimes
2043 that it seems better to use synth_mult always. */
2045 if (GET_CODE (const_op1) == CONST_INT && ! mult_is_very_cheap)
2047 struct algorithm alg;
2048 struct algorithm neg_alg;
2050 HOST_WIDE_INT val = INTVAL (op1);
2051 HOST_WIDE_INT val_so_far;
2054 /* Try to do the computation two ways: multiply by the negative of OP1
2055 and then negate, or do the multiplication directly. The latter is
2056 usually faster for positive numbers and the former for negative
2057 numbers, but the opposite can be faster if the original value
2058 has a factor of 2**m +/- 1, while the negated value does not or
2061 alg = synth_mult (val, mult_cost);
2062 neg_alg = synth_mult (- val,
2063 (alg.cost < mult_cost ? alg.cost : mult_cost)
2066 if (neg_alg.cost + negate_cost < alg.cost)
2067 alg = neg_alg, negate = 1, val = - val;
2069 if (alg.cost < mult_cost)
2071 /* We found something cheaper than a multiply insn. */
2075 op0 = protect_from_queue (op0, 0);
2077 /* Avoid referencing memory over and over.
2078 For speed, but also for correctness when mem is volatile. */
2079 if (GET_CODE (op0) == MEM)
2080 op0 = force_reg (mode, op0);
2082 /* ACCUM starts out either as OP0 or as a zero, depending on
2083 the first operation. */
2085 if (alg.op[0] == alg_zero)
2087 accum = copy_to_mode_reg (mode, const0_rtx);
2090 else if (alg.op[0] == alg_m)
2092 accum = copy_to_mode_reg (mode, op0);
2098 for (opno = 1; opno < alg.ops; opno++)
2100 int log = alg.log[opno];
2101 rtx shift_subtarget = preserve_subexpressions_p () ? 0 : accum;
2102 rtx add_target = opno == alg.ops - 1 && target != 0 ? target : 0;
2104 switch (alg.op[opno])
2107 accum = expand_shift (LSHIFT_EXPR, mode, accum,
2108 build_int_2 (log, 0), NULL_RTX, 0);
2113 tem = expand_shift (LSHIFT_EXPR, mode, op0,
2114 build_int_2 (log, 0), NULL_RTX, 0);
2115 accum = force_operand (gen_rtx (PLUS, mode, accum, tem),
2116 add_target ? add_target : accum);
2117 val_so_far += (HOST_WIDE_INT) 1 << log;
2121 tem = expand_shift (LSHIFT_EXPR, mode, op0,
2122 build_int_2 (log, 0), NULL_RTX, 0);
2123 accum = force_operand (gen_rtx (MINUS, mode, accum, tem),
2124 add_target ? add_target : accum);
2125 val_so_far -= (HOST_WIDE_INT) 1 << log;
2129 accum = expand_shift (LSHIFT_EXPR, mode, accum,
2130 build_int_2 (log, 0), accum, 0);
2131 accum = force_operand (gen_rtx (PLUS, mode, accum, op0),
2132 add_target ? add_target : accum);
2133 val_so_far = (val_so_far << log) + 1;
2137 accum = expand_shift (LSHIFT_EXPR, mode, accum,
2138 build_int_2 (log, 0), accum, 0);
2139 accum = force_operand (gen_rtx (MINUS, mode, accum, op0),
2140 add_target ? add_target : accum);
2141 val_so_far = (val_so_far << log) - 1;
2144 case alg_add_factor:
2145 tem = expand_shift (LSHIFT_EXPR, mode, accum,
2146 build_int_2 (log, 0), NULL_RTX, 0);
2147 accum = force_operand (gen_rtx (PLUS, mode, accum, tem),
2148 add_target ? add_target : accum);
2149 val_so_far += val_so_far << log;
2152 case alg_sub_factor:
2153 tem = expand_shift (LSHIFT_EXPR, mode, accum,
2154 build_int_2 (log, 0), NULL_RTX, 0);
2155 accum = force_operand (gen_rtx (MINUS, mode, tem, accum),
2156 add_target ? add_target : tem);
2157 val_so_far = (val_so_far << log) - val_so_far;
2164 /* Write a REG_EQUAL note on the last insn so that we can cse
2165 multiplication sequences. */
2167 insn = get_last_insn ();
2169 = gen_rtx (EXPR_LIST, REG_EQUAL,
2170 gen_rtx (MULT, mode, op0, GEN_INT (val_so_far)),
2176 val_so_far = - val_so_far;
2177 accum = expand_unop (mode, neg_optab, accum, target, 0);
2180 if (val != val_so_far)
2187 /* This used to use umul_optab if unsigned,
2188 but for non-widening multiply there is no difference
2189 between signed and unsigned. */
2190 op0 = expand_binop (mode, smul_optab,
2191 op0, op1, target, unsignedp, OPTAB_LIB_WIDEN);
2197 /* Emit the code to divide OP0 by OP1, putting the result in TARGET
2198 if that is convenient, and returning where the result is.
2199 You may request either the quotient or the remainder as the result;
2200 specify REM_FLAG nonzero to get the remainder.
2202 CODE is the expression code for which kind of division this is;
2203 it controls how rounding is done. MODE is the machine mode to use.
2204 UNSIGNEDP nonzero means do unsigned division. */
2206 /* ??? For CEIL_MOD_EXPR, can compute incorrect remainder with ANDI
2207 and then correct it by or'ing in missing high bits
2208 if result of ANDI is nonzero.
2209 For ROUND_MOD_EXPR, can use ANDI and then sign-extend the result.
2210 This could optimize to a bfexts instruction.
2211 But C doesn't use these operations, so their optimizations are
2215 expand_divmod (rem_flag, code, mode, op0, op1, target, unsignedp)
2217 enum tree_code code;
2218 enum machine_mode mode;
2219 register rtx op0, op1, target;
2222 register rtx result = 0;
2223 enum machine_mode compute_mode;
2226 int can_clobber_op0;
2227 int mod_insn_no_good = 0;
2228 rtx adjusted_op0 = op0;
2229 optab optab1, optab2;
2231 /* We shouldn't be called with op1 == const1_rtx, but some of the
2232 code below will malfunction if we are, so check here and handle
2233 the special case if so. */
2234 if (op1 == const1_rtx)
2235 return rem_flag ? const0_rtx : op0;
2237 /* Don't use the function value register as a target
2238 since we have to read it as well as write it,
2239 and function-inlining gets confused by this. */
2240 if (target && REG_P (target) && REG_FUNCTION_VALUE_P (target))
2243 /* Don't clobber an operand while doing a multi-step calculation. */
2245 if ((rem_flag && (reg_mentioned_p (target, op0)
2246 || (GET_CODE (op0) == MEM && GET_CODE (target) == MEM)))
2247 || reg_mentioned_p (target, op1)
2248 || (GET_CODE (op1) == MEM && GET_CODE (target) == MEM))
2251 can_clobber_op0 = (GET_CODE (op0) == REG && op0 == target);
2253 if (GET_CODE (op1) == CONST_INT)
2254 log = exact_log2 (INTVAL (op1));
2256 /* If log is >= 0, we are dividing by 2**log, and will do it by shifting,
2257 which is really floor-division. Otherwise we will really do a divide,
2258 and we assume that is trunc-division.
2260 We must correct the dividend by adding or subtracting something
2261 based on the divisor, in order to do the kind of rounding specified
2262 by CODE. The correction depends on what kind of rounding is actually
2263 available, and that depends on whether we will shift or divide.
2265 In many of these cases it is possible to perform the operation by a
2266 clever series of logical operations (shifts and/or exclusive-ors).
2267 Although avoiding the jump has the advantage that it extends the basic
2268 block and allows further optimization, the branch-free code is normally
2269 at least one instruction longer in the (most common) case where the
2270 dividend is non-negative. Performance measurements of the two
2271 alternatives show that the branch-free code is slightly faster on the
2272 IBM ROMP but slower on CISC processors (significantly slower on the
2273 VAX). Accordingly, the jump code has been retained.
2275 On machines where the jump code is slower, the cost of a DIV or MOD
2276 operation can be set small (less than twice that of an addition); in
2277 that case, we pretend that we don't have a power of two and perform
2278 a normal division or modulus operation. */
2280 if ((code == TRUNC_MOD_EXPR || code == TRUNC_DIV_EXPR)
2282 && (rem_flag ? smod_pow2_cheap : sdiv_pow2_cheap))
2285 /* Get the mode in which to perform this computation. Normally it will
2286 be MODE, but sometimes we can't do the desired operation in MODE.
2287 If so, pick a wider mode in which we can do the operation. Convert
2288 to that mode at the start to avoid repeated conversions.
2290 First see what operations we need. These depend on the expression
2291 we are evaluating. (We assume that divxx3 insns exist under the
2292 same conditions that modxx3 insns and that these insns don't normally
2293 fail. If these assumptions are not correct, we may generate less
2294 efficient code in some cases.)
2296 Then see if we find a mode in which we can open-code that operation
2297 (either a division, modulus, or shift). Finally, check for the smallest
2298 mode for which we can do the operation with a library call. */
2300 optab1 = (log >= 0 ? (unsignedp ? lshr_optab : ashr_optab)
2301 : (unsignedp ? udiv_optab : sdiv_optab));
2302 optab2 = (log >= 0 ? optab1 : (unsignedp ? udivmod_optab : sdivmod_optab));
2304 for (compute_mode = mode; compute_mode != VOIDmode;
2305 compute_mode = GET_MODE_WIDER_MODE (compute_mode))
2306 if (optab1->handlers[(int) compute_mode].insn_code != CODE_FOR_nothing
2307 || optab2->handlers[(int) compute_mode].insn_code != CODE_FOR_nothing)
2310 if (compute_mode == VOIDmode)
2311 for (compute_mode = mode; compute_mode != VOIDmode;
2312 compute_mode = GET_MODE_WIDER_MODE (compute_mode))
2313 if (optab1->handlers[(int) compute_mode].libfunc
2314 || optab2->handlers[(int) compute_mode].libfunc)
2317 /* If we still couldn't find a mode, use MODE; we'll probably abort in
2319 if (compute_mode == VOIDmode)
2320 compute_mode = mode;
2322 size = GET_MODE_BITSIZE (compute_mode);
2324 /* Now convert to the best mode to use. Show we made a copy of OP0
2325 and hence we can clobber it (we cannot use a SUBREG to widen
2327 if (compute_mode != mode)
2329 adjusted_op0 = op0 = convert_to_mode (compute_mode, op0, unsignedp);
2330 can_clobber_op0 = 1;
2331 op1 = convert_to_mode (compute_mode, op1, unsignedp);
2334 /* If we are computing the remainder and one of the operands is a volatile
2335 MEM, copy it into a register. */
2337 if (rem_flag && GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0))
2338 adjusted_op0 = op0 = force_reg (compute_mode, op0), can_clobber_op0 = 1;
2339 if (rem_flag && GET_CODE (op1) == MEM && MEM_VOLATILE_P (op1))
2340 op1 = force_reg (compute_mode, op1);
2342 /* If we are computing the remainder, op0 will be needed later to calculate
2343 X - Y * (X / Y), therefore cannot be clobbered. */
2345 can_clobber_op0 = 0;
2347 if (target == 0 || GET_MODE (target) != compute_mode)
2348 target = gen_reg_rtx (compute_mode);
2352 case TRUNC_MOD_EXPR:
2353 case TRUNC_DIV_EXPR:
2354 if (log >= 0 && ! unsignedp)
2356 if (! can_clobber_op0)
2358 adjusted_op0 = copy_to_suggested_reg (adjusted_op0, target,
2360 /* Copy op0 to a reg, since emit_cmp_insn will call emit_queue
2361 which will screw up mem refs for autoincrements. */
2362 op0 = force_reg (compute_mode, op0);
2364 /* Here we need to add OP1-1 if OP0 is negative, 0 otherwise.
2365 This can be computed without jumps by arithmetically shifting
2366 OP0 right LOG-1 places and then shifting right logically
2367 SIZE-LOG bits. The resulting value is unconditionally added
2369 if (log == 1 || BRANCH_COST >= 3)
2371 rtx temp = gen_reg_rtx (compute_mode);
2372 temp = copy_to_suggested_reg (adjusted_op0, temp, compute_mode);
2373 temp = expand_shift (RSHIFT_EXPR, compute_mode, temp,
2374 build_int_2 (log - 1, 0), NULL_RTX, 0);
2375 temp = expand_shift (RSHIFT_EXPR, compute_mode, temp,
2376 build_int_2 (size - log, 0),
2378 expand_inc (adjusted_op0, temp);
2382 rtx label = gen_label_rtx ();
2383 emit_cmp_insn (adjusted_op0, const0_rtx, GE,
2384 NULL_RTX, compute_mode, 0, 0);
2385 emit_jump_insn (gen_bge (label));
2386 expand_inc (adjusted_op0, plus_constant (op1, -1));
2389 mod_insn_no_good = 1;
2393 case FLOOR_DIV_EXPR:
2394 case FLOOR_MOD_EXPR:
2395 if (log < 0 && ! unsignedp)
2397 rtx label = gen_label_rtx ();
2398 if (! can_clobber_op0)
2400 adjusted_op0 = copy_to_suggested_reg (adjusted_op0, target,
2402 /* Copy op0 to a reg, since emit_cmp_insn will call emit_queue
2403 which will screw up mem refs for autoincrements. */
2404 op0 = force_reg (compute_mode, op0);
2406 emit_cmp_insn (adjusted_op0, const0_rtx, GE,
2407 NULL_RTX, compute_mode, 0, 0);
2408 emit_jump_insn (gen_bge (label));
2409 expand_dec (adjusted_op0, op1);
2410 expand_inc (adjusted_op0, const1_rtx);
2412 mod_insn_no_good = 1;
2418 if (! can_clobber_op0)
2420 adjusted_op0 = copy_to_suggested_reg (adjusted_op0, target,
2422 /* Copy op0 to a reg, since emit_cmp_insn will call emit_queue
2423 which will screw up mem refs for autoincrements. */
2424 op0 = force_reg (compute_mode, op0);
2431 label = gen_label_rtx ();
2432 emit_cmp_insn (adjusted_op0, const0_rtx, LE,
2433 NULL_RTX, compute_mode, 0, 0);
2434 emit_jump_insn (gen_ble (label));
2436 expand_inc (adjusted_op0, op1);
2437 expand_dec (adjusted_op0, const1_rtx);
2443 adjusted_op0 = expand_binop (compute_mode, add_optab,
2444 adjusted_op0, plus_constant (op1, -1),
2445 NULL_RTX, 0, OPTAB_LIB_WIDEN);
2447 mod_insn_no_good = 1;
2450 case ROUND_DIV_EXPR:
2451 case ROUND_MOD_EXPR:
2452 if (! can_clobber_op0)
2454 adjusted_op0 = copy_to_suggested_reg (adjusted_op0, target,
2456 /* Copy op0 to a reg, since emit_cmp_insn will call emit_queue
2457 which will screw up mem refs for autoincrements. */
2458 op0 = force_reg (compute_mode, op0);
2462 op1 = expand_shift (RSHIFT_EXPR, compute_mode, op1,
2463 integer_one_node, NULL_RTX, 0);
2466 if (BRANCH_COST >= 2)
2468 /* Negate OP1 if OP0 < 0. Do this by computing a temporary
2469 that has all bits equal to the sign bit and exclusive
2470 or-ing it with OP1. */
2471 rtx temp = gen_reg_rtx (compute_mode);
2472 temp = copy_to_suggested_reg (adjusted_op0, temp, compute_mode);
2473 temp = expand_shift (RSHIFT_EXPR, compute_mode, temp,
2474 build_int_2 (size - 1, 0),
2476 op1 = expand_binop (compute_mode, xor_optab, op1, temp, op1,
2477 unsignedp, OPTAB_LIB_WIDEN);
2481 rtx label = gen_label_rtx ();
2482 emit_cmp_insn (adjusted_op0, const0_rtx, GE, NULL_RTX,
2483 compute_mode, 0, 0);
2484 emit_jump_insn (gen_bge (label));
2485 expand_unop (compute_mode, neg_optab, op1, op1, 0);
2489 expand_inc (adjusted_op0, op1);
2493 op1 = GEN_INT (((HOST_WIDE_INT) 1 << log) / 2);
2494 expand_inc (adjusted_op0, op1);
2496 mod_insn_no_good = 1;
2500 if (rem_flag && !mod_insn_no_good)
2502 /* Try to produce the remainder directly */
2504 result = expand_binop (compute_mode, and_optab, adjusted_op0,
2505 GEN_INT (((HOST_WIDE_INT) 1 << log) - 1),
2506 target, 1, OPTAB_LIB_WIDEN);
2509 /* See if we can do remainder without a library call. */
2510 result = sign_expand_binop (mode, umod_optab, smod_optab,
2511 adjusted_op0, op1, target,
2512 unsignedp, OPTAB_WIDEN);
2515 /* No luck there. Can we do remainder and divide at once
2516 without a library call? */
2517 result = gen_reg_rtx (compute_mode);
2518 if (! expand_twoval_binop (unsignedp
2519 ? udivmod_optab : sdivmod_optab,
2521 NULL_RTX, result, unsignedp))
2528 return gen_lowpart (mode, result);
2530 /* Produce the quotient. */
2532 result = expand_shift (RSHIFT_EXPR, compute_mode, adjusted_op0,
2533 build_int_2 (log, 0), target, unsignedp);
2534 else if (rem_flag && !mod_insn_no_good)
2535 /* If producing quotient in order to subtract for remainder,
2536 and a remainder subroutine would be ok,
2537 don't use a divide subroutine. */
2538 result = sign_expand_binop (compute_mode, udiv_optab, sdiv_optab,
2539 adjusted_op0, op1, NULL_RTX, unsignedp,
2543 /* Try a quotient insn, but not a library call. */
2544 result = sign_expand_binop (compute_mode, udiv_optab, sdiv_optab,
2546 rem_flag ? NULL_RTX : target,
2547 unsignedp, OPTAB_WIDEN);
2550 /* No luck there. Try a quotient-and-remainder insn,
2551 keeping the quotient alone. */
2552 result = gen_reg_rtx (mode);
2553 if (! expand_twoval_binop (unsignedp ? udivmod_optab : sdivmod_optab,
2555 result, NULL_RTX, unsignedp))
2559 /* If still no luck, use a library call. */
2561 result = sign_expand_binop (compute_mode, udiv_optab, sdiv_optab,
2563 rem_flag ? NULL_RTX : target,
2564 unsignedp, OPTAB_LIB_WIDEN);
2567 /* If we really want the remainder, get it by subtraction. */
2571 /* No divide instruction either. Use library for remainder. */
2572 result = sign_expand_binop (compute_mode, umod_optab, smod_optab,
2574 unsignedp, OPTAB_LIB_WIDEN);
2577 /* We divided. Now finish doing X - Y * (X / Y). */
2578 result = expand_mult (compute_mode, result, op1, target, unsignedp);
2579 if (! result) abort ();
2580 result = expand_binop (compute_mode, sub_optab, op0,
2581 result, target, unsignedp, OPTAB_LIB_WIDEN);
2588 return gen_lowpart (mode, result);
2591 /* Return a tree node with data type TYPE, describing the value of X.
2592 Usually this is an RTL_EXPR, if there is no obvious better choice.
2593 X may be an expression, however we only support those expressions
2594 generated by loop.c. */
2603 switch (GET_CODE (x))
2606 t = build_int_2 (INTVAL (x),
2607 ! TREE_UNSIGNED (type) && INTVAL (x) >= 0 ? 0 : -1);
2608 TREE_TYPE (t) = type;
2612 if (GET_MODE (x) == VOIDmode)
2614 t = build_int_2 (CONST_DOUBLE_LOW (x), CONST_DOUBLE_HIGH (x));
2615 TREE_TYPE (t) = type;
2621 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
2622 t = build_real (type, d);
2628 return fold (build (PLUS_EXPR, type, make_tree (type, XEXP (x, 0)),
2629 make_tree (type, XEXP (x, 1))));
2632 return fold (build (MINUS_EXPR, type, make_tree (type, XEXP (x, 0)),
2633 make_tree (type, XEXP (x, 1))));
2636 return fold (build1 (NEGATE_EXPR, type, make_tree (type, XEXP (x, 0))));
2639 return fold (build (MULT_EXPR, type, make_tree (type, XEXP (x, 0)),
2640 make_tree (type, XEXP (x, 1))));
2643 return fold (build (LSHIFT_EXPR, type, make_tree (type, XEXP (x, 0)),
2644 make_tree (type, XEXP (x, 1))));
2647 return fold (convert (type,
2648 build (RSHIFT_EXPR, unsigned_type (type),
2649 make_tree (unsigned_type (type),
2651 make_tree (type, XEXP (x, 1)))));
2654 return fold (convert (type,
2655 build (RSHIFT_EXPR, signed_type (type),
2656 make_tree (signed_type (type), XEXP (x, 0)),
2657 make_tree (type, XEXP (x, 1)))));
2660 if (TREE_CODE (type) != REAL_TYPE)
2661 t = signed_type (type);
2665 return fold (convert (type,
2666 build (TRUNC_DIV_EXPR, t,
2667 make_tree (t, XEXP (x, 0)),
2668 make_tree (t, XEXP (x, 1)))));
2670 t = unsigned_type (type);
2671 return fold (convert (type,
2672 build (TRUNC_DIV_EXPR, t,
2673 make_tree (t, XEXP (x, 0)),
2674 make_tree (t, XEXP (x, 1)))));
2676 t = make_node (RTL_EXPR);
2677 TREE_TYPE (t) = type;
2678 RTL_EXPR_RTL (t) = x;
2679 /* There are no insns to be output
2680 when this rtl_expr is used. */
2681 RTL_EXPR_SEQUENCE (t) = 0;
2686 /* Return an rtx representing the value of X * MULT + ADD.
2687 TARGET is a suggestion for where to store the result (an rtx).
2688 MODE is the machine mode for the computation.
2689 X and MULT must have mode MODE. ADD may have a different mode.
2690 So can X (defaults to same as MODE).
2691 UNSIGNEDP is non-zero to do unsigned multiplication.
2692 This may emit insns. */
2695 expand_mult_add (x, target, mult, add, mode, unsignedp)
2696 rtx x, target, mult, add;
2697 enum machine_mode mode;
2700 tree type = type_for_mode (mode, unsignedp);
2701 tree add_type = (GET_MODE (add) == VOIDmode
2702 ? type : type_for_mode (GET_MODE (add), unsignedp));
2703 tree result = fold (build (PLUS_EXPR, type,
2704 fold (build (MULT_EXPR, type,
2705 make_tree (type, x),
2706 make_tree (type, mult))),
2707 make_tree (add_type, add)));
2709 return expand_expr (result, target, VOIDmode, 0);
2712 /* Compute the logical-and of OP0 and OP1, storing it in TARGET
2713 and returning TARGET.
2715 If TARGET is 0, a pseudo-register or constant is returned. */
2718 expand_and (op0, op1, target)
2719 rtx op0, op1, target;
2721 enum machine_mode mode = VOIDmode;
2724 if (GET_MODE (op0) != VOIDmode)
2725 mode = GET_MODE (op0);
2726 else if (GET_MODE (op1) != VOIDmode)
2727 mode = GET_MODE (op1);
2729 if (mode != VOIDmode)
2730 tem = expand_binop (mode, and_optab, op0, op1, target, 0, OPTAB_LIB_WIDEN);
2731 else if (GET_CODE (op0) == CONST_INT && GET_CODE (op1) == CONST_INT)
2732 tem = GEN_INT (INTVAL (op0) & INTVAL (op1));
2738 else if (tem != target)
2739 emit_move_insn (target, tem);
2743 /* Emit a store-flags instruction for comparison CODE on OP0 and OP1
2744 and storing in TARGET. Normally return TARGET.
2745 Return 0 if that cannot be done.
2747 MODE is the mode to use for OP0 and OP1 should they be CONST_INTs. If
2748 it is VOIDmode, they cannot both be CONST_INT.
2750 UNSIGNEDP is for the case where we have to widen the operands
2751 to perform the operation. It says to use zero-extension.
2753 NORMALIZEP is 1 if we should convert the result to be either zero
2754 or one one. Normalize is -1 if we should convert the result to be
2755 either zero or -1. If NORMALIZEP is zero, the result will be left
2756 "raw" out of the scc insn. */
2759 emit_store_flag (target, code, op0, op1, mode, unsignedp, normalizep)
2763 enum machine_mode mode;
2768 enum insn_code icode;
2769 enum machine_mode compare_mode;
2770 enum machine_mode target_mode = GET_MODE (target);
2773 rtx pattern, comparison;
2775 if (mode == VOIDmode)
2776 mode = GET_MODE (op0);
2778 /* If one operand is constant, make it the second one. Only do this
2779 if the other operand is not constant as well. */
2781 if ((CONSTANT_P (op0) && ! CONSTANT_P (op1))
2782 || (GET_CODE (op0) == CONST_INT && GET_CODE (op1) != CONST_INT))
2787 code = swap_condition (code);
2790 /* For some comparisons with 1 and -1, we can convert this to
2791 comparisons with zero. This will often produce more opportunities for
2792 store-flag insns. */
2797 if (op1 == const1_rtx)
2798 op1 = const0_rtx, code = LE;
2801 if (op1 == constm1_rtx)
2802 op1 = const0_rtx, code = LT;
2805 if (op1 == const1_rtx)
2806 op1 = const0_rtx, code = GT;
2809 if (op1 == constm1_rtx)
2810 op1 = const0_rtx, code = GE;
2813 if (op1 == const1_rtx)
2814 op1 = const0_rtx, code = NE;
2817 if (op1 == const1_rtx)
2818 op1 = const0_rtx, code = EQ;
2822 /* From now on, we won't change CODE, so set ICODE now. */
2823 icode = setcc_gen_code[(int) code];
2825 /* If this is A < 0 or A >= 0, we can do this by taking the ones
2826 complement of A (for GE) and shifting the sign bit to the low bit. */
2827 if (op1 == const0_rtx && (code == LT || code == GE)
2828 && GET_MODE_CLASS (mode) == MODE_INT
2829 && (normalizep || STORE_FLAG_VALUE == 1
2830 || (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
2831 && (STORE_FLAG_VALUE
2832 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1)))))
2836 /* If the result is to be wider than OP0, it is best to convert it
2837 first. If it is to be narrower, it is *incorrect* to convert it
2839 if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (mode))
2841 op0 = protect_from_queue (op0, 0);
2842 op0 = convert_to_mode (target_mode, op0, 0);
2846 if (target_mode != mode)
2850 op0 = expand_unop (mode, one_cmpl_optab, op0, subtarget, 0);
2852 if (normalizep || STORE_FLAG_VALUE == 1)
2853 /* If we are supposed to produce a 0/1 value, we want to do
2854 a logical shift from the sign bit to the low-order bit; for
2855 a -1/0 value, we do an arithmetic shift. */
2856 op0 = expand_shift (RSHIFT_EXPR, mode, op0,
2857 size_int (GET_MODE_BITSIZE (mode) - 1),
2858 subtarget, normalizep != -1);
2860 if (mode != target_mode)
2861 op0 = convert_to_mode (target_mode, op0, 0);
2866 if (icode != CODE_FOR_nothing)
2868 /* We think we may be able to do this with a scc insn. Emit the
2869 comparison and then the scc insn.
2871 compare_from_rtx may call emit_queue, which would be deleted below
2872 if the scc insn fails. So call it ourselves before setting LAST. */
2875 last = get_last_insn ();
2878 = compare_from_rtx (op0, op1, code, unsignedp, mode, NULL_RTX, 0);
2879 if (GET_CODE (comparison) == CONST_INT)
2880 return (comparison == const0_rtx ? const0_rtx
2881 : normalizep == 1 ? const1_rtx
2882 : normalizep == -1 ? constm1_rtx
2885 /* If the code of COMPARISON doesn't match CODE, something is
2886 wrong; we can no longer be sure that we have the operation.
2887 We could handle this case, but it should not happen. */
2889 if (GET_CODE (comparison) != code)
2892 /* Get a reference to the target in the proper mode for this insn. */
2893 compare_mode = insn_operand_mode[(int) icode][0];
2895 if (preserve_subexpressions_p ()
2896 || ! (*insn_operand_predicate[(int) icode][0]) (subtarget, compare_mode))
2897 subtarget = gen_reg_rtx (compare_mode);
2899 pattern = GEN_FCN (icode) (subtarget);
2902 emit_insn (pattern);
2904 /* If we are converting to a wider mode, first convert to
2905 TARGET_MODE, then normalize. This produces better combining
2906 opportunities on machines that have a SIGN_EXTRACT when we are
2907 testing a single bit. This mostly benefits the 68k.
2909 If STORE_FLAG_VALUE does not have the sign bit set when
2910 interpreted in COMPARE_MODE, we can do this conversion as
2911 unsigned, which is usually more efficient. */
2912 if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (compare_mode))
2914 convert_move (target, subtarget,
2915 (GET_MODE_BITSIZE (compare_mode)
2916 <= HOST_BITS_PER_WIDE_INT)
2917 && 0 == (STORE_FLAG_VALUE
2918 & ((HOST_WIDE_INT) 1
2919 << (GET_MODE_BITSIZE (compare_mode) -1))));
2921 compare_mode = target_mode;
2926 /* If we want to keep subexpressions around, don't reuse our
2929 if (preserve_subexpressions_p ())
2932 /* Now normalize to the proper value in COMPARE_MODE. Sometimes
2933 we don't have to do anything. */
2934 if (normalizep == 0 || normalizep == STORE_FLAG_VALUE)
2936 else if (normalizep == - STORE_FLAG_VALUE)
2937 op0 = expand_unop (compare_mode, neg_optab, op0, subtarget, 0);
2939 /* We don't want to use STORE_FLAG_VALUE < 0 below since this
2940 makes it hard to use a value of just the sign bit due to
2941 ANSI integer constant typing rules. */
2942 else if (GET_MODE_BITSIZE (compare_mode) <= HOST_BITS_PER_WIDE_INT
2943 && (STORE_FLAG_VALUE
2944 & ((HOST_WIDE_INT) 1
2945 << (GET_MODE_BITSIZE (compare_mode) - 1))))
2946 op0 = expand_shift (RSHIFT_EXPR, compare_mode, op0,
2947 size_int (GET_MODE_BITSIZE (compare_mode) - 1),
2948 subtarget, normalizep == 1);
2949 else if (STORE_FLAG_VALUE & 1)
2951 op0 = expand_and (op0, const1_rtx, subtarget);
2952 if (normalizep == -1)
2953 op0 = expand_unop (compare_mode, neg_optab, op0, op0, 0);
2958 /* If we were converting to a smaller mode, do the
2960 if (target_mode != compare_mode)
2962 convert_move (target, op0, 0);
2971 delete_insns_since (last);
2973 subtarget = target_mode == mode ? target : 0;
2975 /* If we reached here, we can't do this with a scc insn. However, there
2976 are some comparisons that can be done directly. For example, if
2977 this is an equality comparison of integers, we can try to exclusive-or
2978 (or subtract) the two operands and use a recursive call to try the
2979 comparison with zero. Don't do any of these cases if branches are
2983 && GET_MODE_CLASS (mode) == MODE_INT && (code == EQ || code == NE)
2984 && op1 != const0_rtx)
2986 tem = expand_binop (mode, xor_optab, op0, op1, subtarget, 1,
2990 tem = expand_binop (mode, sub_optab, op0, op1, subtarget, 1,
2993 tem = emit_store_flag (target, code, tem, const0_rtx,
2994 mode, unsignedp, normalizep);
2996 delete_insns_since (last);
3000 /* Some other cases we can do are EQ, NE, LE, and GT comparisons with
3001 the constant zero. Reject all other comparisons at this point. Only
3002 do LE and GT if branches are expensive since they are expensive on
3003 2-operand machines. */
3005 if (BRANCH_COST == 0
3006 || GET_MODE_CLASS (mode) != MODE_INT || op1 != const0_rtx
3007 || (code != EQ && code != NE
3008 && (BRANCH_COST <= 1 || (code != LE && code != GT))))
3011 /* See what we need to return. We can only return a 1, -1, or the
3014 if (normalizep == 0)
3016 if (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
3017 normalizep = STORE_FLAG_VALUE;
3019 else if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3020 && (STORE_FLAG_VALUE
3021 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1)))
3027 /* Try to put the result of the comparison in the sign bit. Assume we can't
3028 do the necessary operation below. */
3032 /* To see if A <= 0, compute (A | (A - 1)). A <= 0 iff that result has
3033 the sign bit set. */
3037 /* This is destructive, so SUBTARGET can't be OP0. */
3038 if (rtx_equal_p (subtarget, op0))
3041 tem = expand_binop (mode, sub_optab, op0, const1_rtx, subtarget, 0,
3044 tem = expand_binop (mode, ior_optab, op0, tem, subtarget, 0,
3048 /* To see if A > 0, compute (((signed) A) << BITS) - A, where BITS is the
3049 number of bits in the mode of OP0, minus one. */
3053 if (rtx_equal_p (subtarget, op0))
3056 tem = expand_shift (RSHIFT_EXPR, mode, op0,
3057 size_int (GET_MODE_BITSIZE (mode) - 1),
3059 tem = expand_binop (mode, sub_optab, tem, op0, subtarget, 0,
3063 if (code == EQ || code == NE)
3065 /* For EQ or NE, one way to do the comparison is to apply an operation
3066 that converts the operand into a positive number if it is non-zero
3067 or zero if it was originally zero. Then, for EQ, we subtract 1 and
3068 for NE we negate. This puts the result in the sign bit. Then we
3069 normalize with a shift, if needed.
3071 Two operations that can do the above actions are ABS and FFS, so try
3072 them. If that doesn't work, and MODE is smaller than a full word,
3073 we can use zero-extension to the wider mode (an unsigned conversion)
3074 as the operation. */
3076 if (abs_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
3077 tem = expand_unop (mode, abs_optab, op0, subtarget, 1);
3078 else if (ffs_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
3079 tem = expand_unop (mode, ffs_optab, op0, subtarget, 1);
3080 else if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3083 op0 = protect_from_queue (op0, 0);
3084 tem = convert_to_mode (mode, op0, 1);
3090 tem = expand_binop (mode, sub_optab, tem, const1_rtx, subtarget,
3093 tem = expand_unop (mode, neg_optab, tem, subtarget, 0);
3096 /* If we couldn't do it that way, for NE we can "or" the two's complement
3097 of the value with itself. For EQ, we take the one's complement of
3098 that "or", which is an extra insn, so we only handle EQ if branches
3101 if (tem == 0 && (code == NE || BRANCH_COST > 1))
3103 if (rtx_equal_p (subtarget, op0))
3106 tem = expand_unop (mode, neg_optab, op0, subtarget, 0);
3107 tem = expand_binop (mode, ior_optab, tem, op0, subtarget, 0,
3110 if (tem && code == EQ)
3111 tem = expand_unop (mode, one_cmpl_optab, tem, subtarget, 0);
3115 if (tem && normalizep)
3116 tem = expand_shift (RSHIFT_EXPR, mode, tem,
3117 size_int (GET_MODE_BITSIZE (mode) - 1),
3118 tem, normalizep == 1);
3120 if (tem && GET_MODE (tem) != target_mode)
3122 convert_move (target, tem, 0);
3127 delete_insns_since (last);
3131 emit_jump_insn ((*bcc_gen_fctn[(int) code]) (label));
3132 emit_move_insn (target, const1_rtx);