1 /* Medium-level subroutines: convert bit-field store and extract
2 and shifts, multiplies and divides to rtl instructions.
3 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
4 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
6 Free Software Foundation, Inc.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it under
11 the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 3, or (at your option) any later
15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
27 #include "coretypes.h"
29 #include "diagnostic-core.h"
34 #include "insn-config.h"
38 #include "langhooks.h"
43 struct target_expmed default_target_expmed;
45 struct target_expmed *this_target_expmed = &default_target_expmed;
48 static void store_fixed_bit_field (rtx, unsigned HOST_WIDE_INT,
49 unsigned HOST_WIDE_INT,
50 unsigned HOST_WIDE_INT,
51 unsigned HOST_WIDE_INT,
52 unsigned HOST_WIDE_INT,
54 static void store_split_bit_field (rtx, unsigned HOST_WIDE_INT,
55 unsigned HOST_WIDE_INT,
56 unsigned HOST_WIDE_INT,
57 unsigned HOST_WIDE_INT,
59 static rtx extract_fixed_bit_field (enum machine_mode, rtx,
60 unsigned HOST_WIDE_INT,
61 unsigned HOST_WIDE_INT,
62 unsigned HOST_WIDE_INT, rtx, int, bool);
63 static rtx mask_rtx (enum machine_mode, int, int, int);
64 static rtx lshift_value (enum machine_mode, rtx, int, int);
65 static rtx extract_split_bit_field (rtx, unsigned HOST_WIDE_INT,
66 unsigned HOST_WIDE_INT, int);
67 static void do_cmp_and_jump (rtx, rtx, enum rtx_code, enum machine_mode, rtx);
68 static rtx expand_smod_pow2 (enum machine_mode, rtx, HOST_WIDE_INT);
69 static rtx expand_sdiv_pow2 (enum machine_mode, rtx, HOST_WIDE_INT);
71 /* Test whether a value is zero of a power of two. */
72 #define EXACT_POWER_OF_2_OR_ZERO_P(x) (((x) & ((x) - 1)) == 0)
74 #ifndef SLOW_UNALIGNED_ACCESS
75 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) STRICT_ALIGNMENT
79 /* Reduce conditional compilation elsewhere. */
82 #define CODE_FOR_insv CODE_FOR_nothing
83 #define gen_insv(a,b,c,d) NULL_RTX
87 #define CODE_FOR_extv CODE_FOR_nothing
88 #define gen_extv(a,b,c,d) NULL_RTX
92 #define CODE_FOR_extzv CODE_FOR_nothing
93 #define gen_extzv(a,b,c,d) NULL_RTX
101 struct rtx_def reg; rtunion reg_fld[2];
102 struct rtx_def plus; rtunion plus_fld1;
104 struct rtx_def mult; rtunion mult_fld1;
105 struct rtx_def sdiv; rtunion sdiv_fld1;
106 struct rtx_def udiv; rtunion udiv_fld1;
108 struct rtx_def sdiv_32; rtunion sdiv_32_fld1;
109 struct rtx_def smod_32; rtunion smod_32_fld1;
110 struct rtx_def wide_mult; rtunion wide_mult_fld1;
111 struct rtx_def wide_lshr; rtunion wide_lshr_fld1;
112 struct rtx_def wide_trunc;
113 struct rtx_def shift; rtunion shift_fld1;
114 struct rtx_def shift_mult; rtunion shift_mult_fld1;
115 struct rtx_def shift_add; rtunion shift_add_fld1;
116 struct rtx_def shift_sub0; rtunion shift_sub0_fld1;
117 struct rtx_def shift_sub1; rtunion shift_sub1_fld1;
120 rtx pow2[MAX_BITS_PER_WORD];
121 rtx cint[MAX_BITS_PER_WORD];
123 enum machine_mode mode, wider_mode;
127 for (m = 1; m < MAX_BITS_PER_WORD; m++)
129 pow2[m] = GEN_INT ((HOST_WIDE_INT) 1 << m);
130 cint[m] = GEN_INT (m);
132 memset (&all, 0, sizeof all);
134 PUT_CODE (&all.reg, REG);
135 /* Avoid using hard regs in ways which may be unsupported. */
136 SET_REGNO (&all.reg, LAST_VIRTUAL_REGISTER + 1);
138 PUT_CODE (&all.plus, PLUS);
139 XEXP (&all.plus, 0) = &all.reg;
140 XEXP (&all.plus, 1) = &all.reg;
142 PUT_CODE (&all.neg, NEG);
143 XEXP (&all.neg, 0) = &all.reg;
145 PUT_CODE (&all.mult, MULT);
146 XEXP (&all.mult, 0) = &all.reg;
147 XEXP (&all.mult, 1) = &all.reg;
149 PUT_CODE (&all.sdiv, DIV);
150 XEXP (&all.sdiv, 0) = &all.reg;
151 XEXP (&all.sdiv, 1) = &all.reg;
153 PUT_CODE (&all.udiv, UDIV);
154 XEXP (&all.udiv, 0) = &all.reg;
155 XEXP (&all.udiv, 1) = &all.reg;
157 PUT_CODE (&all.sdiv_32, DIV);
158 XEXP (&all.sdiv_32, 0) = &all.reg;
159 XEXP (&all.sdiv_32, 1) = 32 < MAX_BITS_PER_WORD ? cint[32] : GEN_INT (32);
161 PUT_CODE (&all.smod_32, MOD);
162 XEXP (&all.smod_32, 0) = &all.reg;
163 XEXP (&all.smod_32, 1) = XEXP (&all.sdiv_32, 1);
165 PUT_CODE (&all.zext, ZERO_EXTEND);
166 XEXP (&all.zext, 0) = &all.reg;
168 PUT_CODE (&all.wide_mult, MULT);
169 XEXP (&all.wide_mult, 0) = &all.zext;
170 XEXP (&all.wide_mult, 1) = &all.zext;
172 PUT_CODE (&all.wide_lshr, LSHIFTRT);
173 XEXP (&all.wide_lshr, 0) = &all.wide_mult;
175 PUT_CODE (&all.wide_trunc, TRUNCATE);
176 XEXP (&all.wide_trunc, 0) = &all.wide_lshr;
178 PUT_CODE (&all.shift, ASHIFT);
179 XEXP (&all.shift, 0) = &all.reg;
181 PUT_CODE (&all.shift_mult, MULT);
182 XEXP (&all.shift_mult, 0) = &all.reg;
184 PUT_CODE (&all.shift_add, PLUS);
185 XEXP (&all.shift_add, 0) = &all.shift_mult;
186 XEXP (&all.shift_add, 1) = &all.reg;
188 PUT_CODE (&all.shift_sub0, MINUS);
189 XEXP (&all.shift_sub0, 0) = &all.shift_mult;
190 XEXP (&all.shift_sub0, 1) = &all.reg;
192 PUT_CODE (&all.shift_sub1, MINUS);
193 XEXP (&all.shift_sub1, 0) = &all.reg;
194 XEXP (&all.shift_sub1, 1) = &all.shift_mult;
196 for (speed = 0; speed < 2; speed++)
198 crtl->maybe_hot_insn_p = speed;
199 zero_cost[speed] = set_src_cost (const0_rtx, speed);
201 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
203 mode = GET_MODE_WIDER_MODE (mode))
205 PUT_MODE (&all.reg, mode);
206 PUT_MODE (&all.plus, mode);
207 PUT_MODE (&all.neg, mode);
208 PUT_MODE (&all.mult, mode);
209 PUT_MODE (&all.sdiv, mode);
210 PUT_MODE (&all.udiv, mode);
211 PUT_MODE (&all.sdiv_32, mode);
212 PUT_MODE (&all.smod_32, mode);
213 PUT_MODE (&all.wide_trunc, mode);
214 PUT_MODE (&all.shift, mode);
215 PUT_MODE (&all.shift_mult, mode);
216 PUT_MODE (&all.shift_add, mode);
217 PUT_MODE (&all.shift_sub0, mode);
218 PUT_MODE (&all.shift_sub1, mode);
220 add_cost[speed][mode] = set_src_cost (&all.plus, speed);
221 neg_cost[speed][mode] = set_src_cost (&all.neg, speed);
222 mul_cost[speed][mode] = set_src_cost (&all.mult, speed);
223 sdiv_cost[speed][mode] = set_src_cost (&all.sdiv, speed);
224 udiv_cost[speed][mode] = set_src_cost (&all.udiv, speed);
226 sdiv_pow2_cheap[speed][mode] = (set_src_cost (&all.sdiv_32, speed)
227 <= 2 * add_cost[speed][mode]);
228 smod_pow2_cheap[speed][mode] = (set_src_cost (&all.smod_32, speed)
229 <= 4 * add_cost[speed][mode]);
231 wider_mode = GET_MODE_WIDER_MODE (mode);
232 if (wider_mode != VOIDmode)
234 PUT_MODE (&all.zext, wider_mode);
235 PUT_MODE (&all.wide_mult, wider_mode);
236 PUT_MODE (&all.wide_lshr, wider_mode);
237 XEXP (&all.wide_lshr, 1) = GEN_INT (GET_MODE_BITSIZE (mode));
239 mul_widen_cost[speed][wider_mode]
240 = set_src_cost (&all.wide_mult, speed);
241 mul_highpart_cost[speed][mode]
242 = set_src_cost (&all.wide_trunc, speed);
245 shift_cost[speed][mode][0] = 0;
246 shiftadd_cost[speed][mode][0] = shiftsub0_cost[speed][mode][0]
247 = shiftsub1_cost[speed][mode][0] = add_cost[speed][mode];
249 n = MIN (MAX_BITS_PER_WORD, GET_MODE_BITSIZE (mode));
250 for (m = 1; m < n; m++)
252 XEXP (&all.shift, 1) = cint[m];
253 XEXP (&all.shift_mult, 1) = pow2[m];
255 shift_cost[speed][mode][m] = set_src_cost (&all.shift, speed);
256 shiftadd_cost[speed][mode][m] = set_src_cost (&all.shift_add,
258 shiftsub0_cost[speed][mode][m] = set_src_cost (&all.shift_sub0,
260 shiftsub1_cost[speed][mode][m] = set_src_cost (&all.shift_sub1,
266 memset (alg_hash, 0, sizeof (alg_hash));
268 alg_hash_used_p = true;
269 default_rtl_profile ();
272 /* Return an rtx representing minus the value of X.
273 MODE is the intended mode of the result,
274 useful if X is a CONST_INT. */
277 negate_rtx (enum machine_mode mode, rtx x)
279 rtx result = simplify_unary_operation (NEG, mode, x, mode);
282 result = expand_unop (mode, neg_optab, x, NULL_RTX, 0);
287 /* Report on the availability of insv/extv/extzv and the desired mode
288 of each of their operands. Returns MAX_MACHINE_MODE if HAVE_foo
289 is false; else the mode of the specified operand. If OPNO is -1,
290 all the caller cares about is whether the insn is available. */
292 mode_for_extraction (enum extraction_pattern pattern, int opno)
294 const struct insn_data_d *data;
301 data = &insn_data[CODE_FOR_insv];
304 return MAX_MACHINE_MODE;
309 data = &insn_data[CODE_FOR_extv];
312 return MAX_MACHINE_MODE;
317 data = &insn_data[CODE_FOR_extzv];
320 return MAX_MACHINE_MODE;
329 /* Everyone who uses this function used to follow it with
330 if (result == VOIDmode) result = word_mode; */
331 if (data->operand[opno].mode == VOIDmode)
333 return data->operand[opno].mode;
336 /* A subroutine of store_bit_field, with the same arguments. Return true
337 if the operation could be implemented.
339 If FALLBACK_P is true, fall back to store_fixed_bit_field if we have
340 no other way of implementing the operation. If FALLBACK_P is false,
341 return false instead. */
344 store_bit_field_1 (rtx str_rtx, unsigned HOST_WIDE_INT bitsize,
345 unsigned HOST_WIDE_INT bitnum,
346 unsigned HOST_WIDE_INT bitregion_start,
347 unsigned HOST_WIDE_INT bitregion_end,
348 enum machine_mode fieldmode,
349 rtx value, bool fallback_p)
352 = (MEM_P (str_rtx)) ? BITS_PER_UNIT : BITS_PER_WORD;
353 unsigned HOST_WIDE_INT offset, bitpos;
358 enum machine_mode op_mode = mode_for_extraction (EP_insv, 3);
360 while (GET_CODE (op0) == SUBREG)
362 /* The following line once was done only if WORDS_BIG_ENDIAN,
363 but I think that is a mistake. WORDS_BIG_ENDIAN is
364 meaningful at a much higher level; when structures are copied
365 between memory and regs, the higher-numbered regs
366 always get higher addresses. */
367 int inner_mode_size = GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0)));
368 int outer_mode_size = GET_MODE_SIZE (GET_MODE (op0));
372 /* Paradoxical subregs need special handling on big endian machines. */
373 if (SUBREG_BYTE (op0) == 0 && inner_mode_size < outer_mode_size)
375 int difference = inner_mode_size - outer_mode_size;
377 if (WORDS_BIG_ENDIAN)
378 byte_offset += (difference / UNITS_PER_WORD) * UNITS_PER_WORD;
379 if (BYTES_BIG_ENDIAN)
380 byte_offset += difference % UNITS_PER_WORD;
383 byte_offset = SUBREG_BYTE (op0);
385 bitnum += byte_offset * BITS_PER_UNIT;
386 op0 = SUBREG_REG (op0);
389 /* No action is needed if the target is a register and if the field
390 lies completely outside that register. This can occur if the source
391 code contains an out-of-bounds access to a small array. */
392 if (REG_P (op0) && bitnum >= GET_MODE_BITSIZE (GET_MODE (op0)))
395 /* Use vec_set patterns for inserting parts of vectors whenever
397 if (VECTOR_MODE_P (GET_MODE (op0))
399 && optab_handler (vec_set_optab, GET_MODE (op0)) != CODE_FOR_nothing
400 && fieldmode == GET_MODE_INNER (GET_MODE (op0))
401 && bitsize == GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0)))
402 && !(bitnum % GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0)))))
404 struct expand_operand ops[3];
405 enum machine_mode outermode = GET_MODE (op0);
406 enum machine_mode innermode = GET_MODE_INNER (outermode);
407 enum insn_code icode = optab_handler (vec_set_optab, outermode);
408 int pos = bitnum / GET_MODE_BITSIZE (innermode);
410 create_fixed_operand (&ops[0], op0);
411 create_input_operand (&ops[1], value, innermode);
412 create_integer_operand (&ops[2], pos);
413 if (maybe_expand_insn (icode, 3, ops))
417 /* If the target is a register, overwriting the entire object, or storing
418 a full-word or multi-word field can be done with just a SUBREG.
420 If the target is memory, storing any naturally aligned field can be
421 done with a simple store. For targets that support fast unaligned
422 memory, any naturally sized, unit aligned field can be done directly. */
424 offset = bitnum / unit;
425 bitpos = bitnum % unit;
426 byte_offset = (bitnum % BITS_PER_WORD) / BITS_PER_UNIT
427 + (offset * UNITS_PER_WORD);
430 && bitsize == GET_MODE_BITSIZE (fieldmode)
432 ? ((GET_MODE_SIZE (fieldmode) >= UNITS_PER_WORD
433 || GET_MODE_SIZE (GET_MODE (op0)) == GET_MODE_SIZE (fieldmode))
434 && ((GET_MODE (op0) == fieldmode && byte_offset == 0)
435 || validate_subreg (fieldmode, GET_MODE (op0), op0,
437 : (! SLOW_UNALIGNED_ACCESS (fieldmode, MEM_ALIGN (op0))
438 || (offset * BITS_PER_UNIT % bitsize == 0
439 && MEM_ALIGN (op0) % GET_MODE_BITSIZE (fieldmode) == 0))))
442 op0 = adjust_address (op0, fieldmode, offset);
443 else if (GET_MODE (op0) != fieldmode)
444 op0 = simplify_gen_subreg (fieldmode, op0, GET_MODE (op0),
446 emit_move_insn (op0, value);
450 /* Make sure we are playing with integral modes. Pun with subregs
451 if we aren't. This must come after the entire register case above,
452 since that case is valid for any mode. The following cases are only
453 valid for integral modes. */
455 enum machine_mode imode = int_mode_for_mode (GET_MODE (op0));
456 if (imode != GET_MODE (op0))
459 op0 = adjust_address (op0, imode, 0);
462 gcc_assert (imode != BLKmode);
463 op0 = gen_lowpart (imode, op0);
468 /* We may be accessing data outside the field, which means
469 we can alias adjacent data. */
470 /* ?? not always for C++0x memory model ?? */
473 op0 = shallow_copy_rtx (op0);
474 set_mem_alias_set (op0, 0);
475 set_mem_expr (op0, 0);
478 /* If OP0 is a register, BITPOS must count within a word.
479 But as we have it, it counts within whatever size OP0 now has.
480 On a bigendian machine, these are not the same, so convert. */
483 && unit > GET_MODE_BITSIZE (GET_MODE (op0)))
484 bitpos += unit - GET_MODE_BITSIZE (GET_MODE (op0));
486 /* Storing an lsb-aligned field in a register
487 can be done with a movestrict instruction. */
490 && (BYTES_BIG_ENDIAN ? bitpos + bitsize == unit : bitpos == 0)
491 && bitsize == GET_MODE_BITSIZE (fieldmode)
492 && optab_handler (movstrict_optab, fieldmode) != CODE_FOR_nothing)
494 struct expand_operand ops[2];
495 enum insn_code icode = optab_handler (movstrict_optab, fieldmode);
497 unsigned HOST_WIDE_INT subreg_off;
499 if (GET_CODE (arg0) == SUBREG)
501 /* Else we've got some float mode source being extracted into
502 a different float mode destination -- this combination of
503 subregs results in Severe Tire Damage. */
504 gcc_assert (GET_MODE (SUBREG_REG (arg0)) == fieldmode
505 || GET_MODE_CLASS (fieldmode) == MODE_INT
506 || GET_MODE_CLASS (fieldmode) == MODE_PARTIAL_INT);
507 arg0 = SUBREG_REG (arg0);
510 subreg_off = (bitnum % BITS_PER_WORD) / BITS_PER_UNIT
511 + (offset * UNITS_PER_WORD);
512 if (validate_subreg (fieldmode, GET_MODE (arg0), arg0, subreg_off))
514 arg0 = gen_rtx_SUBREG (fieldmode, arg0, subreg_off);
516 create_fixed_operand (&ops[0], arg0);
517 /* Shrink the source operand to FIELDMODE. */
518 create_convert_operand_to (&ops[1], value, fieldmode, false);
519 if (maybe_expand_insn (icode, 2, ops))
524 /* Handle fields bigger than a word. */
526 if (bitsize > BITS_PER_WORD)
528 /* Here we transfer the words of the field
529 in the order least significant first.
530 This is because the most significant word is the one which may
532 However, only do that if the value is not BLKmode. */
534 unsigned int backwards = WORDS_BIG_ENDIAN && fieldmode != BLKmode;
535 unsigned int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD;
539 /* This is the mode we must force value to, so that there will be enough
540 subwords to extract. Note that fieldmode will often (always?) be
541 VOIDmode, because that is what store_field uses to indicate that this
542 is a bit field, but passing VOIDmode to operand_subword_force
544 fieldmode = GET_MODE (value);
545 if (fieldmode == VOIDmode)
546 fieldmode = smallest_mode_for_size (nwords * BITS_PER_WORD, MODE_INT);
548 last = get_last_insn ();
549 for (i = 0; i < nwords; i++)
551 /* If I is 0, use the low-order word in both field and target;
552 if I is 1, use the next to lowest word; and so on. */
553 unsigned int wordnum = (backwards ? nwords - i - 1 : i);
554 unsigned int bit_offset = (backwards
555 ? MAX ((int) bitsize - ((int) i + 1)
558 : (int) i * BITS_PER_WORD);
559 rtx value_word = operand_subword_force (value, wordnum, fieldmode);
560 unsigned HOST_WIDE_INT new_bitsize =
561 MIN (BITS_PER_WORD, bitsize - i * BITS_PER_WORD);
563 /* If the remaining chunk doesn't have full wordsize we have
564 to make sure that for big endian machines the higher order
566 if (new_bitsize < BITS_PER_WORD && BYTES_BIG_ENDIAN)
567 value_word = extract_bit_field (value_word, new_bitsize, 0,
568 true, false, NULL_RTX,
571 if (!store_bit_field_1 (op0, new_bitsize,
573 bitregion_start, bitregion_end,
575 value_word, fallback_p))
577 delete_insns_since (last);
584 /* From here on we can assume that the field to be stored in is
585 a full-word (whatever type that is), since it is shorter than a word. */
587 /* OFFSET is the number of words or bytes (UNIT says which)
588 from STR_RTX to the first word or byte containing part of the field. */
593 || GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD)
597 /* Since this is a destination (lvalue), we can't copy
598 it to a pseudo. We can remove a SUBREG that does not
599 change the size of the operand. Such a SUBREG may
600 have been added above. */
601 gcc_assert (GET_CODE (op0) == SUBREG
602 && (GET_MODE_SIZE (GET_MODE (op0))
603 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0)))));
604 op0 = SUBREG_REG (op0);
606 op0 = gen_rtx_SUBREG (mode_for_size (BITS_PER_WORD, MODE_INT, 0),
607 op0, (offset * UNITS_PER_WORD));
612 /* If VALUE has a floating-point or complex mode, access it as an
613 integer of the corresponding size. This can occur on a machine
614 with 64 bit registers that uses SFmode for float. It can also
615 occur for unaligned float or complex fields. */
617 if (GET_MODE (value) != VOIDmode
618 && GET_MODE_CLASS (GET_MODE (value)) != MODE_INT
619 && GET_MODE_CLASS (GET_MODE (value)) != MODE_PARTIAL_INT)
621 value = gen_reg_rtx (int_mode_for_mode (GET_MODE (value)));
622 emit_move_insn (gen_lowpart (GET_MODE (orig_value), value), orig_value);
625 /* Now OFFSET is nonzero only if OP0 is memory
626 and is therefore always measured in bytes. */
629 && GET_MODE (value) != BLKmode
631 && GET_MODE_BITSIZE (op_mode) >= bitsize
632 /* Do not use insv for volatile bitfields when
633 -fstrict-volatile-bitfields is in effect. */
634 && !(MEM_P (op0) && MEM_VOLATILE_P (op0)
635 && flag_strict_volatile_bitfields > 0)
636 && ! ((REG_P (op0) || GET_CODE (op0) == SUBREG)
637 && (bitsize + bitpos > GET_MODE_BITSIZE (op_mode))))
639 struct expand_operand ops[4];
640 int xbitpos = bitpos;
643 rtx last = get_last_insn ();
644 bool copy_back = false;
646 /* Add OFFSET into OP0's address. */
648 xop0 = adjust_address (xop0, byte_mode, offset);
650 /* If xop0 is a register, we need it in OP_MODE
651 to make it acceptable to the format of insv. */
652 if (GET_CODE (xop0) == SUBREG)
653 /* We can't just change the mode, because this might clobber op0,
654 and we will need the original value of op0 if insv fails. */
655 xop0 = gen_rtx_SUBREG (op_mode, SUBREG_REG (xop0), SUBREG_BYTE (xop0));
656 if (REG_P (xop0) && GET_MODE (xop0) != op_mode)
657 xop0 = gen_lowpart_SUBREG (op_mode, xop0);
659 /* If the destination is a paradoxical subreg such that we need a
660 truncate to the inner mode, perform the insertion on a temporary and
661 truncate the result to the original destination. Note that we can't
662 just truncate the paradoxical subreg as (truncate:N (subreg:W (reg:N
663 X) 0)) is (reg:N X). */
664 if (GET_CODE (xop0) == SUBREG
665 && REG_P (SUBREG_REG (xop0))
666 && (!TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (SUBREG_REG (xop0)),
669 rtx tem = gen_reg_rtx (op_mode);
670 emit_move_insn (tem, xop0);
675 /* We have been counting XBITPOS within UNIT.
676 Count instead within the size of the register. */
677 if (BYTES_BIG_ENDIAN && !MEM_P (xop0))
678 xbitpos += GET_MODE_BITSIZE (op_mode) - unit;
680 unit = GET_MODE_BITSIZE (op_mode);
682 /* If BITS_BIG_ENDIAN is zero on a BYTES_BIG_ENDIAN machine, we count
683 "backwards" from the size of the unit we are inserting into.
684 Otherwise, we count bits from the most significant on a
685 BYTES/BITS_BIG_ENDIAN machine. */
687 if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
688 xbitpos = unit - bitsize - xbitpos;
690 /* Convert VALUE to op_mode (which insv insn wants) in VALUE1. */
692 if (GET_MODE (value) != op_mode)
694 if (GET_MODE_BITSIZE (GET_MODE (value)) >= bitsize)
696 /* Optimization: Don't bother really extending VALUE
697 if it has all the bits we will actually use. However,
698 if we must narrow it, be sure we do it correctly. */
700 if (GET_MODE_SIZE (GET_MODE (value)) < GET_MODE_SIZE (op_mode))
704 tmp = simplify_subreg (op_mode, value1, GET_MODE (value), 0);
706 tmp = simplify_gen_subreg (op_mode,
707 force_reg (GET_MODE (value),
709 GET_MODE (value), 0);
713 value1 = gen_lowpart (op_mode, value1);
715 else if (CONST_INT_P (value))
716 value1 = gen_int_mode (INTVAL (value), op_mode);
718 /* Parse phase is supposed to make VALUE's data type
719 match that of the component reference, which is a type
720 at least as wide as the field; so VALUE should have
721 a mode that corresponds to that type. */
722 gcc_assert (CONSTANT_P (value));
725 create_fixed_operand (&ops[0], xop0);
726 create_integer_operand (&ops[1], bitsize);
727 create_integer_operand (&ops[2], xbitpos);
728 create_input_operand (&ops[3], value1, op_mode);
729 if (maybe_expand_insn (CODE_FOR_insv, 4, ops))
732 convert_move (op0, xop0, true);
735 delete_insns_since (last);
738 /* If OP0 is a memory, try copying it to a register and seeing if a
739 cheap register alternative is available. */
740 if (HAVE_insv && MEM_P (op0))
742 enum machine_mode bestmode;
743 unsigned HOST_WIDE_INT maxbits = MAX_FIXED_MODE_SIZE;
746 maxbits = bitregion_end - bitregion_start + 1;
748 /* Get the mode to use for inserting into this field. If OP0 is
749 BLKmode, get the smallest mode consistent with the alignment. If
750 OP0 is a non-BLKmode object that is no wider than OP_MODE, use its
751 mode. Otherwise, use the smallest mode containing the field. */
753 if (GET_MODE (op0) == BLKmode
754 || GET_MODE_BITSIZE (GET_MODE (op0)) > maxbits
755 || (op_mode != MAX_MACHINE_MODE
756 && GET_MODE_SIZE (GET_MODE (op0)) > GET_MODE_SIZE (op_mode)))
757 bestmode = get_best_mode (bitsize, bitnum,
758 bitregion_start, bitregion_end,
760 (op_mode == MAX_MACHINE_MODE
761 ? VOIDmode : op_mode),
762 MEM_VOLATILE_P (op0));
764 bestmode = GET_MODE (op0);
766 if (bestmode != VOIDmode
767 && GET_MODE_SIZE (bestmode) >= GET_MODE_SIZE (fieldmode)
768 && !(SLOW_UNALIGNED_ACCESS (bestmode, MEM_ALIGN (op0))
769 && GET_MODE_BITSIZE (bestmode) > MEM_ALIGN (op0)))
771 rtx last, tempreg, xop0;
772 unsigned HOST_WIDE_INT xoffset, xbitpos;
774 last = get_last_insn ();
776 /* Adjust address to point to the containing unit of
777 that mode. Compute the offset as a multiple of this unit,
778 counting in bytes. */
779 unit = GET_MODE_BITSIZE (bestmode);
780 xoffset = (bitnum / unit) * GET_MODE_SIZE (bestmode);
781 xbitpos = bitnum % unit;
782 xop0 = adjust_address (op0, bestmode, xoffset);
784 /* Fetch that unit, store the bitfield in it, then store
786 tempreg = copy_to_reg (xop0);
787 if (store_bit_field_1 (tempreg, bitsize, xbitpos,
788 bitregion_start, bitregion_end,
789 fieldmode, orig_value, false))
791 emit_move_insn (xop0, tempreg);
794 delete_insns_since (last);
801 store_fixed_bit_field (op0, offset, bitsize, bitpos,
802 bitregion_start, bitregion_end, value);
806 /* Generate code to store value from rtx VALUE
807 into a bit-field within structure STR_RTX
808 containing BITSIZE bits starting at bit BITNUM.
810 BITREGION_START is bitpos of the first bitfield in this region.
811 BITREGION_END is the bitpos of the ending bitfield in this region.
812 These two fields are 0, if the C++ memory model does not apply,
813 or we are not interested in keeping track of bitfield regions.
815 FIELDMODE is the machine-mode of the FIELD_DECL node for this field. */
818 store_bit_field (rtx str_rtx, unsigned HOST_WIDE_INT bitsize,
819 unsigned HOST_WIDE_INT bitnum,
820 unsigned HOST_WIDE_INT bitregion_start,
821 unsigned HOST_WIDE_INT bitregion_end,
822 enum machine_mode fieldmode,
825 /* Under the C++0x memory model, we must not touch bits outside the
826 bit region. Adjust the address to start at the beginning of the
829 && bitregion_start > 0)
831 enum machine_mode bestmode;
832 enum machine_mode op_mode;
833 unsigned HOST_WIDE_INT offset;
835 op_mode = mode_for_extraction (EP_insv, 3);
836 if (op_mode == MAX_MACHINE_MODE)
839 offset = bitregion_start / BITS_PER_UNIT;
840 bitnum -= bitregion_start;
841 bitregion_end -= bitregion_start;
843 bestmode = get_best_mode (bitsize, bitnum,
844 bitregion_start, bitregion_end,
847 MEM_VOLATILE_P (str_rtx));
848 str_rtx = adjust_address (str_rtx, bestmode, offset);
851 if (!store_bit_field_1 (str_rtx, bitsize, bitnum,
852 bitregion_start, bitregion_end,
853 fieldmode, value, true))
857 /* Use shifts and boolean operations to store VALUE
858 into a bit field of width BITSIZE
859 in a memory location specified by OP0 except offset by OFFSET bytes.
860 (OFFSET must be 0 if OP0 is a register.)
861 The field starts at position BITPOS within the byte.
862 (If OP0 is a register, it may be a full word or a narrower mode,
863 but BITPOS still counts within a full word,
864 which is significant on bigendian machines.) */
867 store_fixed_bit_field (rtx op0, unsigned HOST_WIDE_INT offset,
868 unsigned HOST_WIDE_INT bitsize,
869 unsigned HOST_WIDE_INT bitpos,
870 unsigned HOST_WIDE_INT bitregion_start,
871 unsigned HOST_WIDE_INT bitregion_end,
874 enum machine_mode mode;
875 unsigned int total_bits = BITS_PER_WORD;
880 /* There is a case not handled here:
881 a structure with a known alignment of just a halfword
882 and a field split across two aligned halfwords within the structure.
883 Or likewise a structure with a known alignment of just a byte
884 and a field split across two bytes.
885 Such cases are not supposed to be able to occur. */
887 if (REG_P (op0) || GET_CODE (op0) == SUBREG)
889 gcc_assert (!offset);
890 /* Special treatment for a bit field split across two registers. */
891 if (bitsize + bitpos > BITS_PER_WORD)
893 store_split_bit_field (op0, bitsize, bitpos,
894 bitregion_start, bitregion_end,
901 unsigned HOST_WIDE_INT maxbits = MAX_FIXED_MODE_SIZE;
904 maxbits = bitregion_end - bitregion_start + 1;
906 /* Get the proper mode to use for this field. We want a mode that
907 includes the entire field. If such a mode would be larger than
908 a word, we won't be doing the extraction the normal way.
909 We don't want a mode bigger than the destination. */
911 mode = GET_MODE (op0);
912 if (GET_MODE_BITSIZE (mode) == 0
913 || GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (word_mode))
916 if (MEM_VOLATILE_P (op0)
917 && GET_MODE_BITSIZE (GET_MODE (op0)) > 0
918 && GET_MODE_BITSIZE (GET_MODE (op0)) <= maxbits
919 && flag_strict_volatile_bitfields > 0)
920 mode = GET_MODE (op0);
922 mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT,
923 bitregion_start, bitregion_end,
924 MEM_ALIGN (op0), mode, MEM_VOLATILE_P (op0));
926 if (mode == VOIDmode)
928 /* The only way this should occur is if the field spans word
930 store_split_bit_field (op0, bitsize, bitpos + offset * BITS_PER_UNIT,
931 bitregion_start, bitregion_end, value);
935 total_bits = GET_MODE_BITSIZE (mode);
937 /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to
938 be in the range 0 to total_bits-1, and put any excess bytes in
940 if (bitpos >= total_bits)
942 offset += (bitpos / total_bits) * (total_bits / BITS_PER_UNIT);
943 bitpos -= ((bitpos / total_bits) * (total_bits / BITS_PER_UNIT)
947 /* Get ref to an aligned byte, halfword, or word containing the field.
948 Adjust BITPOS to be position within a word,
949 and OFFSET to be the offset of that word.
950 Then alter OP0 to refer to that word. */
951 bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT;
952 offset -= (offset % (total_bits / BITS_PER_UNIT));
953 op0 = adjust_address (op0, mode, offset);
956 mode = GET_MODE (op0);
958 /* Now MODE is either some integral mode for a MEM as OP0,
959 or is a full-word for a REG as OP0. TOTAL_BITS corresponds.
960 The bit field is contained entirely within OP0.
961 BITPOS is the starting bit number within OP0.
962 (OP0's mode may actually be narrower than MODE.) */
964 if (BYTES_BIG_ENDIAN)
965 /* BITPOS is the distance between our msb
966 and that of the containing datum.
967 Convert it to the distance from the lsb. */
968 bitpos = total_bits - bitsize - bitpos;
970 /* Now BITPOS is always the distance between our lsb
973 /* Shift VALUE left by BITPOS bits. If VALUE is not constant,
974 we must first convert its mode to MODE. */
976 if (CONST_INT_P (value))
978 HOST_WIDE_INT v = INTVAL (value);
980 if (bitsize < HOST_BITS_PER_WIDE_INT)
981 v &= ((HOST_WIDE_INT) 1 << bitsize) - 1;
985 else if ((bitsize < HOST_BITS_PER_WIDE_INT
986 && v == ((HOST_WIDE_INT) 1 << bitsize) - 1)
987 || (bitsize == HOST_BITS_PER_WIDE_INT && v == -1))
990 value = lshift_value (mode, value, bitpos, bitsize);
994 int must_and = (GET_MODE_BITSIZE (GET_MODE (value)) != bitsize
995 && bitpos + bitsize != GET_MODE_BITSIZE (mode));
997 if (GET_MODE (value) != mode)
998 value = convert_to_mode (mode, value, 1);
1001 value = expand_binop (mode, and_optab, value,
1002 mask_rtx (mode, 0, bitsize, 0),
1003 NULL_RTX, 1, OPTAB_LIB_WIDEN);
1005 value = expand_shift (LSHIFT_EXPR, mode, value,
1006 bitpos, NULL_RTX, 1);
1009 /* Now clear the chosen bits in OP0,
1010 except that if VALUE is -1 we need not bother. */
1011 /* We keep the intermediates in registers to allow CSE to combine
1012 consecutive bitfield assignments. */
1014 temp = force_reg (mode, op0);
1018 temp = expand_binop (mode, and_optab, temp,
1019 mask_rtx (mode, bitpos, bitsize, 1),
1020 NULL_RTX, 1, OPTAB_LIB_WIDEN);
1021 temp = force_reg (mode, temp);
1024 /* Now logical-or VALUE into OP0, unless it is zero. */
1028 temp = expand_binop (mode, ior_optab, temp, value,
1029 NULL_RTX, 1, OPTAB_LIB_WIDEN);
1030 temp = force_reg (mode, temp);
1035 op0 = copy_rtx (op0);
1036 emit_move_insn (op0, temp);
1040 /* Store a bit field that is split across multiple accessible memory objects.
1042 OP0 is the REG, SUBREG or MEM rtx for the first of the objects.
1043 BITSIZE is the field width; BITPOS the position of its first bit
1045 VALUE is the value to store.
1047 This does not yet handle fields wider than BITS_PER_WORD. */
1050 store_split_bit_field (rtx op0, unsigned HOST_WIDE_INT bitsize,
1051 unsigned HOST_WIDE_INT bitpos,
1052 unsigned HOST_WIDE_INT bitregion_start,
1053 unsigned HOST_WIDE_INT bitregion_end,
1057 unsigned int bitsdone = 0;
1059 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
1061 if (REG_P (op0) || GET_CODE (op0) == SUBREG)
1062 unit = BITS_PER_WORD;
1064 unit = MIN (MEM_ALIGN (op0), BITS_PER_WORD);
1066 /* If VALUE is a constant other than a CONST_INT, get it into a register in
1067 WORD_MODE. If we can do this using gen_lowpart_common, do so. Note
1068 that VALUE might be a floating-point constant. */
1069 if (CONSTANT_P (value) && !CONST_INT_P (value))
1071 rtx word = gen_lowpart_common (word_mode, value);
1073 if (word && (value != word))
1076 value = gen_lowpart_common (word_mode,
1077 force_reg (GET_MODE (value) != VOIDmode
1079 : word_mode, value));
1082 while (bitsdone < bitsize)
1084 unsigned HOST_WIDE_INT thissize;
1086 unsigned HOST_WIDE_INT thispos;
1087 unsigned HOST_WIDE_INT offset;
1089 offset = (bitpos + bitsdone) / unit;
1090 thispos = (bitpos + bitsdone) % unit;
1092 /* THISSIZE must not overrun a word boundary. Otherwise,
1093 store_fixed_bit_field will call us again, and we will mutually
1095 thissize = MIN (bitsize - bitsdone, BITS_PER_WORD);
1096 thissize = MIN (thissize, unit - thispos);
1098 if (BYTES_BIG_ENDIAN)
1102 /* We must do an endian conversion exactly the same way as it is
1103 done in extract_bit_field, so that the two calls to
1104 extract_fixed_bit_field will have comparable arguments. */
1105 if (!MEM_P (value) || GET_MODE (value) == BLKmode)
1106 total_bits = BITS_PER_WORD;
1108 total_bits = GET_MODE_BITSIZE (GET_MODE (value));
1110 /* Fetch successively less significant portions. */
1111 if (CONST_INT_P (value))
1112 part = GEN_INT (((unsigned HOST_WIDE_INT) (INTVAL (value))
1113 >> (bitsize - bitsdone - thissize))
1114 & (((HOST_WIDE_INT) 1 << thissize) - 1));
1116 /* The args are chosen so that the last part includes the
1117 lsb. Give extract_bit_field the value it needs (with
1118 endianness compensation) to fetch the piece we want. */
1119 part = extract_fixed_bit_field (word_mode, value, 0, thissize,
1120 total_bits - bitsize + bitsdone,
1121 NULL_RTX, 1, false);
1125 /* Fetch successively more significant portions. */
1126 if (CONST_INT_P (value))
1127 part = GEN_INT (((unsigned HOST_WIDE_INT) (INTVAL (value))
1129 & (((HOST_WIDE_INT) 1 << thissize) - 1));
1131 part = extract_fixed_bit_field (word_mode, value, 0, thissize,
1132 bitsdone, NULL_RTX, 1, false);
1135 /* If OP0 is a register, then handle OFFSET here.
1137 When handling multiword bitfields, extract_bit_field may pass
1138 down a word_mode SUBREG of a larger REG for a bitfield that actually
1139 crosses a word boundary. Thus, for a SUBREG, we must find
1140 the current word starting from the base register. */
1141 if (GET_CODE (op0) == SUBREG)
1143 int word_offset = (SUBREG_BYTE (op0) / UNITS_PER_WORD) + offset;
1144 enum machine_mode sub_mode = GET_MODE (SUBREG_REG (op0));
1145 if (sub_mode != BLKmode && GET_MODE_SIZE (sub_mode) < UNITS_PER_WORD)
1146 word = word_offset ? const0_rtx : op0;
1148 word = operand_subword_force (SUBREG_REG (op0), word_offset,
1149 GET_MODE (SUBREG_REG (op0)));
1152 else if (REG_P (op0))
1154 enum machine_mode op0_mode = GET_MODE (op0);
1155 if (op0_mode != BLKmode && GET_MODE_SIZE (op0_mode) < UNITS_PER_WORD)
1156 word = offset ? const0_rtx : op0;
1158 word = operand_subword_force (op0, offset, GET_MODE (op0));
1164 /* OFFSET is in UNITs, and UNIT is in bits.
1165 store_fixed_bit_field wants offset in bytes. If WORD is const0_rtx,
1166 it is just an out-of-bounds access. Ignore it. */
1167 if (word != const0_rtx)
1168 store_fixed_bit_field (word, offset * unit / BITS_PER_UNIT, thissize,
1169 thispos, bitregion_start, bitregion_end, part);
1170 bitsdone += thissize;
1174 /* A subroutine of extract_bit_field_1 that converts return value X
1175 to either MODE or TMODE. MODE, TMODE and UNSIGNEDP are arguments
1176 to extract_bit_field. */
1179 convert_extracted_bit_field (rtx x, enum machine_mode mode,
1180 enum machine_mode tmode, bool unsignedp)
1182 if (GET_MODE (x) == tmode || GET_MODE (x) == mode)
1185 /* If the x mode is not a scalar integral, first convert to the
1186 integer mode of that size and then access it as a floating-point
1187 value via a SUBREG. */
1188 if (!SCALAR_INT_MODE_P (tmode))
1190 enum machine_mode smode;
1192 smode = mode_for_size (GET_MODE_BITSIZE (tmode), MODE_INT, 0);
1193 x = convert_to_mode (smode, x, unsignedp);
1194 x = force_reg (smode, x);
1195 return gen_lowpart (tmode, x);
1198 return convert_to_mode (tmode, x, unsignedp);
1201 /* A subroutine of extract_bit_field, with the same arguments.
1202 If FALLBACK_P is true, fall back to extract_fixed_bit_field
1203 if we can find no other means of implementing the operation.
1204 if FALLBACK_P is false, return NULL instead. */
1207 extract_bit_field_1 (rtx str_rtx, unsigned HOST_WIDE_INT bitsize,
1208 unsigned HOST_WIDE_INT bitnum,
1209 int unsignedp, bool packedp, rtx target,
1210 enum machine_mode mode, enum machine_mode tmode,
1214 = (MEM_P (str_rtx)) ? BITS_PER_UNIT : BITS_PER_WORD;
1215 unsigned HOST_WIDE_INT offset, bitpos;
1217 enum machine_mode int_mode;
1218 enum machine_mode ext_mode;
1219 enum machine_mode mode1;
1222 if (tmode == VOIDmode)
1225 while (GET_CODE (op0) == SUBREG)
1227 bitnum += SUBREG_BYTE (op0) * BITS_PER_UNIT;
1228 op0 = SUBREG_REG (op0);
1231 /* If we have an out-of-bounds access to a register, just return an
1232 uninitialized register of the required mode. This can occur if the
1233 source code contains an out-of-bounds access to a small array. */
1234 if (REG_P (op0) && bitnum >= GET_MODE_BITSIZE (GET_MODE (op0)))
1235 return gen_reg_rtx (tmode);
1238 && mode == GET_MODE (op0)
1240 && bitsize == GET_MODE_BITSIZE (GET_MODE (op0)))
1242 /* We're trying to extract a full register from itself. */
1246 /* See if we can get a better vector mode before extracting. */
1247 if (VECTOR_MODE_P (GET_MODE (op0))
1249 && GET_MODE_INNER (GET_MODE (op0)) != tmode)
1251 enum machine_mode new_mode;
1253 if (GET_MODE_CLASS (tmode) == MODE_FLOAT)
1254 new_mode = MIN_MODE_VECTOR_FLOAT;
1255 else if (GET_MODE_CLASS (tmode) == MODE_FRACT)
1256 new_mode = MIN_MODE_VECTOR_FRACT;
1257 else if (GET_MODE_CLASS (tmode) == MODE_UFRACT)
1258 new_mode = MIN_MODE_VECTOR_UFRACT;
1259 else if (GET_MODE_CLASS (tmode) == MODE_ACCUM)
1260 new_mode = MIN_MODE_VECTOR_ACCUM;
1261 else if (GET_MODE_CLASS (tmode) == MODE_UACCUM)
1262 new_mode = MIN_MODE_VECTOR_UACCUM;
1264 new_mode = MIN_MODE_VECTOR_INT;
1266 for (; new_mode != VOIDmode ; new_mode = GET_MODE_WIDER_MODE (new_mode))
1267 if (GET_MODE_SIZE (new_mode) == GET_MODE_SIZE (GET_MODE (op0))
1268 && targetm.vector_mode_supported_p (new_mode))
1270 if (new_mode != VOIDmode)
1271 op0 = gen_lowpart (new_mode, op0);
1274 /* Use vec_extract patterns for extracting parts of vectors whenever
1276 if (VECTOR_MODE_P (GET_MODE (op0))
1278 && optab_handler (vec_extract_optab, GET_MODE (op0)) != CODE_FOR_nothing
1279 && ((bitnum + bitsize - 1) / GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0)))
1280 == bitnum / GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0)))))
1282 struct expand_operand ops[3];
1283 enum machine_mode outermode = GET_MODE (op0);
1284 enum machine_mode innermode = GET_MODE_INNER (outermode);
1285 enum insn_code icode = optab_handler (vec_extract_optab, outermode);
1286 unsigned HOST_WIDE_INT pos = bitnum / GET_MODE_BITSIZE (innermode);
1288 create_output_operand (&ops[0], target, innermode);
1289 create_input_operand (&ops[1], op0, outermode);
1290 create_integer_operand (&ops[2], pos);
1291 if (maybe_expand_insn (icode, 3, ops))
1293 target = ops[0].value;
1294 if (GET_MODE (target) != mode)
1295 return gen_lowpart (tmode, target);
1300 /* Make sure we are playing with integral modes. Pun with subregs
1303 enum machine_mode imode = int_mode_for_mode (GET_MODE (op0));
1304 if (imode != GET_MODE (op0))
1307 op0 = adjust_address (op0, imode, 0);
1308 else if (imode != BLKmode)
1310 op0 = gen_lowpart (imode, op0);
1312 /* If we got a SUBREG, force it into a register since we
1313 aren't going to be able to do another SUBREG on it. */
1314 if (GET_CODE (op0) == SUBREG)
1315 op0 = force_reg (imode, op0);
1317 else if (REG_P (op0))
1320 imode = smallest_mode_for_size (GET_MODE_BITSIZE (GET_MODE (op0)),
1322 reg = gen_reg_rtx (imode);
1323 subreg = gen_lowpart_SUBREG (GET_MODE (op0), reg);
1324 emit_move_insn (subreg, op0);
1326 bitnum += SUBREG_BYTE (subreg) * BITS_PER_UNIT;
1330 rtx mem = assign_stack_temp (GET_MODE (op0),
1331 GET_MODE_SIZE (GET_MODE (op0)), 0);
1332 emit_move_insn (mem, op0);
1333 op0 = adjust_address (mem, BLKmode, 0);
1338 /* We may be accessing data outside the field, which means
1339 we can alias adjacent data. */
1342 op0 = shallow_copy_rtx (op0);
1343 set_mem_alias_set (op0, 0);
1344 set_mem_expr (op0, 0);
1347 /* Extraction of a full-word or multi-word value from a structure
1348 in a register or aligned memory can be done with just a SUBREG.
1349 A subword value in the least significant part of a register
1350 can also be extracted with a SUBREG. For this, we need the
1351 byte offset of the value in op0. */
1353 bitpos = bitnum % unit;
1354 offset = bitnum / unit;
1355 byte_offset = bitpos / BITS_PER_UNIT + offset * UNITS_PER_WORD;
1357 /* If OP0 is a register, BITPOS must count within a word.
1358 But as we have it, it counts within whatever size OP0 now has.
1359 On a bigendian machine, these are not the same, so convert. */
1360 if (BYTES_BIG_ENDIAN
1362 && unit > GET_MODE_BITSIZE (GET_MODE (op0)))
1363 bitpos += unit - GET_MODE_BITSIZE (GET_MODE (op0));
1365 /* ??? We currently assume TARGET is at least as big as BITSIZE.
1366 If that's wrong, the solution is to test for it and set TARGET to 0
1369 /* Only scalar integer modes can be converted via subregs. There is an
1370 additional problem for FP modes here in that they can have a precision
1371 which is different from the size. mode_for_size uses precision, but
1372 we want a mode based on the size, so we must avoid calling it for FP
1374 mode1 = (SCALAR_INT_MODE_P (tmode)
1375 ? mode_for_size (bitsize, GET_MODE_CLASS (tmode), 0)
1378 /* If the bitfield is volatile, we need to make sure the access
1379 remains on a type-aligned boundary. */
1380 if (GET_CODE (op0) == MEM
1381 && MEM_VOLATILE_P (op0)
1382 && GET_MODE_BITSIZE (GET_MODE (op0)) > 0
1383 && flag_strict_volatile_bitfields > 0)
1384 goto no_subreg_mode_swap;
1386 if (((bitsize >= BITS_PER_WORD && bitsize == GET_MODE_BITSIZE (mode)
1387 && bitpos % BITS_PER_WORD == 0)
1388 || (mode1 != BLKmode
1389 /* ??? The big endian test here is wrong. This is correct
1390 if the value is in a register, and if mode_for_size is not
1391 the same mode as op0. This causes us to get unnecessarily
1392 inefficient code from the Thumb port when -mbig-endian. */
1393 && (BYTES_BIG_ENDIAN
1394 ? bitpos + bitsize == BITS_PER_WORD
1397 && TRULY_NOOP_TRUNCATION_MODES_P (mode1, GET_MODE (op0))
1398 && GET_MODE_SIZE (mode1) != 0
1399 && byte_offset % GET_MODE_SIZE (mode1) == 0)
1401 && (! SLOW_UNALIGNED_ACCESS (mode, MEM_ALIGN (op0))
1402 || (offset * BITS_PER_UNIT % bitsize == 0
1403 && MEM_ALIGN (op0) % bitsize == 0)))))
1406 op0 = adjust_address (op0, mode1, offset);
1407 else if (mode1 != GET_MODE (op0))
1409 rtx sub = simplify_gen_subreg (mode1, op0, GET_MODE (op0),
1412 goto no_subreg_mode_swap;
1416 return convert_to_mode (tmode, op0, unsignedp);
1419 no_subreg_mode_swap:
1421 /* Handle fields bigger than a word. */
1423 if (bitsize > BITS_PER_WORD)
1425 /* Here we transfer the words of the field
1426 in the order least significant first.
1427 This is because the most significant word is the one which may
1428 be less than full. */
1430 unsigned int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD;
1433 if (target == 0 || !REG_P (target) || !valid_multiword_target_p (target))
1434 target = gen_reg_rtx (mode);
1436 /* Indicate for flow that the entire target reg is being set. */
1437 emit_clobber (target);
1439 for (i = 0; i < nwords; i++)
1441 /* If I is 0, use the low-order word in both field and target;
1442 if I is 1, use the next to lowest word; and so on. */
1443 /* Word number in TARGET to use. */
1444 unsigned int wordnum
1446 ? GET_MODE_SIZE (GET_MODE (target)) / UNITS_PER_WORD - i - 1
1448 /* Offset from start of field in OP0. */
1449 unsigned int bit_offset = (WORDS_BIG_ENDIAN
1450 ? MAX (0, ((int) bitsize - ((int) i + 1)
1451 * (int) BITS_PER_WORD))
1452 : (int) i * BITS_PER_WORD);
1453 rtx target_part = operand_subword (target, wordnum, 1, VOIDmode);
1455 = extract_bit_field (op0, MIN (BITS_PER_WORD,
1456 bitsize - i * BITS_PER_WORD),
1457 bitnum + bit_offset, 1, false, target_part, mode,
1460 gcc_assert (target_part);
1462 if (result_part != target_part)
1463 emit_move_insn (target_part, result_part);
1468 /* Unless we've filled TARGET, the upper regs in a multi-reg value
1469 need to be zero'd out. */
1470 if (GET_MODE_SIZE (GET_MODE (target)) > nwords * UNITS_PER_WORD)
1472 unsigned int i, total_words;
1474 total_words = GET_MODE_SIZE (GET_MODE (target)) / UNITS_PER_WORD;
1475 for (i = nwords; i < total_words; i++)
1477 (operand_subword (target,
1478 WORDS_BIG_ENDIAN ? total_words - i - 1 : i,
1485 /* Signed bit field: sign-extend with two arithmetic shifts. */
1486 target = expand_shift (LSHIFT_EXPR, mode, target,
1487 GET_MODE_BITSIZE (mode) - bitsize, NULL_RTX, 0);
1488 return expand_shift (RSHIFT_EXPR, mode, target,
1489 GET_MODE_BITSIZE (mode) - bitsize, NULL_RTX, 0);
1492 /* From here on we know the desired field is smaller than a word. */
1494 /* Check if there is a correspondingly-sized integer field, so we can
1495 safely extract it as one size of integer, if necessary; then
1496 truncate or extend to the size that is wanted; then use SUBREGs or
1497 convert_to_mode to get one of the modes we really wanted. */
1499 int_mode = int_mode_for_mode (tmode);
1500 if (int_mode == BLKmode)
1501 int_mode = int_mode_for_mode (mode);
1502 /* Should probably push op0 out to memory and then do a load. */
1503 gcc_assert (int_mode != BLKmode);
1505 /* OFFSET is the number of words or bytes (UNIT says which)
1506 from STR_RTX to the first word or byte containing part of the field. */
1510 || GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD)
1513 op0 = copy_to_reg (op0);
1514 op0 = gen_rtx_SUBREG (mode_for_size (BITS_PER_WORD, MODE_INT, 0),
1515 op0, (offset * UNITS_PER_WORD));
1520 /* Now OFFSET is nonzero only for memory operands. */
1521 ext_mode = mode_for_extraction (unsignedp ? EP_extzv : EP_extv, 0);
1522 if (ext_mode != MAX_MACHINE_MODE
1524 && GET_MODE_BITSIZE (ext_mode) >= bitsize
1525 /* Do not use extv/extzv for volatile bitfields when
1526 -fstrict-volatile-bitfields is in effect. */
1527 && !(MEM_P (op0) && MEM_VOLATILE_P (op0)
1528 && flag_strict_volatile_bitfields > 0)
1529 /* If op0 is a register, we need it in EXT_MODE to make it
1530 acceptable to the format of ext(z)v. */
1531 && !(GET_CODE (op0) == SUBREG && GET_MODE (op0) != ext_mode)
1532 && !((REG_P (op0) || GET_CODE (op0) == SUBREG)
1533 && (bitsize + bitpos > GET_MODE_BITSIZE (ext_mode))))
1535 struct expand_operand ops[4];
1536 unsigned HOST_WIDE_INT xbitpos = bitpos, xoffset = offset;
1538 rtx xtarget = target;
1539 rtx xspec_target = target;
1540 rtx xspec_target_subreg = 0;
1542 /* If op0 is a register, we need it in EXT_MODE to make it
1543 acceptable to the format of ext(z)v. */
1544 if (REG_P (xop0) && GET_MODE (xop0) != ext_mode)
1545 xop0 = gen_lowpart_SUBREG (ext_mode, xop0);
1547 /* Get ref to first byte containing part of the field. */
1548 xop0 = adjust_address (xop0, byte_mode, xoffset);
1550 /* Now convert from counting within UNIT to counting in EXT_MODE. */
1551 if (BYTES_BIG_ENDIAN && !MEM_P (xop0))
1552 xbitpos += GET_MODE_BITSIZE (ext_mode) - unit;
1554 unit = GET_MODE_BITSIZE (ext_mode);
1556 /* If BITS_BIG_ENDIAN is zero on a BYTES_BIG_ENDIAN machine, we count
1557 "backwards" from the size of the unit we are extracting from.
1558 Otherwise, we count bits from the most significant on a
1559 BYTES/BITS_BIG_ENDIAN machine. */
1561 if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
1562 xbitpos = unit - bitsize - xbitpos;
1565 xtarget = xspec_target = gen_reg_rtx (tmode);
1567 if (GET_MODE (xtarget) != ext_mode)
1569 /* Don't use LHS paradoxical subreg if explicit truncation is needed
1570 between the mode of the extraction (word_mode) and the target
1571 mode. Instead, create a temporary and use convert_move to set
1574 && TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (xtarget), ext_mode))
1576 xtarget = gen_lowpart (ext_mode, xtarget);
1577 if (GET_MODE_PRECISION (ext_mode)
1578 > GET_MODE_PRECISION (GET_MODE (xspec_target)))
1579 xspec_target_subreg = xtarget;
1582 xtarget = gen_reg_rtx (ext_mode);
1585 create_output_operand (&ops[0], xtarget, ext_mode);
1586 create_fixed_operand (&ops[1], xop0);
1587 create_integer_operand (&ops[2], bitsize);
1588 create_integer_operand (&ops[3], xbitpos);
1589 if (maybe_expand_insn (unsignedp ? CODE_FOR_extzv : CODE_FOR_extv,
1592 xtarget = ops[0].value;
1593 if (xtarget == xspec_target)
1595 if (xtarget == xspec_target_subreg)
1596 return xspec_target;
1597 return convert_extracted_bit_field (xtarget, mode, tmode, unsignedp);
1601 /* If OP0 is a memory, try copying it to a register and seeing if a
1602 cheap register alternative is available. */
1603 if (ext_mode != MAX_MACHINE_MODE && MEM_P (op0))
1605 enum machine_mode bestmode;
1607 /* Get the mode to use for inserting into this field. If
1608 OP0 is BLKmode, get the smallest mode consistent with the
1609 alignment. If OP0 is a non-BLKmode object that is no
1610 wider than EXT_MODE, use its mode. Otherwise, use the
1611 smallest mode containing the field. */
1613 if (GET_MODE (op0) == BLKmode
1614 || (ext_mode != MAX_MACHINE_MODE
1615 && GET_MODE_SIZE (GET_MODE (op0)) > GET_MODE_SIZE (ext_mode)))
1616 bestmode = get_best_mode (bitsize, bitnum, 0, 0, MEM_ALIGN (op0),
1617 (ext_mode == MAX_MACHINE_MODE
1618 ? VOIDmode : ext_mode),
1619 MEM_VOLATILE_P (op0));
1621 bestmode = GET_MODE (op0);
1623 if (bestmode != VOIDmode
1624 && !(SLOW_UNALIGNED_ACCESS (bestmode, MEM_ALIGN (op0))
1625 && GET_MODE_BITSIZE (bestmode) > MEM_ALIGN (op0)))
1627 unsigned HOST_WIDE_INT xoffset, xbitpos;
1629 /* Compute the offset as a multiple of this unit,
1630 counting in bytes. */
1631 unit = GET_MODE_BITSIZE (bestmode);
1632 xoffset = (bitnum / unit) * GET_MODE_SIZE (bestmode);
1633 xbitpos = bitnum % unit;
1635 /* Make sure the register is big enough for the whole field. */
1636 if (xoffset * BITS_PER_UNIT + unit
1637 >= offset * BITS_PER_UNIT + bitsize)
1639 rtx last, result, xop0;
1641 last = get_last_insn ();
1643 /* Fetch it to a register in that size. */
1644 xop0 = adjust_address (op0, bestmode, xoffset);
1645 xop0 = force_reg (bestmode, xop0);
1646 result = extract_bit_field_1 (xop0, bitsize, xbitpos,
1647 unsignedp, packedp, target,
1648 mode, tmode, false);
1652 delete_insns_since (last);
1660 target = extract_fixed_bit_field (int_mode, op0, offset, bitsize,
1661 bitpos, target, unsignedp, packedp);
1662 return convert_extracted_bit_field (target, mode, tmode, unsignedp);
1665 /* Generate code to extract a byte-field from STR_RTX
1666 containing BITSIZE bits, starting at BITNUM,
1667 and put it in TARGET if possible (if TARGET is nonzero).
1668 Regardless of TARGET, we return the rtx for where the value is placed.
1670 STR_RTX is the structure containing the byte (a REG or MEM).
1671 UNSIGNEDP is nonzero if this is an unsigned bit field.
1672 PACKEDP is nonzero if the field has the packed attribute.
1673 MODE is the natural mode of the field value once extracted.
1674 TMODE is the mode the caller would like the value to have;
1675 but the value may be returned with type MODE instead.
1677 If a TARGET is specified and we can store in it at no extra cost,
1678 we do so, and return TARGET.
1679 Otherwise, we return a REG of mode TMODE or MODE, with TMODE preferred
1680 if they are equally easy. */
1683 extract_bit_field (rtx str_rtx, unsigned HOST_WIDE_INT bitsize,
1684 unsigned HOST_WIDE_INT bitnum, int unsignedp, bool packedp,
1685 rtx target, enum machine_mode mode, enum machine_mode tmode)
1687 return extract_bit_field_1 (str_rtx, bitsize, bitnum, unsignedp, packedp,
1688 target, mode, tmode, true);
1691 /* Extract a bit field using shifts and boolean operations
1692 Returns an rtx to represent the value.
1693 OP0 addresses a register (word) or memory (byte).
1694 BITPOS says which bit within the word or byte the bit field starts in.
1695 OFFSET says how many bytes farther the bit field starts;
1696 it is 0 if OP0 is a register.
1697 BITSIZE says how many bits long the bit field is.
1698 (If OP0 is a register, it may be narrower than a full word,
1699 but BITPOS still counts within a full word,
1700 which is significant on bigendian machines.)
1702 UNSIGNEDP is nonzero for an unsigned bit field (don't sign-extend value).
1703 PACKEDP is true if the field has the packed attribute.
1705 If TARGET is nonzero, attempts to store the value there
1706 and return TARGET, but this is not guaranteed.
1707 If TARGET is not used, create a pseudo-reg of mode TMODE for the value. */
1710 extract_fixed_bit_field (enum machine_mode tmode, rtx op0,
1711 unsigned HOST_WIDE_INT offset,
1712 unsigned HOST_WIDE_INT bitsize,
1713 unsigned HOST_WIDE_INT bitpos, rtx target,
1714 int unsignedp, bool packedp)
1716 unsigned int total_bits = BITS_PER_WORD;
1717 enum machine_mode mode;
1719 if (GET_CODE (op0) == SUBREG || REG_P (op0))
1721 /* Special treatment for a bit field split across two registers. */
1722 if (bitsize + bitpos > BITS_PER_WORD)
1723 return extract_split_bit_field (op0, bitsize, bitpos, unsignedp);
1727 /* Get the proper mode to use for this field. We want a mode that
1728 includes the entire field. If such a mode would be larger than
1729 a word, we won't be doing the extraction the normal way. */
1731 if (MEM_VOLATILE_P (op0)
1732 && flag_strict_volatile_bitfields > 0)
1734 if (GET_MODE_BITSIZE (GET_MODE (op0)) > 0)
1735 mode = GET_MODE (op0);
1736 else if (target && GET_MODE_BITSIZE (GET_MODE (target)) > 0)
1737 mode = GET_MODE (target);
1742 mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT, 0, 0,
1743 MEM_ALIGN (op0), word_mode, MEM_VOLATILE_P (op0));
1745 if (mode == VOIDmode)
1746 /* The only way this should occur is if the field spans word
1748 return extract_split_bit_field (op0, bitsize,
1749 bitpos + offset * BITS_PER_UNIT,
1752 total_bits = GET_MODE_BITSIZE (mode);
1754 /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to
1755 be in the range 0 to total_bits-1, and put any excess bytes in
1757 if (bitpos >= total_bits)
1759 offset += (bitpos / total_bits) * (total_bits / BITS_PER_UNIT);
1760 bitpos -= ((bitpos / total_bits) * (total_bits / BITS_PER_UNIT)
1764 /* If we're accessing a volatile MEM, we can't do the next
1765 alignment step if it results in a multi-word access where we
1766 otherwise wouldn't have one. So, check for that case
1769 && MEM_VOLATILE_P (op0)
1770 && flag_strict_volatile_bitfields > 0
1771 && bitpos + bitsize <= total_bits
1772 && bitpos + bitsize + (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT > total_bits)
1774 if (STRICT_ALIGNMENT)
1776 static bool informed_about_misalignment = false;
1781 if (bitsize == total_bits)
1782 warned = warning_at (input_location, OPT_fstrict_volatile_bitfields,
1783 "multiple accesses to volatile structure member"
1784 " because of packed attribute");
1786 warned = warning_at (input_location, OPT_fstrict_volatile_bitfields,
1787 "multiple accesses to volatile structure bitfield"
1788 " because of packed attribute");
1790 return extract_split_bit_field (op0, bitsize,
1791 bitpos + offset * BITS_PER_UNIT,
1795 if (bitsize == total_bits)
1796 warned = warning_at (input_location, OPT_fstrict_volatile_bitfields,
1797 "mis-aligned access used for structure member");
1799 warned = warning_at (input_location, OPT_fstrict_volatile_bitfields,
1800 "mis-aligned access used for structure bitfield");
1802 if (! informed_about_misalignment && warned)
1804 informed_about_misalignment = true;
1805 inform (input_location,
1806 "when a volatile object spans multiple type-sized locations,"
1807 " the compiler must choose between using a single mis-aligned access to"
1808 " preserve the volatility, or using multiple aligned accesses to avoid"
1809 " runtime faults; this code may fail at runtime if the hardware does"
1810 " not allow this access");
1817 /* Get ref to an aligned byte, halfword, or word containing the field.
1818 Adjust BITPOS to be position within a word,
1819 and OFFSET to be the offset of that word.
1820 Then alter OP0 to refer to that word. */
1821 bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT;
1822 offset -= (offset % (total_bits / BITS_PER_UNIT));
1825 op0 = adjust_address (op0, mode, offset);
1828 mode = GET_MODE (op0);
1830 if (BYTES_BIG_ENDIAN)
1831 /* BITPOS is the distance between our msb and that of OP0.
1832 Convert it to the distance from the lsb. */
1833 bitpos = total_bits - bitsize - bitpos;
1835 /* Now BITPOS is always the distance between the field's lsb and that of OP0.
1836 We have reduced the big-endian case to the little-endian case. */
1842 /* If the field does not already start at the lsb,
1843 shift it so it does. */
1844 /* Maybe propagate the target for the shift. */
1845 /* But not if we will return it--could confuse integrate.c. */
1846 rtx subtarget = (target != 0 && REG_P (target) ? target : 0);
1847 if (tmode != mode) subtarget = 0;
1848 op0 = expand_shift (RSHIFT_EXPR, mode, op0, bitpos, subtarget, 1);
1850 /* Convert the value to the desired mode. */
1852 op0 = convert_to_mode (tmode, op0, 1);
1854 /* Unless the msb of the field used to be the msb when we shifted,
1855 mask out the upper bits. */
1857 if (GET_MODE_BITSIZE (mode) != bitpos + bitsize)
1858 return expand_binop (GET_MODE (op0), and_optab, op0,
1859 mask_rtx (GET_MODE (op0), 0, bitsize, 0),
1860 target, 1, OPTAB_LIB_WIDEN);
1864 /* To extract a signed bit-field, first shift its msb to the msb of the word,
1865 then arithmetic-shift its lsb to the lsb of the word. */
1866 op0 = force_reg (mode, op0);
1868 /* Find the narrowest integer mode that contains the field. */
1870 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode;
1871 mode = GET_MODE_WIDER_MODE (mode))
1872 if (GET_MODE_BITSIZE (mode) >= bitsize + bitpos)
1874 op0 = convert_to_mode (mode, op0, 0);
1881 if (GET_MODE_BITSIZE (mode) != (bitsize + bitpos))
1883 int amount = GET_MODE_BITSIZE (mode) - (bitsize + bitpos);
1884 /* Maybe propagate the target for the shift. */
1885 rtx subtarget = (target != 0 && REG_P (target) ? target : 0);
1886 op0 = expand_shift (LSHIFT_EXPR, mode, op0, amount, subtarget, 1);
1889 return expand_shift (RSHIFT_EXPR, mode, op0,
1890 GET_MODE_BITSIZE (mode) - bitsize, target, 0);
1893 /* Return a constant integer (CONST_INT or CONST_DOUBLE) mask value
1894 of mode MODE with BITSIZE ones followed by BITPOS zeros, or the
1895 complement of that if COMPLEMENT. The mask is truncated if
1896 necessary to the width of mode MODE. The mask is zero-extended if
1897 BITSIZE+BITPOS is too small for MODE. */
1900 mask_rtx (enum machine_mode mode, int bitpos, int bitsize, int complement)
1904 mask = double_int_mask (bitsize);
1905 mask = double_int_lshift (mask, bitpos, HOST_BITS_PER_DOUBLE_INT, false);
1908 mask = double_int_not (mask);
1910 return immed_double_int_const (mask, mode);
1913 /* Return a constant integer (CONST_INT or CONST_DOUBLE) rtx with the value
1914 VALUE truncated to BITSIZE bits and then shifted left BITPOS bits. */
1917 lshift_value (enum machine_mode mode, rtx value, int bitpos, int bitsize)
1921 val = double_int_zext (uhwi_to_double_int (INTVAL (value)), bitsize);
1922 val = double_int_lshift (val, bitpos, HOST_BITS_PER_DOUBLE_INT, false);
1924 return immed_double_int_const (val, mode);
1927 /* Extract a bit field that is split across two words
1928 and return an RTX for the result.
1930 OP0 is the REG, SUBREG or MEM rtx for the first of the two words.
1931 BITSIZE is the field width; BITPOS, position of its first bit, in the word.
1932 UNSIGNEDP is 1 if should zero-extend the contents; else sign-extend. */
1935 extract_split_bit_field (rtx op0, unsigned HOST_WIDE_INT bitsize,
1936 unsigned HOST_WIDE_INT bitpos, int unsignedp)
1939 unsigned int bitsdone = 0;
1940 rtx result = NULL_RTX;
1943 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
1945 if (REG_P (op0) || GET_CODE (op0) == SUBREG)
1946 unit = BITS_PER_WORD;
1948 unit = MIN (MEM_ALIGN (op0), BITS_PER_WORD);
1950 while (bitsdone < bitsize)
1952 unsigned HOST_WIDE_INT thissize;
1954 unsigned HOST_WIDE_INT thispos;
1955 unsigned HOST_WIDE_INT offset;
1957 offset = (bitpos + bitsdone) / unit;
1958 thispos = (bitpos + bitsdone) % unit;
1960 /* THISSIZE must not overrun a word boundary. Otherwise,
1961 extract_fixed_bit_field will call us again, and we will mutually
1963 thissize = MIN (bitsize - bitsdone, BITS_PER_WORD);
1964 thissize = MIN (thissize, unit - thispos);
1966 /* If OP0 is a register, then handle OFFSET here.
1968 When handling multiword bitfields, extract_bit_field may pass
1969 down a word_mode SUBREG of a larger REG for a bitfield that actually
1970 crosses a word boundary. Thus, for a SUBREG, we must find
1971 the current word starting from the base register. */
1972 if (GET_CODE (op0) == SUBREG)
1974 int word_offset = (SUBREG_BYTE (op0) / UNITS_PER_WORD) + offset;
1975 word = operand_subword_force (SUBREG_REG (op0), word_offset,
1976 GET_MODE (SUBREG_REG (op0)));
1979 else if (REG_P (op0))
1981 word = operand_subword_force (op0, offset, GET_MODE (op0));
1987 /* Extract the parts in bit-counting order,
1988 whose meaning is determined by BYTES_PER_UNIT.
1989 OFFSET is in UNITs, and UNIT is in bits.
1990 extract_fixed_bit_field wants offset in bytes. */
1991 part = extract_fixed_bit_field (word_mode, word,
1992 offset * unit / BITS_PER_UNIT,
1993 thissize, thispos, 0, 1, false);
1994 bitsdone += thissize;
1996 /* Shift this part into place for the result. */
1997 if (BYTES_BIG_ENDIAN)
1999 if (bitsize != bitsdone)
2000 part = expand_shift (LSHIFT_EXPR, word_mode, part,
2001 bitsize - bitsdone, 0, 1);
2005 if (bitsdone != thissize)
2006 part = expand_shift (LSHIFT_EXPR, word_mode, part,
2007 bitsdone - thissize, 0, 1);
2013 /* Combine the parts with bitwise or. This works
2014 because we extracted each part as an unsigned bit field. */
2015 result = expand_binop (word_mode, ior_optab, part, result, NULL_RTX, 1,
2021 /* Unsigned bit field: we are done. */
2024 /* Signed bit field: sign-extend with two arithmetic shifts. */
2025 result = expand_shift (LSHIFT_EXPR, word_mode, result,
2026 BITS_PER_WORD - bitsize, NULL_RTX, 0);
2027 return expand_shift (RSHIFT_EXPR, word_mode, result,
2028 BITS_PER_WORD - bitsize, NULL_RTX, 0);
2031 /* Try to read the low bits of SRC as an rvalue of mode MODE, preserving
2032 the bit pattern. SRC_MODE is the mode of SRC; if this is smaller than
2033 MODE, fill the upper bits with zeros. Fail if the layout of either
2034 mode is unknown (as for CC modes) or if the extraction would involve
2035 unprofitable mode punning. Return the value on success, otherwise
2038 This is different from gen_lowpart* in these respects:
2040 - the returned value must always be considered an rvalue
2042 - when MODE is wider than SRC_MODE, the extraction involves
2045 - when MODE is smaller than SRC_MODE, the extraction involves
2046 a truncation (and is thus subject to TRULY_NOOP_TRUNCATION).
2048 In other words, this routine performs a computation, whereas the
2049 gen_lowpart* routines are conceptually lvalue or rvalue subreg
2053 extract_low_bits (enum machine_mode mode, enum machine_mode src_mode, rtx src)
2055 enum machine_mode int_mode, src_int_mode;
2057 if (mode == src_mode)
2060 if (CONSTANT_P (src))
2062 /* simplify_gen_subreg can't be used here, as if simplify_subreg
2063 fails, it will happily create (subreg (symbol_ref)) or similar
2065 unsigned int byte = subreg_lowpart_offset (mode, src_mode);
2066 rtx ret = simplify_subreg (mode, src, src_mode, byte);
2070 if (GET_MODE (src) == VOIDmode
2071 || !validate_subreg (mode, src_mode, src, byte))
2074 src = force_reg (GET_MODE (src), src);
2075 return gen_rtx_SUBREG (mode, src, byte);
2078 if (GET_MODE_CLASS (mode) == MODE_CC || GET_MODE_CLASS (src_mode) == MODE_CC)
2081 if (GET_MODE_BITSIZE (mode) == GET_MODE_BITSIZE (src_mode)
2082 && MODES_TIEABLE_P (mode, src_mode))
2084 rtx x = gen_lowpart_common (mode, src);
2089 src_int_mode = int_mode_for_mode (src_mode);
2090 int_mode = int_mode_for_mode (mode);
2091 if (src_int_mode == BLKmode || int_mode == BLKmode)
2094 if (!MODES_TIEABLE_P (src_int_mode, src_mode))
2096 if (!MODES_TIEABLE_P (int_mode, mode))
2099 src = gen_lowpart (src_int_mode, src);
2100 src = convert_modes (int_mode, src_int_mode, src, true);
2101 src = gen_lowpart (mode, src);
2105 /* Add INC into TARGET. */
2108 expand_inc (rtx target, rtx inc)
2110 rtx value = expand_binop (GET_MODE (target), add_optab,
2112 target, 0, OPTAB_LIB_WIDEN);
2113 if (value != target)
2114 emit_move_insn (target, value);
2117 /* Subtract DEC from TARGET. */
2120 expand_dec (rtx target, rtx dec)
2122 rtx value = expand_binop (GET_MODE (target), sub_optab,
2124 target, 0, OPTAB_LIB_WIDEN);
2125 if (value != target)
2126 emit_move_insn (target, value);
2129 /* Output a shift instruction for expression code CODE,
2130 with SHIFTED being the rtx for the value to shift,
2131 and AMOUNT the rtx for the amount to shift by.
2132 Store the result in the rtx TARGET, if that is convenient.
2133 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
2134 Return the rtx for where the value is. */
2137 expand_shift_1 (enum tree_code code, enum machine_mode mode, rtx shifted,
2138 rtx amount, rtx target, int unsignedp)
2141 int left = (code == LSHIFT_EXPR || code == LROTATE_EXPR);
2142 int rotate = (code == LROTATE_EXPR || code == RROTATE_EXPR);
2143 optab lshift_optab = ashl_optab;
2144 optab rshift_arith_optab = ashr_optab;
2145 optab rshift_uns_optab = lshr_optab;
2146 optab lrotate_optab = rotl_optab;
2147 optab rrotate_optab = rotr_optab;
2148 enum machine_mode op1_mode;
2150 bool speed = optimize_insn_for_speed_p ();
2153 op1_mode = GET_MODE (op1);
2155 /* Determine whether the shift/rotate amount is a vector, or scalar. If the
2156 shift amount is a vector, use the vector/vector shift patterns. */
2157 if (VECTOR_MODE_P (mode) && VECTOR_MODE_P (op1_mode))
2159 lshift_optab = vashl_optab;
2160 rshift_arith_optab = vashr_optab;
2161 rshift_uns_optab = vlshr_optab;
2162 lrotate_optab = vrotl_optab;
2163 rrotate_optab = vrotr_optab;
2166 /* Previously detected shift-counts computed by NEGATE_EXPR
2167 and shifted in the other direction; but that does not work
2170 if (SHIFT_COUNT_TRUNCATED)
2172 if (CONST_INT_P (op1)
2173 && ((unsigned HOST_WIDE_INT) INTVAL (op1) >=
2174 (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode)))
2175 op1 = GEN_INT ((unsigned HOST_WIDE_INT) INTVAL (op1)
2176 % GET_MODE_BITSIZE (mode));
2177 else if (GET_CODE (op1) == SUBREG
2178 && subreg_lowpart_p (op1)
2179 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (op1))))
2180 op1 = SUBREG_REG (op1);
2183 if (op1 == const0_rtx)
2186 /* Check whether its cheaper to implement a left shift by a constant
2187 bit count by a sequence of additions. */
2188 if (code == LSHIFT_EXPR
2189 && CONST_INT_P (op1)
2191 && INTVAL (op1) < GET_MODE_PRECISION (mode)
2192 && INTVAL (op1) < MAX_BITS_PER_WORD
2193 && shift_cost[speed][mode][INTVAL (op1)] > INTVAL (op1) * add_cost[speed][mode]
2194 && shift_cost[speed][mode][INTVAL (op1)] != MAX_COST)
2197 for (i = 0; i < INTVAL (op1); i++)
2199 temp = force_reg (mode, shifted);
2200 shifted = expand_binop (mode, add_optab, temp, temp, NULL_RTX,
2201 unsignedp, OPTAB_LIB_WIDEN);
2206 for (attempt = 0; temp == 0 && attempt < 3; attempt++)
2208 enum optab_methods methods;
2211 methods = OPTAB_DIRECT;
2212 else if (attempt == 1)
2213 methods = OPTAB_WIDEN;
2215 methods = OPTAB_LIB_WIDEN;
2219 /* Widening does not work for rotation. */
2220 if (methods == OPTAB_WIDEN)
2222 else if (methods == OPTAB_LIB_WIDEN)
2224 /* If we have been unable to open-code this by a rotation,
2225 do it as the IOR of two shifts. I.e., to rotate A
2226 by N bits, compute (A << N) | ((unsigned) A >> (C - N))
2227 where C is the bitsize of A.
2229 It is theoretically possible that the target machine might
2230 not be able to perform either shift and hence we would
2231 be making two libcalls rather than just the one for the
2232 shift (similarly if IOR could not be done). We will allow
2233 this extremely unlikely lossage to avoid complicating the
2236 rtx subtarget = target == shifted ? 0 : target;
2237 rtx new_amount, other_amount;
2241 if (CONST_INT_P (op1))
2242 other_amount = GEN_INT (GET_MODE_BITSIZE (mode)
2246 = simplify_gen_binary (MINUS, GET_MODE (op1),
2247 GEN_INT (GET_MODE_PRECISION (mode)),
2250 shifted = force_reg (mode, shifted);
2252 temp = expand_shift_1 (left ? LSHIFT_EXPR : RSHIFT_EXPR,
2253 mode, shifted, new_amount, 0, 1);
2254 temp1 = expand_shift_1 (left ? RSHIFT_EXPR : LSHIFT_EXPR,
2255 mode, shifted, other_amount,
2257 return expand_binop (mode, ior_optab, temp, temp1, target,
2258 unsignedp, methods);
2261 temp = expand_binop (mode,
2262 left ? lrotate_optab : rrotate_optab,
2263 shifted, op1, target, unsignedp, methods);
2266 temp = expand_binop (mode,
2267 left ? lshift_optab : rshift_uns_optab,
2268 shifted, op1, target, unsignedp, methods);
2270 /* Do arithmetic shifts.
2271 Also, if we are going to widen the operand, we can just as well
2272 use an arithmetic right-shift instead of a logical one. */
2273 if (temp == 0 && ! rotate
2274 && (! unsignedp || (! left && methods == OPTAB_WIDEN)))
2276 enum optab_methods methods1 = methods;
2278 /* If trying to widen a log shift to an arithmetic shift,
2279 don't accept an arithmetic shift of the same size. */
2281 methods1 = OPTAB_MUST_WIDEN;
2283 /* Arithmetic shift */
2285 temp = expand_binop (mode,
2286 left ? lshift_optab : rshift_arith_optab,
2287 shifted, op1, target, unsignedp, methods1);
2290 /* We used to try extzv here for logical right shifts, but that was
2291 only useful for one machine, the VAX, and caused poor code
2292 generation there for lshrdi3, so the code was deleted and a
2293 define_expand for lshrsi3 was added to vax.md. */
2300 /* Output a shift instruction for expression code CODE,
2301 with SHIFTED being the rtx for the value to shift,
2302 and AMOUNT the amount to shift by.
2303 Store the result in the rtx TARGET, if that is convenient.
2304 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
2305 Return the rtx for where the value is. */
2308 expand_shift (enum tree_code code, enum machine_mode mode, rtx shifted,
2309 int amount, rtx target, int unsignedp)
2311 return expand_shift_1 (code, mode,
2312 shifted, GEN_INT (amount), target, unsignedp);
2315 /* Output a shift instruction for expression code CODE,
2316 with SHIFTED being the rtx for the value to shift,
2317 and AMOUNT the tree for the amount to shift by.
2318 Store the result in the rtx TARGET, if that is convenient.
2319 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
2320 Return the rtx for where the value is. */
2323 expand_variable_shift (enum tree_code code, enum machine_mode mode, rtx shifted,
2324 tree amount, rtx target, int unsignedp)
2326 return expand_shift_1 (code, mode,
2327 shifted, expand_normal (amount), target, unsignedp);
2331 /* Indicates the type of fixup needed after a constant multiplication.
2332 BASIC_VARIANT means no fixup is needed, NEGATE_VARIANT means that
2333 the result should be negated, and ADD_VARIANT means that the
2334 multiplicand should be added to the result. */
2335 enum mult_variant {basic_variant, negate_variant, add_variant};
2337 static void synth_mult (struct algorithm *, unsigned HOST_WIDE_INT,
2338 const struct mult_cost *, enum machine_mode mode);
2339 static bool choose_mult_variant (enum machine_mode, HOST_WIDE_INT,
2340 struct algorithm *, enum mult_variant *, int);
2341 static rtx expand_mult_const (enum machine_mode, rtx, HOST_WIDE_INT, rtx,
2342 const struct algorithm *, enum mult_variant);
2343 static unsigned HOST_WIDE_INT choose_multiplier (unsigned HOST_WIDE_INT, int,
2344 int, rtx *, int *, int *);
2345 static unsigned HOST_WIDE_INT invert_mod2n (unsigned HOST_WIDE_INT, int);
2346 static rtx extract_high_half (enum machine_mode, rtx);
2347 static rtx expand_mult_highpart (enum machine_mode, rtx, rtx, rtx, int, int);
2348 static rtx expand_mult_highpart_optab (enum machine_mode, rtx, rtx, rtx,
2350 /* Compute and return the best algorithm for multiplying by T.
2351 The algorithm must cost less than cost_limit
2352 If retval.cost >= COST_LIMIT, no algorithm was found and all
2353 other field of the returned struct are undefined.
2354 MODE is the machine mode of the multiplication. */
2357 synth_mult (struct algorithm *alg_out, unsigned HOST_WIDE_INT t,
2358 const struct mult_cost *cost_limit, enum machine_mode mode)
2361 struct algorithm *alg_in, *best_alg;
2362 struct mult_cost best_cost;
2363 struct mult_cost new_limit;
2364 int op_cost, op_latency;
2365 unsigned HOST_WIDE_INT orig_t = t;
2366 unsigned HOST_WIDE_INT q;
2367 int maxm = MIN (BITS_PER_WORD, GET_MODE_BITSIZE (mode));
2369 bool cache_hit = false;
2370 enum alg_code cache_alg = alg_zero;
2371 bool speed = optimize_insn_for_speed_p ();
2373 /* Indicate that no algorithm is yet found. If no algorithm
2374 is found, this value will be returned and indicate failure. */
2375 alg_out->cost.cost = cost_limit->cost + 1;
2376 alg_out->cost.latency = cost_limit->latency + 1;
2378 if (cost_limit->cost < 0
2379 || (cost_limit->cost == 0 && cost_limit->latency <= 0))
2382 /* Restrict the bits of "t" to the multiplication's mode. */
2383 t &= GET_MODE_MASK (mode);
2385 /* t == 1 can be done in zero cost. */
2389 alg_out->cost.cost = 0;
2390 alg_out->cost.latency = 0;
2391 alg_out->op[0] = alg_m;
2395 /* t == 0 sometimes has a cost. If it does and it exceeds our limit,
2399 if (MULT_COST_LESS (cost_limit, zero_cost[speed]))
2404 alg_out->cost.cost = zero_cost[speed];
2405 alg_out->cost.latency = zero_cost[speed];
2406 alg_out->op[0] = alg_zero;
2411 /* We'll be needing a couple extra algorithm structures now. */
2413 alg_in = XALLOCA (struct algorithm);
2414 best_alg = XALLOCA (struct algorithm);
2415 best_cost = *cost_limit;
2417 /* Compute the hash index. */
2418 hash_index = (t ^ (unsigned int) mode ^ (speed * 256)) % NUM_ALG_HASH_ENTRIES;
2420 /* See if we already know what to do for T. */
2421 if (alg_hash[hash_index].t == t
2422 && alg_hash[hash_index].mode == mode
2423 && alg_hash[hash_index].mode == mode
2424 && alg_hash[hash_index].speed == speed
2425 && alg_hash[hash_index].alg != alg_unknown)
2427 cache_alg = alg_hash[hash_index].alg;
2429 if (cache_alg == alg_impossible)
2431 /* The cache tells us that it's impossible to synthesize
2432 multiplication by T within alg_hash[hash_index].cost. */
2433 if (!CHEAPER_MULT_COST (&alg_hash[hash_index].cost, cost_limit))
2434 /* COST_LIMIT is at least as restrictive as the one
2435 recorded in the hash table, in which case we have no
2436 hope of synthesizing a multiplication. Just
2440 /* If we get here, COST_LIMIT is less restrictive than the
2441 one recorded in the hash table, so we may be able to
2442 synthesize a multiplication. Proceed as if we didn't
2443 have the cache entry. */
2447 if (CHEAPER_MULT_COST (cost_limit, &alg_hash[hash_index].cost))
2448 /* The cached algorithm shows that this multiplication
2449 requires more cost than COST_LIMIT. Just return. This
2450 way, we don't clobber this cache entry with
2451 alg_impossible but retain useful information. */
2463 goto do_alg_addsub_t_m2;
2465 case alg_add_factor:
2466 case alg_sub_factor:
2467 goto do_alg_addsub_factor;
2470 goto do_alg_add_t2_m;
2473 goto do_alg_sub_t2_m;
2481 /* If we have a group of zero bits at the low-order part of T, try
2482 multiplying by the remaining bits and then doing a shift. */
2487 m = floor_log2 (t & -t); /* m = number of low zero bits */
2491 /* The function expand_shift will choose between a shift and
2492 a sequence of additions, so the observed cost is given as
2493 MIN (m * add_cost[speed][mode], shift_cost[speed][mode][m]). */
2494 op_cost = m * add_cost[speed][mode];
2495 if (shift_cost[speed][mode][m] < op_cost)
2496 op_cost = shift_cost[speed][mode][m];
2497 new_limit.cost = best_cost.cost - op_cost;
2498 new_limit.latency = best_cost.latency - op_cost;
2499 synth_mult (alg_in, q, &new_limit, mode);
2501 alg_in->cost.cost += op_cost;
2502 alg_in->cost.latency += op_cost;
2503 if (CHEAPER_MULT_COST (&alg_in->cost, &best_cost))
2505 struct algorithm *x;
2506 best_cost = alg_in->cost;
2507 x = alg_in, alg_in = best_alg, best_alg = x;
2508 best_alg->log[best_alg->ops] = m;
2509 best_alg->op[best_alg->ops] = alg_shift;
2512 /* See if treating ORIG_T as a signed number yields a better
2513 sequence. Try this sequence only for a negative ORIG_T
2514 as it would be useless for a non-negative ORIG_T. */
2515 if ((HOST_WIDE_INT) orig_t < 0)
2517 /* Shift ORIG_T as follows because a right shift of a
2518 negative-valued signed type is implementation
2520 q = ~(~orig_t >> m);
2521 /* The function expand_shift will choose between a shift
2522 and a sequence of additions, so the observed cost is
2523 given as MIN (m * add_cost[speed][mode],
2524 shift_cost[speed][mode][m]). */
2525 op_cost = m * add_cost[speed][mode];
2526 if (shift_cost[speed][mode][m] < op_cost)
2527 op_cost = shift_cost[speed][mode][m];
2528 new_limit.cost = best_cost.cost - op_cost;
2529 new_limit.latency = best_cost.latency - op_cost;
2530 synth_mult (alg_in, q, &new_limit, mode);
2532 alg_in->cost.cost += op_cost;
2533 alg_in->cost.latency += op_cost;
2534 if (CHEAPER_MULT_COST (&alg_in->cost, &best_cost))
2536 struct algorithm *x;
2537 best_cost = alg_in->cost;
2538 x = alg_in, alg_in = best_alg, best_alg = x;
2539 best_alg->log[best_alg->ops] = m;
2540 best_alg->op[best_alg->ops] = alg_shift;
2548 /* If we have an odd number, add or subtract one. */
2551 unsigned HOST_WIDE_INT w;
2554 for (w = 1; (w & t) != 0; w <<= 1)
2556 /* If T was -1, then W will be zero after the loop. This is another
2557 case where T ends with ...111. Handling this with (T + 1) and
2558 subtract 1 produces slightly better code and results in algorithm
2559 selection much faster than treating it like the ...0111 case
2563 /* Reject the case where t is 3.
2564 Thus we prefer addition in that case. */
2567 /* T ends with ...111. Multiply by (T + 1) and subtract 1. */
2569 op_cost = add_cost[speed][mode];
2570 new_limit.cost = best_cost.cost - op_cost;
2571 new_limit.latency = best_cost.latency - op_cost;
2572 synth_mult (alg_in, t + 1, &new_limit, mode);
2574 alg_in->cost.cost += op_cost;
2575 alg_in->cost.latency += op_cost;
2576 if (CHEAPER_MULT_COST (&alg_in->cost, &best_cost))
2578 struct algorithm *x;
2579 best_cost = alg_in->cost;
2580 x = alg_in, alg_in = best_alg, best_alg = x;
2581 best_alg->log[best_alg->ops] = 0;
2582 best_alg->op[best_alg->ops] = alg_sub_t_m2;
2587 /* T ends with ...01 or ...011. Multiply by (T - 1) and add 1. */
2589 op_cost = add_cost[speed][mode];
2590 new_limit.cost = best_cost.cost - op_cost;
2591 new_limit.latency = best_cost.latency - op_cost;
2592 synth_mult (alg_in, t - 1, &new_limit, mode);
2594 alg_in->cost.cost += op_cost;
2595 alg_in->cost.latency += op_cost;
2596 if (CHEAPER_MULT_COST (&alg_in->cost, &best_cost))
2598 struct algorithm *x;
2599 best_cost = alg_in->cost;
2600 x = alg_in, alg_in = best_alg, best_alg = x;
2601 best_alg->log[best_alg->ops] = 0;
2602 best_alg->op[best_alg->ops] = alg_add_t_m2;
2606 /* We may be able to calculate a * -7, a * -15, a * -31, etc
2607 quickly with a - a * n for some appropriate constant n. */
2608 m = exact_log2 (-orig_t + 1);
2609 if (m >= 0 && m < maxm)
2611 op_cost = shiftsub1_cost[speed][mode][m];
2612 new_limit.cost = best_cost.cost - op_cost;
2613 new_limit.latency = best_cost.latency - op_cost;
2614 synth_mult (alg_in, (unsigned HOST_WIDE_INT) (-orig_t + 1) >> m, &new_limit, mode);
2616 alg_in->cost.cost += op_cost;
2617 alg_in->cost.latency += op_cost;
2618 if (CHEAPER_MULT_COST (&alg_in->cost, &best_cost))
2620 struct algorithm *x;
2621 best_cost = alg_in->cost;
2622 x = alg_in, alg_in = best_alg, best_alg = x;
2623 best_alg->log[best_alg->ops] = m;
2624 best_alg->op[best_alg->ops] = alg_sub_t_m2;
2632 /* Look for factors of t of the form
2633 t = q(2**m +- 1), 2 <= m <= floor(log2(t - 1)).
2634 If we find such a factor, we can multiply by t using an algorithm that
2635 multiplies by q, shift the result by m and add/subtract it to itself.
2637 We search for large factors first and loop down, even if large factors
2638 are less probable than small; if we find a large factor we will find a
2639 good sequence quickly, and therefore be able to prune (by decreasing
2640 COST_LIMIT) the search. */
2642 do_alg_addsub_factor:
2643 for (m = floor_log2 (t - 1); m >= 2; m--)
2645 unsigned HOST_WIDE_INT d;
2647 d = ((unsigned HOST_WIDE_INT) 1 << m) + 1;
2648 if (t % d == 0 && t > d && m < maxm
2649 && (!cache_hit || cache_alg == alg_add_factor))
2651 /* If the target has a cheap shift-and-add instruction use
2652 that in preference to a shift insn followed by an add insn.
2653 Assume that the shift-and-add is "atomic" with a latency
2654 equal to its cost, otherwise assume that on superscalar
2655 hardware the shift may be executed concurrently with the
2656 earlier steps in the algorithm. */
2657 op_cost = add_cost[speed][mode] + shift_cost[speed][mode][m];
2658 if (shiftadd_cost[speed][mode][m] < op_cost)
2660 op_cost = shiftadd_cost[speed][mode][m];
2661 op_latency = op_cost;
2664 op_latency = add_cost[speed][mode];
2666 new_limit.cost = best_cost.cost - op_cost;
2667 new_limit.latency = best_cost.latency - op_latency;
2668 synth_mult (alg_in, t / d, &new_limit, mode);
2670 alg_in->cost.cost += op_cost;
2671 alg_in->cost.latency += op_latency;
2672 if (alg_in->cost.latency < op_cost)
2673 alg_in->cost.latency = op_cost;
2674 if (CHEAPER_MULT_COST (&alg_in->cost, &best_cost))
2676 struct algorithm *x;
2677 best_cost = alg_in->cost;
2678 x = alg_in, alg_in = best_alg, best_alg = x;
2679 best_alg->log[best_alg->ops] = m;
2680 best_alg->op[best_alg->ops] = alg_add_factor;
2682 /* Other factors will have been taken care of in the recursion. */
2686 d = ((unsigned HOST_WIDE_INT) 1 << m) - 1;
2687 if (t % d == 0 && t > d && m < maxm
2688 && (!cache_hit || cache_alg == alg_sub_factor))
2690 /* If the target has a cheap shift-and-subtract insn use
2691 that in preference to a shift insn followed by a sub insn.
2692 Assume that the shift-and-sub is "atomic" with a latency
2693 equal to it's cost, otherwise assume that on superscalar
2694 hardware the shift may be executed concurrently with the
2695 earlier steps in the algorithm. */
2696 op_cost = add_cost[speed][mode] + shift_cost[speed][mode][m];
2697 if (shiftsub0_cost[speed][mode][m] < op_cost)
2699 op_cost = shiftsub0_cost[speed][mode][m];
2700 op_latency = op_cost;
2703 op_latency = add_cost[speed][mode];
2705 new_limit.cost = best_cost.cost - op_cost;
2706 new_limit.latency = best_cost.latency - op_latency;
2707 synth_mult (alg_in, t / d, &new_limit, mode);
2709 alg_in->cost.cost += op_cost;
2710 alg_in->cost.latency += op_latency;
2711 if (alg_in->cost.latency < op_cost)
2712 alg_in->cost.latency = op_cost;
2713 if (CHEAPER_MULT_COST (&alg_in->cost, &best_cost))
2715 struct algorithm *x;
2716 best_cost = alg_in->cost;
2717 x = alg_in, alg_in = best_alg, best_alg = x;
2718 best_alg->log[best_alg->ops] = m;
2719 best_alg->op[best_alg->ops] = alg_sub_factor;
2727 /* Try shift-and-add (load effective address) instructions,
2728 i.e. do a*3, a*5, a*9. */
2735 if (m >= 0 && m < maxm)
2737 op_cost = shiftadd_cost[speed][mode][m];
2738 new_limit.cost = best_cost.cost - op_cost;
2739 new_limit.latency = best_cost.latency - op_cost;
2740 synth_mult (alg_in, (t - 1) >> m, &new_limit, mode);
2742 alg_in->cost.cost += op_cost;
2743 alg_in->cost.latency += op_cost;
2744 if (CHEAPER_MULT_COST (&alg_in->cost, &best_cost))
2746 struct algorithm *x;
2747 best_cost = alg_in->cost;
2748 x = alg_in, alg_in = best_alg, best_alg = x;
2749 best_alg->log[best_alg->ops] = m;
2750 best_alg->op[best_alg->ops] = alg_add_t2_m;
2760 if (m >= 0 && m < maxm)
2762 op_cost = shiftsub0_cost[speed][mode][m];
2763 new_limit.cost = best_cost.cost - op_cost;
2764 new_limit.latency = best_cost.latency - op_cost;
2765 synth_mult (alg_in, (t + 1) >> m, &new_limit, mode);
2767 alg_in->cost.cost += op_cost;
2768 alg_in->cost.latency += op_cost;
2769 if (CHEAPER_MULT_COST (&alg_in->cost, &best_cost))
2771 struct algorithm *x;
2772 best_cost = alg_in->cost;
2773 x = alg_in, alg_in = best_alg, best_alg = x;
2774 best_alg->log[best_alg->ops] = m;
2775 best_alg->op[best_alg->ops] = alg_sub_t2_m;
2783 /* If best_cost has not decreased, we have not found any algorithm. */
2784 if (!CHEAPER_MULT_COST (&best_cost, cost_limit))
2786 /* We failed to find an algorithm. Record alg_impossible for
2787 this case (that is, <T, MODE, COST_LIMIT>) so that next time
2788 we are asked to find an algorithm for T within the same or
2789 lower COST_LIMIT, we can immediately return to the
2791 alg_hash[hash_index].t = t;
2792 alg_hash[hash_index].mode = mode;
2793 alg_hash[hash_index].speed = speed;
2794 alg_hash[hash_index].alg = alg_impossible;
2795 alg_hash[hash_index].cost = *cost_limit;
2799 /* Cache the result. */
2802 alg_hash[hash_index].t = t;
2803 alg_hash[hash_index].mode = mode;
2804 alg_hash[hash_index].speed = speed;
2805 alg_hash[hash_index].alg = best_alg->op[best_alg->ops];
2806 alg_hash[hash_index].cost.cost = best_cost.cost;
2807 alg_hash[hash_index].cost.latency = best_cost.latency;
2810 /* If we are getting a too long sequence for `struct algorithm'
2811 to record, make this search fail. */
2812 if (best_alg->ops == MAX_BITS_PER_WORD)
2815 /* Copy the algorithm from temporary space to the space at alg_out.
2816 We avoid using structure assignment because the majority of
2817 best_alg is normally undefined, and this is a critical function. */
2818 alg_out->ops = best_alg->ops + 1;
2819 alg_out->cost = best_cost;
2820 memcpy (alg_out->op, best_alg->op,
2821 alg_out->ops * sizeof *alg_out->op);
2822 memcpy (alg_out->log, best_alg->log,
2823 alg_out->ops * sizeof *alg_out->log);
2826 /* Find the cheapest way of multiplying a value of mode MODE by VAL.
2827 Try three variations:
2829 - a shift/add sequence based on VAL itself
2830 - a shift/add sequence based on -VAL, followed by a negation
2831 - a shift/add sequence based on VAL - 1, followed by an addition.
2833 Return true if the cheapest of these cost less than MULT_COST,
2834 describing the algorithm in *ALG and final fixup in *VARIANT. */
2837 choose_mult_variant (enum machine_mode mode, HOST_WIDE_INT val,
2838 struct algorithm *alg, enum mult_variant *variant,
2841 struct algorithm alg2;
2842 struct mult_cost limit;
2844 bool speed = optimize_insn_for_speed_p ();
2846 /* Fail quickly for impossible bounds. */
2850 /* Ensure that mult_cost provides a reasonable upper bound.
2851 Any constant multiplication can be performed with less
2852 than 2 * bits additions. */
2853 op_cost = 2 * GET_MODE_BITSIZE (mode) * add_cost[speed][mode];
2854 if (mult_cost > op_cost)
2855 mult_cost = op_cost;
2857 *variant = basic_variant;
2858 limit.cost = mult_cost;
2859 limit.latency = mult_cost;
2860 synth_mult (alg, val, &limit, mode);
2862 /* This works only if the inverted value actually fits in an
2864 if (HOST_BITS_PER_INT >= GET_MODE_BITSIZE (mode))
2866 op_cost = neg_cost[speed][mode];
2867 if (MULT_COST_LESS (&alg->cost, mult_cost))
2869 limit.cost = alg->cost.cost - op_cost;
2870 limit.latency = alg->cost.latency - op_cost;
2874 limit.cost = mult_cost - op_cost;
2875 limit.latency = mult_cost - op_cost;
2878 synth_mult (&alg2, -val, &limit, mode);
2879 alg2.cost.cost += op_cost;
2880 alg2.cost.latency += op_cost;
2881 if (CHEAPER_MULT_COST (&alg2.cost, &alg->cost))
2882 *alg = alg2, *variant = negate_variant;
2885 /* This proves very useful for division-by-constant. */
2886 op_cost = add_cost[speed][mode];
2887 if (MULT_COST_LESS (&alg->cost, mult_cost))
2889 limit.cost = alg->cost.cost - op_cost;
2890 limit.latency = alg->cost.latency - op_cost;
2894 limit.cost = mult_cost - op_cost;
2895 limit.latency = mult_cost - op_cost;
2898 synth_mult (&alg2, val - 1, &limit, mode);
2899 alg2.cost.cost += op_cost;
2900 alg2.cost.latency += op_cost;
2901 if (CHEAPER_MULT_COST (&alg2.cost, &alg->cost))
2902 *alg = alg2, *variant = add_variant;
2904 return MULT_COST_LESS (&alg->cost, mult_cost);
2907 /* A subroutine of expand_mult, used for constant multiplications.
2908 Multiply OP0 by VAL in mode MODE, storing the result in TARGET if
2909 convenient. Use the shift/add sequence described by ALG and apply
2910 the final fixup specified by VARIANT. */
2913 expand_mult_const (enum machine_mode mode, rtx op0, HOST_WIDE_INT val,
2914 rtx target, const struct algorithm *alg,
2915 enum mult_variant variant)
2917 HOST_WIDE_INT val_so_far;
2918 rtx insn, accum, tem;
2920 enum machine_mode nmode;
2922 /* Avoid referencing memory over and over and invalid sharing
2924 op0 = force_reg (mode, op0);
2926 /* ACCUM starts out either as OP0 or as a zero, depending on
2927 the first operation. */
2929 if (alg->op[0] == alg_zero)
2931 accum = copy_to_mode_reg (mode, const0_rtx);
2934 else if (alg->op[0] == alg_m)
2936 accum = copy_to_mode_reg (mode, op0);
2942 for (opno = 1; opno < alg->ops; opno++)
2944 int log = alg->log[opno];
2945 rtx shift_subtarget = optimize ? 0 : accum;
2947 = (opno == alg->ops - 1 && target != 0 && variant != add_variant
2950 rtx accum_target = optimize ? 0 : accum;
2952 switch (alg->op[opno])
2955 tem = expand_shift (LSHIFT_EXPR, mode, accum, log, NULL_RTX, 0);
2956 /* REG_EQUAL note will be attached to the following insn. */
2957 emit_move_insn (accum, tem);
2962 tem = expand_shift (LSHIFT_EXPR, mode, op0, log, NULL_RTX, 0);
2963 accum = force_operand (gen_rtx_PLUS (mode, accum, tem),
2964 add_target ? add_target : accum_target);
2965 val_so_far += (HOST_WIDE_INT) 1 << log;
2969 tem = expand_shift (LSHIFT_EXPR, mode, op0, log, NULL_RTX, 0);
2970 accum = force_operand (gen_rtx_MINUS (mode, accum, tem),
2971 add_target ? add_target : accum_target);
2972 val_so_far -= (HOST_WIDE_INT) 1 << log;
2976 accum = expand_shift (LSHIFT_EXPR, mode, accum,
2977 log, shift_subtarget, 0);
2978 accum = force_operand (gen_rtx_PLUS (mode, accum, op0),
2979 add_target ? add_target : accum_target);
2980 val_so_far = (val_so_far << log) + 1;
2984 accum = expand_shift (LSHIFT_EXPR, mode, accum,
2985 log, shift_subtarget, 0);
2986 accum = force_operand (gen_rtx_MINUS (mode, accum, op0),
2987 add_target ? add_target : accum_target);
2988 val_so_far = (val_so_far << log) - 1;
2991 case alg_add_factor:
2992 tem = expand_shift (LSHIFT_EXPR, mode, accum, log, NULL_RTX, 0);
2993 accum = force_operand (gen_rtx_PLUS (mode, accum, tem),
2994 add_target ? add_target : accum_target);
2995 val_so_far += val_so_far << log;
2998 case alg_sub_factor:
2999 tem = expand_shift (LSHIFT_EXPR, mode, accum, log, NULL_RTX, 0);
3000 accum = force_operand (gen_rtx_MINUS (mode, tem, accum),
3002 ? add_target : (optimize ? 0 : tem)));
3003 val_so_far = (val_so_far << log) - val_so_far;
3010 /* Write a REG_EQUAL note on the last insn so that we can cse
3011 multiplication sequences. Note that if ACCUM is a SUBREG,
3012 we've set the inner register and must properly indicate
3015 tem = op0, nmode = mode;
3016 if (GET_CODE (accum) == SUBREG)
3018 nmode = GET_MODE (SUBREG_REG (accum));
3019 tem = gen_lowpart (nmode, op0);
3022 insn = get_last_insn ();
3023 set_unique_reg_note (insn, REG_EQUAL,
3024 gen_rtx_MULT (nmode, tem,
3025 GEN_INT (val_so_far)));
3028 if (variant == negate_variant)
3030 val_so_far = -val_so_far;
3031 accum = expand_unop (mode, neg_optab, accum, target, 0);
3033 else if (variant == add_variant)
3035 val_so_far = val_so_far + 1;
3036 accum = force_operand (gen_rtx_PLUS (mode, accum, op0), target);
3039 /* Compare only the bits of val and val_so_far that are significant
3040 in the result mode, to avoid sign-/zero-extension confusion. */
3041 val &= GET_MODE_MASK (mode);
3042 val_so_far &= GET_MODE_MASK (mode);
3043 gcc_assert (val == val_so_far);
3048 /* Perform a multiplication and return an rtx for the result.
3049 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
3050 TARGET is a suggestion for where to store the result (an rtx).
3052 We check specially for a constant integer as OP1.
3053 If you want this check for OP0 as well, then before calling
3054 you should swap the two operands if OP0 would be constant. */
3057 expand_mult (enum machine_mode mode, rtx op0, rtx op1, rtx target,
3060 enum mult_variant variant;
3061 struct algorithm algorithm;
3063 bool speed = optimize_insn_for_speed_p ();
3065 /* Handling const0_rtx here allows us to use zero as a rogue value for
3067 if (op1 == const0_rtx)
3069 if (op1 == const1_rtx)
3071 if (op1 == constm1_rtx)
3072 return expand_unop (mode,
3073 GET_MODE_CLASS (mode) == MODE_INT
3074 && !unsignedp && flag_trapv
3075 ? negv_optab : neg_optab,
3078 /* These are the operations that are potentially turned into a sequence
3079 of shifts and additions. */
3080 if (SCALAR_INT_MODE_P (mode)
3081 && (unsignedp || !flag_trapv))
3083 HOST_WIDE_INT coeff = 0;
3084 rtx fake_reg = gen_raw_REG (mode, LAST_VIRTUAL_REGISTER + 1);
3086 /* synth_mult does an `unsigned int' multiply. As long as the mode is
3087 less than or equal in size to `unsigned int' this doesn't matter.
3088 If the mode is larger than `unsigned int', then synth_mult works
3089 only if the constant value exactly fits in an `unsigned int' without
3090 any truncation. This means that multiplying by negative values does
3091 not work; results are off by 2^32 on a 32 bit machine. */
3093 if (CONST_INT_P (op1))
3095 /* Attempt to handle multiplication of DImode values by negative
3096 coefficients, by performing the multiplication by a positive
3097 multiplier and then inverting the result. */
3098 if (INTVAL (op1) < 0
3099 && GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
3101 /* Its safe to use -INTVAL (op1) even for INT_MIN, as the
3102 result is interpreted as an unsigned coefficient.
3103 Exclude cost of op0 from max_cost to match the cost
3104 calculation of the synth_mult. */
3105 max_cost = (set_src_cost (gen_rtx_MULT (mode, fake_reg, op1),
3107 - neg_cost[speed][mode]);
3109 && choose_mult_variant (mode, -INTVAL (op1), &algorithm,
3110 &variant, max_cost))
3112 rtx temp = expand_mult_const (mode, op0, -INTVAL (op1),
3113 NULL_RTX, &algorithm,
3115 return expand_unop (mode, neg_optab, temp, target, 0);
3118 else coeff = INTVAL (op1);
3120 else if (GET_CODE (op1) == CONST_DOUBLE)
3122 /* If we are multiplying in DImode, it may still be a win
3123 to try to work with shifts and adds. */
3124 if (CONST_DOUBLE_HIGH (op1) == 0
3125 && CONST_DOUBLE_LOW (op1) > 0)
3126 coeff = CONST_DOUBLE_LOW (op1);
3127 else if (CONST_DOUBLE_LOW (op1) == 0
3128 && EXACT_POWER_OF_2_OR_ZERO_P (CONST_DOUBLE_HIGH (op1)))
3130 int shift = floor_log2 (CONST_DOUBLE_HIGH (op1))
3131 + HOST_BITS_PER_WIDE_INT;
3132 return expand_shift (LSHIFT_EXPR, mode, op0,
3133 shift, target, unsignedp);
3137 /* We used to test optimize here, on the grounds that it's better to
3138 produce a smaller program when -O is not used. But this causes
3139 such a terrible slowdown sometimes that it seems better to always
3143 /* Special case powers of two. */
3144 if (EXACT_POWER_OF_2_OR_ZERO_P (coeff))
3145 return expand_shift (LSHIFT_EXPR, mode, op0,
3146 floor_log2 (coeff), target, unsignedp);
3148 /* Exclude cost of op0 from max_cost to match the cost
3149 calculation of the synth_mult. */
3150 max_cost = set_src_cost (gen_rtx_MULT (mode, fake_reg, op1), speed);
3151 if (choose_mult_variant (mode, coeff, &algorithm, &variant,
3153 return expand_mult_const (mode, op0, coeff, target,
3154 &algorithm, variant);
3158 if (GET_CODE (op0) == CONST_DOUBLE)
3165 /* Expand x*2.0 as x+x. */
3166 if (GET_CODE (op1) == CONST_DOUBLE
3167 && SCALAR_FLOAT_MODE_P (mode))
3170 REAL_VALUE_FROM_CONST_DOUBLE (d, op1);
3172 if (REAL_VALUES_EQUAL (d, dconst2))
3174 op0 = force_reg (GET_MODE (op0), op0);
3175 return expand_binop (mode, add_optab, op0, op0,
3176 target, unsignedp, OPTAB_LIB_WIDEN);
3180 /* This used to use umul_optab if unsigned, but for non-widening multiply
3181 there is no difference between signed and unsigned. */
3182 op0 = expand_binop (mode,
3184 && flag_trapv && (GET_MODE_CLASS(mode) == MODE_INT)
3185 ? smulv_optab : smul_optab,
3186 op0, op1, target, unsignedp, OPTAB_LIB_WIDEN);
3191 /* Perform a widening multiplication and return an rtx for the result.
3192 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
3193 TARGET is a suggestion for where to store the result (an rtx).
3194 THIS_OPTAB is the optab we should use, it must be either umul_widen_optab
3195 or smul_widen_optab.
3197 We check specially for a constant integer as OP1, comparing the
3198 cost of a widening multiply against the cost of a sequence of shifts
3202 expand_widening_mult (enum machine_mode mode, rtx op0, rtx op1, rtx target,
3203 int unsignedp, optab this_optab)
3205 bool speed = optimize_insn_for_speed_p ();
3208 if (CONST_INT_P (op1)
3209 && GET_MODE (op0) != VOIDmode
3210 && (cop1 = convert_modes (mode, GET_MODE (op0), op1,
3211 this_optab == umul_widen_optab))
3212 && CONST_INT_P (cop1)
3213 && (INTVAL (cop1) >= 0
3214 || HWI_COMPUTABLE_MODE_P (mode)))
3216 HOST_WIDE_INT coeff = INTVAL (cop1);
3218 enum mult_variant variant;
3219 struct algorithm algorithm;
3221 /* Special case powers of two. */
3222 if (EXACT_POWER_OF_2_OR_ZERO_P (coeff))
3224 op0 = convert_to_mode (mode, op0, this_optab == umul_widen_optab);
3225 return expand_shift (LSHIFT_EXPR, mode, op0,
3226 floor_log2 (coeff), target, unsignedp);
3229 /* Exclude cost of op0 from max_cost to match the cost
3230 calculation of the synth_mult. */
3231 max_cost = mul_widen_cost[speed][mode];
3232 if (choose_mult_variant (mode, coeff, &algorithm, &variant,
3235 op0 = convert_to_mode (mode, op0, this_optab == umul_widen_optab);
3236 return expand_mult_const (mode, op0, coeff, target,
3237 &algorithm, variant);
3240 return expand_binop (mode, this_optab, op0, op1, target,
3241 unsignedp, OPTAB_LIB_WIDEN);
3244 /* Return the smallest n such that 2**n >= X. */
3247 ceil_log2 (unsigned HOST_WIDE_INT x)
3249 return floor_log2 (x - 1) + 1;
3252 /* Choose a minimal N + 1 bit approximation to 1/D that can be used to
3253 replace division by D, and put the least significant N bits of the result
3254 in *MULTIPLIER_PTR and return the most significant bit.
3256 The width of operations is N (should be <= HOST_BITS_PER_WIDE_INT), the
3257 needed precision is in PRECISION (should be <= N).
3259 PRECISION should be as small as possible so this function can choose
3260 multiplier more freely.
3262 The rounded-up logarithm of D is placed in *lgup_ptr. A shift count that
3263 is to be used for a final right shift is placed in *POST_SHIFT_PTR.
3265 Using this function, x/D will be equal to (x * m) >> (*POST_SHIFT_PTR),
3266 where m is the full HOST_BITS_PER_WIDE_INT + 1 bit multiplier. */
3269 unsigned HOST_WIDE_INT
3270 choose_multiplier (unsigned HOST_WIDE_INT d, int n, int precision,
3271 rtx *multiplier_ptr, int *post_shift_ptr, int *lgup_ptr)
3273 HOST_WIDE_INT mhigh_hi, mlow_hi;
3274 unsigned HOST_WIDE_INT mhigh_lo, mlow_lo;
3275 int lgup, post_shift;
3277 unsigned HOST_WIDE_INT nl, dummy1;
3278 HOST_WIDE_INT nh, dummy2;
3280 /* lgup = ceil(log2(divisor)); */
3281 lgup = ceil_log2 (d);
3283 gcc_assert (lgup <= n);
3286 pow2 = n + lgup - precision;
3288 /* We could handle this with some effort, but this case is much
3289 better handled directly with a scc insn, so rely on caller using
3291 gcc_assert (pow != 2 * HOST_BITS_PER_WIDE_INT);
3293 /* mlow = 2^(N + lgup)/d */
3294 if (pow >= HOST_BITS_PER_WIDE_INT)
3296 nh = (HOST_WIDE_INT) 1 << (pow - HOST_BITS_PER_WIDE_INT);
3302 nl = (unsigned HOST_WIDE_INT) 1 << pow;
3304 div_and_round_double (TRUNC_DIV_EXPR, 1, nl, nh, d, (HOST_WIDE_INT) 0,
3305 &mlow_lo, &mlow_hi, &dummy1, &dummy2);
3307 /* mhigh = (2^(N + lgup) + 2^N + lgup - precision)/d */
3308 if (pow2 >= HOST_BITS_PER_WIDE_INT)
3309 nh |= (HOST_WIDE_INT) 1 << (pow2 - HOST_BITS_PER_WIDE_INT);
3311 nl |= (unsigned HOST_WIDE_INT) 1 << pow2;
3312 div_and_round_double (TRUNC_DIV_EXPR, 1, nl, nh, d, (HOST_WIDE_INT) 0,
3313 &mhigh_lo, &mhigh_hi, &dummy1, &dummy2);
3315 gcc_assert (!mhigh_hi || nh - d < d);
3316 gcc_assert (mhigh_hi <= 1 && mlow_hi <= 1);
3317 /* Assert that mlow < mhigh. */
3318 gcc_assert (mlow_hi < mhigh_hi
3319 || (mlow_hi == mhigh_hi && mlow_lo < mhigh_lo));
3321 /* If precision == N, then mlow, mhigh exceed 2^N
3322 (but they do not exceed 2^(N+1)). */
3324 /* Reduce to lowest terms. */
3325 for (post_shift = lgup; post_shift > 0; post_shift--)
3327 unsigned HOST_WIDE_INT ml_lo = (mlow_hi << (HOST_BITS_PER_WIDE_INT - 1)) | (mlow_lo >> 1);
3328 unsigned HOST_WIDE_INT mh_lo = (mhigh_hi << (HOST_BITS_PER_WIDE_INT - 1)) | (mhigh_lo >> 1);
3338 *post_shift_ptr = post_shift;
3340 if (n < HOST_BITS_PER_WIDE_INT)
3342 unsigned HOST_WIDE_INT mask = ((unsigned HOST_WIDE_INT) 1 << n) - 1;
3343 *multiplier_ptr = GEN_INT (mhigh_lo & mask);
3344 return mhigh_lo >= mask;
3348 *multiplier_ptr = GEN_INT (mhigh_lo);
3353 /* Compute the inverse of X mod 2**n, i.e., find Y such that X * Y is
3354 congruent to 1 (mod 2**N). */
3356 static unsigned HOST_WIDE_INT
3357 invert_mod2n (unsigned HOST_WIDE_INT x, int n)
3359 /* Solve x*y == 1 (mod 2^n), where x is odd. Return y. */
3361 /* The algorithm notes that the choice y = x satisfies
3362 x*y == 1 mod 2^3, since x is assumed odd.
3363 Each iteration doubles the number of bits of significance in y. */
3365 unsigned HOST_WIDE_INT mask;
3366 unsigned HOST_WIDE_INT y = x;
3369 mask = (n == HOST_BITS_PER_WIDE_INT
3370 ? ~(unsigned HOST_WIDE_INT) 0
3371 : ((unsigned HOST_WIDE_INT) 1 << n) - 1);
3375 y = y * (2 - x*y) & mask; /* Modulo 2^N */
3381 /* Emit code to adjust ADJ_OPERAND after multiplication of wrong signedness
3382 flavor of OP0 and OP1. ADJ_OPERAND is already the high half of the
3383 product OP0 x OP1. If UNSIGNEDP is nonzero, adjust the signed product
3384 to become unsigned, if UNSIGNEDP is zero, adjust the unsigned product to
3387 The result is put in TARGET if that is convenient.
3389 MODE is the mode of operation. */
3392 expand_mult_highpart_adjust (enum machine_mode mode, rtx adj_operand, rtx op0,
3393 rtx op1, rtx target, int unsignedp)
3396 enum rtx_code adj_code = unsignedp ? PLUS : MINUS;
3398 tem = expand_shift (RSHIFT_EXPR, mode, op0,
3399 GET_MODE_BITSIZE (mode) - 1, NULL_RTX, 0);
3400 tem = expand_and (mode, tem, op1, NULL_RTX);
3402 = force_operand (gen_rtx_fmt_ee (adj_code, mode, adj_operand, tem),
3405 tem = expand_shift (RSHIFT_EXPR, mode, op1,
3406 GET_MODE_BITSIZE (mode) - 1, NULL_RTX, 0);
3407 tem = expand_and (mode, tem, op0, NULL_RTX);
3408 target = force_operand (gen_rtx_fmt_ee (adj_code, mode, adj_operand, tem),
3414 /* Subroutine of expand_mult_highpart. Return the MODE high part of OP. */
3417 extract_high_half (enum machine_mode mode, rtx op)
3419 enum machine_mode wider_mode;
3421 if (mode == word_mode)
3422 return gen_highpart (mode, op);
3424 gcc_assert (!SCALAR_FLOAT_MODE_P (mode));
3426 wider_mode = GET_MODE_WIDER_MODE (mode);
3427 op = expand_shift (RSHIFT_EXPR, wider_mode, op,
3428 GET_MODE_BITSIZE (mode), 0, 1);
3429 return convert_modes (mode, wider_mode, op, 0);
3432 /* Like expand_mult_highpart, but only consider using a multiplication
3433 optab. OP1 is an rtx for the constant operand. */
3436 expand_mult_highpart_optab (enum machine_mode mode, rtx op0, rtx op1,
3437 rtx target, int unsignedp, int max_cost)
3439 rtx narrow_op1 = gen_int_mode (INTVAL (op1), mode);
3440 enum machine_mode wider_mode;
3444 bool speed = optimize_insn_for_speed_p ();
3446 gcc_assert (!SCALAR_FLOAT_MODE_P (mode));
3448 wider_mode = GET_MODE_WIDER_MODE (mode);
3449 size = GET_MODE_BITSIZE (mode);
3451 /* Firstly, try using a multiplication insn that only generates the needed
3452 high part of the product, and in the sign flavor of unsignedp. */
3453 if (mul_highpart_cost[speed][mode] < max_cost)
3455 moptab = unsignedp ? umul_highpart_optab : smul_highpart_optab;
3456 tem = expand_binop (mode, moptab, op0, narrow_op1, target,
3457 unsignedp, OPTAB_DIRECT);
3462 /* Secondly, same as above, but use sign flavor opposite of unsignedp.
3463 Need to adjust the result after the multiplication. */
3464 if (size - 1 < BITS_PER_WORD
3465 && (mul_highpart_cost[speed][mode] + 2 * shift_cost[speed][mode][size-1]
3466 + 4 * add_cost[speed][mode] < max_cost))
3468 moptab = unsignedp ? smul_highpart_optab : umul_highpart_optab;
3469 tem = expand_binop (mode, moptab, op0, narrow_op1, target,
3470 unsignedp, OPTAB_DIRECT);
3472 /* We used the wrong signedness. Adjust the result. */
3473 return expand_mult_highpart_adjust (mode, tem, op0, narrow_op1,
3477 /* Try widening multiplication. */
3478 moptab = unsignedp ? umul_widen_optab : smul_widen_optab;
3479 if (widening_optab_handler (moptab, wider_mode, mode) != CODE_FOR_nothing
3480 && mul_widen_cost[speed][wider_mode] < max_cost)
3482 tem = expand_binop (wider_mode, moptab, op0, narrow_op1, 0,
3483 unsignedp, OPTAB_WIDEN);
3485 return extract_high_half (mode, tem);
3488 /* Try widening the mode and perform a non-widening multiplication. */
3489 if (optab_handler (smul_optab, wider_mode) != CODE_FOR_nothing
3490 && size - 1 < BITS_PER_WORD
3491 && mul_cost[speed][wider_mode] + shift_cost[speed][mode][size-1] < max_cost)
3493 rtx insns, wop0, wop1;
3495 /* We need to widen the operands, for example to ensure the
3496 constant multiplier is correctly sign or zero extended.
3497 Use a sequence to clean-up any instructions emitted by
3498 the conversions if things don't work out. */
3500 wop0 = convert_modes (wider_mode, mode, op0, unsignedp);
3501 wop1 = convert_modes (wider_mode, mode, op1, unsignedp);
3502 tem = expand_binop (wider_mode, smul_optab, wop0, wop1, 0,
3503 unsignedp, OPTAB_WIDEN);
3504 insns = get_insns ();
3510 return extract_high_half (mode, tem);
3514 /* Try widening multiplication of opposite signedness, and adjust. */
3515 moptab = unsignedp ? smul_widen_optab : umul_widen_optab;
3516 if (widening_optab_handler (moptab, wider_mode, mode) != CODE_FOR_nothing
3517 && size - 1 < BITS_PER_WORD
3518 && (mul_widen_cost[speed][wider_mode] + 2 * shift_cost[speed][mode][size-1]
3519 + 4 * add_cost[speed][mode] < max_cost))
3521 tem = expand_binop (wider_mode, moptab, op0, narrow_op1,
3522 NULL_RTX, ! unsignedp, OPTAB_WIDEN);
3525 tem = extract_high_half (mode, tem);
3526 /* We used the wrong signedness. Adjust the result. */
3527 return expand_mult_highpart_adjust (mode, tem, op0, narrow_op1,
3535 /* Emit code to multiply OP0 and OP1 (where OP1 is an integer constant),
3536 putting the high half of the result in TARGET if that is convenient,
3537 and return where the result is. If the operation can not be performed,
3540 MODE is the mode of operation and result.
3542 UNSIGNEDP nonzero means unsigned multiply.
3544 MAX_COST is the total allowed cost for the expanded RTL. */
3547 expand_mult_highpart (enum machine_mode mode, rtx op0, rtx op1,
3548 rtx target, int unsignedp, int max_cost)
3550 enum machine_mode wider_mode = GET_MODE_WIDER_MODE (mode);
3551 unsigned HOST_WIDE_INT cnst1;
3553 bool sign_adjust = false;
3554 enum mult_variant variant;
3555 struct algorithm alg;
3557 bool speed = optimize_insn_for_speed_p ();
3559 gcc_assert (!SCALAR_FLOAT_MODE_P (mode));
3560 /* We can't support modes wider than HOST_BITS_PER_INT. */
3561 gcc_assert (HWI_COMPUTABLE_MODE_P (mode));
3563 cnst1 = INTVAL (op1) & GET_MODE_MASK (mode);
3565 /* We can't optimize modes wider than BITS_PER_WORD.
3566 ??? We might be able to perform double-word arithmetic if
3567 mode == word_mode, however all the cost calculations in
3568 synth_mult etc. assume single-word operations. */
3569 if (GET_MODE_BITSIZE (wider_mode) > BITS_PER_WORD)
3570 return expand_mult_highpart_optab (mode, op0, op1, target,
3571 unsignedp, max_cost);
3573 extra_cost = shift_cost[speed][mode][GET_MODE_BITSIZE (mode) - 1];
3575 /* Check whether we try to multiply by a negative constant. */
3576 if (!unsignedp && ((cnst1 >> (GET_MODE_BITSIZE (mode) - 1)) & 1))
3579 extra_cost += add_cost[speed][mode];
3582 /* See whether shift/add multiplication is cheap enough. */
3583 if (choose_mult_variant (wider_mode, cnst1, &alg, &variant,
3584 max_cost - extra_cost))
3586 /* See whether the specialized multiplication optabs are
3587 cheaper than the shift/add version. */
3588 tem = expand_mult_highpart_optab (mode, op0, op1, target, unsignedp,
3589 alg.cost.cost + extra_cost);
3593 tem = convert_to_mode (wider_mode, op0, unsignedp);
3594 tem = expand_mult_const (wider_mode, tem, cnst1, 0, &alg, variant);
3595 tem = extract_high_half (mode, tem);
3597 /* Adjust result for signedness. */
3599 tem = force_operand (gen_rtx_MINUS (mode, tem, op0), tem);
3603 return expand_mult_highpart_optab (mode, op0, op1, target,
3604 unsignedp, max_cost);
3608 /* Expand signed modulus of OP0 by a power of two D in mode MODE. */
3611 expand_smod_pow2 (enum machine_mode mode, rtx op0, HOST_WIDE_INT d)
3613 unsigned HOST_WIDE_INT masklow, maskhigh;
3614 rtx result, temp, shift, label;
3617 logd = floor_log2 (d);
3618 result = gen_reg_rtx (mode);
3620 /* Avoid conditional branches when they're expensive. */
3621 if (BRANCH_COST (optimize_insn_for_speed_p (), false) >= 2
3622 && optimize_insn_for_speed_p ())
3624 rtx signmask = emit_store_flag (result, LT, op0, const0_rtx,
3628 signmask = force_reg (mode, signmask);
3629 masklow = ((HOST_WIDE_INT) 1 << logd) - 1;
3630 shift = GEN_INT (GET_MODE_BITSIZE (mode) - logd);
3632 /* Use the rtx_cost of a LSHIFTRT instruction to determine
3633 which instruction sequence to use. If logical right shifts
3634 are expensive the use 2 XORs, 2 SUBs and an AND, otherwise
3635 use a LSHIFTRT, 1 ADD, 1 SUB and an AND. */
3637 temp = gen_rtx_LSHIFTRT (mode, result, shift);
3638 if (optab_handler (lshr_optab, mode) == CODE_FOR_nothing
3639 || (set_src_cost (temp, optimize_insn_for_speed_p ())
3640 > COSTS_N_INSNS (2)))
3642 temp = expand_binop (mode, xor_optab, op0, signmask,
3643 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3644 temp = expand_binop (mode, sub_optab, temp, signmask,
3645 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3646 temp = expand_binop (mode, and_optab, temp, GEN_INT (masklow),
3647 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3648 temp = expand_binop (mode, xor_optab, temp, signmask,
3649 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3650 temp = expand_binop (mode, sub_optab, temp, signmask,
3651 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3655 signmask = expand_binop (mode, lshr_optab, signmask, shift,
3656 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3657 signmask = force_reg (mode, signmask);
3659 temp = expand_binop (mode, add_optab, op0, signmask,
3660 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3661 temp = expand_binop (mode, and_optab, temp, GEN_INT (masklow),
3662 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3663 temp = expand_binop (mode, sub_optab, temp, signmask,
3664 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3670 /* Mask contains the mode's signbit and the significant bits of the
3671 modulus. By including the signbit in the operation, many targets
3672 can avoid an explicit compare operation in the following comparison
3675 masklow = ((HOST_WIDE_INT) 1 << logd) - 1;
3676 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3678 masklow |= (HOST_WIDE_INT) -1 << (GET_MODE_BITSIZE (mode) - 1);
3682 maskhigh = (HOST_WIDE_INT) -1
3683 << (GET_MODE_BITSIZE (mode) - HOST_BITS_PER_WIDE_INT - 1);
3685 temp = expand_binop (mode, and_optab, op0,
3686 immed_double_const (masklow, maskhigh, mode),
3687 result, 1, OPTAB_LIB_WIDEN);
3689 emit_move_insn (result, temp);
3691 label = gen_label_rtx ();
3692 do_cmp_and_jump (result, const0_rtx, GE, mode, label);
3694 temp = expand_binop (mode, sub_optab, result, const1_rtx, result,
3695 0, OPTAB_LIB_WIDEN);
3696 masklow = (HOST_WIDE_INT) -1 << logd;
3698 temp = expand_binop (mode, ior_optab, temp,
3699 immed_double_const (masklow, maskhigh, mode),
3700 result, 1, OPTAB_LIB_WIDEN);
3701 temp = expand_binop (mode, add_optab, temp, const1_rtx, result,
3702 0, OPTAB_LIB_WIDEN);
3704 emit_move_insn (result, temp);
3709 /* Expand signed division of OP0 by a power of two D in mode MODE.
3710 This routine is only called for positive values of D. */
3713 expand_sdiv_pow2 (enum machine_mode mode, rtx op0, HOST_WIDE_INT d)
3718 logd = floor_log2 (d);
3721 && BRANCH_COST (optimize_insn_for_speed_p (),
3724 temp = gen_reg_rtx (mode);
3725 temp = emit_store_flag (temp, LT, op0, const0_rtx, mode, 0, 1);
3726 temp = expand_binop (mode, add_optab, temp, op0, NULL_RTX,
3727 0, OPTAB_LIB_WIDEN);
3728 return expand_shift (RSHIFT_EXPR, mode, temp, logd, NULL_RTX, 0);
3731 #ifdef HAVE_conditional_move
3732 if (BRANCH_COST (optimize_insn_for_speed_p (), false)
3737 /* ??? emit_conditional_move forces a stack adjustment via
3738 compare_from_rtx so, if the sequence is discarded, it will
3739 be lost. Do it now instead. */
3740 do_pending_stack_adjust ();
3743 temp2 = copy_to_mode_reg (mode, op0);
3744 temp = expand_binop (mode, add_optab, temp2, GEN_INT (d-1),
3745 NULL_RTX, 0, OPTAB_LIB_WIDEN);
3746 temp = force_reg (mode, temp);
3748 /* Construct "temp2 = (temp2 < 0) ? temp : temp2". */
3749 temp2 = emit_conditional_move (temp2, LT, temp2, const0_rtx,
3750 mode, temp, temp2, mode, 0);
3753 rtx seq = get_insns ();
3756 return expand_shift (RSHIFT_EXPR, mode, temp2, logd, NULL_RTX, 0);
3762 if (BRANCH_COST (optimize_insn_for_speed_p (),
3765 int ushift = GET_MODE_BITSIZE (mode) - logd;
3767 temp = gen_reg_rtx (mode);
3768 temp = emit_store_flag (temp, LT, op0, const0_rtx, mode, 0, -1);
3769 if (shift_cost[optimize_insn_for_speed_p ()][mode][ushift] > COSTS_N_INSNS (1))
3770 temp = expand_binop (mode, and_optab, temp, GEN_INT (d - 1),
3771 NULL_RTX, 0, OPTAB_LIB_WIDEN);
3773 temp = expand_shift (RSHIFT_EXPR, mode, temp,
3774 ushift, NULL_RTX, 1);
3775 temp = expand_binop (mode, add_optab, temp, op0, NULL_RTX,
3776 0, OPTAB_LIB_WIDEN);
3777 return expand_shift (RSHIFT_EXPR, mode, temp, logd, NULL_RTX, 0);
3780 label = gen_label_rtx ();
3781 temp = copy_to_mode_reg (mode, op0);
3782 do_cmp_and_jump (temp, const0_rtx, GE, mode, label);
3783 expand_inc (temp, GEN_INT (d - 1));
3785 return expand_shift (RSHIFT_EXPR, mode, temp, logd, NULL_RTX, 0);
3788 /* Emit the code to divide OP0 by OP1, putting the result in TARGET
3789 if that is convenient, and returning where the result is.
3790 You may request either the quotient or the remainder as the result;
3791 specify REM_FLAG nonzero to get the remainder.
3793 CODE is the expression code for which kind of division this is;
3794 it controls how rounding is done. MODE is the machine mode to use.
3795 UNSIGNEDP nonzero means do unsigned division. */
3797 /* ??? For CEIL_MOD_EXPR, can compute incorrect remainder with ANDI
3798 and then correct it by or'ing in missing high bits
3799 if result of ANDI is nonzero.
3800 For ROUND_MOD_EXPR, can use ANDI and then sign-extend the result.
3801 This could optimize to a bfexts instruction.
3802 But C doesn't use these operations, so their optimizations are
3804 /* ??? For modulo, we don't actually need the highpart of the first product,
3805 the low part will do nicely. And for small divisors, the second multiply
3806 can also be a low-part only multiply or even be completely left out.
3807 E.g. to calculate the remainder of a division by 3 with a 32 bit
3808 multiply, multiply with 0x55555556 and extract the upper two bits;
3809 the result is exact for inputs up to 0x1fffffff.
3810 The input range can be reduced by using cross-sum rules.
3811 For odd divisors >= 3, the following table gives right shift counts
3812 so that if a number is shifted by an integer multiple of the given
3813 amount, the remainder stays the same:
3814 2, 4, 3, 6, 10, 12, 4, 8, 18, 6, 11, 20, 18, 0, 5, 10, 12, 0, 12, 20,
3815 14, 12, 23, 21, 8, 0, 20, 18, 0, 0, 6, 12, 0, 22, 0, 18, 20, 30, 0, 0,
3816 0, 8, 0, 11, 12, 10, 36, 0, 30, 0, 0, 12, 0, 0, 0, 0, 44, 12, 24, 0,
3817 20, 0, 7, 14, 0, 18, 36, 0, 0, 46, 60, 0, 42, 0, 15, 24, 20, 0, 0, 33,
3818 0, 20, 0, 0, 18, 0, 60, 0, 0, 0, 0, 0, 40, 18, 0, 0, 12
3820 Cross-sum rules for even numbers can be derived by leaving as many bits
3821 to the right alone as the divisor has zeros to the right.
3822 E.g. if x is an unsigned 32 bit number:
3823 (x mod 12) == (((x & 1023) + ((x >> 8) & ~3)) * 0x15555558 >> 2 * 3) >> 28
3827 expand_divmod (int rem_flag, enum tree_code code, enum machine_mode mode,
3828 rtx op0, rtx op1, rtx target, int unsignedp)
3830 enum machine_mode compute_mode;
3832 rtx quotient = 0, remainder = 0;
3836 optab optab1, optab2;
3837 int op1_is_constant, op1_is_pow2 = 0;
3838 int max_cost, extra_cost;
3839 static HOST_WIDE_INT last_div_const = 0;
3840 static HOST_WIDE_INT ext_op1;
3841 bool speed = optimize_insn_for_speed_p ();
3843 op1_is_constant = CONST_INT_P (op1);
3844 if (op1_is_constant)
3846 ext_op1 = INTVAL (op1);
3848 ext_op1 &= GET_MODE_MASK (mode);
3849 op1_is_pow2 = ((EXACT_POWER_OF_2_OR_ZERO_P (ext_op1)
3850 || (! unsignedp && EXACT_POWER_OF_2_OR_ZERO_P (-ext_op1))));
3854 This is the structure of expand_divmod:
3856 First comes code to fix up the operands so we can perform the operations
3857 correctly and efficiently.
3859 Second comes a switch statement with code specific for each rounding mode.
3860 For some special operands this code emits all RTL for the desired
3861 operation, for other cases, it generates only a quotient and stores it in
3862 QUOTIENT. The case for trunc division/remainder might leave quotient = 0,
3863 to indicate that it has not done anything.
3865 Last comes code that finishes the operation. If QUOTIENT is set and
3866 REM_FLAG is set, the remainder is computed as OP0 - QUOTIENT * OP1. If
3867 QUOTIENT is not set, it is computed using trunc rounding.
3869 We try to generate special code for division and remainder when OP1 is a
3870 constant. If |OP1| = 2**n we can use shifts and some other fast
3871 operations. For other values of OP1, we compute a carefully selected
3872 fixed-point approximation m = 1/OP1, and generate code that multiplies OP0
3875 In all cases but EXACT_DIV_EXPR, this multiplication requires the upper
3876 half of the product. Different strategies for generating the product are
3877 implemented in expand_mult_highpart.
3879 If what we actually want is the remainder, we generate that by another
3880 by-constant multiplication and a subtraction. */
3882 /* We shouldn't be called with OP1 == const1_rtx, but some of the
3883 code below will malfunction if we are, so check here and handle
3884 the special case if so. */
3885 if (op1 == const1_rtx)
3886 return rem_flag ? const0_rtx : op0;
3888 /* When dividing by -1, we could get an overflow.
3889 negv_optab can handle overflows. */
3890 if (! unsignedp && op1 == constm1_rtx)
3894 return expand_unop (mode, flag_trapv && GET_MODE_CLASS(mode) == MODE_INT
3895 ? negv_optab : neg_optab, op0, target, 0);
3899 /* Don't use the function value register as a target
3900 since we have to read it as well as write it,
3901 and function-inlining gets confused by this. */
3902 && ((REG_P (target) && REG_FUNCTION_VALUE_P (target))
3903 /* Don't clobber an operand while doing a multi-step calculation. */
3904 || ((rem_flag || op1_is_constant)
3905 && (reg_mentioned_p (target, op0)
3906 || (MEM_P (op0) && MEM_P (target))))
3907 || reg_mentioned_p (target, op1)
3908 || (MEM_P (op1) && MEM_P (target))))
3911 /* Get the mode in which to perform this computation. Normally it will
3912 be MODE, but sometimes we can't do the desired operation in MODE.
3913 If so, pick a wider mode in which we can do the operation. Convert
3914 to that mode at the start to avoid repeated conversions.
3916 First see what operations we need. These depend on the expression
3917 we are evaluating. (We assume that divxx3 insns exist under the
3918 same conditions that modxx3 insns and that these insns don't normally
3919 fail. If these assumptions are not correct, we may generate less
3920 efficient code in some cases.)
3922 Then see if we find a mode in which we can open-code that operation
3923 (either a division, modulus, or shift). Finally, check for the smallest
3924 mode for which we can do the operation with a library call. */
3926 /* We might want to refine this now that we have division-by-constant
3927 optimization. Since expand_mult_highpart tries so many variants, it is
3928 not straightforward to generalize this. Maybe we should make an array
3929 of possible modes in init_expmed? Save this for GCC 2.7. */
3931 optab1 = ((op1_is_pow2 && op1 != const0_rtx)
3932 ? (unsignedp ? lshr_optab : ashr_optab)
3933 : (unsignedp ? udiv_optab : sdiv_optab));
3934 optab2 = ((op1_is_pow2 && op1 != const0_rtx)
3936 : (unsignedp ? udivmod_optab : sdivmod_optab));
3938 for (compute_mode = mode; compute_mode != VOIDmode;
3939 compute_mode = GET_MODE_WIDER_MODE (compute_mode))
3940 if (optab_handler (optab1, compute_mode) != CODE_FOR_nothing
3941 || optab_handler (optab2, compute_mode) != CODE_FOR_nothing)
3944 if (compute_mode == VOIDmode)
3945 for (compute_mode = mode; compute_mode != VOIDmode;
3946 compute_mode = GET_MODE_WIDER_MODE (compute_mode))
3947 if (optab_libfunc (optab1, compute_mode)
3948 || optab_libfunc (optab2, compute_mode))
3951 /* If we still couldn't find a mode, use MODE, but expand_binop will
3953 if (compute_mode == VOIDmode)
3954 compute_mode = mode;
3956 if (target && GET_MODE (target) == compute_mode)
3959 tquotient = gen_reg_rtx (compute_mode);
3961 size = GET_MODE_BITSIZE (compute_mode);
3963 /* It should be possible to restrict the precision to GET_MODE_BITSIZE
3964 (mode), and thereby get better code when OP1 is a constant. Do that
3965 later. It will require going over all usages of SIZE below. */
3966 size = GET_MODE_BITSIZE (mode);
3969 /* Only deduct something for a REM if the last divide done was
3970 for a different constant. Then set the constant of the last
3972 max_cost = unsignedp ? udiv_cost[speed][compute_mode] : sdiv_cost[speed][compute_mode];
3973 if (rem_flag && ! (last_div_const != 0 && op1_is_constant
3974 && INTVAL (op1) == last_div_const))
3975 max_cost -= mul_cost[speed][compute_mode] + add_cost[speed][compute_mode];
3977 last_div_const = ! rem_flag && op1_is_constant ? INTVAL (op1) : 0;
3979 /* Now convert to the best mode to use. */
3980 if (compute_mode != mode)
3982 op0 = convert_modes (compute_mode, mode, op0, unsignedp);
3983 op1 = convert_modes (compute_mode, mode, op1, unsignedp);
3985 /* convert_modes may have placed op1 into a register, so we
3986 must recompute the following. */
3987 op1_is_constant = CONST_INT_P (op1);
3988 op1_is_pow2 = (op1_is_constant
3989 && ((EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1))
3991 && EXACT_POWER_OF_2_OR_ZERO_P (-INTVAL (op1)))))) ;
3994 /* If one of the operands is a volatile MEM, copy it into a register. */
3996 if (MEM_P (op0) && MEM_VOLATILE_P (op0))
3997 op0 = force_reg (compute_mode, op0);
3998 if (MEM_P (op1) && MEM_VOLATILE_P (op1))
3999 op1 = force_reg (compute_mode, op1);
4001 /* If we need the remainder or if OP1 is constant, we need to
4002 put OP0 in a register in case it has any queued subexpressions. */
4003 if (rem_flag || op1_is_constant)
4004 op0 = force_reg (compute_mode, op0);
4006 last = get_last_insn ();
4008 /* Promote floor rounding to trunc rounding for unsigned operations. */
4011 if (code == FLOOR_DIV_EXPR)
4012 code = TRUNC_DIV_EXPR;
4013 if (code == FLOOR_MOD_EXPR)
4014 code = TRUNC_MOD_EXPR;
4015 if (code == EXACT_DIV_EXPR && op1_is_pow2)
4016 code = TRUNC_DIV_EXPR;
4019 if (op1 != const0_rtx)
4022 case TRUNC_MOD_EXPR:
4023 case TRUNC_DIV_EXPR:
4024 if (op1_is_constant)
4028 unsigned HOST_WIDE_INT mh;
4029 int pre_shift, post_shift;
4032 unsigned HOST_WIDE_INT d = (INTVAL (op1)
4033 & GET_MODE_MASK (compute_mode));
4035 if (EXACT_POWER_OF_2_OR_ZERO_P (d))
4037 pre_shift = floor_log2 (d);
4041 = expand_binop (compute_mode, and_optab, op0,
4042 GEN_INT (((HOST_WIDE_INT) 1 << pre_shift) - 1),
4046 return gen_lowpart (mode, remainder);
4048 quotient = expand_shift (RSHIFT_EXPR, compute_mode, op0,
4049 pre_shift, tquotient, 1);
4051 else if (size <= HOST_BITS_PER_WIDE_INT)
4053 if (d >= ((unsigned HOST_WIDE_INT) 1 << (size - 1)))
4055 /* Most significant bit of divisor is set; emit an scc
4057 quotient = emit_store_flag_force (tquotient, GEU, op0, op1,
4058 compute_mode, 1, 1);
4062 /* Find a suitable multiplier and right shift count
4063 instead of multiplying with D. */
4065 mh = choose_multiplier (d, size, size,
4066 &ml, &post_shift, &dummy);
4068 /* If the suggested multiplier is more than SIZE bits,
4069 we can do better for even divisors, using an
4070 initial right shift. */
4071 if (mh != 0 && (d & 1) == 0)
4073 pre_shift = floor_log2 (d & -d);
4074 mh = choose_multiplier (d >> pre_shift, size,
4076 &ml, &post_shift, &dummy);
4086 if (post_shift - 1 >= BITS_PER_WORD)
4090 = (shift_cost[speed][compute_mode][post_shift - 1]
4091 + shift_cost[speed][compute_mode][1]
4092 + 2 * add_cost[speed][compute_mode]);
4093 t1 = expand_mult_highpart (compute_mode, op0, ml,
4095 max_cost - extra_cost);
4098 t2 = force_operand (gen_rtx_MINUS (compute_mode,
4101 t3 = expand_shift (RSHIFT_EXPR, compute_mode,
4102 t2, 1, NULL_RTX, 1);
4103 t4 = force_operand (gen_rtx_PLUS (compute_mode,
4106 quotient = expand_shift
4107 (RSHIFT_EXPR, compute_mode, t4,
4108 post_shift - 1, tquotient, 1);
4114 if (pre_shift >= BITS_PER_WORD
4115 || post_shift >= BITS_PER_WORD)
4119 (RSHIFT_EXPR, compute_mode, op0,
4120 pre_shift, NULL_RTX, 1);
4122 = (shift_cost[speed][compute_mode][pre_shift]
4123 + shift_cost[speed][compute_mode][post_shift]);
4124 t2 = expand_mult_highpart (compute_mode, t1, ml,
4126 max_cost - extra_cost);
4129 quotient = expand_shift
4130 (RSHIFT_EXPR, compute_mode, t2,
4131 post_shift, tquotient, 1);
4135 else /* Too wide mode to use tricky code */
4138 insn = get_last_insn ();
4140 && (set = single_set (insn)) != 0
4141 && SET_DEST (set) == quotient)
4142 set_unique_reg_note (insn,
4144 gen_rtx_UDIV (compute_mode, op0, op1));
4146 else /* TRUNC_DIV, signed */
4148 unsigned HOST_WIDE_INT ml;
4149 int lgup, post_shift;
4151 HOST_WIDE_INT d = INTVAL (op1);
4152 unsigned HOST_WIDE_INT abs_d;
4154 /* Since d might be INT_MIN, we have to cast to
4155 unsigned HOST_WIDE_INT before negating to avoid
4156 undefined signed overflow. */
4158 ? (unsigned HOST_WIDE_INT) d
4159 : - (unsigned HOST_WIDE_INT) d);
4161 /* n rem d = n rem -d */
4162 if (rem_flag && d < 0)
4165 op1 = gen_int_mode (abs_d, compute_mode);
4171 quotient = expand_unop (compute_mode, neg_optab, op0,
4173 else if (HOST_BITS_PER_WIDE_INT >= size
4174 && abs_d == (unsigned HOST_WIDE_INT) 1 << (size - 1))
4176 /* This case is not handled correctly below. */
4177 quotient = emit_store_flag (tquotient, EQ, op0, op1,
4178 compute_mode, 1, 1);
4182 else if (EXACT_POWER_OF_2_OR_ZERO_P (d)
4183 && (rem_flag ? smod_pow2_cheap[speed][compute_mode]
4184 : sdiv_pow2_cheap[speed][compute_mode])
4185 /* We assume that cheap metric is true if the
4186 optab has an expander for this mode. */
4187 && ((optab_handler ((rem_flag ? smod_optab
4190 != CODE_FOR_nothing)
4191 || (optab_handler (sdivmod_optab,
4193 != CODE_FOR_nothing)))
4195 else if (EXACT_POWER_OF_2_OR_ZERO_P (abs_d))
4199 remainder = expand_smod_pow2 (compute_mode, op0, d);
4201 return gen_lowpart (mode, remainder);
4204 if (sdiv_pow2_cheap[speed][compute_mode]
4205 && ((optab_handler (sdiv_optab, compute_mode)
4206 != CODE_FOR_nothing)
4207 || (optab_handler (sdivmod_optab, compute_mode)
4208 != CODE_FOR_nothing)))
4209 quotient = expand_divmod (0, TRUNC_DIV_EXPR,
4211 gen_int_mode (abs_d,
4215 quotient = expand_sdiv_pow2 (compute_mode, op0, abs_d);
4217 /* We have computed OP0 / abs(OP1). If OP1 is negative,
4218 negate the quotient. */
4221 insn = get_last_insn ();
4223 && (set = single_set (insn)) != 0
4224 && SET_DEST (set) == quotient
4225 && abs_d < ((unsigned HOST_WIDE_INT) 1
4226 << (HOST_BITS_PER_WIDE_INT - 1)))
4227 set_unique_reg_note (insn,
4229 gen_rtx_DIV (compute_mode,
4236 quotient = expand_unop (compute_mode, neg_optab,
4237 quotient, quotient, 0);
4240 else if (size <= HOST_BITS_PER_WIDE_INT)
4242 choose_multiplier (abs_d, size, size - 1,
4243 &mlr, &post_shift, &lgup);
4244 ml = (unsigned HOST_WIDE_INT) INTVAL (mlr);
4245 if (ml < (unsigned HOST_WIDE_INT) 1 << (size - 1))
4249 if (post_shift >= BITS_PER_WORD
4250 || size - 1 >= BITS_PER_WORD)
4253 extra_cost = (shift_cost[speed][compute_mode][post_shift]
4254 + shift_cost[speed][compute_mode][size - 1]
4255 + add_cost[speed][compute_mode]);
4256 t1 = expand_mult_highpart (compute_mode, op0, mlr,
4258 max_cost - extra_cost);
4262 (RSHIFT_EXPR, compute_mode, t1,
4263 post_shift, NULL_RTX, 0);
4265 (RSHIFT_EXPR, compute_mode, op0,
4266 size - 1, NULL_RTX, 0);
4269 = force_operand (gen_rtx_MINUS (compute_mode,
4274 = force_operand (gen_rtx_MINUS (compute_mode,
4282 if (post_shift >= BITS_PER_WORD
4283 || size - 1 >= BITS_PER_WORD)
4286 ml |= (~(unsigned HOST_WIDE_INT) 0) << (size - 1);
4287 mlr = gen_int_mode (ml, compute_mode);
4288 extra_cost = (shift_cost[speed][compute_mode][post_shift]
4289 + shift_cost[speed][compute_mode][size - 1]
4290 + 2 * add_cost[speed][compute_mode]);
4291 t1 = expand_mult_highpart (compute_mode, op0, mlr,
4293 max_cost - extra_cost);
4296 t2 = force_operand (gen_rtx_PLUS (compute_mode,
4300 (RSHIFT_EXPR, compute_mode, t2,
4301 post_shift, NULL_RTX, 0);
4303 (RSHIFT_EXPR, compute_mode, op0,
4304 size - 1, NULL_RTX, 0);
4307 = force_operand (gen_rtx_MINUS (compute_mode,
4312 = force_operand (gen_rtx_MINUS (compute_mode,
4317 else /* Too wide mode to use tricky code */
4320 insn = get_last_insn ();
4322 && (set = single_set (insn)) != 0
4323 && SET_DEST (set) == quotient)
4324 set_unique_reg_note (insn,
4326 gen_rtx_DIV (compute_mode, op0, op1));
4331 delete_insns_since (last);
4334 case FLOOR_DIV_EXPR:
4335 case FLOOR_MOD_EXPR:
4336 /* We will come here only for signed operations. */
4337 if (op1_is_constant && HOST_BITS_PER_WIDE_INT >= size)
4339 unsigned HOST_WIDE_INT mh;
4340 int pre_shift, lgup, post_shift;
4341 HOST_WIDE_INT d = INTVAL (op1);
4346 /* We could just as easily deal with negative constants here,
4347 but it does not seem worth the trouble for GCC 2.6. */
4348 if (EXACT_POWER_OF_2_OR_ZERO_P (d))
4350 pre_shift = floor_log2 (d);
4353 remainder = expand_binop (compute_mode, and_optab, op0,
4354 GEN_INT (((HOST_WIDE_INT) 1 << pre_shift) - 1),
4355 remainder, 0, OPTAB_LIB_WIDEN);
4357 return gen_lowpart (mode, remainder);
4359 quotient = expand_shift
4360 (RSHIFT_EXPR, compute_mode, op0,
4361 pre_shift, tquotient, 0);
4367 mh = choose_multiplier (d, size, size - 1,
4368 &ml, &post_shift, &lgup);
4371 if (post_shift < BITS_PER_WORD
4372 && size - 1 < BITS_PER_WORD)
4375 (RSHIFT_EXPR, compute_mode, op0,
4376 size - 1, NULL_RTX, 0);
4377 t2 = expand_binop (compute_mode, xor_optab, op0, t1,
4378 NULL_RTX, 0, OPTAB_WIDEN);
4379 extra_cost = (shift_cost[speed][compute_mode][post_shift]
4380 + shift_cost[speed][compute_mode][size - 1]
4381 + 2 * add_cost[speed][compute_mode]);
4382 t3 = expand_mult_highpart (compute_mode, t2, ml,
4384 max_cost - extra_cost);
4388 (RSHIFT_EXPR, compute_mode, t3,
4389 post_shift, NULL_RTX, 1);
4390 quotient = expand_binop (compute_mode, xor_optab,
4391 t4, t1, tquotient, 0,
4399 rtx nsign, t1, t2, t3, t4;
4400 t1 = force_operand (gen_rtx_PLUS (compute_mode,
4401 op0, constm1_rtx), NULL_RTX);
4402 t2 = expand_binop (compute_mode, ior_optab, op0, t1, NULL_RTX,
4404 nsign = expand_shift
4405 (RSHIFT_EXPR, compute_mode, t2,
4406 size - 1, NULL_RTX, 0);
4407 t3 = force_operand (gen_rtx_MINUS (compute_mode, t1, nsign),
4409 t4 = expand_divmod (0, TRUNC_DIV_EXPR, compute_mode, t3, op1,
4414 t5 = expand_unop (compute_mode, one_cmpl_optab, nsign,
4416 quotient = force_operand (gen_rtx_PLUS (compute_mode,
4425 delete_insns_since (last);
4427 /* Try using an instruction that produces both the quotient and
4428 remainder, using truncation. We can easily compensate the quotient
4429 or remainder to get floor rounding, once we have the remainder.
4430 Notice that we compute also the final remainder value here,
4431 and return the result right away. */
4432 if (target == 0 || GET_MODE (target) != compute_mode)
4433 target = gen_reg_rtx (compute_mode);
4438 = REG_P (target) ? target : gen_reg_rtx (compute_mode);
4439 quotient = gen_reg_rtx (compute_mode);
4444 = REG_P (target) ? target : gen_reg_rtx (compute_mode);
4445 remainder = gen_reg_rtx (compute_mode);
4448 if (expand_twoval_binop (sdivmod_optab, op0, op1,
4449 quotient, remainder, 0))
4451 /* This could be computed with a branch-less sequence.
4452 Save that for later. */
4454 rtx label = gen_label_rtx ();
4455 do_cmp_and_jump (remainder, const0_rtx, EQ, compute_mode, label);
4456 tem = expand_binop (compute_mode, xor_optab, op0, op1,
4457 NULL_RTX, 0, OPTAB_WIDEN);
4458 do_cmp_and_jump (tem, const0_rtx, GE, compute_mode, label);
4459 expand_dec (quotient, const1_rtx);
4460 expand_inc (remainder, op1);
4462 return gen_lowpart (mode, rem_flag ? remainder : quotient);
4465 /* No luck with division elimination or divmod. Have to do it
4466 by conditionally adjusting op0 *and* the result. */
4468 rtx label1, label2, label3, label4, label5;
4472 quotient = gen_reg_rtx (compute_mode);
4473 adjusted_op0 = copy_to_mode_reg (compute_mode, op0);
4474 label1 = gen_label_rtx ();
4475 label2 = gen_label_rtx ();
4476 label3 = gen_label_rtx ();
4477 label4 = gen_label_rtx ();
4478 label5 = gen_label_rtx ();
4479 do_cmp_and_jump (op1, const0_rtx, LT, compute_mode, label2);
4480 do_cmp_and_jump (adjusted_op0, const0_rtx, LT, compute_mode, label1);
4481 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
4482 quotient, 0, OPTAB_LIB_WIDEN);
4483 if (tem != quotient)
4484 emit_move_insn (quotient, tem);
4485 emit_jump_insn (gen_jump (label5));
4487 emit_label (label1);
4488 expand_inc (adjusted_op0, const1_rtx);
4489 emit_jump_insn (gen_jump (label4));
4491 emit_label (label2);
4492 do_cmp_and_jump (adjusted_op0, const0_rtx, GT, compute_mode, label3);
4493 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
4494 quotient, 0, OPTAB_LIB_WIDEN);
4495 if (tem != quotient)
4496 emit_move_insn (quotient, tem);
4497 emit_jump_insn (gen_jump (label5));
4499 emit_label (label3);
4500 expand_dec (adjusted_op0, const1_rtx);
4501 emit_label (label4);
4502 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
4503 quotient, 0, OPTAB_LIB_WIDEN);
4504 if (tem != quotient)
4505 emit_move_insn (quotient, tem);
4506 expand_dec (quotient, const1_rtx);
4507 emit_label (label5);
4515 if (op1_is_constant && EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1)))
4518 unsigned HOST_WIDE_INT d = INTVAL (op1);
4519 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
4520 floor_log2 (d), tquotient, 1);
4521 t2 = expand_binop (compute_mode, and_optab, op0,
4523 NULL_RTX, 1, OPTAB_LIB_WIDEN);
4524 t3 = gen_reg_rtx (compute_mode);
4525 t3 = emit_store_flag (t3, NE, t2, const0_rtx,
4526 compute_mode, 1, 1);
4530 lab = gen_label_rtx ();
4531 do_cmp_and_jump (t2, const0_rtx, EQ, compute_mode, lab);
4532 expand_inc (t1, const1_rtx);
4537 quotient = force_operand (gen_rtx_PLUS (compute_mode,
4543 /* Try using an instruction that produces both the quotient and
4544 remainder, using truncation. We can easily compensate the
4545 quotient or remainder to get ceiling rounding, once we have the
4546 remainder. Notice that we compute also the final remainder
4547 value here, and return the result right away. */
4548 if (target == 0 || GET_MODE (target) != compute_mode)
4549 target = gen_reg_rtx (compute_mode);
4553 remainder = (REG_P (target)
4554 ? target : gen_reg_rtx (compute_mode));
4555 quotient = gen_reg_rtx (compute_mode);
4559 quotient = (REG_P (target)
4560 ? target : gen_reg_rtx (compute_mode));
4561 remainder = gen_reg_rtx (compute_mode);
4564 if (expand_twoval_binop (udivmod_optab, op0, op1, quotient,
4567 /* This could be computed with a branch-less sequence.
4568 Save that for later. */
4569 rtx label = gen_label_rtx ();
4570 do_cmp_and_jump (remainder, const0_rtx, EQ,
4571 compute_mode, label);
4572 expand_inc (quotient, const1_rtx);
4573 expand_dec (remainder, op1);
4575 return gen_lowpart (mode, rem_flag ? remainder : quotient);
4578 /* No luck with division elimination or divmod. Have to do it
4579 by conditionally adjusting op0 *and* the result. */
4582 rtx adjusted_op0, tem;
4584 quotient = gen_reg_rtx (compute_mode);
4585 adjusted_op0 = copy_to_mode_reg (compute_mode, op0);
4586 label1 = gen_label_rtx ();
4587 label2 = gen_label_rtx ();
4588 do_cmp_and_jump (adjusted_op0, const0_rtx, NE,
4589 compute_mode, label1);
4590 emit_move_insn (quotient, const0_rtx);
4591 emit_jump_insn (gen_jump (label2));
4593 emit_label (label1);
4594 expand_dec (adjusted_op0, const1_rtx);
4595 tem = expand_binop (compute_mode, udiv_optab, adjusted_op0, op1,
4596 quotient, 1, OPTAB_LIB_WIDEN);
4597 if (tem != quotient)
4598 emit_move_insn (quotient, tem);
4599 expand_inc (quotient, const1_rtx);
4600 emit_label (label2);
4605 if (op1_is_constant && EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1))
4606 && INTVAL (op1) >= 0)
4608 /* This is extremely similar to the code for the unsigned case
4609 above. For 2.7 we should merge these variants, but for
4610 2.6.1 I don't want to touch the code for unsigned since that
4611 get used in C. The signed case will only be used by other
4615 unsigned HOST_WIDE_INT d = INTVAL (op1);
4616 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
4617 floor_log2 (d), tquotient, 0);
4618 t2 = expand_binop (compute_mode, and_optab, op0,
4620 NULL_RTX, 1, OPTAB_LIB_WIDEN);
4621 t3 = gen_reg_rtx (compute_mode);
4622 t3 = emit_store_flag (t3, NE, t2, const0_rtx,
4623 compute_mode, 1, 1);
4627 lab = gen_label_rtx ();
4628 do_cmp_and_jump (t2, const0_rtx, EQ, compute_mode, lab);
4629 expand_inc (t1, const1_rtx);
4634 quotient = force_operand (gen_rtx_PLUS (compute_mode,
4640 /* Try using an instruction that produces both the quotient and
4641 remainder, using truncation. We can easily compensate the
4642 quotient or remainder to get ceiling rounding, once we have the
4643 remainder. Notice that we compute also the final remainder
4644 value here, and return the result right away. */
4645 if (target == 0 || GET_MODE (target) != compute_mode)
4646 target = gen_reg_rtx (compute_mode);
4649 remainder= (REG_P (target)
4650 ? target : gen_reg_rtx (compute_mode));
4651 quotient = gen_reg_rtx (compute_mode);
4655 quotient = (REG_P (target)
4656 ? target : gen_reg_rtx (compute_mode));
4657 remainder = gen_reg_rtx (compute_mode);
4660 if (expand_twoval_binop (sdivmod_optab, op0, op1, quotient,
4663 /* This could be computed with a branch-less sequence.
4664 Save that for later. */
4666 rtx label = gen_label_rtx ();
4667 do_cmp_and_jump (remainder, const0_rtx, EQ,
4668 compute_mode, label);
4669 tem = expand_binop (compute_mode, xor_optab, op0, op1,
4670 NULL_RTX, 0, OPTAB_WIDEN);
4671 do_cmp_and_jump (tem, const0_rtx, LT, compute_mode, label);
4672 expand_inc (quotient, const1_rtx);
4673 expand_dec (remainder, op1);
4675 return gen_lowpart (mode, rem_flag ? remainder : quotient);
4678 /* No luck with division elimination or divmod. Have to do it
4679 by conditionally adjusting op0 *and* the result. */
4681 rtx label1, label2, label3, label4, label5;
4685 quotient = gen_reg_rtx (compute_mode);
4686 adjusted_op0 = copy_to_mode_reg (compute_mode, op0);
4687 label1 = gen_label_rtx ();
4688 label2 = gen_label_rtx ();
4689 label3 = gen_label_rtx ();
4690 label4 = gen_label_rtx ();
4691 label5 = gen_label_rtx ();
4692 do_cmp_and_jump (op1, const0_rtx, LT, compute_mode, label2);
4693 do_cmp_and_jump (adjusted_op0, const0_rtx, GT,
4694 compute_mode, label1);
4695 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
4696 quotient, 0, OPTAB_LIB_WIDEN);
4697 if (tem != quotient)
4698 emit_move_insn (quotient, tem);
4699 emit_jump_insn (gen_jump (label5));
4701 emit_label (label1);
4702 expand_dec (adjusted_op0, const1_rtx);
4703 emit_jump_insn (gen_jump (label4));
4705 emit_label (label2);
4706 do_cmp_and_jump (adjusted_op0, const0_rtx, LT,
4707 compute_mode, label3);
4708 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
4709 quotient, 0, OPTAB_LIB_WIDEN);
4710 if (tem != quotient)
4711 emit_move_insn (quotient, tem);
4712 emit_jump_insn (gen_jump (label5));
4714 emit_label (label3);
4715 expand_inc (adjusted_op0, const1_rtx);
4716 emit_label (label4);
4717 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
4718 quotient, 0, OPTAB_LIB_WIDEN);
4719 if (tem != quotient)
4720 emit_move_insn (quotient, tem);
4721 expand_inc (quotient, const1_rtx);
4722 emit_label (label5);
4727 case EXACT_DIV_EXPR:
4728 if (op1_is_constant && HOST_BITS_PER_WIDE_INT >= size)
4730 HOST_WIDE_INT d = INTVAL (op1);
4731 unsigned HOST_WIDE_INT ml;
4735 pre_shift = floor_log2 (d & -d);
4736 ml = invert_mod2n (d >> pre_shift, size);
4737 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
4738 pre_shift, NULL_RTX, unsignedp);
4739 quotient = expand_mult (compute_mode, t1,
4740 gen_int_mode (ml, compute_mode),
4743 insn = get_last_insn ();
4744 set_unique_reg_note (insn,
4746 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
4752 case ROUND_DIV_EXPR:
4753 case ROUND_MOD_EXPR:
4758 label = gen_label_rtx ();
4759 quotient = gen_reg_rtx (compute_mode);
4760 remainder = gen_reg_rtx (compute_mode);
4761 if (expand_twoval_binop (udivmod_optab, op0, op1, quotient, remainder, 1) == 0)
4764 quotient = expand_binop (compute_mode, udiv_optab, op0, op1,
4765 quotient, 1, OPTAB_LIB_WIDEN);
4766 tem = expand_mult (compute_mode, quotient, op1, NULL_RTX, 1);
4767 remainder = expand_binop (compute_mode, sub_optab, op0, tem,
4768 remainder, 1, OPTAB_LIB_WIDEN);
4770 tem = plus_constant (op1, -1);
4771 tem = expand_shift (RSHIFT_EXPR, compute_mode, tem, 1, NULL_RTX, 1);
4772 do_cmp_and_jump (remainder, tem, LEU, compute_mode, label);
4773 expand_inc (quotient, const1_rtx);
4774 expand_dec (remainder, op1);
4779 rtx abs_rem, abs_op1, tem, mask;
4781 label = gen_label_rtx ();
4782 quotient = gen_reg_rtx (compute_mode);
4783 remainder = gen_reg_rtx (compute_mode);
4784 if (expand_twoval_binop (sdivmod_optab, op0, op1, quotient, remainder, 0) == 0)
4787 quotient = expand_binop (compute_mode, sdiv_optab, op0, op1,
4788 quotient, 0, OPTAB_LIB_WIDEN);
4789 tem = expand_mult (compute_mode, quotient, op1, NULL_RTX, 0);
4790 remainder = expand_binop (compute_mode, sub_optab, op0, tem,
4791 remainder, 0, OPTAB_LIB_WIDEN);
4793 abs_rem = expand_abs (compute_mode, remainder, NULL_RTX, 1, 0);
4794 abs_op1 = expand_abs (compute_mode, op1, NULL_RTX, 1, 0);
4795 tem = expand_shift (LSHIFT_EXPR, compute_mode, abs_rem,
4797 do_cmp_and_jump (tem, abs_op1, LTU, compute_mode, label);
4798 tem = expand_binop (compute_mode, xor_optab, op0, op1,
4799 NULL_RTX, 0, OPTAB_WIDEN);
4800 mask = expand_shift (RSHIFT_EXPR, compute_mode, tem,
4801 size - 1, NULL_RTX, 0);
4802 tem = expand_binop (compute_mode, xor_optab, mask, const1_rtx,
4803 NULL_RTX, 0, OPTAB_WIDEN);
4804 tem = expand_binop (compute_mode, sub_optab, tem, mask,
4805 NULL_RTX, 0, OPTAB_WIDEN);
4806 expand_inc (quotient, tem);
4807 tem = expand_binop (compute_mode, xor_optab, mask, op1,
4808 NULL_RTX, 0, OPTAB_WIDEN);
4809 tem = expand_binop (compute_mode, sub_optab, tem, mask,
4810 NULL_RTX, 0, OPTAB_WIDEN);
4811 expand_dec (remainder, tem);
4814 return gen_lowpart (mode, rem_flag ? remainder : quotient);
4822 if (target && GET_MODE (target) != compute_mode)
4827 /* Try to produce the remainder without producing the quotient.
4828 If we seem to have a divmod pattern that does not require widening,
4829 don't try widening here. We should really have a WIDEN argument
4830 to expand_twoval_binop, since what we'd really like to do here is
4831 1) try a mod insn in compute_mode
4832 2) try a divmod insn in compute_mode
4833 3) try a div insn in compute_mode and multiply-subtract to get
4835 4) try the same things with widening allowed. */
4837 = sign_expand_binop (compute_mode, umod_optab, smod_optab,
4840 ((optab_handler (optab2, compute_mode)
4841 != CODE_FOR_nothing)
4842 ? OPTAB_DIRECT : OPTAB_WIDEN));
4845 /* No luck there. Can we do remainder and divide at once
4846 without a library call? */
4847 remainder = gen_reg_rtx (compute_mode);
4848 if (! expand_twoval_binop ((unsignedp
4852 NULL_RTX, remainder, unsignedp))
4857 return gen_lowpart (mode, remainder);
4860 /* Produce the quotient. Try a quotient insn, but not a library call.
4861 If we have a divmod in this mode, use it in preference to widening
4862 the div (for this test we assume it will not fail). Note that optab2
4863 is set to the one of the two optabs that the call below will use. */
4865 = sign_expand_binop (compute_mode, udiv_optab, sdiv_optab,
4866 op0, op1, rem_flag ? NULL_RTX : target,
4868 ((optab_handler (optab2, compute_mode)
4869 != CODE_FOR_nothing)
4870 ? OPTAB_DIRECT : OPTAB_WIDEN));
4874 /* No luck there. Try a quotient-and-remainder insn,
4875 keeping the quotient alone. */
4876 quotient = gen_reg_rtx (compute_mode);
4877 if (! expand_twoval_binop (unsignedp ? udivmod_optab : sdivmod_optab,
4879 quotient, NULL_RTX, unsignedp))
4883 /* Still no luck. If we are not computing the remainder,
4884 use a library call for the quotient. */
4885 quotient = sign_expand_binop (compute_mode,
4886 udiv_optab, sdiv_optab,
4888 unsignedp, OPTAB_LIB_WIDEN);
4895 if (target && GET_MODE (target) != compute_mode)
4900 /* No divide instruction either. Use library for remainder. */
4901 remainder = sign_expand_binop (compute_mode, umod_optab, smod_optab,
4903 unsignedp, OPTAB_LIB_WIDEN);
4904 /* No remainder function. Try a quotient-and-remainder
4905 function, keeping the remainder. */
4908 remainder = gen_reg_rtx (compute_mode);
4909 if (!expand_twoval_binop_libfunc
4910 (unsignedp ? udivmod_optab : sdivmod_optab,
4912 NULL_RTX, remainder,
4913 unsignedp ? UMOD : MOD))
4914 remainder = NULL_RTX;
4919 /* We divided. Now finish doing X - Y * (X / Y). */
4920 remainder = expand_mult (compute_mode, quotient, op1,
4921 NULL_RTX, unsignedp);
4922 remainder = expand_binop (compute_mode, sub_optab, op0,
4923 remainder, target, unsignedp,
4928 return gen_lowpart (mode, rem_flag ? remainder : quotient);
4931 /* Return a tree node with data type TYPE, describing the value of X.
4932 Usually this is an VAR_DECL, if there is no obvious better choice.
4933 X may be an expression, however we only support those expressions
4934 generated by loop.c. */
4937 make_tree (tree type, rtx x)
4941 switch (GET_CODE (x))
4945 HOST_WIDE_INT hi = 0;
4948 && !(TYPE_UNSIGNED (type)
4949 && (GET_MODE_BITSIZE (TYPE_MODE (type))
4950 < HOST_BITS_PER_WIDE_INT)))
4953 t = build_int_cst_wide (type, INTVAL (x), hi);
4959 if (GET_MODE (x) == VOIDmode)
4960 t = build_int_cst_wide (type,
4961 CONST_DOUBLE_LOW (x), CONST_DOUBLE_HIGH (x));
4966 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
4967 t = build_real (type, d);
4974 int units = CONST_VECTOR_NUNITS (x);
4975 tree itype = TREE_TYPE (type);
4980 /* Build a tree with vector elements. */
4981 for (i = units - 1; i >= 0; --i)
4983 rtx elt = CONST_VECTOR_ELT (x, i);
4984 t = tree_cons (NULL_TREE, make_tree (itype, elt), t);
4987 return build_vector (type, t);
4991 return fold_build2 (PLUS_EXPR, type, make_tree (type, XEXP (x, 0)),
4992 make_tree (type, XEXP (x, 1)));
4995 return fold_build2 (MINUS_EXPR, type, make_tree (type, XEXP (x, 0)),
4996 make_tree (type, XEXP (x, 1)));
4999 return fold_build1 (NEGATE_EXPR, type, make_tree (type, XEXP (x, 0)));
5002 return fold_build2 (MULT_EXPR, type, make_tree (type, XEXP (x, 0)),
5003 make_tree (type, XEXP (x, 1)));
5006 return fold_build2 (LSHIFT_EXPR, type, make_tree (type, XEXP (x, 0)),
5007 make_tree (type, XEXP (x, 1)));
5010 t = unsigned_type_for (type);
5011 return fold_convert (type, build2 (RSHIFT_EXPR, t,
5012 make_tree (t, XEXP (x, 0)),
5013 make_tree (type, XEXP (x, 1))));
5016 t = signed_type_for (type);
5017 return fold_convert (type, build2 (RSHIFT_EXPR, t,
5018 make_tree (t, XEXP (x, 0)),
5019 make_tree (type, XEXP (x, 1))));
5022 if (TREE_CODE (type) != REAL_TYPE)
5023 t = signed_type_for (type);
5027 return fold_convert (type, build2 (TRUNC_DIV_EXPR, t,
5028 make_tree (t, XEXP (x, 0)),
5029 make_tree (t, XEXP (x, 1))));
5031 t = unsigned_type_for (type);
5032 return fold_convert (type, build2 (TRUNC_DIV_EXPR, t,
5033 make_tree (t, XEXP (x, 0)),
5034 make_tree (t, XEXP (x, 1))));
5038 t = lang_hooks.types.type_for_mode (GET_MODE (XEXP (x, 0)),
5039 GET_CODE (x) == ZERO_EXTEND);
5040 return fold_convert (type, make_tree (t, XEXP (x, 0)));
5043 return make_tree (type, XEXP (x, 0));
5046 t = SYMBOL_REF_DECL (x);
5048 return fold_convert (type, build_fold_addr_expr (t));
5049 /* else fall through. */
5052 t = build_decl (RTL_LOCATION (x), VAR_DECL, NULL_TREE, type);
5054 /* If TYPE is a POINTER_TYPE, we might need to convert X from
5055 address mode to pointer mode. */
5056 if (POINTER_TYPE_P (type))
5057 x = convert_memory_address_addr_space
5058 (TYPE_MODE (type), x, TYPE_ADDR_SPACE (TREE_TYPE (type)));
5060 /* Note that we do *not* use SET_DECL_RTL here, because we do not
5061 want set_decl_rtl to go adjusting REG_ATTRS for this temporary. */
5062 t->decl_with_rtl.rtl = x;
5068 /* Compute the logical-and of OP0 and OP1, storing it in TARGET
5069 and returning TARGET.
5071 If TARGET is 0, a pseudo-register or constant is returned. */
5074 expand_and (enum machine_mode mode, rtx op0, rtx op1, rtx target)
5078 if (GET_MODE (op0) == VOIDmode && GET_MODE (op1) == VOIDmode)
5079 tem = simplify_binary_operation (AND, mode, op0, op1);
5081 tem = expand_binop (mode, and_optab, op0, op1, target, 0, OPTAB_LIB_WIDEN);
5085 else if (tem != target)
5086 emit_move_insn (target, tem);
5090 /* Helper function for emit_store_flag. */
5092 emit_cstore (rtx target, enum insn_code icode, enum rtx_code code,
5093 enum machine_mode mode, enum machine_mode compare_mode,
5094 int unsignedp, rtx x, rtx y, int normalizep,
5095 enum machine_mode target_mode)
5097 struct expand_operand ops[4];
5098 rtx op0, last, comparison, subtarget;
5099 enum machine_mode result_mode = insn_data[(int) icode].operand[0].mode;
5101 last = get_last_insn ();
5102 x = prepare_operand (icode, x, 2, mode, compare_mode, unsignedp);
5103 y = prepare_operand (icode, y, 3, mode, compare_mode, unsignedp);
5106 delete_insns_since (last);
5110 if (target_mode == VOIDmode)
5111 target_mode = result_mode;
5113 target = gen_reg_rtx (target_mode);
5115 comparison = gen_rtx_fmt_ee (code, result_mode, x, y);
5117 create_output_operand (&ops[0], optimize ? NULL_RTX : target, result_mode);
5118 create_fixed_operand (&ops[1], comparison);
5119 create_fixed_operand (&ops[2], x);
5120 create_fixed_operand (&ops[3], y);
5121 if (!maybe_expand_insn (icode, 4, ops))
5123 delete_insns_since (last);
5126 subtarget = ops[0].value;
5128 /* If we are converting to a wider mode, first convert to
5129 TARGET_MODE, then normalize. This produces better combining
5130 opportunities on machines that have a SIGN_EXTRACT when we are
5131 testing a single bit. This mostly benefits the 68k.
5133 If STORE_FLAG_VALUE does not have the sign bit set when
5134 interpreted in MODE, we can do this conversion as unsigned, which
5135 is usually more efficient. */
5136 if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (result_mode))
5138 convert_move (target, subtarget,
5139 val_signbit_known_clear_p (result_mode,
5142 result_mode = target_mode;
5147 /* If we want to keep subexpressions around, don't reuse our last
5152 /* Now normalize to the proper value in MODE. Sometimes we don't
5153 have to do anything. */
5154 if (normalizep == 0 || normalizep == STORE_FLAG_VALUE)
5156 /* STORE_FLAG_VALUE might be the most negative number, so write
5157 the comparison this way to avoid a compiler-time warning. */
5158 else if (- normalizep == STORE_FLAG_VALUE)
5159 op0 = expand_unop (result_mode, neg_optab, op0, subtarget, 0);
5161 /* We don't want to use STORE_FLAG_VALUE < 0 below since this makes
5162 it hard to use a value of just the sign bit due to ANSI integer
5163 constant typing rules. */
5164 else if (val_signbit_known_set_p (result_mode, STORE_FLAG_VALUE))
5165 op0 = expand_shift (RSHIFT_EXPR, result_mode, op0,
5166 GET_MODE_BITSIZE (result_mode) - 1, subtarget,
5170 gcc_assert (STORE_FLAG_VALUE & 1);
5172 op0 = expand_and (result_mode, op0, const1_rtx, subtarget);
5173 if (normalizep == -1)
5174 op0 = expand_unop (result_mode, neg_optab, op0, op0, 0);
5177 /* If we were converting to a smaller mode, do the conversion now. */
5178 if (target_mode != result_mode)
5180 convert_move (target, op0, 0);
5188 /* A subroutine of emit_store_flag only including "tricks" that do not
5189 need a recursive call. These are kept separate to avoid infinite
5193 emit_store_flag_1 (rtx target, enum rtx_code code, rtx op0, rtx op1,
5194 enum machine_mode mode, int unsignedp, int normalizep,
5195 enum machine_mode target_mode)
5198 enum insn_code icode;
5199 enum machine_mode compare_mode;
5200 enum mode_class mclass;
5201 enum rtx_code scode;
5205 code = unsigned_condition (code);
5206 scode = swap_condition (code);
5208 /* If one operand is constant, make it the second one. Only do this
5209 if the other operand is not constant as well. */
5211 if (swap_commutative_operands_p (op0, op1))
5216 code = swap_condition (code);
5219 if (mode == VOIDmode)
5220 mode = GET_MODE (op0);
5222 /* For some comparisons with 1 and -1, we can convert this to
5223 comparisons with zero. This will often produce more opportunities for
5224 store-flag insns. */
5229 if (op1 == const1_rtx)
5230 op1 = const0_rtx, code = LE;
5233 if (op1 == constm1_rtx)
5234 op1 = const0_rtx, code = LT;
5237 if (op1 == const1_rtx)
5238 op1 = const0_rtx, code = GT;
5241 if (op1 == constm1_rtx)
5242 op1 = const0_rtx, code = GE;
5245 if (op1 == const1_rtx)
5246 op1 = const0_rtx, code = NE;
5249 if (op1 == const1_rtx)
5250 op1 = const0_rtx, code = EQ;
5256 /* If we are comparing a double-word integer with zero or -1, we can
5257 convert the comparison into one involving a single word. */
5258 if (GET_MODE_BITSIZE (mode) == BITS_PER_WORD * 2
5259 && GET_MODE_CLASS (mode) == MODE_INT
5260 && (!MEM_P (op0) || ! MEM_VOLATILE_P (op0)))
5262 if ((code == EQ || code == NE)
5263 && (op1 == const0_rtx || op1 == constm1_rtx))
5267 /* Do a logical OR or AND of the two words and compare the
5269 op00 = simplify_gen_subreg (word_mode, op0, mode, 0);
5270 op01 = simplify_gen_subreg (word_mode, op0, mode, UNITS_PER_WORD);
5271 tem = expand_binop (word_mode,
5272 op1 == const0_rtx ? ior_optab : and_optab,
5273 op00, op01, NULL_RTX, unsignedp,
5277 tem = emit_store_flag (NULL_RTX, code, tem, op1, word_mode,
5278 unsignedp, normalizep);
5280 else if ((code == LT || code == GE) && op1 == const0_rtx)
5284 /* If testing the sign bit, can just test on high word. */
5285 op0h = simplify_gen_subreg (word_mode, op0, mode,
5286 subreg_highpart_offset (word_mode,
5288 tem = emit_store_flag (NULL_RTX, code, op0h, op1, word_mode,
5289 unsignedp, normalizep);
5296 if (target_mode == VOIDmode || GET_MODE (tem) == target_mode)
5299 target = gen_reg_rtx (target_mode);
5301 convert_move (target, tem,
5302 !val_signbit_known_set_p (word_mode,
5303 (normalizep ? normalizep
5304 : STORE_FLAG_VALUE)));
5309 /* If this is A < 0 or A >= 0, we can do this by taking the ones
5310 complement of A (for GE) and shifting the sign bit to the low bit. */
5311 if (op1 == const0_rtx && (code == LT || code == GE)
5312 && GET_MODE_CLASS (mode) == MODE_INT
5313 && (normalizep || STORE_FLAG_VALUE == 1
5314 || val_signbit_p (mode, STORE_FLAG_VALUE)))
5321 /* If the result is to be wider than OP0, it is best to convert it
5322 first. If it is to be narrower, it is *incorrect* to convert it
5324 else if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (mode))
5326 op0 = convert_modes (target_mode, mode, op0, 0);
5330 if (target_mode != mode)
5334 op0 = expand_unop (mode, one_cmpl_optab, op0,
5335 ((STORE_FLAG_VALUE == 1 || normalizep)
5336 ? 0 : subtarget), 0);
5338 if (STORE_FLAG_VALUE == 1 || normalizep)
5339 /* If we are supposed to produce a 0/1 value, we want to do
5340 a logical shift from the sign bit to the low-order bit; for
5341 a -1/0 value, we do an arithmetic shift. */
5342 op0 = expand_shift (RSHIFT_EXPR, mode, op0,
5343 GET_MODE_BITSIZE (mode) - 1,
5344 subtarget, normalizep != -1);
5346 if (mode != target_mode)
5347 op0 = convert_modes (target_mode, mode, op0, 0);
5352 mclass = GET_MODE_CLASS (mode);
5353 for (compare_mode = mode; compare_mode != VOIDmode;
5354 compare_mode = GET_MODE_WIDER_MODE (compare_mode))
5356 enum machine_mode optab_mode = mclass == MODE_CC ? CCmode : compare_mode;
5357 icode = optab_handler (cstore_optab, optab_mode);
5358 if (icode != CODE_FOR_nothing)
5360 do_pending_stack_adjust ();
5361 tem = emit_cstore (target, icode, code, mode, compare_mode,
5362 unsignedp, op0, op1, normalizep, target_mode);
5366 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
5368 tem = emit_cstore (target, icode, scode, mode, compare_mode,
5369 unsignedp, op1, op0, normalizep, target_mode);
5380 /* Emit a store-flags instruction for comparison CODE on OP0 and OP1
5381 and storing in TARGET. Normally return TARGET.
5382 Return 0 if that cannot be done.
5384 MODE is the mode to use for OP0 and OP1 should they be CONST_INTs. If
5385 it is VOIDmode, they cannot both be CONST_INT.
5387 UNSIGNEDP is for the case where we have to widen the operands
5388 to perform the operation. It says to use zero-extension.
5390 NORMALIZEP is 1 if we should convert the result to be either zero
5391 or one. Normalize is -1 if we should convert the result to be
5392 either zero or -1. If NORMALIZEP is zero, the result will be left
5393 "raw" out of the scc insn. */
5396 emit_store_flag (rtx target, enum rtx_code code, rtx op0, rtx op1,
5397 enum machine_mode mode, int unsignedp, int normalizep)
5399 enum machine_mode target_mode = target ? GET_MODE (target) : VOIDmode;
5400 enum rtx_code rcode;
5402 rtx tem, last, trueval;
5404 tem = emit_store_flag_1 (target, code, op0, op1, mode, unsignedp, normalizep,
5409 /* If we reached here, we can't do this with a scc insn, however there
5410 are some comparisons that can be done in other ways. Don't do any
5411 of these cases if branches are very cheap. */
5412 if (BRANCH_COST (optimize_insn_for_speed_p (), false) == 0)
5415 /* See what we need to return. We can only return a 1, -1, or the
5418 if (normalizep == 0)
5420 if (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
5421 normalizep = STORE_FLAG_VALUE;
5423 else if (val_signbit_p (mode, STORE_FLAG_VALUE))
5429 last = get_last_insn ();
5431 /* If optimizing, use different pseudo registers for each insn, instead
5432 of reusing the same pseudo. This leads to better CSE, but slows
5433 down the compiler, since there are more pseudos */
5434 subtarget = (!optimize
5435 && (target_mode == mode)) ? target : NULL_RTX;
5436 trueval = GEN_INT (normalizep ? normalizep : STORE_FLAG_VALUE);
5438 /* For floating-point comparisons, try the reverse comparison or try
5439 changing the "orderedness" of the comparison. */
5440 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
5442 enum rtx_code first_code;
5445 rcode = reverse_condition_maybe_unordered (code);
5446 if (can_compare_p (rcode, mode, ccp_store_flag)
5447 && (code == ORDERED || code == UNORDERED
5448 || (! HONOR_NANS (mode) && (code == LTGT || code == UNEQ))
5449 || (! HONOR_SNANS (mode) && (code == EQ || code == NE))))
5451 int want_add = ((STORE_FLAG_VALUE == 1 && normalizep == -1)
5452 || (STORE_FLAG_VALUE == -1 && normalizep == 1));
5454 /* For the reverse comparison, use either an addition or a XOR. */
5456 && rtx_cost (GEN_INT (normalizep), PLUS, 1,
5457 optimize_insn_for_speed_p ()) == 0)
5459 tem = emit_store_flag_1 (subtarget, rcode, op0, op1, mode, 0,
5460 STORE_FLAG_VALUE, target_mode);
5462 return expand_binop (target_mode, add_optab, tem,
5463 GEN_INT (normalizep),
5464 target, 0, OPTAB_WIDEN);
5467 && rtx_cost (trueval, XOR, 1,
5468 optimize_insn_for_speed_p ()) == 0)
5470 tem = emit_store_flag_1 (subtarget, rcode, op0, op1, mode, 0,
5471 normalizep, target_mode);
5473 return expand_binop (target_mode, xor_optab, tem, trueval,
5474 target, INTVAL (trueval) >= 0, OPTAB_WIDEN);
5478 delete_insns_since (last);
5480 /* Cannot split ORDERED and UNORDERED, only try the above trick. */
5481 if (code == ORDERED || code == UNORDERED)
5484 and_them = split_comparison (code, mode, &first_code, &code);
5486 /* If there are no NaNs, the first comparison should always fall through.
5487 Effectively change the comparison to the other one. */
5488 if (!HONOR_NANS (mode))
5490 gcc_assert (first_code == (and_them ? ORDERED : UNORDERED));
5491 return emit_store_flag_1 (target, code, op0, op1, mode, 0, normalizep,
5495 #ifdef HAVE_conditional_move
5496 /* Try using a setcc instruction for ORDERED/UNORDERED, followed by a
5497 conditional move. */
5498 tem = emit_store_flag_1 (subtarget, first_code, op0, op1, mode, 0,
5499 normalizep, target_mode);
5504 tem = emit_conditional_move (target, code, op0, op1, mode,
5505 tem, const0_rtx, GET_MODE (tem), 0);
5507 tem = emit_conditional_move (target, code, op0, op1, mode,
5508 trueval, tem, GET_MODE (tem), 0);
5511 delete_insns_since (last);
5518 /* The remaining tricks only apply to integer comparisons. */
5520 if (GET_MODE_CLASS (mode) != MODE_INT)
5523 /* If this is an equality comparison of integers, we can try to exclusive-or
5524 (or subtract) the two operands and use a recursive call to try the
5525 comparison with zero. Don't do any of these cases if branches are
5528 if ((code == EQ || code == NE) && op1 != const0_rtx)
5530 tem = expand_binop (mode, xor_optab, op0, op1, subtarget, 1,
5534 tem = expand_binop (mode, sub_optab, op0, op1, subtarget, 1,
5537 tem = emit_store_flag (target, code, tem, const0_rtx,
5538 mode, unsignedp, normalizep);
5542 delete_insns_since (last);
5545 /* For integer comparisons, try the reverse comparison. However, for
5546 small X and if we'd have anyway to extend, implementing "X != 0"
5547 as "-(int)X >> 31" is still cheaper than inverting "(int)X == 0". */
5548 rcode = reverse_condition (code);
5549 if (can_compare_p (rcode, mode, ccp_store_flag)
5550 && ! (optab_handler (cstore_optab, mode) == CODE_FOR_nothing
5552 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
5553 && op1 == const0_rtx))
5555 int want_add = ((STORE_FLAG_VALUE == 1 && normalizep == -1)
5556 || (STORE_FLAG_VALUE == -1 && normalizep == 1));
5558 /* Again, for the reverse comparison, use either an addition or a XOR. */
5560 && rtx_cost (GEN_INT (normalizep), PLUS, 1,
5561 optimize_insn_for_speed_p ()) == 0)
5563 tem = emit_store_flag_1 (subtarget, rcode, op0, op1, mode, 0,
5564 STORE_FLAG_VALUE, target_mode);
5566 tem = expand_binop (target_mode, add_optab, tem,
5567 GEN_INT (normalizep), target, 0, OPTAB_WIDEN);
5570 && rtx_cost (trueval, XOR, 1,
5571 optimize_insn_for_speed_p ()) == 0)
5573 tem = emit_store_flag_1 (subtarget, rcode, op0, op1, mode, 0,
5574 normalizep, target_mode);
5576 tem = expand_binop (target_mode, xor_optab, tem, trueval, target,
5577 INTVAL (trueval) >= 0, OPTAB_WIDEN);
5582 delete_insns_since (last);
5585 /* Some other cases we can do are EQ, NE, LE, and GT comparisons with
5586 the constant zero. Reject all other comparisons at this point. Only
5587 do LE and GT if branches are expensive since they are expensive on
5588 2-operand machines. */
5590 if (op1 != const0_rtx
5591 || (code != EQ && code != NE
5592 && (BRANCH_COST (optimize_insn_for_speed_p (),
5593 false) <= 1 || (code != LE && code != GT))))
5596 /* Try to put the result of the comparison in the sign bit. Assume we can't
5597 do the necessary operation below. */
5601 /* To see if A <= 0, compute (A | (A - 1)). A <= 0 iff that result has
5602 the sign bit set. */
5606 /* This is destructive, so SUBTARGET can't be OP0. */
5607 if (rtx_equal_p (subtarget, op0))
5610 tem = expand_binop (mode, sub_optab, op0, const1_rtx, subtarget, 0,
5613 tem = expand_binop (mode, ior_optab, op0, tem, subtarget, 0,
5617 /* To see if A > 0, compute (((signed) A) << BITS) - A, where BITS is the
5618 number of bits in the mode of OP0, minus one. */
5622 if (rtx_equal_p (subtarget, op0))
5625 tem = expand_shift (RSHIFT_EXPR, mode, op0,
5626 GET_MODE_BITSIZE (mode) - 1,
5628 tem = expand_binop (mode, sub_optab, tem, op0, subtarget, 0,
5632 if (code == EQ || code == NE)
5634 /* For EQ or NE, one way to do the comparison is to apply an operation
5635 that converts the operand into a positive number if it is nonzero
5636 or zero if it was originally zero. Then, for EQ, we subtract 1 and
5637 for NE we negate. This puts the result in the sign bit. Then we
5638 normalize with a shift, if needed.
5640 Two operations that can do the above actions are ABS and FFS, so try
5641 them. If that doesn't work, and MODE is smaller than a full word,
5642 we can use zero-extension to the wider mode (an unsigned conversion)
5643 as the operation. */
5645 /* Note that ABS doesn't yield a positive number for INT_MIN, but
5646 that is compensated by the subsequent overflow when subtracting
5649 if (optab_handler (abs_optab, mode) != CODE_FOR_nothing)
5650 tem = expand_unop (mode, abs_optab, op0, subtarget, 1);
5651 else if (optab_handler (ffs_optab, mode) != CODE_FOR_nothing)
5652 tem = expand_unop (mode, ffs_optab, op0, subtarget, 1);
5653 else if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
5655 tem = convert_modes (word_mode, mode, op0, 1);
5662 tem = expand_binop (mode, sub_optab, tem, const1_rtx, subtarget,
5665 tem = expand_unop (mode, neg_optab, tem, subtarget, 0);
5668 /* If we couldn't do it that way, for NE we can "or" the two's complement
5669 of the value with itself. For EQ, we take the one's complement of
5670 that "or", which is an extra insn, so we only handle EQ if branches
5675 || BRANCH_COST (optimize_insn_for_speed_p (),
5678 if (rtx_equal_p (subtarget, op0))
5681 tem = expand_unop (mode, neg_optab, op0, subtarget, 0);
5682 tem = expand_binop (mode, ior_optab, tem, op0, subtarget, 0,
5685 if (tem && code == EQ)
5686 tem = expand_unop (mode, one_cmpl_optab, tem, subtarget, 0);
5690 if (tem && normalizep)
5691 tem = expand_shift (RSHIFT_EXPR, mode, tem,
5692 GET_MODE_BITSIZE (mode) - 1,
5693 subtarget, normalizep == 1);
5699 else if (GET_MODE (tem) != target_mode)
5701 convert_move (target, tem, 0);
5704 else if (!subtarget)
5706 emit_move_insn (target, tem);
5711 delete_insns_since (last);
5716 /* Like emit_store_flag, but always succeeds. */
5719 emit_store_flag_force (rtx target, enum rtx_code code, rtx op0, rtx op1,
5720 enum machine_mode mode, int unsignedp, int normalizep)
5723 rtx trueval, falseval;
5725 /* First see if emit_store_flag can do the job. */
5726 tem = emit_store_flag (target, code, op0, op1, mode, unsignedp, normalizep);
5731 target = gen_reg_rtx (word_mode);
5733 /* If this failed, we have to do this with set/compare/jump/set code.
5734 For foo != 0, if foo is in OP0, just replace it with 1 if nonzero. */
5735 trueval = normalizep ? GEN_INT (normalizep) : const1_rtx;
5737 && GET_MODE_CLASS (mode) == MODE_INT
5740 && op1 == const0_rtx)
5742 label = gen_label_rtx ();
5743 do_compare_rtx_and_jump (target, const0_rtx, EQ, unsignedp,
5744 mode, NULL_RTX, NULL_RTX, label, -1);
5745 emit_move_insn (target, trueval);
5751 || reg_mentioned_p (target, op0) || reg_mentioned_p (target, op1))
5752 target = gen_reg_rtx (GET_MODE (target));
5754 /* Jump in the right direction if the target cannot implement CODE
5755 but can jump on its reverse condition. */
5756 falseval = const0_rtx;
5757 if (! can_compare_p (code, mode, ccp_jump)
5758 && (! FLOAT_MODE_P (mode)
5759 || code == ORDERED || code == UNORDERED
5760 || (! HONOR_NANS (mode) && (code == LTGT || code == UNEQ))
5761 || (! HONOR_SNANS (mode) && (code == EQ || code == NE))))
5763 enum rtx_code rcode;
5764 if (FLOAT_MODE_P (mode))
5765 rcode = reverse_condition_maybe_unordered (code);
5767 rcode = reverse_condition (code);
5769 /* Canonicalize to UNORDERED for the libcall. */
5770 if (can_compare_p (rcode, mode, ccp_jump)
5771 || (code == ORDERED && ! can_compare_p (ORDERED, mode, ccp_jump)))
5774 trueval = const0_rtx;
5779 emit_move_insn (target, trueval);
5780 label = gen_label_rtx ();
5781 do_compare_rtx_and_jump (op0, op1, code, unsignedp, mode, NULL_RTX,
5782 NULL_RTX, label, -1);
5784 emit_move_insn (target, falseval);
5790 /* Perform possibly multi-word comparison and conditional jump to LABEL
5791 if ARG1 OP ARG2 true where ARG1 and ARG2 are of mode MODE. This is
5792 now a thin wrapper around do_compare_rtx_and_jump. */
5795 do_cmp_and_jump (rtx arg1, rtx arg2, enum rtx_code op, enum machine_mode mode,
5798 int unsignedp = (op == LTU || op == LEU || op == GTU || op == GEU);
5799 do_compare_rtx_and_jump (arg1, arg2, op, unsignedp, mode,
5800 NULL_RTX, NULL_RTX, label, -1);