1 /* Medium-level subroutines: convert bit-field store and extract
2 and shifts, multiplies and divides to rtl instructions.
3 Copyright (C) 1987, 88, 89, 92, 93, 94, 1995 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
26 #include "insn-flags.h"
27 #include "insn-codes.h"
28 #include "insn-config.h"
33 static void store_fixed_bit_field PROTO((rtx, int, int, int, rtx, int));
34 static void store_split_bit_field PROTO((rtx, int, int, rtx, int));
35 static rtx extract_fixed_bit_field PROTO((enum machine_mode, rtx, int,
36 int, int, rtx, int, int));
37 static rtx mask_rtx PROTO((enum machine_mode, int,
39 static rtx lshift_value PROTO((enum machine_mode, rtx,
41 static rtx extract_split_bit_field PROTO((rtx, int, int, int, int));
43 #define CEIL(x,y) (((x) + (y) - 1) / (y))
45 /* Non-zero means divides or modulus operations are relatively cheap for
46 powers of two, so don't use branches; emit the operation instead.
47 Usually, this will mean that the MD file will emit non-branch
50 static int sdiv_pow2_cheap, smod_pow2_cheap;
52 #ifndef SLOW_UNALIGNED_ACCESS
53 #define SLOW_UNALIGNED_ACCESS STRICT_ALIGNMENT
56 /* For compilers that support multiple targets with different word sizes,
57 MAX_BITS_PER_WORD contains the biggest value of BITS_PER_WORD. An example
58 is the H8/300(H) compiler. */
60 #ifndef MAX_BITS_PER_WORD
61 #define MAX_BITS_PER_WORD BITS_PER_WORD
64 /* Cost of various pieces of RTL. Note that some of these are indexed by shift count,
66 static int add_cost, negate_cost, zero_cost;
67 static int shift_cost[MAX_BITS_PER_WORD];
68 static int shiftadd_cost[MAX_BITS_PER_WORD];
69 static int shiftsub_cost[MAX_BITS_PER_WORD];
70 static int mul_cost[NUM_MACHINE_MODES];
71 static int div_cost[NUM_MACHINE_MODES];
72 static int mul_widen_cost[NUM_MACHINE_MODES];
73 static int mul_highpart_cost[NUM_MACHINE_MODES];
79 /* This is "some random pseudo register" for purposes of calling recog
80 to see what insns exist. */
81 rtx reg = gen_rtx (REG, word_mode, 10000);
82 rtx shift_insn, shiftadd_insn, shiftsub_insn;
85 enum machine_mode mode, wider_mode;
89 /* Since we are on the permanent obstack, we must be sure we save this
90 spot AFTER we call start_sequence, since it will reuse the rtl it
93 free_point = (char *) oballoc (0);
95 zero_cost = rtx_cost (const0_rtx, 0);
96 add_cost = rtx_cost (gen_rtx (PLUS, word_mode, reg, reg), SET);
98 shift_insn = emit_insn (gen_rtx (SET, VOIDmode, reg,
99 gen_rtx (ASHIFT, word_mode, reg,
102 shiftadd_insn = emit_insn (gen_rtx (SET, VOIDmode, reg,
103 gen_rtx (PLUS, word_mode,
104 gen_rtx (MULT, word_mode,
108 shiftsub_insn = emit_insn (gen_rtx (SET, VOIDmode, reg,
109 gen_rtx (MINUS, word_mode,
110 gen_rtx (MULT, word_mode,
117 shiftadd_cost[0] = shiftsub_cost[0] = add_cost;
119 for (m = 1; m < BITS_PER_WORD; m++)
121 shift_cost[m] = shiftadd_cost[m] = shiftsub_cost[m] = 32000;
123 XEXP (SET_SRC (PATTERN (shift_insn)), 1) = GEN_INT (m);
124 if (recog (PATTERN (shift_insn), shift_insn, &dummy) >= 0)
125 shift_cost[m] = rtx_cost (SET_SRC (PATTERN (shift_insn)), SET);
127 XEXP (XEXP (SET_SRC (PATTERN (shiftadd_insn)), 0), 1)
128 = GEN_INT ((HOST_WIDE_INT) 1 << m);
129 if (recog (PATTERN (shiftadd_insn), shiftadd_insn, &dummy) >= 0)
130 shiftadd_cost[m] = rtx_cost (SET_SRC (PATTERN (shiftadd_insn)), SET);
132 XEXP (XEXP (SET_SRC (PATTERN (shiftsub_insn)), 0), 1)
133 = GEN_INT ((HOST_WIDE_INT) 1 << m);
134 if (recog (PATTERN (shiftsub_insn), shiftsub_insn, &dummy) >= 0)
135 shiftsub_cost[m] = rtx_cost (SET_SRC (PATTERN (shiftsub_insn)), SET);
138 negate_cost = rtx_cost (gen_rtx (NEG, word_mode, reg), SET);
141 = (rtx_cost (gen_rtx (DIV, word_mode, reg, GEN_INT (32)), SET)
144 = (rtx_cost (gen_rtx (MOD, word_mode, reg, GEN_INT (32)), SET)
147 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
149 mode = GET_MODE_WIDER_MODE (mode))
151 reg = gen_rtx (REG, mode, 10000);
152 div_cost[(int) mode] = rtx_cost (gen_rtx (UDIV, mode, reg, reg), SET);
153 mul_cost[(int) mode] = rtx_cost (gen_rtx (MULT, mode, reg, reg), SET);
154 wider_mode = GET_MODE_WIDER_MODE (mode);
155 if (wider_mode != VOIDmode)
157 mul_widen_cost[(int) wider_mode]
158 = rtx_cost (gen_rtx (MULT, wider_mode,
159 gen_rtx (ZERO_EXTEND, wider_mode, reg),
160 gen_rtx (ZERO_EXTEND, wider_mode, reg)),
162 mul_highpart_cost[(int) mode]
163 = rtx_cost (gen_rtx (TRUNCATE, mode,
164 gen_rtx (LSHIFTRT, wider_mode,
165 gen_rtx (MULT, wider_mode,
166 gen_rtx (ZERO_EXTEND, wider_mode, reg),
167 gen_rtx (ZERO_EXTEND, wider_mode, reg)),
168 GEN_INT (GET_MODE_BITSIZE (mode)))),
173 /* Free the objects we just allocated. */
178 /* Return an rtx representing minus the value of X.
179 MODE is the intended mode of the result,
180 useful if X is a CONST_INT. */
184 enum machine_mode mode;
187 if (GET_CODE (x) == CONST_INT)
189 HOST_WIDE_INT val = - INTVAL (x);
190 if (GET_MODE_BITSIZE (mode) < HOST_BITS_PER_WIDE_INT)
192 /* Sign extend the value from the bits that are significant. */
193 if (val & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1)))
194 val |= (HOST_WIDE_INT) (-1) << GET_MODE_BITSIZE (mode);
196 val &= ((HOST_WIDE_INT) 1 << GET_MODE_BITSIZE (mode)) - 1;
198 return GEN_INT (val);
201 return expand_unop (GET_MODE (x), neg_optab, x, NULL_RTX, 0);
204 /* Generate code to store value from rtx VALUE
205 into a bit-field within structure STR_RTX
206 containing BITSIZE bits starting at bit BITNUM.
207 FIELDMODE is the machine-mode of the FIELD_DECL node for this field.
208 ALIGN is the alignment that STR_RTX is known to have, measured in bytes.
209 TOTAL_SIZE is the size of the structure in bytes, or -1 if varying. */
211 /* ??? Note that there are two different ideas here for how
212 to determine the size to count bits within, for a register.
213 One is BITS_PER_WORD, and the other is the size of operand 3
214 of the insv pattern. (The latter assumes that an n-bit machine
215 will be able to insert bit fields up to n bits wide.)
216 It isn't certain that either of these is right.
217 extract_bit_field has the same quandary. */
220 store_bit_field (str_rtx, bitsize, bitnum, fieldmode, value, align, total_size)
222 register int bitsize;
224 enum machine_mode fieldmode;
229 int unit = (GET_CODE (str_rtx) == MEM) ? BITS_PER_UNIT : BITS_PER_WORD;
230 register int offset = bitnum / unit;
231 register int bitpos = bitnum % unit;
232 register rtx op0 = str_rtx;
234 if (GET_CODE (str_rtx) == MEM && ! MEM_IN_STRUCT_P (str_rtx))
237 /* Discount the part of the structure before the desired byte.
238 We need to know how many bytes are safe to reference after it. */
240 total_size -= (bitpos / BIGGEST_ALIGNMENT
241 * (BIGGEST_ALIGNMENT / BITS_PER_UNIT));
243 while (GET_CODE (op0) == SUBREG)
245 /* The following line once was done only if WORDS_BIG_ENDIAN,
246 but I think that is a mistake. WORDS_BIG_ENDIAN is
247 meaningful at a much higher level; when structures are copied
248 between memory and regs, the higher-numbered regs
249 always get higher addresses. */
250 offset += SUBREG_WORD (op0);
251 /* We used to adjust BITPOS here, but now we do the whole adjustment
252 right after the loop. */
253 op0 = SUBREG_REG (op0);
256 /* If OP0 is a register, BITPOS must count within a word.
257 But as we have it, it counts within whatever size OP0 now has.
258 On a bigendian machine, these are not the same, so convert. */
260 && GET_CODE (op0) != MEM
261 && unit > GET_MODE_BITSIZE (GET_MODE (op0)))
262 bitpos += unit - GET_MODE_BITSIZE (GET_MODE (op0));
264 value = protect_from_queue (value, 0);
267 value = force_not_mem (value);
269 /* Note that the adjustment of BITPOS above has no effect on whether
270 BITPOS is 0 in a REG bigger than a word. */
271 if (GET_MODE_SIZE (fieldmode) >= UNITS_PER_WORD
272 && (GET_CODE (op0) != MEM
273 || ! SLOW_UNALIGNED_ACCESS
274 || (offset * BITS_PER_UNIT % bitsize == 0
275 && align % GET_MODE_SIZE (fieldmode) == 0))
276 && bitpos == 0 && bitsize == GET_MODE_BITSIZE (fieldmode))
278 /* Storing in a full-word or multi-word field in a register
279 can be done with just SUBREG. */
280 if (GET_MODE (op0) != fieldmode)
282 if (GET_CODE (op0) == REG)
283 op0 = gen_rtx (SUBREG, fieldmode, op0, offset);
285 op0 = change_address (op0, fieldmode,
286 plus_constant (XEXP (op0, 0), offset));
288 emit_move_insn (op0, value);
292 /* Storing an lsb-aligned field in a register
293 can be done with a movestrict instruction. */
295 if (GET_CODE (op0) != MEM
296 && (BYTES_BIG_ENDIAN ? bitpos + bitsize == unit : bitpos == 0)
297 && bitsize == GET_MODE_BITSIZE (fieldmode)
298 && (GET_MODE (op0) == fieldmode
299 || (movstrict_optab->handlers[(int) fieldmode].insn_code
300 != CODE_FOR_nothing)))
302 /* Get appropriate low part of the value being stored. */
303 if (GET_CODE (value) == CONST_INT || GET_CODE (value) == REG)
304 value = gen_lowpart (fieldmode, value);
305 else if (!(GET_CODE (value) == SYMBOL_REF
306 || GET_CODE (value) == LABEL_REF
307 || GET_CODE (value) == CONST))
308 value = convert_to_mode (fieldmode, value, 0);
310 if (GET_MODE (op0) == fieldmode)
311 emit_move_insn (op0, value);
314 int icode = movstrict_optab->handlers[(int) fieldmode].insn_code;
315 if(! (*insn_operand_predicate[icode][1]) (value, fieldmode))
316 value = copy_to_mode_reg (fieldmode, value);
317 emit_insn (GEN_FCN (icode)
318 (gen_rtx (SUBREG, fieldmode, op0, offset), value));
323 /* Handle fields bigger than a word. */
325 if (bitsize > BITS_PER_WORD)
327 /* Here we transfer the words of the field
328 in the order least significant first.
329 This is because the most significant word is the one which may
331 However, only do that if the value is not BLKmode. */
333 int backwards = WORDS_BIG_ENDIAN && fieldmode != BLKmode;
335 int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD;
338 /* This is the mode we must force value to, so that there will be enough
339 subwords to extract. Note that fieldmode will often (always?) be
340 VOIDmode, because that is what store_field uses to indicate that this
341 is a bit field, but passing VOIDmode to operand_subword_force will
342 result in an abort. */
343 fieldmode = mode_for_size (nwords * BITS_PER_WORD, MODE_INT, 0);
345 for (i = 0; i < nwords; i++)
347 /* If I is 0, use the low-order word in both field and target;
348 if I is 1, use the next to lowest word; and so on. */
349 int wordnum = (backwards ? nwords - i - 1 : i);
350 int bit_offset = (backwards
351 ? MAX (bitsize - (i + 1) * BITS_PER_WORD, 0)
352 : i * BITS_PER_WORD);
353 store_bit_field (op0, MIN (BITS_PER_WORD,
354 bitsize - i * BITS_PER_WORD),
355 bitnum + bit_offset, word_mode,
356 operand_subword_force (value, wordnum,
357 (GET_MODE (value) == VOIDmode
359 : GET_MODE (value))),
365 /* From here on we can assume that the field to be stored in is
366 a full-word (whatever type that is), since it is shorter than a word. */
368 /* OFFSET is the number of words or bytes (UNIT says which)
369 from STR_RTX to the first word or byte containing part of the field. */
371 if (GET_CODE (op0) == REG)
374 || GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD)
375 op0 = gen_rtx (SUBREG, TYPE_MODE (type_for_size (BITS_PER_WORD, 0)),
381 op0 = protect_from_queue (op0, 1);
384 /* If VALUE is a floating-point mode, access it as an integer of the
385 corresponding size. This can occur on a machine with 64 bit registers
386 that uses SFmode for float. This can also occur for unaligned float
388 if (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT)
390 if (GET_CODE (value) != REG)
391 value = copy_to_reg (value);
392 value = gen_rtx (SUBREG, word_mode, value, 0);
395 /* Now OFFSET is nonzero only if OP0 is memory
396 and is therefore always measured in bytes. */
400 && !(bitsize == 1 && GET_CODE (value) == CONST_INT)
401 /* Ensure insv's size is wide enough for this field. */
402 && (GET_MODE_BITSIZE (insn_operand_mode[(int) CODE_FOR_insv][3])
404 && ! ((GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
406 > GET_MODE_BITSIZE (insn_operand_mode[(int) CODE_FOR_insv][3]))))
408 int xbitpos = bitpos;
411 rtx last = get_last_insn ();
413 enum machine_mode maxmode
414 = insn_operand_mode[(int) CODE_FOR_insv][3];
416 int save_volatile_ok = volatile_ok;
419 /* If this machine's insv can only insert into a register, or if we
420 are to force MEMs into a register, copy OP0 into a register and
421 save it back later. */
422 if (GET_CODE (op0) == MEM
424 || ! ((*insn_operand_predicate[(int) CODE_FOR_insv][0])
428 enum machine_mode bestmode;
430 /* Get the mode to use for inserting into this field. If OP0 is
431 BLKmode, get the smallest mode consistent with the alignment. If
432 OP0 is a non-BLKmode object that is no wider than MAXMODE, use its
433 mode. Otherwise, use the smallest mode containing the field. */
435 if (GET_MODE (op0) == BLKmode
436 || GET_MODE_SIZE (GET_MODE (op0)) > GET_MODE_SIZE (maxmode))
438 = get_best_mode (bitsize, bitnum, align * BITS_PER_UNIT, maxmode,
439 MEM_VOLATILE_P (op0));
441 bestmode = GET_MODE (op0);
443 if (bestmode == VOIDmode
444 || (SLOW_UNALIGNED_ACCESS && GET_MODE_SIZE (bestmode) > align))
447 /* Adjust address to point to the containing unit of that mode. */
448 unit = GET_MODE_BITSIZE (bestmode);
449 /* Compute offset as multiple of this unit, counting in bytes. */
450 offset = (bitnum / unit) * GET_MODE_SIZE (bestmode);
451 bitpos = bitnum % unit;
452 op0 = change_address (op0, bestmode,
453 plus_constant (XEXP (op0, 0), offset));
455 /* Fetch that unit, store the bitfield in it, then store the unit. */
456 tempreg = copy_to_reg (op0);
457 store_bit_field (tempreg, bitsize, bitpos, fieldmode, value,
459 emit_move_insn (op0, tempreg);
462 volatile_ok = save_volatile_ok;
464 /* Add OFFSET into OP0's address. */
465 if (GET_CODE (xop0) == MEM)
466 xop0 = change_address (xop0, byte_mode,
467 plus_constant (XEXP (xop0, 0), offset));
469 /* If xop0 is a register, we need it in MAXMODE
470 to make it acceptable to the format of insv. */
471 if (GET_CODE (xop0) == SUBREG)
472 /* We can't just change the mode, because this might clobber op0,
473 and we will need the original value of op0 if insv fails. */
474 xop0 = gen_rtx (SUBREG, maxmode, SUBREG_REG (xop0), SUBREG_WORD (xop0));
475 if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode)
476 xop0 = gen_rtx (SUBREG, maxmode, xop0, 0);
478 /* On big-endian machines, we count bits from the most significant.
479 If the bit field insn does not, we must invert. */
481 if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
482 xbitpos = unit - bitsize - xbitpos;
484 /* We have been counting XBITPOS within UNIT.
485 Count instead within the size of the register. */
486 if (BITS_BIG_ENDIAN && GET_CODE (xop0) != MEM)
487 xbitpos += GET_MODE_BITSIZE (maxmode) - unit;
489 unit = GET_MODE_BITSIZE (maxmode);
491 /* Convert VALUE to maxmode (which insv insn wants) in VALUE1. */
493 if (GET_MODE (value) != maxmode)
495 if (GET_MODE_BITSIZE (GET_MODE (value)) >= bitsize)
497 /* Optimization: Don't bother really extending VALUE
498 if it has all the bits we will actually use. However,
499 if we must narrow it, be sure we do it correctly. */
501 if (GET_MODE_SIZE (GET_MODE (value)) < GET_MODE_SIZE (maxmode))
503 /* Avoid making subreg of a subreg, or of a mem. */
504 if (GET_CODE (value1) != REG)
505 value1 = copy_to_reg (value1);
506 value1 = gen_rtx (SUBREG, maxmode, value1, 0);
509 value1 = gen_lowpart (maxmode, value1);
511 else if (!CONSTANT_P (value))
512 /* Parse phase is supposed to make VALUE's data type
513 match that of the component reference, which is a type
514 at least as wide as the field; so VALUE should have
515 a mode that corresponds to that type. */
519 /* If this machine's insv insists on a register,
520 get VALUE1 into a register. */
521 if (! ((*insn_operand_predicate[(int) CODE_FOR_insv][3])
523 value1 = force_reg (maxmode, value1);
525 pat = gen_insv (xop0, GEN_INT (bitsize), GEN_INT (xbitpos), value1);
530 delete_insns_since (last);
531 store_fixed_bit_field (op0, offset, bitsize, bitpos, value, align);
537 /* Insv is not available; store using shifts and boolean ops. */
538 store_fixed_bit_field (op0, offset, bitsize, bitpos, value, align);
542 /* Use shifts and boolean operations to store VALUE
543 into a bit field of width BITSIZE
544 in a memory location specified by OP0 except offset by OFFSET bytes.
545 (OFFSET must be 0 if OP0 is a register.)
546 The field starts at position BITPOS within the byte.
547 (If OP0 is a register, it may be a full word or a narrower mode,
548 but BITPOS still counts within a full word,
549 which is significant on bigendian machines.)
550 STRUCT_ALIGN is the alignment the structure is known to have (in bytes).
552 Note that protect_from_queue has already been done on OP0 and VALUE. */
555 store_fixed_bit_field (op0, offset, bitsize, bitpos, value, struct_align)
557 register int offset, bitsize, bitpos;
561 register enum machine_mode mode;
562 int total_bits = BITS_PER_WORD;
567 /* There is a case not handled here:
568 a structure with a known alignment of just a halfword
569 and a field split across two aligned halfwords within the structure.
570 Or likewise a structure with a known alignment of just a byte
571 and a field split across two bytes.
572 Such cases are not supposed to be able to occur. */
574 if (GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
578 /* Special treatment for a bit field split across two registers. */
579 if (bitsize + bitpos > BITS_PER_WORD)
581 store_split_bit_field (op0, bitsize, bitpos,
582 value, BITS_PER_WORD);
588 /* Get the proper mode to use for this field. We want a mode that
589 includes the entire field. If such a mode would be larger than
590 a word, we won't be doing the extraction the normal way. */
592 mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT,
593 struct_align * BITS_PER_UNIT, word_mode,
594 GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0));
596 if (mode == VOIDmode)
598 /* The only way this should occur is if the field spans word
600 store_split_bit_field (op0,
601 bitsize, bitpos + offset * BITS_PER_UNIT,
602 value, struct_align);
606 total_bits = GET_MODE_BITSIZE (mode);
608 /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to
609 be be in the range 0 to total_bits-1, and put any excess bytes in
611 if (bitpos >= total_bits)
613 offset += (bitpos / total_bits) * (total_bits / BITS_PER_UNIT);
614 bitpos -= ((bitpos / total_bits) * (total_bits / BITS_PER_UNIT)
618 /* Get ref to an aligned byte, halfword, or word containing the field.
619 Adjust BITPOS to be position within a word,
620 and OFFSET to be the offset of that word.
621 Then alter OP0 to refer to that word. */
622 bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT;
623 offset -= (offset % (total_bits / BITS_PER_UNIT));
624 op0 = change_address (op0, mode,
625 plus_constant (XEXP (op0, 0), offset));
628 mode = GET_MODE (op0);
630 /* Now MODE is either some integral mode for a MEM as OP0,
631 or is a full-word for a REG as OP0. TOTAL_BITS corresponds.
632 The bit field is contained entirely within OP0.
633 BITPOS is the starting bit number within OP0.
634 (OP0's mode may actually be narrower than MODE.) */
636 if (BYTES_BIG_ENDIAN)
637 /* BITPOS is the distance between our msb
638 and that of the containing datum.
639 Convert it to the distance from the lsb. */
640 bitpos = total_bits - bitsize - bitpos;
642 /* Now BITPOS is always the distance between our lsb
645 /* Shift VALUE left by BITPOS bits. If VALUE is not constant,
646 we must first convert its mode to MODE. */
648 if (GET_CODE (value) == CONST_INT)
650 register HOST_WIDE_INT v = INTVAL (value);
652 if (bitsize < HOST_BITS_PER_WIDE_INT)
653 v &= ((HOST_WIDE_INT) 1 << bitsize) - 1;
657 else if ((bitsize < HOST_BITS_PER_WIDE_INT
658 && v == ((HOST_WIDE_INT) 1 << bitsize) - 1)
659 || (bitsize == HOST_BITS_PER_WIDE_INT && v == -1))
662 value = lshift_value (mode, value, bitpos, bitsize);
666 int must_and = (GET_MODE_BITSIZE (GET_MODE (value)) != bitsize
667 && bitpos + bitsize != GET_MODE_BITSIZE (mode));
669 if (GET_MODE (value) != mode)
671 if ((GET_CODE (value) == REG || GET_CODE (value) == SUBREG)
672 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (value)))
673 value = gen_lowpart (mode, value);
675 value = convert_to_mode (mode, value, 1);
679 value = expand_binop (mode, and_optab, value,
680 mask_rtx (mode, 0, bitsize, 0),
681 NULL_RTX, 1, OPTAB_LIB_WIDEN);
683 value = expand_shift (LSHIFT_EXPR, mode, value,
684 build_int_2 (bitpos, 0), NULL_RTX, 1);
687 /* Now clear the chosen bits in OP0,
688 except that if VALUE is -1 we need not bother. */
690 subtarget = (GET_CODE (op0) == REG || ! flag_force_mem) ? op0 : 0;
694 temp = expand_binop (mode, and_optab, op0,
695 mask_rtx (mode, bitpos, bitsize, 1),
696 subtarget, 1, OPTAB_LIB_WIDEN);
702 /* Now logical-or VALUE into OP0, unless it is zero. */
705 temp = expand_binop (mode, ior_optab, temp, value,
706 subtarget, 1, OPTAB_LIB_WIDEN);
708 emit_move_insn (op0, temp);
711 /* Store a bit field that is split across multiple accessible memory objects.
713 OP0 is the REG, SUBREG or MEM rtx for the first of the objects.
714 BITSIZE is the field width; BITPOS the position of its first bit
716 VALUE is the value to store.
717 ALIGN is the known alignment of OP0, measured in bytes.
718 This is also the size of the memory objects to be used.
720 This does not yet handle fields wider than BITS_PER_WORD. */
723 store_split_bit_field (op0, bitsize, bitpos, value, align)
732 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
734 if (GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
735 unit = BITS_PER_WORD;
737 unit = MIN (align * BITS_PER_UNIT, BITS_PER_WORD);
739 /* If VALUE is a constant other than a CONST_INT, get it into a register in
740 WORD_MODE. If we can do this using gen_lowpart_common, do so. Note
741 that VALUE might be a floating-point constant. */
742 if (CONSTANT_P (value) && GET_CODE (value) != CONST_INT)
744 rtx word = gen_lowpart_common (word_mode, value);
746 if (word && (value != word))
749 value = gen_lowpart_common (word_mode,
750 force_reg (GET_MODE (value) != VOIDmode
752 : word_mode, value));
755 while (bitsdone < bitsize)
762 offset = (bitpos + bitsdone) / unit;
763 thispos = (bitpos + bitsdone) % unit;
765 /* THISSIZE must not overrun a word boundary. Otherwise,
766 store_fixed_bit_field will call us again, and we will mutually
768 thissize = MIN (bitsize - bitsdone, BITS_PER_WORD);
769 thissize = MIN (thissize, unit - thispos);
771 if (BYTES_BIG_ENDIAN)
775 /* We must do an endian conversion exactly the same way as it is
776 done in extract_bit_field, so that the two calls to
777 extract_fixed_bit_field will have comparable arguments. */
778 if (GET_CODE (value) != MEM)
779 total_bits = BITS_PER_WORD;
781 total_bits = GET_MODE_BITSIZE (GET_MODE (value));
783 /* Fetch successively less significant portions. */
784 if (GET_CODE (value) == CONST_INT)
785 part = GEN_INT (((unsigned HOST_WIDE_INT) (INTVAL (value))
786 >> (bitsize - bitsdone - thissize))
787 & (((HOST_WIDE_INT) 1 << thissize) - 1));
789 /* The args are chosen so that the last part includes the
790 lsb. Give extract_bit_field the value it needs (with
791 endianness compensation) to fetch the piece we want. */
792 part = extract_fixed_bit_field (word_mode, value, 0, thissize,
793 total_bits - bitsize + bitsdone,
798 /* Fetch successively more significant portions. */
799 if (GET_CODE (value) == CONST_INT)
800 part = GEN_INT (((unsigned HOST_WIDE_INT) (INTVAL (value))
802 & (((HOST_WIDE_INT) 1 << thissize) - 1));
804 part = extract_fixed_bit_field (word_mode, value, 0, thissize,
805 bitsdone, NULL_RTX, 1, align);
808 /* If OP0 is a register, then handle OFFSET here.
810 When handling multiword bitfields, extract_bit_field may pass
811 down a word_mode SUBREG of a larger REG for a bitfield that actually
812 crosses a word boundary. Thus, for a SUBREG, we must find
813 the current word starting from the base register. */
814 if (GET_CODE (op0) == SUBREG)
816 word = operand_subword_force (SUBREG_REG (op0),
817 SUBREG_WORD (op0) + offset,
818 GET_MODE (SUBREG_REG (op0)));
821 else if (GET_CODE (op0) == REG)
823 word = operand_subword_force (op0, offset, GET_MODE (op0));
829 /* OFFSET is in UNITs, and UNIT is in bits.
830 store_fixed_bit_field wants offset in bytes. */
831 store_fixed_bit_field (word, offset * unit / BITS_PER_UNIT,
832 thissize, thispos, part, align);
833 bitsdone += thissize;
837 /* Generate code to extract a byte-field from STR_RTX
838 containing BITSIZE bits, starting at BITNUM,
839 and put it in TARGET if possible (if TARGET is nonzero).
840 Regardless of TARGET, we return the rtx for where the value is placed.
843 STR_RTX is the structure containing the byte (a REG or MEM).
844 UNSIGNEDP is nonzero if this is an unsigned bit field.
845 MODE is the natural mode of the field value once extracted.
846 TMODE is the mode the caller would like the value to have;
847 but the value may be returned with type MODE instead.
849 ALIGN is the alignment that STR_RTX is known to have, measured in bytes.
850 TOTAL_SIZE is the size in bytes of the containing structure,
853 If a TARGET is specified and we can store in it at no extra cost,
854 we do so, and return TARGET.
855 Otherwise, we return a REG of mode TMODE or MODE, with TMODE preferred
856 if they are equally easy. */
859 extract_bit_field (str_rtx, bitsize, bitnum, unsignedp,
860 target, mode, tmode, align, total_size)
862 register int bitsize;
866 enum machine_mode mode, tmode;
870 int unit = (GET_CODE (str_rtx) == MEM) ? BITS_PER_UNIT : BITS_PER_WORD;
871 register int offset = bitnum / unit;
872 register int bitpos = bitnum % unit;
873 register rtx op0 = str_rtx;
874 rtx spec_target = target;
875 rtx spec_target_subreg = 0;
877 if (GET_CODE (str_rtx) == MEM && ! MEM_IN_STRUCT_P (str_rtx))
880 /* Discount the part of the structure before the desired byte.
881 We need to know how many bytes are safe to reference after it. */
883 total_size -= (bitpos / BIGGEST_ALIGNMENT
884 * (BIGGEST_ALIGNMENT / BITS_PER_UNIT));
886 if (tmode == VOIDmode)
888 while (GET_CODE (op0) == SUBREG)
890 int outer_size = GET_MODE_BITSIZE (GET_MODE (op0));
891 int inner_size = GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)));
893 offset += SUBREG_WORD (op0);
895 if (BYTES_BIG_ENDIAN && (outer_size < inner_size))
897 bitpos += inner_size - outer_size;
900 offset += (bitpos / unit);
905 op0 = SUBREG_REG (op0);
908 /* ??? We currently assume TARGET is at least as big as BITSIZE.
909 If that's wrong, the solution is to test for it and set TARGET to 0
912 /* If OP0 is a register, BITPOS must count within a word.
913 But as we have it, it counts within whatever size OP0 now has.
914 On a bigendian machine, these are not the same, so convert. */
915 if (BYTES_BIG_ENDIAN &&
916 GET_CODE (op0) != MEM
917 && unit > GET_MODE_BITSIZE (GET_MODE (op0)))
918 bitpos += unit - GET_MODE_BITSIZE (GET_MODE (op0));
920 /* Extracting a full-word or multi-word value
921 from a structure in a register or aligned memory.
922 This can be done with just SUBREG.
923 So too extracting a subword value in
924 the least significant part of the register. */
926 if ((GET_CODE (op0) == REG
927 || (GET_CODE (op0) == MEM
928 && (! SLOW_UNALIGNED_ACCESS
929 || (offset * BITS_PER_UNIT % bitsize == 0
930 && align * BITS_PER_UNIT % bitsize == 0))))
931 && ((bitsize >= BITS_PER_WORD && bitsize == GET_MODE_BITSIZE (mode)
932 && bitpos % BITS_PER_WORD == 0)
933 || (mode_for_size (bitsize, GET_MODE_CLASS (tmode), 0) != BLKmode
935 ? bitpos + bitsize == BITS_PER_WORD
938 enum machine_mode mode1
939 = mode_for_size (bitsize, GET_MODE_CLASS (tmode), 0);
941 if (mode1 != GET_MODE (op0))
943 if (GET_CODE (op0) == REG)
944 op0 = gen_rtx (SUBREG, mode1, op0, offset);
946 op0 = change_address (op0, mode1,
947 plus_constant (XEXP (op0, 0), offset));
950 return convert_to_mode (tmode, op0, unsignedp);
954 /* Handle fields bigger than a word. */
956 if (bitsize > BITS_PER_WORD)
958 /* Here we transfer the words of the field
959 in the order least significant first.
960 This is because the most significant word is the one which may
961 be less than full. */
963 int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD;
966 if (target == 0 || GET_CODE (target) != REG)
967 target = gen_reg_rtx (mode);
969 for (i = 0; i < nwords; i++)
971 /* If I is 0, use the low-order word in both field and target;
972 if I is 1, use the next to lowest word; and so on. */
973 /* Word number in TARGET to use. */
974 int wordnum = (WORDS_BIG_ENDIAN
975 ? GET_MODE_SIZE (GET_MODE (target)) / UNITS_PER_WORD - i - 1
977 /* Offset from start of field in OP0. */
978 int bit_offset = (WORDS_BIG_ENDIAN
979 ? MAX (0, bitsize - (i + 1) * BITS_PER_WORD)
980 : i * BITS_PER_WORD);
981 rtx target_part = operand_subword (target, wordnum, 1, VOIDmode);
983 = extract_bit_field (op0, MIN (BITS_PER_WORD,
984 bitsize - i * BITS_PER_WORD),
986 1, target_part, mode, word_mode,
989 if (target_part == 0)
992 if (result_part != target_part)
993 emit_move_insn (target_part, result_part);
998 /* Unless we've filled TARGET, the upper regs in a multi-reg value
999 need to be zero'd out. */
1000 if (GET_MODE_SIZE (GET_MODE (target)) > nwords * UNITS_PER_WORD)
1004 total_words = GET_MODE_SIZE (GET_MODE (target)) / UNITS_PER_WORD;
1005 for (i = nwords; i < total_words; i++)
1007 int wordnum = WORDS_BIG_ENDIAN ? total_words - i - 1 : i;
1008 rtx target_part = operand_subword (target, wordnum, 1, VOIDmode);
1009 emit_move_insn (target_part, const0_rtx);
1015 /* Signed bit field: sign-extend with two arithmetic shifts. */
1016 target = expand_shift (LSHIFT_EXPR, mode, target,
1017 build_int_2 (GET_MODE_BITSIZE (mode) - bitsize, 0),
1019 return expand_shift (RSHIFT_EXPR, mode, target,
1020 build_int_2 (GET_MODE_BITSIZE (mode) - bitsize, 0),
1024 /* From here on we know the desired field is smaller than a word
1025 so we can assume it is an integer. So we can safely extract it as one
1026 size of integer, if necessary, and then truncate or extend
1027 to the size that is wanted. */
1029 /* OFFSET is the number of words or bytes (UNIT says which)
1030 from STR_RTX to the first word or byte containing part of the field. */
1032 if (GET_CODE (op0) == REG)
1035 || GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD)
1036 op0 = gen_rtx (SUBREG, TYPE_MODE (type_for_size (BITS_PER_WORD, 0)),
1042 op0 = protect_from_queue (str_rtx, 1);
1045 /* Now OFFSET is nonzero only for memory operands. */
1051 && (GET_MODE_BITSIZE (insn_operand_mode[(int) CODE_FOR_extzv][0])
1053 && ! ((GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
1054 && (bitsize + bitpos
1055 > GET_MODE_BITSIZE (insn_operand_mode[(int) CODE_FOR_extzv][0]))))
1057 int xbitpos = bitpos, xoffset = offset;
1058 rtx bitsize_rtx, bitpos_rtx;
1059 rtx last = get_last_insn();
1061 rtx xtarget = target;
1062 rtx xspec_target = spec_target;
1063 rtx xspec_target_subreg = spec_target_subreg;
1065 enum machine_mode maxmode
1066 = insn_operand_mode[(int) CODE_FOR_extzv][0];
1068 if (GET_CODE (xop0) == MEM)
1070 int save_volatile_ok = volatile_ok;
1073 /* Is the memory operand acceptable? */
1075 || ! ((*insn_operand_predicate[(int) CODE_FOR_extzv][1])
1076 (xop0, GET_MODE (xop0))))
1078 /* No, load into a reg and extract from there. */
1079 enum machine_mode bestmode;
1081 /* Get the mode to use for inserting into this field. If
1082 OP0 is BLKmode, get the smallest mode consistent with the
1083 alignment. If OP0 is a non-BLKmode object that is no
1084 wider than MAXMODE, use its mode. Otherwise, use the
1085 smallest mode containing the field. */
1087 if (GET_MODE (xop0) == BLKmode
1088 || (GET_MODE_SIZE (GET_MODE (op0))
1089 > GET_MODE_SIZE (maxmode)))
1090 bestmode = get_best_mode (bitsize, bitnum,
1091 align * BITS_PER_UNIT, maxmode,
1092 MEM_VOLATILE_P (xop0));
1094 bestmode = GET_MODE (xop0);
1096 if (bestmode == VOIDmode
1097 || (SLOW_UNALIGNED_ACCESS && GET_MODE_SIZE (bestmode) > align))
1100 /* Compute offset as multiple of this unit,
1101 counting in bytes. */
1102 unit = GET_MODE_BITSIZE (bestmode);
1103 xoffset = (bitnum / unit) * GET_MODE_SIZE (bestmode);
1104 xbitpos = bitnum % unit;
1105 xop0 = change_address (xop0, bestmode,
1106 plus_constant (XEXP (xop0, 0),
1108 /* Fetch it to a register in that size. */
1109 xop0 = force_reg (bestmode, xop0);
1111 /* XBITPOS counts within UNIT, which is what is expected. */
1114 /* Get ref to first byte containing part of the field. */
1115 xop0 = change_address (xop0, byte_mode,
1116 plus_constant (XEXP (xop0, 0), xoffset));
1118 volatile_ok = save_volatile_ok;
1121 /* If op0 is a register, we need it in MAXMODE (which is usually
1122 SImode). to make it acceptable to the format of extzv. */
1123 if (GET_CODE (xop0) == SUBREG && GET_MODE (xop0) != maxmode)
1125 if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode)
1126 xop0 = gen_rtx (SUBREG, maxmode, xop0, 0);
1128 /* On big-endian machines, we count bits from the most significant.
1129 If the bit field insn does not, we must invert. */
1130 if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
1131 xbitpos = unit - bitsize - xbitpos;
1133 /* Now convert from counting within UNIT to counting in MAXMODE. */
1134 if (BITS_BIG_ENDIAN && GET_CODE (xop0) != MEM)
1135 xbitpos += GET_MODE_BITSIZE (maxmode) - unit;
1137 unit = GET_MODE_BITSIZE (maxmode);
1140 || (flag_force_mem && GET_CODE (xtarget) == MEM))
1141 xtarget = xspec_target = gen_reg_rtx (tmode);
1143 if (GET_MODE (xtarget) != maxmode)
1145 if (GET_CODE (xtarget) == REG)
1147 int wider = (GET_MODE_SIZE (maxmode)
1148 > GET_MODE_SIZE (GET_MODE (xtarget)));
1149 xtarget = gen_lowpart (maxmode, xtarget);
1151 xspec_target_subreg = xtarget;
1154 xtarget = gen_reg_rtx (maxmode);
1157 /* If this machine's extzv insists on a register target,
1158 make sure we have one. */
1159 if (! ((*insn_operand_predicate[(int) CODE_FOR_extzv][0])
1160 (xtarget, maxmode)))
1161 xtarget = gen_reg_rtx (maxmode);
1163 bitsize_rtx = GEN_INT (bitsize);
1164 bitpos_rtx = GEN_INT (xbitpos);
1166 pat = gen_extzv (protect_from_queue (xtarget, 1),
1167 xop0, bitsize_rtx, bitpos_rtx);
1172 spec_target = xspec_target;
1173 spec_target_subreg = xspec_target_subreg;
1177 delete_insns_since (last);
1178 target = extract_fixed_bit_field (tmode, op0, offset, bitsize,
1179 bitpos, target, 1, align);
1185 target = extract_fixed_bit_field (tmode, op0, offset, bitsize, bitpos,
1192 && (GET_MODE_BITSIZE (insn_operand_mode[(int) CODE_FOR_extv][0])
1194 && ! ((GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
1195 && (bitsize + bitpos
1196 > GET_MODE_BITSIZE (insn_operand_mode[(int) CODE_FOR_extv][0]))))
1198 int xbitpos = bitpos, xoffset = offset;
1199 rtx bitsize_rtx, bitpos_rtx;
1200 rtx last = get_last_insn();
1201 rtx xop0 = op0, xtarget = target;
1202 rtx xspec_target = spec_target;
1203 rtx xspec_target_subreg = spec_target_subreg;
1205 enum machine_mode maxmode
1206 = insn_operand_mode[(int) CODE_FOR_extv][0];
1208 if (GET_CODE (xop0) == MEM)
1210 /* Is the memory operand acceptable? */
1211 if (! ((*insn_operand_predicate[(int) CODE_FOR_extv][1])
1212 (xop0, GET_MODE (xop0))))
1214 /* No, load into a reg and extract from there. */
1215 enum machine_mode bestmode;
1217 /* Get the mode to use for inserting into this field. If
1218 OP0 is BLKmode, get the smallest mode consistent with the
1219 alignment. If OP0 is a non-BLKmode object that is no
1220 wider than MAXMODE, use its mode. Otherwise, use the
1221 smallest mode containing the field. */
1223 if (GET_MODE (xop0) == BLKmode
1224 || (GET_MODE_SIZE (GET_MODE (op0))
1225 > GET_MODE_SIZE (maxmode)))
1226 bestmode = get_best_mode (bitsize, bitnum,
1227 align * BITS_PER_UNIT, maxmode,
1228 MEM_VOLATILE_P (xop0));
1230 bestmode = GET_MODE (xop0);
1232 if (bestmode == VOIDmode
1233 || (SLOW_UNALIGNED_ACCESS && GET_MODE_SIZE (bestmode) > align))
1236 /* Compute offset as multiple of this unit,
1237 counting in bytes. */
1238 unit = GET_MODE_BITSIZE (bestmode);
1239 xoffset = (bitnum / unit) * GET_MODE_SIZE (bestmode);
1240 xbitpos = bitnum % unit;
1241 xop0 = change_address (xop0, bestmode,
1242 plus_constant (XEXP (xop0, 0),
1244 /* Fetch it to a register in that size. */
1245 xop0 = force_reg (bestmode, xop0);
1247 /* XBITPOS counts within UNIT, which is what is expected. */
1250 /* Get ref to first byte containing part of the field. */
1251 xop0 = change_address (xop0, byte_mode,
1252 plus_constant (XEXP (xop0, 0), xoffset));
1255 /* If op0 is a register, we need it in MAXMODE (which is usually
1256 SImode) to make it acceptable to the format of extv. */
1257 if (GET_CODE (xop0) == SUBREG && GET_MODE (xop0) != maxmode)
1259 if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode)
1260 xop0 = gen_rtx (SUBREG, maxmode, xop0, 0);
1262 /* On big-endian machines, we count bits from the most significant.
1263 If the bit field insn does not, we must invert. */
1264 if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
1265 xbitpos = unit - bitsize - xbitpos;
1267 /* XBITPOS counts within a size of UNIT.
1268 Adjust to count within a size of MAXMODE. */
1269 if (BITS_BIG_ENDIAN && GET_CODE (xop0) != MEM)
1270 xbitpos += (GET_MODE_BITSIZE (maxmode) - unit);
1272 unit = GET_MODE_BITSIZE (maxmode);
1275 || (flag_force_mem && GET_CODE (xtarget) == MEM))
1276 xtarget = xspec_target = gen_reg_rtx (tmode);
1278 if (GET_MODE (xtarget) != maxmode)
1280 if (GET_CODE (xtarget) == REG)
1282 int wider = (GET_MODE_SIZE (maxmode)
1283 > GET_MODE_SIZE (GET_MODE (xtarget)));
1284 xtarget = gen_lowpart (maxmode, xtarget);
1286 xspec_target_subreg = xtarget;
1289 xtarget = gen_reg_rtx (maxmode);
1292 /* If this machine's extv insists on a register target,
1293 make sure we have one. */
1294 if (! ((*insn_operand_predicate[(int) CODE_FOR_extv][0])
1295 (xtarget, maxmode)))
1296 xtarget = gen_reg_rtx (maxmode);
1298 bitsize_rtx = GEN_INT (bitsize);
1299 bitpos_rtx = GEN_INT (xbitpos);
1301 pat = gen_extv (protect_from_queue (xtarget, 1),
1302 xop0, bitsize_rtx, bitpos_rtx);
1307 spec_target = xspec_target;
1308 spec_target_subreg = xspec_target_subreg;
1312 delete_insns_since (last);
1313 target = extract_fixed_bit_field (tmode, op0, offset, bitsize,
1314 bitpos, target, 0, align);
1320 target = extract_fixed_bit_field (tmode, op0, offset, bitsize, bitpos,
1323 if (target == spec_target)
1325 if (target == spec_target_subreg)
1327 if (GET_MODE (target) != tmode && GET_MODE (target) != mode)
1329 /* If the target mode is floating-point, first convert to the
1330 integer mode of that size and then access it as a floating-point
1331 value via a SUBREG. */
1332 if (GET_MODE_CLASS (tmode) == MODE_FLOAT)
1334 target = convert_to_mode (mode_for_size (GET_MODE_BITSIZE (tmode),
1337 if (GET_CODE (target) != REG)
1338 target = copy_to_reg (target);
1339 return gen_rtx (SUBREG, tmode, target, 0);
1342 return convert_to_mode (tmode, target, unsignedp);
1347 /* Extract a bit field using shifts and boolean operations
1348 Returns an rtx to represent the value.
1349 OP0 addresses a register (word) or memory (byte).
1350 BITPOS says which bit within the word or byte the bit field starts in.
1351 OFFSET says how many bytes farther the bit field starts;
1352 it is 0 if OP0 is a register.
1353 BITSIZE says how many bits long the bit field is.
1354 (If OP0 is a register, it may be narrower than a full word,
1355 but BITPOS still counts within a full word,
1356 which is significant on bigendian machines.)
1358 UNSIGNEDP is nonzero for an unsigned bit field (don't sign-extend value).
1359 If TARGET is nonzero, attempts to store the value there
1360 and return TARGET, but this is not guaranteed.
1361 If TARGET is not used, create a pseudo-reg of mode TMODE for the value.
1363 ALIGN is the alignment that STR_RTX is known to have, measured in bytes. */
1366 extract_fixed_bit_field (tmode, op0, offset, bitsize, bitpos,
1367 target, unsignedp, align)
1368 enum machine_mode tmode;
1369 register rtx op0, target;
1370 register int offset, bitsize, bitpos;
1374 int total_bits = BITS_PER_WORD;
1375 enum machine_mode mode;
1377 if (GET_CODE (op0) == SUBREG || GET_CODE (op0) == REG)
1379 /* Special treatment for a bit field split across two registers. */
1380 if (bitsize + bitpos > BITS_PER_WORD)
1381 return extract_split_bit_field (op0, bitsize, bitpos,
1386 /* Get the proper mode to use for this field. We want a mode that
1387 includes the entire field. If such a mode would be larger than
1388 a word, we won't be doing the extraction the normal way. */
1390 mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT,
1391 align * BITS_PER_UNIT, word_mode,
1392 GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0));
1394 if (mode == VOIDmode)
1395 /* The only way this should occur is if the field spans word
1397 return extract_split_bit_field (op0, bitsize,
1398 bitpos + offset * BITS_PER_UNIT,
1401 total_bits = GET_MODE_BITSIZE (mode);
1403 /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to
1404 be be in the range 0 to total_bits-1, and put any excess bytes in
1406 if (bitpos >= total_bits)
1408 offset += (bitpos / total_bits) * (total_bits / BITS_PER_UNIT);
1409 bitpos -= ((bitpos / total_bits) * (total_bits / BITS_PER_UNIT)
1413 /* Get ref to an aligned byte, halfword, or word containing the field.
1414 Adjust BITPOS to be position within a word,
1415 and OFFSET to be the offset of that word.
1416 Then alter OP0 to refer to that word. */
1417 bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT;
1418 offset -= (offset % (total_bits / BITS_PER_UNIT));
1419 op0 = change_address (op0, mode,
1420 plus_constant (XEXP (op0, 0), offset));
1423 mode = GET_MODE (op0);
1425 if (BYTES_BIG_ENDIAN)
1427 /* BITPOS is the distance between our msb and that of OP0.
1428 Convert it to the distance from the lsb. */
1430 bitpos = total_bits - bitsize - bitpos;
1433 /* Now BITPOS is always the distance between the field's lsb and that of OP0.
1434 We have reduced the big-endian case to the little-endian case. */
1440 /* If the field does not already start at the lsb,
1441 shift it so it does. */
1442 tree amount = build_int_2 (bitpos, 0);
1443 /* Maybe propagate the target for the shift. */
1444 /* But not if we will return it--could confuse integrate.c. */
1445 rtx subtarget = (target != 0 && GET_CODE (target) == REG
1446 && !REG_FUNCTION_VALUE_P (target)
1448 if (tmode != mode) subtarget = 0;
1449 op0 = expand_shift (RSHIFT_EXPR, mode, op0, amount, subtarget, 1);
1451 /* Convert the value to the desired mode. */
1453 op0 = convert_to_mode (tmode, op0, 1);
1455 /* Unless the msb of the field used to be the msb when we shifted,
1456 mask out the upper bits. */
1458 if (GET_MODE_BITSIZE (mode) != bitpos + bitsize
1460 #ifdef SLOW_ZERO_EXTEND
1461 /* Always generate an `and' if
1462 we just zero-extended op0 and SLOW_ZERO_EXTEND, since it
1463 will combine fruitfully with the zero-extend. */
1468 return expand_binop (GET_MODE (op0), and_optab, op0,
1469 mask_rtx (GET_MODE (op0), 0, bitsize, 0),
1470 target, 1, OPTAB_LIB_WIDEN);
1474 /* To extract a signed bit-field, first shift its msb to the msb of the word,
1475 then arithmetic-shift its lsb to the lsb of the word. */
1476 op0 = force_reg (mode, op0);
1480 /* Find the narrowest integer mode that contains the field. */
1482 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode;
1483 mode = GET_MODE_WIDER_MODE (mode))
1484 if (GET_MODE_BITSIZE (mode) >= bitsize + bitpos)
1486 op0 = convert_to_mode (mode, op0, 0);
1490 if (GET_MODE_BITSIZE (mode) != (bitsize + bitpos))
1492 tree amount = build_int_2 (GET_MODE_BITSIZE (mode) - (bitsize + bitpos), 0);
1493 /* Maybe propagate the target for the shift. */
1494 /* But not if we will return the result--could confuse integrate.c. */
1495 rtx subtarget = (target != 0 && GET_CODE (target) == REG
1496 && ! REG_FUNCTION_VALUE_P (target)
1498 op0 = expand_shift (LSHIFT_EXPR, mode, op0, amount, subtarget, 1);
1501 return expand_shift (RSHIFT_EXPR, mode, op0,
1502 build_int_2 (GET_MODE_BITSIZE (mode) - bitsize, 0),
1506 /* Return a constant integer (CONST_INT or CONST_DOUBLE) mask value
1507 of mode MODE with BITSIZE ones followed by BITPOS zeros, or the
1508 complement of that if COMPLEMENT. The mask is truncated if
1509 necessary to the width of mode MODE. The mask is zero-extended if
1510 BITSIZE+BITPOS is too small for MODE. */
1513 mask_rtx (mode, bitpos, bitsize, complement)
1514 enum machine_mode mode;
1515 int bitpos, bitsize, complement;
1517 HOST_WIDE_INT masklow, maskhigh;
1519 if (bitpos < HOST_BITS_PER_WIDE_INT)
1520 masklow = (HOST_WIDE_INT) -1 << bitpos;
1524 if (bitpos + bitsize < HOST_BITS_PER_WIDE_INT)
1525 masklow &= ((unsigned HOST_WIDE_INT) -1
1526 >> (HOST_BITS_PER_WIDE_INT - bitpos - bitsize));
1528 if (bitpos <= HOST_BITS_PER_WIDE_INT)
1531 maskhigh = (HOST_WIDE_INT) -1 << (bitpos - HOST_BITS_PER_WIDE_INT);
1533 if (bitpos + bitsize > HOST_BITS_PER_WIDE_INT)
1534 maskhigh &= ((unsigned HOST_WIDE_INT) -1
1535 >> (2 * HOST_BITS_PER_WIDE_INT - bitpos - bitsize));
1541 maskhigh = ~maskhigh;
1545 return immed_double_const (masklow, maskhigh, mode);
1548 /* Return a constant integer (CONST_INT or CONST_DOUBLE) rtx with the value
1549 VALUE truncated to BITSIZE bits and then shifted left BITPOS bits. */
1552 lshift_value (mode, value, bitpos, bitsize)
1553 enum machine_mode mode;
1555 int bitpos, bitsize;
1557 unsigned HOST_WIDE_INT v = INTVAL (value);
1558 HOST_WIDE_INT low, high;
1560 if (bitsize < HOST_BITS_PER_WIDE_INT)
1561 v &= ~((HOST_WIDE_INT) -1 << bitsize);
1563 if (bitpos < HOST_BITS_PER_WIDE_INT)
1566 high = (bitpos > 0 ? (v >> (HOST_BITS_PER_WIDE_INT - bitpos)) : 0);
1571 high = v << (bitpos - HOST_BITS_PER_WIDE_INT);
1574 return immed_double_const (low, high, mode);
1577 /* Extract a bit field that is split across two words
1578 and return an RTX for the result.
1580 OP0 is the REG, SUBREG or MEM rtx for the first of the two words.
1581 BITSIZE is the field width; BITPOS, position of its first bit, in the word.
1582 UNSIGNEDP is 1 if should zero-extend the contents; else sign-extend.
1584 ALIGN is the known alignment of OP0, measured in bytes.
1585 This is also the size of the memory objects to be used. */
1588 extract_split_bit_field (op0, bitsize, bitpos, unsignedp, align)
1590 int bitsize, bitpos, unsignedp, align;
1597 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
1599 if (GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
1600 unit = BITS_PER_WORD;
1602 unit = MIN (align * BITS_PER_UNIT, BITS_PER_WORD);
1604 while (bitsdone < bitsize)
1611 offset = (bitpos + bitsdone) / unit;
1612 thispos = (bitpos + bitsdone) % unit;
1614 /* THISSIZE must not overrun a word boundary. Otherwise,
1615 extract_fixed_bit_field will call us again, and we will mutually
1617 thissize = MIN (bitsize - bitsdone, BITS_PER_WORD);
1618 thissize = MIN (thissize, unit - thispos);
1620 /* If OP0 is a register, then handle OFFSET here.
1622 When handling multiword bitfields, extract_bit_field may pass
1623 down a word_mode SUBREG of a larger REG for a bitfield that actually
1624 crosses a word boundary. Thus, for a SUBREG, we must find
1625 the current word starting from the base register. */
1626 if (GET_CODE (op0) == SUBREG)
1628 word = operand_subword_force (SUBREG_REG (op0),
1629 SUBREG_WORD (op0) + offset,
1630 GET_MODE (SUBREG_REG (op0)));
1633 else if (GET_CODE (op0) == REG)
1635 word = operand_subword_force (op0, offset, GET_MODE (op0));
1641 /* Extract the parts in bit-counting order,
1642 whose meaning is determined by BYTES_PER_UNIT.
1643 OFFSET is in UNITs, and UNIT is in bits.
1644 extract_fixed_bit_field wants offset in bytes. */
1645 part = extract_fixed_bit_field (word_mode, word,
1646 offset * unit / BITS_PER_UNIT,
1647 thissize, thispos, 0, 1, align);
1648 bitsdone += thissize;
1650 /* Shift this part into place for the result. */
1651 if (BYTES_BIG_ENDIAN)
1653 if (bitsize != bitsdone)
1654 part = expand_shift (LSHIFT_EXPR, word_mode, part,
1655 build_int_2 (bitsize - bitsdone, 0), 0, 1);
1659 if (bitsdone != thissize)
1660 part = expand_shift (LSHIFT_EXPR, word_mode, part,
1661 build_int_2 (bitsdone - thissize, 0), 0, 1);
1667 /* Combine the parts with bitwise or. This works
1668 because we extracted each part as an unsigned bit field. */
1669 result = expand_binop (word_mode, ior_optab, part, result, NULL_RTX, 1,
1675 /* Unsigned bit field: we are done. */
1678 /* Signed bit field: sign-extend with two arithmetic shifts. */
1679 result = expand_shift (LSHIFT_EXPR, word_mode, result,
1680 build_int_2 (BITS_PER_WORD - bitsize, 0),
1682 return expand_shift (RSHIFT_EXPR, word_mode, result,
1683 build_int_2 (BITS_PER_WORD - bitsize, 0), NULL_RTX, 0);
1686 /* Add INC into TARGET. */
1689 expand_inc (target, inc)
1692 rtx value = expand_binop (GET_MODE (target), add_optab,
1694 target, 0, OPTAB_LIB_WIDEN);
1695 if (value != target)
1696 emit_move_insn (target, value);
1699 /* Subtract DEC from TARGET. */
1702 expand_dec (target, dec)
1705 rtx value = expand_binop (GET_MODE (target), sub_optab,
1707 target, 0, OPTAB_LIB_WIDEN);
1708 if (value != target)
1709 emit_move_insn (target, value);
1712 /* Output a shift instruction for expression code CODE,
1713 with SHIFTED being the rtx for the value to shift,
1714 and AMOUNT the tree for the amount to shift by.
1715 Store the result in the rtx TARGET, if that is convenient.
1716 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
1717 Return the rtx for where the value is. */
1720 expand_shift (code, mode, shifted, amount, target, unsignedp)
1721 enum tree_code code;
1722 register enum machine_mode mode;
1725 register rtx target;
1728 register rtx op1, temp = 0;
1729 register int left = (code == LSHIFT_EXPR || code == LROTATE_EXPR);
1730 register int rotate = (code == LROTATE_EXPR || code == RROTATE_EXPR);
1733 /* Previously detected shift-counts computed by NEGATE_EXPR
1734 and shifted in the other direction; but that does not work
1737 op1 = expand_expr (amount, NULL_RTX, VOIDmode, 0);
1739 #if SHIFT_COUNT_TRUNCATED
1740 if (SHIFT_COUNT_TRUNCATED
1741 && GET_CODE (op1) == CONST_INT
1742 && (unsigned HOST_WIDE_INT) INTVAL (op1) >= GET_MODE_BITSIZE (mode))
1743 op1 = GEN_INT ((unsigned HOST_WIDE_INT) INTVAL (op1)
1744 % GET_MODE_BITSIZE (mode));
1747 if (op1 == const0_rtx)
1750 for (try = 0; temp == 0 && try < 3; try++)
1752 enum optab_methods methods;
1755 methods = OPTAB_DIRECT;
1757 methods = OPTAB_WIDEN;
1759 methods = OPTAB_LIB_WIDEN;
1763 /* Widening does not work for rotation. */
1764 if (methods == OPTAB_WIDEN)
1766 else if (methods == OPTAB_LIB_WIDEN)
1768 /* If we have been unable to open-code this by a rotation,
1769 do it as the IOR of two shifts. I.e., to rotate A
1770 by N bits, compute (A << N) | ((unsigned) A >> (C - N))
1771 where C is the bitsize of A.
1773 It is theoretically possible that the target machine might
1774 not be able to perform either shift and hence we would
1775 be making two libcalls rather than just the one for the
1776 shift (similarly if IOR could not be done). We will allow
1777 this extremely unlikely lossage to avoid complicating the
1780 rtx subtarget = target == shifted ? 0 : target;
1782 tree type = TREE_TYPE (amount);
1783 tree new_amount = make_tree (type, op1);
1785 = fold (build (MINUS_EXPR, type,
1787 build_int_2 (GET_MODE_BITSIZE (mode),
1791 shifted = force_reg (mode, shifted);
1793 temp = expand_shift (left ? LSHIFT_EXPR : RSHIFT_EXPR,
1794 mode, shifted, new_amount, subtarget, 1);
1795 temp1 = expand_shift (left ? RSHIFT_EXPR : LSHIFT_EXPR,
1796 mode, shifted, other_amount, 0, 1);
1797 return expand_binop (mode, ior_optab, temp, temp1, target,
1798 unsignedp, methods);
1801 temp = expand_binop (mode,
1802 left ? rotl_optab : rotr_optab,
1803 shifted, op1, target, unsignedp, methods);
1805 /* If we don't have the rotate, but we are rotating by a constant
1806 that is in range, try a rotate in the opposite direction. */
1808 if (temp == 0 && GET_CODE (op1) == CONST_INT
1809 && INTVAL (op1) > 0 && INTVAL (op1) < GET_MODE_BITSIZE (mode))
1810 temp = expand_binop (mode,
1811 left ? rotr_optab : rotl_optab,
1813 GEN_INT (GET_MODE_BITSIZE (mode)
1815 target, unsignedp, methods);
1818 temp = expand_binop (mode,
1819 left ? ashl_optab : lshr_optab,
1820 shifted, op1, target, unsignedp, methods);
1822 /* Do arithmetic shifts.
1823 Also, if we are going to widen the operand, we can just as well
1824 use an arithmetic right-shift instead of a logical one. */
1825 if (temp == 0 && ! rotate
1826 && (! unsignedp || (! left && methods == OPTAB_WIDEN)))
1828 enum optab_methods methods1 = methods;
1830 /* If trying to widen a log shift to an arithmetic shift,
1831 don't accept an arithmetic shift of the same size. */
1833 methods1 = OPTAB_MUST_WIDEN;
1835 /* Arithmetic shift */
1837 temp = expand_binop (mode,
1838 left ? ashl_optab : ashr_optab,
1839 shifted, op1, target, unsignedp, methods1);
1842 /* We used to try extzv here for logical right shifts, but that was
1843 only useful for one machine, the VAX, and caused poor code
1844 generation there for lshrdi3, so the code was deleted and a
1845 define_expand for lshrsi3 was added to vax.md. */
1853 enum alg_code { alg_zero, alg_m, alg_shift,
1854 alg_add_t_m2, alg_sub_t_m2,
1855 alg_add_factor, alg_sub_factor,
1856 alg_add_t2_m, alg_sub_t2_m,
1857 alg_add, alg_subtract, alg_factor, alg_shiftop };
1859 /* This structure records a sequence of operations.
1860 `ops' is the number of operations recorded.
1861 `cost' is their total cost.
1862 The operations are stored in `op' and the corresponding
1863 logarithms of the integer coefficients in `log'.
1865 These are the operations:
1866 alg_zero total := 0;
1867 alg_m total := multiplicand;
1868 alg_shift total := total * coeff
1869 alg_add_t_m2 total := total + multiplicand * coeff;
1870 alg_sub_t_m2 total := total - multiplicand * coeff;
1871 alg_add_factor total := total * coeff + total;
1872 alg_sub_factor total := total * coeff - total;
1873 alg_add_t2_m total := total * coeff + multiplicand;
1874 alg_sub_t2_m total := total * coeff - multiplicand;
1876 The first operand must be either alg_zero or alg_m. */
1882 /* The size of the OP and LOG fields are not directly related to the
1883 word size, but the worst-case algorithms will be if we have few
1884 consecutive ones or zeros, i.e., a multiplicand like 10101010101...
1885 In that case we will generate shift-by-2, add, shift-by-2, add,...,
1886 in total wordsize operations. */
1887 enum alg_code op[MAX_BITS_PER_WORD];
1888 char log[MAX_BITS_PER_WORD];
1891 /* Compute and return the best algorithm for multiplying by T.
1892 The algorithm must cost less than cost_limit
1893 If retval.cost >= COST_LIMIT, no algorithm was found and all
1894 other field of the returned struct are undefined. */
1897 synth_mult (alg_out, t, cost_limit)
1898 struct algorithm *alg_out;
1899 unsigned HOST_WIDE_INT t;
1903 struct algorithm *alg_in, *best_alg;
1905 unsigned HOST_WIDE_INT q;
1907 /* Indicate that no algorithm is yet found. If no algorithm
1908 is found, this value will be returned and indicate failure. */
1909 alg_out->cost = cost_limit;
1911 if (cost_limit <= 0)
1914 /* t == 1 can be done in zero cost. */
1919 alg_out->op[0] = alg_m;
1923 /* t == 0 sometimes has a cost. If it does and it exceeds our limit,
1927 if (zero_cost >= cost_limit)
1932 alg_out->cost = zero_cost;
1933 alg_out->op[0] = alg_zero;
1938 /* We'll be needing a couple extra algorithm structures now. */
1940 alg_in = (struct algorithm *)alloca (sizeof (struct algorithm));
1941 best_alg = (struct algorithm *)alloca (sizeof (struct algorithm));
1943 /* If we have a group of zero bits at the low-order part of T, try
1944 multiplying by the remaining bits and then doing a shift. */
1948 m = floor_log2 (t & -t); /* m = number of low zero bits */
1950 cost = shift_cost[m];
1951 synth_mult (alg_in, q, cost_limit - cost);
1953 cost += alg_in->cost;
1954 if (cost < cost_limit)
1956 struct algorithm *x;
1957 x = alg_in, alg_in = best_alg, best_alg = x;
1958 best_alg->log[best_alg->ops] = m;
1959 best_alg->op[best_alg->ops] = alg_shift;
1964 /* If we have an odd number, add or subtract one. */
1967 unsigned HOST_WIDE_INT w;
1969 for (w = 1; (w & t) != 0; w <<= 1)
1972 /* Reject the case where t is 3.
1973 Thus we prefer addition in that case. */
1976 /* T ends with ...111. Multiply by (T + 1) and subtract 1. */
1979 synth_mult (alg_in, t + 1, cost_limit - cost);
1981 cost += alg_in->cost;
1982 if (cost < cost_limit)
1984 struct algorithm *x;
1985 x = alg_in, alg_in = best_alg, best_alg = x;
1986 best_alg->log[best_alg->ops] = 0;
1987 best_alg->op[best_alg->ops] = alg_sub_t_m2;
1993 /* T ends with ...01 or ...011. Multiply by (T - 1) and add 1. */
1996 synth_mult (alg_in, t - 1, cost_limit - cost);
1998 cost += alg_in->cost;
1999 if (cost < cost_limit)
2001 struct algorithm *x;
2002 x = alg_in, alg_in = best_alg, best_alg = x;
2003 best_alg->log[best_alg->ops] = 0;
2004 best_alg->op[best_alg->ops] = alg_add_t_m2;
2010 /* Look for factors of t of the form
2011 t = q(2**m +- 1), 2 <= m <= floor(log2(t - 1)).
2012 If we find such a factor, we can multiply by t using an algorithm that
2013 multiplies by q, shift the result by m and add/subtract it to itself.
2015 We search for large factors first and loop down, even if large factors
2016 are less probable than small; if we find a large factor we will find a
2017 good sequence quickly, and therefore be able to prune (by decreasing
2018 COST_LIMIT) the search. */
2020 for (m = floor_log2 (t - 1); m >= 2; m--)
2022 unsigned HOST_WIDE_INT d;
2024 d = ((unsigned HOST_WIDE_INT) 1 << m) + 1;
2025 if (t % d == 0 && t > d)
2027 cost = MIN (shiftadd_cost[m], add_cost + shift_cost[m]);
2028 synth_mult (alg_in, t / d, cost_limit - cost);
2030 cost += alg_in->cost;
2031 if (cost < cost_limit)
2033 struct algorithm *x;
2034 x = alg_in, alg_in = best_alg, best_alg = x;
2035 best_alg->log[best_alg->ops] = m;
2036 best_alg->op[best_alg->ops] = alg_add_factor;
2039 /* Other factors will have been taken care of in the recursion. */
2043 d = ((unsigned HOST_WIDE_INT) 1 << m) - 1;
2044 if (t % d == 0 && t > d)
2046 cost = MIN (shiftsub_cost[m], add_cost + shift_cost[m]);
2047 synth_mult (alg_in, t / d, cost_limit - cost);
2049 cost += alg_in->cost;
2050 if (cost < cost_limit)
2052 struct algorithm *x;
2053 x = alg_in, alg_in = best_alg, best_alg = x;
2054 best_alg->log[best_alg->ops] = m;
2055 best_alg->op[best_alg->ops] = alg_sub_factor;
2062 /* Try shift-and-add (load effective address) instructions,
2063 i.e. do a*3, a*5, a*9. */
2071 cost = shiftadd_cost[m];
2072 synth_mult (alg_in, (t - 1) >> m, cost_limit - cost);
2074 cost += alg_in->cost;
2075 if (cost < cost_limit)
2077 struct algorithm *x;
2078 x = alg_in, alg_in = best_alg, best_alg = x;
2079 best_alg->log[best_alg->ops] = m;
2080 best_alg->op[best_alg->ops] = alg_add_t2_m;
2090 cost = shiftsub_cost[m];
2091 synth_mult (alg_in, (t + 1) >> m, cost_limit - cost);
2093 cost += alg_in->cost;
2094 if (cost < cost_limit)
2096 struct algorithm *x;
2097 x = alg_in, alg_in = best_alg, best_alg = x;
2098 best_alg->log[best_alg->ops] = m;
2099 best_alg->op[best_alg->ops] = alg_sub_t2_m;
2105 /* If cost_limit has not decreased since we stored it in alg_out->cost,
2106 we have not found any algorithm. */
2107 if (cost_limit == alg_out->cost)
2110 /* If we are getting a too long sequence for `struct algorithm'
2111 to record, make this search fail. */
2112 if (best_alg->ops == MAX_BITS_PER_WORD)
2115 /* Copy the algorithm from temporary space to the space at alg_out.
2116 We avoid using structure assignment because the majority of
2117 best_alg is normally undefined, and this is a critical function. */
2118 alg_out->ops = best_alg->ops + 1;
2119 alg_out->cost = cost_limit;
2120 bcopy ((char *) best_alg->op, (char *) alg_out->op,
2121 alg_out->ops * sizeof *alg_out->op);
2122 bcopy ((char *) best_alg->log, (char *) alg_out->log,
2123 alg_out->ops * sizeof *alg_out->log);
2126 /* Perform a multiplication and return an rtx for the result.
2127 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
2128 TARGET is a suggestion for where to store the result (an rtx).
2130 We check specially for a constant integer as OP1.
2131 If you want this check for OP0 as well, then before calling
2132 you should swap the two operands if OP0 would be constant. */
2135 expand_mult (mode, op0, op1, target, unsignedp)
2136 enum machine_mode mode;
2137 register rtx op0, op1, target;
2140 rtx const_op1 = op1;
2142 /* synth_mult does an `unsigned int' multiply. As long as the mode is
2143 less than or equal in size to `unsigned int' this doesn't matter.
2144 If the mode is larger than `unsigned int', then synth_mult works only
2145 if the constant value exactly fits in an `unsigned int' without any
2146 truncation. This means that multiplying by negative values does
2147 not work; results are off by 2^32 on a 32 bit machine. */
2149 /* If we are multiplying in DImode, it may still be a win
2150 to try to work with shifts and adds. */
2151 if (GET_CODE (op1) == CONST_DOUBLE
2152 && GET_MODE_CLASS (GET_MODE (op1)) == MODE_INT
2153 && HOST_BITS_PER_INT >= BITS_PER_WORD
2154 && CONST_DOUBLE_HIGH (op1) == 0)
2155 const_op1 = GEN_INT (CONST_DOUBLE_LOW (op1));
2156 else if (HOST_BITS_PER_INT < GET_MODE_BITSIZE (mode)
2157 && GET_CODE (op1) == CONST_INT
2158 && INTVAL (op1) < 0)
2161 /* We used to test optimize here, on the grounds that it's better to
2162 produce a smaller program when -O is not used.
2163 But this causes such a terrible slowdown sometimes
2164 that it seems better to use synth_mult always. */
2166 if (const_op1 && GET_CODE (const_op1) == CONST_INT)
2168 struct algorithm alg;
2169 struct algorithm alg2;
2170 HOST_WIDE_INT val = INTVAL (op1);
2171 HOST_WIDE_INT val_so_far;
2174 enum {basic_variant, negate_variant, add_variant} variant = basic_variant;
2176 /* Try to do the computation three ways: multiply by the negative of OP1
2177 and then negate, do the multiplication directly, or do multiplication
2180 mult_cost = rtx_cost (gen_rtx (MULT, mode, op0, op1), SET);
2181 mult_cost = MIN (12 * add_cost, mult_cost);
2183 synth_mult (&alg, val, mult_cost);
2185 /* This works only if the inverted value actually fits in an
2187 if (HOST_BITS_PER_INT >= GET_MODE_BITSIZE (mode))
2189 synth_mult (&alg2, - val,
2190 (alg.cost < mult_cost ? alg.cost : mult_cost) - negate_cost);
2191 if (alg2.cost + negate_cost < alg.cost)
2192 alg = alg2, variant = negate_variant;
2195 /* This proves very useful for division-by-constant. */
2196 synth_mult (&alg2, val - 1,
2197 (alg.cost < mult_cost ? alg.cost : mult_cost) - add_cost);
2198 if (alg2.cost + add_cost < alg.cost)
2199 alg = alg2, variant = add_variant;
2201 if (alg.cost < mult_cost)
2203 /* We found something cheaper than a multiply insn. */
2207 op0 = protect_from_queue (op0, 0);
2209 /* Avoid referencing memory over and over.
2210 For speed, but also for correctness when mem is volatile. */
2211 if (GET_CODE (op0) == MEM)
2212 op0 = force_reg (mode, op0);
2214 /* ACCUM starts out either as OP0 or as a zero, depending on
2215 the first operation. */
2217 if (alg.op[0] == alg_zero)
2219 accum = copy_to_mode_reg (mode, const0_rtx);
2222 else if (alg.op[0] == alg_m)
2224 accum = copy_to_mode_reg (mode, op0);
2230 for (opno = 1; opno < alg.ops; opno++)
2232 int log = alg.log[opno];
2233 int preserve = preserve_subexpressions_p ();
2234 rtx shift_subtarget = preserve ? 0 : accum;
2236 = (opno == alg.ops - 1 && target != 0 && variant != add_variant
2238 rtx accum_target = preserve ? 0 : accum;
2240 switch (alg.op[opno])
2243 accum = expand_shift (LSHIFT_EXPR, mode, accum,
2244 build_int_2 (log, 0), NULL_RTX, 0);
2249 tem = expand_shift (LSHIFT_EXPR, mode, op0,
2250 build_int_2 (log, 0), NULL_RTX, 0);
2251 accum = force_operand (gen_rtx (PLUS, mode, accum, tem),
2252 add_target ? add_target : accum_target);
2253 val_so_far += (HOST_WIDE_INT) 1 << log;
2257 tem = expand_shift (LSHIFT_EXPR, mode, op0,
2258 build_int_2 (log, 0), NULL_RTX, 0);
2259 accum = force_operand (gen_rtx (MINUS, mode, accum, tem),
2260 add_target ? add_target : accum_target);
2261 val_so_far -= (HOST_WIDE_INT) 1 << log;
2265 accum = expand_shift (LSHIFT_EXPR, mode, accum,
2266 build_int_2 (log, 0), shift_subtarget,
2268 accum = force_operand (gen_rtx (PLUS, mode, accum, op0),
2269 add_target ? add_target : accum_target);
2270 val_so_far = (val_so_far << log) + 1;
2274 accum = expand_shift (LSHIFT_EXPR, mode, accum,
2275 build_int_2 (log, 0), shift_subtarget,
2277 accum = force_operand (gen_rtx (MINUS, mode, accum, op0),
2278 add_target ? add_target : accum_target);
2279 val_so_far = (val_so_far << log) - 1;
2282 case alg_add_factor:
2283 tem = expand_shift (LSHIFT_EXPR, mode, accum,
2284 build_int_2 (log, 0), NULL_RTX, 0);
2285 accum = force_operand (gen_rtx (PLUS, mode, accum, tem),
2286 add_target ? add_target : accum_target);
2287 val_so_far += val_so_far << log;
2290 case alg_sub_factor:
2291 tem = expand_shift (LSHIFT_EXPR, mode, accum,
2292 build_int_2 (log, 0), NULL_RTX, 0);
2293 accum = force_operand (gen_rtx (MINUS, mode, tem, accum),
2294 (add_target ? add_target
2295 : preserve ? 0 : tem));
2296 val_so_far = (val_so_far << log) - val_so_far;
2303 /* Write a REG_EQUAL note on the last insn so that we can cse
2304 multiplication sequences. */
2306 insn = get_last_insn ();
2308 = gen_rtx (EXPR_LIST, REG_EQUAL,
2309 gen_rtx (MULT, mode, op0, GEN_INT (val_so_far)),
2313 if (variant == negate_variant)
2315 val_so_far = - val_so_far;
2316 accum = expand_unop (mode, neg_optab, accum, target, 0);
2318 else if (variant == add_variant)
2320 val_so_far = val_so_far + 1;
2321 accum = force_operand (gen_rtx (PLUS, mode, accum, op0), target);
2324 if (val != val_so_far)
2331 /* This used to use umul_optab if unsigned, but for non-widening multiply
2332 there is no difference between signed and unsigned. */
2333 op0 = expand_binop (mode, smul_optab,
2334 op0, op1, target, unsignedp, OPTAB_LIB_WIDEN);
2340 /* Return the smallest n such that 2**n >= X. */
2344 unsigned HOST_WIDE_INT x;
2346 return floor_log2 (x - 1) + 1;
2349 /* Choose a minimal N + 1 bit approximation to 1/D that can be used to
2350 replace division by D, and put the least significant N bits of the result
2351 in *MULTIPLIER_PTR and return the most significant bit.
2353 The width of operations is N (should be <= HOST_BITS_PER_WIDE_INT), the
2354 needed precision is in PRECISION (should be <= N).
2356 PRECISION should be as small as possible so this function can choose
2357 multiplier more freely.
2359 The rounded-up logarithm of D is placed in *lgup_ptr. A shift count that
2360 is to be used for a final right shift is placed in *POST_SHIFT_PTR.
2362 Using this function, x/D will be equal to (x * m) >> (*POST_SHIFT_PTR),
2363 where m is the full HOST_BITS_PER_WIDE_INT + 1 bit multiplier. */
2366 unsigned HOST_WIDE_INT
2367 choose_multiplier (d, n, precision, multiplier_ptr, post_shift_ptr, lgup_ptr)
2368 unsigned HOST_WIDE_INT d;
2371 unsigned HOST_WIDE_INT *multiplier_ptr;
2372 int *post_shift_ptr;
2375 unsigned HOST_WIDE_INT mhigh_hi, mhigh_lo;
2376 unsigned HOST_WIDE_INT mlow_hi, mlow_lo;
2377 int lgup, post_shift;
2379 unsigned HOST_WIDE_INT nh, nl, dummy1, dummy2;
2381 /* lgup = ceil(log2(divisor)); */
2382 lgup = ceil_log2 (d);
2388 pow2 = n + lgup - precision;
2390 if (pow == 2 * HOST_BITS_PER_WIDE_INT)
2392 /* We could handle this with some effort, but this case is much better
2393 handled directly with a scc insn, so rely on caller using that. */
2397 /* mlow = 2^(N + lgup)/d */
2398 if (pow >= HOST_BITS_PER_WIDE_INT)
2400 nh = (unsigned HOST_WIDE_INT) 1 << (pow - HOST_BITS_PER_WIDE_INT);
2406 nl = (unsigned HOST_WIDE_INT) 1 << pow;
2408 div_and_round_double (TRUNC_DIV_EXPR, 1, nl, nh, d, (HOST_WIDE_INT) 0,
2409 &mlow_lo, &mlow_hi, &dummy1, &dummy2);
2411 /* mhigh = (2^(N + lgup) + 2^N + lgup - precision)/d */
2412 if (pow2 >= HOST_BITS_PER_WIDE_INT)
2413 nh |= (unsigned HOST_WIDE_INT) 1 << (pow2 - HOST_BITS_PER_WIDE_INT);
2415 nl |= (unsigned HOST_WIDE_INT) 1 << pow2;
2416 div_and_round_double (TRUNC_DIV_EXPR, 1, nl, nh, d, (HOST_WIDE_INT) 0,
2417 &mhigh_lo, &mhigh_hi, &dummy1, &dummy2);
2419 if (mhigh_hi && nh - d >= d)
2421 if (mhigh_hi > 1 || mlow_hi > 1)
2423 /* assert that mlow < mhigh. */
2424 if (! (mlow_hi < mhigh_hi || (mlow_hi == mhigh_hi && mlow_lo < mhigh_lo)))
2427 /* If precision == N, then mlow, mhigh exceed 2^N
2428 (but they do not exceed 2^(N+1)). */
2430 /* Reduce to lowest terms */
2431 for (post_shift = lgup; post_shift > 0; post_shift--)
2433 unsigned HOST_WIDE_INT ml_lo = (mlow_hi << (HOST_BITS_PER_WIDE_INT - 1)) | (mlow_lo >> 1);
2434 unsigned HOST_WIDE_INT mh_lo = (mhigh_hi << (HOST_BITS_PER_WIDE_INT - 1)) | (mhigh_lo >> 1);
2444 *post_shift_ptr = post_shift;
2446 if (n < HOST_BITS_PER_WIDE_INT)
2448 unsigned HOST_WIDE_INT mask = ((unsigned HOST_WIDE_INT) 1 << n) - 1;
2449 *multiplier_ptr = mhigh_lo & mask;
2450 return mhigh_lo >= mask;
2454 *multiplier_ptr = mhigh_lo;
2459 /* Compute the inverse of X mod 2**n, i.e., find Y such that X * Y is
2460 congruent to 1 (mod 2**N). */
2462 static unsigned HOST_WIDE_INT
2464 unsigned HOST_WIDE_INT x;
2467 /* Solve x*y == 1 (mod 2^n), where x is odd. Return y. */
2469 /* The algorithm notes that the choice y = x satisfies
2470 x*y == 1 mod 2^3, since x is assumed odd.
2471 Each iteration doubles the number of bits of significance in y. */
2473 unsigned HOST_WIDE_INT mask;
2474 unsigned HOST_WIDE_INT y = x;
2477 mask = (n == HOST_BITS_PER_WIDE_INT
2478 ? ~(unsigned HOST_WIDE_INT) 0
2479 : ((unsigned HOST_WIDE_INT) 1 << n) - 1);
2483 y = y * (2 - x*y) & mask; /* Modulo 2^N */
2489 /* Emit code to adjust ADJ_OPERAND after multiplication of wrong signedness
2490 flavor of OP0 and OP1. ADJ_OPERAND is already the high half of the
2491 product OP0 x OP1. If UNSIGNEDP is nonzero, adjust the signed product
2492 to become unsigned, if UNSIGNEDP is zero, adjust the unsigned product to
2495 The result is put in TARGET if that is convenient.
2497 MODE is the mode of operation. */
2500 expand_mult_highpart_adjust (mode, adj_operand, op0, op1, target, unsignedp)
2501 enum machine_mode mode;
2502 register rtx adj_operand, op0, op1, target;
2506 enum rtx_code adj_code = unsignedp ? PLUS : MINUS;
2508 tem = expand_shift (RSHIFT_EXPR, mode, op0,
2509 build_int_2 (GET_MODE_BITSIZE (mode) - 1, 0),
2511 tem = expand_and (tem, op1, NULL_RTX);
2512 adj_operand = force_operand (gen_rtx (adj_code, mode, adj_operand, tem),
2515 tem = expand_shift (RSHIFT_EXPR, mode, op1,
2516 build_int_2 (GET_MODE_BITSIZE (mode) - 1, 0),
2518 tem = expand_and (tem, op0, NULL_RTX);
2519 target = force_operand (gen_rtx (adj_code, mode, adj_operand, tem), target);
2524 /* Emit code to multiply OP0 and CNST1, putting the high half of the result
2525 in TARGET if that is convenient, and return where the result is. If the
2526 operation can not be performed, 0 is returned.
2528 MODE is the mode of operation and result.
2530 UNSIGNEDP nonzero means unsigned multiply.
2532 MAX_COST is the total allowed cost for the expanded RTL. */
2535 expand_mult_highpart (mode, op0, cnst1, target, unsignedp, max_cost)
2536 enum machine_mode mode;
2537 register rtx op0, target;
2538 unsigned HOST_WIDE_INT cnst1;
2542 enum machine_mode wider_mode = GET_MODE_WIDER_MODE (mode);
2543 optab mul_highpart_optab;
2546 int size = GET_MODE_BITSIZE (mode);
2549 /* We can't support modes wider than HOST_BITS_PER_INT. */
2550 if (size > HOST_BITS_PER_WIDE_INT)
2553 op1 = GEN_INT (cnst1);
2555 if (GET_MODE_BITSIZE (wider_mode) <= HOST_BITS_PER_INT)
2559 = immed_double_const (cnst1,
2562 : -(cnst1 >> (HOST_BITS_PER_WIDE_INT - 1))),
2565 /* expand_mult handles constant multiplication of word_mode
2566 or narrower. It does a poor job for large modes. */
2567 if (size < BITS_PER_WORD
2568 && mul_cost[(int) wider_mode] + shift_cost[size-1] < max_cost)
2570 /* We have to do this, since expand_binop doesn't do conversion for
2571 multiply. Maybe change expand_binop to handle widening multiply? */
2572 op0 = convert_to_mode (wider_mode, op0, unsignedp);
2574 tem = expand_mult (wider_mode, op0, wide_op1, NULL_RTX, unsignedp);
2575 tem = expand_shift (RSHIFT_EXPR, wider_mode, tem,
2576 build_int_2 (size, 0), NULL_RTX, 1);
2577 return convert_modes (mode, wider_mode, tem, unsignedp);
2581 target = gen_reg_rtx (mode);
2583 /* Firstly, try using a multiplication insn that only generates the needed
2584 high part of the product, and in the sign flavor of unsignedp. */
2585 if (mul_highpart_cost[(int) mode] < max_cost)
2587 mul_highpart_optab = unsignedp ? umul_highpart_optab : smul_highpart_optab;
2588 target = expand_binop (mode, mul_highpart_optab,
2589 op0, wide_op1, target, unsignedp, OPTAB_DIRECT);
2594 /* Secondly, same as above, but use sign flavor opposite of unsignedp.
2595 Need to adjust the result after the multiplication. */
2596 if (mul_highpart_cost[(int) mode] + 2 * shift_cost[size-1] + 4 * add_cost < max_cost)
2598 mul_highpart_optab = unsignedp ? smul_highpart_optab : umul_highpart_optab;
2599 target = expand_binop (mode, mul_highpart_optab,
2600 op0, wide_op1, target, unsignedp, OPTAB_DIRECT);
2602 /* We used the wrong signedness. Adjust the result. */
2603 return expand_mult_highpart_adjust (mode, target, op0,
2604 op1, target, unsignedp);
2607 /* Try widening multiplication. */
2608 moptab = unsignedp ? umul_widen_optab : smul_widen_optab;
2609 if (moptab->handlers[(int) wider_mode].insn_code != CODE_FOR_nothing
2610 && mul_widen_cost[(int) wider_mode] < max_cost)
2613 /* Try widening the mode and perform a non-widening multiplication. */
2614 moptab = smul_optab;
2615 if (smul_optab->handlers[(int) wider_mode].insn_code != CODE_FOR_nothing
2616 && mul_cost[(int) wider_mode] + shift_cost[size-1] < max_cost)
2619 /* Try widening multiplication of opposite signedness, and adjust. */
2620 moptab = unsignedp ? smul_widen_optab : umul_widen_optab;
2621 if (moptab->handlers[(int) wider_mode].insn_code != CODE_FOR_nothing
2622 && (mul_widen_cost[(int) wider_mode]
2623 + 2 * shift_cost[size-1] + 4 * add_cost < max_cost))
2625 tem = expand_binop (wider_mode, moptab, op0, wide_op1,
2626 NULL_RTX, ! unsignedp, OPTAB_WIDEN);
2629 /* Extract the high half of the just generated product. */
2630 tem = expand_shift (RSHIFT_EXPR, wider_mode, tem,
2631 build_int_2 (size, 0), NULL_RTX, 1);
2632 tem = convert_modes (mode, wider_mode, tem, unsignedp);
2633 /* We used the wrong signedness. Adjust the result. */
2634 return expand_mult_highpart_adjust (mode, tem, op0, op1,
2642 /* Pass NULL_RTX as target since TARGET has wrong mode. */
2643 tem = expand_binop (wider_mode, moptab, op0, wide_op1,
2644 NULL_RTX, unsignedp, OPTAB_WIDEN);
2648 /* Extract the high half of the just generated product. */
2649 tem = expand_shift (RSHIFT_EXPR, wider_mode, tem,
2650 build_int_2 (size, 0), NULL_RTX, 1);
2651 return convert_modes (mode, wider_mode, tem, unsignedp);
2654 /* Emit the code to divide OP0 by OP1, putting the result in TARGET
2655 if that is convenient, and returning where the result is.
2656 You may request either the quotient or the remainder as the result;
2657 specify REM_FLAG nonzero to get the remainder.
2659 CODE is the expression code for which kind of division this is;
2660 it controls how rounding is done. MODE is the machine mode to use.
2661 UNSIGNEDP nonzero means do unsigned division. */
2663 /* ??? For CEIL_MOD_EXPR, can compute incorrect remainder with ANDI
2664 and then correct it by or'ing in missing high bits
2665 if result of ANDI is nonzero.
2666 For ROUND_MOD_EXPR, can use ANDI and then sign-extend the result.
2667 This could optimize to a bfexts instruction.
2668 But C doesn't use these operations, so their optimizations are
2671 #define EXACT_POWER_OF_2_OR_ZERO_P(x) (((x) & ((x) - 1)) == 0)
2674 expand_divmod (rem_flag, code, mode, op0, op1, target, unsignedp)
2676 enum tree_code code;
2677 enum machine_mode mode;
2678 register rtx op0, op1, target;
2681 enum machine_mode compute_mode;
2682 register rtx tquotient;
2683 rtx quotient = 0, remainder = 0;
2687 optab optab1, optab2;
2688 int op1_is_constant, op1_is_pow2;
2689 int max_cost, extra_cost;
2691 op1_is_constant = GET_CODE (op1) == CONST_INT;
2692 op1_is_pow2 = (op1_is_constant
2693 && ((EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1))
2694 || EXACT_POWER_OF_2_OR_ZERO_P (-INTVAL (op1)))));
2697 This is the structure of expand_divmod:
2699 First comes code to fix up the operands so we can perform the operations
2700 correctly and efficiently.
2702 Second comes a switch statement with code specific for each rounding mode.
2703 For some special operands this code emits all RTL for the desired
2704 operation, for other cases, it generates only a quotient and stores it in
2705 QUOTIENT. The case for trunc division/remainder might leave quotient = 0,
2706 to indicate that it has not done anything.
2708 Last comes code that finishes the operation. If QUOTIENT is set and
2709 REM_FLAG is set, the remainder is computed as OP0 - QUOTIENT * OP1. If
2710 QUOTIENT is not set, it is computed using trunc rounding.
2712 We try to generate special code for division and remainder when OP1 is a
2713 constant. If |OP1| = 2**n we can use shifts and some other fast
2714 operations. For other values of OP1, we compute a carefully selected
2715 fixed-point approximation m = 1/OP1, and generate code that multiplies OP0
2718 In all cases but EXACT_DIV_EXPR, this multiplication requires the upper
2719 half of the product. Different strategies for generating the product are
2720 implemented in expand_mult_highpart.
2722 If what we actually want is the remainder, we generate that by another
2723 by-constant multiplication and a subtraction. */
2725 /* We shouldn't be called with OP1 == const1_rtx, but some of the
2726 code below will malfunction if we are, so check here and handle
2727 the special case if so. */
2728 if (op1 == const1_rtx)
2729 return rem_flag ? const0_rtx : op0;
2732 /* Don't use the function value register as a target
2733 since we have to read it as well as write it,
2734 and function-inlining gets confused by this. */
2735 && ((REG_P (target) && REG_FUNCTION_VALUE_P (target))
2736 /* Don't clobber an operand while doing a multi-step calculation. */
2737 || ((rem_flag || op1_is_constant)
2738 && (reg_mentioned_p (target, op0)
2739 || (GET_CODE (op0) == MEM && GET_CODE (target) == MEM)))
2740 || reg_mentioned_p (target, op1)
2741 || (GET_CODE (op1) == MEM && GET_CODE (target) == MEM)))
2744 /* Get the mode in which to perform this computation. Normally it will
2745 be MODE, but sometimes we can't do the desired operation in MODE.
2746 If so, pick a wider mode in which we can do the operation. Convert
2747 to that mode at the start to avoid repeated conversions.
2749 First see what operations we need. These depend on the expression
2750 we are evaluating. (We assume that divxx3 insns exist under the
2751 same conditions that modxx3 insns and that these insns don't normally
2752 fail. If these assumptions are not correct, we may generate less
2753 efficient code in some cases.)
2755 Then see if we find a mode in which we can open-code that operation
2756 (either a division, modulus, or shift). Finally, check for the smallest
2757 mode for which we can do the operation with a library call. */
2759 /* We might want to refine this now that we have division-by-constant
2760 optimization. Since expand_mult_highpart tries so many variants, it is
2761 not straightforward to generalize this. Maybe we should make an array
2762 of possible modes in init_expmed? Save this for GCC 2.7. */
2764 optab1 = (op1_is_pow2 ? (unsignedp ? lshr_optab : ashr_optab)
2765 : (unsignedp ? udiv_optab : sdiv_optab));
2766 optab2 = (op1_is_pow2 ? optab1 : (unsignedp ? udivmod_optab : sdivmod_optab));
2768 for (compute_mode = mode; compute_mode != VOIDmode;
2769 compute_mode = GET_MODE_WIDER_MODE (compute_mode))
2770 if (optab1->handlers[(int) compute_mode].insn_code != CODE_FOR_nothing
2771 || optab2->handlers[(int) compute_mode].insn_code != CODE_FOR_nothing)
2774 if (compute_mode == VOIDmode)
2775 for (compute_mode = mode; compute_mode != VOIDmode;
2776 compute_mode = GET_MODE_WIDER_MODE (compute_mode))
2777 if (optab1->handlers[(int) compute_mode].libfunc
2778 || optab2->handlers[(int) compute_mode].libfunc)
2781 /* If we still couldn't find a mode, use MODE, but we'll probably abort
2783 if (compute_mode == VOIDmode)
2784 compute_mode = mode;
2786 if (target && GET_MODE (target) == compute_mode)
2789 tquotient = gen_reg_rtx (compute_mode);
2791 size = GET_MODE_BITSIZE (compute_mode);
2793 /* It should be possible to restrict the precision to GET_MODE_BITSIZE
2794 (mode), and thereby get better code when OP1 is a constant. Do that
2795 later. It will require going over all usages of SIZE below. */
2796 size = GET_MODE_BITSIZE (mode);
2799 max_cost = div_cost[(int) compute_mode]
2800 - (rem_flag ? mul_cost[(int) compute_mode] + add_cost : 0);
2802 /* Now convert to the best mode to use. */
2803 if (compute_mode != mode)
2805 op0 = convert_modes (compute_mode, mode, op0, unsignedp);
2806 op1 = convert_modes (compute_mode, mode, op1, unsignedp);
2809 /* If one of the operands is a volatile MEM, copy it into a register. */
2811 if (GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0))
2812 op0 = force_reg (compute_mode, op0);
2813 if (GET_CODE (op1) == MEM && MEM_VOLATILE_P (op1))
2814 op1 = force_reg (compute_mode, op1);
2816 /* If we need the remainder or if OP1 is constant, we need to
2817 put OP0 in a register in case it has any queued subexpressions. */
2818 if (rem_flag || op1_is_constant)
2819 op0 = force_reg (compute_mode, op0);
2821 last = get_last_insn ();
2823 /* Promote floor rounding to trunc rounding for unsigned operations. */
2826 if (code == FLOOR_DIV_EXPR)
2827 code = TRUNC_DIV_EXPR;
2828 if (code == FLOOR_MOD_EXPR)
2829 code = TRUNC_MOD_EXPR;
2832 if (op1 != const0_rtx)
2835 case TRUNC_MOD_EXPR:
2836 case TRUNC_DIV_EXPR:
2837 if (op1_is_constant && HOST_BITS_PER_WIDE_INT >= size)
2841 unsigned HOST_WIDE_INT mh, ml;
2842 int pre_shift, post_shift;
2844 unsigned HOST_WIDE_INT d = INTVAL (op1);
2846 if (EXACT_POWER_OF_2_OR_ZERO_P (d))
2848 pre_shift = floor_log2 (d);
2851 remainder = expand_binop (compute_mode, and_optab, op0,
2852 GEN_INT (((HOST_WIDE_INT) 1 << pre_shift) - 1),
2856 return gen_lowpart (mode, remainder);
2858 quotient = expand_shift (RSHIFT_EXPR, compute_mode, op0,
2859 build_int_2 (pre_shift, 0),
2862 else if (d >= ((unsigned HOST_WIDE_INT) 1 << (size - 1)))
2864 /* Most significant bit of divisor is set, emit a scc insn.
2865 emit_store_flag needs to be passed a place for the
2867 quotient = emit_store_flag (tquotient, GEU, op0, op1,
2868 compute_mode, 1, 1);
2874 /* Find a suitable multiplier and right shift count instead
2875 of multiplying with D. */
2877 mh = choose_multiplier (d, size, size,
2878 &ml, &post_shift, &dummy);
2880 /* If the suggested multiplier is more than SIZE bits, we
2881 can do better for even divisors, using an initial right
2883 if (mh != 0 && (d & 1) == 0)
2885 pre_shift = floor_log2 (d & -d);
2886 mh = choose_multiplier (d >> pre_shift, size,
2888 &ml, &post_shift, &dummy);
2899 extra_cost = (shift_cost[post_shift - 1]
2900 + shift_cost[1] + 2 * add_cost);
2901 t1 = expand_mult_highpart (compute_mode, op0, ml,
2903 max_cost - extra_cost);
2906 t2 = force_operand (gen_rtx (MINUS, compute_mode,
2909 t3 = expand_shift (RSHIFT_EXPR, compute_mode, t2,
2910 build_int_2 (1, 0), NULL_RTX, 1);
2911 t4 = force_operand (gen_rtx (PLUS, compute_mode,
2914 quotient = expand_shift (RSHIFT_EXPR, compute_mode, t4,
2915 build_int_2 (post_shift - 1,
2923 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
2924 build_int_2 (pre_shift, 0),
2926 extra_cost = (shift_cost[pre_shift]
2927 + shift_cost[post_shift]);
2928 t2 = expand_mult_highpart (compute_mode, t1, ml,
2930 max_cost - extra_cost);
2933 quotient = expand_shift (RSHIFT_EXPR, compute_mode, t2,
2934 build_int_2 (post_shift, 0),
2939 insn = get_last_insn ();
2941 && (set = single_set (insn)) != 0
2942 && SET_DEST (set) == quotient)
2944 = gen_rtx (EXPR_LIST, REG_EQUAL,
2945 gen_rtx (UDIV, compute_mode, op0, op1),
2948 else /* TRUNC_DIV, signed */
2950 unsigned HOST_WIDE_INT ml;
2951 int lgup, post_shift;
2952 HOST_WIDE_INT d = INTVAL (op1);
2953 unsigned HOST_WIDE_INT abs_d = d >= 0 ? d : -d;
2955 /* n rem d = n rem -d */
2956 if (rem_flag && d < 0)
2959 op1 = GEN_INT (abs_d);
2965 quotient = expand_unop (compute_mode, neg_optab, op0,
2967 else if (abs_d == (unsigned HOST_WIDE_INT) 1 << (size - 1))
2969 /* This case is not handled correctly below. */
2970 quotient = emit_store_flag (tquotient, EQ, op0, op1,
2971 compute_mode, 1, 1);
2975 else if (EXACT_POWER_OF_2_OR_ZERO_P (d)
2976 && (rem_flag ? smod_pow2_cheap : sdiv_pow2_cheap))
2978 else if (EXACT_POWER_OF_2_OR_ZERO_P (abs_d))
2980 lgup = floor_log2 (abs_d);
2981 if (abs_d != 2 && BRANCH_COST < 3)
2983 rtx label = gen_label_rtx ();
2986 t1 = copy_to_mode_reg (compute_mode, op0);
2987 emit_cmp_insn (t1, const0_rtx, GE,
2988 NULL_RTX, compute_mode, 0, 0);
2989 emit_jump_insn (gen_bge (label));
2990 expand_inc (t1, GEN_INT (abs_d - 1));
2992 quotient = expand_shift (RSHIFT_EXPR, compute_mode, t1,
2993 build_int_2 (lgup, 0),
2999 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3000 build_int_2 (size - 1, 0),
3002 t2 = expand_shift (RSHIFT_EXPR, compute_mode, t1,
3003 build_int_2 (size - lgup, 0),
3005 t3 = force_operand (gen_rtx (PLUS, compute_mode,
3008 quotient = expand_shift (RSHIFT_EXPR, compute_mode, t3,
3009 build_int_2 (lgup, 0),
3013 /* We have computed OP0 / abs(OP1). If OP1 is negative, negate
3017 insn = get_last_insn ();
3019 && (set = single_set (insn)) != 0
3020 && SET_DEST (set) == quotient)
3022 = gen_rtx (EXPR_LIST, REG_EQUAL,
3023 gen_rtx (DIV, compute_mode, op0,
3027 quotient = expand_unop (compute_mode, neg_optab,
3028 quotient, quotient, 0);
3033 choose_multiplier (abs_d, size, size - 1,
3034 &ml, &post_shift, &lgup);
3035 if (ml < (unsigned HOST_WIDE_INT) 1 << (size - 1))
3039 extra_cost = (shift_cost[post_shift]
3040 + shift_cost[size - 1] + add_cost);
3041 t1 = expand_mult_highpart (compute_mode, op0, ml,
3043 max_cost - extra_cost);
3046 t2 = expand_shift (RSHIFT_EXPR, compute_mode, t1,
3047 build_int_2 (post_shift, 0), NULL_RTX, 0);
3048 t3 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3049 build_int_2 (size - 1, 0), NULL_RTX, 0);
3051 quotient = force_operand (gen_rtx (MINUS, compute_mode, t3, t2),
3054 quotient = force_operand (gen_rtx (MINUS, compute_mode, t2, t3),
3061 ml |= (~(unsigned HOST_WIDE_INT) 0) << (size - 1);
3062 extra_cost = (shift_cost[post_shift]
3063 + shift_cost[size - 1] + 2 * add_cost);
3064 t1 = expand_mult_highpart (compute_mode, op0, ml,
3066 max_cost - extra_cost);
3069 t2 = force_operand (gen_rtx (PLUS, compute_mode, t1, op0),
3071 t3 = expand_shift (RSHIFT_EXPR, compute_mode, t2,
3072 build_int_2 (post_shift, 0), NULL_RTX, 0);
3073 t4 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3074 build_int_2 (size - 1, 0), NULL_RTX, 0);
3076 quotient = force_operand (gen_rtx (MINUS, compute_mode, t4, t3),
3079 quotient = force_operand (gen_rtx (MINUS, compute_mode, t3, t4),
3084 insn = get_last_insn ();
3086 && (set = single_set (insn)) != 0
3087 && SET_DEST (set) == quotient)
3089 = gen_rtx (EXPR_LIST, REG_EQUAL,
3090 gen_rtx (DIV, compute_mode, op0, op1),
3096 delete_insns_since (last);
3099 case FLOOR_DIV_EXPR:
3100 case FLOOR_MOD_EXPR:
3101 /* We will come here only for signed operations. */
3102 if (op1_is_constant && HOST_BITS_PER_WIDE_INT >= size)
3104 unsigned HOST_WIDE_INT mh, ml;
3105 int pre_shift, lgup, post_shift;
3106 HOST_WIDE_INT d = INTVAL (op1);
3110 /* We could just as easily deal with negative constants here,
3111 but it does not seem worth the trouble for GCC 2.6. */
3112 if (EXACT_POWER_OF_2_OR_ZERO_P (d))
3114 pre_shift = floor_log2 (d);
3117 remainder = expand_binop (compute_mode, and_optab, op0,
3118 GEN_INT (((HOST_WIDE_INT) 1 << pre_shift) - 1),
3119 remainder, 0, OPTAB_LIB_WIDEN);
3121 return gen_lowpart (mode, remainder);
3123 quotient = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3124 build_int_2 (pre_shift, 0),
3131 mh = choose_multiplier (d, size, size - 1,
3132 &ml, &post_shift, &lgup);
3136 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3137 build_int_2 (size - 1, 0), NULL_RTX, 0);
3138 t2 = expand_binop (compute_mode, xor_optab, op0, t1,
3139 NULL_RTX, 0, OPTAB_WIDEN);
3140 extra_cost = (shift_cost[post_shift]
3141 + shift_cost[size - 1] + 2 * add_cost);
3142 t3 = expand_mult_highpart (compute_mode, t2, ml,
3144 max_cost - extra_cost);
3147 t4 = expand_shift (RSHIFT_EXPR, compute_mode, t3,
3148 build_int_2 (post_shift, 0),
3150 quotient = expand_binop (compute_mode, xor_optab,
3151 t4, t1, tquotient, 0,
3158 rtx nsign, t1, t2, t3, t4;
3159 t1 = force_operand (gen_rtx (PLUS, compute_mode,
3160 op0, constm1_rtx), NULL_RTX);
3161 t2 = expand_binop (compute_mode, ior_optab, op0, t1, NULL_RTX,
3163 nsign = expand_shift (RSHIFT_EXPR, compute_mode, t2,
3164 build_int_2 (size - 1, 0), NULL_RTX, 0);
3165 t3 = force_operand (gen_rtx (MINUS, compute_mode, t1, nsign),
3167 t4 = expand_divmod (0, TRUNC_DIV_EXPR, compute_mode, t3, op1,
3172 t5 = expand_unop (compute_mode, one_cmpl_optab, nsign,
3174 quotient = force_operand (gen_rtx (PLUS, compute_mode,
3183 delete_insns_since (last);
3185 /* Try using an instruction that produces both the quotient and
3186 remainder, using truncation. We can easily compensate the quotient
3187 or remainder to get floor rounding, once we have the remainder.
3188 Notice that we compute also the final remainder value here,
3189 and return the result right away. */
3191 target = gen_reg_rtx (compute_mode);
3196 = GET_CODE (target) == REG ? target : gen_reg_rtx (compute_mode);
3197 quotient = gen_reg_rtx (compute_mode);
3202 = GET_CODE (target) == REG ? target : gen_reg_rtx (compute_mode);
3203 remainder = gen_reg_rtx (compute_mode);
3206 if (expand_twoval_binop (sdivmod_optab, op0, op1,
3207 quotient, remainder, 0))
3209 /* This could be computed with a branch-less sequence.
3210 Save that for later. */
3212 rtx label = gen_label_rtx ();
3213 emit_cmp_insn (remainder, const0_rtx, EQ, NULL_RTX,
3214 compute_mode, 0, 0);
3215 emit_jump_insn (gen_beq (label));
3216 tem = expand_binop (compute_mode, xor_optab, op0, op1,
3217 NULL_RTX, 0, OPTAB_WIDEN);
3218 emit_cmp_insn (tem, const0_rtx, GE, NULL_RTX, compute_mode, 0, 0);
3219 emit_jump_insn (gen_bge (label));
3220 expand_dec (quotient, const1_rtx);
3221 expand_inc (remainder, op1);
3223 return gen_lowpart (mode, rem_flag ? remainder : quotient);
3226 /* No luck with division elimination or divmod. Have to do it
3227 by conditionally adjusting op0 *and* the result. */
3229 rtx label1, label2, label3, label4, label5;
3233 quotient = gen_reg_rtx (compute_mode);
3234 adjusted_op0 = copy_to_mode_reg (compute_mode, op0);
3235 label1 = gen_label_rtx ();
3236 label2 = gen_label_rtx ();
3237 label3 = gen_label_rtx ();
3238 label4 = gen_label_rtx ();
3239 label5 = gen_label_rtx ();
3240 emit_cmp_insn (op1, const0_rtx, LT, NULL_RTX, compute_mode, 0, 0);
3241 emit_jump_insn (gen_blt (label2));
3242 emit_cmp_insn (adjusted_op0, const0_rtx, LT, NULL_RTX,
3243 compute_mode, 0, 0);
3244 emit_jump_insn (gen_blt (label1));
3245 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
3246 quotient, 0, OPTAB_LIB_WIDEN);
3247 if (tem != quotient)
3248 emit_move_insn (quotient, tem);
3249 emit_jump_insn (gen_jump (label5));
3251 emit_label (label1);
3252 expand_inc (adjusted_op0, const1_rtx);
3253 emit_jump_insn (gen_jump (label4));
3255 emit_label (label2);
3256 emit_cmp_insn (adjusted_op0, const0_rtx, GT, NULL_RTX,
3257 compute_mode, 0, 0);
3258 emit_jump_insn (gen_bgt (label3));
3259 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
3260 quotient, 0, OPTAB_LIB_WIDEN);
3261 if (tem != quotient)
3262 emit_move_insn (quotient, tem);
3263 emit_jump_insn (gen_jump (label5));
3265 emit_label (label3);
3266 expand_dec (adjusted_op0, const1_rtx);
3267 emit_label (label4);
3268 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
3269 quotient, 0, OPTAB_LIB_WIDEN);
3270 if (tem != quotient)
3271 emit_move_insn (quotient, tem);
3272 expand_dec (quotient, const1_rtx);
3273 emit_label (label5);
3281 if (op1_is_constant && EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1)))
3284 unsigned HOST_WIDE_INT d = INTVAL (op1);
3285 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3286 build_int_2 (floor_log2 (d), 0),
3288 t2 = expand_binop (compute_mode, and_optab, op0,
3290 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3291 t3 = gen_reg_rtx (compute_mode);
3292 t3 = emit_store_flag (t3, NE, t2, const0_rtx,
3293 compute_mode, 1, 1);
3297 lab = gen_label_rtx ();
3298 emit_cmp_insn (t2, const0_rtx, EQ, NULL_RTX,
3299 compute_mode, 0, 0);
3300 emit_jump_insn (gen_beq (lab));
3301 expand_inc (t1, const1_rtx);
3306 quotient = force_operand (gen_rtx (PLUS, compute_mode,
3312 /* Try using an instruction that produces both the quotient and
3313 remainder, using truncation. We can easily compensate the
3314 quotient or remainder to get ceiling rounding, once we have the
3315 remainder. Notice that we compute also the final remainder
3316 value here, and return the result right away. */
3318 target = gen_reg_rtx (compute_mode);
3322 remainder = (GET_CODE (target) == REG
3323 ? target : gen_reg_rtx (compute_mode));
3324 quotient = gen_reg_rtx (compute_mode);
3328 quotient = (GET_CODE (target) == REG
3329 ? target : gen_reg_rtx (compute_mode));
3330 remainder = gen_reg_rtx (compute_mode);
3333 if (expand_twoval_binop (udivmod_optab, op0, op1, quotient,
3336 /* This could be computed with a branch-less sequence.
3337 Save that for later. */
3338 rtx label = gen_label_rtx ();
3339 emit_cmp_insn (remainder, const0_rtx, EQ, NULL_RTX,
3340 compute_mode, 0, 0);
3341 emit_jump_insn (gen_beq (label));
3342 expand_inc (quotient, const1_rtx);
3343 expand_dec (remainder, op1);
3345 return gen_lowpart (mode, rem_flag ? remainder : quotient);
3348 /* No luck with division elimination or divmod. Have to do it
3349 by conditionally adjusting op0 *and* the result. */
3352 rtx adjusted_op0, tem;
3354 quotient = gen_reg_rtx (compute_mode);
3355 adjusted_op0 = copy_to_mode_reg (compute_mode, op0);
3356 label1 = gen_label_rtx ();
3357 label2 = gen_label_rtx ();
3358 emit_cmp_insn (adjusted_op0, const0_rtx, NE, NULL_RTX,
3359 compute_mode, 0, 0);
3360 emit_jump_insn (gen_bne (label1));
3361 emit_move_insn (quotient, const0_rtx);
3362 emit_jump_insn (gen_jump (label2));
3364 emit_label (label1);
3365 expand_dec (adjusted_op0, const1_rtx);
3366 tem = expand_binop (compute_mode, udiv_optab, adjusted_op0, op1,
3367 quotient, 1, OPTAB_LIB_WIDEN);
3368 if (tem != quotient)
3369 emit_move_insn (quotient, tem);
3370 expand_inc (quotient, const1_rtx);
3371 emit_label (label2);
3376 if (op1_is_constant && EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1))
3377 && INTVAL (op1) >= 0)
3379 /* This is extremely similar to the code for the unsigned case
3380 above. For 2.7 we should merge these variants, but for
3381 2.6.1 I don't want to touch the code for unsigned since that
3382 get used in C. The signed case will only be used by other
3386 unsigned HOST_WIDE_INT d = INTVAL (op1);
3387 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3388 build_int_2 (floor_log2 (d), 0),
3390 t2 = expand_binop (compute_mode, and_optab, op0,
3392 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3393 t3 = gen_reg_rtx (compute_mode);
3394 t3 = emit_store_flag (t3, NE, t2, const0_rtx,
3395 compute_mode, 1, 1);
3399 lab = gen_label_rtx ();
3400 emit_cmp_insn (t2, const0_rtx, EQ, NULL_RTX,
3401 compute_mode, 0, 0);
3402 emit_jump_insn (gen_beq (lab));
3403 expand_inc (t1, const1_rtx);
3408 quotient = force_operand (gen_rtx (PLUS, compute_mode,
3414 /* Try using an instruction that produces both the quotient and
3415 remainder, using truncation. We can easily compensate the
3416 quotient or remainder to get ceiling rounding, once we have the
3417 remainder. Notice that we compute also the final remainder
3418 value here, and return the result right away. */
3420 target = gen_reg_rtx (compute_mode);
3423 remainder= (GET_CODE (target) == REG
3424 ? target : gen_reg_rtx (compute_mode));
3425 quotient = gen_reg_rtx (compute_mode);
3429 quotient = (GET_CODE (target) == REG
3430 ? target : gen_reg_rtx (compute_mode));
3431 remainder = gen_reg_rtx (compute_mode);
3434 if (expand_twoval_binop (sdivmod_optab, op0, op1, quotient,
3437 /* This could be computed with a branch-less sequence.
3438 Save that for later. */
3440 rtx label = gen_label_rtx ();
3441 emit_cmp_insn (remainder, const0_rtx, EQ, NULL_RTX,
3442 compute_mode, 0, 0);
3443 emit_jump_insn (gen_beq (label));
3444 tem = expand_binop (compute_mode, xor_optab, op0, op1,
3445 NULL_RTX, 0, OPTAB_WIDEN);
3446 emit_cmp_insn (tem, const0_rtx, LT, NULL_RTX,
3447 compute_mode, 0, 0);
3448 emit_jump_insn (gen_blt (label));
3449 expand_inc (quotient, const1_rtx);
3450 expand_dec (remainder, op1);
3452 return gen_lowpart (mode, rem_flag ? remainder : quotient);
3455 /* No luck with division elimination or divmod. Have to do it
3456 by conditionally adjusting op0 *and* the result. */
3458 rtx label1, label2, label3, label4, label5;
3462 quotient = gen_reg_rtx (compute_mode);
3463 adjusted_op0 = copy_to_mode_reg (compute_mode, op0);
3464 label1 = gen_label_rtx ();
3465 label2 = gen_label_rtx ();
3466 label3 = gen_label_rtx ();
3467 label4 = gen_label_rtx ();
3468 label5 = gen_label_rtx ();
3469 emit_cmp_insn (op1, const0_rtx, LT, NULL_RTX,
3470 compute_mode, 0, 0);
3471 emit_jump_insn (gen_blt (label2));
3472 emit_cmp_insn (adjusted_op0, const0_rtx, GT, NULL_RTX,
3473 compute_mode, 0, 0);
3474 emit_jump_insn (gen_bgt (label1));
3475 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
3476 quotient, 0, OPTAB_LIB_WIDEN);
3477 if (tem != quotient)
3478 emit_move_insn (quotient, tem);
3479 emit_jump_insn (gen_jump (label5));
3481 emit_label (label1);
3482 expand_dec (adjusted_op0, const1_rtx);
3483 emit_jump_insn (gen_jump (label4));
3485 emit_label (label2);
3486 emit_cmp_insn (adjusted_op0, const0_rtx, LT, NULL_RTX,
3487 compute_mode, 0, 0);
3488 emit_jump_insn (gen_blt (label3));
3489 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
3490 quotient, 0, OPTAB_LIB_WIDEN);
3491 if (tem != quotient)
3492 emit_move_insn (quotient, tem);
3493 emit_jump_insn (gen_jump (label5));
3495 emit_label (label3);
3496 expand_inc (adjusted_op0, const1_rtx);
3497 emit_label (label4);
3498 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
3499 quotient, 0, OPTAB_LIB_WIDEN);
3500 if (tem != quotient)
3501 emit_move_insn (quotient, tem);
3502 expand_inc (quotient, const1_rtx);
3503 emit_label (label5);
3508 case EXACT_DIV_EXPR:
3509 if (op1_is_constant && HOST_BITS_PER_WIDE_INT >= size)
3511 HOST_WIDE_INT d = INTVAL (op1);
3512 unsigned HOST_WIDE_INT ml;
3516 post_shift = floor_log2 (d & -d);
3517 ml = invert_mod2n (d >> post_shift, size);
3518 t1 = expand_mult (compute_mode, op0, GEN_INT (ml), NULL_RTX,
3520 quotient = expand_shift (RSHIFT_EXPR, compute_mode, t1,
3521 build_int_2 (post_shift, 0),
3522 NULL_RTX, unsignedp);
3524 insn = get_last_insn ();
3526 = gen_rtx (EXPR_LIST, REG_EQUAL,
3527 gen_rtx (unsignedp ? UDIV : DIV, compute_mode,
3533 case ROUND_DIV_EXPR:
3534 case ROUND_MOD_EXPR:
3539 label = gen_label_rtx ();
3540 quotient = gen_reg_rtx (compute_mode);
3541 remainder = gen_reg_rtx (compute_mode);
3542 if (expand_twoval_binop (udivmod_optab, op0, op1, quotient, remainder, 1) == 0)
3545 quotient = expand_binop (compute_mode, udiv_optab, op0, op1,
3546 quotient, 1, OPTAB_LIB_WIDEN);
3547 tem = expand_mult (compute_mode, quotient, op1, NULL_RTX, 1);
3548 remainder = expand_binop (compute_mode, sub_optab, op0, tem,
3549 remainder, 1, OPTAB_LIB_WIDEN);
3551 tem = plus_constant (op1, -1);
3552 tem = expand_shift (RSHIFT_EXPR, compute_mode, tem,
3553 build_int_2 (1, 0), NULL_RTX, 1);
3554 emit_cmp_insn (remainder, tem, LEU, NULL_RTX, compute_mode, 0, 0);
3555 emit_jump_insn (gen_bleu (label));
3556 expand_inc (quotient, const1_rtx);
3557 expand_dec (remainder, op1);
3562 rtx abs_rem, abs_op1, tem, mask;
3564 label = gen_label_rtx ();
3565 quotient = gen_reg_rtx (compute_mode);
3566 remainder = gen_reg_rtx (compute_mode);
3567 if (expand_twoval_binop (sdivmod_optab, op0, op1, quotient, remainder, 0) == 0)
3570 quotient = expand_binop (compute_mode, sdiv_optab, op0, op1,
3571 quotient, 0, OPTAB_LIB_WIDEN);
3572 tem = expand_mult (compute_mode, quotient, op1, NULL_RTX, 0);
3573 remainder = expand_binop (compute_mode, sub_optab, op0, tem,
3574 remainder, 0, OPTAB_LIB_WIDEN);
3576 abs_rem = expand_abs (compute_mode, remainder, NULL_RTX, 0, 0);
3577 abs_op1 = expand_abs (compute_mode, op1, NULL_RTX, 0, 0);
3578 tem = expand_shift (LSHIFT_EXPR, compute_mode, abs_rem,
3579 build_int_2 (1, 0), NULL_RTX, 1);
3580 emit_cmp_insn (tem, abs_op1, LTU, NULL_RTX, compute_mode, 0, 0);
3581 emit_jump_insn (gen_bltu (label));
3582 tem = expand_binop (compute_mode, xor_optab, op0, op1,
3583 NULL_RTX, 0, OPTAB_WIDEN);
3584 mask = expand_shift (RSHIFT_EXPR, compute_mode, tem,
3585 build_int_2 (size - 1, 0), NULL_RTX, 0);
3586 tem = expand_binop (compute_mode, xor_optab, mask, const1_rtx,
3587 NULL_RTX, 0, OPTAB_WIDEN);
3588 tem = expand_binop (compute_mode, sub_optab, tem, mask,
3589 NULL_RTX, 0, OPTAB_WIDEN);
3590 expand_inc (quotient, tem);
3591 tem = expand_binop (compute_mode, xor_optab, mask, op1,
3592 NULL_RTX, 0, OPTAB_WIDEN);
3593 tem = expand_binop (compute_mode, sub_optab, tem, mask,
3594 NULL_RTX, 0, OPTAB_WIDEN);
3595 expand_dec (remainder, tem);
3598 return gen_lowpart (mode, rem_flag ? remainder : quotient);
3605 /* Try to produce the remainder directly without a library call. */
3606 remainder = sign_expand_binop (compute_mode, umod_optab, smod_optab,
3608 unsignedp, OPTAB_WIDEN);
3611 /* No luck there. Can we do remainder and divide at once
3612 without a library call? */
3613 remainder = gen_reg_rtx (compute_mode);
3614 if (! expand_twoval_binop ((unsignedp
3618 NULL_RTX, remainder, unsignedp))
3623 return gen_lowpart (mode, remainder);
3626 /* Produce the quotient. */
3627 /* Try a quotient insn, but not a library call. */
3628 quotient = sign_expand_binop (compute_mode, udiv_optab, sdiv_optab,
3629 op0, op1, rem_flag ? NULL_RTX : target,
3630 unsignedp, OPTAB_WIDEN);
3633 /* No luck there. Try a quotient-and-remainder insn,
3634 keeping the quotient alone. */
3635 quotient = gen_reg_rtx (compute_mode);
3636 if (! expand_twoval_binop (unsignedp ? udivmod_optab : sdivmod_optab,
3638 quotient, NULL_RTX, unsignedp))
3642 /* Still no luck. If we are not computing the remainder,
3643 use a library call for the quotient. */
3644 quotient = sign_expand_binop (compute_mode,
3645 udiv_optab, sdiv_optab,
3647 unsignedp, OPTAB_LIB_WIDEN);
3655 /* No divide instruction either. Use library for remainder. */
3656 remainder = sign_expand_binop (compute_mode, umod_optab, smod_optab,
3658 unsignedp, OPTAB_LIB_WIDEN);
3661 /* We divided. Now finish doing X - Y * (X / Y). */
3662 remainder = expand_mult (compute_mode, quotient, op1,
3663 NULL_RTX, unsignedp);
3664 remainder = expand_binop (compute_mode, sub_optab, op0,
3665 remainder, target, unsignedp,
3670 return gen_lowpart (mode, rem_flag ? remainder : quotient);
3673 /* Return a tree node with data type TYPE, describing the value of X.
3674 Usually this is an RTL_EXPR, if there is no obvious better choice.
3675 X may be an expression, however we only support those expressions
3676 generated by loop.c. */
3685 switch (GET_CODE (x))
3688 t = build_int_2 (INTVAL (x),
3689 TREE_UNSIGNED (type) || INTVAL (x) >= 0 ? 0 : -1);
3690 TREE_TYPE (t) = type;
3694 if (GET_MODE (x) == VOIDmode)
3696 t = build_int_2 (CONST_DOUBLE_LOW (x), CONST_DOUBLE_HIGH (x));
3697 TREE_TYPE (t) = type;
3703 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
3704 t = build_real (type, d);
3710 return fold (build (PLUS_EXPR, type, make_tree (type, XEXP (x, 0)),
3711 make_tree (type, XEXP (x, 1))));
3714 return fold (build (MINUS_EXPR, type, make_tree (type, XEXP (x, 0)),
3715 make_tree (type, XEXP (x, 1))));
3718 return fold (build1 (NEGATE_EXPR, type, make_tree (type, XEXP (x, 0))));
3721 return fold (build (MULT_EXPR, type, make_tree (type, XEXP (x, 0)),
3722 make_tree (type, XEXP (x, 1))));
3725 return fold (build (LSHIFT_EXPR, type, make_tree (type, XEXP (x, 0)),
3726 make_tree (type, XEXP (x, 1))));
3729 return fold (convert (type,
3730 build (RSHIFT_EXPR, unsigned_type (type),
3731 make_tree (unsigned_type (type),
3733 make_tree (type, XEXP (x, 1)))));
3736 return fold (convert (type,
3737 build (RSHIFT_EXPR, signed_type (type),
3738 make_tree (signed_type (type), XEXP (x, 0)),
3739 make_tree (type, XEXP (x, 1)))));
3742 if (TREE_CODE (type) != REAL_TYPE)
3743 t = signed_type (type);
3747 return fold (convert (type,
3748 build (TRUNC_DIV_EXPR, t,
3749 make_tree (t, XEXP (x, 0)),
3750 make_tree (t, XEXP (x, 1)))));
3752 t = unsigned_type (type);
3753 return fold (convert (type,
3754 build (TRUNC_DIV_EXPR, t,
3755 make_tree (t, XEXP (x, 0)),
3756 make_tree (t, XEXP (x, 1)))));
3758 t = make_node (RTL_EXPR);
3759 TREE_TYPE (t) = type;
3760 RTL_EXPR_RTL (t) = x;
3761 /* There are no insns to be output
3762 when this rtl_expr is used. */
3763 RTL_EXPR_SEQUENCE (t) = 0;
3768 /* Return an rtx representing the value of X * MULT + ADD.
3769 TARGET is a suggestion for where to store the result (an rtx).
3770 MODE is the machine mode for the computation.
3771 X and MULT must have mode MODE. ADD may have a different mode.
3772 So can X (defaults to same as MODE).
3773 UNSIGNEDP is non-zero to do unsigned multiplication.
3774 This may emit insns. */
3777 expand_mult_add (x, target, mult, add, mode, unsignedp)
3778 rtx x, target, mult, add;
3779 enum machine_mode mode;
3782 tree type = type_for_mode (mode, unsignedp);
3783 tree add_type = (GET_MODE (add) == VOIDmode
3784 ? type : type_for_mode (GET_MODE (add), unsignedp));
3785 tree result = fold (build (PLUS_EXPR, type,
3786 fold (build (MULT_EXPR, type,
3787 make_tree (type, x),
3788 make_tree (type, mult))),
3789 make_tree (add_type, add)));
3791 return expand_expr (result, target, VOIDmode, 0);
3794 /* Compute the logical-and of OP0 and OP1, storing it in TARGET
3795 and returning TARGET.
3797 If TARGET is 0, a pseudo-register or constant is returned. */
3800 expand_and (op0, op1, target)
3801 rtx op0, op1, target;
3803 enum machine_mode mode = VOIDmode;
3806 if (GET_MODE (op0) != VOIDmode)
3807 mode = GET_MODE (op0);
3808 else if (GET_MODE (op1) != VOIDmode)
3809 mode = GET_MODE (op1);
3811 if (mode != VOIDmode)
3812 tem = expand_binop (mode, and_optab, op0, op1, target, 0, OPTAB_LIB_WIDEN);
3813 else if (GET_CODE (op0) == CONST_INT && GET_CODE (op1) == CONST_INT)
3814 tem = GEN_INT (INTVAL (op0) & INTVAL (op1));
3820 else if (tem != target)
3821 emit_move_insn (target, tem);
3825 /* Emit a store-flags instruction for comparison CODE on OP0 and OP1
3826 and storing in TARGET. Normally return TARGET.
3827 Return 0 if that cannot be done.
3829 MODE is the mode to use for OP0 and OP1 should they be CONST_INTs. If
3830 it is VOIDmode, they cannot both be CONST_INT.
3832 UNSIGNEDP is for the case where we have to widen the operands
3833 to perform the operation. It says to use zero-extension.
3835 NORMALIZEP is 1 if we should convert the result to be either zero
3836 or one one. Normalize is -1 if we should convert the result to be
3837 either zero or -1. If NORMALIZEP is zero, the result will be left
3838 "raw" out of the scc insn. */
3841 emit_store_flag (target, code, op0, op1, mode, unsignedp, normalizep)
3845 enum machine_mode mode;
3850 enum insn_code icode;
3851 enum machine_mode compare_mode;
3852 enum machine_mode target_mode = GET_MODE (target);
3855 rtx pattern, comparison;
3857 /* If one operand is constant, make it the second one. Only do this
3858 if the other operand is not constant as well. */
3860 if ((CONSTANT_P (op0) && ! CONSTANT_P (op1))
3861 || (GET_CODE (op0) == CONST_INT && GET_CODE (op1) != CONST_INT))
3866 code = swap_condition (code);
3869 if (mode == VOIDmode)
3870 mode = GET_MODE (op0);
3872 /* For some comparisons with 1 and -1, we can convert this to
3873 comparisons with zero. This will often produce more opportunities for
3874 store-flag insns. */
3879 if (op1 == const1_rtx)
3880 op1 = const0_rtx, code = LE;
3883 if (op1 == constm1_rtx)
3884 op1 = const0_rtx, code = LT;
3887 if (op1 == const1_rtx)
3888 op1 = const0_rtx, code = GT;
3891 if (op1 == constm1_rtx)
3892 op1 = const0_rtx, code = GE;
3895 if (op1 == const1_rtx)
3896 op1 = const0_rtx, code = NE;
3899 if (op1 == const1_rtx)
3900 op1 = const0_rtx, code = EQ;
3904 /* From now on, we won't change CODE, so set ICODE now. */
3905 icode = setcc_gen_code[(int) code];
3907 /* If this is A < 0 or A >= 0, we can do this by taking the ones
3908 complement of A (for GE) and shifting the sign bit to the low bit. */
3909 if (op1 == const0_rtx && (code == LT || code == GE)
3910 && GET_MODE_CLASS (mode) == MODE_INT
3911 && (normalizep || STORE_FLAG_VALUE == 1
3912 || (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3913 && (STORE_FLAG_VALUE
3914 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1)))))
3918 /* If the result is to be wider than OP0, it is best to convert it
3919 first. If it is to be narrower, it is *incorrect* to convert it
3921 if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (mode))
3923 op0 = protect_from_queue (op0, 0);
3924 op0 = convert_modes (target_mode, mode, op0, 0);
3928 if (target_mode != mode)
3932 op0 = expand_unop (mode, one_cmpl_optab, op0, subtarget, 0);
3934 if (normalizep || STORE_FLAG_VALUE == 1)
3935 /* If we are supposed to produce a 0/1 value, we want to do
3936 a logical shift from the sign bit to the low-order bit; for
3937 a -1/0 value, we do an arithmetic shift. */
3938 op0 = expand_shift (RSHIFT_EXPR, mode, op0,
3939 size_int (GET_MODE_BITSIZE (mode) - 1),
3940 subtarget, normalizep != -1);
3942 if (mode != target_mode)
3943 op0 = convert_modes (target_mode, mode, op0, 0);
3948 if (icode != CODE_FOR_nothing)
3950 /* We think we may be able to do this with a scc insn. Emit the
3951 comparison and then the scc insn.
3953 compare_from_rtx may call emit_queue, which would be deleted below
3954 if the scc insn fails. So call it ourselves before setting LAST. */
3957 last = get_last_insn ();
3960 = compare_from_rtx (op0, op1, code, unsignedp, mode, NULL_RTX, 0);
3961 if (GET_CODE (comparison) == CONST_INT)
3962 return (comparison == const0_rtx ? const0_rtx
3963 : normalizep == 1 ? const1_rtx
3964 : normalizep == -1 ? constm1_rtx
3967 /* If the code of COMPARISON doesn't match CODE, something is
3968 wrong; we can no longer be sure that we have the operation.
3969 We could handle this case, but it should not happen. */
3971 if (GET_CODE (comparison) != code)
3974 /* Get a reference to the target in the proper mode for this insn. */
3975 compare_mode = insn_operand_mode[(int) icode][0];
3977 if (preserve_subexpressions_p ()
3978 || ! (*insn_operand_predicate[(int) icode][0]) (subtarget, compare_mode))
3979 subtarget = gen_reg_rtx (compare_mode);
3981 pattern = GEN_FCN (icode) (subtarget);
3984 emit_insn (pattern);
3986 /* If we are converting to a wider mode, first convert to
3987 TARGET_MODE, then normalize. This produces better combining
3988 opportunities on machines that have a SIGN_EXTRACT when we are
3989 testing a single bit. This mostly benefits the 68k.
3991 If STORE_FLAG_VALUE does not have the sign bit set when
3992 interpreted in COMPARE_MODE, we can do this conversion as
3993 unsigned, which is usually more efficient. */
3994 if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (compare_mode))
3996 convert_move (target, subtarget,
3997 (GET_MODE_BITSIZE (compare_mode)
3998 <= HOST_BITS_PER_WIDE_INT)
3999 && 0 == (STORE_FLAG_VALUE
4000 & ((HOST_WIDE_INT) 1
4001 << (GET_MODE_BITSIZE (compare_mode) -1))));
4003 compare_mode = target_mode;
4008 /* If we want to keep subexpressions around, don't reuse our
4011 if (preserve_subexpressions_p ())
4014 /* Now normalize to the proper value in COMPARE_MODE. Sometimes
4015 we don't have to do anything. */
4016 if (normalizep == 0 || normalizep == STORE_FLAG_VALUE)
4018 else if (normalizep == - STORE_FLAG_VALUE)
4019 op0 = expand_unop (compare_mode, neg_optab, op0, subtarget, 0);
4021 /* We don't want to use STORE_FLAG_VALUE < 0 below since this
4022 makes it hard to use a value of just the sign bit due to
4023 ANSI integer constant typing rules. */
4024 else if (GET_MODE_BITSIZE (compare_mode) <= HOST_BITS_PER_WIDE_INT
4025 && (STORE_FLAG_VALUE
4026 & ((HOST_WIDE_INT) 1
4027 << (GET_MODE_BITSIZE (compare_mode) - 1))))
4028 op0 = expand_shift (RSHIFT_EXPR, compare_mode, op0,
4029 size_int (GET_MODE_BITSIZE (compare_mode) - 1),
4030 subtarget, normalizep == 1);
4031 else if (STORE_FLAG_VALUE & 1)
4033 op0 = expand_and (op0, const1_rtx, subtarget);
4034 if (normalizep == -1)
4035 op0 = expand_unop (compare_mode, neg_optab, op0, op0, 0);
4040 /* If we were converting to a smaller mode, do the
4042 if (target_mode != compare_mode)
4044 convert_move (target, op0, 0);
4053 delete_insns_since (last);
4055 /* If expensive optimizations, use different pseudo registers for each
4056 insn, instead of reusing the same pseudo. This leads to better CSE,
4057 but slows down the compiler, since there are more pseudos */
4058 subtarget = (!flag_expensive_optimizations
4059 && (target_mode == mode)) ? target : NULL_RTX;
4061 /* If we reached here, we can't do this with a scc insn. However, there
4062 are some comparisons that can be done directly. For example, if
4063 this is an equality comparison of integers, we can try to exclusive-or
4064 (or subtract) the two operands and use a recursive call to try the
4065 comparison with zero. Don't do any of these cases if branches are
4069 && GET_MODE_CLASS (mode) == MODE_INT && (code == EQ || code == NE)
4070 && op1 != const0_rtx)
4072 tem = expand_binop (mode, xor_optab, op0, op1, subtarget, 1,
4076 tem = expand_binop (mode, sub_optab, op0, op1, subtarget, 1,
4079 tem = emit_store_flag (target, code, tem, const0_rtx,
4080 mode, unsignedp, normalizep);
4082 delete_insns_since (last);
4086 /* Some other cases we can do are EQ, NE, LE, and GT comparisons with
4087 the constant zero. Reject all other comparisons at this point. Only
4088 do LE and GT if branches are expensive since they are expensive on
4089 2-operand machines. */
4091 if (BRANCH_COST == 0
4092 || GET_MODE_CLASS (mode) != MODE_INT || op1 != const0_rtx
4093 || (code != EQ && code != NE
4094 && (BRANCH_COST <= 1 || (code != LE && code != GT))))
4097 /* See what we need to return. We can only return a 1, -1, or the
4100 if (normalizep == 0)
4102 if (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4103 normalizep = STORE_FLAG_VALUE;
4105 else if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4106 && (STORE_FLAG_VALUE
4107 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1)))
4113 /* Try to put the result of the comparison in the sign bit. Assume we can't
4114 do the necessary operation below. */
4118 /* To see if A <= 0, compute (A | (A - 1)). A <= 0 iff that result has
4119 the sign bit set. */
4123 /* This is destructive, so SUBTARGET can't be OP0. */
4124 if (rtx_equal_p (subtarget, op0))
4127 tem = expand_binop (mode, sub_optab, op0, const1_rtx, subtarget, 0,
4130 tem = expand_binop (mode, ior_optab, op0, tem, subtarget, 0,
4134 /* To see if A > 0, compute (((signed) A) << BITS) - A, where BITS is the
4135 number of bits in the mode of OP0, minus one. */
4139 if (rtx_equal_p (subtarget, op0))
4142 tem = expand_shift (RSHIFT_EXPR, mode, op0,
4143 size_int (GET_MODE_BITSIZE (mode) - 1),
4145 tem = expand_binop (mode, sub_optab, tem, op0, subtarget, 0,
4149 if (code == EQ || code == NE)
4151 /* For EQ or NE, one way to do the comparison is to apply an operation
4152 that converts the operand into a positive number if it is non-zero
4153 or zero if it was originally zero. Then, for EQ, we subtract 1 and
4154 for NE we negate. This puts the result in the sign bit. Then we
4155 normalize with a shift, if needed.
4157 Two operations that can do the above actions are ABS and FFS, so try
4158 them. If that doesn't work, and MODE is smaller than a full word,
4159 we can use zero-extension to the wider mode (an unsigned conversion)
4160 as the operation. */
4162 if (abs_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
4163 tem = expand_unop (mode, abs_optab, op0, subtarget, 1);
4164 else if (ffs_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
4165 tem = expand_unop (mode, ffs_optab, op0, subtarget, 1);
4166 else if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
4168 op0 = protect_from_queue (op0, 0);
4169 tem = convert_modes (word_mode, mode, op0, 1);
4176 tem = expand_binop (mode, sub_optab, tem, const1_rtx, subtarget,
4179 tem = expand_unop (mode, neg_optab, tem, subtarget, 0);
4182 /* If we couldn't do it that way, for NE we can "or" the two's complement
4183 of the value with itself. For EQ, we take the one's complement of
4184 that "or", which is an extra insn, so we only handle EQ if branches
4187 if (tem == 0 && (code == NE || BRANCH_COST > 1))
4189 if (rtx_equal_p (subtarget, op0))
4192 tem = expand_unop (mode, neg_optab, op0, subtarget, 0);
4193 tem = expand_binop (mode, ior_optab, tem, op0, subtarget, 0,
4196 if (tem && code == EQ)
4197 tem = expand_unop (mode, one_cmpl_optab, tem, subtarget, 0);
4201 if (tem && normalizep)
4202 tem = expand_shift (RSHIFT_EXPR, mode, tem,
4203 size_int (GET_MODE_BITSIZE (mode) - 1),
4204 subtarget, normalizep == 1);
4208 if (GET_MODE (tem) != target_mode)
4210 convert_move (target, tem, 0);
4213 else if (!subtarget)
4215 emit_move_insn (target, tem);
4220 delete_insns_since (last);
4224 emit_jump_insn ((*bcc_gen_fctn[(int) code]) (label));
4225 emit_move_insn (target, const1_rtx);