1 /* Medium-level subroutines: convert bit-field store and extract
2 and shifts, multiplies and divides to rtl instructions.
3 Copyright (C) 1987, 1988, 1989, 1992, 1993 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
26 #include "insn-flags.h"
27 #include "insn-codes.h"
28 #include "insn-config.h"
33 static rtx extract_split_bit_field ();
34 static rtx extract_fixed_bit_field ();
35 static void store_split_bit_field ();
36 static void store_fixed_bit_field ();
37 static rtx mask_rtx ();
38 static rtx lshift_value ();
40 #define CEIL(x,y) (((x) + (y) - 1) / (y))
42 /* Non-zero means multiply instructions are cheaper than shifts. */
43 int mult_is_very_cheap;
45 /* Non-zero means divides or modulus operations are relatively cheap for
46 powers of two, so don't use branches; emit the operation instead.
47 Usually, this will mean that the MD file will emit non-branch
50 static int sdiv_pow2_cheap, smod_pow2_cheap;
52 /* For compilers that support multiple targets with different word sizes,
53 MAX_BITS_PER_WORD contains the biggest value of BITS_PER_WORD. An example
54 is the H8/300(H) compiler. */
56 #ifndef MAX_BITS_PER_WORD
57 #define MAX_BITS_PER_WORD BITS_PER_WORD
60 /* Cost of various pieces of RTL. */
61 static int add_cost, mult_cost, negate_cost, zero_cost;
62 static int shift_cost[MAX_BITS_PER_WORD];
63 static int shiftadd_cost[MAX_BITS_PER_WORD];
64 static int shiftsub_cost[MAX_BITS_PER_WORD];
70 /* This is "some random pseudo register" for purposes of calling recog
71 to see what insns exist. */
72 rtx reg = gen_rtx (REG, word_mode, FIRST_PSEUDO_REGISTER);
73 rtx shift_insn, shiftadd_insn, shiftsub_insn;
79 /* Since we are on the permanent obstack, we must be sure we save this
80 spot AFTER we call start_sequence, since it will reuse the rtl it
83 free_point = (char *) oballoc (0);
85 zero_cost = rtx_cost (const0_rtx, 0);
86 add_cost = rtx_cost (gen_rtx (PLUS, word_mode, reg, reg), SET);
88 shift_insn = emit_insn (gen_rtx (SET, VOIDmode, reg,
89 gen_rtx (ASHIFT, word_mode, reg,
92 shiftadd_insn = emit_insn (gen_rtx (SET, VOIDmode, reg,
93 gen_rtx (PLUS, word_mode,
94 gen_rtx (MULT, word_mode,
98 shiftsub_insn = emit_insn (gen_rtx (SET, VOIDmode, reg,
99 gen_rtx (MINUS, word_mode,
100 gen_rtx (MULT, word_mode,
107 shiftadd_cost[0] = shiftsub_cost[0] = add_cost;
109 for (m = 1; m < BITS_PER_WORD; m++)
111 shift_cost[m] = shiftadd_cost[m] = shiftsub_cost[m] = 32000;
113 XEXP (SET_SRC (PATTERN (shift_insn)), 1) = GEN_INT (m);
114 if (recog (PATTERN (shift_insn), shift_insn, &dummy) >= 0)
115 shift_cost[m] = rtx_cost (SET_SRC (PATTERN (shift_insn)), SET);
117 XEXP (XEXP (SET_SRC (PATTERN (shiftadd_insn)), 0), 1)
118 = GEN_INT ((HOST_WIDE_INT) 1 << m);
119 if (recog (PATTERN (shiftadd_insn), shiftadd_insn, &dummy) >= 0)
120 shiftadd_cost[m] = rtx_cost (SET_SRC (PATTERN (shiftadd_insn)), SET);
122 XEXP (XEXP (SET_SRC (PATTERN (shiftsub_insn)), 0), 1)
123 = GEN_INT ((HOST_WIDE_INT) 1 << m);
124 if (recog (PATTERN (shiftsub_insn), shiftsub_insn, &dummy) >= 0)
125 shiftsub_cost[m] = rtx_cost (SET_SRC (PATTERN (shiftsub_insn)), SET);
128 mult_cost = rtx_cost (gen_rtx (MULT, word_mode, reg, reg), SET);
129 /* For gcc 2.4 keep MULT_COST small to avoid really slow searches
131 mult_cost = MIN (12 * add_cost, mult_cost);
132 negate_cost = rtx_cost (gen_rtx (NEG, word_mode, reg), SET);
134 /* 999999 is chosen to avoid any plausible faster special case. */
136 = (rtx_cost (gen_rtx (MULT, word_mode, reg, GEN_INT (999999)), SET)
137 < rtx_cost (gen_rtx (ASHIFT, word_mode, reg, GEN_INT (7)), SET));
140 = (rtx_cost (gen_rtx (DIV, word_mode, reg, GEN_INT (32)), SET)
143 = (rtx_cost (gen_rtx (MOD, word_mode, reg, GEN_INT (32)), SET)
146 /* Free the objects we just allocated. */
151 /* Return an rtx representing minus the value of X.
152 MODE is the intended mode of the result,
153 useful if X is a CONST_INT. */
157 enum machine_mode mode;
160 if (GET_CODE (x) == CONST_INT)
162 HOST_WIDE_INT val = - INTVAL (x);
163 if (GET_MODE_BITSIZE (mode) < HOST_BITS_PER_WIDE_INT)
165 /* Sign extend the value from the bits that are significant. */
166 if (val & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1)))
167 val |= (HOST_WIDE_INT) (-1) << GET_MODE_BITSIZE (mode);
169 val &= ((HOST_WIDE_INT) 1 << GET_MODE_BITSIZE (mode)) - 1;
171 return GEN_INT (val);
174 return expand_unop (GET_MODE (x), neg_optab, x, NULL_RTX, 0);
177 /* Generate code to store value from rtx VALUE
178 into a bit-field within structure STR_RTX
179 containing BITSIZE bits starting at bit BITNUM.
180 FIELDMODE is the machine-mode of the FIELD_DECL node for this field.
181 ALIGN is the alignment that STR_RTX is known to have, measured in bytes.
182 TOTAL_SIZE is the size of the structure in bytes, or -1 if varying. */
184 /* ??? Note that there are two different ideas here for how
185 to determine the size to count bits within, for a register.
186 One is BITS_PER_WORD, and the other is the size of operand 3
187 of the insv pattern. (The latter assumes that an n-bit machine
188 will be able to insert bit fields up to n bits wide.)
189 It isn't certain that either of these is right.
190 extract_bit_field has the same quandary. */
193 store_bit_field (str_rtx, bitsize, bitnum, fieldmode, value, align, total_size)
195 register int bitsize;
197 enum machine_mode fieldmode;
202 int unit = (GET_CODE (str_rtx) == MEM) ? BITS_PER_UNIT : BITS_PER_WORD;
203 register int offset = bitnum / unit;
204 register int bitpos = bitnum % unit;
205 register rtx op0 = str_rtx;
207 if (GET_CODE (str_rtx) == MEM && ! MEM_IN_STRUCT_P (str_rtx))
210 /* Discount the part of the structure before the desired byte.
211 We need to know how many bytes are safe to reference after it. */
213 total_size -= (bitpos / BIGGEST_ALIGNMENT
214 * (BIGGEST_ALIGNMENT / BITS_PER_UNIT));
216 while (GET_CODE (op0) == SUBREG)
218 /* The following line once was done only if WORDS_BIG_ENDIAN,
219 but I think that is a mistake. WORDS_BIG_ENDIAN is
220 meaningful at a much higher level; when structures are copied
221 between memory and regs, the higher-numbered regs
222 always get higher addresses. */
223 offset += SUBREG_WORD (op0);
224 /* We used to adjust BITPOS here, but now we do the whole adjustment
225 right after the loop. */
226 op0 = SUBREG_REG (op0);
230 /* If OP0 is a register, BITPOS must count within a word.
231 But as we have it, it counts within whatever size OP0 now has.
232 On a bigendian machine, these are not the same, so convert. */
233 if (GET_CODE (op0) != MEM && unit > GET_MODE_BITSIZE (GET_MODE (op0)))
234 bitpos += unit - GET_MODE_BITSIZE (GET_MODE (op0));
237 value = protect_from_queue (value, 0);
240 value = force_not_mem (value);
242 /* Note that the adjustment of BITPOS above has no effect on whether
243 BITPOS is 0 in a REG bigger than a word. */
244 if (GET_MODE_SIZE (fieldmode) >= UNITS_PER_WORD
245 && (! STRICT_ALIGNMENT || GET_CODE (op0) != MEM)
246 && bitpos == 0 && bitsize == GET_MODE_BITSIZE (fieldmode))
248 /* Storing in a full-word or multi-word field in a register
249 can be done with just SUBREG. */
250 if (GET_MODE (op0) != fieldmode)
251 if (GET_CODE (op0) == REG)
252 op0 = gen_rtx (SUBREG, fieldmode, op0, offset);
254 op0 = change_address (op0, fieldmode,
255 plus_constant (XEXP (op0, 0), offset));
256 emit_move_insn (op0, value);
260 /* Storing an lsb-aligned field in a register
261 can be done with a movestrict instruction. */
263 if (GET_CODE (op0) != MEM
265 && bitpos + bitsize == unit
269 && bitsize == GET_MODE_BITSIZE (fieldmode)
270 && (GET_MODE (op0) == fieldmode
271 || (movstrict_optab->handlers[(int) fieldmode].insn_code
272 != CODE_FOR_nothing)))
274 /* Get appropriate low part of the value being stored. */
275 if (GET_CODE (value) == CONST_INT || GET_CODE (value) == REG)
276 value = gen_lowpart (fieldmode, value);
277 else if (!(GET_CODE (value) == SYMBOL_REF
278 || GET_CODE (value) == LABEL_REF
279 || GET_CODE (value) == CONST))
280 value = convert_to_mode (fieldmode, value, 0);
282 if (GET_MODE (op0) == fieldmode)
283 emit_move_insn (op0, value);
286 int icode = movstrict_optab->handlers[(int) fieldmode].insn_code;
287 if(! (*insn_operand_predicate[icode][1]) (value, fieldmode))
288 value = copy_to_mode_reg (fieldmode, value);
289 emit_insn (GEN_FCN (icode)
290 (gen_rtx (SUBREG, fieldmode, op0, offset), value));
295 /* Handle fields bigger than a word. */
297 if (bitsize > BITS_PER_WORD)
299 /* Here we transfer the words of the field
300 in the order least significant first.
301 This is because the most significant word is the one which may
302 be less than full. */
304 int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD;
307 /* This is the mode we must force value to, so that there will be enough
308 subwords to extract. Note that fieldmode will often (always?) be
309 VOIDmode, because that is what store_field uses to indicate that this
310 is a bit field, but passing VOIDmode to operand_subword_force will
311 result in an abort. */
312 fieldmode = mode_for_size (nwords * BITS_PER_WORD, MODE_INT, 0);
314 for (i = 0; i < nwords; i++)
316 /* If I is 0, use the low-order word in both field and target;
317 if I is 1, use the next to lowest word; and so on. */
318 int wordnum = (WORDS_BIG_ENDIAN ? nwords - i - 1 : i);
319 int bit_offset = (WORDS_BIG_ENDIAN
320 ? MAX (bitsize - (i + 1) * BITS_PER_WORD, 0)
321 : i * BITS_PER_WORD);
322 store_bit_field (op0, MIN (BITS_PER_WORD,
323 bitsize - i * BITS_PER_WORD),
324 bitnum + bit_offset, word_mode,
325 operand_subword_force (value, wordnum, fieldmode),
331 /* From here on we can assume that the field to be stored in is
332 a full-word (whatever type that is), since it is shorter than a word. */
334 /* OFFSET is the number of words or bytes (UNIT says which)
335 from STR_RTX to the first word or byte containing part of the field. */
337 if (GET_CODE (op0) == REG)
340 || GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD)
341 op0 = gen_rtx (SUBREG, TYPE_MODE (type_for_size (BITS_PER_WORD, 0)),
347 op0 = protect_from_queue (op0, 1);
350 /* Now OFFSET is nonzero only if OP0 is memory
351 and is therefore always measured in bytes. */
355 && !(bitsize == 1 && GET_CODE (value) == CONST_INT)
356 /* Ensure insv's size is wide enough for this field. */
357 && (GET_MODE_BITSIZE (insn_operand_mode[(int) CODE_FOR_insv][3])
360 int xbitpos = bitpos;
363 rtx last = get_last_insn ();
365 enum machine_mode maxmode
366 = insn_operand_mode[(int) CODE_FOR_insv][3];
368 int save_volatile_ok = volatile_ok;
371 /* If this machine's insv can only insert into a register, or if we
372 are to force MEMs into a register, copy OP0 into a register and
373 save it back later. */
374 if (GET_CODE (op0) == MEM
376 || ! ((*insn_operand_predicate[(int) CODE_FOR_insv][0])
380 enum machine_mode bestmode;
382 /* Get the mode to use for inserting into this field. If OP0 is
383 BLKmode, get the smallest mode consistent with the alignment. If
384 OP0 is a non-BLKmode object that is no wider than MAXMODE, use its
385 mode. Otherwise, use the smallest mode containing the field. */
387 if (GET_MODE (op0) == BLKmode
388 || GET_MODE_SIZE (GET_MODE (op0)) > GET_MODE_SIZE (maxmode))
390 = get_best_mode (bitsize, bitnum, align * BITS_PER_UNIT, maxmode,
391 MEM_VOLATILE_P (op0));
393 bestmode = GET_MODE (op0);
395 if (bestmode == VOIDmode)
398 /* Adjust address to point to the containing unit of that mode. */
399 unit = GET_MODE_BITSIZE (bestmode);
400 /* Compute offset as multiple of this unit, counting in bytes. */
401 offset = (bitnum / unit) * GET_MODE_SIZE (bestmode);
402 bitpos = bitnum % unit;
403 op0 = change_address (op0, bestmode,
404 plus_constant (XEXP (op0, 0), offset));
406 /* Fetch that unit, store the bitfield in it, then store the unit. */
407 tempreg = copy_to_reg (op0);
408 store_bit_field (tempreg, bitsize, bitpos, fieldmode, value,
410 emit_move_insn (op0, tempreg);
413 volatile_ok = save_volatile_ok;
415 /* Add OFFSET into OP0's address. */
416 if (GET_CODE (xop0) == MEM)
417 xop0 = change_address (xop0, byte_mode,
418 plus_constant (XEXP (xop0, 0), offset));
420 /* If xop0 is a register, we need it in MAXMODE
421 to make it acceptable to the format of insv. */
422 if (GET_CODE (xop0) == SUBREG)
423 PUT_MODE (xop0, maxmode);
424 if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode)
425 xop0 = gen_rtx (SUBREG, maxmode, xop0, 0);
427 /* On big-endian machines, we count bits from the most significant.
428 If the bit field insn does not, we must invert. */
430 #if BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN
431 xbitpos = unit - bitsize - xbitpos;
433 /* We have been counting XBITPOS within UNIT.
434 Count instead within the size of the register. */
436 if (GET_CODE (xop0) != MEM)
437 xbitpos += GET_MODE_BITSIZE (maxmode) - unit;
439 unit = GET_MODE_BITSIZE (maxmode);
441 /* Convert VALUE to maxmode (which insv insn wants) in VALUE1. */
443 if (GET_MODE (value) != maxmode)
445 if (GET_MODE_BITSIZE (GET_MODE (value)) >= bitsize)
447 /* Optimization: Don't bother really extending VALUE
448 if it has all the bits we will actually use. However,
449 if we must narrow it, be sure we do it correctly. */
451 if (GET_MODE_SIZE (GET_MODE (value)) < GET_MODE_SIZE (maxmode))
453 /* Avoid making subreg of a subreg, or of a mem. */
454 if (GET_CODE (value1) != REG)
455 value1 = copy_to_reg (value1);
456 value1 = gen_rtx (SUBREG, maxmode, value1, 0);
459 value1 = gen_lowpart (maxmode, value1);
461 else if (!CONSTANT_P (value))
462 /* Parse phase is supposed to make VALUE's data type
463 match that of the component reference, which is a type
464 at least as wide as the field; so VALUE should have
465 a mode that corresponds to that type. */
469 /* If this machine's insv insists on a register,
470 get VALUE1 into a register. */
471 if (! ((*insn_operand_predicate[(int) CODE_FOR_insv][3])
473 value1 = force_reg (maxmode, value1);
475 pat = gen_insv (xop0, GEN_INT (bitsize), GEN_INT (xbitpos), value1);
480 delete_insns_since (last);
481 store_fixed_bit_field (op0, offset, bitsize, bitpos, value, align);
487 /* Insv is not available; store using shifts and boolean ops. */
488 store_fixed_bit_field (op0, offset, bitsize, bitpos, value, align);
492 /* Use shifts and boolean operations to store VALUE
493 into a bit field of width BITSIZE
494 in a memory location specified by OP0 except offset by OFFSET bytes.
495 (OFFSET must be 0 if OP0 is a register.)
496 The field starts at position BITPOS within the byte.
497 (If OP0 is a register, it may be a full word or a narrower mode,
498 but BITPOS still counts within a full word,
499 which is significant on bigendian machines.)
500 STRUCT_ALIGN is the alignment the structure is known to have (in bytes).
502 Note that protect_from_queue has already been done on OP0 and VALUE. */
505 store_fixed_bit_field (op0, offset, bitsize, bitpos, value, struct_align)
507 register int offset, bitsize, bitpos;
511 register enum machine_mode mode;
512 int total_bits = BITS_PER_WORD;
517 /* There is a case not handled here:
518 a structure with a known alignment of just a halfword
519 and a field split across two aligned halfwords within the structure.
520 Or likewise a structure with a known alignment of just a byte
521 and a field split across two bytes.
522 Such cases are not supposed to be able to occur. */
524 if (GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
528 /* Special treatment for a bit field split across two registers. */
529 if (bitsize + bitpos > BITS_PER_WORD)
531 store_split_bit_field (op0, bitsize, bitpos,
532 value, BITS_PER_WORD);
538 /* Get the proper mode to use for this field. We want a mode that
539 includes the entire field. If such a mode would be larger than
540 a word, we won't be doing the extraction the normal way. */
542 mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT,
543 struct_align * BITS_PER_UNIT, word_mode,
544 GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0));
546 if (mode == VOIDmode)
548 /* The only way this should occur is if the field spans word
550 store_split_bit_field (op0,
551 bitsize, bitpos + offset * BITS_PER_UNIT,
552 value, struct_align);
556 total_bits = GET_MODE_BITSIZE (mode);
558 /* Get ref to an aligned byte, halfword, or word containing the field.
559 Adjust BITPOS to be position within a word,
560 and OFFSET to be the offset of that word.
561 Then alter OP0 to refer to that word. */
562 bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT;
563 offset -= (offset % (total_bits / BITS_PER_UNIT));
564 op0 = change_address (op0, mode,
565 plus_constant (XEXP (op0, 0), offset));
568 mode = GET_MODE (op0);
570 /* Now MODE is either some integral mode for a MEM as OP0,
571 or is a full-word for a REG as OP0. TOTAL_BITS corresponds.
572 The bit field is contained entirely within OP0.
573 BITPOS is the starting bit number within OP0.
574 (OP0's mode may actually be narrower than MODE.) */
577 /* BITPOS is the distance between our msb
578 and that of the containing datum.
579 Convert it to the distance from the lsb. */
581 bitpos = total_bits - bitsize - bitpos;
583 /* Now BITPOS is always the distance between our lsb
586 /* Shift VALUE left by BITPOS bits. If VALUE is not constant,
587 we must first convert its mode to MODE. */
589 if (GET_CODE (value) == CONST_INT)
591 register HOST_WIDE_INT v = INTVAL (value);
593 if (bitsize < HOST_BITS_PER_WIDE_INT)
594 v &= ((HOST_WIDE_INT) 1 << bitsize) - 1;
598 else if ((bitsize < HOST_BITS_PER_WIDE_INT
599 && v == ((HOST_WIDE_INT) 1 << bitsize) - 1)
600 || (bitsize == HOST_BITS_PER_WIDE_INT && v == -1))
603 value = lshift_value (mode, value, bitpos, bitsize);
607 int must_and = (GET_MODE_BITSIZE (GET_MODE (value)) != bitsize
608 && bitpos + bitsize != GET_MODE_BITSIZE (mode));
610 if (GET_MODE (value) != mode)
612 /* If VALUE is a floating-point mode, access it as an integer
613 of the corresponding size, then convert it. This can occur on
614 a machine with 64 bit registers that uses SFmode for float. */
615 if (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT)
617 if (GET_CODE (value) != REG)
618 value = copy_to_reg (value);
620 = gen_rtx (SUBREG, word_mode, value, 0);
623 if ((GET_CODE (value) == REG || GET_CODE (value) == SUBREG)
624 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (value)))
625 value = gen_lowpart (mode, value);
627 value = convert_to_mode (mode, value, 1);
631 value = expand_binop (mode, and_optab, value,
632 mask_rtx (mode, 0, bitsize, 0),
633 NULL_RTX, 1, OPTAB_LIB_WIDEN);
635 value = expand_shift (LSHIFT_EXPR, mode, value,
636 build_int_2 (bitpos, 0), NULL_RTX, 1);
639 /* Now clear the chosen bits in OP0,
640 except that if VALUE is -1 we need not bother. */
642 subtarget = (GET_CODE (op0) == REG || ! flag_force_mem) ? op0 : 0;
646 temp = expand_binop (mode, and_optab, op0,
647 mask_rtx (mode, bitpos, bitsize, 1),
648 subtarget, 1, OPTAB_LIB_WIDEN);
654 /* Now logical-or VALUE into OP0, unless it is zero. */
657 temp = expand_binop (mode, ior_optab, temp, value,
658 subtarget, 1, OPTAB_LIB_WIDEN);
660 emit_move_insn (op0, temp);
663 /* Store a bit field that is split across multiple accessible memory objects.
665 OP0 is the REG, SUBREG or MEM rtx for the first of the objects.
666 BITSIZE is the field width; BITPOS the position of its first bit
668 VALUE is the value to store.
669 ALIGN is the known alignment of OP0, measured in bytes.
670 This is also the size of the memory objects to be used.
672 This does not yet handle fields wider than BITS_PER_WORD. */
675 store_split_bit_field (op0, bitsize, bitpos, value, align)
681 int unit = align * BITS_PER_UNIT;
685 if (GET_CODE (value) == CONST_DOUBLE
686 && (word = gen_lowpart_common (word_mode, value)) != 0)
689 if (CONSTANT_P (value) && GET_CODE (value) != CONST_INT)
690 value = copy_to_mode_reg (word_mode, value);
692 while (bitsdone < bitsize)
699 offset = (bitpos + bitsdone) / unit;
700 thispos = (bitpos + bitsdone) % unit;
702 thissize = unit - offset * BITS_PER_UNIT % unit;
705 /* Fetch successively less significant portions. */
706 if (GET_CODE (value) == CONST_INT)
707 part = GEN_INT (((unsigned HOST_WIDE_INT) (INTVAL (value))
708 >> (bitsize - bitsdone - thissize))
709 & (((HOST_WIDE_INT) 1 << thissize) - 1));
711 /* The args are chosen so that the last part
713 part = extract_fixed_bit_field (word_mode, value, 0, thissize,
714 BITS_PER_WORD - bitsize + bitsdone,
717 /* Fetch successively more significant portions. */
718 if (GET_CODE (value) == CONST_INT)
719 part = GEN_INT (((unsigned HOST_WIDE_INT) (INTVAL (value)) >> bitsdone)
720 & (((HOST_WIDE_INT) 1 << thissize) - 1));
722 part = extract_fixed_bit_field (word_mode, value, 0, thissize,
723 bitsdone, NULL_RTX, 1, align);
726 /* If OP0 is a register, then handle OFFSET here.
727 In the register case, UNIT must be a whole word. */
728 if (GET_CODE (op0) == SUBREG || GET_CODE (op0) == REG)
730 word = operand_subword (op0, offset, 1, GET_MODE (op0));
739 store_fixed_bit_field (word, offset, thissize, thispos, part, align);
740 bitsdone += thissize;
744 /* Generate code to extract a byte-field from STR_RTX
745 containing BITSIZE bits, starting at BITNUM,
746 and put it in TARGET if possible (if TARGET is nonzero).
747 Regardless of TARGET, we return the rtx for where the value is placed.
750 STR_RTX is the structure containing the byte (a REG or MEM).
751 UNSIGNEDP is nonzero if this is an unsigned bit field.
752 MODE is the natural mode of the field value once extracted.
753 TMODE is the mode the caller would like the value to have;
754 but the value may be returned with type MODE instead.
756 ALIGN is the alignment that STR_RTX is known to have, measured in bytes.
757 TOTAL_SIZE is the size in bytes of the containing structure,
760 If a TARGET is specified and we can store in it at no extra cost,
761 we do so, and return TARGET.
762 Otherwise, we return a REG of mode TMODE or MODE, with TMODE preferred
763 if they are equally easy. */
766 extract_bit_field (str_rtx, bitsize, bitnum, unsignedp,
767 target, mode, tmode, align, total_size)
769 register int bitsize;
773 enum machine_mode mode, tmode;
777 int unit = (GET_CODE (str_rtx) == MEM) ? BITS_PER_UNIT : BITS_PER_WORD;
778 register int offset = bitnum / unit;
779 register int bitpos = bitnum % unit;
780 register rtx op0 = str_rtx;
781 rtx spec_target = target;
782 rtx spec_target_subreg = 0;
784 if (GET_CODE (str_rtx) == MEM && ! MEM_IN_STRUCT_P (str_rtx))
787 /* Discount the part of the structure before the desired byte.
788 We need to know how many bytes are safe to reference after it. */
790 total_size -= (bitpos / BIGGEST_ALIGNMENT
791 * (BIGGEST_ALIGNMENT / BITS_PER_UNIT));
793 if (tmode == VOIDmode)
795 while (GET_CODE (op0) == SUBREG)
797 offset += SUBREG_WORD (op0);
798 op0 = SUBREG_REG (op0);
802 /* If OP0 is a register, BITPOS must count within a word.
803 But as we have it, it counts within whatever size OP0 now has.
804 On a bigendian machine, these are not the same, so convert. */
805 if (GET_CODE (op0) != MEM && unit > GET_MODE_BITSIZE (GET_MODE (op0)))
806 bitpos += unit - GET_MODE_BITSIZE (GET_MODE (op0));
809 /* Extracting a full-word or multi-word value
810 from a structure in a register.
811 This can be done with just SUBREG.
812 So too extracting a subword value in
813 the least significant part of the register. */
815 if (GET_CODE (op0) == REG
816 && ((bitsize >= BITS_PER_WORD && bitsize == GET_MODE_BITSIZE (mode)
817 && bitpos % BITS_PER_WORD == 0)
818 || (mode_for_size (bitsize, GET_MODE_CLASS (tmode), 0) != BLKmode
820 && bitpos + bitsize == BITS_PER_WORD
826 enum machine_mode mode1
827 = mode_for_size (bitsize, GET_MODE_CLASS (tmode), 0);
829 if (mode1 != GET_MODE (op0))
830 op0 = gen_rtx (SUBREG, mode1, op0, offset);
833 return convert_to_mode (tmode, op0, unsignedp);
837 /* Handle fields bigger than a word. */
839 if (bitsize > BITS_PER_WORD)
841 /* Here we transfer the words of the field
842 in the order least significant first.
843 This is because the most significant word is the one which may
844 be less than full. */
846 int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD;
849 if (target == 0 || GET_CODE (target) != REG)
850 target = gen_reg_rtx (mode);
852 for (i = 0; i < nwords; i++)
854 /* If I is 0, use the low-order word in both field and target;
855 if I is 1, use the next to lowest word; and so on. */
856 int wordnum = (WORDS_BIG_ENDIAN ? nwords - i - 1 : i);
857 int bit_offset = (WORDS_BIG_ENDIAN
858 ? MAX (0, bitsize - (i + 1) * BITS_PER_WORD)
859 : i * BITS_PER_WORD);
860 rtx target_part = operand_subword (target, wordnum, 1, VOIDmode);
862 = extract_bit_field (op0, MIN (BITS_PER_WORD,
863 bitsize - i * BITS_PER_WORD),
865 1, target_part, mode, word_mode,
868 if (target_part == 0)
871 if (result_part != target_part)
872 emit_move_insn (target_part, result_part);
878 /* From here on we know the desired field is smaller than a word
879 so we can assume it is an integer. So we can safely extract it as one
880 size of integer, if necessary, and then truncate or extend
881 to the size that is wanted. */
883 /* OFFSET is the number of words or bytes (UNIT says which)
884 from STR_RTX to the first word or byte containing part of the field. */
886 if (GET_CODE (op0) == REG)
889 || GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD)
890 op0 = gen_rtx (SUBREG, TYPE_MODE (type_for_size (BITS_PER_WORD, 0)),
896 op0 = protect_from_queue (str_rtx, 1);
899 /* Now OFFSET is nonzero only for memory operands. */
905 && (GET_MODE_BITSIZE (insn_operand_mode[(int) CODE_FOR_extzv][0])
908 int xbitpos = bitpos, xoffset = offset;
909 rtx bitsize_rtx, bitpos_rtx;
910 rtx last = get_last_insn();
912 rtx xtarget = target;
913 rtx xspec_target = spec_target;
914 rtx xspec_target_subreg = spec_target_subreg;
916 enum machine_mode maxmode
917 = insn_operand_mode[(int) CODE_FOR_extzv][0];
919 if (GET_CODE (xop0) == MEM)
921 int save_volatile_ok = volatile_ok;
924 /* Is the memory operand acceptable? */
926 || ! ((*insn_operand_predicate[(int) CODE_FOR_extzv][1])
927 (xop0, GET_MODE (xop0))))
929 /* No, load into a reg and extract from there. */
930 enum machine_mode bestmode;
932 /* Get the mode to use for inserting into this field. If
933 OP0 is BLKmode, get the smallest mode consistent with the
934 alignment. If OP0 is a non-BLKmode object that is no
935 wider than MAXMODE, use its mode. Otherwise, use the
936 smallest mode containing the field. */
938 if (GET_MODE (xop0) == BLKmode
939 || (GET_MODE_SIZE (GET_MODE (op0))
940 > GET_MODE_SIZE (maxmode)))
941 bestmode = get_best_mode (bitsize, bitnum,
942 align * BITS_PER_UNIT, maxmode,
943 MEM_VOLATILE_P (xop0));
945 bestmode = GET_MODE (xop0);
947 if (bestmode == VOIDmode)
950 /* Compute offset as multiple of this unit,
951 counting in bytes. */
952 unit = GET_MODE_BITSIZE (bestmode);
953 xoffset = (bitnum / unit) * GET_MODE_SIZE (bestmode);
954 xbitpos = bitnum % unit;
955 xop0 = change_address (xop0, bestmode,
956 plus_constant (XEXP (xop0, 0),
958 /* Fetch it to a register in that size. */
959 xop0 = force_reg (bestmode, xop0);
961 /* XBITPOS counts within UNIT, which is what is expected. */
964 /* Get ref to first byte containing part of the field. */
965 xop0 = change_address (xop0, byte_mode,
966 plus_constant (XEXP (xop0, 0), xoffset));
968 volatile_ok = save_volatile_ok;
971 /* If op0 is a register, we need it in MAXMODE (which is usually
972 SImode). to make it acceptable to the format of extzv. */
973 if (GET_CODE (xop0) == SUBREG && GET_MODE (xop0) != maxmode)
975 if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode)
976 xop0 = gen_rtx (SUBREG, maxmode, xop0, 0);
978 /* On big-endian machines, we count bits from the most significant.
979 If the bit field insn does not, we must invert. */
980 #if BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN
981 xbitpos = unit - bitsize - xbitpos;
983 /* Now convert from counting within UNIT to counting in MAXMODE. */
985 if (GET_CODE (xop0) != MEM)
986 xbitpos += GET_MODE_BITSIZE (maxmode) - unit;
988 unit = GET_MODE_BITSIZE (maxmode);
991 || (flag_force_mem && GET_CODE (xtarget) == MEM))
992 xtarget = xspec_target = gen_reg_rtx (tmode);
994 if (GET_MODE (xtarget) != maxmode)
996 if (GET_CODE (xtarget) == REG)
998 int wider = (GET_MODE_SIZE (maxmode)
999 > GET_MODE_SIZE (GET_MODE (xtarget)));
1000 xtarget = gen_lowpart (maxmode, xtarget);
1002 xspec_target_subreg = xtarget;
1005 xtarget = gen_reg_rtx (maxmode);
1008 /* If this machine's extzv insists on a register target,
1009 make sure we have one. */
1010 if (! ((*insn_operand_predicate[(int) CODE_FOR_extzv][0])
1011 (xtarget, maxmode)))
1012 xtarget = gen_reg_rtx (maxmode);
1014 bitsize_rtx = GEN_INT (bitsize);
1015 bitpos_rtx = GEN_INT (xbitpos);
1017 pat = gen_extzv (protect_from_queue (xtarget, 1),
1018 xop0, bitsize_rtx, bitpos_rtx);
1023 spec_target = xspec_target;
1024 spec_target_subreg = xspec_target_subreg;
1028 delete_insns_since (last);
1029 target = extract_fixed_bit_field (tmode, op0, offset, bitsize,
1030 bitpos, target, 1, align);
1036 target = extract_fixed_bit_field (tmode, op0, offset, bitsize, bitpos,
1043 && (GET_MODE_BITSIZE (insn_operand_mode[(int) CODE_FOR_extv][0])
1046 int xbitpos = bitpos, xoffset = offset;
1047 rtx bitsize_rtx, bitpos_rtx;
1048 rtx last = get_last_insn();
1049 rtx xop0 = op0, xtarget = target;
1050 rtx xspec_target = spec_target;
1051 rtx xspec_target_subreg = spec_target_subreg;
1053 enum machine_mode maxmode
1054 = insn_operand_mode[(int) CODE_FOR_extv][0];
1056 if (GET_CODE (xop0) == MEM)
1058 /* Is the memory operand acceptable? */
1059 if (! ((*insn_operand_predicate[(int) CODE_FOR_extv][1])
1060 (xop0, GET_MODE (xop0))))
1062 /* No, load into a reg and extract from there. */
1063 enum machine_mode bestmode;
1065 /* Get the mode to use for inserting into this field. If
1066 OP0 is BLKmode, get the smallest mode consistent with the
1067 alignment. If OP0 is a non-BLKmode object that is no
1068 wider than MAXMODE, use its mode. Otherwise, use the
1069 smallest mode containing the field. */
1071 if (GET_MODE (xop0) == BLKmode
1072 || (GET_MODE_SIZE (GET_MODE (op0))
1073 > GET_MODE_SIZE (maxmode)))
1074 bestmode = get_best_mode (bitsize, bitnum,
1075 align * BITS_PER_UNIT, maxmode,
1076 MEM_VOLATILE_P (xop0));
1078 bestmode = GET_MODE (xop0);
1080 if (bestmode == VOIDmode)
1083 /* Compute offset as multiple of this unit,
1084 counting in bytes. */
1085 unit = GET_MODE_BITSIZE (bestmode);
1086 xoffset = (bitnum / unit) * GET_MODE_SIZE (bestmode);
1087 xbitpos = bitnum % unit;
1088 xop0 = change_address (xop0, bestmode,
1089 plus_constant (XEXP (xop0, 0),
1091 /* Fetch it to a register in that size. */
1092 xop0 = force_reg (bestmode, xop0);
1094 /* XBITPOS counts within UNIT, which is what is expected. */
1097 /* Get ref to first byte containing part of the field. */
1098 xop0 = change_address (xop0, byte_mode,
1099 plus_constant (XEXP (xop0, 0), xoffset));
1102 /* If op0 is a register, we need it in MAXMODE (which is usually
1103 SImode) to make it acceptable to the format of extv. */
1104 if (GET_CODE (xop0) == SUBREG && GET_MODE (xop0) != maxmode)
1106 if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode)
1107 xop0 = gen_rtx (SUBREG, maxmode, xop0, 0);
1109 /* On big-endian machines, we count bits from the most significant.
1110 If the bit field insn does not, we must invert. */
1111 #if BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN
1112 xbitpos = unit - bitsize - xbitpos;
1114 /* XBITPOS counts within a size of UNIT.
1115 Adjust to count within a size of MAXMODE. */
1117 if (GET_CODE (xop0) != MEM)
1118 xbitpos += (GET_MODE_BITSIZE (maxmode) - unit);
1120 unit = GET_MODE_BITSIZE (maxmode);
1123 || (flag_force_mem && GET_CODE (xtarget) == MEM))
1124 xtarget = xspec_target = gen_reg_rtx (tmode);
1126 if (GET_MODE (xtarget) != maxmode)
1128 if (GET_CODE (xtarget) == REG)
1130 int wider = (GET_MODE_SIZE (maxmode)
1131 > GET_MODE_SIZE (GET_MODE (xtarget)));
1132 xtarget = gen_lowpart (maxmode, xtarget);
1134 xspec_target_subreg = xtarget;
1137 xtarget = gen_reg_rtx (maxmode);
1140 /* If this machine's extv insists on a register target,
1141 make sure we have one. */
1142 if (! ((*insn_operand_predicate[(int) CODE_FOR_extv][0])
1143 (xtarget, maxmode)))
1144 xtarget = gen_reg_rtx (maxmode);
1146 bitsize_rtx = GEN_INT (bitsize);
1147 bitpos_rtx = GEN_INT (xbitpos);
1149 pat = gen_extv (protect_from_queue (xtarget, 1),
1150 xop0, bitsize_rtx, bitpos_rtx);
1155 spec_target = xspec_target;
1156 spec_target_subreg = xspec_target_subreg;
1160 delete_insns_since (last);
1161 target = extract_fixed_bit_field (tmode, op0, offset, bitsize,
1162 bitpos, target, 0, align);
1168 target = extract_fixed_bit_field (tmode, op0, offset, bitsize, bitpos,
1171 if (target == spec_target)
1173 if (target == spec_target_subreg)
1175 if (GET_MODE (target) != tmode && GET_MODE (target) != mode)
1177 /* If the target mode is floating-point, first convert to the
1178 integer mode of that size and then access it as a floating-point
1179 value via a SUBREG. */
1180 if (GET_MODE_CLASS (tmode) == MODE_FLOAT)
1182 target = convert_to_mode (mode_for_size (GET_MODE_BITSIZE (tmode),
1185 if (GET_CODE (target) != REG)
1186 target = copy_to_reg (target);
1187 return gen_rtx (SUBREG, tmode, target, 0);
1190 return convert_to_mode (tmode, target, unsignedp);
1195 /* Extract a bit field using shifts and boolean operations
1196 Returns an rtx to represent the value.
1197 OP0 addresses a register (word) or memory (byte).
1198 BITPOS says which bit within the word or byte the bit field starts in.
1199 OFFSET says how many bytes farther the bit field starts;
1200 it is 0 if OP0 is a register.
1201 BITSIZE says how many bits long the bit field is.
1202 (If OP0 is a register, it may be narrower than a full word,
1203 but BITPOS still counts within a full word,
1204 which is significant on bigendian machines.)
1206 UNSIGNEDP is nonzero for an unsigned bit field (don't sign-extend value).
1207 If TARGET is nonzero, attempts to store the value there
1208 and return TARGET, but this is not guaranteed.
1209 If TARGET is not used, create a pseudo-reg of mode TMODE for the value.
1211 ALIGN is the alignment that STR_RTX is known to have, measured in bytes. */
1214 extract_fixed_bit_field (tmode, op0, offset, bitsize, bitpos,
1215 target, unsignedp, align)
1216 enum machine_mode tmode;
1217 register rtx op0, target;
1218 register int offset, bitsize, bitpos;
1222 int total_bits = BITS_PER_WORD;
1223 enum machine_mode mode;
1225 if (GET_CODE (op0) == SUBREG || GET_CODE (op0) == REG)
1227 /* Special treatment for a bit field split across two registers. */
1228 if (bitsize + bitpos > BITS_PER_WORD)
1229 return extract_split_bit_field (op0, bitsize, bitpos,
1234 /* Get the proper mode to use for this field. We want a mode that
1235 includes the entire field. If such a mode would be larger than
1236 a word, we won't be doing the extraction the normal way. */
1238 mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT,
1239 align * BITS_PER_UNIT, word_mode,
1240 GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0));
1242 if (mode == VOIDmode)
1243 /* The only way this should occur is if the field spans word
1245 return extract_split_bit_field (op0, bitsize,
1246 bitpos + offset * BITS_PER_UNIT,
1249 total_bits = GET_MODE_BITSIZE (mode);
1251 /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to
1252 be be in the range 0 to total_bits-1, and put any excess bytes in
1254 if (bitpos >= total_bits)
1256 offset += (bitpos / total_bits) * (total_bits / BITS_PER_UNIT);
1257 bitpos -= ((bitpos / total_bits) * (total_bits / BITS_PER_UNIT)
1261 /* Get ref to an aligned byte, halfword, or word containing the field.
1262 Adjust BITPOS to be position within a word,
1263 and OFFSET to be the offset of that word.
1264 Then alter OP0 to refer to that word. */
1265 bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT;
1266 offset -= (offset % (total_bits / BITS_PER_UNIT));
1267 op0 = change_address (op0, mode,
1268 plus_constant (XEXP (op0, 0), offset));
1271 mode = GET_MODE (op0);
1273 #if BYTES_BIG_ENDIAN
1274 /* BITPOS is the distance between our msb and that of OP0.
1275 Convert it to the distance from the lsb. */
1277 bitpos = total_bits - bitsize - bitpos;
1279 /* Now BITPOS is always the distance between the field's lsb and that of OP0.
1280 We have reduced the big-endian case to the little-endian case. */
1286 /* If the field does not already start at the lsb,
1287 shift it so it does. */
1288 tree amount = build_int_2 (bitpos, 0);
1289 /* Maybe propagate the target for the shift. */
1290 /* But not if we will return it--could confuse integrate.c. */
1291 rtx subtarget = (target != 0 && GET_CODE (target) == REG
1292 && !REG_FUNCTION_VALUE_P (target)
1294 if (tmode != mode) subtarget = 0;
1295 op0 = expand_shift (RSHIFT_EXPR, mode, op0, amount, subtarget, 1);
1297 /* Convert the value to the desired mode. */
1299 op0 = convert_to_mode (tmode, op0, 1);
1301 /* Unless the msb of the field used to be the msb when we shifted,
1302 mask out the upper bits. */
1304 if (GET_MODE_BITSIZE (mode) != bitpos + bitsize
1306 #ifdef SLOW_ZERO_EXTEND
1307 /* Always generate an `and' if
1308 we just zero-extended op0 and SLOW_ZERO_EXTEND, since it
1309 will combine fruitfully with the zero-extend. */
1314 return expand_binop (GET_MODE (op0), and_optab, op0,
1315 mask_rtx (GET_MODE (op0), 0, bitsize, 0),
1316 target, 1, OPTAB_LIB_WIDEN);
1320 /* To extract a signed bit-field, first shift its msb to the msb of the word,
1321 then arithmetic-shift its lsb to the lsb of the word. */
1322 op0 = force_reg (mode, op0);
1326 /* Find the narrowest integer mode that contains the field. */
1328 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode;
1329 mode = GET_MODE_WIDER_MODE (mode))
1330 if (GET_MODE_BITSIZE (mode) >= bitsize + bitpos)
1332 op0 = convert_to_mode (mode, op0, 0);
1336 if (GET_MODE_BITSIZE (mode) != (bitsize + bitpos))
1338 tree amount = build_int_2 (GET_MODE_BITSIZE (mode) - (bitsize + bitpos), 0);
1339 /* Maybe propagate the target for the shift. */
1340 /* But not if we will return the result--could confuse integrate.c. */
1341 rtx subtarget = (target != 0 && GET_CODE (target) == REG
1342 && ! REG_FUNCTION_VALUE_P (target)
1344 op0 = expand_shift (LSHIFT_EXPR, mode, op0, amount, subtarget, 1);
1347 return expand_shift (RSHIFT_EXPR, mode, op0,
1348 build_int_2 (GET_MODE_BITSIZE (mode) - bitsize, 0),
1352 /* Return a constant integer (CONST_INT or CONST_DOUBLE) mask value
1353 of mode MODE with BITSIZE ones followed by BITPOS zeros, or the
1354 complement of that if COMPLEMENT. The mask is truncated if
1355 necessary to the width of mode MODE. */
1358 mask_rtx (mode, bitpos, bitsize, complement)
1359 enum machine_mode mode;
1360 int bitpos, bitsize, complement;
1362 HOST_WIDE_INT masklow, maskhigh;
1364 if (bitpos < HOST_BITS_PER_WIDE_INT)
1365 masklow = (HOST_WIDE_INT) -1 << bitpos;
1369 if (bitpos + bitsize < HOST_BITS_PER_WIDE_INT)
1370 masklow &= ((unsigned HOST_WIDE_INT) -1
1371 >> (HOST_BITS_PER_WIDE_INT - bitpos - bitsize));
1373 if (bitpos <= HOST_BITS_PER_WIDE_INT)
1376 maskhigh = (HOST_WIDE_INT) -1 << (bitpos - HOST_BITS_PER_WIDE_INT);
1378 if (bitpos + bitsize > HOST_BITS_PER_WIDE_INT)
1379 maskhigh &= ((unsigned HOST_WIDE_INT) -1
1380 >> (2 * HOST_BITS_PER_WIDE_INT - bitpos - bitsize));
1386 maskhigh = ~maskhigh;
1390 return immed_double_const (masklow, maskhigh, mode);
1393 /* Return a constant integer (CONST_INT or CONST_DOUBLE) rtx with the value
1394 VALUE truncated to BITSIZE bits and then shifted left BITPOS bits. */
1397 lshift_value (mode, value, bitpos, bitsize)
1398 enum machine_mode mode;
1400 int bitpos, bitsize;
1402 unsigned HOST_WIDE_INT v = INTVAL (value);
1403 HOST_WIDE_INT low, high;
1405 if (bitsize < HOST_BITS_PER_WIDE_INT)
1406 v &= ~((HOST_WIDE_INT) -1 << bitsize);
1408 if (bitpos < HOST_BITS_PER_WIDE_INT)
1411 high = (bitpos > 0 ? (v >> (HOST_BITS_PER_WIDE_INT - bitpos)) : 0);
1416 high = v << (bitpos - HOST_BITS_PER_WIDE_INT);
1419 return immed_double_const (low, high, mode);
1422 /* Extract a bit field that is split across two words
1423 and return an RTX for the result.
1425 OP0 is the REG, SUBREG or MEM rtx for the first of the two words.
1426 BITSIZE is the field width; BITPOS, position of its first bit, in the word.
1427 UNSIGNEDP is 1 if should zero-extend the contents; else sign-extend.
1429 ALIGN is the known alignment of OP0, measured in bytes.
1430 This is also the size of the memory objects to be used. */
1433 extract_split_bit_field (op0, bitsize, bitpos, unsignedp, align)
1435 int bitsize, bitpos, unsignedp, align;
1437 int unit = align * BITS_PER_UNIT;
1442 while (bitsdone < bitsize)
1449 offset = (bitpos + bitsdone) / unit;
1450 thispos = (bitpos + bitsdone) % unit;
1452 thissize = unit - offset * BITS_PER_UNIT % unit;
1454 /* If OP0 is a register, then handle OFFSET here.
1455 In the register case, UNIT must be a whole word. */
1456 if (GET_CODE (op0) == SUBREG || GET_CODE (op0) == REG)
1458 word = operand_subword_force (op0, offset, GET_MODE (op0));
1467 /* Extract the parts in bit-counting order,
1468 whose meaning is determined by BYTES_PER_UNIT. */
1469 part = extract_fixed_bit_field (word_mode, word, offset,
1470 thissize, thispos, 0, 1, align);
1471 bitsdone += thissize;
1473 /* Shift this part into place for the result. */
1474 #if BYTES_BIG_ENDIAN
1475 if (bitsize != bitsdone)
1476 part = expand_shift (LSHIFT_EXPR, word_mode, part,
1477 build_int_2 (bitsize - bitsdone, 0), 0, 1);
1480 part = expand_shift (LSHIFT_EXPR, word_mode, part,
1481 build_int_2 (bitsdone, 0), 0, 1);
1487 /* Combine the parts with bitwise or. This works
1488 because we extracted each part as an unsigned bit field. */
1489 result = expand_binop (word_mode, ior_optab, part, result, NULL_RTX, 1,
1495 /* Unsigned bit field: we are done. */
1498 /* Signed bit field: sign-extend with two arithmetic shifts. */
1499 result = expand_shift (LSHIFT_EXPR, word_mode, result,
1500 build_int_2 (BITS_PER_WORD - bitsize, 0),
1502 return expand_shift (RSHIFT_EXPR, word_mode, result,
1503 build_int_2 (BITS_PER_WORD - bitsize, 0), NULL_RTX, 0);
1506 /* Add INC into TARGET. */
1509 expand_inc (target, inc)
1512 rtx value = expand_binop (GET_MODE (target), add_optab,
1514 target, 0, OPTAB_LIB_WIDEN);
1515 if (value != target)
1516 emit_move_insn (target, value);
1519 /* Subtract DEC from TARGET. */
1522 expand_dec (target, dec)
1525 rtx value = expand_binop (GET_MODE (target), sub_optab,
1527 target, 0, OPTAB_LIB_WIDEN);
1528 if (value != target)
1529 emit_move_insn (target, value);
1532 /* Output a shift instruction for expression code CODE,
1533 with SHIFTED being the rtx for the value to shift,
1534 and AMOUNT the tree for the amount to shift by.
1535 Store the result in the rtx TARGET, if that is convenient.
1536 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
1537 Return the rtx for where the value is. */
1540 expand_shift (code, mode, shifted, amount, target, unsignedp)
1541 enum tree_code code;
1542 register enum machine_mode mode;
1545 register rtx target;
1548 register rtx op1, temp = 0;
1549 register int left = (code == LSHIFT_EXPR || code == LROTATE_EXPR);
1550 register int rotate = (code == LROTATE_EXPR || code == RROTATE_EXPR);
1553 /* Previously detected shift-counts computed by NEGATE_EXPR
1554 and shifted in the other direction; but that does not work
1557 op1 = expand_expr (amount, NULL_RTX, VOIDmode, 0);
1559 if (op1 == const0_rtx)
1562 for (try = 0; temp == 0 && try < 3; try++)
1564 enum optab_methods methods;
1567 methods = OPTAB_DIRECT;
1569 methods = OPTAB_WIDEN;
1571 methods = OPTAB_LIB_WIDEN;
1575 /* Widening does not work for rotation. */
1576 if (methods == OPTAB_WIDEN)
1578 else if (methods == OPTAB_LIB_WIDEN)
1580 /* If we are rotating by a constant that is valid and
1581 we have been unable to open-code this by a rotation,
1582 do it as the IOR of two shifts. I.e., to rotate A
1583 by N bits, compute (A << N) | ((unsigned) A >> (C - N))
1584 where C is the bitsize of A.
1586 It is theoretically possible that the target machine might
1587 not be able to perform either shift and hence we would
1588 be making two libcalls rather than just the one for the
1589 shift (similarly if IOR could not be done). We will allow
1590 this extremely unlikely lossage to avoid complicating the
1593 if (GET_CODE (op1) == CONST_INT && INTVAL (op1) > 0
1594 && INTVAL (op1) < GET_MODE_BITSIZE (mode))
1596 rtx subtarget = target == shifted ? 0 : target;
1599 = build_int_2 (GET_MODE_BITSIZE (mode) - INTVAL (op1), 0);
1601 shifted = force_reg (mode, shifted);
1603 temp = expand_shift (left ? LSHIFT_EXPR : RSHIFT_EXPR,
1604 mode, shifted, amount, subtarget, 1);
1605 temp1 = expand_shift (left ? RSHIFT_EXPR : LSHIFT_EXPR,
1606 mode, shifted, other_amount, 0, 1);
1607 return expand_binop (mode, ior_optab, temp, temp1, target,
1608 unsignedp, methods);
1611 methods = OPTAB_LIB;
1614 temp = expand_binop (mode,
1615 left ? rotl_optab : rotr_optab,
1616 shifted, op1, target, unsignedp, methods);
1618 /* If we don't have the rotate, but we are rotating by a constant
1619 that is in range, try a rotate in the opposite direction. */
1621 if (temp == 0 && GET_CODE (op1) == CONST_INT
1622 && INTVAL (op1) > 0 && INTVAL (op1) < GET_MODE_BITSIZE (mode))
1623 temp = expand_binop (mode,
1624 left ? rotr_optab : rotl_optab,
1626 GEN_INT (GET_MODE_BITSIZE (mode)
1628 target, unsignedp, methods);
1632 temp = expand_binop (mode,
1633 left ? lshl_optab : lshr_optab,
1634 shifted, op1, target, unsignedp, methods);
1635 if (temp == 0 && left)
1636 temp = expand_binop (mode, ashl_optab,
1637 shifted, op1, target, unsignedp, methods);
1640 /* Do arithmetic shifts.
1641 Also, if we are going to widen the operand, we can just as well
1642 use an arithmetic right-shift instead of a logical one. */
1643 if (temp == 0 && ! rotate
1644 && (! unsignedp || (! left && methods == OPTAB_WIDEN)))
1646 enum optab_methods methods1 = methods;
1648 /* If trying to widen a log shift to an arithmetic shift,
1649 don't accept an arithmetic shift of the same size. */
1651 methods1 = OPTAB_MUST_WIDEN;
1653 /* Arithmetic shift */
1655 temp = expand_binop (mode,
1656 left ? ashl_optab : ashr_optab,
1657 shifted, op1, target, unsignedp, methods1);
1661 /* We can do a logical (unsigned) right shift with a bit-field
1662 extract insn. But first check if one of the above methods worked. */
1666 if (unsignedp && code == RSHIFT_EXPR && ! BITS_BIG_ENDIAN && HAVE_extzv)
1668 enum machine_mode output_mode
1669 = insn_operand_mode[(int) CODE_FOR_extzv][0];
1671 if ((methods == OPTAB_DIRECT && mode == output_mode)
1672 || (methods == OPTAB_WIDEN
1673 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (output_mode)))
1675 rtx shifted1 = convert_to_mode (output_mode,
1676 protect_from_queue (shifted, 0),
1678 enum machine_mode length_mode
1679 = insn_operand_mode[(int) CODE_FOR_extzv][2];
1680 enum machine_mode pos_mode
1681 = insn_operand_mode[(int) CODE_FOR_extzv][3];
1683 rtx last = get_last_insn ();
1689 target1 = protect_from_queue (target, 1);
1691 /* We define extract insns as having OUTPUT_MODE in a register
1692 and the mode of operand 1 in memory. Since we want
1693 OUTPUT_MODE, we will always force the operand into a
1694 register. At some point we might want to support MEM
1696 shifted1 = force_reg (output_mode, shifted1);
1698 /* If we don't have or cannot use a suggested target,
1699 make a place for the result, in the proper mode. */
1700 if (methods == OPTAB_WIDEN || target1 == 0
1701 || ! ((*insn_operand_predicate[(int) CODE_FOR_extzv][0])
1702 (target1, output_mode)))
1703 target1 = gen_reg_rtx (output_mode);
1705 xop1 = protect_from_queue (xop1, 0);
1706 xop1 = convert_to_mode (pos_mode, xop1,
1707 TREE_UNSIGNED (TREE_TYPE (amount)));
1709 /* If this machine's extzv insists on a register for
1710 operand 3 (position), arrange for that. */
1711 if (! ((*insn_operand_predicate[(int) CODE_FOR_extzv][3])
1713 xop1 = force_reg (pos_mode, xop1);
1715 /* WIDTH gets the width of the bit field to extract:
1716 wordsize minus # bits to shift by. */
1717 if (GET_CODE (xop1) == CONST_INT)
1718 width = GEN_INT (GET_MODE_BITSIZE (mode) - INTVAL (op1));
1721 /* Now get the width in the proper mode. */
1722 op1 = protect_from_queue (op1, 0);
1723 width = convert_to_mode (length_mode, op1,
1724 TREE_UNSIGNED (TREE_TYPE (amount)));
1726 width = expand_binop (length_mode, sub_optab,
1727 GEN_INT (GET_MODE_BITSIZE (mode)),
1728 width, NULL_RTX, 0, OPTAB_LIB_WIDEN);
1731 /* If this machine's extzv insists on a register for
1732 operand 2 (length), arrange for that. */
1733 if (! ((*insn_operand_predicate[(int) CODE_FOR_extzv][2])
1734 (width, length_mode)))
1735 width = force_reg (length_mode, width);
1737 /* Now extract with WIDTH, omitting OP1 least sig bits. */
1738 pat = gen_extzv (target1, shifted1, width, xop1);
1742 temp = convert_to_mode (mode, target1, 1);
1745 delete_insns_since (last);
1748 /* Can also do logical shift with signed bit-field extract
1749 followed by inserting the bit-field at a different position.
1750 That strategy is not yet implemented. */
1752 #endif /* HAVE_extzv */
1760 enum alg_code { alg_zero, alg_m, alg_shift,
1761 alg_add_t_m2, alg_sub_t_m2,
1762 alg_add_factor, alg_sub_factor,
1763 alg_add_t2_m, alg_sub_t2_m,
1764 alg_add, alg_subtract, alg_factor, alg_shiftop };
1766 /* This structure records a sequence of operations.
1767 `ops' is the number of operations recorded.
1768 `cost' is their total cost.
1769 The operations are stored in `op' and the corresponding
1770 logarithms of the integer coefficients in `log'.
1772 These are the operations:
1773 alg_zero total := 0;
1774 alg_m total := multiplicand;
1775 alg_shift total := total * coeff
1776 alg_add_t_m2 total := total + multiplicand * coeff;
1777 alg_sub_t_m2 total := total - multiplicand * coeff;
1778 alg_add_factor total := total * coeff + total;
1779 alg_sub_factor total := total * coeff - total;
1780 alg_add_t2_m total := total * coeff + multiplicand;
1781 alg_sub_t2_m total := total * coeff - multiplicand;
1783 The first operand must be either alg_zero or alg_m. */
1789 /* The size of the OP and LOG fields are not directly related to the
1790 word size, but the worst-case algorithms will be if we have few
1791 consecutive ones or zeros, i.e., a multiplicand like 10101010101...
1792 In that case we will generate shift-by-2, add, shift-by-2, add,...,
1793 in total wordsize operations. */
1794 enum alg_code op[MAX_BITS_PER_WORD];
1795 char log[MAX_BITS_PER_WORD];
1798 /* Compute and return the best algorithm for multiplying by T.
1799 The algorithm must cost less than cost_limit
1800 If retval.cost >= COST_LIMIT, no algorithm was found and all
1801 other field of the returned struct are undefined. */
1803 static struct algorithm
1804 synth_mult (t, cost_limit)
1805 unsigned HOST_WIDE_INT t;
1809 struct algorithm *best_alg
1810 = (struct algorithm *)alloca (sizeof (struct algorithm));
1811 struct algorithm *alg_in
1812 = (struct algorithm *)alloca (sizeof (struct algorithm));
1814 unsigned HOST_WIDE_INT q;
1816 /* Indicate that no algorithm is yet found. If no algorithm
1817 is found, this value will be returned and indicate failure. */
1818 best_alg->cost = cost_limit;
1820 if (cost_limit <= 0)
1823 /* t == 1 can be done in zero cost. */
1828 best_alg->op[0] = alg_m;
1832 /* t == 0 sometimes has a cost. If it does and it exceeds our limit,
1837 if (zero_cost >= cost_limit)
1842 best_alg->cost = zero_cost;
1843 best_alg->op[0] = alg_zero;
1848 /* If we have a group of zero bits at the low-order part of T, try
1849 multiplying by the remaining bits and then doing a shift. */
1853 m = floor_log2 (t & -t); /* m = number of low zero bits */
1855 cost = shift_cost[m];
1856 if (cost < cost_limit)
1858 *alg_in = synth_mult (q, cost_limit - cost);
1860 cost += alg_in->cost;
1861 if (cost < best_alg->cost)
1863 struct algorithm *x;
1864 x = alg_in, alg_in = best_alg, best_alg = x;
1865 best_alg->log[best_alg->ops] = m;
1866 best_alg->op[best_alg->ops++] = alg_shift;
1867 best_alg->cost = cost_limit = cost;
1872 /* If we have an odd number, add or subtract one. */
1875 unsigned HOST_WIDE_INT w;
1877 for (w = 1; (w & t) != 0; w <<= 1)
1880 /* Reject the case where t is 3.
1881 Thus we prefer addition in that case. */
1884 /* T ends with ...111. Multiply by (T + 1) and subtract 1. */
1887 *alg_in = synth_mult (t + 1, cost_limit - cost);
1889 cost += alg_in->cost;
1890 if (cost < best_alg->cost)
1892 struct algorithm *x;
1893 x = alg_in, alg_in = best_alg, best_alg = x;
1894 best_alg->log[best_alg->ops] = 0;
1895 best_alg->op[best_alg->ops++] = alg_sub_t_m2;
1896 best_alg->cost = cost_limit = cost;
1901 /* T ends with ...01 or ...011. Multiply by (T - 1) and add 1. */
1904 *alg_in = synth_mult (t - 1, cost_limit - cost);
1906 cost += alg_in->cost;
1907 if (cost < best_alg->cost)
1909 struct algorithm *x;
1910 x = alg_in, alg_in = best_alg, best_alg = x;
1911 best_alg->log[best_alg->ops] = 0;
1912 best_alg->op[best_alg->ops++] = alg_add_t_m2;
1913 best_alg->cost = cost_limit = cost;
1918 /* Look for factors of t of the form
1919 t = q(2**m +- 1), 2 <= m <= floor(log2(t - 1)).
1920 If we find such a factor, we can multiply by t using an algorithm that
1921 multiplies by q, shift the result by m and add/subtract it to itself.
1923 We search for large factors first and loop down, even if large factors
1924 are less probable than small; if we find a large factor we will find a
1925 good sequence quickly, and therefore be able to prune (by decreasing
1926 COST_LIMIT) the search. */
1928 for (m = floor_log2 (t - 1); m >= 2; m--)
1930 unsigned HOST_WIDE_INT d;
1932 d = ((unsigned HOST_WIDE_INT) 1 << m) + 1;
1933 if (t % d == 0 && t > d)
1935 cost = MIN (shiftadd_cost[m], add_cost + shift_cost[m]);
1936 *alg_in = synth_mult (t / d, cost_limit - cost);
1938 cost += alg_in->cost;
1939 if (cost < best_alg->cost)
1941 struct algorithm *x;
1942 x = alg_in, alg_in = best_alg, best_alg = x;
1943 best_alg->log[best_alg->ops] = m;
1944 best_alg->op[best_alg->ops++] = alg_add_factor;
1945 best_alg->cost = cost_limit = cost;
1949 d = ((unsigned HOST_WIDE_INT) 1 << m) - 1;
1950 if (t % d == 0 && t > d)
1952 cost = MIN (shiftsub_cost[m], add_cost + shift_cost[m]);
1953 *alg_in = synth_mult (t / d, cost_limit - cost);
1955 cost += alg_in->cost;
1956 if (cost < best_alg->cost)
1958 struct algorithm *x;
1959 x = alg_in, alg_in = best_alg, best_alg = x;
1960 best_alg->log[best_alg->ops] = m;
1961 best_alg->op[best_alg->ops++] = alg_sub_factor;
1962 best_alg->cost = cost_limit = cost;
1967 /* Try shift-and-add (load effective address) instructions,
1968 i.e. do a*3, a*5, a*9. */
1976 cost = shiftadd_cost[m];
1977 *alg_in = synth_mult ((t - 1) >> m, cost_limit - cost);
1979 cost += alg_in->cost;
1980 if (cost < best_alg->cost)
1982 struct algorithm *x;
1983 x = alg_in, alg_in = best_alg, best_alg = x;
1984 best_alg->log[best_alg->ops] = m;
1985 best_alg->op[best_alg->ops++] = alg_add_t2_m;
1986 best_alg->cost = cost_limit = cost;
1995 cost = shiftsub_cost[m];
1996 *alg_in = synth_mult ((t + 1) >> m, cost_limit - cost);
1998 cost += alg_in->cost;
1999 if (cost < best_alg->cost)
2001 struct algorithm *x;
2002 x = alg_in, alg_in = best_alg, best_alg = x;
2003 best_alg->log[best_alg->ops] = m;
2004 best_alg->op[best_alg->ops++] = alg_sub_t2_m;
2005 best_alg->cost = cost_limit = cost;
2010 /* If we are getting a too long sequence for `struct algorithm'
2011 to record, store a fake cost to make this search fail. */
2012 if (best_alg->ops == MAX_BITS_PER_WORD)
2013 best_alg->cost = cost_limit;
2018 /* Perform a multiplication and return an rtx for the result.
2019 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
2020 TARGET is a suggestion for where to store the result (an rtx).
2022 We check specially for a constant integer as OP1.
2023 If you want this check for OP0 as well, then before calling
2024 you should swap the two operands if OP0 would be constant. */
2027 expand_mult (mode, op0, op1, target, unsignedp)
2028 enum machine_mode mode;
2029 register rtx op0, op1, target;
2032 rtx const_op1 = op1;
2034 /* If we are multiplying in DImode, it may still be a win
2035 to try to work with shifts and adds. */
2036 if (GET_CODE (op1) == CONST_DOUBLE
2037 && GET_MODE_CLASS (GET_MODE (op1)) == MODE_INT
2038 && HOST_BITS_PER_INT <= BITS_PER_WORD)
2040 if ((CONST_DOUBLE_HIGH (op1) == 0 && CONST_DOUBLE_LOW (op1) >= 0)
2041 || (CONST_DOUBLE_HIGH (op1) == -1 && CONST_DOUBLE_LOW (op1) < 0))
2042 const_op1 = GEN_INT (CONST_DOUBLE_LOW (op1));
2045 /* We used to test optimize here, on the grounds that it's better to
2046 produce a smaller program when -O is not used.
2047 But this causes such a terrible slowdown sometimes
2048 that it seems better to use synth_mult always. */
2050 if (GET_CODE (const_op1) == CONST_INT && ! mult_is_very_cheap)
2052 struct algorithm alg;
2053 struct algorithm neg_alg;
2055 HOST_WIDE_INT val = INTVAL (op1);
2056 HOST_WIDE_INT val_so_far;
2059 /* Try to do the computation two ways: multiply by the negative of OP1
2060 and then negate, or do the multiplication directly. The latter is
2061 usually faster for positive numbers and the former for negative
2062 numbers, but the opposite can be faster if the original value
2063 has a factor of 2**m +/- 1, while the negated value does not or
2066 alg = synth_mult (val, mult_cost);
2067 neg_alg = synth_mult (- val,
2068 (alg.cost < mult_cost ? alg.cost : mult_cost)
2071 if (neg_alg.cost + negate_cost < alg.cost)
2072 alg = neg_alg, negate = 1;
2074 if (alg.cost < mult_cost)
2076 /* We found something cheaper than a multiply insn. */
2080 op0 = protect_from_queue (op0, 0);
2082 /* Avoid referencing memory over and over.
2083 For speed, but also for correctness when mem is volatile. */
2084 if (GET_CODE (op0) == MEM)
2085 op0 = force_reg (mode, op0);
2087 /* ACCUM starts out either as OP0 or as a zero, depending on
2088 the first operation. */
2090 if (alg.op[0] == alg_zero)
2092 accum = copy_to_mode_reg (mode, const0_rtx);
2095 else if (alg.op[0] == alg_m)
2097 accum = copy_to_mode_reg (mode, op0);
2103 for (opno = 1; opno < alg.ops; opno++)
2105 int log = alg.log[opno];
2106 rtx shift_subtarget = preserve_subexpressions_p () ? 0 : accum;
2107 rtx add_target = opno == alg.ops - 1 && target != 0 ? target : 0;
2109 switch (alg.op[opno])
2112 accum = expand_shift (LSHIFT_EXPR, mode, accum,
2113 build_int_2 (log, 0), NULL_RTX, 0);
2118 tem = expand_shift (LSHIFT_EXPR, mode, op0,
2119 build_int_2 (log, 0), NULL_RTX, 0);
2120 accum = force_operand (gen_rtx (PLUS, mode, accum, tem),
2121 add_target ? add_target : accum);
2122 val_so_far += (HOST_WIDE_INT) 1 << log;
2126 tem = expand_shift (LSHIFT_EXPR, mode, op0,
2127 build_int_2 (log, 0), NULL_RTX, 0);
2128 accum = force_operand (gen_rtx (MINUS, mode, accum, tem),
2129 add_target ? add_target : accum);
2130 val_so_far -= (HOST_WIDE_INT) 1 << log;
2134 accum = expand_shift (LSHIFT_EXPR, mode, accum,
2135 build_int_2 (log, 0), accum, 0);
2136 accum = force_operand (gen_rtx (PLUS, mode, accum, op0),
2137 add_target ? add_target : accum);
2138 val_so_far = (val_so_far << log) + 1;
2142 accum = expand_shift (LSHIFT_EXPR, mode, accum,
2143 build_int_2 (log, 0), accum, 0);
2144 accum = force_operand (gen_rtx (MINUS, mode, accum, op0),
2145 add_target ? add_target : accum);
2146 val_so_far = (val_so_far << log) - 1;
2149 case alg_add_factor:
2150 tem = expand_shift (LSHIFT_EXPR, mode, accum,
2151 build_int_2 (log, 0), NULL_RTX, 0);
2152 accum = force_operand (gen_rtx (PLUS, mode, accum, tem),
2153 add_target ? add_target : accum);
2154 val_so_far += val_so_far << log;
2157 case alg_sub_factor:
2158 tem = expand_shift (LSHIFT_EXPR, mode, accum,
2159 build_int_2 (log, 0), NULL_RTX, 0);
2160 accum = force_operand (gen_rtx (MINUS, mode, tem, accum),
2161 add_target ? add_target : tem);
2162 val_so_far = (val_so_far << log) - val_so_far;
2169 /* Write a REG_EQUAL note on the last insn so that we can cse
2170 multiplication sequences. */
2172 insn = get_last_insn ();
2174 = gen_rtx (EXPR_LIST, REG_EQUAL,
2175 gen_rtx (MULT, mode, op0, GEN_INT (val_so_far)),
2181 val_so_far = - val_so_far;
2182 accum = expand_unop (mode, neg_optab, accum, target, 0);
2185 if (val != val_so_far)
2192 /* This used to use umul_optab if unsigned,
2193 but for non-widening multiply there is no difference
2194 between signed and unsigned. */
2195 op0 = expand_binop (mode, smul_optab,
2196 op0, op1, target, unsignedp, OPTAB_LIB_WIDEN);
2202 /* Emit the code to divide OP0 by OP1, putting the result in TARGET
2203 if that is convenient, and returning where the result is.
2204 You may request either the quotient or the remainder as the result;
2205 specify REM_FLAG nonzero to get the remainder.
2207 CODE is the expression code for which kind of division this is;
2208 it controls how rounding is done. MODE is the machine mode to use.
2209 UNSIGNEDP nonzero means do unsigned division. */
2211 /* ??? For CEIL_MOD_EXPR, can compute incorrect remainder with ANDI
2212 and then correct it by or'ing in missing high bits
2213 if result of ANDI is nonzero.
2214 For ROUND_MOD_EXPR, can use ANDI and then sign-extend the result.
2215 This could optimize to a bfexts instruction.
2216 But C doesn't use these operations, so their optimizations are
2220 expand_divmod (rem_flag, code, mode, op0, op1, target, unsignedp)
2222 enum tree_code code;
2223 enum machine_mode mode;
2224 register rtx op0, op1, target;
2227 register rtx result = 0;
2228 enum machine_mode compute_mode;
2231 int can_clobber_op0;
2232 int mod_insn_no_good = 0;
2233 rtx adjusted_op0 = op0;
2234 optab optab1, optab2;
2236 /* We shouldn't be called with op1 == const1_rtx, but some of the
2237 code below will malfunction if we are, so check here and handle
2238 the special case if so. */
2239 if (op1 == const1_rtx)
2240 return rem_flag ? const0_rtx : op0;
2242 /* Don't use the function value register as a target
2243 since we have to read it as well as write it,
2244 and function-inlining gets confused by this. */
2245 if (target && REG_P (target) && REG_FUNCTION_VALUE_P (target))
2248 /* Don't clobber an operand while doing a multi-step calculation. */
2250 if ((rem_flag && (reg_mentioned_p (target, op0)
2251 || (GET_CODE (op0) == MEM && GET_CODE (target) == MEM)))
2252 || reg_mentioned_p (target, op1)
2253 || (GET_CODE (op1) == MEM && GET_CODE (target) == MEM))
2256 can_clobber_op0 = (GET_CODE (op0) == REG && op0 == target);
2258 if (GET_CODE (op1) == CONST_INT)
2259 log = exact_log2 (INTVAL (op1));
2261 /* If log is >= 0, we are dividing by 2**log, and will do it by shifting,
2262 which is really floor-division. Otherwise we will really do a divide,
2263 and we assume that is trunc-division.
2265 We must correct the dividend by adding or subtracting something
2266 based on the divisor, in order to do the kind of rounding specified
2267 by CODE. The correction depends on what kind of rounding is actually
2268 available, and that depends on whether we will shift or divide.
2270 In many of these cases it is possible to perform the operation by a
2271 clever series of logical operations (shifts and/or exclusive-ors).
2272 Although avoiding the jump has the advantage that it extends the basic
2273 block and allows further optimization, the branch-free code is normally
2274 at least one instruction longer in the (most common) case where the
2275 dividend is non-negative. Performance measurements of the two
2276 alternatives show that the branch-free code is slightly faster on the
2277 IBM ROMP but slower on CISC processors (significantly slower on the
2278 VAX). Accordingly, the jump code has been retained.
2280 On machines where the jump code is slower, the cost of a DIV or MOD
2281 operation can be set small (less than twice that of an addition); in
2282 that case, we pretend that we don't have a power of two and perform
2283 a normal division or modulus operation. */
2285 if ((code == TRUNC_MOD_EXPR || code == TRUNC_DIV_EXPR)
2287 && (rem_flag ? smod_pow2_cheap : sdiv_pow2_cheap))
2290 /* Get the mode in which to perform this computation. Normally it will
2291 be MODE, but sometimes we can't do the desired operation in MODE.
2292 If so, pick a wider mode in which we can do the operation. Convert
2293 to that mode at the start to avoid repeated conversions.
2295 First see what operations we need. These depend on the expression
2296 we are evaluating. (We assume that divxx3 insns exist under the
2297 same conditions that modxx3 insns and that these insns don't normally
2298 fail. If these assumptions are not correct, we may generate less
2299 efficient code in some cases.)
2301 Then see if we find a mode in which we can open-code that operation
2302 (either a division, modulus, or shift). Finally, check for the smallest
2303 mode for which we can do the operation with a library call. */
2305 optab1 = (log >= 0 ? (unsignedp ? lshr_optab : ashr_optab)
2306 : (unsignedp ? udiv_optab : sdiv_optab));
2307 optab2 = (log >= 0 ? optab1 : (unsignedp ? udivmod_optab : sdivmod_optab));
2309 for (compute_mode = mode; compute_mode != VOIDmode;
2310 compute_mode = GET_MODE_WIDER_MODE (compute_mode))
2311 if (optab1->handlers[(int) compute_mode].insn_code != CODE_FOR_nothing
2312 || optab2->handlers[(int) compute_mode].insn_code != CODE_FOR_nothing)
2315 if (compute_mode == VOIDmode)
2316 for (compute_mode = mode; compute_mode != VOIDmode;
2317 compute_mode = GET_MODE_WIDER_MODE (compute_mode))
2318 if (optab1->handlers[(int) compute_mode].libfunc
2319 || optab2->handlers[(int) compute_mode].libfunc)
2322 /* If we still couldn't find a mode, use MODE; we'll probably abort in
2324 if (compute_mode == VOIDmode)
2325 compute_mode = mode;
2327 size = GET_MODE_BITSIZE (compute_mode);
2329 /* Now convert to the best mode to use. Show we made a copy of OP0
2330 and hence we can clobber it (we cannot use a SUBREG to widen
2332 if (compute_mode != mode)
2334 adjusted_op0 = op0 = convert_to_mode (compute_mode, op0, unsignedp);
2335 can_clobber_op0 = 1;
2336 op1 = convert_to_mode (compute_mode, op1, unsignedp);
2339 /* If we are computing the remainder and one of the operands is a volatile
2340 MEM, copy it into a register. */
2342 if (rem_flag && GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0))
2343 adjusted_op0 = op0 = force_reg (compute_mode, op0), can_clobber_op0 = 1;
2344 if (rem_flag && GET_CODE (op1) == MEM && MEM_VOLATILE_P (op1))
2345 op1 = force_reg (compute_mode, op1);
2347 /* If we are computing the remainder, op0 will be needed later to calculate
2348 X - Y * (X / Y), therefore cannot be clobbered. */
2350 can_clobber_op0 = 0;
2352 if (target == 0 || GET_MODE (target) != compute_mode)
2353 target = gen_reg_rtx (compute_mode);
2357 case TRUNC_MOD_EXPR:
2358 case TRUNC_DIV_EXPR:
2359 if (log >= 0 && ! unsignedp)
2361 /* Here we need to add OP1-1 if OP0 is negative, 0 otherwise.
2362 This can be computed without jumps by arithmetically shifting
2363 OP0 right LOG-1 places and then shifting right logically
2364 SIZE-LOG bits. The resulting value is unconditionally added
2366 if (log == 1 || BRANCH_COST >= 3)
2368 rtx temp = gen_reg_rtx (compute_mode);
2369 if (! can_clobber_op0)
2370 /* Copy op0 to a reg, to play safe,
2371 since this is done in the other path. */
2372 op0 = force_reg (compute_mode, op0);
2373 temp = copy_to_suggested_reg (adjusted_op0, temp, compute_mode);
2374 temp = expand_shift (RSHIFT_EXPR, compute_mode, temp,
2375 build_int_2 (log - 1, 0), NULL_RTX, 0);
2376 temp = expand_shift (RSHIFT_EXPR, compute_mode, temp,
2377 build_int_2 (size - log, 0),
2379 /* We supply 0 as the target to make a new pseudo
2380 for the value; that helps loop.c optimize the result. */
2381 adjusted_op0 = expand_binop (compute_mode, add_optab,
2383 0, 0, OPTAB_LIB_WIDEN);
2387 rtx label = gen_label_rtx ();
2388 if (! can_clobber_op0)
2390 adjusted_op0 = copy_to_suggested_reg (adjusted_op0, target,
2392 /* Copy op0 to a reg, since emit_cmp_insn will call emit_queue
2393 which will screw up mem refs for autoincrements. */
2394 op0 = force_reg (compute_mode, op0);
2396 emit_cmp_insn (adjusted_op0, const0_rtx, GE,
2397 NULL_RTX, compute_mode, 0, 0);
2398 emit_jump_insn (gen_bge (label));
2399 expand_inc (adjusted_op0, plus_constant (op1, -1));
2402 mod_insn_no_good = 1;
2406 case FLOOR_DIV_EXPR:
2407 case FLOOR_MOD_EXPR:
2408 if (log < 0 && ! unsignedp)
2410 rtx label = gen_label_rtx ();
2411 if (! can_clobber_op0)
2413 adjusted_op0 = copy_to_suggested_reg (adjusted_op0, target,
2415 /* Copy op0 to a reg, since emit_cmp_insn will call emit_queue
2416 which will screw up mem refs for autoincrements. */
2417 op0 = force_reg (compute_mode, op0);
2419 emit_cmp_insn (adjusted_op0, const0_rtx, GE,
2420 NULL_RTX, compute_mode, 0, 0);
2421 emit_jump_insn (gen_bge (label));
2422 expand_dec (adjusted_op0, op1);
2423 expand_inc (adjusted_op0, const1_rtx);
2425 mod_insn_no_good = 1;
2431 if (! can_clobber_op0)
2433 adjusted_op0 = copy_to_suggested_reg (adjusted_op0, target,
2435 /* Copy op0 to a reg, since emit_cmp_insn will call emit_queue
2436 which will screw up mem refs for autoincrements. */
2437 op0 = force_reg (compute_mode, op0);
2444 label = gen_label_rtx ();
2445 emit_cmp_insn (adjusted_op0, const0_rtx, LE,
2446 NULL_RTX, compute_mode, 0, 0);
2447 emit_jump_insn (gen_ble (label));
2449 expand_inc (adjusted_op0, op1);
2450 expand_dec (adjusted_op0, const1_rtx);
2456 adjusted_op0 = expand_binop (compute_mode, add_optab,
2457 adjusted_op0, plus_constant (op1, -1),
2458 NULL_RTX, 0, OPTAB_LIB_WIDEN);
2460 mod_insn_no_good = 1;
2463 case ROUND_DIV_EXPR:
2464 case ROUND_MOD_EXPR:
2465 if (! can_clobber_op0)
2467 adjusted_op0 = copy_to_suggested_reg (adjusted_op0, target,
2469 /* Copy op0 to a reg, since emit_cmp_insn will call emit_queue
2470 which will screw up mem refs for autoincrements. */
2471 op0 = force_reg (compute_mode, op0);
2475 op1 = expand_shift (RSHIFT_EXPR, compute_mode, op1,
2476 integer_one_node, NULL_RTX, 0);
2479 if (BRANCH_COST >= 2)
2481 /* Negate OP1 if OP0 < 0. Do this by computing a temporary
2482 that has all bits equal to the sign bit and exclusive
2483 or-ing it with OP1. */
2484 rtx temp = gen_reg_rtx (compute_mode);
2485 temp = copy_to_suggested_reg (adjusted_op0, temp, compute_mode);
2486 temp = expand_shift (RSHIFT_EXPR, compute_mode, temp,
2487 build_int_2 (size - 1, 0),
2489 op1 = expand_binop (compute_mode, xor_optab, op1, temp, op1,
2490 unsignedp, OPTAB_LIB_WIDEN);
2494 rtx label = gen_label_rtx ();
2495 emit_cmp_insn (adjusted_op0, const0_rtx, GE, NULL_RTX,
2496 compute_mode, 0, 0);
2497 emit_jump_insn (gen_bge (label));
2498 expand_unop (compute_mode, neg_optab, op1, op1, 0);
2502 expand_inc (adjusted_op0, op1);
2506 op1 = GEN_INT (((HOST_WIDE_INT) 1 << log) / 2);
2507 expand_inc (adjusted_op0, op1);
2509 mod_insn_no_good = 1;
2513 if (rem_flag && !mod_insn_no_good)
2515 /* Try to produce the remainder directly */
2517 result = expand_binop (compute_mode, and_optab, adjusted_op0,
2518 GEN_INT (((HOST_WIDE_INT) 1 << log) - 1),
2519 target, 1, OPTAB_LIB_WIDEN);
2522 /* See if we can do remainder without a library call. */
2523 result = sign_expand_binop (mode, umod_optab, smod_optab,
2524 adjusted_op0, op1, target,
2525 unsignedp, OPTAB_WIDEN);
2528 /* No luck there. Can we do remainder and divide at once
2529 without a library call? */
2530 result = gen_reg_rtx (compute_mode);
2531 if (! expand_twoval_binop (unsignedp
2532 ? udivmod_optab : sdivmod_optab,
2534 NULL_RTX, result, unsignedp))
2541 return gen_lowpart (mode, result);
2543 /* Produce the quotient. */
2545 result = expand_shift (RSHIFT_EXPR, compute_mode, adjusted_op0,
2546 build_int_2 (log, 0), target, unsignedp);
2547 else if (rem_flag && !mod_insn_no_good)
2548 /* If producing quotient in order to subtract for remainder,
2549 and a remainder subroutine would be ok,
2550 don't use a divide subroutine. */
2551 result = sign_expand_binop (compute_mode, udiv_optab, sdiv_optab,
2552 adjusted_op0, op1, NULL_RTX, unsignedp,
2556 /* Try a quotient insn, but not a library call. */
2557 result = sign_expand_binop (compute_mode, udiv_optab, sdiv_optab,
2559 rem_flag ? NULL_RTX : target,
2560 unsignedp, OPTAB_WIDEN);
2563 /* No luck there. Try a quotient-and-remainder insn,
2564 keeping the quotient alone. */
2565 result = gen_reg_rtx (mode);
2566 if (! expand_twoval_binop (unsignedp ? udivmod_optab : sdivmod_optab,
2568 result, NULL_RTX, unsignedp))
2572 /* If still no luck, use a library call. */
2574 result = sign_expand_binop (compute_mode, udiv_optab, sdiv_optab,
2576 rem_flag ? NULL_RTX : target,
2577 unsignedp, OPTAB_LIB_WIDEN);
2580 /* If we really want the remainder, get it by subtraction. */
2584 /* No divide instruction either. Use library for remainder. */
2585 result = sign_expand_binop (compute_mode, umod_optab, smod_optab,
2587 unsignedp, OPTAB_LIB_WIDEN);
2590 /* We divided. Now finish doing X - Y * (X / Y). */
2591 result = expand_mult (compute_mode, result, op1, target, unsignedp);
2592 if (! result) abort ();
2593 result = expand_binop (compute_mode, sub_optab, op0,
2594 result, target, unsignedp, OPTAB_LIB_WIDEN);
2601 return gen_lowpart (mode, result);
2604 /* Return a tree node with data type TYPE, describing the value of X.
2605 Usually this is an RTL_EXPR, if there is no obvious better choice.
2606 X may be an expression, however we only support those expressions
2607 generated by loop.c. */
2616 switch (GET_CODE (x))
2619 t = build_int_2 (INTVAL (x),
2620 ! TREE_UNSIGNED (type) && INTVAL (x) >= 0 ? 0 : -1);
2621 TREE_TYPE (t) = type;
2625 if (GET_MODE (x) == VOIDmode)
2627 t = build_int_2 (CONST_DOUBLE_LOW (x), CONST_DOUBLE_HIGH (x));
2628 TREE_TYPE (t) = type;
2634 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
2635 t = build_real (type, d);
2641 return fold (build (PLUS_EXPR, type, make_tree (type, XEXP (x, 0)),
2642 make_tree (type, XEXP (x, 1))));
2645 return fold (build (MINUS_EXPR, type, make_tree (type, XEXP (x, 0)),
2646 make_tree (type, XEXP (x, 1))));
2649 return fold (build1 (NEGATE_EXPR, type, make_tree (type, XEXP (x, 0))));
2652 return fold (build (MULT_EXPR, type, make_tree (type, XEXP (x, 0)),
2653 make_tree (type, XEXP (x, 1))));
2656 return fold (build (LSHIFT_EXPR, type, make_tree (type, XEXP (x, 0)),
2657 make_tree (type, XEXP (x, 1))));
2660 return fold (convert (type,
2661 build (RSHIFT_EXPR, unsigned_type (type),
2662 make_tree (unsigned_type (type),
2664 make_tree (type, XEXP (x, 1)))));
2667 return fold (convert (type,
2668 build (RSHIFT_EXPR, signed_type (type),
2669 make_tree (signed_type (type), XEXP (x, 0)),
2670 make_tree (type, XEXP (x, 1)))));
2673 if (TREE_CODE (type) != REAL_TYPE)
2674 t = signed_type (type);
2678 return fold (convert (type,
2679 build (TRUNC_DIV_EXPR, t,
2680 make_tree (t, XEXP (x, 0)),
2681 make_tree (t, XEXP (x, 1)))));
2683 t = unsigned_type (type);
2684 return fold (convert (type,
2685 build (TRUNC_DIV_EXPR, t,
2686 make_tree (t, XEXP (x, 0)),
2687 make_tree (t, XEXP (x, 1)))));
2689 t = make_node (RTL_EXPR);
2690 TREE_TYPE (t) = type;
2691 RTL_EXPR_RTL (t) = x;
2692 /* There are no insns to be output
2693 when this rtl_expr is used. */
2694 RTL_EXPR_SEQUENCE (t) = 0;
2699 /* Return an rtx representing the value of X * MULT + ADD.
2700 TARGET is a suggestion for where to store the result (an rtx).
2701 MODE is the machine mode for the computation.
2702 X and MULT must have mode MODE. ADD may have a different mode.
2703 So can X (defaults to same as MODE).
2704 UNSIGNEDP is non-zero to do unsigned multiplication.
2705 This may emit insns. */
2708 expand_mult_add (x, target, mult, add, mode, unsignedp)
2709 rtx x, target, mult, add;
2710 enum machine_mode mode;
2713 tree type = type_for_mode (mode, unsignedp);
2714 tree add_type = (GET_MODE (add) == VOIDmode
2715 ? type : type_for_mode (GET_MODE (add), unsignedp));
2716 tree result = fold (build (PLUS_EXPR, type,
2717 fold (build (MULT_EXPR, type,
2718 make_tree (type, x),
2719 make_tree (type, mult))),
2720 make_tree (add_type, add)));
2722 return expand_expr (result, target, VOIDmode, 0);
2725 /* Compute the logical-and of OP0 and OP1, storing it in TARGET
2726 and returning TARGET.
2728 If TARGET is 0, a pseudo-register or constant is returned. */
2731 expand_and (op0, op1, target)
2732 rtx op0, op1, target;
2734 enum machine_mode mode = VOIDmode;
2737 if (GET_MODE (op0) != VOIDmode)
2738 mode = GET_MODE (op0);
2739 else if (GET_MODE (op1) != VOIDmode)
2740 mode = GET_MODE (op1);
2742 if (mode != VOIDmode)
2743 tem = expand_binop (mode, and_optab, op0, op1, target, 0, OPTAB_LIB_WIDEN);
2744 else if (GET_CODE (op0) == CONST_INT && GET_CODE (op1) == CONST_INT)
2745 tem = GEN_INT (INTVAL (op0) & INTVAL (op1));
2751 else if (tem != target)
2752 emit_move_insn (target, tem);
2756 /* Emit a store-flags instruction for comparison CODE on OP0 and OP1
2757 and storing in TARGET. Normally return TARGET.
2758 Return 0 if that cannot be done.
2760 MODE is the mode to use for OP0 and OP1 should they be CONST_INTs. If
2761 it is VOIDmode, they cannot both be CONST_INT.
2763 UNSIGNEDP is for the case where we have to widen the operands
2764 to perform the operation. It says to use zero-extension.
2766 NORMALIZEP is 1 if we should convert the result to be either zero
2767 or one one. Normalize is -1 if we should convert the result to be
2768 either zero or -1. If NORMALIZEP is zero, the result will be left
2769 "raw" out of the scc insn. */
2772 emit_store_flag (target, code, op0, op1, mode, unsignedp, normalizep)
2776 enum machine_mode mode;
2781 enum insn_code icode;
2782 enum machine_mode compare_mode;
2783 enum machine_mode target_mode = GET_MODE (target);
2786 rtx pattern, comparison;
2788 if (mode == VOIDmode)
2789 mode = GET_MODE (op0);
2791 /* If one operand is constant, make it the second one. Only do this
2792 if the other operand is not constant as well. */
2794 if ((CONSTANT_P (op0) && ! CONSTANT_P (op1))
2795 || (GET_CODE (op0) == CONST_INT && GET_CODE (op1) != CONST_INT))
2800 code = swap_condition (code);
2803 /* For some comparisons with 1 and -1, we can convert this to
2804 comparisons with zero. This will often produce more opportunities for
2805 store-flag insns. */
2810 if (op1 == const1_rtx)
2811 op1 = const0_rtx, code = LE;
2814 if (op1 == constm1_rtx)
2815 op1 = const0_rtx, code = LT;
2818 if (op1 == const1_rtx)
2819 op1 = const0_rtx, code = GT;
2822 if (op1 == constm1_rtx)
2823 op1 = const0_rtx, code = GE;
2826 if (op1 == const1_rtx)
2827 op1 = const0_rtx, code = NE;
2830 if (op1 == const1_rtx)
2831 op1 = const0_rtx, code = EQ;
2835 /* From now on, we won't change CODE, so set ICODE now. */
2836 icode = setcc_gen_code[(int) code];
2838 /* If this is A < 0 or A >= 0, we can do this by taking the ones
2839 complement of A (for GE) and shifting the sign bit to the low bit. */
2840 if (op1 == const0_rtx && (code == LT || code == GE)
2841 && GET_MODE_CLASS (mode) == MODE_INT
2842 && (normalizep || STORE_FLAG_VALUE == 1
2843 || (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
2844 && (STORE_FLAG_VALUE
2845 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1)))))
2849 /* If the result is to be wider than OP0, it is best to convert it
2850 first. If it is to be narrower, it is *incorrect* to convert it
2852 if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (mode))
2854 op0 = protect_from_queue (op0, 0);
2855 op0 = convert_to_mode (target_mode, op0, 0);
2859 if (target_mode != mode)
2863 op0 = expand_unop (mode, one_cmpl_optab, op0, subtarget, 0);
2865 if (normalizep || STORE_FLAG_VALUE == 1)
2866 /* If we are supposed to produce a 0/1 value, we want to do
2867 a logical shift from the sign bit to the low-order bit; for
2868 a -1/0 value, we do an arithmetic shift. */
2869 op0 = expand_shift (RSHIFT_EXPR, mode, op0,
2870 size_int (GET_MODE_BITSIZE (mode) - 1),
2871 subtarget, normalizep != -1);
2873 if (mode != target_mode)
2874 op0 = convert_to_mode (target_mode, op0, 0);
2879 if (icode != CODE_FOR_nothing)
2881 /* We think we may be able to do this with a scc insn. Emit the
2882 comparison and then the scc insn.
2884 compare_from_rtx may call emit_queue, which would be deleted below
2885 if the scc insn fails. So call it ourselves before setting LAST. */
2888 last = get_last_insn ();
2891 = compare_from_rtx (op0, op1, code, unsignedp, mode, NULL_RTX, 0);
2892 if (GET_CODE (comparison) == CONST_INT)
2893 return (comparison == const0_rtx ? const0_rtx
2894 : normalizep == 1 ? const1_rtx
2895 : normalizep == -1 ? constm1_rtx
2898 /* If the code of COMPARISON doesn't match CODE, something is
2899 wrong; we can no longer be sure that we have the operation.
2900 We could handle this case, but it should not happen. */
2902 if (GET_CODE (comparison) != code)
2905 /* Get a reference to the target in the proper mode for this insn. */
2906 compare_mode = insn_operand_mode[(int) icode][0];
2908 if (preserve_subexpressions_p ()
2909 || ! (*insn_operand_predicate[(int) icode][0]) (subtarget, compare_mode))
2910 subtarget = gen_reg_rtx (compare_mode);
2912 pattern = GEN_FCN (icode) (subtarget);
2915 emit_insn (pattern);
2917 /* If we are converting to a wider mode, first convert to
2918 TARGET_MODE, then normalize. This produces better combining
2919 opportunities on machines that have a SIGN_EXTRACT when we are
2920 testing a single bit. This mostly benefits the 68k.
2922 If STORE_FLAG_VALUE does not have the sign bit set when
2923 interpreted in COMPARE_MODE, we can do this conversion as
2924 unsigned, which is usually more efficient. */
2925 if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (compare_mode))
2927 convert_move (target, subtarget,
2928 (GET_MODE_BITSIZE (compare_mode)
2929 <= HOST_BITS_PER_WIDE_INT)
2930 && 0 == (STORE_FLAG_VALUE
2931 & ((HOST_WIDE_INT) 1
2932 << (GET_MODE_BITSIZE (compare_mode) -1))));
2934 compare_mode = target_mode;
2939 /* If we want to keep subexpressions around, don't reuse our
2942 if (preserve_subexpressions_p ())
2945 /* Now normalize to the proper value in COMPARE_MODE. Sometimes
2946 we don't have to do anything. */
2947 if (normalizep == 0 || normalizep == STORE_FLAG_VALUE)
2949 else if (normalizep == - STORE_FLAG_VALUE)
2950 op0 = expand_unop (compare_mode, neg_optab, op0, subtarget, 0);
2952 /* We don't want to use STORE_FLAG_VALUE < 0 below since this
2953 makes it hard to use a value of just the sign bit due to
2954 ANSI integer constant typing rules. */
2955 else if (GET_MODE_BITSIZE (compare_mode) <= HOST_BITS_PER_WIDE_INT
2956 && (STORE_FLAG_VALUE
2957 & ((HOST_WIDE_INT) 1
2958 << (GET_MODE_BITSIZE (compare_mode) - 1))))
2959 op0 = expand_shift (RSHIFT_EXPR, compare_mode, op0,
2960 size_int (GET_MODE_BITSIZE (compare_mode) - 1),
2961 subtarget, normalizep == 1);
2962 else if (STORE_FLAG_VALUE & 1)
2964 op0 = expand_and (op0, const1_rtx, subtarget);
2965 if (normalizep == -1)
2966 op0 = expand_unop (compare_mode, neg_optab, op0, op0, 0);
2971 /* If we were converting to a smaller mode, do the
2973 if (target_mode != compare_mode)
2975 convert_move (target, op0, 0);
2984 delete_insns_since (last);
2986 subtarget = target_mode == mode ? target : 0;
2988 /* If we reached here, we can't do this with a scc insn. However, there
2989 are some comparisons that can be done directly. For example, if
2990 this is an equality comparison of integers, we can try to exclusive-or
2991 (or subtract) the two operands and use a recursive call to try the
2992 comparison with zero. Don't do any of these cases if branches are
2996 && GET_MODE_CLASS (mode) == MODE_INT && (code == EQ || code == NE)
2997 && op1 != const0_rtx)
2999 tem = expand_binop (mode, xor_optab, op0, op1, subtarget, 1,
3003 tem = expand_binop (mode, sub_optab, op0, op1, subtarget, 1,
3006 tem = emit_store_flag (target, code, tem, const0_rtx,
3007 mode, unsignedp, normalizep);
3009 delete_insns_since (last);
3013 /* Some other cases we can do are EQ, NE, LE, and GT comparisons with
3014 the constant zero. Reject all other comparisons at this point. Only
3015 do LE and GT if branches are expensive since they are expensive on
3016 2-operand machines. */
3018 if (BRANCH_COST == 0
3019 || GET_MODE_CLASS (mode) != MODE_INT || op1 != const0_rtx
3020 || (code != EQ && code != NE
3021 && (BRANCH_COST <= 1 || (code != LE && code != GT))))
3024 /* See what we need to return. We can only return a 1, -1, or the
3027 if (normalizep == 0)
3029 if (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
3030 normalizep = STORE_FLAG_VALUE;
3032 else if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3033 && (STORE_FLAG_VALUE
3034 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1)))
3040 /* Try to put the result of the comparison in the sign bit. Assume we can't
3041 do the necessary operation below. */
3045 /* To see if A <= 0, compute (A | (A - 1)). A <= 0 iff that result has
3046 the sign bit set. */
3050 /* This is destructive, so SUBTARGET can't be OP0. */
3051 if (rtx_equal_p (subtarget, op0))
3054 tem = expand_binop (mode, sub_optab, op0, const1_rtx, subtarget, 0,
3057 tem = expand_binop (mode, ior_optab, op0, tem, subtarget, 0,
3061 /* To see if A > 0, compute (((signed) A) << BITS) - A, where BITS is the
3062 number of bits in the mode of OP0, minus one. */
3066 if (rtx_equal_p (subtarget, op0))
3069 tem = expand_shift (RSHIFT_EXPR, mode, op0,
3070 size_int (GET_MODE_BITSIZE (mode) - 1),
3072 tem = expand_binop (mode, sub_optab, tem, op0, subtarget, 0,
3076 if (code == EQ || code == NE)
3078 /* For EQ or NE, one way to do the comparison is to apply an operation
3079 that converts the operand into a positive number if it is non-zero
3080 or zero if it was originally zero. Then, for EQ, we subtract 1 and
3081 for NE we negate. This puts the result in the sign bit. Then we
3082 normalize with a shift, if needed.
3084 Two operations that can do the above actions are ABS and FFS, so try
3085 them. If that doesn't work, and MODE is smaller than a full word,
3086 we can use zero-extension to the wider mode (an unsigned conversion)
3087 as the operation. */
3089 if (abs_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
3090 tem = expand_unop (mode, abs_optab, op0, subtarget, 1);
3091 else if (ffs_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
3092 tem = expand_unop (mode, ffs_optab, op0, subtarget, 1);
3093 else if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3096 op0 = protect_from_queue (op0, 0);
3097 tem = convert_to_mode (mode, op0, 1);
3103 tem = expand_binop (mode, sub_optab, tem, const1_rtx, subtarget,
3106 tem = expand_unop (mode, neg_optab, tem, subtarget, 0);
3109 /* If we couldn't do it that way, for NE we can "or" the two's complement
3110 of the value with itself. For EQ, we take the one's complement of
3111 that "or", which is an extra insn, so we only handle EQ if branches
3114 if (tem == 0 && (code == NE || BRANCH_COST > 1))
3116 if (rtx_equal_p (subtarget, op0))
3119 tem = expand_unop (mode, neg_optab, op0, subtarget, 0);
3120 tem = expand_binop (mode, ior_optab, tem, op0, subtarget, 0,
3123 if (tem && code == EQ)
3124 tem = expand_unop (mode, one_cmpl_optab, tem, subtarget, 0);
3128 if (tem && normalizep)
3129 tem = expand_shift (RSHIFT_EXPR, mode, tem,
3130 size_int (GET_MODE_BITSIZE (mode) - 1),
3131 tem, normalizep == 1);
3133 if (tem && GET_MODE (tem) != target_mode)
3135 convert_move (target, tem, 0);
3140 delete_insns_since (last);
3144 emit_jump_insn ((*bcc_gen_fctn[(int) code]) (label));
3145 emit_move_insn (target, const1_rtx);