1 /* Medium-level subroutines: convert bit-field store and extract
2 and shifts, multiplies and divides to rtl instructions.
3 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
4 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 2, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
26 #include "coretypes.h"
33 #include "insn-config.h"
38 #include "langhooks.h"
40 static void store_fixed_bit_field (rtx, unsigned HOST_WIDE_INT,
41 unsigned HOST_WIDE_INT,
42 unsigned HOST_WIDE_INT, rtx);
43 static void store_split_bit_field (rtx, unsigned HOST_WIDE_INT,
44 unsigned HOST_WIDE_INT, rtx);
45 static rtx extract_fixed_bit_field (enum machine_mode, rtx,
46 unsigned HOST_WIDE_INT,
47 unsigned HOST_WIDE_INT,
48 unsigned HOST_WIDE_INT, rtx, int);
49 static rtx mask_rtx (enum machine_mode, int, int, int);
50 static rtx lshift_value (enum machine_mode, rtx, int, int);
51 static rtx extract_split_bit_field (rtx, unsigned HOST_WIDE_INT,
52 unsigned HOST_WIDE_INT, int);
53 static void do_cmp_and_jump (rtx, rtx, enum rtx_code, enum machine_mode, rtx);
55 /* Nonzero means divides or modulus operations are relatively cheap for
56 powers of two, so don't use branches; emit the operation instead.
57 Usually, this will mean that the MD file will emit non-branch
60 static int sdiv_pow2_cheap[NUM_MACHINE_MODES];
61 static int smod_pow2_cheap[NUM_MACHINE_MODES];
63 #ifndef SLOW_UNALIGNED_ACCESS
64 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) STRICT_ALIGNMENT
67 /* For compilers that support multiple targets with different word sizes,
68 MAX_BITS_PER_WORD contains the biggest value of BITS_PER_WORD. An example
69 is the H8/300(H) compiler. */
71 #ifndef MAX_BITS_PER_WORD
72 #define MAX_BITS_PER_WORD BITS_PER_WORD
75 /* Reduce conditional compilation elsewhere. */
78 #define CODE_FOR_insv CODE_FOR_nothing
79 #define gen_insv(a,b,c,d) NULL_RTX
83 #define CODE_FOR_extv CODE_FOR_nothing
84 #define gen_extv(a,b,c,d) NULL_RTX
88 #define CODE_FOR_extzv CODE_FOR_nothing
89 #define gen_extzv(a,b,c,d) NULL_RTX
92 /* Cost of various pieces of RTL. Note that some of these are indexed by
93 shift count and some by mode. */
95 static int add_cost[NUM_MACHINE_MODES];
96 static int neg_cost[NUM_MACHINE_MODES];
97 static int shift_cost[MAX_BITS_PER_WORD];
98 static int shiftadd_cost[MAX_BITS_PER_WORD];
99 static int shiftsub_cost[MAX_BITS_PER_WORD];
100 static int mul_cost[NUM_MACHINE_MODES];
101 static int div_cost[NUM_MACHINE_MODES];
102 static int mul_widen_cost[NUM_MACHINE_MODES];
103 static int mul_highpart_cost[NUM_MACHINE_MODES];
108 rtx reg, shift_insn, shiftadd_insn, shiftsub_insn;
111 enum machine_mode mode, wider_mode;
115 /* This is "some random pseudo register" for purposes of calling recog
116 to see what insns exist. */
117 reg = gen_rtx_REG (word_mode, 10000);
119 zero_cost = rtx_cost (const0_rtx, 0);
121 shift_insn = emit_insn (gen_rtx_SET (VOIDmode, reg,
122 gen_rtx_ASHIFT (word_mode, reg,
126 = emit_insn (gen_rtx_SET (VOIDmode, reg,
127 gen_rtx_PLUS (word_mode,
128 gen_rtx_MULT (word_mode,
133 = emit_insn (gen_rtx_SET (VOIDmode, reg,
134 gen_rtx_MINUS (word_mode,
135 gen_rtx_MULT (word_mode,
142 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
144 mode = GET_MODE_WIDER_MODE (mode))
146 reg = gen_rtx_REG (mode, 10000);
147 add_cost[mode] = rtx_cost (gen_rtx_PLUS (mode, reg, reg), SET);
148 neg_cost[mode] = rtx_cost (gen_rtx_NEG (mode, reg), SET);
149 div_cost[mode] = rtx_cost (gen_rtx_UDIV (mode, reg, reg), SET);
150 mul_cost[mode] = rtx_cost (gen_rtx_MULT (mode, reg, reg), SET);
152 sdiv_pow2_cheap[mode]
153 = (rtx_cost (gen_rtx_DIV (mode, reg, GEN_INT (32)), SET)
154 <= 2 * add_cost[mode]);
155 smod_pow2_cheap[mode]
156 = (rtx_cost (gen_rtx_MOD (mode, reg, GEN_INT (32)), SET)
157 <= 2 * add_cost[mode]);
159 wider_mode = GET_MODE_WIDER_MODE (mode);
160 if (wider_mode != VOIDmode)
162 mul_widen_cost[wider_mode]
163 = rtx_cost (gen_rtx_MULT (wider_mode,
164 gen_rtx_ZERO_EXTEND (wider_mode, reg),
165 gen_rtx_ZERO_EXTEND (wider_mode, reg)),
167 mul_highpart_cost[mode]
168 = rtx_cost (gen_rtx_TRUNCATE
170 gen_rtx_LSHIFTRT (wider_mode,
171 gen_rtx_MULT (wider_mode,
176 GEN_INT (GET_MODE_BITSIZE (mode)))),
182 shiftadd_cost[0] = shiftsub_cost[0] = add_cost[word_mode];
184 for (m = 1; m < MAX_BITS_PER_WORD; m++)
186 rtx c_int = GEN_INT ((HOST_WIDE_INT) 1 << m);
187 shift_cost[m] = shiftadd_cost[m] = shiftsub_cost[m] = 32000;
189 XEXP (SET_SRC (PATTERN (shift_insn)), 1) = GEN_INT (m);
190 if (recog (PATTERN (shift_insn), shift_insn, &dummy) >= 0)
191 shift_cost[m] = rtx_cost (SET_SRC (PATTERN (shift_insn)), SET);
193 XEXP (XEXP (SET_SRC (PATTERN (shiftadd_insn)), 0), 1) = c_int;
194 if (recog (PATTERN (shiftadd_insn), shiftadd_insn, &dummy) >= 0)
195 shiftadd_cost[m] = rtx_cost (SET_SRC (PATTERN (shiftadd_insn)), SET);
197 XEXP (XEXP (SET_SRC (PATTERN (shiftsub_insn)), 0), 1) = c_int;
198 if (recog (PATTERN (shiftsub_insn), shiftsub_insn, &dummy) >= 0)
199 shiftsub_cost[m] = rtx_cost (SET_SRC (PATTERN (shiftsub_insn)), SET);
205 /* Return an rtx representing minus the value of X.
206 MODE is the intended mode of the result,
207 useful if X is a CONST_INT. */
210 negate_rtx (enum machine_mode mode, rtx x)
212 rtx result = simplify_unary_operation (NEG, mode, x, mode);
215 result = expand_unop (mode, neg_optab, x, NULL_RTX, 0);
220 /* Report on the availability of insv/extv/extzv and the desired mode
221 of each of their operands. Returns MAX_MACHINE_MODE if HAVE_foo
222 is false; else the mode of the specified operand. If OPNO is -1,
223 all the caller cares about is whether the insn is available. */
225 mode_for_extraction (enum extraction_pattern pattern, int opno)
227 const struct insn_data *data;
234 data = &insn_data[CODE_FOR_insv];
237 return MAX_MACHINE_MODE;
242 data = &insn_data[CODE_FOR_extv];
245 return MAX_MACHINE_MODE;
250 data = &insn_data[CODE_FOR_extzv];
253 return MAX_MACHINE_MODE;
262 /* Everyone who uses this function used to follow it with
263 if (result == VOIDmode) result = word_mode; */
264 if (data->operand[opno].mode == VOIDmode)
266 return data->operand[opno].mode;
270 /* Generate code to store value from rtx VALUE
271 into a bit-field within structure STR_RTX
272 containing BITSIZE bits starting at bit BITNUM.
273 FIELDMODE is the machine-mode of the FIELD_DECL node for this field.
274 ALIGN is the alignment that STR_RTX is known to have.
275 TOTAL_SIZE is the size of the structure in bytes, or -1 if varying. */
277 /* ??? Note that there are two different ideas here for how
278 to determine the size to count bits within, for a register.
279 One is BITS_PER_WORD, and the other is the size of operand 3
282 If operand 3 of the insv pattern is VOIDmode, then we will use BITS_PER_WORD
283 else, we use the mode of operand 3. */
286 store_bit_field (rtx str_rtx, unsigned HOST_WIDE_INT bitsize,
287 unsigned HOST_WIDE_INT bitnum, enum machine_mode fieldmode,
288 rtx value, HOST_WIDE_INT total_size)
291 = (GET_CODE (str_rtx) == MEM) ? BITS_PER_UNIT : BITS_PER_WORD;
292 unsigned HOST_WIDE_INT offset = bitnum / unit;
293 unsigned HOST_WIDE_INT bitpos = bitnum % unit;
297 enum machine_mode op_mode = mode_for_extraction (EP_insv, 3);
299 /* Discount the part of the structure before the desired byte.
300 We need to know how many bytes are safe to reference after it. */
302 total_size -= (bitpos / BIGGEST_ALIGNMENT
303 * (BIGGEST_ALIGNMENT / BITS_PER_UNIT));
305 while (GET_CODE (op0) == SUBREG)
307 /* The following line once was done only if WORDS_BIG_ENDIAN,
308 but I think that is a mistake. WORDS_BIG_ENDIAN is
309 meaningful at a much higher level; when structures are copied
310 between memory and regs, the higher-numbered regs
311 always get higher addresses. */
312 offset += (SUBREG_BYTE (op0) / UNITS_PER_WORD);
313 /* We used to adjust BITPOS here, but now we do the whole adjustment
314 right after the loop. */
315 op0 = SUBREG_REG (op0);
318 value = protect_from_queue (value, 0);
320 /* Use vec_extract patterns for extracting parts of vectors whenever
322 if (VECTOR_MODE_P (GET_MODE (op0))
323 && GET_CODE (op0) != MEM
324 && (vec_set_optab->handlers[GET_MODE (op0)].insn_code
326 && fieldmode == GET_MODE_INNER (GET_MODE (op0))
327 && bitsize == GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0)))
328 && !(bitnum % GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0)))))
330 enum machine_mode outermode = GET_MODE (op0);
331 enum machine_mode innermode = GET_MODE_INNER (outermode);
332 int icode = (int) vec_set_optab->handlers[outermode].insn_code;
333 int pos = bitnum / GET_MODE_BITSIZE (innermode);
334 rtx rtxpos = GEN_INT (pos);
338 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
339 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
340 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
344 if (! (*insn_data[icode].operand[1].predicate) (src, mode1))
345 src = copy_to_mode_reg (mode1, src);
347 if (! (*insn_data[icode].operand[2].predicate) (rtxpos, mode2))
348 rtxpos = copy_to_mode_reg (mode1, rtxpos);
350 /* We could handle this, but we should always be called with a pseudo
351 for our targets and all insns should take them as outputs. */
352 if (! (*insn_data[icode].operand[0].predicate) (dest, mode0)
353 || ! (*insn_data[icode].operand[1].predicate) (src, mode1)
354 || ! (*insn_data[icode].operand[2].predicate) (rtxpos, mode2))
356 pat = GEN_FCN (icode) (dest, src, rtxpos);
369 int old_generating_concat_p = generating_concat_p;
370 generating_concat_p = 0;
371 value = force_not_mem (value);
372 generating_concat_p = old_generating_concat_p;
375 /* If the target is a register, overwriting the entire object, or storing
376 a full-word or multi-word field can be done with just a SUBREG.
378 If the target is memory, storing any naturally aligned field can be
379 done with a simple store. For targets that support fast unaligned
380 memory, any naturally sized, unit aligned field can be done directly. */
382 byte_offset = (bitnum % BITS_PER_WORD) / BITS_PER_UNIT
383 + (offset * UNITS_PER_WORD);
386 && bitsize == GET_MODE_BITSIZE (fieldmode)
387 && (GET_CODE (op0) != MEM
388 ? ((GET_MODE_SIZE (fieldmode) >= UNITS_PER_WORD
389 || GET_MODE_SIZE (GET_MODE (op0)) == GET_MODE_SIZE (fieldmode))
390 && byte_offset % GET_MODE_SIZE (fieldmode) == 0)
391 : (! SLOW_UNALIGNED_ACCESS (fieldmode, MEM_ALIGN (op0))
392 || (offset * BITS_PER_UNIT % bitsize == 0
393 && MEM_ALIGN (op0) % GET_MODE_BITSIZE (fieldmode) == 0))))
395 if (GET_MODE (op0) != fieldmode)
397 if (GET_CODE (op0) == SUBREG)
399 if (GET_MODE (SUBREG_REG (op0)) == fieldmode
400 || GET_MODE_CLASS (fieldmode) == MODE_INT
401 || GET_MODE_CLASS (fieldmode) == MODE_PARTIAL_INT)
402 op0 = SUBREG_REG (op0);
404 /* Else we've got some float mode source being extracted into
405 a different float mode destination -- this combination of
406 subregs results in Severe Tire Damage. */
409 if (GET_CODE (op0) == REG)
410 op0 = gen_rtx_SUBREG (fieldmode, op0, byte_offset);
412 op0 = adjust_address (op0, fieldmode, offset);
414 emit_move_insn (op0, value);
418 /* Make sure we are playing with integral modes. Pun with subregs
419 if we aren't. This must come after the entire register case above,
420 since that case is valid for any mode. The following cases are only
421 valid for integral modes. */
423 enum machine_mode imode = int_mode_for_mode (GET_MODE (op0));
424 if (imode != GET_MODE (op0))
426 if (GET_CODE (op0) == MEM)
427 op0 = adjust_address (op0, imode, 0);
428 else if (imode != BLKmode)
429 op0 = gen_lowpart (imode, op0);
435 /* We may be accessing data outside the field, which means
436 we can alias adjacent data. */
437 if (GET_CODE (op0) == MEM)
439 op0 = shallow_copy_rtx (op0);
440 set_mem_alias_set (op0, 0);
441 set_mem_expr (op0, 0);
444 /* If OP0 is a register, BITPOS must count within a word.
445 But as we have it, it counts within whatever size OP0 now has.
446 On a bigendian machine, these are not the same, so convert. */
448 && GET_CODE (op0) != MEM
449 && unit > GET_MODE_BITSIZE (GET_MODE (op0)))
450 bitpos += unit - GET_MODE_BITSIZE (GET_MODE (op0));
452 /* Storing an lsb-aligned field in a register
453 can be done with a movestrict instruction. */
455 if (GET_CODE (op0) != MEM
456 && (BYTES_BIG_ENDIAN ? bitpos + bitsize == unit : bitpos == 0)
457 && bitsize == GET_MODE_BITSIZE (fieldmode)
458 && (movstrict_optab->handlers[fieldmode].insn_code
459 != CODE_FOR_nothing))
461 int icode = movstrict_optab->handlers[fieldmode].insn_code;
463 /* Get appropriate low part of the value being stored. */
464 if (GET_CODE (value) == CONST_INT || GET_CODE (value) == REG)
465 value = gen_lowpart (fieldmode, value);
466 else if (!(GET_CODE (value) == SYMBOL_REF
467 || GET_CODE (value) == LABEL_REF
468 || GET_CODE (value) == CONST))
469 value = convert_to_mode (fieldmode, value, 0);
471 if (! (*insn_data[icode].operand[1].predicate) (value, fieldmode))
472 value = copy_to_mode_reg (fieldmode, value);
474 if (GET_CODE (op0) == SUBREG)
476 if (GET_MODE (SUBREG_REG (op0)) == fieldmode
477 || GET_MODE_CLASS (fieldmode) == MODE_INT
478 || GET_MODE_CLASS (fieldmode) == MODE_PARTIAL_INT)
479 op0 = SUBREG_REG (op0);
481 /* Else we've got some float mode source being extracted into
482 a different float mode destination -- this combination of
483 subregs results in Severe Tire Damage. */
487 emit_insn (GEN_FCN (icode)
488 (gen_rtx_SUBREG (fieldmode, op0,
489 (bitnum % BITS_PER_WORD) / BITS_PER_UNIT
490 + (offset * UNITS_PER_WORD)),
496 /* Handle fields bigger than a word. */
498 if (bitsize > BITS_PER_WORD)
500 /* Here we transfer the words of the field
501 in the order least significant first.
502 This is because the most significant word is the one which may
504 However, only do that if the value is not BLKmode. */
506 unsigned int backwards = WORDS_BIG_ENDIAN && fieldmode != BLKmode;
507 unsigned int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD;
510 /* This is the mode we must force value to, so that there will be enough
511 subwords to extract. Note that fieldmode will often (always?) be
512 VOIDmode, because that is what store_field uses to indicate that this
513 is a bit field, but passing VOIDmode to operand_subword_force will
514 result in an abort. */
515 fieldmode = GET_MODE (value);
516 if (fieldmode == VOIDmode)
517 fieldmode = smallest_mode_for_size (nwords * BITS_PER_WORD, MODE_INT);
519 for (i = 0; i < nwords; i++)
521 /* If I is 0, use the low-order word in both field and target;
522 if I is 1, use the next to lowest word; and so on. */
523 unsigned int wordnum = (backwards ? nwords - i - 1 : i);
524 unsigned int bit_offset = (backwards
525 ? MAX ((int) bitsize - ((int) i + 1)
528 : (int) i * BITS_PER_WORD);
530 store_bit_field (op0, MIN (BITS_PER_WORD,
531 bitsize - i * BITS_PER_WORD),
532 bitnum + bit_offset, word_mode,
533 operand_subword_force (value, wordnum, fieldmode),
539 /* From here on we can assume that the field to be stored in is
540 a full-word (whatever type that is), since it is shorter than a word. */
542 /* OFFSET is the number of words or bytes (UNIT says which)
543 from STR_RTX to the first word or byte containing part of the field. */
545 if (GET_CODE (op0) != MEM)
548 || GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD)
550 if (GET_CODE (op0) != REG)
552 /* Since this is a destination (lvalue), we can't copy it to a
553 pseudo. We can trivially remove a SUBREG that does not
554 change the size of the operand. Such a SUBREG may have been
555 added above. Otherwise, abort. */
556 if (GET_CODE (op0) == SUBREG
557 && (GET_MODE_SIZE (GET_MODE (op0))
558 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0)))))
559 op0 = SUBREG_REG (op0);
563 op0 = gen_rtx_SUBREG (mode_for_size (BITS_PER_WORD, MODE_INT, 0),
564 op0, (offset * UNITS_PER_WORD));
569 op0 = protect_from_queue (op0, 1);
571 /* If VALUE is a floating-point mode, access it as an integer of the
572 corresponding size. This can occur on a machine with 64 bit registers
573 that uses SFmode for float. This can also occur for unaligned float
575 if (GET_MODE_CLASS (GET_MODE (value)) != MODE_INT
576 && GET_MODE_CLASS (GET_MODE (value)) != MODE_PARTIAL_INT)
577 value = gen_lowpart ((GET_MODE (value) == VOIDmode
578 ? word_mode : int_mode_for_mode (GET_MODE (value))),
581 /* Now OFFSET is nonzero only if OP0 is memory
582 and is therefore always measured in bytes. */
585 && GET_MODE (value) != BLKmode
586 && !(bitsize == 1 && GET_CODE (value) == CONST_INT)
587 /* Ensure insv's size is wide enough for this field. */
588 && (GET_MODE_BITSIZE (op_mode) >= bitsize)
589 && ! ((GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
590 && (bitsize + bitpos > GET_MODE_BITSIZE (op_mode))))
592 int xbitpos = bitpos;
595 rtx last = get_last_insn ();
597 enum machine_mode maxmode = mode_for_extraction (EP_insv, 3);
598 int save_volatile_ok = volatile_ok;
602 /* If this machine's insv can only insert into a register, copy OP0
603 into a register and save it back later. */
604 /* This used to check flag_force_mem, but that was a serious
605 de-optimization now that flag_force_mem is enabled by -O2. */
606 if (GET_CODE (op0) == MEM
607 && ! ((*insn_data[(int) CODE_FOR_insv].operand[0].predicate)
611 enum machine_mode bestmode;
613 /* Get the mode to use for inserting into this field. If OP0 is
614 BLKmode, get the smallest mode consistent with the alignment. If
615 OP0 is a non-BLKmode object that is no wider than MAXMODE, use its
616 mode. Otherwise, use the smallest mode containing the field. */
618 if (GET_MODE (op0) == BLKmode
619 || GET_MODE_SIZE (GET_MODE (op0)) > GET_MODE_SIZE (maxmode))
621 = get_best_mode (bitsize, bitnum, MEM_ALIGN (op0), maxmode,
622 MEM_VOLATILE_P (op0));
624 bestmode = GET_MODE (op0);
626 if (bestmode == VOIDmode
627 || (SLOW_UNALIGNED_ACCESS (bestmode, MEM_ALIGN (op0))
628 && GET_MODE_BITSIZE (bestmode) > MEM_ALIGN (op0)))
631 /* Adjust address to point to the containing unit of that mode.
632 Compute offset as multiple of this unit, counting in bytes. */
633 unit = GET_MODE_BITSIZE (bestmode);
634 offset = (bitnum / unit) * GET_MODE_SIZE (bestmode);
635 bitpos = bitnum % unit;
636 op0 = adjust_address (op0, bestmode, offset);
638 /* Fetch that unit, store the bitfield in it, then store
640 tempreg = copy_to_reg (op0);
641 store_bit_field (tempreg, bitsize, bitpos, fieldmode, value,
643 emit_move_insn (op0, tempreg);
646 volatile_ok = save_volatile_ok;
648 /* Add OFFSET into OP0's address. */
649 if (GET_CODE (xop0) == MEM)
650 xop0 = adjust_address (xop0, byte_mode, offset);
652 /* If xop0 is a register, we need it in MAXMODE
653 to make it acceptable to the format of insv. */
654 if (GET_CODE (xop0) == SUBREG)
655 /* We can't just change the mode, because this might clobber op0,
656 and we will need the original value of op0 if insv fails. */
657 xop0 = gen_rtx_SUBREG (maxmode, SUBREG_REG (xop0), SUBREG_BYTE (xop0));
658 if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode)
659 xop0 = gen_rtx_SUBREG (maxmode, xop0, 0);
661 /* On big-endian machines, we count bits from the most significant.
662 If the bit field insn does not, we must invert. */
664 if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
665 xbitpos = unit - bitsize - xbitpos;
667 /* We have been counting XBITPOS within UNIT.
668 Count instead within the size of the register. */
669 if (BITS_BIG_ENDIAN && GET_CODE (xop0) != MEM)
670 xbitpos += GET_MODE_BITSIZE (maxmode) - unit;
672 unit = GET_MODE_BITSIZE (maxmode);
674 /* Convert VALUE to maxmode (which insv insn wants) in VALUE1. */
676 if (GET_MODE (value) != maxmode)
678 if (GET_MODE_BITSIZE (GET_MODE (value)) >= bitsize)
680 /* Optimization: Don't bother really extending VALUE
681 if it has all the bits we will actually use. However,
682 if we must narrow it, be sure we do it correctly. */
684 if (GET_MODE_SIZE (GET_MODE (value)) < GET_MODE_SIZE (maxmode))
688 tmp = simplify_subreg (maxmode, value1, GET_MODE (value), 0);
690 tmp = simplify_gen_subreg (maxmode,
691 force_reg (GET_MODE (value),
693 GET_MODE (value), 0);
697 value1 = gen_lowpart (maxmode, value1);
699 else if (GET_CODE (value) == CONST_INT)
700 value1 = gen_int_mode (INTVAL (value), maxmode);
701 else if (!CONSTANT_P (value))
702 /* Parse phase is supposed to make VALUE's data type
703 match that of the component reference, which is a type
704 at least as wide as the field; so VALUE should have
705 a mode that corresponds to that type. */
709 /* If this machine's insv insists on a register,
710 get VALUE1 into a register. */
711 if (! ((*insn_data[(int) CODE_FOR_insv].operand[3].predicate)
713 value1 = force_reg (maxmode, value1);
715 pat = gen_insv (xop0, GEN_INT (bitsize), GEN_INT (xbitpos), value1);
720 delete_insns_since (last);
721 store_fixed_bit_field (op0, offset, bitsize, bitpos, value);
726 /* Insv is not available; store using shifts and boolean ops. */
727 store_fixed_bit_field (op0, offset, bitsize, bitpos, value);
731 /* Use shifts and boolean operations to store VALUE
732 into a bit field of width BITSIZE
733 in a memory location specified by OP0 except offset by OFFSET bytes.
734 (OFFSET must be 0 if OP0 is a register.)
735 The field starts at position BITPOS within the byte.
736 (If OP0 is a register, it may be a full word or a narrower mode,
737 but BITPOS still counts within a full word,
738 which is significant on bigendian machines.)
740 Note that protect_from_queue has already been done on OP0 and VALUE. */
743 store_fixed_bit_field (rtx op0, unsigned HOST_WIDE_INT offset,
744 unsigned HOST_WIDE_INT bitsize,
745 unsigned HOST_WIDE_INT bitpos, rtx value)
747 enum machine_mode mode;
748 unsigned int total_bits = BITS_PER_WORD;
753 /* There is a case not handled here:
754 a structure with a known alignment of just a halfword
755 and a field split across two aligned halfwords within the structure.
756 Or likewise a structure with a known alignment of just a byte
757 and a field split across two bytes.
758 Such cases are not supposed to be able to occur. */
760 if (GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
764 /* Special treatment for a bit field split across two registers. */
765 if (bitsize + bitpos > BITS_PER_WORD)
767 store_split_bit_field (op0, bitsize, bitpos, value);
773 /* Get the proper mode to use for this field. We want a mode that
774 includes the entire field. If such a mode would be larger than
775 a word, we won't be doing the extraction the normal way.
776 We don't want a mode bigger than the destination. */
778 mode = GET_MODE (op0);
779 if (GET_MODE_BITSIZE (mode) == 0
780 || GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (word_mode))
782 mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT,
783 MEM_ALIGN (op0), mode, MEM_VOLATILE_P (op0));
785 if (mode == VOIDmode)
787 /* The only way this should occur is if the field spans word
789 store_split_bit_field (op0, bitsize, bitpos + offset * BITS_PER_UNIT,
794 total_bits = GET_MODE_BITSIZE (mode);
796 /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to
797 be in the range 0 to total_bits-1, and put any excess bytes in
799 if (bitpos >= total_bits)
801 offset += (bitpos / total_bits) * (total_bits / BITS_PER_UNIT);
802 bitpos -= ((bitpos / total_bits) * (total_bits / BITS_PER_UNIT)
806 /* Get ref to an aligned byte, halfword, or word containing the field.
807 Adjust BITPOS to be position within a word,
808 and OFFSET to be the offset of that word.
809 Then alter OP0 to refer to that word. */
810 bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT;
811 offset -= (offset % (total_bits / BITS_PER_UNIT));
812 op0 = adjust_address (op0, mode, offset);
815 mode = GET_MODE (op0);
817 /* Now MODE is either some integral mode for a MEM as OP0,
818 or is a full-word for a REG as OP0. TOTAL_BITS corresponds.
819 The bit field is contained entirely within OP0.
820 BITPOS is the starting bit number within OP0.
821 (OP0's mode may actually be narrower than MODE.) */
823 if (BYTES_BIG_ENDIAN)
824 /* BITPOS is the distance between our msb
825 and that of the containing datum.
826 Convert it to the distance from the lsb. */
827 bitpos = total_bits - bitsize - bitpos;
829 /* Now BITPOS is always the distance between our lsb
832 /* Shift VALUE left by BITPOS bits. If VALUE is not constant,
833 we must first convert its mode to MODE. */
835 if (GET_CODE (value) == CONST_INT)
837 HOST_WIDE_INT v = INTVAL (value);
839 if (bitsize < HOST_BITS_PER_WIDE_INT)
840 v &= ((HOST_WIDE_INT) 1 << bitsize) - 1;
844 else if ((bitsize < HOST_BITS_PER_WIDE_INT
845 && v == ((HOST_WIDE_INT) 1 << bitsize) - 1)
846 || (bitsize == HOST_BITS_PER_WIDE_INT && v == -1))
849 value = lshift_value (mode, value, bitpos, bitsize);
853 int must_and = (GET_MODE_BITSIZE (GET_MODE (value)) != bitsize
854 && bitpos + bitsize != GET_MODE_BITSIZE (mode));
856 if (GET_MODE (value) != mode)
858 if ((GET_CODE (value) == REG || GET_CODE (value) == SUBREG)
859 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (value)))
860 value = gen_lowpart (mode, value);
862 value = convert_to_mode (mode, value, 1);
866 value = expand_binop (mode, and_optab, value,
867 mask_rtx (mode, 0, bitsize, 0),
868 NULL_RTX, 1, OPTAB_LIB_WIDEN);
870 value = expand_shift (LSHIFT_EXPR, mode, value,
871 build_int_2 (bitpos, 0), NULL_RTX, 1);
874 /* Now clear the chosen bits in OP0,
875 except that if VALUE is -1 we need not bother. */
877 subtarget = (GET_CODE (op0) == REG || ! flag_force_mem) ? op0 : 0;
881 temp = expand_binop (mode, and_optab, op0,
882 mask_rtx (mode, bitpos, bitsize, 1),
883 subtarget, 1, OPTAB_LIB_WIDEN);
889 /* Now logical-or VALUE into OP0, unless it is zero. */
892 temp = expand_binop (mode, ior_optab, temp, value,
893 subtarget, 1, OPTAB_LIB_WIDEN);
895 emit_move_insn (op0, temp);
898 /* Store a bit field that is split across multiple accessible memory objects.
900 OP0 is the REG, SUBREG or MEM rtx for the first of the objects.
901 BITSIZE is the field width; BITPOS the position of its first bit
903 VALUE is the value to store.
905 This does not yet handle fields wider than BITS_PER_WORD. */
908 store_split_bit_field (rtx op0, unsigned HOST_WIDE_INT bitsize,
909 unsigned HOST_WIDE_INT bitpos, rtx value)
912 unsigned int bitsdone = 0;
914 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
916 if (GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
917 unit = BITS_PER_WORD;
919 unit = MIN (MEM_ALIGN (op0), BITS_PER_WORD);
921 /* If VALUE is a constant other than a CONST_INT, get it into a register in
922 WORD_MODE. If we can do this using gen_lowpart_common, do so. Note
923 that VALUE might be a floating-point constant. */
924 if (CONSTANT_P (value) && GET_CODE (value) != CONST_INT)
926 rtx word = gen_lowpart_common (word_mode, value);
928 if (word && (value != word))
931 value = gen_lowpart_common (word_mode,
932 force_reg (GET_MODE (value) != VOIDmode
934 : word_mode, value));
936 else if (GET_CODE (value) == ADDRESSOF)
937 value = copy_to_reg (value);
939 while (bitsdone < bitsize)
941 unsigned HOST_WIDE_INT thissize;
943 unsigned HOST_WIDE_INT thispos;
944 unsigned HOST_WIDE_INT offset;
946 offset = (bitpos + bitsdone) / unit;
947 thispos = (bitpos + bitsdone) % unit;
949 /* THISSIZE must not overrun a word boundary. Otherwise,
950 store_fixed_bit_field will call us again, and we will mutually
952 thissize = MIN (bitsize - bitsdone, BITS_PER_WORD);
953 thissize = MIN (thissize, unit - thispos);
955 if (BYTES_BIG_ENDIAN)
959 /* We must do an endian conversion exactly the same way as it is
960 done in extract_bit_field, so that the two calls to
961 extract_fixed_bit_field will have comparable arguments. */
962 if (GET_CODE (value) != MEM || GET_MODE (value) == BLKmode)
963 total_bits = BITS_PER_WORD;
965 total_bits = GET_MODE_BITSIZE (GET_MODE (value));
967 /* Fetch successively less significant portions. */
968 if (GET_CODE (value) == CONST_INT)
969 part = GEN_INT (((unsigned HOST_WIDE_INT) (INTVAL (value))
970 >> (bitsize - bitsdone - thissize))
971 & (((HOST_WIDE_INT) 1 << thissize) - 1));
973 /* The args are chosen so that the last part includes the
974 lsb. Give extract_bit_field the value it needs (with
975 endianness compensation) to fetch the piece we want. */
976 part = extract_fixed_bit_field (word_mode, value, 0, thissize,
977 total_bits - bitsize + bitsdone,
982 /* Fetch successively more significant portions. */
983 if (GET_CODE (value) == CONST_INT)
984 part = GEN_INT (((unsigned HOST_WIDE_INT) (INTVAL (value))
986 & (((HOST_WIDE_INT) 1 << thissize) - 1));
988 part = extract_fixed_bit_field (word_mode, value, 0, thissize,
989 bitsdone, NULL_RTX, 1);
992 /* If OP0 is a register, then handle OFFSET here.
994 When handling multiword bitfields, extract_bit_field may pass
995 down a word_mode SUBREG of a larger REG for a bitfield that actually
996 crosses a word boundary. Thus, for a SUBREG, we must find
997 the current word starting from the base register. */
998 if (GET_CODE (op0) == SUBREG)
1000 int word_offset = (SUBREG_BYTE (op0) / UNITS_PER_WORD) + offset;
1001 word = operand_subword_force (SUBREG_REG (op0), word_offset,
1002 GET_MODE (SUBREG_REG (op0)));
1005 else if (GET_CODE (op0) == REG)
1007 word = operand_subword_force (op0, offset, GET_MODE (op0));
1013 /* OFFSET is in UNITs, and UNIT is in bits.
1014 store_fixed_bit_field wants offset in bytes. */
1015 store_fixed_bit_field (word, offset * unit / BITS_PER_UNIT, thissize,
1017 bitsdone += thissize;
1021 /* Generate code to extract a byte-field from STR_RTX
1022 containing BITSIZE bits, starting at BITNUM,
1023 and put it in TARGET if possible (if TARGET is nonzero).
1024 Regardless of TARGET, we return the rtx for where the value is placed.
1027 STR_RTX is the structure containing the byte (a REG or MEM).
1028 UNSIGNEDP is nonzero if this is an unsigned bit field.
1029 MODE is the natural mode of the field value once extracted.
1030 TMODE is the mode the caller would like the value to have;
1031 but the value may be returned with type MODE instead.
1033 TOTAL_SIZE is the size in bytes of the containing structure,
1036 If a TARGET is specified and we can store in it at no extra cost,
1037 we do so, and return TARGET.
1038 Otherwise, we return a REG of mode TMODE or MODE, with TMODE preferred
1039 if they are equally easy. */
1042 extract_bit_field (rtx str_rtx, unsigned HOST_WIDE_INT bitsize,
1043 unsigned HOST_WIDE_INT bitnum, int unsignedp, rtx target,
1044 enum machine_mode mode, enum machine_mode tmode,
1045 HOST_WIDE_INT total_size)
1048 = (GET_CODE (str_rtx) == MEM) ? BITS_PER_UNIT : BITS_PER_WORD;
1049 unsigned HOST_WIDE_INT offset = bitnum / unit;
1050 unsigned HOST_WIDE_INT bitpos = bitnum % unit;
1052 rtx spec_target = target;
1053 rtx spec_target_subreg = 0;
1054 enum machine_mode int_mode;
1055 enum machine_mode extv_mode = mode_for_extraction (EP_extv, 0);
1056 enum machine_mode extzv_mode = mode_for_extraction (EP_extzv, 0);
1057 enum machine_mode mode1;
1060 /* Discount the part of the structure before the desired byte.
1061 We need to know how many bytes are safe to reference after it. */
1062 if (total_size >= 0)
1063 total_size -= (bitpos / BIGGEST_ALIGNMENT
1064 * (BIGGEST_ALIGNMENT / BITS_PER_UNIT));
1066 if (tmode == VOIDmode)
1069 while (GET_CODE (op0) == SUBREG)
1071 bitpos += SUBREG_BYTE (op0) * BITS_PER_UNIT;
1074 offset += (bitpos / unit);
1077 op0 = SUBREG_REG (op0);
1080 if (GET_CODE (op0) == REG
1081 && mode == GET_MODE (op0)
1083 && bitsize == GET_MODE_BITSIZE (GET_MODE (op0)))
1085 /* We're trying to extract a full register from itself. */
1089 /* Use vec_extract patterns for extracting parts of vectors whenever
1091 if (VECTOR_MODE_P (GET_MODE (op0))
1092 && GET_CODE (op0) != MEM
1093 && (vec_extract_optab->handlers[GET_MODE (op0)].insn_code
1094 != CODE_FOR_nothing)
1095 && ((bitsize + bitnum) / GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0)))
1096 == bitsize / GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0)))))
1098 enum machine_mode outermode = GET_MODE (op0);
1099 enum machine_mode innermode = GET_MODE_INNER (outermode);
1100 int icode = (int) vec_extract_optab->handlers[outermode].insn_code;
1101 int pos = bitnum / GET_MODE_BITSIZE (innermode);
1102 rtx rtxpos = GEN_INT (pos);
1104 rtx dest = NULL, pat, seq;
1105 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
1106 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
1107 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
1109 if (innermode == tmode || innermode == mode)
1113 dest = gen_reg_rtx (innermode);
1117 if (! (*insn_data[icode].operand[0].predicate) (dest, mode0))
1118 dest = copy_to_mode_reg (mode0, dest);
1120 if (! (*insn_data[icode].operand[1].predicate) (src, mode1))
1121 src = copy_to_mode_reg (mode1, src);
1123 if (! (*insn_data[icode].operand[2].predicate) (rtxpos, mode2))
1124 rtxpos = copy_to_mode_reg (mode1, rtxpos);
1126 /* We could handle this, but we should always be called with a pseudo
1127 for our targets and all insns should take them as outputs. */
1128 if (! (*insn_data[icode].operand[0].predicate) (dest, mode0)
1129 || ! (*insn_data[icode].operand[1].predicate) (src, mode1)
1130 || ! (*insn_data[icode].operand[2].predicate) (rtxpos, mode2))
1133 pat = GEN_FCN (icode) (dest, src, rtxpos);
1144 /* Make sure we are playing with integral modes. Pun with subregs
1147 enum machine_mode imode = int_mode_for_mode (GET_MODE (op0));
1148 if (imode != GET_MODE (op0))
1150 if (GET_CODE (op0) == MEM)
1151 op0 = adjust_address (op0, imode, 0);
1152 else if (imode != BLKmode)
1153 op0 = gen_lowpart (imode, op0);
1159 /* We may be accessing data outside the field, which means
1160 we can alias adjacent data. */
1161 if (GET_CODE (op0) == MEM)
1163 op0 = shallow_copy_rtx (op0);
1164 set_mem_alias_set (op0, 0);
1165 set_mem_expr (op0, 0);
1168 /* Extraction of a full-word or multi-word value from a structure
1169 in a register or aligned memory can be done with just a SUBREG.
1170 A subword value in the least significant part of a register
1171 can also be extracted with a SUBREG. For this, we need the
1172 byte offset of the value in op0. */
1174 byte_offset = bitpos / BITS_PER_UNIT + offset * UNITS_PER_WORD;
1176 /* If OP0 is a register, BITPOS must count within a word.
1177 But as we have it, it counts within whatever size OP0 now has.
1178 On a bigendian machine, these are not the same, so convert. */
1179 if (BYTES_BIG_ENDIAN
1180 && GET_CODE (op0) != MEM
1181 && unit > GET_MODE_BITSIZE (GET_MODE (op0)))
1182 bitpos += unit - GET_MODE_BITSIZE (GET_MODE (op0));
1184 /* ??? We currently assume TARGET is at least as big as BITSIZE.
1185 If that's wrong, the solution is to test for it and set TARGET to 0
1188 /* Only scalar integer modes can be converted via subregs. There is an
1189 additional problem for FP modes here in that they can have a precision
1190 which is different from the size. mode_for_size uses precision, but
1191 we want a mode based on the size, so we must avoid calling it for FP
1193 mode1 = (SCALAR_INT_MODE_P (tmode)
1194 ? mode_for_size (bitsize, GET_MODE_CLASS (tmode), 0)
1197 if (((bitsize >= BITS_PER_WORD && bitsize == GET_MODE_BITSIZE (mode)
1198 && bitpos % BITS_PER_WORD == 0)
1199 || (mode1 != BLKmode
1200 /* ??? The big endian test here is wrong. This is correct
1201 if the value is in a register, and if mode_for_size is not
1202 the same mode as op0. This causes us to get unnecessarily
1203 inefficient code from the Thumb port when -mbig-endian. */
1204 && (BYTES_BIG_ENDIAN
1205 ? bitpos + bitsize == BITS_PER_WORD
1207 && ((GET_CODE (op0) != MEM
1208 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
1209 GET_MODE_BITSIZE (GET_MODE (op0)))
1210 && GET_MODE_SIZE (mode1) != 0
1211 && byte_offset % GET_MODE_SIZE (mode1) == 0)
1212 || (GET_CODE (op0) == MEM
1213 && (! SLOW_UNALIGNED_ACCESS (mode, MEM_ALIGN (op0))
1214 || (offset * BITS_PER_UNIT % bitsize == 0
1215 && MEM_ALIGN (op0) % bitsize == 0)))))
1217 if (mode1 != GET_MODE (op0))
1219 if (GET_CODE (op0) == SUBREG)
1221 if (GET_MODE (SUBREG_REG (op0)) == mode1
1222 || GET_MODE_CLASS (mode1) == MODE_INT
1223 || GET_MODE_CLASS (mode1) == MODE_PARTIAL_INT)
1224 op0 = SUBREG_REG (op0);
1226 /* Else we've got some float mode source being extracted into
1227 a different float mode destination -- this combination of
1228 subregs results in Severe Tire Damage. */
1229 goto no_subreg_mode_swap;
1231 if (GET_CODE (op0) == REG)
1232 op0 = gen_rtx_SUBREG (mode1, op0, byte_offset);
1234 op0 = adjust_address (op0, mode1, offset);
1237 return convert_to_mode (tmode, op0, unsignedp);
1240 no_subreg_mode_swap:
1242 /* Handle fields bigger than a word. */
1244 if (bitsize > BITS_PER_WORD)
1246 /* Here we transfer the words of the field
1247 in the order least significant first.
1248 This is because the most significant word is the one which may
1249 be less than full. */
1251 unsigned int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD;
1254 if (target == 0 || GET_CODE (target) != REG)
1255 target = gen_reg_rtx (mode);
1257 /* Indicate for flow that the entire target reg is being set. */
1258 emit_insn (gen_rtx_CLOBBER (VOIDmode, target));
1260 for (i = 0; i < nwords; i++)
1262 /* If I is 0, use the low-order word in both field and target;
1263 if I is 1, use the next to lowest word; and so on. */
1264 /* Word number in TARGET to use. */
1265 unsigned int wordnum
1267 ? GET_MODE_SIZE (GET_MODE (target)) / UNITS_PER_WORD - i - 1
1269 /* Offset from start of field in OP0. */
1270 unsigned int bit_offset = (WORDS_BIG_ENDIAN
1271 ? MAX (0, ((int) bitsize - ((int) i + 1)
1272 * (int) BITS_PER_WORD))
1273 : (int) i * BITS_PER_WORD);
1274 rtx target_part = operand_subword (target, wordnum, 1, VOIDmode);
1276 = extract_bit_field (op0, MIN (BITS_PER_WORD,
1277 bitsize - i * BITS_PER_WORD),
1278 bitnum + bit_offset, 1, target_part, mode,
1279 word_mode, total_size);
1281 if (target_part == 0)
1284 if (result_part != target_part)
1285 emit_move_insn (target_part, result_part);
1290 /* Unless we've filled TARGET, the upper regs in a multi-reg value
1291 need to be zero'd out. */
1292 if (GET_MODE_SIZE (GET_MODE (target)) > nwords * UNITS_PER_WORD)
1294 unsigned int i, total_words;
1296 total_words = GET_MODE_SIZE (GET_MODE (target)) / UNITS_PER_WORD;
1297 for (i = nwords; i < total_words; i++)
1299 (operand_subword (target,
1300 WORDS_BIG_ENDIAN ? total_words - i - 1 : i,
1307 /* Signed bit field: sign-extend with two arithmetic shifts. */
1308 target = expand_shift (LSHIFT_EXPR, mode, target,
1309 build_int_2 (GET_MODE_BITSIZE (mode) - bitsize, 0),
1311 return expand_shift (RSHIFT_EXPR, mode, target,
1312 build_int_2 (GET_MODE_BITSIZE (mode) - bitsize, 0),
1316 /* From here on we know the desired field is smaller than a word. */
1318 /* Check if there is a correspondingly-sized integer field, so we can
1319 safely extract it as one size of integer, if necessary; then
1320 truncate or extend to the size that is wanted; then use SUBREGs or
1321 convert_to_mode to get one of the modes we really wanted. */
1323 int_mode = int_mode_for_mode (tmode);
1324 if (int_mode == BLKmode)
1325 int_mode = int_mode_for_mode (mode);
1326 if (int_mode == BLKmode)
1327 abort (); /* Should probably push op0 out to memory and then
1330 /* OFFSET is the number of words or bytes (UNIT says which)
1331 from STR_RTX to the first word or byte containing part of the field. */
1333 if (GET_CODE (op0) != MEM)
1336 || GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD)
1338 if (GET_CODE (op0) != REG)
1339 op0 = copy_to_reg (op0);
1340 op0 = gen_rtx_SUBREG (mode_for_size (BITS_PER_WORD, MODE_INT, 0),
1341 op0, (offset * UNITS_PER_WORD));
1346 op0 = protect_from_queue (str_rtx, 1);
1348 /* Now OFFSET is nonzero only for memory operands. */
1353 && (GET_MODE_BITSIZE (extzv_mode) >= bitsize)
1354 && ! ((GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
1355 && (bitsize + bitpos > GET_MODE_BITSIZE (extzv_mode))))
1357 unsigned HOST_WIDE_INT xbitpos = bitpos, xoffset = offset;
1358 rtx bitsize_rtx, bitpos_rtx;
1359 rtx last = get_last_insn ();
1361 rtx xtarget = target;
1362 rtx xspec_target = spec_target;
1363 rtx xspec_target_subreg = spec_target_subreg;
1365 enum machine_mode maxmode = mode_for_extraction (EP_extzv, 0);
1367 if (GET_CODE (xop0) == MEM)
1369 int save_volatile_ok = volatile_ok;
1372 /* Is the memory operand acceptable? */
1373 if (! ((*insn_data[(int) CODE_FOR_extzv].operand[1].predicate)
1374 (xop0, GET_MODE (xop0))))
1376 /* No, load into a reg and extract from there. */
1377 enum machine_mode bestmode;
1379 /* Get the mode to use for inserting into this field. If
1380 OP0 is BLKmode, get the smallest mode consistent with the
1381 alignment. If OP0 is a non-BLKmode object that is no
1382 wider than MAXMODE, use its mode. Otherwise, use the
1383 smallest mode containing the field. */
1385 if (GET_MODE (xop0) == BLKmode
1386 || (GET_MODE_SIZE (GET_MODE (op0))
1387 > GET_MODE_SIZE (maxmode)))
1388 bestmode = get_best_mode (bitsize, bitnum,
1389 MEM_ALIGN (xop0), maxmode,
1390 MEM_VOLATILE_P (xop0));
1392 bestmode = GET_MODE (xop0);
1394 if (bestmode == VOIDmode
1395 || (SLOW_UNALIGNED_ACCESS (bestmode, MEM_ALIGN (xop0))
1396 && GET_MODE_BITSIZE (bestmode) > MEM_ALIGN (xop0)))
1399 /* Compute offset as multiple of this unit,
1400 counting in bytes. */
1401 unit = GET_MODE_BITSIZE (bestmode);
1402 xoffset = (bitnum / unit) * GET_MODE_SIZE (bestmode);
1403 xbitpos = bitnum % unit;
1404 xop0 = adjust_address (xop0, bestmode, xoffset);
1406 /* Fetch it to a register in that size. */
1407 xop0 = force_reg (bestmode, xop0);
1409 /* XBITPOS counts within UNIT, which is what is expected. */
1412 /* Get ref to first byte containing part of the field. */
1413 xop0 = adjust_address (xop0, byte_mode, xoffset);
1415 volatile_ok = save_volatile_ok;
1418 /* If op0 is a register, we need it in MAXMODE (which is usually
1419 SImode). to make it acceptable to the format of extzv. */
1420 if (GET_CODE (xop0) == SUBREG && GET_MODE (xop0) != maxmode)
1422 if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode)
1423 xop0 = gen_rtx_SUBREG (maxmode, xop0, 0);
1425 /* On big-endian machines, we count bits from the most significant.
1426 If the bit field insn does not, we must invert. */
1427 if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
1428 xbitpos = unit - bitsize - xbitpos;
1430 /* Now convert from counting within UNIT to counting in MAXMODE. */
1431 if (BITS_BIG_ENDIAN && GET_CODE (xop0) != MEM)
1432 xbitpos += GET_MODE_BITSIZE (maxmode) - unit;
1434 unit = GET_MODE_BITSIZE (maxmode);
1437 || (flag_force_mem && GET_CODE (xtarget) == MEM))
1438 xtarget = xspec_target = gen_reg_rtx (tmode);
1440 if (GET_MODE (xtarget) != maxmode)
1442 if (GET_CODE (xtarget) == REG)
1444 int wider = (GET_MODE_SIZE (maxmode)
1445 > GET_MODE_SIZE (GET_MODE (xtarget)));
1446 xtarget = gen_lowpart (maxmode, xtarget);
1448 xspec_target_subreg = xtarget;
1451 xtarget = gen_reg_rtx (maxmode);
1454 /* If this machine's extzv insists on a register target,
1455 make sure we have one. */
1456 if (! ((*insn_data[(int) CODE_FOR_extzv].operand[0].predicate)
1457 (xtarget, maxmode)))
1458 xtarget = gen_reg_rtx (maxmode);
1460 bitsize_rtx = GEN_INT (bitsize);
1461 bitpos_rtx = GEN_INT (xbitpos);
1463 pat = gen_extzv (protect_from_queue (xtarget, 1),
1464 xop0, bitsize_rtx, bitpos_rtx);
1469 spec_target = xspec_target;
1470 spec_target_subreg = xspec_target_subreg;
1474 delete_insns_since (last);
1475 target = extract_fixed_bit_field (int_mode, op0, offset, bitsize,
1481 target = extract_fixed_bit_field (int_mode, op0, offset, bitsize,
1487 && (GET_MODE_BITSIZE (extv_mode) >= bitsize)
1488 && ! ((GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
1489 && (bitsize + bitpos > GET_MODE_BITSIZE (extv_mode))))
1491 int xbitpos = bitpos, xoffset = offset;
1492 rtx bitsize_rtx, bitpos_rtx;
1493 rtx last = get_last_insn ();
1494 rtx xop0 = op0, xtarget = target;
1495 rtx xspec_target = spec_target;
1496 rtx xspec_target_subreg = spec_target_subreg;
1498 enum machine_mode maxmode = mode_for_extraction (EP_extv, 0);
1500 if (GET_CODE (xop0) == MEM)
1502 /* Is the memory operand acceptable? */
1503 if (! ((*insn_data[(int) CODE_FOR_extv].operand[1].predicate)
1504 (xop0, GET_MODE (xop0))))
1506 /* No, load into a reg and extract from there. */
1507 enum machine_mode bestmode;
1509 /* Get the mode to use for inserting into this field. If
1510 OP0 is BLKmode, get the smallest mode consistent with the
1511 alignment. If OP0 is a non-BLKmode object that is no
1512 wider than MAXMODE, use its mode. Otherwise, use the
1513 smallest mode containing the field. */
1515 if (GET_MODE (xop0) == BLKmode
1516 || (GET_MODE_SIZE (GET_MODE (op0))
1517 > GET_MODE_SIZE (maxmode)))
1518 bestmode = get_best_mode (bitsize, bitnum,
1519 MEM_ALIGN (xop0), maxmode,
1520 MEM_VOLATILE_P (xop0));
1522 bestmode = GET_MODE (xop0);
1524 if (bestmode == VOIDmode
1525 || (SLOW_UNALIGNED_ACCESS (bestmode, MEM_ALIGN (xop0))
1526 && GET_MODE_BITSIZE (bestmode) > MEM_ALIGN (xop0)))
1529 /* Compute offset as multiple of this unit,
1530 counting in bytes. */
1531 unit = GET_MODE_BITSIZE (bestmode);
1532 xoffset = (bitnum / unit) * GET_MODE_SIZE (bestmode);
1533 xbitpos = bitnum % unit;
1534 xop0 = adjust_address (xop0, bestmode, xoffset);
1536 /* Fetch it to a register in that size. */
1537 xop0 = force_reg (bestmode, xop0);
1539 /* XBITPOS counts within UNIT, which is what is expected. */
1542 /* Get ref to first byte containing part of the field. */
1543 xop0 = adjust_address (xop0, byte_mode, xoffset);
1546 /* If op0 is a register, we need it in MAXMODE (which is usually
1547 SImode) to make it acceptable to the format of extv. */
1548 if (GET_CODE (xop0) == SUBREG && GET_MODE (xop0) != maxmode)
1550 if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode)
1551 xop0 = gen_rtx_SUBREG (maxmode, xop0, 0);
1553 /* On big-endian machines, we count bits from the most significant.
1554 If the bit field insn does not, we must invert. */
1555 if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
1556 xbitpos = unit - bitsize - xbitpos;
1558 /* XBITPOS counts within a size of UNIT.
1559 Adjust to count within a size of MAXMODE. */
1560 if (BITS_BIG_ENDIAN && GET_CODE (xop0) != MEM)
1561 xbitpos += (GET_MODE_BITSIZE (maxmode) - unit);
1563 unit = GET_MODE_BITSIZE (maxmode);
1566 || (flag_force_mem && GET_CODE (xtarget) == MEM))
1567 xtarget = xspec_target = gen_reg_rtx (tmode);
1569 if (GET_MODE (xtarget) != maxmode)
1571 if (GET_CODE (xtarget) == REG)
1573 int wider = (GET_MODE_SIZE (maxmode)
1574 > GET_MODE_SIZE (GET_MODE (xtarget)));
1575 xtarget = gen_lowpart (maxmode, xtarget);
1577 xspec_target_subreg = xtarget;
1580 xtarget = gen_reg_rtx (maxmode);
1583 /* If this machine's extv insists on a register target,
1584 make sure we have one. */
1585 if (! ((*insn_data[(int) CODE_FOR_extv].operand[0].predicate)
1586 (xtarget, maxmode)))
1587 xtarget = gen_reg_rtx (maxmode);
1589 bitsize_rtx = GEN_INT (bitsize);
1590 bitpos_rtx = GEN_INT (xbitpos);
1592 pat = gen_extv (protect_from_queue (xtarget, 1),
1593 xop0, bitsize_rtx, bitpos_rtx);
1598 spec_target = xspec_target;
1599 spec_target_subreg = xspec_target_subreg;
1603 delete_insns_since (last);
1604 target = extract_fixed_bit_field (int_mode, op0, offset, bitsize,
1610 target = extract_fixed_bit_field (int_mode, op0, offset, bitsize,
1613 if (target == spec_target)
1615 if (target == spec_target_subreg)
1617 if (GET_MODE (target) != tmode && GET_MODE (target) != mode)
1619 /* If the target mode is floating-point, first convert to the
1620 integer mode of that size and then access it as a floating-point
1621 value via a SUBREG. */
1622 if (GET_MODE_CLASS (tmode) != MODE_INT
1623 && GET_MODE_CLASS (tmode) != MODE_PARTIAL_INT)
1625 target = convert_to_mode (mode_for_size (GET_MODE_BITSIZE (tmode),
1628 return gen_lowpart (tmode, target);
1631 return convert_to_mode (tmode, target, unsignedp);
1636 /* Extract a bit field using shifts and boolean operations
1637 Returns an rtx to represent the value.
1638 OP0 addresses a register (word) or memory (byte).
1639 BITPOS says which bit within the word or byte the bit field starts in.
1640 OFFSET says how many bytes farther the bit field starts;
1641 it is 0 if OP0 is a register.
1642 BITSIZE says how many bits long the bit field is.
1643 (If OP0 is a register, it may be narrower than a full word,
1644 but BITPOS still counts within a full word,
1645 which is significant on bigendian machines.)
1647 UNSIGNEDP is nonzero for an unsigned bit field (don't sign-extend value).
1648 If TARGET is nonzero, attempts to store the value there
1649 and return TARGET, but this is not guaranteed.
1650 If TARGET is not used, create a pseudo-reg of mode TMODE for the value. */
1653 extract_fixed_bit_field (enum machine_mode tmode, rtx op0,
1654 unsigned HOST_WIDE_INT offset,
1655 unsigned HOST_WIDE_INT bitsize,
1656 unsigned HOST_WIDE_INT bitpos, rtx target,
1659 unsigned int total_bits = BITS_PER_WORD;
1660 enum machine_mode mode;
1662 if (GET_CODE (op0) == SUBREG || GET_CODE (op0) == REG)
1664 /* Special treatment for a bit field split across two registers. */
1665 if (bitsize + bitpos > BITS_PER_WORD)
1666 return extract_split_bit_field (op0, bitsize, bitpos, unsignedp);
1670 /* Get the proper mode to use for this field. We want a mode that
1671 includes the entire field. If such a mode would be larger than
1672 a word, we won't be doing the extraction the normal way. */
1674 mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT,
1675 MEM_ALIGN (op0), word_mode, MEM_VOLATILE_P (op0));
1677 if (mode == VOIDmode)
1678 /* The only way this should occur is if the field spans word
1680 return extract_split_bit_field (op0, bitsize,
1681 bitpos + offset * BITS_PER_UNIT,
1684 total_bits = GET_MODE_BITSIZE (mode);
1686 /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to
1687 be in the range 0 to total_bits-1, and put any excess bytes in
1689 if (bitpos >= total_bits)
1691 offset += (bitpos / total_bits) * (total_bits / BITS_PER_UNIT);
1692 bitpos -= ((bitpos / total_bits) * (total_bits / BITS_PER_UNIT)
1696 /* Get ref to an aligned byte, halfword, or word containing the field.
1697 Adjust BITPOS to be position within a word,
1698 and OFFSET to be the offset of that word.
1699 Then alter OP0 to refer to that word. */
1700 bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT;
1701 offset -= (offset % (total_bits / BITS_PER_UNIT));
1702 op0 = adjust_address (op0, mode, offset);
1705 mode = GET_MODE (op0);
1707 if (BYTES_BIG_ENDIAN)
1708 /* BITPOS is the distance between our msb and that of OP0.
1709 Convert it to the distance from the lsb. */
1710 bitpos = total_bits - bitsize - bitpos;
1712 /* Now BITPOS is always the distance between the field's lsb and that of OP0.
1713 We have reduced the big-endian case to the little-endian case. */
1719 /* If the field does not already start at the lsb,
1720 shift it so it does. */
1721 tree amount = build_int_2 (bitpos, 0);
1722 /* Maybe propagate the target for the shift. */
1723 /* But not if we will return it--could confuse integrate.c. */
1724 rtx subtarget = (target != 0 && GET_CODE (target) == REG ? target : 0);
1725 if (tmode != mode) subtarget = 0;
1726 op0 = expand_shift (RSHIFT_EXPR, mode, op0, amount, subtarget, 1);
1728 /* Convert the value to the desired mode. */
1730 op0 = convert_to_mode (tmode, op0, 1);
1732 /* Unless the msb of the field used to be the msb when we shifted,
1733 mask out the upper bits. */
1735 if (GET_MODE_BITSIZE (mode) != bitpos + bitsize)
1736 return expand_binop (GET_MODE (op0), and_optab, op0,
1737 mask_rtx (GET_MODE (op0), 0, bitsize, 0),
1738 target, 1, OPTAB_LIB_WIDEN);
1742 /* To extract a signed bit-field, first shift its msb to the msb of the word,
1743 then arithmetic-shift its lsb to the lsb of the word. */
1744 op0 = force_reg (mode, op0);
1748 /* Find the narrowest integer mode that contains the field. */
1750 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode;
1751 mode = GET_MODE_WIDER_MODE (mode))
1752 if (GET_MODE_BITSIZE (mode) >= bitsize + bitpos)
1754 op0 = convert_to_mode (mode, op0, 0);
1758 if (GET_MODE_BITSIZE (mode) != (bitsize + bitpos))
1761 = build_int_2 (GET_MODE_BITSIZE (mode) - (bitsize + bitpos), 0);
1762 /* Maybe propagate the target for the shift. */
1763 rtx subtarget = (target != 0 && GET_CODE (target) == REG ? target : 0);
1764 op0 = expand_shift (LSHIFT_EXPR, mode, op0, amount, subtarget, 1);
1767 return expand_shift (RSHIFT_EXPR, mode, op0,
1768 build_int_2 (GET_MODE_BITSIZE (mode) - bitsize, 0),
1772 /* Return a constant integer (CONST_INT or CONST_DOUBLE) mask value
1773 of mode MODE with BITSIZE ones followed by BITPOS zeros, or the
1774 complement of that if COMPLEMENT. The mask is truncated if
1775 necessary to the width of mode MODE. The mask is zero-extended if
1776 BITSIZE+BITPOS is too small for MODE. */
1779 mask_rtx (enum machine_mode mode, int bitpos, int bitsize, int complement)
1781 HOST_WIDE_INT masklow, maskhigh;
1785 else if (bitpos < HOST_BITS_PER_WIDE_INT)
1786 masklow = (HOST_WIDE_INT) -1 << bitpos;
1790 if (bitpos + bitsize < HOST_BITS_PER_WIDE_INT)
1791 masklow &= ((unsigned HOST_WIDE_INT) -1
1792 >> (HOST_BITS_PER_WIDE_INT - bitpos - bitsize));
1794 if (bitpos <= HOST_BITS_PER_WIDE_INT)
1797 maskhigh = (HOST_WIDE_INT) -1 << (bitpos - HOST_BITS_PER_WIDE_INT);
1801 else if (bitpos + bitsize > HOST_BITS_PER_WIDE_INT)
1802 maskhigh &= ((unsigned HOST_WIDE_INT) -1
1803 >> (2 * HOST_BITS_PER_WIDE_INT - bitpos - bitsize));
1809 maskhigh = ~maskhigh;
1813 return immed_double_const (masklow, maskhigh, mode);
1816 /* Return a constant integer (CONST_INT or CONST_DOUBLE) rtx with the value
1817 VALUE truncated to BITSIZE bits and then shifted left BITPOS bits. */
1820 lshift_value (enum machine_mode mode, rtx value, int bitpos, int bitsize)
1822 unsigned HOST_WIDE_INT v = INTVAL (value);
1823 HOST_WIDE_INT low, high;
1825 if (bitsize < HOST_BITS_PER_WIDE_INT)
1826 v &= ~((HOST_WIDE_INT) -1 << bitsize);
1828 if (bitpos < HOST_BITS_PER_WIDE_INT)
1831 high = (bitpos > 0 ? (v >> (HOST_BITS_PER_WIDE_INT - bitpos)) : 0);
1836 high = v << (bitpos - HOST_BITS_PER_WIDE_INT);
1839 return immed_double_const (low, high, mode);
1842 /* Extract a bit field that is split across two words
1843 and return an RTX for the result.
1845 OP0 is the REG, SUBREG or MEM rtx for the first of the two words.
1846 BITSIZE is the field width; BITPOS, position of its first bit, in the word.
1847 UNSIGNEDP is 1 if should zero-extend the contents; else sign-extend. */
1850 extract_split_bit_field (rtx op0, unsigned HOST_WIDE_INT bitsize,
1851 unsigned HOST_WIDE_INT bitpos, int unsignedp)
1854 unsigned int bitsdone = 0;
1855 rtx result = NULL_RTX;
1858 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
1860 if (GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
1861 unit = BITS_PER_WORD;
1863 unit = MIN (MEM_ALIGN (op0), BITS_PER_WORD);
1865 while (bitsdone < bitsize)
1867 unsigned HOST_WIDE_INT thissize;
1869 unsigned HOST_WIDE_INT thispos;
1870 unsigned HOST_WIDE_INT offset;
1872 offset = (bitpos + bitsdone) / unit;
1873 thispos = (bitpos + bitsdone) % unit;
1875 /* THISSIZE must not overrun a word boundary. Otherwise,
1876 extract_fixed_bit_field will call us again, and we will mutually
1878 thissize = MIN (bitsize - bitsdone, BITS_PER_WORD);
1879 thissize = MIN (thissize, unit - thispos);
1881 /* If OP0 is a register, then handle OFFSET here.
1883 When handling multiword bitfields, extract_bit_field may pass
1884 down a word_mode SUBREG of a larger REG for a bitfield that actually
1885 crosses a word boundary. Thus, for a SUBREG, we must find
1886 the current word starting from the base register. */
1887 if (GET_CODE (op0) == SUBREG)
1889 int word_offset = (SUBREG_BYTE (op0) / UNITS_PER_WORD) + offset;
1890 word = operand_subword_force (SUBREG_REG (op0), word_offset,
1891 GET_MODE (SUBREG_REG (op0)));
1894 else if (GET_CODE (op0) == REG)
1896 word = operand_subword_force (op0, offset, GET_MODE (op0));
1902 /* Extract the parts in bit-counting order,
1903 whose meaning is determined by BYTES_PER_UNIT.
1904 OFFSET is in UNITs, and UNIT is in bits.
1905 extract_fixed_bit_field wants offset in bytes. */
1906 part = extract_fixed_bit_field (word_mode, word,
1907 offset * unit / BITS_PER_UNIT,
1908 thissize, thispos, 0, 1);
1909 bitsdone += thissize;
1911 /* Shift this part into place for the result. */
1912 if (BYTES_BIG_ENDIAN)
1914 if (bitsize != bitsdone)
1915 part = expand_shift (LSHIFT_EXPR, word_mode, part,
1916 build_int_2 (bitsize - bitsdone, 0), 0, 1);
1920 if (bitsdone != thissize)
1921 part = expand_shift (LSHIFT_EXPR, word_mode, part,
1922 build_int_2 (bitsdone - thissize, 0), 0, 1);
1928 /* Combine the parts with bitwise or. This works
1929 because we extracted each part as an unsigned bit field. */
1930 result = expand_binop (word_mode, ior_optab, part, result, NULL_RTX, 1,
1936 /* Unsigned bit field: we are done. */
1939 /* Signed bit field: sign-extend with two arithmetic shifts. */
1940 result = expand_shift (LSHIFT_EXPR, word_mode, result,
1941 build_int_2 (BITS_PER_WORD - bitsize, 0),
1943 return expand_shift (RSHIFT_EXPR, word_mode, result,
1944 build_int_2 (BITS_PER_WORD - bitsize, 0), NULL_RTX, 0);
1947 /* Add INC into TARGET. */
1950 expand_inc (rtx target, rtx inc)
1952 rtx value = expand_binop (GET_MODE (target), add_optab,
1954 target, 0, OPTAB_LIB_WIDEN);
1955 if (value != target)
1956 emit_move_insn (target, value);
1959 /* Subtract DEC from TARGET. */
1962 expand_dec (rtx target, rtx dec)
1964 rtx value = expand_binop (GET_MODE (target), sub_optab,
1966 target, 0, OPTAB_LIB_WIDEN);
1967 if (value != target)
1968 emit_move_insn (target, value);
1971 /* Output a shift instruction for expression code CODE,
1972 with SHIFTED being the rtx for the value to shift,
1973 and AMOUNT the tree for the amount to shift by.
1974 Store the result in the rtx TARGET, if that is convenient.
1975 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
1976 Return the rtx for where the value is. */
1979 expand_shift (enum tree_code code, enum machine_mode mode, rtx shifted,
1980 tree amount, rtx target, int unsignedp)
1983 int left = (code == LSHIFT_EXPR || code == LROTATE_EXPR);
1984 int rotate = (code == LROTATE_EXPR || code == RROTATE_EXPR);
1987 /* Previously detected shift-counts computed by NEGATE_EXPR
1988 and shifted in the other direction; but that does not work
1991 op1 = expand_expr (amount, NULL_RTX, VOIDmode, 0);
1993 if (SHIFT_COUNT_TRUNCATED)
1995 if (GET_CODE (op1) == CONST_INT
1996 && ((unsigned HOST_WIDE_INT) INTVAL (op1) >=
1997 (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode)))
1998 op1 = GEN_INT ((unsigned HOST_WIDE_INT) INTVAL (op1)
1999 % GET_MODE_BITSIZE (mode));
2000 else if (GET_CODE (op1) == SUBREG
2001 && subreg_lowpart_p (op1))
2002 op1 = SUBREG_REG (op1);
2005 if (op1 == const0_rtx)
2008 for (try = 0; temp == 0 && try < 3; try++)
2010 enum optab_methods methods;
2013 methods = OPTAB_DIRECT;
2015 methods = OPTAB_WIDEN;
2017 methods = OPTAB_LIB_WIDEN;
2021 /* Widening does not work for rotation. */
2022 if (methods == OPTAB_WIDEN)
2024 else if (methods == OPTAB_LIB_WIDEN)
2026 /* If we have been unable to open-code this by a rotation,
2027 do it as the IOR of two shifts. I.e., to rotate A
2028 by N bits, compute (A << N) | ((unsigned) A >> (C - N))
2029 where C is the bitsize of A.
2031 It is theoretically possible that the target machine might
2032 not be able to perform either shift and hence we would
2033 be making two libcalls rather than just the one for the
2034 shift (similarly if IOR could not be done). We will allow
2035 this extremely unlikely lossage to avoid complicating the
2038 rtx subtarget = target == shifted ? 0 : target;
2040 tree type = TREE_TYPE (amount);
2041 tree new_amount = make_tree (type, op1);
2043 = fold (build (MINUS_EXPR, type,
2045 build_int_2 (GET_MODE_BITSIZE (mode),
2049 shifted = force_reg (mode, shifted);
2051 temp = expand_shift (left ? LSHIFT_EXPR : RSHIFT_EXPR,
2052 mode, shifted, new_amount, subtarget, 1);
2053 temp1 = expand_shift (left ? RSHIFT_EXPR : LSHIFT_EXPR,
2054 mode, shifted, other_amount, 0, 1);
2055 return expand_binop (mode, ior_optab, temp, temp1, target,
2056 unsignedp, methods);
2059 temp = expand_binop (mode,
2060 left ? rotl_optab : rotr_optab,
2061 shifted, op1, target, unsignedp, methods);
2063 /* If we don't have the rotate, but we are rotating by a constant
2064 that is in range, try a rotate in the opposite direction. */
2066 if (temp == 0 && GET_CODE (op1) == CONST_INT
2068 && (unsigned int) INTVAL (op1) < GET_MODE_BITSIZE (mode))
2069 temp = expand_binop (mode,
2070 left ? rotr_optab : rotl_optab,
2072 GEN_INT (GET_MODE_BITSIZE (mode)
2074 target, unsignedp, methods);
2077 temp = expand_binop (mode,
2078 left ? ashl_optab : lshr_optab,
2079 shifted, op1, target, unsignedp, methods);
2081 /* Do arithmetic shifts.
2082 Also, if we are going to widen the operand, we can just as well
2083 use an arithmetic right-shift instead of a logical one. */
2084 if (temp == 0 && ! rotate
2085 && (! unsignedp || (! left && methods == OPTAB_WIDEN)))
2087 enum optab_methods methods1 = methods;
2089 /* If trying to widen a log shift to an arithmetic shift,
2090 don't accept an arithmetic shift of the same size. */
2092 methods1 = OPTAB_MUST_WIDEN;
2094 /* Arithmetic shift */
2096 temp = expand_binop (mode,
2097 left ? ashl_optab : ashr_optab,
2098 shifted, op1, target, unsignedp, methods1);
2101 /* We used to try extzv here for logical right shifts, but that was
2102 only useful for one machine, the VAX, and caused poor code
2103 generation there for lshrdi3, so the code was deleted and a
2104 define_expand for lshrsi3 was added to vax.md. */
2112 enum alg_code { alg_zero, alg_m, alg_shift,
2113 alg_add_t_m2, alg_sub_t_m2,
2114 alg_add_factor, alg_sub_factor,
2115 alg_add_t2_m, alg_sub_t2_m,
2116 alg_add, alg_subtract, alg_factor, alg_shiftop };
2118 /* This structure records a sequence of operations.
2119 `ops' is the number of operations recorded.
2120 `cost' is their total cost.
2121 The operations are stored in `op' and the corresponding
2122 logarithms of the integer coefficients in `log'.
2124 These are the operations:
2125 alg_zero total := 0;
2126 alg_m total := multiplicand;
2127 alg_shift total := total * coeff
2128 alg_add_t_m2 total := total + multiplicand * coeff;
2129 alg_sub_t_m2 total := total - multiplicand * coeff;
2130 alg_add_factor total := total * coeff + total;
2131 alg_sub_factor total := total * coeff - total;
2132 alg_add_t2_m total := total * coeff + multiplicand;
2133 alg_sub_t2_m total := total * coeff - multiplicand;
2135 The first operand must be either alg_zero or alg_m. */
2141 /* The size of the OP and LOG fields are not directly related to the
2142 word size, but the worst-case algorithms will be if we have few
2143 consecutive ones or zeros, i.e., a multiplicand like 10101010101...
2144 In that case we will generate shift-by-2, add, shift-by-2, add,...,
2145 in total wordsize operations. */
2146 enum alg_code op[MAX_BITS_PER_WORD];
2147 char log[MAX_BITS_PER_WORD];
2150 /* Indicates the type of fixup needed after a constant multiplication.
2151 BASIC_VARIANT means no fixup is needed, NEGATE_VARIANT means that
2152 the result should be negated, and ADD_VARIANT means that the
2153 multiplicand should be added to the result. */
2154 enum mult_variant {basic_variant, negate_variant, add_variant};
2156 static void synth_mult (struct algorithm *, unsigned HOST_WIDE_INT, int);
2157 static bool choose_mult_variant (enum machine_mode, HOST_WIDE_INT,
2158 struct algorithm *, enum mult_variant *, int);
2159 static rtx expand_mult_const (enum machine_mode, rtx, HOST_WIDE_INT, rtx,
2160 const struct algorithm *, enum mult_variant);
2161 static unsigned HOST_WIDE_INT choose_multiplier (unsigned HOST_WIDE_INT, int,
2162 int, unsigned HOST_WIDE_INT *,
2164 static unsigned HOST_WIDE_INT invert_mod2n (unsigned HOST_WIDE_INT, int);
2165 static rtx extract_high_half (enum machine_mode, rtx);
2166 static rtx expand_mult_highpart_optab (enum machine_mode, rtx, rtx, rtx,
2168 /* Compute and return the best algorithm for multiplying by T.
2169 The algorithm must cost less than cost_limit
2170 If retval.cost >= COST_LIMIT, no algorithm was found and all
2171 other field of the returned struct are undefined. */
2174 synth_mult (struct algorithm *alg_out, unsigned HOST_WIDE_INT t,
2178 struct algorithm *alg_in, *best_alg;
2180 unsigned HOST_WIDE_INT q;
2182 /* Indicate that no algorithm is yet found. If no algorithm
2183 is found, this value will be returned and indicate failure. */
2184 alg_out->cost = cost_limit;
2186 if (cost_limit <= 0)
2189 /* t == 1 can be done in zero cost. */
2194 alg_out->op[0] = alg_m;
2198 /* t == 0 sometimes has a cost. If it does and it exceeds our limit,
2202 if (zero_cost >= cost_limit)
2207 alg_out->cost = zero_cost;
2208 alg_out->op[0] = alg_zero;
2213 /* We'll be needing a couple extra algorithm structures now. */
2215 alg_in = alloca (sizeof (struct algorithm));
2216 best_alg = alloca (sizeof (struct algorithm));
2218 /* If we have a group of zero bits at the low-order part of T, try
2219 multiplying by the remaining bits and then doing a shift. */
2223 m = floor_log2 (t & -t); /* m = number of low zero bits */
2224 if (m < BITS_PER_WORD)
2227 cost = shift_cost[m];
2228 synth_mult (alg_in, q, cost_limit - cost);
2230 cost += alg_in->cost;
2231 if (cost < cost_limit)
2233 struct algorithm *x;
2234 x = alg_in, alg_in = best_alg, best_alg = x;
2235 best_alg->log[best_alg->ops] = m;
2236 best_alg->op[best_alg->ops] = alg_shift;
2242 /* If we have an odd number, add or subtract one. */
2245 unsigned HOST_WIDE_INT w;
2247 for (w = 1; (w & t) != 0; w <<= 1)
2249 /* If T was -1, then W will be zero after the loop. This is another
2250 case where T ends with ...111. Handling this with (T + 1) and
2251 subtract 1 produces slightly better code and results in algorithm
2252 selection much faster than treating it like the ...0111 case
2256 /* Reject the case where t is 3.
2257 Thus we prefer addition in that case. */
2260 /* T ends with ...111. Multiply by (T + 1) and subtract 1. */
2262 cost = add_cost[word_mode];
2263 synth_mult (alg_in, t + 1, cost_limit - cost);
2265 cost += alg_in->cost;
2266 if (cost < cost_limit)
2268 struct algorithm *x;
2269 x = alg_in, alg_in = best_alg, best_alg = x;
2270 best_alg->log[best_alg->ops] = 0;
2271 best_alg->op[best_alg->ops] = alg_sub_t_m2;
2277 /* T ends with ...01 or ...011. Multiply by (T - 1) and add 1. */
2279 cost = add_cost[word_mode];
2280 synth_mult (alg_in, t - 1, cost_limit - cost);
2282 cost += alg_in->cost;
2283 if (cost < cost_limit)
2285 struct algorithm *x;
2286 x = alg_in, alg_in = best_alg, best_alg = x;
2287 best_alg->log[best_alg->ops] = 0;
2288 best_alg->op[best_alg->ops] = alg_add_t_m2;
2294 /* Look for factors of t of the form
2295 t = q(2**m +- 1), 2 <= m <= floor(log2(t - 1)).
2296 If we find such a factor, we can multiply by t using an algorithm that
2297 multiplies by q, shift the result by m and add/subtract it to itself.
2299 We search for large factors first and loop down, even if large factors
2300 are less probable than small; if we find a large factor we will find a
2301 good sequence quickly, and therefore be able to prune (by decreasing
2302 COST_LIMIT) the search. */
2304 for (m = floor_log2 (t - 1); m >= 2; m--)
2306 unsigned HOST_WIDE_INT d;
2308 d = ((unsigned HOST_WIDE_INT) 1 << m) + 1;
2309 if (t % d == 0 && t > d && m < BITS_PER_WORD)
2311 cost = add_cost[word_mode] + shift_cost[m];
2312 if (shiftadd_cost[m] < cost)
2313 cost = shiftadd_cost[m];
2314 synth_mult (alg_in, t / d, cost_limit - cost);
2316 cost += alg_in->cost;
2317 if (cost < cost_limit)
2319 struct algorithm *x;
2320 x = alg_in, alg_in = best_alg, best_alg = x;
2321 best_alg->log[best_alg->ops] = m;
2322 best_alg->op[best_alg->ops] = alg_add_factor;
2325 /* Other factors will have been taken care of in the recursion. */
2329 d = ((unsigned HOST_WIDE_INT) 1 << m) - 1;
2330 if (t % d == 0 && t > d && m < BITS_PER_WORD)
2332 cost = add_cost[word_mode] + shift_cost[m];
2333 if (shiftsub_cost[m] < cost)
2334 cost = shiftsub_cost[m];
2335 synth_mult (alg_in, t / d, cost_limit - cost);
2337 cost += alg_in->cost;
2338 if (cost < cost_limit)
2340 struct algorithm *x;
2341 x = alg_in, alg_in = best_alg, best_alg = x;
2342 best_alg->log[best_alg->ops] = m;
2343 best_alg->op[best_alg->ops] = alg_sub_factor;
2350 /* Try shift-and-add (load effective address) instructions,
2351 i.e. do a*3, a*5, a*9. */
2357 if (m >= 0 && m < BITS_PER_WORD)
2359 cost = shiftadd_cost[m];
2360 synth_mult (alg_in, (t - 1) >> m, cost_limit - cost);
2362 cost += alg_in->cost;
2363 if (cost < cost_limit)
2365 struct algorithm *x;
2366 x = alg_in, alg_in = best_alg, best_alg = x;
2367 best_alg->log[best_alg->ops] = m;
2368 best_alg->op[best_alg->ops] = alg_add_t2_m;
2376 if (m >= 0 && m < BITS_PER_WORD)
2378 cost = shiftsub_cost[m];
2379 synth_mult (alg_in, (t + 1) >> m, cost_limit - cost);
2381 cost += alg_in->cost;
2382 if (cost < cost_limit)
2384 struct algorithm *x;
2385 x = alg_in, alg_in = best_alg, best_alg = x;
2386 best_alg->log[best_alg->ops] = m;
2387 best_alg->op[best_alg->ops] = alg_sub_t2_m;
2393 /* If cost_limit has not decreased since we stored it in alg_out->cost,
2394 we have not found any algorithm. */
2395 if (cost_limit == alg_out->cost)
2398 /* If we are getting a too long sequence for `struct algorithm'
2399 to record, make this search fail. */
2400 if (best_alg->ops == MAX_BITS_PER_WORD)
2403 /* Copy the algorithm from temporary space to the space at alg_out.
2404 We avoid using structure assignment because the majority of
2405 best_alg is normally undefined, and this is a critical function. */
2406 alg_out->ops = best_alg->ops + 1;
2407 alg_out->cost = cost_limit;
2408 memcpy (alg_out->op, best_alg->op,
2409 alg_out->ops * sizeof *alg_out->op);
2410 memcpy (alg_out->log, best_alg->log,
2411 alg_out->ops * sizeof *alg_out->log);
2414 /* Find the cheapest way of multiplying a value of mode MODE by VAL.
2415 Try three variations:
2417 - a shift/add sequence based on VAL itself
2418 - a shift/add sequence based on -VAL, followed by a negation
2419 - a shift/add sequence based on VAL - 1, followed by an addition.
2421 Return true if the cheapest of these cost less than MULT_COST,
2422 describing the algorithm in *ALG and final fixup in *VARIANT. */
2425 choose_mult_variant (enum machine_mode mode, HOST_WIDE_INT val,
2426 struct algorithm *alg, enum mult_variant *variant,
2429 struct algorithm alg2;
2431 *variant = basic_variant;
2432 synth_mult (alg, val, mult_cost);
2434 /* This works only if the inverted value actually fits in an
2436 if (HOST_BITS_PER_INT >= GET_MODE_BITSIZE (mode))
2438 synth_mult (&alg2, -val, MIN (alg->cost, mult_cost)
2440 alg2.cost += neg_cost[mode];
2441 if (alg2.cost < alg->cost)
2442 *alg = alg2, *variant = negate_variant;
2445 /* This proves very useful for division-by-constant. */
2446 synth_mult (&alg2, val - 1, MIN (alg->cost, mult_cost)
2448 alg2.cost += add_cost[mode];
2449 if (alg2.cost < alg->cost)
2450 *alg = alg2, *variant = add_variant;
2452 return alg->cost < mult_cost;
2455 /* A subroutine of expand_mult, used for constant multiplications.
2456 Multiply OP0 by VAL in mode MODE, storing the result in TARGET if
2457 convenient. Use the shift/add sequence described by ALG and apply
2458 the final fixup specified by VARIANT. */
2461 expand_mult_const (enum machine_mode mode, rtx op0, HOST_WIDE_INT val,
2462 rtx target, const struct algorithm *alg,
2463 enum mult_variant variant)
2465 HOST_WIDE_INT val_so_far;
2466 rtx insn, accum, tem;
2468 enum machine_mode nmode;
2470 /* op0 must be register to make mult_cost match the precomputed
2471 shiftadd_cost array. */
2472 op0 = protect_from_queue (op0, 0);
2474 /* Avoid referencing memory over and over.
2475 For speed, but also for correctness when mem is volatile. */
2476 if (GET_CODE (op0) == MEM)
2477 op0 = force_reg (mode, op0);
2479 /* ACCUM starts out either as OP0 or as a zero, depending on
2480 the first operation. */
2482 if (alg->op[0] == alg_zero)
2484 accum = copy_to_mode_reg (mode, const0_rtx);
2487 else if (alg->op[0] == alg_m)
2489 accum = copy_to_mode_reg (mode, op0);
2495 for (opno = 1; opno < alg->ops; opno++)
2497 int log = alg->log[opno];
2498 int preserve = preserve_subexpressions_p ();
2499 rtx shift_subtarget = preserve ? 0 : accum;
2501 = (opno == alg->ops - 1 && target != 0 && variant != add_variant
2504 rtx accum_target = preserve ? 0 : accum;
2506 switch (alg->op[opno])
2509 accum = expand_shift (LSHIFT_EXPR, mode, accum,
2510 build_int_2 (log, 0), NULL_RTX, 0);
2515 tem = expand_shift (LSHIFT_EXPR, mode, op0,
2516 build_int_2 (log, 0), NULL_RTX, 0);
2517 accum = force_operand (gen_rtx_PLUS (mode, accum, tem),
2518 add_target ? add_target : accum_target);
2519 val_so_far += (HOST_WIDE_INT) 1 << log;
2523 tem = expand_shift (LSHIFT_EXPR, mode, op0,
2524 build_int_2 (log, 0), NULL_RTX, 0);
2525 accum = force_operand (gen_rtx_MINUS (mode, accum, tem),
2526 add_target ? add_target : accum_target);
2527 val_so_far -= (HOST_WIDE_INT) 1 << log;
2531 accum = expand_shift (LSHIFT_EXPR, mode, accum,
2532 build_int_2 (log, 0), shift_subtarget,
2534 accum = force_operand (gen_rtx_PLUS (mode, accum, op0),
2535 add_target ? add_target : accum_target);
2536 val_so_far = (val_so_far << log) + 1;
2540 accum = expand_shift (LSHIFT_EXPR, mode, accum,
2541 build_int_2 (log, 0), shift_subtarget, 0);
2542 accum = force_operand (gen_rtx_MINUS (mode, accum, op0),
2543 add_target ? add_target : accum_target);
2544 val_so_far = (val_so_far << log) - 1;
2547 case alg_add_factor:
2548 tem = expand_shift (LSHIFT_EXPR, mode, accum,
2549 build_int_2 (log, 0), NULL_RTX, 0);
2550 accum = force_operand (gen_rtx_PLUS (mode, accum, tem),
2551 add_target ? add_target : accum_target);
2552 val_so_far += val_so_far << log;
2555 case alg_sub_factor:
2556 tem = expand_shift (LSHIFT_EXPR, mode, accum,
2557 build_int_2 (log, 0), NULL_RTX, 0);
2558 accum = force_operand (gen_rtx_MINUS (mode, tem, accum),
2559 (add_target ? add_target
2560 : preserve ? 0 : tem));
2561 val_so_far = (val_so_far << log) - val_so_far;
2568 /* Write a REG_EQUAL note on the last insn so that we can cse
2569 multiplication sequences. Note that if ACCUM is a SUBREG,
2570 we've set the inner register and must properly indicate
2573 tem = op0, nmode = mode;
2574 if (GET_CODE (accum) == SUBREG)
2576 nmode = GET_MODE (SUBREG_REG (accum));
2577 tem = gen_lowpart (nmode, op0);
2580 insn = get_last_insn ();
2581 set_unique_reg_note (insn, REG_EQUAL,
2582 gen_rtx_MULT (nmode, tem, GEN_INT (val_so_far)));
2585 if (variant == negate_variant)
2587 val_so_far = -val_so_far;
2588 accum = expand_unop (mode, neg_optab, accum, target, 0);
2590 else if (variant == add_variant)
2592 val_so_far = val_so_far + 1;
2593 accum = force_operand (gen_rtx_PLUS (mode, accum, op0), target);
2596 if (val != val_so_far)
2602 /* Perform a multiplication and return an rtx for the result.
2603 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
2604 TARGET is a suggestion for where to store the result (an rtx).
2606 We check specially for a constant integer as OP1.
2607 If you want this check for OP0 as well, then before calling
2608 you should swap the two operands if OP0 would be constant. */
2611 expand_mult (enum machine_mode mode, rtx op0, rtx op1, rtx target,
2614 rtx const_op1 = op1;
2615 enum mult_variant variant;
2616 struct algorithm algorithm;
2618 /* synth_mult does an `unsigned int' multiply. As long as the mode is
2619 less than or equal in size to `unsigned int' this doesn't matter.
2620 If the mode is larger than `unsigned int', then synth_mult works only
2621 if the constant value exactly fits in an `unsigned int' without any
2622 truncation. This means that multiplying by negative values does
2623 not work; results are off by 2^32 on a 32 bit machine. */
2625 /* If we are multiplying in DImode, it may still be a win
2626 to try to work with shifts and adds. */
2627 if (GET_CODE (op1) == CONST_DOUBLE
2628 && GET_MODE_CLASS (GET_MODE (op1)) == MODE_INT
2629 && HOST_BITS_PER_INT >= BITS_PER_WORD
2630 && CONST_DOUBLE_HIGH (op1) == 0)
2631 const_op1 = GEN_INT (CONST_DOUBLE_LOW (op1));
2632 else if (HOST_BITS_PER_INT < GET_MODE_BITSIZE (mode)
2633 && GET_CODE (op1) == CONST_INT
2634 && INTVAL (op1) < 0)
2637 /* We used to test optimize here, on the grounds that it's better to
2638 produce a smaller program when -O is not used.
2639 But this causes such a terrible slowdown sometimes
2640 that it seems better to use synth_mult always. */
2642 if (const_op1 && GET_CODE (const_op1) == CONST_INT
2643 && (unsignedp || !flag_trapv))
2645 int mult_cost = rtx_cost (gen_rtx_MULT (mode, op0, op1), SET);
2646 mult_cost = MIN (12 * add_cost[mode], mult_cost);
2648 if (choose_mult_variant (mode, INTVAL (const_op1), &algorithm, &variant,
2650 return expand_mult_const (mode, op0, INTVAL (const_op1), target,
2651 &algorithm, variant);
2654 if (GET_CODE (op0) == CONST_DOUBLE)
2661 /* Expand x*2.0 as x+x. */
2662 if (GET_CODE (op1) == CONST_DOUBLE
2663 && GET_MODE_CLASS (mode) == MODE_FLOAT)
2666 REAL_VALUE_FROM_CONST_DOUBLE (d, op1);
2668 if (REAL_VALUES_EQUAL (d, dconst2))
2670 op0 = force_reg (GET_MODE (op0), op0);
2671 return expand_binop (mode, add_optab, op0, op0,
2672 target, unsignedp, OPTAB_LIB_WIDEN);
2676 /* This used to use umul_optab if unsigned, but for non-widening multiply
2677 there is no difference between signed and unsigned. */
2678 op0 = expand_binop (mode,
2680 && flag_trapv && (GET_MODE_CLASS(mode) == MODE_INT)
2681 ? smulv_optab : smul_optab,
2682 op0, op1, target, unsignedp, OPTAB_LIB_WIDEN);
2688 /* Return the smallest n such that 2**n >= X. */
2691 ceil_log2 (unsigned HOST_WIDE_INT x)
2693 return floor_log2 (x - 1) + 1;
2696 /* Choose a minimal N + 1 bit approximation to 1/D that can be used to
2697 replace division by D, and put the least significant N bits of the result
2698 in *MULTIPLIER_PTR and return the most significant bit.
2700 The width of operations is N (should be <= HOST_BITS_PER_WIDE_INT), the
2701 needed precision is in PRECISION (should be <= N).
2703 PRECISION should be as small as possible so this function can choose
2704 multiplier more freely.
2706 The rounded-up logarithm of D is placed in *lgup_ptr. A shift count that
2707 is to be used for a final right shift is placed in *POST_SHIFT_PTR.
2709 Using this function, x/D will be equal to (x * m) >> (*POST_SHIFT_PTR),
2710 where m is the full HOST_BITS_PER_WIDE_INT + 1 bit multiplier. */
2713 unsigned HOST_WIDE_INT
2714 choose_multiplier (unsigned HOST_WIDE_INT d, int n, int precision,
2715 unsigned HOST_WIDE_INT *multiplier_ptr,
2716 int *post_shift_ptr, int *lgup_ptr)
2718 HOST_WIDE_INT mhigh_hi, mlow_hi;
2719 unsigned HOST_WIDE_INT mhigh_lo, mlow_lo;
2720 int lgup, post_shift;
2722 unsigned HOST_WIDE_INT nl, dummy1;
2723 HOST_WIDE_INT nh, dummy2;
2725 /* lgup = ceil(log2(divisor)); */
2726 lgup = ceil_log2 (d);
2732 pow2 = n + lgup - precision;
2734 if (pow == 2 * HOST_BITS_PER_WIDE_INT)
2736 /* We could handle this with some effort, but this case is much better
2737 handled directly with a scc insn, so rely on caller using that. */
2741 /* mlow = 2^(N + lgup)/d */
2742 if (pow >= HOST_BITS_PER_WIDE_INT)
2744 nh = (HOST_WIDE_INT) 1 << (pow - HOST_BITS_PER_WIDE_INT);
2750 nl = (unsigned HOST_WIDE_INT) 1 << pow;
2752 div_and_round_double (TRUNC_DIV_EXPR, 1, nl, nh, d, (HOST_WIDE_INT) 0,
2753 &mlow_lo, &mlow_hi, &dummy1, &dummy2);
2755 /* mhigh = (2^(N + lgup) + 2^N + lgup - precision)/d */
2756 if (pow2 >= HOST_BITS_PER_WIDE_INT)
2757 nh |= (HOST_WIDE_INT) 1 << (pow2 - HOST_BITS_PER_WIDE_INT);
2759 nl |= (unsigned HOST_WIDE_INT) 1 << pow2;
2760 div_and_round_double (TRUNC_DIV_EXPR, 1, nl, nh, d, (HOST_WIDE_INT) 0,
2761 &mhigh_lo, &mhigh_hi, &dummy1, &dummy2);
2763 if (mhigh_hi && nh - d >= d)
2765 if (mhigh_hi > 1 || mlow_hi > 1)
2767 /* Assert that mlow < mhigh. */
2768 if (! (mlow_hi < mhigh_hi || (mlow_hi == mhigh_hi && mlow_lo < mhigh_lo)))
2771 /* If precision == N, then mlow, mhigh exceed 2^N
2772 (but they do not exceed 2^(N+1)). */
2774 /* Reduce to lowest terms. */
2775 for (post_shift = lgup; post_shift > 0; post_shift--)
2777 unsigned HOST_WIDE_INT ml_lo = (mlow_hi << (HOST_BITS_PER_WIDE_INT - 1)) | (mlow_lo >> 1);
2778 unsigned HOST_WIDE_INT mh_lo = (mhigh_hi << (HOST_BITS_PER_WIDE_INT - 1)) | (mhigh_lo >> 1);
2788 *post_shift_ptr = post_shift;
2790 if (n < HOST_BITS_PER_WIDE_INT)
2792 unsigned HOST_WIDE_INT mask = ((unsigned HOST_WIDE_INT) 1 << n) - 1;
2793 *multiplier_ptr = mhigh_lo & mask;
2794 return mhigh_lo >= mask;
2798 *multiplier_ptr = mhigh_lo;
2803 /* Compute the inverse of X mod 2**n, i.e., find Y such that X * Y is
2804 congruent to 1 (mod 2**N). */
2806 static unsigned HOST_WIDE_INT
2807 invert_mod2n (unsigned HOST_WIDE_INT x, int n)
2809 /* Solve x*y == 1 (mod 2^n), where x is odd. Return y. */
2811 /* The algorithm notes that the choice y = x satisfies
2812 x*y == 1 mod 2^3, since x is assumed odd.
2813 Each iteration doubles the number of bits of significance in y. */
2815 unsigned HOST_WIDE_INT mask;
2816 unsigned HOST_WIDE_INT y = x;
2819 mask = (n == HOST_BITS_PER_WIDE_INT
2820 ? ~(unsigned HOST_WIDE_INT) 0
2821 : ((unsigned HOST_WIDE_INT) 1 << n) - 1);
2825 y = y * (2 - x*y) & mask; /* Modulo 2^N */
2831 /* Emit code to adjust ADJ_OPERAND after multiplication of wrong signedness
2832 flavor of OP0 and OP1. ADJ_OPERAND is already the high half of the
2833 product OP0 x OP1. If UNSIGNEDP is nonzero, adjust the signed product
2834 to become unsigned, if UNSIGNEDP is zero, adjust the unsigned product to
2837 The result is put in TARGET if that is convenient.
2839 MODE is the mode of operation. */
2842 expand_mult_highpart_adjust (enum machine_mode mode, rtx adj_operand, rtx op0,
2843 rtx op1, rtx target, int unsignedp)
2846 enum rtx_code adj_code = unsignedp ? PLUS : MINUS;
2848 tem = expand_shift (RSHIFT_EXPR, mode, op0,
2849 build_int_2 (GET_MODE_BITSIZE (mode) - 1, 0),
2851 tem = expand_and (mode, tem, op1, NULL_RTX);
2853 = force_operand (gen_rtx_fmt_ee (adj_code, mode, adj_operand, tem),
2856 tem = expand_shift (RSHIFT_EXPR, mode, op1,
2857 build_int_2 (GET_MODE_BITSIZE (mode) - 1, 0),
2859 tem = expand_and (mode, tem, op0, NULL_RTX);
2860 target = force_operand (gen_rtx_fmt_ee (adj_code, mode, adj_operand, tem),
2866 /* Subroutine of expand_mult_highpart. Return the MODE high part of OP. */
2869 extract_high_half (enum machine_mode mode, rtx op)
2871 enum machine_mode wider_mode;
2873 if (mode == word_mode)
2874 return gen_highpart (mode, op);
2876 wider_mode = GET_MODE_WIDER_MODE (mode);
2877 op = expand_shift (RSHIFT_EXPR, wider_mode, op,
2878 build_int_2 (GET_MODE_BITSIZE (mode), 0), 0, 1);
2879 return convert_modes (mode, wider_mode, op, 0);
2882 /* Like expand_mult_highpart, but only consider using a multiplication
2883 optab. OP1 is an rtx for the constant operand. */
2886 expand_mult_highpart_optab (enum machine_mode mode, rtx op0, rtx op1,
2887 rtx target, int unsignedp, int max_cost)
2889 rtx narrow_op1 = gen_int_mode (INTVAL (op1), mode);
2890 enum machine_mode wider_mode;
2895 wider_mode = GET_MODE_WIDER_MODE (mode);
2896 size = GET_MODE_BITSIZE (mode);
2898 /* Firstly, try using a multiplication insn that only generates the needed
2899 high part of the product, and in the sign flavor of unsignedp. */
2900 if (mul_highpart_cost[mode] < max_cost)
2902 moptab = unsignedp ? umul_highpart_optab : smul_highpart_optab;
2903 tem = expand_binop (mode, moptab, op0, narrow_op1, target,
2904 unsignedp, OPTAB_DIRECT);
2909 /* Secondly, same as above, but use sign flavor opposite of unsignedp.
2910 Need to adjust the result after the multiplication. */
2911 if (size - 1 < BITS_PER_WORD
2912 && (mul_highpart_cost[mode] + 2 * shift_cost[size-1]
2913 + 4 * add_cost[mode] < max_cost))
2915 moptab = unsignedp ? smul_highpart_optab : umul_highpart_optab;
2916 tem = expand_binop (mode, moptab, op0, narrow_op1, target,
2917 unsignedp, OPTAB_DIRECT);
2919 /* We used the wrong signedness. Adjust the result. */
2920 return expand_mult_highpart_adjust (mode, tem, op0, narrow_op1,
2924 /* Try widening multiplication. */
2925 moptab = unsignedp ? umul_widen_optab : smul_widen_optab;
2926 if (moptab->handlers[wider_mode].insn_code != CODE_FOR_nothing
2927 && mul_widen_cost[wider_mode] < max_cost)
2929 tem = expand_binop (wider_mode, moptab, op0, narrow_op1, 0,
2930 unsignedp, OPTAB_WIDEN);
2932 return extract_high_half (mode, tem);
2935 /* Try widening the mode and perform a non-widening multiplication. */
2936 moptab = smul_optab;
2937 if (smul_optab->handlers[wider_mode].insn_code != CODE_FOR_nothing
2938 && size - 1 < BITS_PER_WORD
2939 && mul_cost[wider_mode] + shift_cost[size-1] < max_cost)
2941 tem = expand_binop (wider_mode, moptab, op0, op1, 0,
2942 unsignedp, OPTAB_WIDEN);
2944 return extract_high_half (mode, tem);
2947 /* Try widening multiplication of opposite signedness, and adjust. */
2948 moptab = unsignedp ? smul_widen_optab : umul_widen_optab;
2949 if (moptab->handlers[wider_mode].insn_code != CODE_FOR_nothing
2950 && size - 1 < BITS_PER_WORD
2951 && (mul_widen_cost[wider_mode] + 2 * shift_cost[size-1]
2952 + 4 * add_cost[mode] < max_cost))
2954 tem = expand_binop (wider_mode, moptab, op0, narrow_op1,
2955 NULL_RTX, ! unsignedp, OPTAB_WIDEN);
2958 tem = extract_high_half (mode, tem);
2959 /* We used the wrong signedness. Adjust the result. */
2960 return expand_mult_highpart_adjust (mode, tem, op0, narrow_op1,
2968 /* Emit code to multiply OP0 and CNST1, putting the high half of the result
2969 in TARGET if that is convenient, and return where the result is. If the
2970 operation can not be performed, 0 is returned.
2972 MODE is the mode of operation and result.
2974 UNSIGNEDP nonzero means unsigned multiply.
2976 MAX_COST is the total allowed cost for the expanded RTL. */
2979 expand_mult_highpart (enum machine_mode mode, rtx op0,
2980 unsigned HOST_WIDE_INT cnst1, rtx target,
2981 int unsignedp, int max_cost)
2983 enum machine_mode wider_mode = GET_MODE_WIDER_MODE (mode);
2985 bool sign_adjust = false;
2986 enum mult_variant variant;
2987 struct algorithm alg;
2990 /* We can't support modes wider than HOST_BITS_PER_INT. */
2991 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
2994 op1 = gen_int_mode (cnst1, wider_mode);
2995 cnst1 &= GET_MODE_MASK (mode);
2997 /* We can't optimize modes wider than BITS_PER_WORD.
2998 ??? We might be able to perform double-word arithmetic if
2999 mode == word_mode, however all the cost calculations in
3000 synth_mult etc. assume single-word operations. */
3001 if (GET_MODE_BITSIZE (wider_mode) > BITS_PER_WORD)
3002 return expand_mult_highpart_optab (mode, op0, op1, target,
3003 unsignedp, max_cost);
3005 extra_cost = shift_cost[GET_MODE_BITSIZE (mode) - 1];
3007 /* Check whether we try to multiply by a negative constant. */
3008 if (!unsignedp && ((cnst1 >> (GET_MODE_BITSIZE (mode) - 1)) & 1))
3011 extra_cost += add_cost[mode];
3014 /* See whether shift/add multiplication is cheap enough. */
3015 if (choose_mult_variant (wider_mode, cnst1, &alg, &variant,
3016 max_cost - extra_cost))
3018 /* See whether the specialized multiplication optabs are
3019 cheaper than the shift/add version. */
3020 tem = expand_mult_highpart_optab (mode, op0, op1, target,
3021 unsignedp, alg.cost + extra_cost);
3025 tem = convert_to_mode (wider_mode, op0, unsignedp);
3026 tem = expand_mult_const (wider_mode, tem, cnst1, 0, &alg, variant);
3027 tem = extract_high_half (mode, tem);
3029 /* Adjust result for signedness. */
3031 tem = force_operand (gen_rtx_MINUS (mode, tem, op0), tem);
3035 return expand_mult_highpart_optab (mode, op0, op1, target,
3036 unsignedp, max_cost);
3039 /* Emit the code to divide OP0 by OP1, putting the result in TARGET
3040 if that is convenient, and returning where the result is.
3041 You may request either the quotient or the remainder as the result;
3042 specify REM_FLAG nonzero to get the remainder.
3044 CODE is the expression code for which kind of division this is;
3045 it controls how rounding is done. MODE is the machine mode to use.
3046 UNSIGNEDP nonzero means do unsigned division. */
3048 /* ??? For CEIL_MOD_EXPR, can compute incorrect remainder with ANDI
3049 and then correct it by or'ing in missing high bits
3050 if result of ANDI is nonzero.
3051 For ROUND_MOD_EXPR, can use ANDI and then sign-extend the result.
3052 This could optimize to a bfexts instruction.
3053 But C doesn't use these operations, so their optimizations are
3055 /* ??? For modulo, we don't actually need the highpart of the first product,
3056 the low part will do nicely. And for small divisors, the second multiply
3057 can also be a low-part only multiply or even be completely left out.
3058 E.g. to calculate the remainder of a division by 3 with a 32 bit
3059 multiply, multiply with 0x55555556 and extract the upper two bits;
3060 the result is exact for inputs up to 0x1fffffff.
3061 The input range can be reduced by using cross-sum rules.
3062 For odd divisors >= 3, the following table gives right shift counts
3063 so that if a number is shifted by an integer multiple of the given
3064 amount, the remainder stays the same:
3065 2, 4, 3, 6, 10, 12, 4, 8, 18, 6, 11, 20, 18, 0, 5, 10, 12, 0, 12, 20,
3066 14, 12, 23, 21, 8, 0, 20, 18, 0, 0, 6, 12, 0, 22, 0, 18, 20, 30, 0, 0,
3067 0, 8, 0, 11, 12, 10, 36, 0, 30, 0, 0, 12, 0, 0, 0, 0, 44, 12, 24, 0,
3068 20, 0, 7, 14, 0, 18, 36, 0, 0, 46, 60, 0, 42, 0, 15, 24, 20, 0, 0, 33,
3069 0, 20, 0, 0, 18, 0, 60, 0, 0, 0, 0, 0, 40, 18, 0, 0, 12
3071 Cross-sum rules for even numbers can be derived by leaving as many bits
3072 to the right alone as the divisor has zeros to the right.
3073 E.g. if x is an unsigned 32 bit number:
3074 (x mod 12) == (((x & 1023) + ((x >> 8) & ~3)) * 0x15555558 >> 2 * 3) >> 28
3077 #define EXACT_POWER_OF_2_OR_ZERO_P(x) (((x) & ((x) - 1)) == 0)
3080 expand_divmod (int rem_flag, enum tree_code code, enum machine_mode mode,
3081 rtx op0, rtx op1, rtx target, int unsignedp)
3083 enum machine_mode compute_mode;
3085 rtx quotient = 0, remainder = 0;
3089 optab optab1, optab2;
3090 int op1_is_constant, op1_is_pow2 = 0;
3091 int max_cost, extra_cost;
3092 static HOST_WIDE_INT last_div_const = 0;
3093 static HOST_WIDE_INT ext_op1;
3095 op1_is_constant = GET_CODE (op1) == CONST_INT;
3096 if (op1_is_constant)
3098 ext_op1 = INTVAL (op1);
3100 ext_op1 &= GET_MODE_MASK (mode);
3101 op1_is_pow2 = ((EXACT_POWER_OF_2_OR_ZERO_P (ext_op1)
3102 || (! unsignedp && EXACT_POWER_OF_2_OR_ZERO_P (-ext_op1))));
3106 This is the structure of expand_divmod:
3108 First comes code to fix up the operands so we can perform the operations
3109 correctly and efficiently.
3111 Second comes a switch statement with code specific for each rounding mode.
3112 For some special operands this code emits all RTL for the desired
3113 operation, for other cases, it generates only a quotient and stores it in
3114 QUOTIENT. The case for trunc division/remainder might leave quotient = 0,
3115 to indicate that it has not done anything.
3117 Last comes code that finishes the operation. If QUOTIENT is set and
3118 REM_FLAG is set, the remainder is computed as OP0 - QUOTIENT * OP1. If
3119 QUOTIENT is not set, it is computed using trunc rounding.
3121 We try to generate special code for division and remainder when OP1 is a
3122 constant. If |OP1| = 2**n we can use shifts and some other fast
3123 operations. For other values of OP1, we compute a carefully selected
3124 fixed-point approximation m = 1/OP1, and generate code that multiplies OP0
3127 In all cases but EXACT_DIV_EXPR, this multiplication requires the upper
3128 half of the product. Different strategies for generating the product are
3129 implemented in expand_mult_highpart.
3131 If what we actually want is the remainder, we generate that by another
3132 by-constant multiplication and a subtraction. */
3134 /* We shouldn't be called with OP1 == const1_rtx, but some of the
3135 code below will malfunction if we are, so check here and handle
3136 the special case if so. */
3137 if (op1 == const1_rtx)
3138 return rem_flag ? const0_rtx : op0;
3140 /* When dividing by -1, we could get an overflow.
3141 negv_optab can handle overflows. */
3142 if (! unsignedp && op1 == constm1_rtx)
3146 return expand_unop (mode, flag_trapv && GET_MODE_CLASS(mode) == MODE_INT
3147 ? negv_optab : neg_optab, op0, target, 0);
3151 /* Don't use the function value register as a target
3152 since we have to read it as well as write it,
3153 and function-inlining gets confused by this. */
3154 && ((REG_P (target) && REG_FUNCTION_VALUE_P (target))
3155 /* Don't clobber an operand while doing a multi-step calculation. */
3156 || ((rem_flag || op1_is_constant)
3157 && (reg_mentioned_p (target, op0)
3158 || (GET_CODE (op0) == MEM && GET_CODE (target) == MEM)))
3159 || reg_mentioned_p (target, op1)
3160 || (GET_CODE (op1) == MEM && GET_CODE (target) == MEM)))
3163 /* Get the mode in which to perform this computation. Normally it will
3164 be MODE, but sometimes we can't do the desired operation in MODE.
3165 If so, pick a wider mode in which we can do the operation. Convert
3166 to that mode at the start to avoid repeated conversions.
3168 First see what operations we need. These depend on the expression
3169 we are evaluating. (We assume that divxx3 insns exist under the
3170 same conditions that modxx3 insns and that these insns don't normally
3171 fail. If these assumptions are not correct, we may generate less
3172 efficient code in some cases.)
3174 Then see if we find a mode in which we can open-code that operation
3175 (either a division, modulus, or shift). Finally, check for the smallest
3176 mode for which we can do the operation with a library call. */
3178 /* We might want to refine this now that we have division-by-constant
3179 optimization. Since expand_mult_highpart tries so many variants, it is
3180 not straightforward to generalize this. Maybe we should make an array
3181 of possible modes in init_expmed? Save this for GCC 2.7. */
3183 optab1 = ((op1_is_pow2 && op1 != const0_rtx)
3184 ? (unsignedp ? lshr_optab : ashr_optab)
3185 : (unsignedp ? udiv_optab : sdiv_optab));
3186 optab2 = ((op1_is_pow2 && op1 != const0_rtx)
3188 : (unsignedp ? udivmod_optab : sdivmod_optab));
3190 for (compute_mode = mode; compute_mode != VOIDmode;
3191 compute_mode = GET_MODE_WIDER_MODE (compute_mode))
3192 if (optab1->handlers[compute_mode].insn_code != CODE_FOR_nothing
3193 || optab2->handlers[compute_mode].insn_code != CODE_FOR_nothing)
3196 if (compute_mode == VOIDmode)
3197 for (compute_mode = mode; compute_mode != VOIDmode;
3198 compute_mode = GET_MODE_WIDER_MODE (compute_mode))
3199 if (optab1->handlers[compute_mode].libfunc
3200 || optab2->handlers[compute_mode].libfunc)
3203 /* If we still couldn't find a mode, use MODE, but we'll probably abort
3205 if (compute_mode == VOIDmode)
3206 compute_mode = mode;
3208 if (target && GET_MODE (target) == compute_mode)
3211 tquotient = gen_reg_rtx (compute_mode);
3213 size = GET_MODE_BITSIZE (compute_mode);
3215 /* It should be possible to restrict the precision to GET_MODE_BITSIZE
3216 (mode), and thereby get better code when OP1 is a constant. Do that
3217 later. It will require going over all usages of SIZE below. */
3218 size = GET_MODE_BITSIZE (mode);
3221 /* Only deduct something for a REM if the last divide done was
3222 for a different constant. Then set the constant of the last
3224 max_cost = div_cost[compute_mode]
3225 - (rem_flag && ! (last_div_const != 0 && op1_is_constant
3226 && INTVAL (op1) == last_div_const)
3227 ? mul_cost[compute_mode] + add_cost[compute_mode]
3230 last_div_const = ! rem_flag && op1_is_constant ? INTVAL (op1) : 0;
3232 /* Now convert to the best mode to use. */
3233 if (compute_mode != mode)
3235 op0 = convert_modes (compute_mode, mode, op0, unsignedp);
3236 op1 = convert_modes (compute_mode, mode, op1, unsignedp);
3238 /* convert_modes may have placed op1 into a register, so we
3239 must recompute the following. */
3240 op1_is_constant = GET_CODE (op1) == CONST_INT;
3241 op1_is_pow2 = (op1_is_constant
3242 && ((EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1))
3244 && EXACT_POWER_OF_2_OR_ZERO_P (-INTVAL (op1)))))) ;
3247 /* If one of the operands is a volatile MEM, copy it into a register. */
3249 if (GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0))
3250 op0 = force_reg (compute_mode, op0);
3251 if (GET_CODE (op1) == MEM && MEM_VOLATILE_P (op1))
3252 op1 = force_reg (compute_mode, op1);
3254 /* If we need the remainder or if OP1 is constant, we need to
3255 put OP0 in a register in case it has any queued subexpressions. */
3256 if (rem_flag || op1_is_constant)
3257 op0 = force_reg (compute_mode, op0);
3259 last = get_last_insn ();
3261 /* Promote floor rounding to trunc rounding for unsigned operations. */
3264 if (code == FLOOR_DIV_EXPR)
3265 code = TRUNC_DIV_EXPR;
3266 if (code == FLOOR_MOD_EXPR)
3267 code = TRUNC_MOD_EXPR;
3268 if (code == EXACT_DIV_EXPR && op1_is_pow2)
3269 code = TRUNC_DIV_EXPR;
3272 if (op1 != const0_rtx)
3275 case TRUNC_MOD_EXPR:
3276 case TRUNC_DIV_EXPR:
3277 if (op1_is_constant)
3281 unsigned HOST_WIDE_INT mh, ml;
3282 int pre_shift, post_shift;
3284 unsigned HOST_WIDE_INT d = (INTVAL (op1)
3285 & GET_MODE_MASK (compute_mode));
3287 if (EXACT_POWER_OF_2_OR_ZERO_P (d))
3289 pre_shift = floor_log2 (d);
3293 = expand_binop (compute_mode, and_optab, op0,
3294 GEN_INT (((HOST_WIDE_INT) 1 << pre_shift) - 1),
3298 return gen_lowpart (mode, remainder);
3300 quotient = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3301 build_int_2 (pre_shift, 0),
3304 else if (size <= HOST_BITS_PER_WIDE_INT)
3306 if (d >= ((unsigned HOST_WIDE_INT) 1 << (size - 1)))
3308 /* Most significant bit of divisor is set; emit an scc
3310 quotient = emit_store_flag (tquotient, GEU, op0, op1,
3311 compute_mode, 1, 1);
3317 /* Find a suitable multiplier and right shift count
3318 instead of multiplying with D. */
3320 mh = choose_multiplier (d, size, size,
3321 &ml, &post_shift, &dummy);
3323 /* If the suggested multiplier is more than SIZE bits,
3324 we can do better for even divisors, using an
3325 initial right shift. */
3326 if (mh != 0 && (d & 1) == 0)
3328 pre_shift = floor_log2 (d & -d);
3329 mh = choose_multiplier (d >> pre_shift, size,
3331 &ml, &post_shift, &dummy);
3342 if (post_shift - 1 >= BITS_PER_WORD)
3345 extra_cost = (shift_cost[post_shift - 1]
3347 + 2 * add_cost[compute_mode]);
3348 t1 = expand_mult_highpart (compute_mode, op0, ml,
3350 max_cost - extra_cost);
3353 t2 = force_operand (gen_rtx_MINUS (compute_mode,
3356 t3 = expand_shift (RSHIFT_EXPR, compute_mode, t2,
3357 build_int_2 (1, 0), NULL_RTX,1);
3358 t4 = force_operand (gen_rtx_PLUS (compute_mode,
3362 = expand_shift (RSHIFT_EXPR, compute_mode, t4,
3363 build_int_2 (post_shift - 1, 0),
3370 if (pre_shift >= BITS_PER_WORD
3371 || post_shift >= BITS_PER_WORD)
3374 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3375 build_int_2 (pre_shift, 0),
3377 extra_cost = (shift_cost[pre_shift]
3378 + shift_cost[post_shift]);
3379 t2 = expand_mult_highpart (compute_mode, t1, ml,
3381 max_cost - extra_cost);
3385 = expand_shift (RSHIFT_EXPR, compute_mode, t2,
3386 build_int_2 (post_shift, 0),
3391 else /* Too wide mode to use tricky code */
3394 insn = get_last_insn ();
3396 && (set = single_set (insn)) != 0
3397 && SET_DEST (set) == quotient)
3398 set_unique_reg_note (insn,
3400 gen_rtx_UDIV (compute_mode, op0, op1));
3402 else /* TRUNC_DIV, signed */
3404 unsigned HOST_WIDE_INT ml;
3405 int lgup, post_shift;
3406 HOST_WIDE_INT d = INTVAL (op1);
3407 unsigned HOST_WIDE_INT abs_d = d >= 0 ? d : -d;
3409 /* n rem d = n rem -d */
3410 if (rem_flag && d < 0)
3413 op1 = gen_int_mode (abs_d, compute_mode);
3419 quotient = expand_unop (compute_mode, neg_optab, op0,
3421 else if (abs_d == (unsigned HOST_WIDE_INT) 1 << (size - 1))
3423 /* This case is not handled correctly below. */
3424 quotient = emit_store_flag (tquotient, EQ, op0, op1,
3425 compute_mode, 1, 1);
3429 else if (EXACT_POWER_OF_2_OR_ZERO_P (d)
3430 && (rem_flag ? smod_pow2_cheap[compute_mode]
3431 : sdiv_pow2_cheap[compute_mode])
3432 /* ??? The cheap metric is computed only for
3433 word_mode. If this operation is wider, this may
3434 not be so. Assume true if the optab has an
3435 expander for this mode. */
3436 && (((rem_flag ? smod_optab : sdiv_optab)
3437 ->handlers[compute_mode].insn_code
3438 != CODE_FOR_nothing)
3439 || (sdivmod_optab->handlers[compute_mode]
3440 .insn_code != CODE_FOR_nothing)))
3442 else if (EXACT_POWER_OF_2_OR_ZERO_P (abs_d))
3444 lgup = floor_log2 (abs_d);
3445 if (BRANCH_COST < 1 || (abs_d != 2 && BRANCH_COST < 3))
3447 rtx label = gen_label_rtx ();
3450 t1 = copy_to_mode_reg (compute_mode, op0);
3451 do_cmp_and_jump (t1, const0_rtx, GE,
3452 compute_mode, label);
3453 expand_inc (t1, gen_int_mode (abs_d - 1,
3456 quotient = expand_shift (RSHIFT_EXPR, compute_mode, t1,
3457 build_int_2 (lgup, 0),
3463 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3464 build_int_2 (size - 1, 0),
3466 t2 = expand_shift (RSHIFT_EXPR, compute_mode, t1,
3467 build_int_2 (size - lgup, 0),
3469 t3 = force_operand (gen_rtx_PLUS (compute_mode,
3472 quotient = expand_shift (RSHIFT_EXPR, compute_mode, t3,
3473 build_int_2 (lgup, 0),
3477 /* We have computed OP0 / abs(OP1). If OP1 is negative, negate
3481 insn = get_last_insn ();
3483 && (set = single_set (insn)) != 0
3484 && SET_DEST (set) == quotient
3485 && abs_d < ((unsigned HOST_WIDE_INT) 1
3486 << (HOST_BITS_PER_WIDE_INT - 1)))
3487 set_unique_reg_note (insn,
3489 gen_rtx_DIV (compute_mode,
3496 quotient = expand_unop (compute_mode, neg_optab,
3497 quotient, quotient, 0);
3500 else if (size <= HOST_BITS_PER_WIDE_INT)
3502 choose_multiplier (abs_d, size, size - 1,
3503 &ml, &post_shift, &lgup);
3504 if (ml < (unsigned HOST_WIDE_INT) 1 << (size - 1))
3508 if (post_shift >= BITS_PER_WORD
3509 || size - 1 >= BITS_PER_WORD)
3512 extra_cost = (shift_cost[post_shift]
3513 + shift_cost[size - 1]
3514 + add_cost[compute_mode]);
3515 t1 = expand_mult_highpart (compute_mode, op0, ml,
3517 max_cost - extra_cost);
3520 t2 = expand_shift (RSHIFT_EXPR, compute_mode, t1,
3521 build_int_2 (post_shift, 0), NULL_RTX, 0);
3522 t3 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3523 build_int_2 (size - 1, 0), NULL_RTX, 0);
3526 = force_operand (gen_rtx_MINUS (compute_mode,
3531 = force_operand (gen_rtx_MINUS (compute_mode,
3539 if (post_shift >= BITS_PER_WORD
3540 || size - 1 >= BITS_PER_WORD)
3543 ml |= (~(unsigned HOST_WIDE_INT) 0) << (size - 1);
3544 extra_cost = (shift_cost[post_shift]
3545 + shift_cost[size - 1]
3546 + 2 * add_cost[compute_mode]);
3547 t1 = expand_mult_highpart (compute_mode, op0, ml,
3549 max_cost - extra_cost);
3552 t2 = force_operand (gen_rtx_PLUS (compute_mode,
3555 t3 = expand_shift (RSHIFT_EXPR, compute_mode, t2,
3556 build_int_2 (post_shift, 0),
3558 t4 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3559 build_int_2 (size - 1, 0),
3563 = force_operand (gen_rtx_MINUS (compute_mode,
3568 = force_operand (gen_rtx_MINUS (compute_mode,
3573 else /* Too wide mode to use tricky code */
3576 insn = get_last_insn ();
3578 && (set = single_set (insn)) != 0
3579 && SET_DEST (set) == quotient)
3580 set_unique_reg_note (insn,
3582 gen_rtx_DIV (compute_mode, op0, op1));
3587 delete_insns_since (last);
3590 case FLOOR_DIV_EXPR:
3591 case FLOOR_MOD_EXPR:
3592 /* We will come here only for signed operations. */
3593 if (op1_is_constant && HOST_BITS_PER_WIDE_INT >= size)
3595 unsigned HOST_WIDE_INT mh, ml;
3596 int pre_shift, lgup, post_shift;
3597 HOST_WIDE_INT d = INTVAL (op1);
3601 /* We could just as easily deal with negative constants here,
3602 but it does not seem worth the trouble for GCC 2.6. */
3603 if (EXACT_POWER_OF_2_OR_ZERO_P (d))
3605 pre_shift = floor_log2 (d);
3608 remainder = expand_binop (compute_mode, and_optab, op0,
3609 GEN_INT (((HOST_WIDE_INT) 1 << pre_shift) - 1),
3610 remainder, 0, OPTAB_LIB_WIDEN);
3612 return gen_lowpart (mode, remainder);
3614 quotient = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3615 build_int_2 (pre_shift, 0),
3622 mh = choose_multiplier (d, size, size - 1,
3623 &ml, &post_shift, &lgup);
3627 if (post_shift < BITS_PER_WORD
3628 && size - 1 < BITS_PER_WORD)
3630 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3631 build_int_2 (size - 1, 0),
3633 t2 = expand_binop (compute_mode, xor_optab, op0, t1,
3634 NULL_RTX, 0, OPTAB_WIDEN);
3635 extra_cost = (shift_cost[post_shift]
3636 + shift_cost[size - 1]
3637 + 2 * add_cost[compute_mode]);
3638 t3 = expand_mult_highpart (compute_mode, t2, ml,
3640 max_cost - extra_cost);
3643 t4 = expand_shift (RSHIFT_EXPR, compute_mode, t3,
3644 build_int_2 (post_shift, 0),
3646 quotient = expand_binop (compute_mode, xor_optab,
3647 t4, t1, tquotient, 0,
3655 rtx nsign, t1, t2, t3, t4;
3656 t1 = force_operand (gen_rtx_PLUS (compute_mode,
3657 op0, constm1_rtx), NULL_RTX);
3658 t2 = expand_binop (compute_mode, ior_optab, op0, t1, NULL_RTX,
3660 nsign = expand_shift (RSHIFT_EXPR, compute_mode, t2,
3661 build_int_2 (size - 1, 0), NULL_RTX, 0);
3662 t3 = force_operand (gen_rtx_MINUS (compute_mode, t1, nsign),
3664 t4 = expand_divmod (0, TRUNC_DIV_EXPR, compute_mode, t3, op1,
3669 t5 = expand_unop (compute_mode, one_cmpl_optab, nsign,
3671 quotient = force_operand (gen_rtx_PLUS (compute_mode,
3680 delete_insns_since (last);
3682 /* Try using an instruction that produces both the quotient and
3683 remainder, using truncation. We can easily compensate the quotient
3684 or remainder to get floor rounding, once we have the remainder.
3685 Notice that we compute also the final remainder value here,
3686 and return the result right away. */
3687 if (target == 0 || GET_MODE (target) != compute_mode)
3688 target = gen_reg_rtx (compute_mode);
3693 = GET_CODE (target) == REG ? target : gen_reg_rtx (compute_mode);
3694 quotient = gen_reg_rtx (compute_mode);
3699 = GET_CODE (target) == REG ? target : gen_reg_rtx (compute_mode);
3700 remainder = gen_reg_rtx (compute_mode);
3703 if (expand_twoval_binop (sdivmod_optab, op0, op1,
3704 quotient, remainder, 0))
3706 /* This could be computed with a branch-less sequence.
3707 Save that for later. */
3709 rtx label = gen_label_rtx ();
3710 do_cmp_and_jump (remainder, const0_rtx, EQ, compute_mode, label);
3711 tem = expand_binop (compute_mode, xor_optab, op0, op1,
3712 NULL_RTX, 0, OPTAB_WIDEN);
3713 do_cmp_and_jump (tem, const0_rtx, GE, compute_mode, label);
3714 expand_dec (quotient, const1_rtx);
3715 expand_inc (remainder, op1);
3717 return gen_lowpart (mode, rem_flag ? remainder : quotient);
3720 /* No luck with division elimination or divmod. Have to do it
3721 by conditionally adjusting op0 *and* the result. */
3723 rtx label1, label2, label3, label4, label5;
3727 quotient = gen_reg_rtx (compute_mode);
3728 adjusted_op0 = copy_to_mode_reg (compute_mode, op0);
3729 label1 = gen_label_rtx ();
3730 label2 = gen_label_rtx ();
3731 label3 = gen_label_rtx ();
3732 label4 = gen_label_rtx ();
3733 label5 = gen_label_rtx ();
3734 do_cmp_and_jump (op1, const0_rtx, LT, compute_mode, label2);
3735 do_cmp_and_jump (adjusted_op0, const0_rtx, LT, compute_mode, label1);
3736 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
3737 quotient, 0, OPTAB_LIB_WIDEN);
3738 if (tem != quotient)
3739 emit_move_insn (quotient, tem);
3740 emit_jump_insn (gen_jump (label5));
3742 emit_label (label1);
3743 expand_inc (adjusted_op0, const1_rtx);
3744 emit_jump_insn (gen_jump (label4));
3746 emit_label (label2);
3747 do_cmp_and_jump (adjusted_op0, const0_rtx, GT, compute_mode, label3);
3748 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
3749 quotient, 0, OPTAB_LIB_WIDEN);
3750 if (tem != quotient)
3751 emit_move_insn (quotient, tem);
3752 emit_jump_insn (gen_jump (label5));
3754 emit_label (label3);
3755 expand_dec (adjusted_op0, const1_rtx);
3756 emit_label (label4);
3757 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
3758 quotient, 0, OPTAB_LIB_WIDEN);
3759 if (tem != quotient)
3760 emit_move_insn (quotient, tem);
3761 expand_dec (quotient, const1_rtx);
3762 emit_label (label5);
3770 if (op1_is_constant && EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1)))
3773 unsigned HOST_WIDE_INT d = INTVAL (op1);
3774 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3775 build_int_2 (floor_log2 (d), 0),
3777 t2 = expand_binop (compute_mode, and_optab, op0,
3779 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3780 t3 = gen_reg_rtx (compute_mode);
3781 t3 = emit_store_flag (t3, NE, t2, const0_rtx,
3782 compute_mode, 1, 1);
3786 lab = gen_label_rtx ();
3787 do_cmp_and_jump (t2, const0_rtx, EQ, compute_mode, lab);
3788 expand_inc (t1, const1_rtx);
3793 quotient = force_operand (gen_rtx_PLUS (compute_mode,
3799 /* Try using an instruction that produces both the quotient and
3800 remainder, using truncation. We can easily compensate the
3801 quotient or remainder to get ceiling rounding, once we have the
3802 remainder. Notice that we compute also the final remainder
3803 value here, and return the result right away. */
3804 if (target == 0 || GET_MODE (target) != compute_mode)
3805 target = gen_reg_rtx (compute_mode);
3809 remainder = (GET_CODE (target) == REG
3810 ? target : gen_reg_rtx (compute_mode));
3811 quotient = gen_reg_rtx (compute_mode);
3815 quotient = (GET_CODE (target) == REG
3816 ? target : gen_reg_rtx (compute_mode));
3817 remainder = gen_reg_rtx (compute_mode);
3820 if (expand_twoval_binop (udivmod_optab, op0, op1, quotient,
3823 /* This could be computed with a branch-less sequence.
3824 Save that for later. */
3825 rtx label = gen_label_rtx ();
3826 do_cmp_and_jump (remainder, const0_rtx, EQ,
3827 compute_mode, label);
3828 expand_inc (quotient, const1_rtx);
3829 expand_dec (remainder, op1);
3831 return gen_lowpart (mode, rem_flag ? remainder : quotient);
3834 /* No luck with division elimination or divmod. Have to do it
3835 by conditionally adjusting op0 *and* the result. */
3838 rtx adjusted_op0, tem;
3840 quotient = gen_reg_rtx (compute_mode);
3841 adjusted_op0 = copy_to_mode_reg (compute_mode, op0);
3842 label1 = gen_label_rtx ();
3843 label2 = gen_label_rtx ();
3844 do_cmp_and_jump (adjusted_op0, const0_rtx, NE,
3845 compute_mode, label1);
3846 emit_move_insn (quotient, const0_rtx);
3847 emit_jump_insn (gen_jump (label2));
3849 emit_label (label1);
3850 expand_dec (adjusted_op0, const1_rtx);
3851 tem = expand_binop (compute_mode, udiv_optab, adjusted_op0, op1,
3852 quotient, 1, OPTAB_LIB_WIDEN);
3853 if (tem != quotient)
3854 emit_move_insn (quotient, tem);
3855 expand_inc (quotient, const1_rtx);
3856 emit_label (label2);
3861 if (op1_is_constant && EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1))
3862 && INTVAL (op1) >= 0)
3864 /* This is extremely similar to the code for the unsigned case
3865 above. For 2.7 we should merge these variants, but for
3866 2.6.1 I don't want to touch the code for unsigned since that
3867 get used in C. The signed case will only be used by other
3871 unsigned HOST_WIDE_INT d = INTVAL (op1);
3872 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3873 build_int_2 (floor_log2 (d), 0),
3875 t2 = expand_binop (compute_mode, and_optab, op0,
3877 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3878 t3 = gen_reg_rtx (compute_mode);
3879 t3 = emit_store_flag (t3, NE, t2, const0_rtx,
3880 compute_mode, 1, 1);
3884 lab = gen_label_rtx ();
3885 do_cmp_and_jump (t2, const0_rtx, EQ, compute_mode, lab);
3886 expand_inc (t1, const1_rtx);
3891 quotient = force_operand (gen_rtx_PLUS (compute_mode,
3897 /* Try using an instruction that produces both the quotient and
3898 remainder, using truncation. We can easily compensate the
3899 quotient or remainder to get ceiling rounding, once we have the
3900 remainder. Notice that we compute also the final remainder
3901 value here, and return the result right away. */
3902 if (target == 0 || GET_MODE (target) != compute_mode)
3903 target = gen_reg_rtx (compute_mode);
3906 remainder= (GET_CODE (target) == REG
3907 ? target : gen_reg_rtx (compute_mode));
3908 quotient = gen_reg_rtx (compute_mode);
3912 quotient = (GET_CODE (target) == REG
3913 ? target : gen_reg_rtx (compute_mode));
3914 remainder = gen_reg_rtx (compute_mode);
3917 if (expand_twoval_binop (sdivmod_optab, op0, op1, quotient,
3920 /* This could be computed with a branch-less sequence.
3921 Save that for later. */
3923 rtx label = gen_label_rtx ();
3924 do_cmp_and_jump (remainder, const0_rtx, EQ,
3925 compute_mode, label);
3926 tem = expand_binop (compute_mode, xor_optab, op0, op1,
3927 NULL_RTX, 0, OPTAB_WIDEN);
3928 do_cmp_and_jump (tem, const0_rtx, LT, compute_mode, label);
3929 expand_inc (quotient, const1_rtx);
3930 expand_dec (remainder, op1);
3932 return gen_lowpart (mode, rem_flag ? remainder : quotient);
3935 /* No luck with division elimination or divmod. Have to do it
3936 by conditionally adjusting op0 *and* the result. */
3938 rtx label1, label2, label3, label4, label5;
3942 quotient = gen_reg_rtx (compute_mode);
3943 adjusted_op0 = copy_to_mode_reg (compute_mode, op0);
3944 label1 = gen_label_rtx ();
3945 label2 = gen_label_rtx ();
3946 label3 = gen_label_rtx ();
3947 label4 = gen_label_rtx ();
3948 label5 = gen_label_rtx ();
3949 do_cmp_and_jump (op1, const0_rtx, LT, compute_mode, label2);
3950 do_cmp_and_jump (adjusted_op0, const0_rtx, GT,
3951 compute_mode, label1);
3952 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
3953 quotient, 0, OPTAB_LIB_WIDEN);
3954 if (tem != quotient)
3955 emit_move_insn (quotient, tem);
3956 emit_jump_insn (gen_jump (label5));
3958 emit_label (label1);
3959 expand_dec (adjusted_op0, const1_rtx);
3960 emit_jump_insn (gen_jump (label4));
3962 emit_label (label2);
3963 do_cmp_and_jump (adjusted_op0, const0_rtx, LT,
3964 compute_mode, label3);
3965 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
3966 quotient, 0, OPTAB_LIB_WIDEN);
3967 if (tem != quotient)
3968 emit_move_insn (quotient, tem);
3969 emit_jump_insn (gen_jump (label5));
3971 emit_label (label3);
3972 expand_inc (adjusted_op0, const1_rtx);
3973 emit_label (label4);
3974 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
3975 quotient, 0, OPTAB_LIB_WIDEN);
3976 if (tem != quotient)
3977 emit_move_insn (quotient, tem);
3978 expand_inc (quotient, const1_rtx);
3979 emit_label (label5);
3984 case EXACT_DIV_EXPR:
3985 if (op1_is_constant && HOST_BITS_PER_WIDE_INT >= size)
3987 HOST_WIDE_INT d = INTVAL (op1);
3988 unsigned HOST_WIDE_INT ml;
3992 pre_shift = floor_log2 (d & -d);
3993 ml = invert_mod2n (d >> pre_shift, size);
3994 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3995 build_int_2 (pre_shift, 0), NULL_RTX, unsignedp);
3996 quotient = expand_mult (compute_mode, t1,
3997 gen_int_mode (ml, compute_mode),
4000 insn = get_last_insn ();
4001 set_unique_reg_note (insn,
4003 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
4009 case ROUND_DIV_EXPR:
4010 case ROUND_MOD_EXPR:
4015 label = gen_label_rtx ();
4016 quotient = gen_reg_rtx (compute_mode);
4017 remainder = gen_reg_rtx (compute_mode);
4018 if (expand_twoval_binop (udivmod_optab, op0, op1, quotient, remainder, 1) == 0)
4021 quotient = expand_binop (compute_mode, udiv_optab, op0, op1,
4022 quotient, 1, OPTAB_LIB_WIDEN);
4023 tem = expand_mult (compute_mode, quotient, op1, NULL_RTX, 1);
4024 remainder = expand_binop (compute_mode, sub_optab, op0, tem,
4025 remainder, 1, OPTAB_LIB_WIDEN);
4027 tem = plus_constant (op1, -1);
4028 tem = expand_shift (RSHIFT_EXPR, compute_mode, tem,
4029 build_int_2 (1, 0), NULL_RTX, 1);
4030 do_cmp_and_jump (remainder, tem, LEU, compute_mode, label);
4031 expand_inc (quotient, const1_rtx);
4032 expand_dec (remainder, op1);
4037 rtx abs_rem, abs_op1, tem, mask;
4039 label = gen_label_rtx ();
4040 quotient = gen_reg_rtx (compute_mode);
4041 remainder = gen_reg_rtx (compute_mode);
4042 if (expand_twoval_binop (sdivmod_optab, op0, op1, quotient, remainder, 0) == 0)
4045 quotient = expand_binop (compute_mode, sdiv_optab, op0, op1,
4046 quotient, 0, OPTAB_LIB_WIDEN);
4047 tem = expand_mult (compute_mode, quotient, op1, NULL_RTX, 0);
4048 remainder = expand_binop (compute_mode, sub_optab, op0, tem,
4049 remainder, 0, OPTAB_LIB_WIDEN);
4051 abs_rem = expand_abs (compute_mode, remainder, NULL_RTX, 1, 0);
4052 abs_op1 = expand_abs (compute_mode, op1, NULL_RTX, 1, 0);
4053 tem = expand_shift (LSHIFT_EXPR, compute_mode, abs_rem,
4054 build_int_2 (1, 0), NULL_RTX, 1);
4055 do_cmp_and_jump (tem, abs_op1, LTU, compute_mode, label);
4056 tem = expand_binop (compute_mode, xor_optab, op0, op1,
4057 NULL_RTX, 0, OPTAB_WIDEN);
4058 mask = expand_shift (RSHIFT_EXPR, compute_mode, tem,
4059 build_int_2 (size - 1, 0), NULL_RTX, 0);
4060 tem = expand_binop (compute_mode, xor_optab, mask, const1_rtx,
4061 NULL_RTX, 0, OPTAB_WIDEN);
4062 tem = expand_binop (compute_mode, sub_optab, tem, mask,
4063 NULL_RTX, 0, OPTAB_WIDEN);
4064 expand_inc (quotient, tem);
4065 tem = expand_binop (compute_mode, xor_optab, mask, op1,
4066 NULL_RTX, 0, OPTAB_WIDEN);
4067 tem = expand_binop (compute_mode, sub_optab, tem, mask,
4068 NULL_RTX, 0, OPTAB_WIDEN);
4069 expand_dec (remainder, tem);
4072 return gen_lowpart (mode, rem_flag ? remainder : quotient);
4080 if (target && GET_MODE (target) != compute_mode)
4085 /* Try to produce the remainder without producing the quotient.
4086 If we seem to have a divmod pattern that does not require widening,
4087 don't try widening here. We should really have a WIDEN argument
4088 to expand_twoval_binop, since what we'd really like to do here is
4089 1) try a mod insn in compute_mode
4090 2) try a divmod insn in compute_mode
4091 3) try a div insn in compute_mode and multiply-subtract to get
4093 4) try the same things with widening allowed. */
4095 = sign_expand_binop (compute_mode, umod_optab, smod_optab,
4098 ((optab2->handlers[compute_mode].insn_code
4099 != CODE_FOR_nothing)
4100 ? OPTAB_DIRECT : OPTAB_WIDEN));
4103 /* No luck there. Can we do remainder and divide at once
4104 without a library call? */
4105 remainder = gen_reg_rtx (compute_mode);
4106 if (! expand_twoval_binop ((unsignedp
4110 NULL_RTX, remainder, unsignedp))
4115 return gen_lowpart (mode, remainder);
4118 /* Produce the quotient. Try a quotient insn, but not a library call.
4119 If we have a divmod in this mode, use it in preference to widening
4120 the div (for this test we assume it will not fail). Note that optab2
4121 is set to the one of the two optabs that the call below will use. */
4123 = sign_expand_binop (compute_mode, udiv_optab, sdiv_optab,
4124 op0, op1, rem_flag ? NULL_RTX : target,
4126 ((optab2->handlers[compute_mode].insn_code
4127 != CODE_FOR_nothing)
4128 ? OPTAB_DIRECT : OPTAB_WIDEN));
4132 /* No luck there. Try a quotient-and-remainder insn,
4133 keeping the quotient alone. */
4134 quotient = gen_reg_rtx (compute_mode);
4135 if (! expand_twoval_binop (unsignedp ? udivmod_optab : sdivmod_optab,
4137 quotient, NULL_RTX, unsignedp))
4141 /* Still no luck. If we are not computing the remainder,
4142 use a library call for the quotient. */
4143 quotient = sign_expand_binop (compute_mode,
4144 udiv_optab, sdiv_optab,
4146 unsignedp, OPTAB_LIB_WIDEN);
4153 if (target && GET_MODE (target) != compute_mode)
4157 /* No divide instruction either. Use library for remainder. */
4158 remainder = sign_expand_binop (compute_mode, umod_optab, smod_optab,
4160 unsignedp, OPTAB_LIB_WIDEN);
4163 /* We divided. Now finish doing X - Y * (X / Y). */
4164 remainder = expand_mult (compute_mode, quotient, op1,
4165 NULL_RTX, unsignedp);
4166 remainder = expand_binop (compute_mode, sub_optab, op0,
4167 remainder, target, unsignedp,
4172 return gen_lowpart (mode, rem_flag ? remainder : quotient);
4175 /* Return a tree node with data type TYPE, describing the value of X.
4176 Usually this is an RTL_EXPR, if there is no obvious better choice.
4177 X may be an expression, however we only support those expressions
4178 generated by loop.c. */
4181 make_tree (tree type, rtx x)
4185 switch (GET_CODE (x))
4188 t = build_int_2 (INTVAL (x),
4189 (TYPE_UNSIGNED (type)
4190 && (GET_MODE_BITSIZE (TYPE_MODE (type))
4191 < HOST_BITS_PER_WIDE_INT))
4192 || INTVAL (x) >= 0 ? 0 : -1);
4193 TREE_TYPE (t) = type;
4197 if (GET_MODE (x) == VOIDmode)
4199 t = build_int_2 (CONST_DOUBLE_LOW (x), CONST_DOUBLE_HIGH (x));
4200 TREE_TYPE (t) = type;
4206 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
4207 t = build_real (type, d);
4218 units = CONST_VECTOR_NUNITS (x);
4220 /* Build a tree with vector elements. */
4221 for (i = units - 1; i >= 0; --i)
4223 elt = CONST_VECTOR_ELT (x, i);
4224 t = tree_cons (NULL_TREE, make_tree (type, elt), t);
4227 return build_vector (type, t);
4231 return fold (build (PLUS_EXPR, type, make_tree (type, XEXP (x, 0)),
4232 make_tree (type, XEXP (x, 1))));
4235 return fold (build (MINUS_EXPR, type, make_tree (type, XEXP (x, 0)),
4236 make_tree (type, XEXP (x, 1))));
4239 return fold (build1 (NEGATE_EXPR, type, make_tree (type, XEXP (x, 0))));
4242 return fold (build (MULT_EXPR, type, make_tree (type, XEXP (x, 0)),
4243 make_tree (type, XEXP (x, 1))));
4246 return fold (build (LSHIFT_EXPR, type, make_tree (type, XEXP (x, 0)),
4247 make_tree (type, XEXP (x, 1))));
4250 t = lang_hooks.types.unsigned_type (type);
4251 return fold (convert (type,
4252 build (RSHIFT_EXPR, t,
4253 make_tree (t, XEXP (x, 0)),
4254 make_tree (type, XEXP (x, 1)))));
4257 t = lang_hooks.types.signed_type (type);
4258 return fold (convert (type,
4259 build (RSHIFT_EXPR, t,
4260 make_tree (t, XEXP (x, 0)),
4261 make_tree (type, XEXP (x, 1)))));
4264 if (TREE_CODE (type) != REAL_TYPE)
4265 t = lang_hooks.types.signed_type (type);
4269 return fold (convert (type,
4270 build (TRUNC_DIV_EXPR, t,
4271 make_tree (t, XEXP (x, 0)),
4272 make_tree (t, XEXP (x, 1)))));
4274 t = lang_hooks.types.unsigned_type (type);
4275 return fold (convert (type,
4276 build (TRUNC_DIV_EXPR, t,
4277 make_tree (t, XEXP (x, 0)),
4278 make_tree (t, XEXP (x, 1)))));
4282 t = lang_hooks.types.type_for_mode (GET_MODE (XEXP (x, 0)),
4283 GET_CODE (x) == ZERO_EXTEND);
4284 return fold (convert (type, make_tree (t, XEXP (x, 0))));
4287 t = make_node (RTL_EXPR);
4288 TREE_TYPE (t) = type;
4290 /* If TYPE is a POINTER_TYPE, X might be Pmode with TYPE_MODE being
4291 ptr_mode. So convert. */
4292 if (POINTER_TYPE_P (type))
4293 x = convert_memory_address (TYPE_MODE (type), x);
4295 RTL_EXPR_RTL (t) = x;
4296 /* There are no insns to be output
4297 when this rtl_expr is used. */
4298 RTL_EXPR_SEQUENCE (t) = 0;
4303 /* Check whether the multiplication X * MULT + ADD overflows.
4304 X, MULT and ADD must be CONST_*.
4305 MODE is the machine mode for the computation.
4306 X and MULT must have mode MODE. ADD may have a different mode.
4307 So can X (defaults to same as MODE).
4308 UNSIGNEDP is nonzero to do unsigned multiplication. */
4311 const_mult_add_overflow_p (rtx x, rtx mult, rtx add, enum machine_mode mode, int unsignedp)
4313 tree type, mult_type, add_type, result;
4315 type = lang_hooks.types.type_for_mode (mode, unsignedp);
4317 /* In order to get a proper overflow indication from an unsigned
4318 type, we have to pretend that it's a sizetype. */
4322 mult_type = copy_node (type);
4323 TYPE_IS_SIZETYPE (mult_type) = 1;
4326 add_type = (GET_MODE (add) == VOIDmode ? mult_type
4327 : lang_hooks.types.type_for_mode (GET_MODE (add), unsignedp));
4329 result = fold (build (PLUS_EXPR, mult_type,
4330 fold (build (MULT_EXPR, mult_type,
4331 make_tree (mult_type, x),
4332 make_tree (mult_type, mult))),
4333 make_tree (add_type, add)));
4335 return TREE_CONSTANT_OVERFLOW (result);
4338 /* Return an rtx representing the value of X * MULT + ADD.
4339 TARGET is a suggestion for where to store the result (an rtx).
4340 MODE is the machine mode for the computation.
4341 X and MULT must have mode MODE. ADD may have a different mode.
4342 So can X (defaults to same as MODE).
4343 UNSIGNEDP is nonzero to do unsigned multiplication.
4344 This may emit insns. */
4347 expand_mult_add (rtx x, rtx target, rtx mult, rtx add, enum machine_mode mode,
4350 tree type = lang_hooks.types.type_for_mode (mode, unsignedp);
4351 tree add_type = (GET_MODE (add) == VOIDmode
4352 ? type: lang_hooks.types.type_for_mode (GET_MODE (add),
4354 tree result = fold (build (PLUS_EXPR, type,
4355 fold (build (MULT_EXPR, type,
4356 make_tree (type, x),
4357 make_tree (type, mult))),
4358 make_tree (add_type, add)));
4360 return expand_expr (result, target, VOIDmode, 0);
4363 /* Compute the logical-and of OP0 and OP1, storing it in TARGET
4364 and returning TARGET.
4366 If TARGET is 0, a pseudo-register or constant is returned. */
4369 expand_and (enum machine_mode mode, rtx op0, rtx op1, rtx target)
4373 if (GET_MODE (op0) == VOIDmode && GET_MODE (op1) == VOIDmode)
4374 tem = simplify_binary_operation (AND, mode, op0, op1);
4376 tem = expand_binop (mode, and_optab, op0, op1, target, 0, OPTAB_LIB_WIDEN);
4380 else if (tem != target)
4381 emit_move_insn (target, tem);
4385 /* Emit a store-flags instruction for comparison CODE on OP0 and OP1
4386 and storing in TARGET. Normally return TARGET.
4387 Return 0 if that cannot be done.
4389 MODE is the mode to use for OP0 and OP1 should they be CONST_INTs. If
4390 it is VOIDmode, they cannot both be CONST_INT.
4392 UNSIGNEDP is for the case where we have to widen the operands
4393 to perform the operation. It says to use zero-extension.
4395 NORMALIZEP is 1 if we should convert the result to be either zero
4396 or one. Normalize is -1 if we should convert the result to be
4397 either zero or -1. If NORMALIZEP is zero, the result will be left
4398 "raw" out of the scc insn. */
4401 emit_store_flag (rtx target, enum rtx_code code, rtx op0, rtx op1,
4402 enum machine_mode mode, int unsignedp, int normalizep)
4405 enum insn_code icode;
4406 enum machine_mode compare_mode;
4407 enum machine_mode target_mode = GET_MODE (target);
4409 rtx last = get_last_insn ();
4410 rtx pattern, comparison;
4412 /* ??? Ok to do this and then fail? */
4413 op0 = protect_from_queue (op0, 0);
4414 op1 = protect_from_queue (op1, 0);
4417 code = unsigned_condition (code);
4419 /* If one operand is constant, make it the second one. Only do this
4420 if the other operand is not constant as well. */
4422 if (swap_commutative_operands_p (op0, op1))
4427 code = swap_condition (code);
4430 if (mode == VOIDmode)
4431 mode = GET_MODE (op0);
4433 /* For some comparisons with 1 and -1, we can convert this to
4434 comparisons with zero. This will often produce more opportunities for
4435 store-flag insns. */
4440 if (op1 == const1_rtx)
4441 op1 = const0_rtx, code = LE;
4444 if (op1 == constm1_rtx)
4445 op1 = const0_rtx, code = LT;
4448 if (op1 == const1_rtx)
4449 op1 = const0_rtx, code = GT;
4452 if (op1 == constm1_rtx)
4453 op1 = const0_rtx, code = GE;
4456 if (op1 == const1_rtx)
4457 op1 = const0_rtx, code = NE;
4460 if (op1 == const1_rtx)
4461 op1 = const0_rtx, code = EQ;
4467 /* If we are comparing a double-word integer with zero, we can convert
4468 the comparison into one involving a single word. */
4469 if (GET_MODE_BITSIZE (mode) == BITS_PER_WORD * 2
4470 && GET_MODE_CLASS (mode) == MODE_INT
4471 && op1 == const0_rtx
4472 && (GET_CODE (op0) != MEM || ! MEM_VOLATILE_P (op0)))
4474 if (code == EQ || code == NE)
4476 rtx op00, op01, op0both;
4478 /* Do a logical OR of the two words and compare the result. */
4479 op00 = simplify_gen_subreg (word_mode, op0, mode, 0);
4480 op01 = simplify_gen_subreg (word_mode, op0, mode, UNITS_PER_WORD);
4481 op0both = expand_binop (word_mode, ior_optab, op00, op01,
4482 NULL_RTX, unsignedp, OPTAB_DIRECT);
4484 return emit_store_flag (target, code, op0both, op1, word_mode,
4485 unsignedp, normalizep);
4487 else if (code == LT || code == GE)
4491 /* If testing the sign bit, can just test on high word. */
4492 op0h = simplify_gen_subreg (word_mode, op0, mode,
4493 subreg_highpart_offset (word_mode, mode));
4494 return emit_store_flag (target, code, op0h, op1, word_mode,
4495 unsignedp, normalizep);
4499 /* From now on, we won't change CODE, so set ICODE now. */
4500 icode = setcc_gen_code[(int) code];
4502 /* If this is A < 0 or A >= 0, we can do this by taking the ones
4503 complement of A (for GE) and shifting the sign bit to the low bit. */
4504 if (op1 == const0_rtx && (code == LT || code == GE)
4505 && GET_MODE_CLASS (mode) == MODE_INT
4506 && (normalizep || STORE_FLAG_VALUE == 1
4507 || (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4508 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4509 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1)))))
4513 /* If the result is to be wider than OP0, it is best to convert it
4514 first. If it is to be narrower, it is *incorrect* to convert it
4516 if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (mode))
4518 op0 = protect_from_queue (op0, 0);
4519 op0 = convert_modes (target_mode, mode, op0, 0);
4523 if (target_mode != mode)
4527 op0 = expand_unop (mode, one_cmpl_optab, op0,
4528 ((STORE_FLAG_VALUE == 1 || normalizep)
4529 ? 0 : subtarget), 0);
4531 if (STORE_FLAG_VALUE == 1 || normalizep)
4532 /* If we are supposed to produce a 0/1 value, we want to do
4533 a logical shift from the sign bit to the low-order bit; for
4534 a -1/0 value, we do an arithmetic shift. */
4535 op0 = expand_shift (RSHIFT_EXPR, mode, op0,
4536 size_int (GET_MODE_BITSIZE (mode) - 1),
4537 subtarget, normalizep != -1);
4539 if (mode != target_mode)
4540 op0 = convert_modes (target_mode, mode, op0, 0);
4545 if (icode != CODE_FOR_nothing)
4547 insn_operand_predicate_fn pred;
4549 /* We think we may be able to do this with a scc insn. Emit the
4550 comparison and then the scc insn.
4552 compare_from_rtx may call emit_queue, which would be deleted below
4553 if the scc insn fails. So call it ourselves before setting LAST.
4554 Likewise for do_pending_stack_adjust. */
4557 do_pending_stack_adjust ();
4558 last = get_last_insn ();
4561 = compare_from_rtx (op0, op1, code, unsignedp, mode, NULL_RTX);
4562 if (GET_CODE (comparison) == CONST_INT)
4563 return (comparison == const0_rtx ? const0_rtx
4564 : normalizep == 1 ? const1_rtx
4565 : normalizep == -1 ? constm1_rtx
4568 /* The code of COMPARISON may not match CODE if compare_from_rtx
4569 decided to swap its operands and reverse the original code.
4571 We know that compare_from_rtx returns either a CONST_INT or
4572 a new comparison code, so it is safe to just extract the
4573 code from COMPARISON. */
4574 code = GET_CODE (comparison);
4576 /* Get a reference to the target in the proper mode for this insn. */
4577 compare_mode = insn_data[(int) icode].operand[0].mode;
4579 pred = insn_data[(int) icode].operand[0].predicate;
4580 if (preserve_subexpressions_p ()
4581 || ! (*pred) (subtarget, compare_mode))
4582 subtarget = gen_reg_rtx (compare_mode);
4584 pattern = GEN_FCN (icode) (subtarget);
4587 emit_insn (pattern);
4589 /* If we are converting to a wider mode, first convert to
4590 TARGET_MODE, then normalize. This produces better combining
4591 opportunities on machines that have a SIGN_EXTRACT when we are
4592 testing a single bit. This mostly benefits the 68k.
4594 If STORE_FLAG_VALUE does not have the sign bit set when
4595 interpreted in COMPARE_MODE, we can do this conversion as
4596 unsigned, which is usually more efficient. */
4597 if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (compare_mode))
4599 convert_move (target, subtarget,
4600 (GET_MODE_BITSIZE (compare_mode)
4601 <= HOST_BITS_PER_WIDE_INT)
4602 && 0 == (STORE_FLAG_VALUE
4603 & ((HOST_WIDE_INT) 1
4604 << (GET_MODE_BITSIZE (compare_mode) -1))));
4606 compare_mode = target_mode;
4611 /* If we want to keep subexpressions around, don't reuse our
4614 if (preserve_subexpressions_p ())
4617 /* Now normalize to the proper value in COMPARE_MODE. Sometimes
4618 we don't have to do anything. */
4619 if (normalizep == 0 || normalizep == STORE_FLAG_VALUE)
4621 /* STORE_FLAG_VALUE might be the most negative number, so write
4622 the comparison this way to avoid a compiler-time warning. */
4623 else if (- normalizep == STORE_FLAG_VALUE)
4624 op0 = expand_unop (compare_mode, neg_optab, op0, subtarget, 0);
4626 /* We don't want to use STORE_FLAG_VALUE < 0 below since this
4627 makes it hard to use a value of just the sign bit due to
4628 ANSI integer constant typing rules. */
4629 else if (GET_MODE_BITSIZE (compare_mode) <= HOST_BITS_PER_WIDE_INT
4630 && (STORE_FLAG_VALUE
4631 & ((HOST_WIDE_INT) 1
4632 << (GET_MODE_BITSIZE (compare_mode) - 1))))
4633 op0 = expand_shift (RSHIFT_EXPR, compare_mode, op0,
4634 size_int (GET_MODE_BITSIZE (compare_mode) - 1),
4635 subtarget, normalizep == 1);
4636 else if (STORE_FLAG_VALUE & 1)
4638 op0 = expand_and (compare_mode, op0, const1_rtx, subtarget);
4639 if (normalizep == -1)
4640 op0 = expand_unop (compare_mode, neg_optab, op0, op0, 0);
4645 /* If we were converting to a smaller mode, do the
4647 if (target_mode != compare_mode)
4649 convert_move (target, op0, 0);
4657 delete_insns_since (last);
4659 /* If expensive optimizations, use different pseudo registers for each
4660 insn, instead of reusing the same pseudo. This leads to better CSE,
4661 but slows down the compiler, since there are more pseudos */
4662 subtarget = (!flag_expensive_optimizations
4663 && (target_mode == mode)) ? target : NULL_RTX;
4665 /* If we reached here, we can't do this with a scc insn. However, there
4666 are some comparisons that can be done directly. For example, if
4667 this is an equality comparison of integers, we can try to exclusive-or
4668 (or subtract) the two operands and use a recursive call to try the
4669 comparison with zero. Don't do any of these cases if branches are
4673 && GET_MODE_CLASS (mode) == MODE_INT && (code == EQ || code == NE)
4674 && op1 != const0_rtx)
4676 tem = expand_binop (mode, xor_optab, op0, op1, subtarget, 1,
4680 tem = expand_binop (mode, sub_optab, op0, op1, subtarget, 1,
4683 tem = emit_store_flag (target, code, tem, const0_rtx,
4684 mode, unsignedp, normalizep);
4686 delete_insns_since (last);
4690 /* Some other cases we can do are EQ, NE, LE, and GT comparisons with
4691 the constant zero. Reject all other comparisons at this point. Only
4692 do LE and GT if branches are expensive since they are expensive on
4693 2-operand machines. */
4695 if (BRANCH_COST == 0
4696 || GET_MODE_CLASS (mode) != MODE_INT || op1 != const0_rtx
4697 || (code != EQ && code != NE
4698 && (BRANCH_COST <= 1 || (code != LE && code != GT))))
4701 /* See what we need to return. We can only return a 1, -1, or the
4704 if (normalizep == 0)
4706 if (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4707 normalizep = STORE_FLAG_VALUE;
4709 else if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4710 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4711 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1)))
4717 /* Try to put the result of the comparison in the sign bit. Assume we can't
4718 do the necessary operation below. */
4722 /* To see if A <= 0, compute (A | (A - 1)). A <= 0 iff that result has
4723 the sign bit set. */
4727 /* This is destructive, so SUBTARGET can't be OP0. */
4728 if (rtx_equal_p (subtarget, op0))
4731 tem = expand_binop (mode, sub_optab, op0, const1_rtx, subtarget, 0,
4734 tem = expand_binop (mode, ior_optab, op0, tem, subtarget, 0,
4738 /* To see if A > 0, compute (((signed) A) << BITS) - A, where BITS is the
4739 number of bits in the mode of OP0, minus one. */
4743 if (rtx_equal_p (subtarget, op0))
4746 tem = expand_shift (RSHIFT_EXPR, mode, op0,
4747 size_int (GET_MODE_BITSIZE (mode) - 1),
4749 tem = expand_binop (mode, sub_optab, tem, op0, subtarget, 0,
4753 if (code == EQ || code == NE)
4755 /* For EQ or NE, one way to do the comparison is to apply an operation
4756 that converts the operand into a positive number if it is nonzero
4757 or zero if it was originally zero. Then, for EQ, we subtract 1 and
4758 for NE we negate. This puts the result in the sign bit. Then we
4759 normalize with a shift, if needed.
4761 Two operations that can do the above actions are ABS and FFS, so try
4762 them. If that doesn't work, and MODE is smaller than a full word,
4763 we can use zero-extension to the wider mode (an unsigned conversion)
4764 as the operation. */
4766 /* Note that ABS doesn't yield a positive number for INT_MIN, but
4767 that is compensated by the subsequent overflow when subtracting
4770 if (abs_optab->handlers[mode].insn_code != CODE_FOR_nothing)
4771 tem = expand_unop (mode, abs_optab, op0, subtarget, 1);
4772 else if (ffs_optab->handlers[mode].insn_code != CODE_FOR_nothing)
4773 tem = expand_unop (mode, ffs_optab, op0, subtarget, 1);
4774 else if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
4776 op0 = protect_from_queue (op0, 0);
4777 tem = convert_modes (word_mode, mode, op0, 1);
4784 tem = expand_binop (mode, sub_optab, tem, const1_rtx, subtarget,
4787 tem = expand_unop (mode, neg_optab, tem, subtarget, 0);
4790 /* If we couldn't do it that way, for NE we can "or" the two's complement
4791 of the value with itself. For EQ, we take the one's complement of
4792 that "or", which is an extra insn, so we only handle EQ if branches
4795 if (tem == 0 && (code == NE || BRANCH_COST > 1))
4797 if (rtx_equal_p (subtarget, op0))
4800 tem = expand_unop (mode, neg_optab, op0, subtarget, 0);
4801 tem = expand_binop (mode, ior_optab, tem, op0, subtarget, 0,
4804 if (tem && code == EQ)
4805 tem = expand_unop (mode, one_cmpl_optab, tem, subtarget, 0);
4809 if (tem && normalizep)
4810 tem = expand_shift (RSHIFT_EXPR, mode, tem,
4811 size_int (GET_MODE_BITSIZE (mode) - 1),
4812 subtarget, normalizep == 1);
4816 if (GET_MODE (tem) != target_mode)
4818 convert_move (target, tem, 0);
4821 else if (!subtarget)
4823 emit_move_insn (target, tem);
4828 delete_insns_since (last);
4833 /* Like emit_store_flag, but always succeeds. */
4836 emit_store_flag_force (rtx target, enum rtx_code code, rtx op0, rtx op1,
4837 enum machine_mode mode, int unsignedp, int normalizep)
4841 /* First see if emit_store_flag can do the job. */
4842 tem = emit_store_flag (target, code, op0, op1, mode, unsignedp, normalizep);
4846 if (normalizep == 0)
4849 /* If this failed, we have to do this with set/compare/jump/set code. */
4851 if (GET_CODE (target) != REG
4852 || reg_mentioned_p (target, op0) || reg_mentioned_p (target, op1))
4853 target = gen_reg_rtx (GET_MODE (target));
4855 emit_move_insn (target, const1_rtx);
4856 label = gen_label_rtx ();
4857 do_compare_rtx_and_jump (op0, op1, code, unsignedp, mode, NULL_RTX,
4860 emit_move_insn (target, const0_rtx);
4866 /* Perform possibly multi-word comparison and conditional jump to LABEL
4867 if ARG1 OP ARG2 true where ARG1 and ARG2 are of mode MODE
4869 The algorithm is based on the code in expr.c:do_jump.
4871 Note that this does not perform a general comparison. Only variants
4872 generated within expmed.c are correctly handled, others abort (but could
4873 be handled if needed). */
4876 do_cmp_and_jump (rtx arg1, rtx arg2, enum rtx_code op, enum machine_mode mode,
4879 /* If this mode is an integer too wide to compare properly,
4880 compare word by word. Rely on cse to optimize constant cases. */
4882 if (GET_MODE_CLASS (mode) == MODE_INT
4883 && ! can_compare_p (op, mode, ccp_jump))
4885 rtx label2 = gen_label_rtx ();
4890 do_jump_by_parts_greater_rtx (mode, 1, arg2, arg1, label2, label);
4894 do_jump_by_parts_greater_rtx (mode, 1, arg1, arg2, label, label2);
4898 do_jump_by_parts_greater_rtx (mode, 0, arg2, arg1, label2, label);
4902 do_jump_by_parts_greater_rtx (mode, 0, arg1, arg2, label2, label);
4906 do_jump_by_parts_greater_rtx (mode, 0, arg2, arg1, label, label2);
4909 /* do_jump_by_parts_equality_rtx compares with zero. Luckily
4910 that's the only equality operations we do */
4912 if (arg2 != const0_rtx || mode != GET_MODE(arg1))
4914 do_jump_by_parts_equality_rtx (arg1, label2, label);
4918 if (arg2 != const0_rtx || mode != GET_MODE(arg1))
4920 do_jump_by_parts_equality_rtx (arg1, label, label2);
4927 emit_label (label2);
4930 emit_cmp_and_jump_insns (arg1, arg2, op, NULL_RTX, mode, 0, label);