1 /* Medium-level subroutines: convert bit-field store and extract
2 and shifts, multiplies and divides to rtl instructions.
3 Copyright (C) 1987, 88, 89, 92, 93, 1994 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
26 #include "insn-flags.h"
27 #include "insn-codes.h"
28 #include "insn-config.h"
33 static void store_fixed_bit_field PROTO((rtx, int, int, int, rtx, int));
34 static void store_split_bit_field PROTO((rtx, int, int, rtx, int));
35 static rtx extract_fixed_bit_field PROTO((enum machine_mode, rtx, int,
36 int, int, rtx, int, int));
37 static rtx mask_rtx PROTO((enum machine_mode, int,
39 static rtx lshift_value PROTO((enum machine_mode, rtx,
41 static rtx extract_split_bit_field PROTO((rtx, int, int, int, int));
43 #define CEIL(x,y) (((x) + (y) - 1) / (y))
45 /* Non-zero means divides or modulus operations are relatively cheap for
46 powers of two, so don't use branches; emit the operation instead.
47 Usually, this will mean that the MD file will emit non-branch
50 static int sdiv_pow2_cheap, smod_pow2_cheap;
52 #ifndef SLOW_UNALIGNED_ACCESS
53 #define SLOW_UNALIGNED_ACCESS STRICT_ALIGNMENT
56 /* For compilers that support multiple targets with different word sizes,
57 MAX_BITS_PER_WORD contains the biggest value of BITS_PER_WORD. An example
58 is the H8/300(H) compiler. */
60 #ifndef MAX_BITS_PER_WORD
61 #define MAX_BITS_PER_WORD BITS_PER_WORD
64 /* Cost of various pieces of RTL. */
65 static int add_cost, negate_cost, zero_cost;
66 static int shift_cost[MAX_BITS_PER_WORD];
67 static int shiftadd_cost[MAX_BITS_PER_WORD];
68 static int shiftsub_cost[MAX_BITS_PER_WORD];
74 /* This is "some random pseudo register" for purposes of calling recog
75 to see what insns exist. */
76 rtx reg = gen_rtx (REG, word_mode, 10000);
77 rtx shift_insn, shiftadd_insn, shiftsub_insn;
83 /* Since we are on the permanent obstack, we must be sure we save this
84 spot AFTER we call start_sequence, since it will reuse the rtl it
87 free_point = (char *) oballoc (0);
89 zero_cost = rtx_cost (const0_rtx, 0);
90 add_cost = rtx_cost (gen_rtx (PLUS, word_mode, reg, reg), SET);
92 shift_insn = emit_insn (gen_rtx (SET, VOIDmode, reg,
93 gen_rtx (ASHIFT, word_mode, reg,
96 shiftadd_insn = emit_insn (gen_rtx (SET, VOIDmode, reg,
97 gen_rtx (PLUS, word_mode,
98 gen_rtx (MULT, word_mode,
102 shiftsub_insn = emit_insn (gen_rtx (SET, VOIDmode, reg,
103 gen_rtx (MINUS, word_mode,
104 gen_rtx (MULT, word_mode,
111 shiftadd_cost[0] = shiftsub_cost[0] = add_cost;
113 for (m = 1; m < BITS_PER_WORD; m++)
115 shift_cost[m] = shiftadd_cost[m] = shiftsub_cost[m] = 32000;
117 XEXP (SET_SRC (PATTERN (shift_insn)), 1) = GEN_INT (m);
118 if (recog (PATTERN (shift_insn), shift_insn, &dummy) >= 0)
119 shift_cost[m] = rtx_cost (SET_SRC (PATTERN (shift_insn)), SET);
121 XEXP (XEXP (SET_SRC (PATTERN (shiftadd_insn)), 0), 1)
122 = GEN_INT ((HOST_WIDE_INT) 1 << m);
123 if (recog (PATTERN (shiftadd_insn), shiftadd_insn, &dummy) >= 0)
124 shiftadd_cost[m] = rtx_cost (SET_SRC (PATTERN (shiftadd_insn)), SET);
126 XEXP (XEXP (SET_SRC (PATTERN (shiftsub_insn)), 0), 1)
127 = GEN_INT ((HOST_WIDE_INT) 1 << m);
128 if (recog (PATTERN (shiftsub_insn), shiftsub_insn, &dummy) >= 0)
129 shiftsub_cost[m] = rtx_cost (SET_SRC (PATTERN (shiftsub_insn)), SET);
132 negate_cost = rtx_cost (gen_rtx (NEG, word_mode, reg), SET);
135 = (rtx_cost (gen_rtx (DIV, word_mode, reg, GEN_INT (32)), SET)
138 = (rtx_cost (gen_rtx (MOD, word_mode, reg, GEN_INT (32)), SET)
141 /* Free the objects we just allocated. */
146 /* Return an rtx representing minus the value of X.
147 MODE is the intended mode of the result,
148 useful if X is a CONST_INT. */
152 enum machine_mode mode;
155 if (GET_CODE (x) == CONST_INT)
157 HOST_WIDE_INT val = - INTVAL (x);
158 if (GET_MODE_BITSIZE (mode) < HOST_BITS_PER_WIDE_INT)
160 /* Sign extend the value from the bits that are significant. */
161 if (val & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1)))
162 val |= (HOST_WIDE_INT) (-1) << GET_MODE_BITSIZE (mode);
164 val &= ((HOST_WIDE_INT) 1 << GET_MODE_BITSIZE (mode)) - 1;
166 return GEN_INT (val);
169 return expand_unop (GET_MODE (x), neg_optab, x, NULL_RTX, 0);
172 /* Generate code to store value from rtx VALUE
173 into a bit-field within structure STR_RTX
174 containing BITSIZE bits starting at bit BITNUM.
175 FIELDMODE is the machine-mode of the FIELD_DECL node for this field.
176 ALIGN is the alignment that STR_RTX is known to have, measured in bytes.
177 TOTAL_SIZE is the size of the structure in bytes, or -1 if varying. */
179 /* ??? Note that there are two different ideas here for how
180 to determine the size to count bits within, for a register.
181 One is BITS_PER_WORD, and the other is the size of operand 3
182 of the insv pattern. (The latter assumes that an n-bit machine
183 will be able to insert bit fields up to n bits wide.)
184 It isn't certain that either of these is right.
185 extract_bit_field has the same quandary. */
188 store_bit_field (str_rtx, bitsize, bitnum, fieldmode, value, align, total_size)
190 register int bitsize;
192 enum machine_mode fieldmode;
197 int unit = (GET_CODE (str_rtx) == MEM) ? BITS_PER_UNIT : BITS_PER_WORD;
198 register int offset = bitnum / unit;
199 register int bitpos = bitnum % unit;
200 register rtx op0 = str_rtx;
202 if (GET_CODE (str_rtx) == MEM && ! MEM_IN_STRUCT_P (str_rtx))
205 /* Discount the part of the structure before the desired byte.
206 We need to know how many bytes are safe to reference after it. */
208 total_size -= (bitpos / BIGGEST_ALIGNMENT
209 * (BIGGEST_ALIGNMENT / BITS_PER_UNIT));
211 while (GET_CODE (op0) == SUBREG)
213 /* The following line once was done only if WORDS_BIG_ENDIAN,
214 but I think that is a mistake. WORDS_BIG_ENDIAN is
215 meaningful at a much higher level; when structures are copied
216 between memory and regs, the higher-numbered regs
217 always get higher addresses. */
218 offset += SUBREG_WORD (op0);
219 /* We used to adjust BITPOS here, but now we do the whole adjustment
220 right after the loop. */
221 op0 = SUBREG_REG (op0);
225 /* If OP0 is a register, BITPOS must count within a word.
226 But as we have it, it counts within whatever size OP0 now has.
227 On a bigendian machine, these are not the same, so convert. */
228 if (GET_CODE (op0) != MEM && unit > GET_MODE_BITSIZE (GET_MODE (op0)))
229 bitpos += unit - GET_MODE_BITSIZE (GET_MODE (op0));
232 value = protect_from_queue (value, 0);
235 value = force_not_mem (value);
237 /* Note that the adjustment of BITPOS above has no effect on whether
238 BITPOS is 0 in a REG bigger than a word. */
239 if (GET_MODE_SIZE (fieldmode) >= UNITS_PER_WORD
240 && (GET_CODE (op0) != MEM
241 || ! SLOW_UNALIGNED_ACCESS
242 || (offset * BITS_PER_UNIT % bitsize == 0
243 && align % GET_MODE_SIZE (fieldmode) == 0))
244 && bitpos == 0 && bitsize == GET_MODE_BITSIZE (fieldmode))
246 /* Storing in a full-word or multi-word field in a register
247 can be done with just SUBREG. */
248 if (GET_MODE (op0) != fieldmode)
250 if (GET_CODE (op0) == REG)
251 op0 = gen_rtx (SUBREG, fieldmode, op0, offset);
253 op0 = change_address (op0, fieldmode,
254 plus_constant (XEXP (op0, 0), offset));
256 emit_move_insn (op0, value);
260 /* Storing an lsb-aligned field in a register
261 can be done with a movestrict instruction. */
263 if (GET_CODE (op0) != MEM
265 && bitpos + bitsize == unit
269 && bitsize == GET_MODE_BITSIZE (fieldmode)
270 && (GET_MODE (op0) == fieldmode
271 || (movstrict_optab->handlers[(int) fieldmode].insn_code
272 != CODE_FOR_nothing)))
274 /* Get appropriate low part of the value being stored. */
275 if (GET_CODE (value) == CONST_INT || GET_CODE (value) == REG)
276 value = gen_lowpart (fieldmode, value);
277 else if (!(GET_CODE (value) == SYMBOL_REF
278 || GET_CODE (value) == LABEL_REF
279 || GET_CODE (value) == CONST))
280 value = convert_to_mode (fieldmode, value, 0);
282 if (GET_MODE (op0) == fieldmode)
283 emit_move_insn (op0, value);
286 int icode = movstrict_optab->handlers[(int) fieldmode].insn_code;
287 if(! (*insn_operand_predicate[icode][1]) (value, fieldmode))
288 value = copy_to_mode_reg (fieldmode, value);
289 emit_insn (GEN_FCN (icode)
290 (gen_rtx (SUBREG, fieldmode, op0, offset), value));
295 /* Handle fields bigger than a word. */
297 if (bitsize > BITS_PER_WORD)
299 /* Here we transfer the words of the field
300 in the order least significant first.
301 This is because the most significant word is the one which may
302 be less than full. */
304 int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD;
307 /* This is the mode we must force value to, so that there will be enough
308 subwords to extract. Note that fieldmode will often (always?) be
309 VOIDmode, because that is what store_field uses to indicate that this
310 is a bit field, but passing VOIDmode to operand_subword_force will
311 result in an abort. */
312 fieldmode = mode_for_size (nwords * BITS_PER_WORD, MODE_INT, 0);
314 for (i = 0; i < nwords; i++)
316 /* If I is 0, use the low-order word in both field and target;
317 if I is 1, use the next to lowest word; and so on. */
318 int wordnum = (WORDS_BIG_ENDIAN ? nwords - i - 1 : i);
319 int bit_offset = (WORDS_BIG_ENDIAN
320 ? MAX (bitsize - (i + 1) * BITS_PER_WORD, 0)
321 : i * BITS_PER_WORD);
322 store_bit_field (op0, MIN (BITS_PER_WORD,
323 bitsize - i * BITS_PER_WORD),
324 bitnum + bit_offset, word_mode,
325 operand_subword_force (value, wordnum,
326 (GET_MODE (value) == VOIDmode
328 : GET_MODE (value))),
334 /* From here on we can assume that the field to be stored in is
335 a full-word (whatever type that is), since it is shorter than a word. */
337 /* OFFSET is the number of words or bytes (UNIT says which)
338 from STR_RTX to the first word or byte containing part of the field. */
340 if (GET_CODE (op0) == REG)
343 || GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD)
344 op0 = gen_rtx (SUBREG, TYPE_MODE (type_for_size (BITS_PER_WORD, 0)),
350 op0 = protect_from_queue (op0, 1);
353 /* If VALUE is a floating-point mode, access it as an integer of the
354 corresponding size. This can occur on a machine with 64 bit registers
355 that uses SFmode for float. This can also occur for unaligned float
357 if (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT)
359 if (GET_CODE (value) != REG)
360 value = copy_to_reg (value);
361 value = gen_rtx (SUBREG, word_mode, value, 0);
364 /* Now OFFSET is nonzero only if OP0 is memory
365 and is therefore always measured in bytes. */
369 && !(bitsize == 1 && GET_CODE (value) == CONST_INT)
370 /* Ensure insv's size is wide enough for this field. */
371 && (GET_MODE_BITSIZE (insn_operand_mode[(int) CODE_FOR_insv][3])
373 && ! ((GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
375 > GET_MODE_BITSIZE (insn_operand_mode[(int) CODE_FOR_insv][3]))))
377 int xbitpos = bitpos;
380 rtx last = get_last_insn ();
382 enum machine_mode maxmode
383 = insn_operand_mode[(int) CODE_FOR_insv][3];
385 int save_volatile_ok = volatile_ok;
388 /* If this machine's insv can only insert into a register, or if we
389 are to force MEMs into a register, copy OP0 into a register and
390 save it back later. */
391 if (GET_CODE (op0) == MEM
393 || ! ((*insn_operand_predicate[(int) CODE_FOR_insv][0])
397 enum machine_mode bestmode;
399 /* Get the mode to use for inserting into this field. If OP0 is
400 BLKmode, get the smallest mode consistent with the alignment. If
401 OP0 is a non-BLKmode object that is no wider than MAXMODE, use its
402 mode. Otherwise, use the smallest mode containing the field. */
404 if (GET_MODE (op0) == BLKmode
405 || GET_MODE_SIZE (GET_MODE (op0)) > GET_MODE_SIZE (maxmode))
407 = get_best_mode (bitsize, bitnum, align * BITS_PER_UNIT, maxmode,
408 MEM_VOLATILE_P (op0));
410 bestmode = GET_MODE (op0);
412 if (bestmode == VOIDmode
413 || (STRICT_ALIGNMENT && GET_MODE_SIZE (bestmode) > align))
416 /* Adjust address to point to the containing unit of that mode. */
417 unit = GET_MODE_BITSIZE (bestmode);
418 /* Compute offset as multiple of this unit, counting in bytes. */
419 offset = (bitnum / unit) * GET_MODE_SIZE (bestmode);
420 bitpos = bitnum % unit;
421 op0 = change_address (op0, bestmode,
422 plus_constant (XEXP (op0, 0), offset));
424 /* Fetch that unit, store the bitfield in it, then store the unit. */
425 tempreg = copy_to_reg (op0);
426 store_bit_field (tempreg, bitsize, bitpos, fieldmode, value,
428 emit_move_insn (op0, tempreg);
431 volatile_ok = save_volatile_ok;
433 /* Add OFFSET into OP0's address. */
434 if (GET_CODE (xop0) == MEM)
435 xop0 = change_address (xop0, byte_mode,
436 plus_constant (XEXP (xop0, 0), offset));
438 /* If xop0 is a register, we need it in MAXMODE
439 to make it acceptable to the format of insv. */
440 if (GET_CODE (xop0) == SUBREG)
441 /* We can't just change the mode, because this might clobber op0,
442 and we will need the original value of op0 if insv fails. */
443 xop0 = gen_rtx (SUBREG, maxmode, SUBREG_REG (xop0), SUBREG_WORD (xop0));
444 if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode)
445 xop0 = gen_rtx (SUBREG, maxmode, xop0, 0);
447 /* On big-endian machines, we count bits from the most significant.
448 If the bit field insn does not, we must invert. */
450 #if BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN
451 xbitpos = unit - bitsize - xbitpos;
453 /* We have been counting XBITPOS within UNIT.
454 Count instead within the size of the register. */
456 if (GET_CODE (xop0) != MEM)
457 xbitpos += GET_MODE_BITSIZE (maxmode) - unit;
459 unit = GET_MODE_BITSIZE (maxmode);
461 /* Convert VALUE to maxmode (which insv insn wants) in VALUE1. */
463 if (GET_MODE (value) != maxmode)
465 if (GET_MODE_BITSIZE (GET_MODE (value)) >= bitsize)
467 /* Optimization: Don't bother really extending VALUE
468 if it has all the bits we will actually use. However,
469 if we must narrow it, be sure we do it correctly. */
471 if (GET_MODE_SIZE (GET_MODE (value)) < GET_MODE_SIZE (maxmode))
473 /* Avoid making subreg of a subreg, or of a mem. */
474 if (GET_CODE (value1) != REG)
475 value1 = copy_to_reg (value1);
476 value1 = gen_rtx (SUBREG, maxmode, value1, 0);
479 value1 = gen_lowpart (maxmode, value1);
481 else if (!CONSTANT_P (value))
482 /* Parse phase is supposed to make VALUE's data type
483 match that of the component reference, which is a type
484 at least as wide as the field; so VALUE should have
485 a mode that corresponds to that type. */
489 /* If this machine's insv insists on a register,
490 get VALUE1 into a register. */
491 if (! ((*insn_operand_predicate[(int) CODE_FOR_insv][3])
493 value1 = force_reg (maxmode, value1);
495 pat = gen_insv (xop0, GEN_INT (bitsize), GEN_INT (xbitpos), value1);
500 delete_insns_since (last);
501 store_fixed_bit_field (op0, offset, bitsize, bitpos, value, align);
507 /* Insv is not available; store using shifts and boolean ops. */
508 store_fixed_bit_field (op0, offset, bitsize, bitpos, value, align);
512 /* Use shifts and boolean operations to store VALUE
513 into a bit field of width BITSIZE
514 in a memory location specified by OP0 except offset by OFFSET bytes.
515 (OFFSET must be 0 if OP0 is a register.)
516 The field starts at position BITPOS within the byte.
517 (If OP0 is a register, it may be a full word or a narrower mode,
518 but BITPOS still counts within a full word,
519 which is significant on bigendian machines.)
520 STRUCT_ALIGN is the alignment the structure is known to have (in bytes).
522 Note that protect_from_queue has already been done on OP0 and VALUE. */
525 store_fixed_bit_field (op0, offset, bitsize, bitpos, value, struct_align)
527 register int offset, bitsize, bitpos;
531 register enum machine_mode mode;
532 int total_bits = BITS_PER_WORD;
537 /* There is a case not handled here:
538 a structure with a known alignment of just a halfword
539 and a field split across two aligned halfwords within the structure.
540 Or likewise a structure with a known alignment of just a byte
541 and a field split across two bytes.
542 Such cases are not supposed to be able to occur. */
544 if (GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
548 /* Special treatment for a bit field split across two registers. */
549 if (bitsize + bitpos > BITS_PER_WORD)
551 store_split_bit_field (op0, bitsize, bitpos,
552 value, BITS_PER_WORD);
558 /* Get the proper mode to use for this field. We want a mode that
559 includes the entire field. If such a mode would be larger than
560 a word, we won't be doing the extraction the normal way. */
562 mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT,
563 struct_align * BITS_PER_UNIT, word_mode,
564 GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0));
566 if (mode == VOIDmode)
568 /* The only way this should occur is if the field spans word
570 store_split_bit_field (op0,
571 bitsize, bitpos + offset * BITS_PER_UNIT,
572 value, struct_align);
576 total_bits = GET_MODE_BITSIZE (mode);
578 /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to
579 be be in the range 0 to total_bits-1, and put any excess bytes in
581 if (bitpos >= total_bits)
583 offset += (bitpos / total_bits) * (total_bits / BITS_PER_UNIT);
584 bitpos -= ((bitpos / total_bits) * (total_bits / BITS_PER_UNIT)
588 /* Get ref to an aligned byte, halfword, or word containing the field.
589 Adjust BITPOS to be position within a word,
590 and OFFSET to be the offset of that word.
591 Then alter OP0 to refer to that word. */
592 bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT;
593 offset -= (offset % (total_bits / BITS_PER_UNIT));
594 op0 = change_address (op0, mode,
595 plus_constant (XEXP (op0, 0), offset));
598 mode = GET_MODE (op0);
600 /* Now MODE is either some integral mode for a MEM as OP0,
601 or is a full-word for a REG as OP0. TOTAL_BITS corresponds.
602 The bit field is contained entirely within OP0.
603 BITPOS is the starting bit number within OP0.
604 (OP0's mode may actually be narrower than MODE.) */
607 /* BITPOS is the distance between our msb
608 and that of the containing datum.
609 Convert it to the distance from the lsb. */
611 bitpos = total_bits - bitsize - bitpos;
613 /* Now BITPOS is always the distance between our lsb
616 /* Shift VALUE left by BITPOS bits. If VALUE is not constant,
617 we must first convert its mode to MODE. */
619 if (GET_CODE (value) == CONST_INT)
621 register HOST_WIDE_INT v = INTVAL (value);
623 if (bitsize < HOST_BITS_PER_WIDE_INT)
624 v &= ((HOST_WIDE_INT) 1 << bitsize) - 1;
628 else if ((bitsize < HOST_BITS_PER_WIDE_INT
629 && v == ((HOST_WIDE_INT) 1 << bitsize) - 1)
630 || (bitsize == HOST_BITS_PER_WIDE_INT && v == -1))
633 value = lshift_value (mode, value, bitpos, bitsize);
637 int must_and = (GET_MODE_BITSIZE (GET_MODE (value)) != bitsize
638 && bitpos + bitsize != GET_MODE_BITSIZE (mode));
640 if (GET_MODE (value) != mode)
642 if ((GET_CODE (value) == REG || GET_CODE (value) == SUBREG)
643 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (value)))
644 value = gen_lowpart (mode, value);
646 value = convert_to_mode (mode, value, 1);
650 value = expand_binop (mode, and_optab, value,
651 mask_rtx (mode, 0, bitsize, 0),
652 NULL_RTX, 1, OPTAB_LIB_WIDEN);
654 value = expand_shift (LSHIFT_EXPR, mode, value,
655 build_int_2 (bitpos, 0), NULL_RTX, 1);
658 /* Now clear the chosen bits in OP0,
659 except that if VALUE is -1 we need not bother. */
661 subtarget = (GET_CODE (op0) == REG || ! flag_force_mem) ? op0 : 0;
665 temp = expand_binop (mode, and_optab, op0,
666 mask_rtx (mode, bitpos, bitsize, 1),
667 subtarget, 1, OPTAB_LIB_WIDEN);
673 /* Now logical-or VALUE into OP0, unless it is zero. */
676 temp = expand_binop (mode, ior_optab, temp, value,
677 subtarget, 1, OPTAB_LIB_WIDEN);
679 emit_move_insn (op0, temp);
682 /* Store a bit field that is split across multiple accessible memory objects.
684 OP0 is the REG, SUBREG or MEM rtx for the first of the objects.
685 BITSIZE is the field width; BITPOS the position of its first bit
687 VALUE is the value to store.
688 ALIGN is the known alignment of OP0, measured in bytes.
689 This is also the size of the memory objects to be used.
691 This does not yet handle fields wider than BITS_PER_WORD. */
694 store_split_bit_field (op0, bitsize, bitpos, value, align)
703 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
705 if (GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
706 unit = BITS_PER_WORD;
708 unit = MIN (align * BITS_PER_UNIT, BITS_PER_WORD);
710 /* If VALUE is a constant other than a CONST_INT, get it into a register in
711 WORD_MODE. If we can do this using gen_lowpart_common, do so. Note
712 that VALUE might be a floating-point constant. */
713 if (CONSTANT_P (value) && GET_CODE (value) != CONST_INT)
715 rtx word = gen_lowpart_common (word_mode, value);
717 if (word && (value != word))
720 value = gen_lowpart_common (word_mode,
721 force_reg (GET_MODE (value), value));
724 while (bitsdone < bitsize)
731 offset = (bitpos + bitsdone) / unit;
732 thispos = (bitpos + bitsdone) % unit;
734 /* THISSIZE must not overrun a word boundary. Otherwise,
735 store_fixed_bit_field will call us again, and we will mutually
737 thissize = MIN (bitsize - bitsdone, BITS_PER_WORD);
738 thissize = MIN (thissize, unit - thispos);
741 /* Fetch successively less significant portions. */
742 if (GET_CODE (value) == CONST_INT)
743 part = GEN_INT (((unsigned HOST_WIDE_INT) (INTVAL (value))
744 >> (bitsize - bitsdone - thissize))
745 & (((HOST_WIDE_INT) 1 << thissize) - 1));
748 /* The args are chosen so that the last part
751 /* If the value isn't in memory, then it must be right aligned
752 if a register, so skip past the padding on the left. If it
753 is in memory, then there is no padding on the left. */
754 if (GET_CODE (value) != MEM)
755 bit_offset = BITS_PER_WORD - bitsize;
756 part = extract_fixed_bit_field (word_mode, value, 0, thissize,
757 bit_offset + bitsdone,
761 /* Fetch successively more significant portions. */
762 if (GET_CODE (value) == CONST_INT)
763 part = GEN_INT (((unsigned HOST_WIDE_INT) (INTVAL (value)) >> bitsdone)
764 & (((HOST_WIDE_INT) 1 << thissize) - 1));
766 part = extract_fixed_bit_field (word_mode, value, 0, thissize,
767 bitsdone, NULL_RTX, 1, align);
770 /* If OP0 is a register, then handle OFFSET here.
772 When handling multiword bitfields, extract_bit_field may pass
773 down a word_mode SUBREG of a larger REG for a bitfield that actually
774 crosses a word boundary. Thus, for a SUBREG, we must find
775 the current word starting from the base register. */
776 if (GET_CODE (op0) == SUBREG)
778 word = operand_subword_force (SUBREG_REG (op0),
779 SUBREG_WORD (op0) + offset,
780 GET_MODE (SUBREG_REG (op0)));
783 else if (GET_CODE (op0) == REG)
785 word = operand_subword_force (op0, offset, GET_MODE (op0));
791 /* OFFSET is in UNITs, and UNIT is in bits.
792 store_fixed_bit_field wants offset in bytes. */
793 store_fixed_bit_field (word, offset * unit / BITS_PER_UNIT,
794 thissize, thispos, part, align);
795 bitsdone += thissize;
799 /* Generate code to extract a byte-field from STR_RTX
800 containing BITSIZE bits, starting at BITNUM,
801 and put it in TARGET if possible (if TARGET is nonzero).
802 Regardless of TARGET, we return the rtx for where the value is placed.
805 STR_RTX is the structure containing the byte (a REG or MEM).
806 UNSIGNEDP is nonzero if this is an unsigned bit field.
807 MODE is the natural mode of the field value once extracted.
808 TMODE is the mode the caller would like the value to have;
809 but the value may be returned with type MODE instead.
811 ALIGN is the alignment that STR_RTX is known to have, measured in bytes.
812 TOTAL_SIZE is the size in bytes of the containing structure,
815 If a TARGET is specified and we can store in it at no extra cost,
816 we do so, and return TARGET.
817 Otherwise, we return a REG of mode TMODE or MODE, with TMODE preferred
818 if they are equally easy. */
821 extract_bit_field (str_rtx, bitsize, bitnum, unsignedp,
822 target, mode, tmode, align, total_size)
824 register int bitsize;
828 enum machine_mode mode, tmode;
832 int unit = (GET_CODE (str_rtx) == MEM) ? BITS_PER_UNIT : BITS_PER_WORD;
833 register int offset = bitnum / unit;
834 register int bitpos = bitnum % unit;
835 register rtx op0 = str_rtx;
836 rtx spec_target = target;
837 rtx spec_target_subreg = 0;
839 if (GET_CODE (str_rtx) == MEM && ! MEM_IN_STRUCT_P (str_rtx))
842 /* Discount the part of the structure before the desired byte.
843 We need to know how many bytes are safe to reference after it. */
845 total_size -= (bitpos / BIGGEST_ALIGNMENT
846 * (BIGGEST_ALIGNMENT / BITS_PER_UNIT));
848 if (tmode == VOIDmode)
850 while (GET_CODE (op0) == SUBREG)
852 offset += SUBREG_WORD (op0);
853 op0 = SUBREG_REG (op0);
857 /* If OP0 is a register, BITPOS must count within a word.
858 But as we have it, it counts within whatever size OP0 now has.
859 On a bigendian machine, these are not the same, so convert. */
860 if (GET_CODE (op0) != MEM && unit > GET_MODE_BITSIZE (GET_MODE (op0)))
861 bitpos += unit - GET_MODE_BITSIZE (GET_MODE (op0));
864 /* Extracting a full-word or multi-word value
865 from a structure in a register or aligned memory.
866 This can be done with just SUBREG.
867 So too extracting a subword value in
868 the least significant part of the register. */
870 if ((GET_CODE (op0) == REG
871 || (GET_CODE (op0) == MEM
872 && (! SLOW_UNALIGNED_ACCESS
873 || (offset * BITS_PER_UNIT % bitsize == 0
874 && align * BITS_PER_UNIT % bitsize == 0))))
875 && ((bitsize >= BITS_PER_WORD && bitsize == GET_MODE_BITSIZE (mode)
876 && bitpos % BITS_PER_WORD == 0)
877 || (mode_for_size (bitsize, GET_MODE_CLASS (tmode), 0) != BLKmode
879 && bitpos + bitsize == BITS_PER_WORD
885 enum machine_mode mode1
886 = mode_for_size (bitsize, GET_MODE_CLASS (tmode), 0);
888 if (mode1 != GET_MODE (op0))
890 if (GET_CODE (op0) == REG)
891 op0 = gen_rtx (SUBREG, mode1, op0, offset);
893 op0 = change_address (op0, mode1,
894 plus_constant (XEXP (op0, 0), offset));
897 return convert_to_mode (tmode, op0, unsignedp);
901 /* Handle fields bigger than a word. */
903 if (bitsize > BITS_PER_WORD)
905 /* Here we transfer the words of the field
906 in the order least significant first.
907 This is because the most significant word is the one which may
908 be less than full. */
910 int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD;
913 if (target == 0 || GET_CODE (target) != REG)
914 target = gen_reg_rtx (mode);
916 for (i = 0; i < nwords; i++)
918 /* If I is 0, use the low-order word in both field and target;
919 if I is 1, use the next to lowest word; and so on. */
920 int wordnum = (WORDS_BIG_ENDIAN ? nwords - i - 1 : i);
921 int bit_offset = (WORDS_BIG_ENDIAN
922 ? MAX (0, bitsize - (i + 1) * BITS_PER_WORD)
923 : i * BITS_PER_WORD);
924 rtx target_part = operand_subword (target, wordnum, 1, VOIDmode);
926 = extract_bit_field (op0, MIN (BITS_PER_WORD,
927 bitsize - i * BITS_PER_WORD),
929 1, target_part, mode, word_mode,
932 if (target_part == 0)
935 if (result_part != target_part)
936 emit_move_insn (target_part, result_part);
941 /* Signed bit field: sign-extend with two arithmetic shifts. */
942 target = expand_shift (LSHIFT_EXPR, mode, target,
943 build_int_2 (GET_MODE_BITSIZE (mode) - bitsize, 0),
945 return expand_shift (RSHIFT_EXPR, mode, target,
946 build_int_2 (GET_MODE_BITSIZE (mode) - bitsize, 0),
950 /* From here on we know the desired field is smaller than a word
951 so we can assume it is an integer. So we can safely extract it as one
952 size of integer, if necessary, and then truncate or extend
953 to the size that is wanted. */
955 /* OFFSET is the number of words or bytes (UNIT says which)
956 from STR_RTX to the first word or byte containing part of the field. */
958 if (GET_CODE (op0) == REG)
961 || GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD)
962 op0 = gen_rtx (SUBREG, TYPE_MODE (type_for_size (BITS_PER_WORD, 0)),
968 op0 = protect_from_queue (str_rtx, 1);
971 /* Now OFFSET is nonzero only for memory operands. */
977 && (GET_MODE_BITSIZE (insn_operand_mode[(int) CODE_FOR_extzv][0])
979 && ! ((GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
981 > GET_MODE_BITSIZE (insn_operand_mode[(int) CODE_FOR_extzv][0]))))
983 int xbitpos = bitpos, xoffset = offset;
984 rtx bitsize_rtx, bitpos_rtx;
985 rtx last = get_last_insn();
987 rtx xtarget = target;
988 rtx xspec_target = spec_target;
989 rtx xspec_target_subreg = spec_target_subreg;
991 enum machine_mode maxmode
992 = insn_operand_mode[(int) CODE_FOR_extzv][0];
994 if (GET_CODE (xop0) == MEM)
996 int save_volatile_ok = volatile_ok;
999 /* Is the memory operand acceptable? */
1001 || ! ((*insn_operand_predicate[(int) CODE_FOR_extzv][1])
1002 (xop0, GET_MODE (xop0))))
1004 /* No, load into a reg and extract from there. */
1005 enum machine_mode bestmode;
1007 /* Get the mode to use for inserting into this field. If
1008 OP0 is BLKmode, get the smallest mode consistent with the
1009 alignment. If OP0 is a non-BLKmode object that is no
1010 wider than MAXMODE, use its mode. Otherwise, use the
1011 smallest mode containing the field. */
1013 if (GET_MODE (xop0) == BLKmode
1014 || (GET_MODE_SIZE (GET_MODE (op0))
1015 > GET_MODE_SIZE (maxmode)))
1016 bestmode = get_best_mode (bitsize, bitnum,
1017 align * BITS_PER_UNIT, maxmode,
1018 MEM_VOLATILE_P (xop0));
1020 bestmode = GET_MODE (xop0);
1022 if (bestmode == VOIDmode
1023 || (STRICT_ALIGNMENT && GET_MODE_SIZE (bestmode) > align))
1026 /* Compute offset as multiple of this unit,
1027 counting in bytes. */
1028 unit = GET_MODE_BITSIZE (bestmode);
1029 xoffset = (bitnum / unit) * GET_MODE_SIZE (bestmode);
1030 xbitpos = bitnum % unit;
1031 xop0 = change_address (xop0, bestmode,
1032 plus_constant (XEXP (xop0, 0),
1034 /* Fetch it to a register in that size. */
1035 xop0 = force_reg (bestmode, xop0);
1037 /* XBITPOS counts within UNIT, which is what is expected. */
1040 /* Get ref to first byte containing part of the field. */
1041 xop0 = change_address (xop0, byte_mode,
1042 plus_constant (XEXP (xop0, 0), xoffset));
1044 volatile_ok = save_volatile_ok;
1047 /* If op0 is a register, we need it in MAXMODE (which is usually
1048 SImode). to make it acceptable to the format of extzv. */
1049 if (GET_CODE (xop0) == SUBREG && GET_MODE (xop0) != maxmode)
1051 if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode)
1052 xop0 = gen_rtx (SUBREG, maxmode, xop0, 0);
1054 /* On big-endian machines, we count bits from the most significant.
1055 If the bit field insn does not, we must invert. */
1056 #if BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN
1057 xbitpos = unit - bitsize - xbitpos;
1059 /* Now convert from counting within UNIT to counting in MAXMODE. */
1061 if (GET_CODE (xop0) != MEM)
1062 xbitpos += GET_MODE_BITSIZE (maxmode) - unit;
1064 unit = GET_MODE_BITSIZE (maxmode);
1067 || (flag_force_mem && GET_CODE (xtarget) == MEM))
1068 xtarget = xspec_target = gen_reg_rtx (tmode);
1070 if (GET_MODE (xtarget) != maxmode)
1072 if (GET_CODE (xtarget) == REG)
1074 int wider = (GET_MODE_SIZE (maxmode)
1075 > GET_MODE_SIZE (GET_MODE (xtarget)));
1076 xtarget = gen_lowpart (maxmode, xtarget);
1078 xspec_target_subreg = xtarget;
1081 xtarget = gen_reg_rtx (maxmode);
1084 /* If this machine's extzv insists on a register target,
1085 make sure we have one. */
1086 if (! ((*insn_operand_predicate[(int) CODE_FOR_extzv][0])
1087 (xtarget, maxmode)))
1088 xtarget = gen_reg_rtx (maxmode);
1090 bitsize_rtx = GEN_INT (bitsize);
1091 bitpos_rtx = GEN_INT (xbitpos);
1093 pat = gen_extzv (protect_from_queue (xtarget, 1),
1094 xop0, bitsize_rtx, bitpos_rtx);
1099 spec_target = xspec_target;
1100 spec_target_subreg = xspec_target_subreg;
1104 delete_insns_since (last);
1105 target = extract_fixed_bit_field (tmode, op0, offset, bitsize,
1106 bitpos, target, 1, align);
1112 target = extract_fixed_bit_field (tmode, op0, offset, bitsize, bitpos,
1119 && (GET_MODE_BITSIZE (insn_operand_mode[(int) CODE_FOR_extv][0])
1121 && ! ((GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
1122 && (bitsize + bitpos
1123 > GET_MODE_BITSIZE (insn_operand_mode[(int) CODE_FOR_extv][0]))))
1125 int xbitpos = bitpos, xoffset = offset;
1126 rtx bitsize_rtx, bitpos_rtx;
1127 rtx last = get_last_insn();
1128 rtx xop0 = op0, xtarget = target;
1129 rtx xspec_target = spec_target;
1130 rtx xspec_target_subreg = spec_target_subreg;
1132 enum machine_mode maxmode
1133 = insn_operand_mode[(int) CODE_FOR_extv][0];
1135 if (GET_CODE (xop0) == MEM)
1137 /* Is the memory operand acceptable? */
1138 if (! ((*insn_operand_predicate[(int) CODE_FOR_extv][1])
1139 (xop0, GET_MODE (xop0))))
1141 /* No, load into a reg and extract from there. */
1142 enum machine_mode bestmode;
1144 /* Get the mode to use for inserting into this field. If
1145 OP0 is BLKmode, get the smallest mode consistent with the
1146 alignment. If OP0 is a non-BLKmode object that is no
1147 wider than MAXMODE, use its mode. Otherwise, use the
1148 smallest mode containing the field. */
1150 if (GET_MODE (xop0) == BLKmode
1151 || (GET_MODE_SIZE (GET_MODE (op0))
1152 > GET_MODE_SIZE (maxmode)))
1153 bestmode = get_best_mode (bitsize, bitnum,
1154 align * BITS_PER_UNIT, maxmode,
1155 MEM_VOLATILE_P (xop0));
1157 bestmode = GET_MODE (xop0);
1159 if (bestmode == VOIDmode
1160 || (STRICT_ALIGNMENT && GET_MODE_SIZE (bestmode) > align))
1163 /* Compute offset as multiple of this unit,
1164 counting in bytes. */
1165 unit = GET_MODE_BITSIZE (bestmode);
1166 xoffset = (bitnum / unit) * GET_MODE_SIZE (bestmode);
1167 xbitpos = bitnum % unit;
1168 xop0 = change_address (xop0, bestmode,
1169 plus_constant (XEXP (xop0, 0),
1171 /* Fetch it to a register in that size. */
1172 xop0 = force_reg (bestmode, xop0);
1174 /* XBITPOS counts within UNIT, which is what is expected. */
1177 /* Get ref to first byte containing part of the field. */
1178 xop0 = change_address (xop0, byte_mode,
1179 plus_constant (XEXP (xop0, 0), xoffset));
1182 /* If op0 is a register, we need it in MAXMODE (which is usually
1183 SImode) to make it acceptable to the format of extv. */
1184 if (GET_CODE (xop0) == SUBREG && GET_MODE (xop0) != maxmode)
1186 if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode)
1187 xop0 = gen_rtx (SUBREG, maxmode, xop0, 0);
1189 /* On big-endian machines, we count bits from the most significant.
1190 If the bit field insn does not, we must invert. */
1191 #if BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN
1192 xbitpos = unit - bitsize - xbitpos;
1194 /* XBITPOS counts within a size of UNIT.
1195 Adjust to count within a size of MAXMODE. */
1197 if (GET_CODE (xop0) != MEM)
1198 xbitpos += (GET_MODE_BITSIZE (maxmode) - unit);
1200 unit = GET_MODE_BITSIZE (maxmode);
1203 || (flag_force_mem && GET_CODE (xtarget) == MEM))
1204 xtarget = xspec_target = gen_reg_rtx (tmode);
1206 if (GET_MODE (xtarget) != maxmode)
1208 if (GET_CODE (xtarget) == REG)
1210 int wider = (GET_MODE_SIZE (maxmode)
1211 > GET_MODE_SIZE (GET_MODE (xtarget)));
1212 xtarget = gen_lowpart (maxmode, xtarget);
1214 xspec_target_subreg = xtarget;
1217 xtarget = gen_reg_rtx (maxmode);
1220 /* If this machine's extv insists on a register target,
1221 make sure we have one. */
1222 if (! ((*insn_operand_predicate[(int) CODE_FOR_extv][0])
1223 (xtarget, maxmode)))
1224 xtarget = gen_reg_rtx (maxmode);
1226 bitsize_rtx = GEN_INT (bitsize);
1227 bitpos_rtx = GEN_INT (xbitpos);
1229 pat = gen_extv (protect_from_queue (xtarget, 1),
1230 xop0, bitsize_rtx, bitpos_rtx);
1235 spec_target = xspec_target;
1236 spec_target_subreg = xspec_target_subreg;
1240 delete_insns_since (last);
1241 target = extract_fixed_bit_field (tmode, op0, offset, bitsize,
1242 bitpos, target, 0, align);
1248 target = extract_fixed_bit_field (tmode, op0, offset, bitsize, bitpos,
1251 if (target == spec_target)
1253 if (target == spec_target_subreg)
1255 if (GET_MODE (target) != tmode && GET_MODE (target) != mode)
1257 /* If the target mode is floating-point, first convert to the
1258 integer mode of that size and then access it as a floating-point
1259 value via a SUBREG. */
1260 if (GET_MODE_CLASS (tmode) == MODE_FLOAT)
1262 target = convert_to_mode (mode_for_size (GET_MODE_BITSIZE (tmode),
1265 if (GET_CODE (target) != REG)
1266 target = copy_to_reg (target);
1267 return gen_rtx (SUBREG, tmode, target, 0);
1270 return convert_to_mode (tmode, target, unsignedp);
1275 /* Extract a bit field using shifts and boolean operations
1276 Returns an rtx to represent the value.
1277 OP0 addresses a register (word) or memory (byte).
1278 BITPOS says which bit within the word or byte the bit field starts in.
1279 OFFSET says how many bytes farther the bit field starts;
1280 it is 0 if OP0 is a register.
1281 BITSIZE says how many bits long the bit field is.
1282 (If OP0 is a register, it may be narrower than a full word,
1283 but BITPOS still counts within a full word,
1284 which is significant on bigendian machines.)
1286 UNSIGNEDP is nonzero for an unsigned bit field (don't sign-extend value).
1287 If TARGET is nonzero, attempts to store the value there
1288 and return TARGET, but this is not guaranteed.
1289 If TARGET is not used, create a pseudo-reg of mode TMODE for the value.
1291 ALIGN is the alignment that STR_RTX is known to have, measured in bytes. */
1294 extract_fixed_bit_field (tmode, op0, offset, bitsize, bitpos,
1295 target, unsignedp, align)
1296 enum machine_mode tmode;
1297 register rtx op0, target;
1298 register int offset, bitsize, bitpos;
1302 int total_bits = BITS_PER_WORD;
1303 enum machine_mode mode;
1305 if (GET_CODE (op0) == SUBREG || GET_CODE (op0) == REG)
1307 /* Special treatment for a bit field split across two registers. */
1308 if (bitsize + bitpos > BITS_PER_WORD)
1309 return extract_split_bit_field (op0, bitsize, bitpos,
1314 /* Get the proper mode to use for this field. We want a mode that
1315 includes the entire field. If such a mode would be larger than
1316 a word, we won't be doing the extraction the normal way. */
1318 mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT,
1319 align * BITS_PER_UNIT, word_mode,
1320 GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0));
1322 if (mode == VOIDmode)
1323 /* The only way this should occur is if the field spans word
1325 return extract_split_bit_field (op0, bitsize,
1326 bitpos + offset * BITS_PER_UNIT,
1329 total_bits = GET_MODE_BITSIZE (mode);
1331 /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to
1332 be be in the range 0 to total_bits-1, and put any excess bytes in
1334 if (bitpos >= total_bits)
1336 offset += (bitpos / total_bits) * (total_bits / BITS_PER_UNIT);
1337 bitpos -= ((bitpos / total_bits) * (total_bits / BITS_PER_UNIT)
1341 /* Get ref to an aligned byte, halfword, or word containing the field.
1342 Adjust BITPOS to be position within a word,
1343 and OFFSET to be the offset of that word.
1344 Then alter OP0 to refer to that word. */
1345 bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT;
1346 offset -= (offset % (total_bits / BITS_PER_UNIT));
1347 op0 = change_address (op0, mode,
1348 plus_constant (XEXP (op0, 0), offset));
1351 mode = GET_MODE (op0);
1353 #if BYTES_BIG_ENDIAN
1354 /* BITPOS is the distance between our msb and that of OP0.
1355 Convert it to the distance from the lsb. */
1357 bitpos = total_bits - bitsize - bitpos;
1359 /* Now BITPOS is always the distance between the field's lsb and that of OP0.
1360 We have reduced the big-endian case to the little-endian case. */
1366 /* If the field does not already start at the lsb,
1367 shift it so it does. */
1368 tree amount = build_int_2 (bitpos, 0);
1369 /* Maybe propagate the target for the shift. */
1370 /* But not if we will return it--could confuse integrate.c. */
1371 rtx subtarget = (target != 0 && GET_CODE (target) == REG
1372 && !REG_FUNCTION_VALUE_P (target)
1374 if (tmode != mode) subtarget = 0;
1375 op0 = expand_shift (RSHIFT_EXPR, mode, op0, amount, subtarget, 1);
1377 /* Convert the value to the desired mode. */
1379 op0 = convert_to_mode (tmode, op0, 1);
1381 /* Unless the msb of the field used to be the msb when we shifted,
1382 mask out the upper bits. */
1384 if (GET_MODE_BITSIZE (mode) != bitpos + bitsize
1386 #ifdef SLOW_ZERO_EXTEND
1387 /* Always generate an `and' if
1388 we just zero-extended op0 and SLOW_ZERO_EXTEND, since it
1389 will combine fruitfully with the zero-extend. */
1394 return expand_binop (GET_MODE (op0), and_optab, op0,
1395 mask_rtx (GET_MODE (op0), 0, bitsize, 0),
1396 target, 1, OPTAB_LIB_WIDEN);
1400 /* To extract a signed bit-field, first shift its msb to the msb of the word,
1401 then arithmetic-shift its lsb to the lsb of the word. */
1402 op0 = force_reg (mode, op0);
1406 /* Find the narrowest integer mode that contains the field. */
1408 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode;
1409 mode = GET_MODE_WIDER_MODE (mode))
1410 if (GET_MODE_BITSIZE (mode) >= bitsize + bitpos)
1412 op0 = convert_to_mode (mode, op0, 0);
1416 if (GET_MODE_BITSIZE (mode) != (bitsize + bitpos))
1418 tree amount = build_int_2 (GET_MODE_BITSIZE (mode) - (bitsize + bitpos), 0);
1419 /* Maybe propagate the target for the shift. */
1420 /* But not if we will return the result--could confuse integrate.c. */
1421 rtx subtarget = (target != 0 && GET_CODE (target) == REG
1422 && ! REG_FUNCTION_VALUE_P (target)
1424 op0 = expand_shift (LSHIFT_EXPR, mode, op0, amount, subtarget, 1);
1427 return expand_shift (RSHIFT_EXPR, mode, op0,
1428 build_int_2 (GET_MODE_BITSIZE (mode) - bitsize, 0),
1432 /* Return a constant integer (CONST_INT or CONST_DOUBLE) mask value
1433 of mode MODE with BITSIZE ones followed by BITPOS zeros, or the
1434 complement of that if COMPLEMENT. The mask is truncated if
1435 necessary to the width of mode MODE. */
1438 mask_rtx (mode, bitpos, bitsize, complement)
1439 enum machine_mode mode;
1440 int bitpos, bitsize, complement;
1442 HOST_WIDE_INT masklow, maskhigh;
1444 if (bitpos < HOST_BITS_PER_WIDE_INT)
1445 masklow = (HOST_WIDE_INT) -1 << bitpos;
1449 if (bitpos + bitsize < HOST_BITS_PER_WIDE_INT)
1450 masklow &= ((unsigned HOST_WIDE_INT) -1
1451 >> (HOST_BITS_PER_WIDE_INT - bitpos - bitsize));
1453 if (bitpos <= HOST_BITS_PER_WIDE_INT)
1456 maskhigh = (HOST_WIDE_INT) -1 << (bitpos - HOST_BITS_PER_WIDE_INT);
1458 if (bitpos + bitsize > HOST_BITS_PER_WIDE_INT)
1459 maskhigh &= ((unsigned HOST_WIDE_INT) -1
1460 >> (2 * HOST_BITS_PER_WIDE_INT - bitpos - bitsize));
1466 maskhigh = ~maskhigh;
1470 return immed_double_const (masklow, maskhigh, mode);
1473 /* Return a constant integer (CONST_INT or CONST_DOUBLE) rtx with the value
1474 VALUE truncated to BITSIZE bits and then shifted left BITPOS bits. */
1477 lshift_value (mode, value, bitpos, bitsize)
1478 enum machine_mode mode;
1480 int bitpos, bitsize;
1482 unsigned HOST_WIDE_INT v = INTVAL (value);
1483 HOST_WIDE_INT low, high;
1485 if (bitsize < HOST_BITS_PER_WIDE_INT)
1486 v &= ~((HOST_WIDE_INT) -1 << bitsize);
1488 if (bitpos < HOST_BITS_PER_WIDE_INT)
1491 high = (bitpos > 0 ? (v >> (HOST_BITS_PER_WIDE_INT - bitpos)) : 0);
1496 high = v << (bitpos - HOST_BITS_PER_WIDE_INT);
1499 return immed_double_const (low, high, mode);
1502 /* Extract a bit field that is split across two words
1503 and return an RTX for the result.
1505 OP0 is the REG, SUBREG or MEM rtx for the first of the two words.
1506 BITSIZE is the field width; BITPOS, position of its first bit, in the word.
1507 UNSIGNEDP is 1 if should zero-extend the contents; else sign-extend.
1509 ALIGN is the known alignment of OP0, measured in bytes.
1510 This is also the size of the memory objects to be used. */
1513 extract_split_bit_field (op0, bitsize, bitpos, unsignedp, align)
1515 int bitsize, bitpos, unsignedp, align;
1522 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
1524 if (GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
1525 unit = BITS_PER_WORD;
1527 unit = MIN (align * BITS_PER_UNIT, BITS_PER_WORD);
1529 while (bitsdone < bitsize)
1536 offset = (bitpos + bitsdone) / unit;
1537 thispos = (bitpos + bitsdone) % unit;
1539 /* THISSIZE must not overrun a word boundary. Otherwise,
1540 extract_fixed_bit_field will call us again, and we will mutually
1542 thissize = MIN (bitsize - bitsdone, BITS_PER_WORD);
1543 thissize = MIN (thissize, unit - thispos);
1545 /* If OP0 is a register, then handle OFFSET here.
1547 When handling multiword bitfields, extract_bit_field may pass
1548 down a word_mode SUBREG of a larger REG for a bitfield that actually
1549 crosses a word boundary. Thus, for a SUBREG, we must find
1550 the current word starting from the base register. */
1551 if (GET_CODE (op0) == SUBREG)
1553 word = operand_subword_force (SUBREG_REG (op0),
1554 SUBREG_WORD (op0) + offset,
1555 GET_MODE (SUBREG_REG (op0)));
1558 else if (GET_CODE (op0) == REG)
1560 word = operand_subword_force (op0, offset, GET_MODE (op0));
1566 /* Extract the parts in bit-counting order,
1567 whose meaning is determined by BYTES_PER_UNIT.
1568 OFFSET is in UNITs, and UNIT is in bits.
1569 extract_fixed_bit_field wants offset in bytes. */
1570 part = extract_fixed_bit_field (word_mode, word,
1571 offset * unit / BITS_PER_UNIT,
1572 thissize, thispos, 0, 1, align);
1573 bitsdone += thissize;
1575 /* Shift this part into place for the result. */
1576 #if BYTES_BIG_ENDIAN
1577 if (bitsize != bitsdone)
1578 part = expand_shift (LSHIFT_EXPR, word_mode, part,
1579 build_int_2 (bitsize - bitsdone, 0), 0, 1);
1581 if (bitsdone != thissize)
1582 part = expand_shift (LSHIFT_EXPR, word_mode, part,
1583 build_int_2 (bitsdone - thissize, 0), 0, 1);
1589 /* Combine the parts with bitwise or. This works
1590 because we extracted each part as an unsigned bit field. */
1591 result = expand_binop (word_mode, ior_optab, part, result, NULL_RTX, 1,
1597 /* Unsigned bit field: we are done. */
1600 /* Signed bit field: sign-extend with two arithmetic shifts. */
1601 result = expand_shift (LSHIFT_EXPR, word_mode, result,
1602 build_int_2 (BITS_PER_WORD - bitsize, 0),
1604 return expand_shift (RSHIFT_EXPR, word_mode, result,
1605 build_int_2 (BITS_PER_WORD - bitsize, 0), NULL_RTX, 0);
1608 /* Add INC into TARGET. */
1611 expand_inc (target, inc)
1614 rtx value = expand_binop (GET_MODE (target), add_optab,
1616 target, 0, OPTAB_LIB_WIDEN);
1617 if (value != target)
1618 emit_move_insn (target, value);
1621 /* Subtract DEC from TARGET. */
1624 expand_dec (target, dec)
1627 rtx value = expand_binop (GET_MODE (target), sub_optab,
1629 target, 0, OPTAB_LIB_WIDEN);
1630 if (value != target)
1631 emit_move_insn (target, value);
1634 /* Output a shift instruction for expression code CODE,
1635 with SHIFTED being the rtx for the value to shift,
1636 and AMOUNT the tree for the amount to shift by.
1637 Store the result in the rtx TARGET, if that is convenient.
1638 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
1639 Return the rtx for where the value is. */
1642 expand_shift (code, mode, shifted, amount, target, unsignedp)
1643 enum tree_code code;
1644 register enum machine_mode mode;
1647 register rtx target;
1650 register rtx op1, temp = 0;
1651 register int left = (code == LSHIFT_EXPR || code == LROTATE_EXPR);
1652 register int rotate = (code == LROTATE_EXPR || code == RROTATE_EXPR);
1655 /* Previously detected shift-counts computed by NEGATE_EXPR
1656 and shifted in the other direction; but that does not work
1659 op1 = expand_expr (amount, NULL_RTX, VOIDmode, 0);
1661 #if 0 && SHIFT_COUNT_TRUNCATED
1662 if (SHIFT_COUNT_TRUNCATED
1663 && GET_CODE (op1) == CONST_INT
1664 && (unsigned HOST_WIDE_INT) INTVAL (op1) >= GET_MODE_BITSIZE (mode))
1665 op1 = GEN_INT ((unsigned HOST_WIDE_INT) INTVAL (op1)
1666 % GET_MODE_BITSIZE (mode));
1669 if (op1 == const0_rtx)
1672 for (try = 0; temp == 0 && try < 3; try++)
1674 enum optab_methods methods;
1677 methods = OPTAB_DIRECT;
1679 methods = OPTAB_WIDEN;
1681 methods = OPTAB_LIB_WIDEN;
1685 /* Widening does not work for rotation. */
1686 if (methods == OPTAB_WIDEN)
1688 else if (methods == OPTAB_LIB_WIDEN)
1690 /* If we are rotating by a constant that is valid and
1691 we have been unable to open-code this by a rotation,
1692 do it as the IOR of two shifts. I.e., to rotate A
1693 by N bits, compute (A << N) | ((unsigned) A >> (C - N))
1694 where C is the bitsize of A.
1696 It is theoretically possible that the target machine might
1697 not be able to perform either shift and hence we would
1698 be making two libcalls rather than just the one for the
1699 shift (similarly if IOR could not be done). We will allow
1700 this extremely unlikely lossage to avoid complicating the
1703 if (GET_CODE (op1) == CONST_INT && INTVAL (op1) > 0
1704 && INTVAL (op1) < GET_MODE_BITSIZE (mode))
1706 rtx subtarget = target == shifted ? 0 : target;
1709 = build_int_2 (GET_MODE_BITSIZE (mode) - INTVAL (op1), 0);
1711 shifted = force_reg (mode, shifted);
1713 temp = expand_shift (left ? LSHIFT_EXPR : RSHIFT_EXPR,
1714 mode, shifted, amount, subtarget, 1);
1715 temp1 = expand_shift (left ? RSHIFT_EXPR : LSHIFT_EXPR,
1716 mode, shifted, other_amount, 0, 1);
1717 return expand_binop (mode, ior_optab, temp, temp1, target,
1718 unsignedp, methods);
1721 methods = OPTAB_LIB;
1724 temp = expand_binop (mode,
1725 left ? rotl_optab : rotr_optab,
1726 shifted, op1, target, unsignedp, methods);
1728 /* If we don't have the rotate, but we are rotating by a constant
1729 that is in range, try a rotate in the opposite direction. */
1731 if (temp == 0 && GET_CODE (op1) == CONST_INT
1732 && INTVAL (op1) > 0 && INTVAL (op1) < GET_MODE_BITSIZE (mode))
1733 temp = expand_binop (mode,
1734 left ? rotr_optab : rotl_optab,
1736 GEN_INT (GET_MODE_BITSIZE (mode)
1738 target, unsignedp, methods);
1741 temp = expand_binop (mode,
1742 left ? ashl_optab : lshr_optab,
1743 shifted, op1, target, unsignedp, methods);
1745 /* Do arithmetic shifts.
1746 Also, if we are going to widen the operand, we can just as well
1747 use an arithmetic right-shift instead of a logical one. */
1748 if (temp == 0 && ! rotate
1749 && (! unsignedp || (! left && methods == OPTAB_WIDEN)))
1751 enum optab_methods methods1 = methods;
1753 /* If trying to widen a log shift to an arithmetic shift,
1754 don't accept an arithmetic shift of the same size. */
1756 methods1 = OPTAB_MUST_WIDEN;
1758 /* Arithmetic shift */
1760 temp = expand_binop (mode,
1761 left ? ashl_optab : ashr_optab,
1762 shifted, op1, target, unsignedp, methods1);
1765 /* We used to try extzv here for logical right shifts, but that was
1766 only useful for one machine, the VAX, and caused poor code
1767 generation there for lshrdi3, so the code was deleted and a
1768 define_expand for lshrsi3 was added to vax.md. */
1776 enum alg_code { alg_zero, alg_m, alg_shift,
1777 alg_add_t_m2, alg_sub_t_m2,
1778 alg_add_factor, alg_sub_factor,
1779 alg_add_t2_m, alg_sub_t2_m,
1780 alg_add, alg_subtract, alg_factor, alg_shiftop };
1782 /* This structure records a sequence of operations.
1783 `ops' is the number of operations recorded.
1784 `cost' is their total cost.
1785 The operations are stored in `op' and the corresponding
1786 logarithms of the integer coefficients in `log'.
1788 These are the operations:
1789 alg_zero total := 0;
1790 alg_m total := multiplicand;
1791 alg_shift total := total * coeff
1792 alg_add_t_m2 total := total + multiplicand * coeff;
1793 alg_sub_t_m2 total := total - multiplicand * coeff;
1794 alg_add_factor total := total * coeff + total;
1795 alg_sub_factor total := total * coeff - total;
1796 alg_add_t2_m total := total * coeff + multiplicand;
1797 alg_sub_t2_m total := total * coeff - multiplicand;
1799 The first operand must be either alg_zero or alg_m. */
1805 /* The size of the OP and LOG fields are not directly related to the
1806 word size, but the worst-case algorithms will be if we have few
1807 consecutive ones or zeros, i.e., a multiplicand like 10101010101...
1808 In that case we will generate shift-by-2, add, shift-by-2, add,...,
1809 in total wordsize operations. */
1810 enum alg_code op[MAX_BITS_PER_WORD];
1811 char log[MAX_BITS_PER_WORD];
1814 /* Compute and return the best algorithm for multiplying by T.
1815 The algorithm must cost less than cost_limit
1816 If retval.cost >= COST_LIMIT, no algorithm was found and all
1817 other field of the returned struct are undefined. */
1820 synth_mult (alg_out, t, cost_limit)
1821 struct algorithm *alg_out;
1822 unsigned HOST_WIDE_INT t;
1826 struct algorithm *alg_in, *best_alg;
1828 unsigned HOST_WIDE_INT q;
1830 /* Indicate that no algorithm is yet found. If no algorithm
1831 is found, this value will be returned and indicate failure. */
1832 alg_out->cost = cost_limit;
1834 if (cost_limit <= 0)
1837 /* t == 1 can be done in zero cost. */
1842 alg_out->op[0] = alg_m;
1846 /* t == 0 sometimes has a cost. If it does and it exceeds our limit,
1850 if (zero_cost >= cost_limit)
1855 alg_out->cost = zero_cost;
1856 alg_out->op[0] = alg_zero;
1861 /* We'll be needing a couple extra algorithm structures now. */
1863 alg_in = (struct algorithm *)alloca (sizeof (struct algorithm));
1864 best_alg = (struct algorithm *)alloca (sizeof (struct algorithm));
1866 /* If we have a group of zero bits at the low-order part of T, try
1867 multiplying by the remaining bits and then doing a shift. */
1871 m = floor_log2 (t & -t); /* m = number of low zero bits */
1873 cost = shift_cost[m];
1874 synth_mult (alg_in, q, cost_limit - cost);
1876 cost += alg_in->cost;
1877 if (cost < cost_limit)
1879 struct algorithm *x;
1880 x = alg_in, alg_in = best_alg, best_alg = x;
1881 best_alg->log[best_alg->ops] = m;
1882 best_alg->op[best_alg->ops] = alg_shift;
1887 /* If we have an odd number, add or subtract one. */
1890 unsigned HOST_WIDE_INT w;
1892 for (w = 1; (w & t) != 0; w <<= 1)
1895 /* Reject the case where t is 3.
1896 Thus we prefer addition in that case. */
1899 /* T ends with ...111. Multiply by (T + 1) and subtract 1. */
1902 synth_mult (alg_in, t + 1, cost_limit - cost);
1904 cost += alg_in->cost;
1905 if (cost < cost_limit)
1907 struct algorithm *x;
1908 x = alg_in, alg_in = best_alg, best_alg = x;
1909 best_alg->log[best_alg->ops] = 0;
1910 best_alg->op[best_alg->ops] = alg_sub_t_m2;
1916 /* T ends with ...01 or ...011. Multiply by (T - 1) and add 1. */
1919 synth_mult (alg_in, t - 1, cost_limit - cost);
1921 cost += alg_in->cost;
1922 if (cost < cost_limit)
1924 struct algorithm *x;
1925 x = alg_in, alg_in = best_alg, best_alg = x;
1926 best_alg->log[best_alg->ops] = 0;
1927 best_alg->op[best_alg->ops] = alg_add_t_m2;
1933 /* Look for factors of t of the form
1934 t = q(2**m +- 1), 2 <= m <= floor(log2(t - 1)).
1935 If we find such a factor, we can multiply by t using an algorithm that
1936 multiplies by q, shift the result by m and add/subtract it to itself.
1938 We search for large factors first and loop down, even if large factors
1939 are less probable than small; if we find a large factor we will find a
1940 good sequence quickly, and therefore be able to prune (by decreasing
1941 COST_LIMIT) the search. */
1943 for (m = floor_log2 (t - 1); m >= 2; m--)
1945 unsigned HOST_WIDE_INT d;
1947 d = ((unsigned HOST_WIDE_INT) 1 << m) + 1;
1948 if (t % d == 0 && t > d)
1950 cost = MIN (shiftadd_cost[m], add_cost + shift_cost[m]);
1951 synth_mult (alg_in, t / d, cost_limit - cost);
1953 cost += alg_in->cost;
1954 if (cost < cost_limit)
1956 struct algorithm *x;
1957 x = alg_in, alg_in = best_alg, best_alg = x;
1958 best_alg->log[best_alg->ops] = m;
1959 best_alg->op[best_alg->ops] = alg_add_factor;
1962 /* Other factors will have been taken care of in the recursion. */
1966 d = ((unsigned HOST_WIDE_INT) 1 << m) - 1;
1967 if (t % d == 0 && t > d)
1969 cost = MIN (shiftsub_cost[m], add_cost + shift_cost[m]);
1970 synth_mult (alg_in, t / d, cost_limit - cost);
1972 cost += alg_in->cost;
1973 if (cost < cost_limit)
1975 struct algorithm *x;
1976 x = alg_in, alg_in = best_alg, best_alg = x;
1977 best_alg->log[best_alg->ops] = m;
1978 best_alg->op[best_alg->ops] = alg_sub_factor;
1985 /* Try shift-and-add (load effective address) instructions,
1986 i.e. do a*3, a*5, a*9. */
1994 cost = shiftadd_cost[m];
1995 synth_mult (alg_in, (t - 1) >> m, cost_limit - cost);
1997 cost += alg_in->cost;
1998 if (cost < cost_limit)
2000 struct algorithm *x;
2001 x = alg_in, alg_in = best_alg, best_alg = x;
2002 best_alg->log[best_alg->ops] = m;
2003 best_alg->op[best_alg->ops] = alg_add_t2_m;
2013 cost = shiftsub_cost[m];
2014 synth_mult (alg_in, (t + 1) >> m, cost_limit - cost);
2016 cost += alg_in->cost;
2017 if (cost < cost_limit)
2019 struct algorithm *x;
2020 x = alg_in, alg_in = best_alg, best_alg = x;
2021 best_alg->log[best_alg->ops] = m;
2022 best_alg->op[best_alg->ops] = alg_sub_t2_m;
2028 /* If cost_limit has not decreased since we stored it in alg_out->cost,
2029 we have not found any algorithm. */
2030 if (cost_limit == alg_out->cost)
2033 /* If we are getting a too long sequence for `struct algorithm'
2034 to record, make this search fail. */
2035 if (best_alg->ops == MAX_BITS_PER_WORD)
2038 /* Copy the algorithm from temporary space to the space at alg_out.
2039 We avoid using structure assignment because the majority of
2040 best_alg is normally undefined, and this is a critical function. */
2041 alg_out->ops = best_alg->ops + 1;
2042 alg_out->cost = cost_limit;
2043 bcopy ((char *) best_alg->op, (char *) alg_out->op,
2044 alg_out->ops * sizeof *alg_out->op);
2045 bcopy ((char *) best_alg->log, (char *) alg_out->log,
2046 alg_out->ops * sizeof *alg_out->log);
2049 /* Perform a multiplication and return an rtx for the result.
2050 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
2051 TARGET is a suggestion for where to store the result (an rtx).
2053 We check specially for a constant integer as OP1.
2054 If you want this check for OP0 as well, then before calling
2055 you should swap the two operands if OP0 would be constant. */
2058 expand_mult (mode, op0, op1, target, unsignedp)
2059 enum machine_mode mode;
2060 register rtx op0, op1, target;
2063 rtx const_op1 = op1;
2065 /* synth_mult does an `unsigned int' multiply. As long as the mode is
2066 less than or equal in size to `unsigned int' this doesn't matter.
2067 If the mode is larger than `unsigned int', then synth_mult works only
2068 if the constant value exactly fits in an `unsigned int' without any
2069 truncation. This means that multiplying by negative values does
2070 not work; results are off by 2^32 on a 32 bit machine. */
2072 /* If we are multiplying in DImode, it may still be a win
2073 to try to work with shifts and adds. */
2074 if (GET_CODE (op1) == CONST_DOUBLE
2075 && GET_MODE_CLASS (GET_MODE (op1)) == MODE_INT
2076 && HOST_BITS_PER_INT >= BITS_PER_WORD
2077 && CONST_DOUBLE_HIGH (op1) == 0)
2078 const_op1 = GEN_INT (CONST_DOUBLE_LOW (op1));
2079 else if (HOST_BITS_PER_INT < GET_MODE_BITSIZE (mode)
2080 && GET_CODE (op1) == CONST_INT
2081 && INTVAL (op1) < 0)
2084 /* We used to test optimize here, on the grounds that it's better to
2085 produce a smaller program when -O is not used.
2086 But this causes such a terrible slowdown sometimes
2087 that it seems better to use synth_mult always. */
2089 if (const_op1 && GET_CODE (const_op1) == CONST_INT)
2091 struct algorithm alg;
2092 struct algorithm alg2;
2093 HOST_WIDE_INT val = INTVAL (op1);
2094 HOST_WIDE_INT val_so_far;
2097 enum {basic_variant, negate_variant, add_variant} variant = basic_variant;
2099 /* Try to do the computation three ways: multiply by the negative of OP1
2100 and then negate, do the multiplication directly, or do multiplication
2103 mult_cost = rtx_cost (gen_rtx (MULT, mode, op0, op1), SET);
2104 mult_cost = MIN (12 * add_cost, mult_cost);
2106 synth_mult (&alg, val, mult_cost);
2108 /* This works only if the inverted value actually fits in an
2110 if (HOST_BITS_PER_INT >= GET_MODE_BITSIZE (mode))
2112 synth_mult (&alg2, - val,
2113 (alg.cost < mult_cost ? alg.cost : mult_cost) - negate_cost);
2114 if (alg2.cost + negate_cost < alg.cost)
2115 alg = alg2, variant = negate_variant;
2118 /* This proves very useful for division-by-constant. */
2119 synth_mult (&alg2, val - 1,
2120 (alg.cost < mult_cost ? alg.cost : mult_cost) - add_cost);
2121 if (alg2.cost + add_cost < alg.cost)
2122 alg = alg2, variant = add_variant;
2124 if (alg.cost < mult_cost)
2126 /* We found something cheaper than a multiply insn. */
2130 op0 = protect_from_queue (op0, 0);
2132 /* Avoid referencing memory over and over.
2133 For speed, but also for correctness when mem is volatile. */
2134 if (GET_CODE (op0) == MEM)
2135 op0 = force_reg (mode, op0);
2137 /* ACCUM starts out either as OP0 or as a zero, depending on
2138 the first operation. */
2140 if (alg.op[0] == alg_zero)
2142 accum = copy_to_mode_reg (mode, const0_rtx);
2145 else if (alg.op[0] == alg_m)
2147 accum = copy_to_mode_reg (mode, op0);
2153 for (opno = 1; opno < alg.ops; opno++)
2155 int log = alg.log[opno];
2156 int preserve = preserve_subexpressions_p ();
2157 rtx shift_subtarget = preserve ? 0 : accum;
2159 = (opno == alg.ops - 1 && target != 0 && variant != add_variant
2161 rtx accum_target = preserve ? 0 : accum;
2163 switch (alg.op[opno])
2166 accum = expand_shift (LSHIFT_EXPR, mode, accum,
2167 build_int_2 (log, 0), NULL_RTX, 0);
2172 tem = expand_shift (LSHIFT_EXPR, mode, op0,
2173 build_int_2 (log, 0), NULL_RTX, 0);
2174 accum = force_operand (gen_rtx (PLUS, mode, accum, tem),
2175 add_target ? add_target : accum_target);
2176 val_so_far += (HOST_WIDE_INT) 1 << log;
2180 tem = expand_shift (LSHIFT_EXPR, mode, op0,
2181 build_int_2 (log, 0), NULL_RTX, 0);
2182 accum = force_operand (gen_rtx (MINUS, mode, accum, tem),
2183 add_target ? add_target : accum_target);
2184 val_so_far -= (HOST_WIDE_INT) 1 << log;
2188 accum = expand_shift (LSHIFT_EXPR, mode, accum,
2189 build_int_2 (log, 0), shift_subtarget,
2191 accum = force_operand (gen_rtx (PLUS, mode, accum, op0),
2192 add_target ? add_target : accum_target);
2193 val_so_far = (val_so_far << log) + 1;
2197 accum = expand_shift (LSHIFT_EXPR, mode, accum,
2198 build_int_2 (log, 0), shift_subtarget,
2200 accum = force_operand (gen_rtx (MINUS, mode, accum, op0),
2201 add_target ? add_target : accum_target);
2202 val_so_far = (val_so_far << log) - 1;
2205 case alg_add_factor:
2206 tem = expand_shift (LSHIFT_EXPR, mode, accum,
2207 build_int_2 (log, 0), NULL_RTX, 0);
2208 accum = force_operand (gen_rtx (PLUS, mode, accum, tem),
2209 add_target ? add_target : accum_target);
2210 val_so_far += val_so_far << log;
2213 case alg_sub_factor:
2214 tem = expand_shift (LSHIFT_EXPR, mode, accum,
2215 build_int_2 (log, 0), NULL_RTX, 0);
2216 accum = force_operand (gen_rtx (MINUS, mode, tem, accum),
2217 (add_target ? add_target
2218 : preserve ? 0 : tem));
2219 val_so_far = (val_so_far << log) - val_so_far;
2226 /* Write a REG_EQUAL note on the last insn so that we can cse
2227 multiplication sequences. */
2229 insn = get_last_insn ();
2231 = gen_rtx (EXPR_LIST, REG_EQUAL,
2232 gen_rtx (MULT, mode, op0, GEN_INT (val_so_far)),
2236 if (variant == negate_variant)
2238 val_so_far = - val_so_far;
2239 accum = expand_unop (mode, neg_optab, accum, target, 0);
2241 else if (variant == add_variant)
2243 val_so_far = val_so_far + 1;
2244 accum = force_operand (gen_rtx (PLUS, mode, accum, op0), target);
2247 if (val != val_so_far)
2254 /* This used to use umul_optab if unsigned, but for non-widening multiply
2255 there is no difference between signed and unsigned. */
2256 op0 = expand_binop (mode, smul_optab,
2257 op0, op1, target, unsignedp, OPTAB_LIB_WIDEN);
2263 /* Return the smallest n such that 2**n >= X. */
2267 unsigned HOST_WIDE_INT x;
2269 return floor_log2 (x - 1) + 1;
2272 /* Choose a minimal N + 1 bit approximation to 1/D that can be used to
2273 replace division by D, and put the least significant N bits of the result
2274 in *MULTIPLIER_PTR and return the most significant bit.
2276 The width of operations is N (should be <= HOST_BITS_PER_WIDE_INT), the
2277 needed precision is in PRECISION (should be <= N).
2279 PRECISION should be as small as possible so this function can choose
2280 multiplier more freely.
2282 The rounded-up logarithm of D is placed in *lgup_ptr. A shift count that
2283 is to be used for a final right shift is placed in *POST_SHIFT_PTR.
2285 Using this function, x/D will be equal to (x * m) >> (*POST_SHIFT_PTR),
2286 where m is the full HOST_BITS_PER_WIDE_INT + 1 bit multiplier. */
2289 unsigned HOST_WIDE_INT
2290 choose_multiplier (d, n, precision, multiplier_ptr, post_shift_ptr, lgup_ptr)
2291 unsigned HOST_WIDE_INT d;
2294 unsigned HOST_WIDE_INT *multiplier_ptr;
2295 int *post_shift_ptr;
2298 unsigned HOST_WIDE_INT mhigh_hi, mhigh_lo;
2299 unsigned HOST_WIDE_INT mlow_hi, mlow_lo;
2300 int lgup, post_shift;
2302 unsigned HOST_WIDE_INT nh, nl, dummy1, dummy2;
2304 /* lgup = ceil(log2(divisor)); */
2305 lgup = ceil_log2 (d);
2311 pow2 = n + lgup - precision;
2313 if (pow == 2 * HOST_BITS_PER_WIDE_INT)
2315 /* We could handle this with some effort, but this case is much better
2316 handled directly with a scc insn, so rely on caller using that. */
2320 /* mlow = 2^(N + lgup)/d */
2321 if (pow >= HOST_BITS_PER_WIDE_INT)
2323 nh = (unsigned HOST_WIDE_INT) 1 << (pow - HOST_BITS_PER_WIDE_INT);
2329 nl = (unsigned HOST_WIDE_INT) 1 << pow;
2331 div_and_round_double (TRUNC_DIV_EXPR, 1, nl, nh, d, (HOST_WIDE_INT) 0,
2332 &mlow_lo, &mlow_hi, &dummy1, &dummy2);
2334 /* mhigh = (2^(N + lgup) + 2^N + lgup - precision)/d */
2335 if (pow2 >= HOST_BITS_PER_WIDE_INT)
2336 nh |= (unsigned HOST_WIDE_INT) 1 << (pow2 - HOST_BITS_PER_WIDE_INT);
2338 nl |= (unsigned HOST_WIDE_INT) 1 << pow2;
2339 div_and_round_double (TRUNC_DIV_EXPR, 1, nl, nh, d, (HOST_WIDE_INT) 0,
2340 &mhigh_lo, &mhigh_hi, &dummy1, &dummy2);
2342 if (mhigh_hi && nh - d >= d)
2344 if (mhigh_hi > 1 || mlow_hi > 1)
2346 /* assert that mlow < mhigh. */
2347 if (! (mlow_hi < mhigh_hi || (mlow_hi == mhigh_hi && mlow_lo < mhigh_lo)))
2350 /* If precision == N, then mlow, mhigh exceed 2^N
2351 (but they do not exceed 2^(N+1)). */
2353 /* Reduce to lowest terms */
2354 for (post_shift = lgup; post_shift > 0; post_shift--)
2356 unsigned HOST_WIDE_INT ml_lo = (mlow_hi << (HOST_BITS_PER_WIDE_INT - 1)) | (mlow_lo >> 1);
2357 unsigned HOST_WIDE_INT mh_lo = (mhigh_hi << (HOST_BITS_PER_WIDE_INT - 1)) | (mhigh_lo >> 1);
2367 *post_shift_ptr = post_shift;
2369 if (n < HOST_BITS_PER_WIDE_INT)
2371 unsigned HOST_WIDE_INT mask = ((unsigned HOST_WIDE_INT) 1 << n) - 1;
2372 *multiplier_ptr = mhigh_lo & mask;
2373 return mhigh_lo >= mask;
2377 *multiplier_ptr = mhigh_lo;
2382 /* Compute the inverse of X mod 2**n, i.e., find Y such that X * Y is
2383 congruent to 1 (mod 2**N). */
2385 static unsigned HOST_WIDE_INT
2387 unsigned HOST_WIDE_INT x;
2390 /* Solve x*y == 1 (mod 2^n), where x is odd. Return y. */
2392 /* The algorithm notes that the choice y = x satisfies
2393 x*y == 1 mod 2^3, since x is assumed odd.
2394 Each iteration doubles the number of bits of significance in y. */
2396 unsigned HOST_WIDE_INT mask;
2397 unsigned HOST_WIDE_INT y = x;
2400 mask = (n == HOST_BITS_PER_WIDE_INT
2401 ? ~(unsigned HOST_WIDE_INT) 0
2402 : ((unsigned HOST_WIDE_INT) 1 << n) - 1);
2406 y = y * (2 - x*y) & mask; /* Modulo 2^N */
2412 /* Emit code to adjust ADJ_OPERAND after multiplication of wrong signedness
2413 flavor of OP0 and OP1. ADJ_OPERAND is already the high half of the
2414 product OP0 x OP1. If UNSIGNEDP is nonzero, adjust the signed product
2415 to become unsigned, if UNSIGNEDP is zero, adjust the unsigned product to
2418 The result is put in TARGET if that is convenient.
2420 MODE is the mode of operation. */
2423 expand_mult_highpart_adjust (mode, adj_operand, op0, op1, target, unsignedp)
2424 enum machine_mode mode;
2425 register rtx adj_operand, op0, op1, target;
2429 enum rtx_code adj_code = unsignedp ? PLUS : MINUS;
2431 tem = expand_shift (RSHIFT_EXPR, mode, op0,
2432 build_int_2 (GET_MODE_BITSIZE (mode) - 1, 0),
2434 tem = expand_and (tem, op1, NULL_RTX);
2435 adj_operand = force_operand (gen_rtx (adj_code, mode, adj_operand, tem),
2438 tem = expand_shift (RSHIFT_EXPR, mode, op1,
2439 build_int_2 (GET_MODE_BITSIZE (mode) - 1, 0),
2441 tem = expand_and (tem, op0, NULL_RTX);
2442 target = force_operand (gen_rtx (adj_code, mode, adj_operand, tem), target);
2447 /* Emit code to multiply OP0 and CNST1, putting the high half of the result
2448 in TARGET if that is convenient, and return where the result is. If the
2449 operation can not be performed, 0 is returned.
2451 MODE is the mode of operation and result.
2453 UNSIGNEDP nonzero means unsigned multiply. */
2456 expand_mult_highpart (mode, op0, cnst1, target, unsignedp)
2457 enum machine_mode mode;
2458 register rtx op0, target;
2459 unsigned HOST_WIDE_INT cnst1;
2462 enum machine_mode wider_mode = GET_MODE_WIDER_MODE (mode);
2463 optab mul_highpart_optab;
2466 int size = GET_MODE_BITSIZE (mode);
2469 /* We can't support modes wider than HOST_BITS_PER_INT. */
2470 if (size > HOST_BITS_PER_WIDE_INT)
2473 op1 = GEN_INT (cnst1);
2475 if (GET_MODE_BITSIZE (wider_mode) <= HOST_BITS_PER_INT)
2479 = immed_double_const (cnst1,
2482 : -(cnst1 >> (HOST_BITS_PER_WIDE_INT - 1))),
2485 /* expand_mult handles constant multiplication of word_mode
2486 or narrower. It does a poor job for large modes. */
2487 if (size < BITS_PER_WORD)
2489 /* We have to do this, since expand_binop doesn't do conversion for
2490 multiply. Maybe change expand_binop to handle widening multiply? */
2491 op0 = convert_to_mode (wider_mode, op0, unsignedp);
2493 tem = expand_mult (wider_mode, op0, wide_op1, NULL_RTX, unsignedp);
2494 tem = expand_shift (RSHIFT_EXPR, wider_mode, tem,
2495 build_int_2 (size, 0), NULL_RTX, 1);
2496 return gen_lowpart (mode, tem);
2500 target = gen_reg_rtx (mode);
2502 /* Firstly, try using a multiplication insn that only generates the needed
2503 high part of the product, and in the sign flavor of unsignedp. */
2504 mul_highpart_optab = unsignedp ? umul_highpart_optab : smul_highpart_optab;
2505 target = expand_binop (mode, mul_highpart_optab,
2506 op0, op1, target, unsignedp, OPTAB_DIRECT);
2510 /* Secondly, same as above, but use sign flavor opposite of unsignedp.
2511 Need to adjust the result after the multiplication. */
2512 mul_highpart_optab = unsignedp ? smul_highpart_optab : umul_highpart_optab;
2513 target = expand_binop (mode, mul_highpart_optab,
2514 op0, op1, target, unsignedp, OPTAB_DIRECT);
2516 /* We used the wrong signedness. Adjust the result. */
2517 return expand_mult_highpart_adjust (mode, target, op0,
2518 op1, target, unsignedp);
2520 /* Thirdly, we try to use a widening multiplication, or a wider mode
2523 moptab = unsignedp ? umul_widen_optab : smul_widen_optab;
2524 if (moptab->handlers[(int) wider_mode].insn_code != CODE_FOR_nothing)
2526 else if (smul_optab->handlers[(int) wider_mode].insn_code != CODE_FOR_nothing)
2527 moptab = smul_optab;
2530 /* Try widening multiplication of opposite signedness, and adjust. */
2531 moptab = unsignedp ? smul_widen_optab : umul_widen_optab;
2532 if (moptab->handlers[(int) wider_mode].insn_code != CODE_FOR_nothing)
2534 tem = expand_binop (wider_mode, moptab, op0, wide_op1,
2535 NULL_RTX, ! unsignedp, OPTAB_WIDEN);
2538 /* Extract the high half of the just generated product. */
2539 tem = expand_shift (RSHIFT_EXPR, wider_mode, tem,
2540 build_int_2 (size, 0), NULL_RTX, 1);
2541 tem = gen_lowpart (mode, tem);
2542 /* We used the wrong signedness. Adjust the result. */
2543 return expand_mult_highpart_adjust (mode, tem, op0, op1,
2548 /* As a last resort, try widening the mode and perform a
2549 non-widening multiplication. */
2550 moptab = smul_optab;
2553 /* Pass NULL_RTX as target since TARGET has wrong mode. */
2554 tem = expand_binop (wider_mode, moptab, op0, wide_op1,
2555 NULL_RTX, unsignedp, OPTAB_WIDEN);
2559 /* Extract the high half of the just generated product. */
2560 tem = expand_shift (RSHIFT_EXPR, wider_mode, tem,
2561 build_int_2 (size, 0), NULL_RTX, 1);
2562 return gen_lowpart (mode, tem);
2565 /* Emit the code to divide OP0 by OP1, putting the result in TARGET
2566 if that is convenient, and returning where the result is.
2567 You may request either the quotient or the remainder as the result;
2568 specify REM_FLAG nonzero to get the remainder.
2570 CODE is the expression code for which kind of division this is;
2571 it controls how rounding is done. MODE is the machine mode to use.
2572 UNSIGNEDP nonzero means do unsigned division. */
2574 /* ??? For CEIL_MOD_EXPR, can compute incorrect remainder with ANDI
2575 and then correct it by or'ing in missing high bits
2576 if result of ANDI is nonzero.
2577 For ROUND_MOD_EXPR, can use ANDI and then sign-extend the result.
2578 This could optimize to a bfexts instruction.
2579 But C doesn't use these operations, so their optimizations are
2582 #define EXACT_POWER_OF_2_OR_ZERO_P(x) (((x) & ((x) - 1)) == 0)
2585 expand_divmod (rem_flag, code, mode, op0, op1, target, unsignedp)
2587 enum tree_code code;
2588 enum machine_mode mode;
2589 register rtx op0, op1, target;
2592 enum machine_mode compute_mode;
2593 register rtx tquotient;
2594 rtx quotient = 0, remainder = 0;
2598 optab optab1, optab2;
2599 int op1_is_constant, op1_is_pow2;
2601 op1_is_constant = GET_CODE (op1) == CONST_INT;
2602 op1_is_pow2 = (op1_is_constant
2603 && ((EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1))
2604 || EXACT_POWER_OF_2_OR_ZERO_P (-INTVAL (op1)))));
2607 This is the structure of expand_divmod:
2609 First comes code to fix up the operands so we can perform the operations
2610 correctly and efficiently.
2612 Second comes a switch statement with code specific for each rounding mode.
2613 For some special operands this code emits all RTL for the desired
2614 operation, for other cases, it generates a quotient and stores it in
2615 QUOTIENT. The case for trunc division/remainder might leave quotient = 0,
2616 to indicate that it has not done anything.
2618 Last comes code that finishes the operation. If QUOTIENT is set an
2619 REM_FLAG, the remainder is computed as OP0 - QUOTIENT * OP1. If QUOTIENT
2620 is not set, it is computed using trunc rounding.
2622 We try to generate special code for division and remainder when OP1 is a
2623 constant. If |OP1| = 2**n we can use shifts and some other fast
2624 operations. For other values of OP1, we compute a carefully selected
2625 fixed-point approximation m = 1/OP1, and generate code that multiplies OP0
2628 In all cases but EXACT_DIV_EXPR, this multiplication requires the upper
2629 half of the product. Different strategies for generating the product are
2630 implemented in expand_mult_highpart.
2632 If what we actually want is the remainder, we generate that by another
2633 by-constant multiplication and a subtraction. */
2635 /* We shouldn't be called with OP1 == const1_rtx, but some of the
2636 code below will malfunction if we are, so check here and handle
2637 the special case if so. */
2638 if (op1 == const1_rtx)
2639 return rem_flag ? const0_rtx : op0;
2642 /* Don't use the function value register as a target
2643 since we have to read it as well as write it,
2644 and function-inlining gets confused by this. */
2645 && ((REG_P (target) && REG_FUNCTION_VALUE_P (target))
2646 /* Don't clobber an operand while doing a multi-step calculation. */
2647 || ((rem_flag || op1_is_constant)
2648 && (reg_mentioned_p (target, op0)
2649 || (GET_CODE (op0) == MEM && GET_CODE (target) == MEM)))
2650 || reg_mentioned_p (target, op1)
2651 || (GET_CODE (op1) == MEM && GET_CODE (target) == MEM)))
2654 /* Get the mode in which to perform this computation. Normally it will
2655 be MODE, but sometimes we can't do the desired operation in MODE.
2656 If so, pick a wider mode in which we can do the operation. Convert
2657 to that mode at the start to avoid repeated conversions.
2659 First see what operations we need. These depend on the expression
2660 we are evaluating. (We assume that divxx3 insns exist under the
2661 same conditions that modxx3 insns and that these insns don't normally
2662 fail. If these assumptions are not correct, we may generate less
2663 efficient code in some cases.)
2665 Then see if we find a mode in which we can open-code that operation
2666 (either a division, modulus, or shift). Finally, check for the smallest
2667 mode for which we can do the operation with a library call. */
2669 /* We might want to refine this now that we have division-by-constant
2670 optimization. Since expand_mult_highpart tries so many variants, it is
2671 not straightforward to generalize this. Maybe we should make an array
2672 of possible modes in init_expmed? Save this for GCC 2.7. */
2674 optab1 = (op1_is_pow2 ? (unsignedp ? lshr_optab : ashr_optab)
2675 : (unsignedp ? udiv_optab : sdiv_optab));
2676 optab2 = (op1_is_pow2 ? optab1 : (unsignedp ? udivmod_optab : sdivmod_optab));
2678 for (compute_mode = mode; compute_mode != VOIDmode;
2679 compute_mode = GET_MODE_WIDER_MODE (compute_mode))
2680 if (optab1->handlers[(int) compute_mode].insn_code != CODE_FOR_nothing
2681 || optab2->handlers[(int) compute_mode].insn_code != CODE_FOR_nothing)
2684 if (compute_mode == VOIDmode)
2685 for (compute_mode = mode; compute_mode != VOIDmode;
2686 compute_mode = GET_MODE_WIDER_MODE (compute_mode))
2687 if (optab1->handlers[(int) compute_mode].libfunc
2688 || optab2->handlers[(int) compute_mode].libfunc)
2691 /* If we still couldn't find a mode, use MODE, but we'll probably abort
2693 if (compute_mode == VOIDmode)
2694 compute_mode = mode;
2696 if (target && GET_MODE (target) == compute_mode)
2699 tquotient = gen_reg_rtx (compute_mode);
2701 size = GET_MODE_BITSIZE (compute_mode);
2703 /* It should be possible to restrict the precision to GET_MODE_BITSIZE
2704 (mode), and thereby get better code when OP1 is a constant. Do that for
2705 GCC 2.7. It will require going over all usages of SIZE below. */
2706 size = GET_MODE_BITSIZE (mode);
2709 /* Now convert to the best mode to use. */
2710 if (compute_mode != mode)
2712 op0 = convert_modes (compute_mode, mode, op0, unsignedp);
2713 op1 = convert_modes (compute_mode, mode, op1, unsignedp);
2716 /* If one of the operands is a volatile MEM, copy it into a register. */
2718 if (GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0))
2719 op0 = force_reg (compute_mode, op0);
2720 if (GET_CODE (op1) == MEM && MEM_VOLATILE_P (op1))
2721 op1 = force_reg (compute_mode, op1);
2723 /* If we need the remainder or if OP1 is constant, we need to
2724 put OP0 in a register in case it has any queued subexpressions. */
2725 if (rem_flag || op1_is_constant)
2726 op0 = force_reg (compute_mode, op0);
2728 last = get_last_insn ();
2730 /* Promote floor rouding to trunc rounding for unsigned operations. */
2733 if (code == FLOOR_DIV_EXPR)
2734 code = TRUNC_DIV_EXPR;
2735 if (code == FLOOR_MOD_EXPR)
2736 code = TRUNC_MOD_EXPR;
2739 if (op1 != const0_rtx)
2742 case TRUNC_MOD_EXPR:
2743 case TRUNC_DIV_EXPR:
2744 if (op1_is_constant && HOST_BITS_PER_WIDE_INT >= size)
2748 unsigned HOST_WIDE_INT mh, ml;
2749 int pre_shift, post_shift;
2751 unsigned HOST_WIDE_INT d = INTVAL (op1);
2753 if (EXACT_POWER_OF_2_OR_ZERO_P (d))
2755 pre_shift = floor_log2 (d);
2758 remainder = expand_binop (compute_mode, and_optab, op0,
2759 GEN_INT (((HOST_WIDE_INT) 1 << pre_shift) - 1),
2763 return gen_lowpart (mode, remainder);
2765 quotient = expand_shift (RSHIFT_EXPR, compute_mode, op0,
2766 build_int_2 (pre_shift, 0),
2769 else if (d >= ((unsigned HOST_WIDE_INT) 1 << (size - 1)))
2771 /* Most significant bit of divisor is set, emit a scc insn.
2772 emit_store_flag needs to be passed a place for the
2774 quotient = emit_store_flag (tquotient, GEU, op0, op1,
2775 compute_mode, 1, 1);
2776 /* Can emit_store_flag have failed? */
2782 /* Find a suitable multiplier and right shift count instead
2783 of multiplying with D. */
2785 mh = choose_multiplier (d, size, size,
2786 &ml, &post_shift, &dummy);
2788 /* If the suggested multiplier is more than SIZE bits, we
2789 can do better for even divisors, using an initial right
2791 if (mh != 0 && (d & 1) == 0)
2793 pre_shift = floor_log2 (d & -d);
2794 mh = choose_multiplier (d >> pre_shift, size,
2796 &ml, &post_shift, &dummy);
2807 t1 = expand_mult_highpart (compute_mode, op0, ml,
2811 t2 = force_operand (gen_rtx (MINUS, compute_mode,
2814 t3 = expand_shift (RSHIFT_EXPR, compute_mode, t2,
2815 build_int_2 (1, 0), NULL_RTX, 1);
2816 t4 = force_operand (gen_rtx (PLUS, compute_mode,
2819 quotient = expand_shift (RSHIFT_EXPR, compute_mode, t4,
2820 build_int_2 (post_shift - 1,
2828 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
2829 build_int_2 (pre_shift, 0),
2831 t2 = expand_mult_highpart (compute_mode, t1, ml,
2835 quotient = expand_shift (RSHIFT_EXPR, compute_mode, t2,
2836 build_int_2 (post_shift, 0),
2841 insn = get_last_insn ();
2843 && (set = single_set (insn)) != 0
2844 && SET_DEST (set) == quotient)
2846 = gen_rtx (EXPR_LIST, REG_EQUAL,
2847 gen_rtx (UDIV, compute_mode, op0, op1),
2850 else /* TRUNC_DIV, signed */
2852 unsigned HOST_WIDE_INT ml;
2853 int lgup, post_shift;
2854 HOST_WIDE_INT d = INTVAL (op1);
2855 unsigned HOST_WIDE_INT abs_d = d >= 0 ? d : -d;
2857 /* n rem d = n rem -d */
2858 if (rem_flag && d < 0)
2861 op1 = GEN_INT (abs_d);
2867 quotient = expand_unop (compute_mode, neg_optab, op0,
2869 else if (EXACT_POWER_OF_2_OR_ZERO_P (d)
2870 && (rem_flag ? smod_pow2_cheap : sdiv_pow2_cheap))
2872 else if (EXACT_POWER_OF_2_OR_ZERO_P (abs_d))
2874 lgup = floor_log2 (abs_d);
2875 if (abs_d != 2 && BRANCH_COST < 3)
2877 rtx label = gen_label_rtx ();
2880 t1 = copy_to_mode_reg (compute_mode, op0);
2881 emit_cmp_insn (t1, const0_rtx, GE,
2882 NULL_RTX, compute_mode, 0, 0);
2883 emit_jump_insn (gen_bge (label));
2884 expand_inc (t1, GEN_INT (abs_d - 1));
2886 quotient = expand_shift (RSHIFT_EXPR, compute_mode, t1,
2887 build_int_2 (lgup, 0),
2893 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
2894 build_int_2 (size - 1, 0),
2896 t2 = expand_shift (RSHIFT_EXPR, compute_mode, t1,
2897 build_int_2 (size - lgup, 0),
2899 t3 = force_operand (gen_rtx (PLUS, compute_mode,
2902 quotient = expand_shift (RSHIFT_EXPR, compute_mode, t3,
2903 build_int_2 (lgup, 0),
2909 insn = get_last_insn ();
2911 && (set = single_set (insn)) != 0
2912 && SET_DEST (set) == quotient)
2914 = gen_rtx (EXPR_LIST, REG_EQUAL,
2915 gen_rtx (DIV, compute_mode, op0,
2919 quotient = expand_unop (compute_mode, neg_optab,
2920 quotient, quotient, 0);
2925 choose_multiplier (abs_d, size, size - 1,
2926 &ml, &post_shift, &lgup);
2927 if (ml < (unsigned HOST_WIDE_INT) 1 << (size - 1))
2931 t1 = expand_mult_highpart (compute_mode, op0, ml,
2935 t2 = expand_shift (RSHIFT_EXPR, compute_mode, t1,
2936 build_int_2 (post_shift, 0), NULL_RTX, 0);
2937 t3 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
2938 build_int_2 (size - 1, 0), NULL_RTX, 0);
2940 quotient = force_operand (gen_rtx (MINUS, compute_mode, t3, t2),
2943 quotient = force_operand (gen_rtx (MINUS, compute_mode, t2, t3),
2950 ml |= (~(unsigned HOST_WIDE_INT) 0) << (size - 1);
2951 t1 = expand_mult_highpart (compute_mode, op0, ml,
2955 t2 = force_operand (gen_rtx (PLUS, compute_mode, t1, op0),
2957 t3 = expand_shift (RSHIFT_EXPR, compute_mode, t2,
2958 build_int_2 (post_shift, 0), NULL_RTX, 0);
2959 t4 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
2960 build_int_2 (size - 1, 0), NULL_RTX, 0);
2962 quotient = force_operand (gen_rtx (MINUS, compute_mode, t4, t3),
2965 quotient = force_operand (gen_rtx (MINUS, compute_mode, t3, t4),
2970 insn = get_last_insn ();
2972 && (set = single_set (insn)) != 0
2973 && SET_DEST (set) == quotient)
2975 = gen_rtx (EXPR_LIST, REG_EQUAL,
2976 gen_rtx (DIV, compute_mode, op0, op1),
2982 delete_insns_since (last);
2985 case FLOOR_DIV_EXPR:
2986 case FLOOR_MOD_EXPR:
2987 /* We will come here only for signed operations. */
2988 if (op1_is_constant && HOST_BITS_PER_WIDE_INT >= size)
2990 unsigned HOST_WIDE_INT mh, ml;
2991 int pre_shift, lgup, post_shift;
2992 HOST_WIDE_INT d = INTVAL (op1);
2996 /* We could just as easily deal with negative constants here,
2997 but it does not seem worth the trouble for GCC 2.6. */
2998 if (EXACT_POWER_OF_2_OR_ZERO_P (d))
3000 pre_shift = floor_log2 (d);
3003 remainder = expand_binop (compute_mode, and_optab, op0,
3004 GEN_INT (((HOST_WIDE_INT) 1 << pre_shift) - 1),
3005 remainder, 0, OPTAB_LIB_WIDEN);
3007 return gen_lowpart (mode, remainder);
3009 quotient = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3010 build_int_2 (pre_shift, 0),
3017 mh = choose_multiplier (d, size, size - 1,
3018 &ml, &post_shift, &lgup);
3022 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3023 build_int_2 (size - 1, 0), NULL_RTX, 0);
3024 t2 = expand_binop (compute_mode, xor_optab, op0, t1,
3025 NULL_RTX, 0, OPTAB_WIDEN);
3026 t3 = expand_mult_highpart (compute_mode, t2, ml,
3030 t4 = expand_shift (RSHIFT_EXPR, compute_mode, t3,
3031 build_int_2 (post_shift, 0),
3033 quotient = expand_binop (compute_mode, xor_optab,
3034 t4, t1, tquotient, 0,
3041 rtx nsign, t1, t2, t3, t4;
3042 t1 = force_operand (gen_rtx (PLUS, compute_mode,
3043 op0, constm1_rtx), NULL_RTX);
3044 t2 = expand_binop (compute_mode, ior_optab, op0, t1, NULL_RTX,
3046 nsign = expand_shift (RSHIFT_EXPR, compute_mode, t2,
3047 build_int_2 (size - 1, 0), NULL_RTX, 0);
3048 t3 = force_operand (gen_rtx (MINUS, compute_mode, t1, nsign),
3050 t4 = expand_divmod (0, TRUNC_DIV_EXPR, compute_mode, t3, op1,
3055 t5 = expand_unop (compute_mode, one_cmpl_optab, nsign,
3057 quotient = force_operand (gen_rtx (PLUS, compute_mode,
3066 delete_insns_since (last);
3068 /* Try using an instruction that produces both the quotient and
3069 remainder, using truncation. We can easily compensate the quotient
3070 or remainder to get floor rounding, once we have the remainder.
3071 Notice that we compute also the final remainder value here,
3072 and return the result right away. */
3074 target = gen_reg_rtx (compute_mode);
3078 quotient = gen_reg_rtx (compute_mode);
3083 remainder = gen_reg_rtx (compute_mode);
3086 if (expand_twoval_binop (sdivmod_optab, op0, op1,
3087 quotient, remainder, 0))
3089 /* This could be computed with a branch-less sequence.
3090 Save that for later. */
3092 rtx label = gen_label_rtx ();
3093 emit_cmp_insn (remainder, const0_rtx, EQ, NULL_RTX,
3094 compute_mode, 0, 0);
3095 emit_jump_insn (gen_beq (label));
3096 tem = expand_binop (compute_mode, xor_optab, op0, op1,
3097 NULL_RTX, 0, OPTAB_WIDEN);
3098 emit_cmp_insn (tem, const0_rtx, GE, NULL_RTX, compute_mode, 0, 0);
3099 emit_jump_insn (gen_bge (label));
3100 expand_dec (quotient, const1_rtx);
3101 expand_inc (remainder, op1);
3103 return gen_lowpart (mode, rem_flag ? remainder : quotient);
3106 /* No luck with division elimination or divmod. Have to do it
3107 by conditionally adjusting op0 *and* the result. */
3109 rtx label1, label2, label3, label4, label5;
3113 quotient = gen_reg_rtx (compute_mode);
3114 adjusted_op0 = copy_to_mode_reg (compute_mode, op0);
3115 label1 = gen_label_rtx ();
3116 label2 = gen_label_rtx ();
3117 label3 = gen_label_rtx ();
3118 label4 = gen_label_rtx ();
3119 label5 = gen_label_rtx ();
3120 emit_cmp_insn (op1, const0_rtx, LT, NULL_RTX, compute_mode, 0, 0);
3121 emit_jump_insn (gen_blt (label2));
3122 emit_cmp_insn (adjusted_op0, const0_rtx, LT, NULL_RTX,
3123 compute_mode, 0, 0);
3124 emit_jump_insn (gen_blt (label1));
3125 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
3126 quotient, 0, OPTAB_LIB_WIDEN);
3127 if (tem != quotient)
3128 emit_move_insn (quotient, tem);
3129 emit_jump_insn (gen_jump (label5));
3131 emit_label (label1);
3132 expand_inc (adjusted_op0, const1_rtx);
3133 emit_jump_insn (gen_jump (label4));
3135 emit_label (label2);
3136 emit_cmp_insn (adjusted_op0, const0_rtx, GT, NULL_RTX,
3137 compute_mode, 0, 0);
3138 emit_jump_insn (gen_bgt (label3));
3139 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
3140 quotient, 0, OPTAB_LIB_WIDEN);
3141 if (tem != quotient)
3142 emit_move_insn (quotient, tem);
3143 emit_jump_insn (gen_jump (label5));
3145 emit_label (label3);
3146 expand_dec (adjusted_op0, const1_rtx);
3147 emit_label (label4);
3148 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
3149 quotient, 0, OPTAB_LIB_WIDEN);
3150 if (tem != quotient)
3151 emit_move_insn (quotient, tem);
3152 expand_dec (quotient, const1_rtx);
3153 emit_label (label5);
3161 if (op1_is_constant && EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1)))
3164 unsigned HOST_WIDE_INT d = INTVAL (op1);
3165 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3166 build_int_2 (floor_log2 (d), 0),
3168 t2 = expand_binop (compute_mode, and_optab, op0,
3170 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3171 t3 = gen_reg_rtx (compute_mode);
3172 t3 = emit_store_flag (t3, NE, t2, const0_rtx,
3173 compute_mode, 1, 1);
3177 lab = gen_label_rtx ();
3178 emit_cmp_insn (t2, const0_rtx, EQ, NULL_RTX,
3179 compute_mode, 0, 0);
3180 emit_jump_insn (gen_beq (lab));
3181 expand_inc (t1, const1_rtx);
3186 quotient = force_operand (gen_rtx (PLUS, compute_mode,
3192 /* Try using an instruction that produces both the quotient and
3193 remainder, using truncation. We can easily compensate the
3194 quotient or remainder to get ceiling rounding, once we have the
3195 remainder. Notice that we compute also the final remainder
3196 value here, and return the result right away. */
3198 target = gen_reg_rtx (compute_mode);
3202 quotient = gen_reg_rtx (compute_mode);
3207 remainder = gen_reg_rtx (compute_mode);
3210 if (expand_twoval_binop (udivmod_optab, op0, op1, quotient,
3213 /* This could be computed with a branch-less sequence.
3214 Save that for later. */
3215 rtx label = gen_label_rtx ();
3216 emit_cmp_insn (remainder, const0_rtx, EQ, NULL_RTX,
3217 compute_mode, 0, 0);
3218 emit_jump_insn (gen_beq (label));
3219 expand_inc (quotient, const1_rtx);
3220 expand_dec (remainder, op1);
3222 return gen_lowpart (mode, rem_flag ? remainder : quotient);
3225 /* No luck with division elimination or divmod. Have to do it
3226 by conditionally adjusting op0 *and* the result. */
3229 rtx adjusted_op0, tem;
3231 quotient = gen_reg_rtx (compute_mode);
3232 adjusted_op0 = copy_to_mode_reg (compute_mode, op0);
3233 label1 = gen_label_rtx ();
3234 label2 = gen_label_rtx ();
3235 emit_cmp_insn (adjusted_op0, const0_rtx, NE, NULL_RTX,
3236 compute_mode, 0, 0);
3237 emit_jump_insn (gen_bne (label1));
3238 emit_move_insn (quotient, const0_rtx);
3239 emit_jump_insn (gen_jump (label2));
3241 emit_label (label1);
3242 expand_dec (adjusted_op0, const1_rtx);
3243 tem = expand_binop (compute_mode, udiv_optab, adjusted_op0, op1,
3244 quotient, 1, OPTAB_LIB_WIDEN);
3245 if (tem != quotient)
3246 emit_move_insn (quotient, tem);
3247 expand_inc (quotient, const1_rtx);
3248 emit_label (label2);
3253 /* Try using an instruction that produces both the quotient and
3254 remainder, using truncation. We can easily compensate the
3255 quotient or remainder to get ceiling rounding, once we have the
3256 remainder. Notice that we compute also the final remainder
3257 value here, and return the result right away. */
3259 target = gen_reg_rtx (compute_mode);
3263 quotient = gen_reg_rtx (compute_mode);
3268 remainder = gen_reg_rtx (compute_mode);
3271 if (expand_twoval_binop (sdivmod_optab, op0, op1, quotient,
3274 /* This could be computed with a branch-less sequence.
3275 Save that for later. */
3277 rtx label = gen_label_rtx ();
3278 emit_cmp_insn (remainder, const0_rtx, EQ, NULL_RTX,
3279 compute_mode, 0, 0);
3280 emit_jump_insn (gen_beq (label));
3281 tem = expand_binop (compute_mode, xor_optab, op0, op1,
3282 NULL_RTX, 0, OPTAB_WIDEN);
3283 emit_cmp_insn (tem, const0_rtx, LT, NULL_RTX,
3284 compute_mode, 0, 0);
3285 emit_jump_insn (gen_blt (label));
3286 expand_inc (quotient, const1_rtx);
3287 expand_dec (remainder, op1);
3289 return gen_lowpart (mode, rem_flag ? remainder : quotient);
3292 /* No luck with division elimination or divmod. Have to do it
3293 by conditionally adjusting op0 *and* the result. */
3295 rtx label1, label2, label3, label4, label5;
3299 quotient = gen_reg_rtx (compute_mode);
3300 adjusted_op0 = copy_to_mode_reg (compute_mode, op0);
3301 label1 = gen_label_rtx ();
3302 label2 = gen_label_rtx ();
3303 label3 = gen_label_rtx ();
3304 label4 = gen_label_rtx ();
3305 label5 = gen_label_rtx ();
3306 emit_cmp_insn (op1, const0_rtx, LT, NULL_RTX,
3307 compute_mode, 0, 0);
3308 emit_jump_insn (gen_blt (label2));
3309 emit_cmp_insn (adjusted_op0, const0_rtx, GT, NULL_RTX,
3310 compute_mode, 0, 0);
3311 emit_jump_insn (gen_bgt (label1));
3312 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
3313 quotient, 0, OPTAB_LIB_WIDEN);
3314 if (tem != quotient)
3315 emit_move_insn (quotient, tem);
3316 emit_jump_insn (gen_jump (label5));
3318 emit_label (label1);
3319 expand_dec (adjusted_op0, const1_rtx);
3320 emit_jump_insn (gen_jump (label4));
3322 emit_label (label2);
3323 emit_cmp_insn (adjusted_op0, const0_rtx, LT, NULL_RTX,
3324 compute_mode, 0, 0);
3325 emit_jump_insn (gen_blt (label3));
3326 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
3327 quotient, 0, OPTAB_LIB_WIDEN);
3328 if (tem != quotient)
3329 emit_move_insn (quotient, tem);
3330 emit_jump_insn (gen_jump (label5));
3332 emit_label (label3);
3333 expand_inc (adjusted_op0, const1_rtx);
3334 emit_label (label4);
3335 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
3336 quotient, 0, OPTAB_LIB_WIDEN);
3337 if (tem != quotient)
3338 emit_move_insn (quotient, tem);
3339 expand_inc (quotient, const1_rtx);
3340 emit_label (label5);
3345 case EXACT_DIV_EXPR:
3346 if (op1_is_constant && HOST_BITS_PER_WIDE_INT >= size)
3348 HOST_WIDE_INT d = INTVAL (op1);
3349 unsigned HOST_WIDE_INT ml;
3353 post_shift = floor_log2 (d & -d);
3354 ml = invert_mod2n (d >> post_shift, size);
3355 t1 = expand_mult (compute_mode, op0, GEN_INT (ml), NULL_RTX,
3357 quotient = expand_shift (RSHIFT_EXPR, compute_mode, t1,
3358 build_int_2 (post_shift, 0),
3359 NULL_RTX, unsignedp);
3361 insn = get_last_insn ();
3363 = gen_rtx (EXPR_LIST, REG_EQUAL,
3364 gen_rtx (unsignedp ? UDIV : DIV, compute_mode,
3370 case ROUND_DIV_EXPR:
3371 case ROUND_MOD_EXPR:
3372 /* The code that used to be here was wrong, and nothing really
3382 /* Try to produce the remainder directly without a library call. */
3383 remainder = sign_expand_binop (compute_mode, umod_optab, smod_optab,
3385 unsignedp, OPTAB_WIDEN);
3388 /* No luck there. Can we do remainder and divide at once
3389 without a library call? */
3390 remainder = gen_reg_rtx (compute_mode);
3391 if (! expand_twoval_binop ((unsignedp
3395 NULL_RTX, remainder, unsignedp))
3400 return gen_lowpart (mode, remainder);
3403 /* Produce the quotient. */
3404 /* Try a quotient insn, but not a library call. */
3405 quotient = sign_expand_binop (compute_mode, udiv_optab, sdiv_optab,
3406 op0, op1, rem_flag ? NULL_RTX : target,
3407 unsignedp, OPTAB_WIDEN);
3410 /* No luck there. Try a quotient-and-remainder insn,
3411 keeping the quotient alone. */
3412 quotient = gen_reg_rtx (compute_mode);
3413 if (! expand_twoval_binop (unsignedp ? udivmod_optab : sdivmod_optab,
3415 quotient, NULL_RTX, unsignedp))
3419 /* Still no luck. If we are not computing the remainder,
3420 use a library call for the quotient. */
3421 quotient = sign_expand_binop (compute_mode,
3422 udiv_optab, sdiv_optab,
3424 unsignedp, OPTAB_LIB_WIDEN);
3432 /* No divide instruction either. Use library for remainder. */
3433 remainder = sign_expand_binop (compute_mode, umod_optab, smod_optab,
3435 unsignedp, OPTAB_LIB_WIDEN);
3438 /* We divided. Now finish doing X - Y * (X / Y). */
3439 remainder = expand_mult (compute_mode, quotient, op1,
3440 NULL_RTX, unsignedp);
3441 remainder = expand_binop (compute_mode, sub_optab, op0,
3442 remainder, target, unsignedp,
3447 return gen_lowpart (mode, rem_flag ? remainder : quotient);
3450 /* Return a tree node with data type TYPE, describing the value of X.
3451 Usually this is an RTL_EXPR, if there is no obvious better choice.
3452 X may be an expression, however we only support those expressions
3453 generated by loop.c. */
3462 switch (GET_CODE (x))
3465 t = build_int_2 (INTVAL (x),
3466 TREE_UNSIGNED (type) || INTVAL (x) >= 0 ? 0 : -1);
3467 TREE_TYPE (t) = type;
3471 if (GET_MODE (x) == VOIDmode)
3473 t = build_int_2 (CONST_DOUBLE_LOW (x), CONST_DOUBLE_HIGH (x));
3474 TREE_TYPE (t) = type;
3480 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
3481 t = build_real (type, d);
3487 return fold (build (PLUS_EXPR, type, make_tree (type, XEXP (x, 0)),
3488 make_tree (type, XEXP (x, 1))));
3491 return fold (build (MINUS_EXPR, type, make_tree (type, XEXP (x, 0)),
3492 make_tree (type, XEXP (x, 1))));
3495 return fold (build1 (NEGATE_EXPR, type, make_tree (type, XEXP (x, 0))));
3498 return fold (build (MULT_EXPR, type, make_tree (type, XEXP (x, 0)),
3499 make_tree (type, XEXP (x, 1))));
3502 return fold (build (LSHIFT_EXPR, type, make_tree (type, XEXP (x, 0)),
3503 make_tree (type, XEXP (x, 1))));
3506 return fold (convert (type,
3507 build (RSHIFT_EXPR, unsigned_type (type),
3508 make_tree (unsigned_type (type),
3510 make_tree (type, XEXP (x, 1)))));
3513 return fold (convert (type,
3514 build (RSHIFT_EXPR, signed_type (type),
3515 make_tree (signed_type (type), XEXP (x, 0)),
3516 make_tree (type, XEXP (x, 1)))));
3519 if (TREE_CODE (type) != REAL_TYPE)
3520 t = signed_type (type);
3524 return fold (convert (type,
3525 build (TRUNC_DIV_EXPR, t,
3526 make_tree (t, XEXP (x, 0)),
3527 make_tree (t, XEXP (x, 1)))));
3529 t = unsigned_type (type);
3530 return fold (convert (type,
3531 build (TRUNC_DIV_EXPR, t,
3532 make_tree (t, XEXP (x, 0)),
3533 make_tree (t, XEXP (x, 1)))));
3535 t = make_node (RTL_EXPR);
3536 TREE_TYPE (t) = type;
3537 RTL_EXPR_RTL (t) = x;
3538 /* There are no insns to be output
3539 when this rtl_expr is used. */
3540 RTL_EXPR_SEQUENCE (t) = 0;
3545 /* Return an rtx representing the value of X * MULT + ADD.
3546 TARGET is a suggestion for where to store the result (an rtx).
3547 MODE is the machine mode for the computation.
3548 X and MULT must have mode MODE. ADD may have a different mode.
3549 So can X (defaults to same as MODE).
3550 UNSIGNEDP is non-zero to do unsigned multiplication.
3551 This may emit insns. */
3554 expand_mult_add (x, target, mult, add, mode, unsignedp)
3555 rtx x, target, mult, add;
3556 enum machine_mode mode;
3559 tree type = type_for_mode (mode, unsignedp);
3560 tree add_type = (GET_MODE (add) == VOIDmode
3561 ? type : type_for_mode (GET_MODE (add), unsignedp));
3562 tree result = fold (build (PLUS_EXPR, type,
3563 fold (build (MULT_EXPR, type,
3564 make_tree (type, x),
3565 make_tree (type, mult))),
3566 make_tree (add_type, add)));
3568 return expand_expr (result, target, VOIDmode, 0);
3571 /* Compute the logical-and of OP0 and OP1, storing it in TARGET
3572 and returning TARGET.
3574 If TARGET is 0, a pseudo-register or constant is returned. */
3577 expand_and (op0, op1, target)
3578 rtx op0, op1, target;
3580 enum machine_mode mode = VOIDmode;
3583 if (GET_MODE (op0) != VOIDmode)
3584 mode = GET_MODE (op0);
3585 else if (GET_MODE (op1) != VOIDmode)
3586 mode = GET_MODE (op1);
3588 if (mode != VOIDmode)
3589 tem = expand_binop (mode, and_optab, op0, op1, target, 0, OPTAB_LIB_WIDEN);
3590 else if (GET_CODE (op0) == CONST_INT && GET_CODE (op1) == CONST_INT)
3591 tem = GEN_INT (INTVAL (op0) & INTVAL (op1));
3597 else if (tem != target)
3598 emit_move_insn (target, tem);
3602 /* Emit a store-flags instruction for comparison CODE on OP0 and OP1
3603 and storing in TARGET. Normally return TARGET.
3604 Return 0 if that cannot be done.
3606 MODE is the mode to use for OP0 and OP1 should they be CONST_INTs. If
3607 it is VOIDmode, they cannot both be CONST_INT.
3609 UNSIGNEDP is for the case where we have to widen the operands
3610 to perform the operation. It says to use zero-extension.
3612 NORMALIZEP is 1 if we should convert the result to be either zero
3613 or one one. Normalize is -1 if we should convert the result to be
3614 either zero or -1. If NORMALIZEP is zero, the result will be left
3615 "raw" out of the scc insn. */
3618 emit_store_flag (target, code, op0, op1, mode, unsignedp, normalizep)
3622 enum machine_mode mode;
3627 enum insn_code icode;
3628 enum machine_mode compare_mode;
3629 enum machine_mode target_mode = GET_MODE (target);
3632 rtx pattern, comparison;
3634 if (mode == VOIDmode)
3635 mode = GET_MODE (op0);
3637 /* If one operand is constant, make it the second one. Only do this
3638 if the other operand is not constant as well. */
3640 if ((CONSTANT_P (op0) && ! CONSTANT_P (op1))
3641 || (GET_CODE (op0) == CONST_INT && GET_CODE (op1) != CONST_INT))
3646 code = swap_condition (code);
3649 /* For some comparisons with 1 and -1, we can convert this to
3650 comparisons with zero. This will often produce more opportunities for
3651 store-flag insns. */
3656 if (op1 == const1_rtx)
3657 op1 = const0_rtx, code = LE;
3660 if (op1 == constm1_rtx)
3661 op1 = const0_rtx, code = LT;
3664 if (op1 == const1_rtx)
3665 op1 = const0_rtx, code = GT;
3668 if (op1 == constm1_rtx)
3669 op1 = const0_rtx, code = GE;
3672 if (op1 == const1_rtx)
3673 op1 = const0_rtx, code = NE;
3676 if (op1 == const1_rtx)
3677 op1 = const0_rtx, code = EQ;
3681 /* From now on, we won't change CODE, so set ICODE now. */
3682 icode = setcc_gen_code[(int) code];
3684 /* If this is A < 0 or A >= 0, we can do this by taking the ones
3685 complement of A (for GE) and shifting the sign bit to the low bit. */
3686 if (op1 == const0_rtx && (code == LT || code == GE)
3687 && GET_MODE_CLASS (mode) == MODE_INT
3688 && (normalizep || STORE_FLAG_VALUE == 1
3689 || (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3690 && (STORE_FLAG_VALUE
3691 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1)))))
3695 /* If the result is to be wider than OP0, it is best to convert it
3696 first. If it is to be narrower, it is *incorrect* to convert it
3698 if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (mode))
3700 op0 = protect_from_queue (op0, 0);
3701 op0 = convert_modes (target_mode, mode, op0, 0);
3705 if (target_mode != mode)
3709 op0 = expand_unop (mode, one_cmpl_optab, op0, subtarget, 0);
3711 if (normalizep || STORE_FLAG_VALUE == 1)
3712 /* If we are supposed to produce a 0/1 value, we want to do
3713 a logical shift from the sign bit to the low-order bit; for
3714 a -1/0 value, we do an arithmetic shift. */
3715 op0 = expand_shift (RSHIFT_EXPR, mode, op0,
3716 size_int (GET_MODE_BITSIZE (mode) - 1),
3717 subtarget, normalizep != -1);
3719 if (mode != target_mode)
3720 op0 = convert_modes (target_mode, mode, op0, 0);
3725 if (icode != CODE_FOR_nothing)
3727 /* We think we may be able to do this with a scc insn. Emit the
3728 comparison and then the scc insn.
3730 compare_from_rtx may call emit_queue, which would be deleted below
3731 if the scc insn fails. So call it ourselves before setting LAST. */
3734 last = get_last_insn ();
3737 = compare_from_rtx (op0, op1, code, unsignedp, mode, NULL_RTX, 0);
3738 if (GET_CODE (comparison) == CONST_INT)
3739 return (comparison == const0_rtx ? const0_rtx
3740 : normalizep == 1 ? const1_rtx
3741 : normalizep == -1 ? constm1_rtx
3744 /* If the code of COMPARISON doesn't match CODE, something is
3745 wrong; we can no longer be sure that we have the operation.
3746 We could handle this case, but it should not happen. */
3748 if (GET_CODE (comparison) != code)
3751 /* Get a reference to the target in the proper mode for this insn. */
3752 compare_mode = insn_operand_mode[(int) icode][0];
3754 if (preserve_subexpressions_p ()
3755 || ! (*insn_operand_predicate[(int) icode][0]) (subtarget, compare_mode))
3756 subtarget = gen_reg_rtx (compare_mode);
3758 pattern = GEN_FCN (icode) (subtarget);
3761 emit_insn (pattern);
3763 /* If we are converting to a wider mode, first convert to
3764 TARGET_MODE, then normalize. This produces better combining
3765 opportunities on machines that have a SIGN_EXTRACT when we are
3766 testing a single bit. This mostly benefits the 68k.
3768 If STORE_FLAG_VALUE does not have the sign bit set when
3769 interpreted in COMPARE_MODE, we can do this conversion as
3770 unsigned, which is usually more efficient. */
3771 if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (compare_mode))
3773 convert_move (target, subtarget,
3774 (GET_MODE_BITSIZE (compare_mode)
3775 <= HOST_BITS_PER_WIDE_INT)
3776 && 0 == (STORE_FLAG_VALUE
3777 & ((HOST_WIDE_INT) 1
3778 << (GET_MODE_BITSIZE (compare_mode) -1))));
3780 compare_mode = target_mode;
3785 /* If we want to keep subexpressions around, don't reuse our
3788 if (preserve_subexpressions_p ())
3791 /* Now normalize to the proper value in COMPARE_MODE. Sometimes
3792 we don't have to do anything. */
3793 if (normalizep == 0 || normalizep == STORE_FLAG_VALUE)
3795 else if (normalizep == - STORE_FLAG_VALUE)
3796 op0 = expand_unop (compare_mode, neg_optab, op0, subtarget, 0);
3798 /* We don't want to use STORE_FLAG_VALUE < 0 below since this
3799 makes it hard to use a value of just the sign bit due to
3800 ANSI integer constant typing rules. */
3801 else if (GET_MODE_BITSIZE (compare_mode) <= HOST_BITS_PER_WIDE_INT
3802 && (STORE_FLAG_VALUE
3803 & ((HOST_WIDE_INT) 1
3804 << (GET_MODE_BITSIZE (compare_mode) - 1))))
3805 op0 = expand_shift (RSHIFT_EXPR, compare_mode, op0,
3806 size_int (GET_MODE_BITSIZE (compare_mode) - 1),
3807 subtarget, normalizep == 1);
3808 else if (STORE_FLAG_VALUE & 1)
3810 op0 = expand_and (op0, const1_rtx, subtarget);
3811 if (normalizep == -1)
3812 op0 = expand_unop (compare_mode, neg_optab, op0, op0, 0);
3817 /* If we were converting to a smaller mode, do the
3819 if (target_mode != compare_mode)
3821 convert_move (target, op0, 0);
3830 delete_insns_since (last);
3832 subtarget = target_mode == mode ? target : 0;
3834 /* If we reached here, we can't do this with a scc insn. However, there
3835 are some comparisons that can be done directly. For example, if
3836 this is an equality comparison of integers, we can try to exclusive-or
3837 (or subtract) the two operands and use a recursive call to try the
3838 comparison with zero. Don't do any of these cases if branches are
3842 && GET_MODE_CLASS (mode) == MODE_INT && (code == EQ || code == NE)
3843 && op1 != const0_rtx)
3845 tem = expand_binop (mode, xor_optab, op0, op1, subtarget, 1,
3849 tem = expand_binop (mode, sub_optab, op0, op1, subtarget, 1,
3852 tem = emit_store_flag (target, code, tem, const0_rtx,
3853 mode, unsignedp, normalizep);
3855 delete_insns_since (last);
3859 /* Some other cases we can do are EQ, NE, LE, and GT comparisons with
3860 the constant zero. Reject all other comparisons at this point. Only
3861 do LE and GT if branches are expensive since they are expensive on
3862 2-operand machines. */
3864 if (BRANCH_COST == 0
3865 || GET_MODE_CLASS (mode) != MODE_INT || op1 != const0_rtx
3866 || (code != EQ && code != NE
3867 && (BRANCH_COST <= 1 || (code != LE && code != GT))))
3870 /* See what we need to return. We can only return a 1, -1, or the
3873 if (normalizep == 0)
3875 if (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
3876 normalizep = STORE_FLAG_VALUE;
3878 else if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3879 && (STORE_FLAG_VALUE
3880 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1)))
3886 /* Try to put the result of the comparison in the sign bit. Assume we can't
3887 do the necessary operation below. */
3891 /* To see if A <= 0, compute (A | (A - 1)). A <= 0 iff that result has
3892 the sign bit set. */
3896 /* This is destructive, so SUBTARGET can't be OP0. */
3897 if (rtx_equal_p (subtarget, op0))
3900 tem = expand_binop (mode, sub_optab, op0, const1_rtx, subtarget, 0,
3903 tem = expand_binop (mode, ior_optab, op0, tem, subtarget, 0,
3907 /* To see if A > 0, compute (((signed) A) << BITS) - A, where BITS is the
3908 number of bits in the mode of OP0, minus one. */
3912 if (rtx_equal_p (subtarget, op0))
3915 tem = expand_shift (RSHIFT_EXPR, mode, op0,
3916 size_int (GET_MODE_BITSIZE (mode) - 1),
3918 tem = expand_binop (mode, sub_optab, tem, op0, subtarget, 0,
3922 if (code == EQ || code == NE)
3924 /* For EQ or NE, one way to do the comparison is to apply an operation
3925 that converts the operand into a positive number if it is non-zero
3926 or zero if it was originally zero. Then, for EQ, we subtract 1 and
3927 for NE we negate. This puts the result in the sign bit. Then we
3928 normalize with a shift, if needed.
3930 Two operations that can do the above actions are ABS and FFS, so try
3931 them. If that doesn't work, and MODE is smaller than a full word,
3932 we can use zero-extension to the wider mode (an unsigned conversion)
3933 as the operation. */
3935 if (abs_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
3936 tem = expand_unop (mode, abs_optab, op0, subtarget, 1);
3937 else if (ffs_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
3938 tem = expand_unop (mode, ffs_optab, op0, subtarget, 1);
3939 else if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3941 op0 = protect_from_queue (op0, 0);
3942 tem = convert_modes (word_mode, mode, op0, 1);
3949 tem = expand_binop (mode, sub_optab, tem, const1_rtx, subtarget,
3952 tem = expand_unop (mode, neg_optab, tem, subtarget, 0);
3955 /* If we couldn't do it that way, for NE we can "or" the two's complement
3956 of the value with itself. For EQ, we take the one's complement of
3957 that "or", which is an extra insn, so we only handle EQ if branches
3960 if (tem == 0 && (code == NE || BRANCH_COST > 1))
3962 if (rtx_equal_p (subtarget, op0))
3965 tem = expand_unop (mode, neg_optab, op0, subtarget, 0);
3966 tem = expand_binop (mode, ior_optab, tem, op0, subtarget, 0,
3969 if (tem && code == EQ)
3970 tem = expand_unop (mode, one_cmpl_optab, tem, subtarget, 0);
3974 if (tem && normalizep)
3975 tem = expand_shift (RSHIFT_EXPR, mode, tem,
3976 size_int (GET_MODE_BITSIZE (mode) - 1),
3977 tem, normalizep == 1);
3979 if (tem && GET_MODE (tem) != target_mode)
3981 convert_move (target, tem, 0);
3986 delete_insns_since (last);
3990 emit_jump_insn ((*bcc_gen_fctn[(int) code]) (label));
3991 emit_move_insn (target, const1_rtx);