1 /* Medium-level subroutines: convert bit-field store and extract
2 and shifts, multiplies and divides to rtl instructions.
3 Copyright (C) 1987, 88, 89, 92-97, 1998 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
30 #include "insn-flags.h"
31 #include "insn-codes.h"
32 #include "insn-config.h"
37 static void store_fixed_bit_field PROTO((rtx, int, int, int, rtx, int));
38 static void store_split_bit_field PROTO((rtx, int, int, rtx, int));
39 static rtx extract_fixed_bit_field PROTO((enum machine_mode, rtx, int,
40 int, int, rtx, int, int));
41 static rtx mask_rtx PROTO((enum machine_mode, int,
43 static rtx lshift_value PROTO((enum machine_mode, rtx,
45 static rtx extract_split_bit_field PROTO((rtx, int, int, int, int));
46 static void do_cmp_and_jump PROTO((rtx, rtx, enum rtx_code,
47 enum machine_mode, rtx));
49 /* Non-zero means divides or modulus operations are relatively cheap for
50 powers of two, so don't use branches; emit the operation instead.
51 Usually, this will mean that the MD file will emit non-branch
54 static int sdiv_pow2_cheap, smod_pow2_cheap;
56 #ifndef SLOW_UNALIGNED_ACCESS
57 #define SLOW_UNALIGNED_ACCESS STRICT_ALIGNMENT
60 /* For compilers that support multiple targets with different word sizes,
61 MAX_BITS_PER_WORD contains the biggest value of BITS_PER_WORD. An example
62 is the H8/300(H) compiler. */
64 #ifndef MAX_BITS_PER_WORD
65 #define MAX_BITS_PER_WORD BITS_PER_WORD
68 /* Cost of various pieces of RTL. Note that some of these are indexed by
69 shift count and some by mode. */
70 static int add_cost, negate_cost, zero_cost;
71 static int shift_cost[MAX_BITS_PER_WORD];
72 static int shiftadd_cost[MAX_BITS_PER_WORD];
73 static int shiftsub_cost[MAX_BITS_PER_WORD];
74 static int mul_cost[NUM_MACHINE_MODES];
75 static int div_cost[NUM_MACHINE_MODES];
76 static int mul_widen_cost[NUM_MACHINE_MODES];
77 static int mul_highpart_cost[NUM_MACHINE_MODES];
83 /* This is "some random pseudo register" for purposes of calling recog
84 to see what insns exist. */
85 rtx reg = gen_rtx_REG (word_mode, 10000);
86 rtx shift_insn, shiftadd_insn, shiftsub_insn;
89 enum machine_mode mode, wider_mode;
93 /* Since we are on the permanent obstack, we must be sure we save this
94 spot AFTER we call start_sequence, since it will reuse the rtl it
96 free_point = (char *) oballoc (0);
98 reg = gen_rtx_REG (word_mode, 10000);
100 zero_cost = rtx_cost (const0_rtx, 0);
101 add_cost = rtx_cost (gen_rtx_PLUS (word_mode, reg, reg), SET);
103 shift_insn = emit_insn (gen_rtx_SET (VOIDmode, reg,
104 gen_rtx_ASHIFT (word_mode, reg,
108 = emit_insn (gen_rtx_SET (VOIDmode, reg,
109 gen_rtx_PLUS (word_mode,
110 gen_rtx_MULT (word_mode,
115 = emit_insn (gen_rtx_SET (VOIDmode, reg,
116 gen_rtx_MINUS (word_mode,
117 gen_rtx_MULT (word_mode,
124 shiftadd_cost[0] = shiftsub_cost[0] = add_cost;
126 for (m = 1; m < MAX_BITS_PER_WORD; m++)
128 shift_cost[m] = shiftadd_cost[m] = shiftsub_cost[m] = 32000;
130 XEXP (SET_SRC (PATTERN (shift_insn)), 1) = GEN_INT (m);
131 if (recog (PATTERN (shift_insn), shift_insn, &dummy) >= 0)
132 shift_cost[m] = rtx_cost (SET_SRC (PATTERN (shift_insn)), SET);
134 XEXP (XEXP (SET_SRC (PATTERN (shiftadd_insn)), 0), 1)
135 = GEN_INT ((HOST_WIDE_INT) 1 << m);
136 if (recog (PATTERN (shiftadd_insn), shiftadd_insn, &dummy) >= 0)
137 shiftadd_cost[m] = rtx_cost (SET_SRC (PATTERN (shiftadd_insn)), SET);
139 XEXP (XEXP (SET_SRC (PATTERN (shiftsub_insn)), 0), 1)
140 = GEN_INT ((HOST_WIDE_INT) 1 << m);
141 if (recog (PATTERN (shiftsub_insn), shiftsub_insn, &dummy) >= 0)
142 shiftsub_cost[m] = rtx_cost (SET_SRC (PATTERN (shiftsub_insn)), SET);
145 negate_cost = rtx_cost (gen_rtx_NEG (word_mode, reg), SET);
148 = (rtx_cost (gen_rtx_DIV (word_mode, reg, GEN_INT (32)), SET)
151 = (rtx_cost (gen_rtx_MOD (word_mode, reg, GEN_INT (32)), SET)
154 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
156 mode = GET_MODE_WIDER_MODE (mode))
158 reg = gen_rtx_REG (mode, 10000);
159 div_cost[(int) mode] = rtx_cost (gen_rtx_UDIV (mode, reg, reg), SET);
160 mul_cost[(int) mode] = rtx_cost (gen_rtx_MULT (mode, reg, reg), SET);
161 wider_mode = GET_MODE_WIDER_MODE (mode);
162 if (wider_mode != VOIDmode)
164 mul_widen_cost[(int) wider_mode]
165 = rtx_cost (gen_rtx_MULT (wider_mode,
166 gen_rtx_ZERO_EXTEND (wider_mode, reg),
167 gen_rtx_ZERO_EXTEND (wider_mode, reg)),
169 mul_highpart_cost[(int) mode]
170 = rtx_cost (gen_rtx_TRUNCATE
172 gen_rtx_LSHIFTRT (wider_mode,
173 gen_rtx_MULT (wider_mode,
178 GEN_INT (GET_MODE_BITSIZE (mode)))),
183 /* Free the objects we just allocated. */
188 /* Return an rtx representing minus the value of X.
189 MODE is the intended mode of the result,
190 useful if X is a CONST_INT. */
194 enum machine_mode mode;
197 rtx result = simplify_unary_operation (NEG, mode, x, mode);
200 result = expand_unop (mode, neg_optab, x, NULL_RTX, 0);
205 /* Generate code to store value from rtx VALUE
206 into a bit-field within structure STR_RTX
207 containing BITSIZE bits starting at bit BITNUM.
208 FIELDMODE is the machine-mode of the FIELD_DECL node for this field.
209 ALIGN is the alignment that STR_RTX is known to have, measured in bytes.
210 TOTAL_SIZE is the size of the structure in bytes, or -1 if varying. */
212 /* ??? Note that there are two different ideas here for how
213 to determine the size to count bits within, for a register.
214 One is BITS_PER_WORD, and the other is the size of operand 3
217 If operand 3 of the insv pattern is VOIDmode, then we will use BITS_PER_WORD
218 else, we use the mode of operand 3. */
221 store_bit_field (str_rtx, bitsize, bitnum, fieldmode, value, align, total_size)
223 register int bitsize;
225 enum machine_mode fieldmode;
230 int unit = (GET_CODE (str_rtx) == MEM) ? BITS_PER_UNIT : BITS_PER_WORD;
231 register int offset = bitnum / unit;
232 register int bitpos = bitnum % unit;
233 register rtx op0 = str_rtx;
236 enum machine_mode op_mode;
238 op_mode = insn_data[(int) CODE_FOR_insv].operand[3].mode;
239 if (op_mode == VOIDmode)
241 insv_bitsize = GET_MODE_BITSIZE (op_mode);
244 if (GET_CODE (str_rtx) == MEM && ! MEM_IN_STRUCT_P (str_rtx))
247 /* Discount the part of the structure before the desired byte.
248 We need to know how many bytes are safe to reference after it. */
250 total_size -= (bitpos / BIGGEST_ALIGNMENT
251 * (BIGGEST_ALIGNMENT / BITS_PER_UNIT));
253 while (GET_CODE (op0) == SUBREG)
255 /* The following line once was done only if WORDS_BIG_ENDIAN,
256 but I think that is a mistake. WORDS_BIG_ENDIAN is
257 meaningful at a much higher level; when structures are copied
258 between memory and regs, the higher-numbered regs
259 always get higher addresses. */
260 offset += SUBREG_WORD (op0);
261 /* We used to adjust BITPOS here, but now we do the whole adjustment
262 right after the loop. */
263 op0 = SUBREG_REG (op0);
266 /* Make sure we are playing with integral modes. Pun with subregs
269 enum machine_mode imode = int_mode_for_mode (GET_MODE (op0));
270 if (imode != GET_MODE (op0))
272 if (GET_CODE (op0) == MEM)
273 op0 = change_address (op0, imode, NULL_RTX);
274 else if (imode != BLKmode)
275 op0 = gen_lowpart (imode, op0);
281 /* If OP0 is a register, BITPOS must count within a word.
282 But as we have it, it counts within whatever size OP0 now has.
283 On a bigendian machine, these are not the same, so convert. */
285 && GET_CODE (op0) != MEM
286 && unit > GET_MODE_BITSIZE (GET_MODE (op0)))
287 bitpos += unit - GET_MODE_BITSIZE (GET_MODE (op0));
289 value = protect_from_queue (value, 0);
292 value = force_not_mem (value);
294 /* Note that the adjustment of BITPOS above has no effect on whether
295 BITPOS is 0 in a REG bigger than a word. */
296 if (GET_MODE_SIZE (fieldmode) >= UNITS_PER_WORD
297 && (GET_CODE (op0) != MEM
298 || ! SLOW_UNALIGNED_ACCESS
299 || (offset * BITS_PER_UNIT % bitsize == 0
300 && align % GET_MODE_SIZE (fieldmode) == 0))
301 && bitpos == 0 && bitsize == GET_MODE_BITSIZE (fieldmode))
303 /* Storing in a full-word or multi-word field in a register
304 can be done with just SUBREG. */
305 if (GET_MODE (op0) != fieldmode)
307 if (GET_CODE (op0) == SUBREG)
309 if (GET_MODE (SUBREG_REG (op0)) == fieldmode
310 || GET_MODE_CLASS (fieldmode) == MODE_INT
311 || GET_MODE_CLASS (fieldmode) == MODE_PARTIAL_INT)
312 op0 = SUBREG_REG (op0);
314 /* Else we've got some float mode source being extracted into
315 a different float mode destination -- this combination of
316 subregs results in Severe Tire Damage. */
319 if (GET_CODE (op0) == REG)
320 op0 = gen_rtx_SUBREG (fieldmode, op0, offset);
322 op0 = change_address (op0, fieldmode,
323 plus_constant (XEXP (op0, 0), offset));
325 emit_move_insn (op0, value);
329 /* Storing an lsb-aligned field in a register
330 can be done with a movestrict instruction. */
332 if (GET_CODE (op0) != MEM
333 && (BYTES_BIG_ENDIAN ? bitpos + bitsize == unit : bitpos == 0)
334 && bitsize == GET_MODE_BITSIZE (fieldmode)
335 && (GET_MODE (op0) == fieldmode
336 || (movstrict_optab->handlers[(int) fieldmode].insn_code
337 != CODE_FOR_nothing)))
339 /* Get appropriate low part of the value being stored. */
340 if (GET_CODE (value) == CONST_INT || GET_CODE (value) == REG)
341 value = gen_lowpart (fieldmode, value);
342 else if (!(GET_CODE (value) == SYMBOL_REF
343 || GET_CODE (value) == LABEL_REF
344 || GET_CODE (value) == CONST))
345 value = convert_to_mode (fieldmode, value, 0);
347 if (GET_MODE (op0) == fieldmode)
348 emit_move_insn (op0, value);
351 int icode = movstrict_optab->handlers[(int) fieldmode].insn_code;
352 if (! (*insn_data[icode].operand[1].predicate) (value, fieldmode))
353 value = copy_to_mode_reg (fieldmode, value);
355 if (GET_CODE (op0) == SUBREG)
357 if (GET_MODE (SUBREG_REG (op0)) == fieldmode
358 || GET_MODE_CLASS (fieldmode) == MODE_INT
359 || GET_MODE_CLASS (fieldmode) == MODE_PARTIAL_INT)
360 op0 = SUBREG_REG (op0);
362 /* Else we've got some float mode source being extracted into
363 a different float mode destination -- this combination of
364 subregs results in Severe Tire Damage. */
368 emit_insn (GEN_FCN (icode)
369 (gen_rtx_SUBREG (fieldmode, op0, offset), value));
374 /* Handle fields bigger than a word. */
376 if (bitsize > BITS_PER_WORD)
378 /* Here we transfer the words of the field
379 in the order least significant first.
380 This is because the most significant word is the one which may
382 However, only do that if the value is not BLKmode. */
384 int backwards = WORDS_BIG_ENDIAN && fieldmode != BLKmode;
386 int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD;
389 /* This is the mode we must force value to, so that there will be enough
390 subwords to extract. Note that fieldmode will often (always?) be
391 VOIDmode, because that is what store_field uses to indicate that this
392 is a bit field, but passing VOIDmode to operand_subword_force will
393 result in an abort. */
394 fieldmode = mode_for_size (nwords * BITS_PER_WORD, MODE_INT, 0);
396 for (i = 0; i < nwords; i++)
398 /* If I is 0, use the low-order word in both field and target;
399 if I is 1, use the next to lowest word; and so on. */
400 int wordnum = (backwards ? nwords - i - 1 : i);
401 int bit_offset = (backwards
402 ? MAX (bitsize - (i + 1) * BITS_PER_WORD, 0)
403 : i * BITS_PER_WORD);
404 store_bit_field (op0, MIN (BITS_PER_WORD,
405 bitsize - i * BITS_PER_WORD),
406 bitnum + bit_offset, word_mode,
407 operand_subword_force (value, wordnum,
408 (GET_MODE (value) == VOIDmode
410 : GET_MODE (value))),
416 /* From here on we can assume that the field to be stored in is
417 a full-word (whatever type that is), since it is shorter than a word. */
419 /* OFFSET is the number of words or bytes (UNIT says which)
420 from STR_RTX to the first word or byte containing part of the field. */
422 if (GET_CODE (op0) != MEM)
425 || GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD)
427 if (GET_CODE (op0) != REG)
429 /* Since this is a destination (lvalue), we can't copy it to a
430 pseudo. We can trivially remove a SUBREG that does not
431 change the size of the operand. Such a SUBREG may have been
432 added above. Otherwise, abort. */
433 if (GET_CODE (op0) == SUBREG
434 && (GET_MODE_SIZE (GET_MODE (op0))
435 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0)))))
436 op0 = SUBREG_REG (op0);
440 op0 = gen_rtx_SUBREG (mode_for_size (BITS_PER_WORD, MODE_INT, 0),
447 op0 = protect_from_queue (op0, 1);
450 /* If VALUE is a floating-point mode, access it as an integer of the
451 corresponding size. This can occur on a machine with 64 bit registers
452 that uses SFmode for float. This can also occur for unaligned float
454 if (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT)
456 if (GET_CODE (value) != REG)
457 value = copy_to_reg (value);
458 value = gen_rtx_SUBREG (word_mode, value, 0);
461 /* Now OFFSET is nonzero only if OP0 is memory
462 and is therefore always measured in bytes. */
466 && GET_MODE (value) != BLKmode
467 && !(bitsize == 1 && GET_CODE (value) == CONST_INT)
468 /* Ensure insv's size is wide enough for this field. */
469 && (insv_bitsize >= bitsize)
470 && ! ((GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
471 && (bitsize + bitpos > insv_bitsize)))
473 int xbitpos = bitpos;
476 rtx last = get_last_insn ();
478 enum machine_mode maxmode;
479 int save_volatile_ok = volatile_ok;
481 maxmode = insn_data[(int) CODE_FOR_insv].operand[3].mode;
482 if (maxmode == VOIDmode)
487 /* If this machine's insv can only insert into a register, copy OP0
488 into a register and save it back later. */
489 /* This used to check flag_force_mem, but that was a serious
490 de-optimization now that flag_force_mem is enabled by -O2. */
491 if (GET_CODE (op0) == MEM
492 && ! ((*insn_data[(int) CODE_FOR_insv].operand[0].predicate)
496 enum machine_mode bestmode;
498 /* Get the mode to use for inserting into this field. If OP0 is
499 BLKmode, get the smallest mode consistent with the alignment. If
500 OP0 is a non-BLKmode object that is no wider than MAXMODE, use its
501 mode. Otherwise, use the smallest mode containing the field. */
503 if (GET_MODE (op0) == BLKmode
504 || GET_MODE_SIZE (GET_MODE (op0)) > GET_MODE_SIZE (maxmode))
506 = get_best_mode (bitsize, bitnum, align * BITS_PER_UNIT, maxmode,
507 MEM_VOLATILE_P (op0));
509 bestmode = GET_MODE (op0);
511 if (bestmode == VOIDmode
512 || (SLOW_UNALIGNED_ACCESS && GET_MODE_SIZE (bestmode) > align))
515 /* Adjust address to point to the containing unit of that mode. */
516 unit = GET_MODE_BITSIZE (bestmode);
517 /* Compute offset as multiple of this unit, counting in bytes. */
518 offset = (bitnum / unit) * GET_MODE_SIZE (bestmode);
519 bitpos = bitnum % unit;
520 op0 = change_address (op0, bestmode,
521 plus_constant (XEXP (op0, 0), offset));
523 /* Fetch that unit, store the bitfield in it, then store the unit. */
524 tempreg = copy_to_reg (op0);
525 store_bit_field (tempreg, bitsize, bitpos, fieldmode, value,
527 emit_move_insn (op0, tempreg);
530 volatile_ok = save_volatile_ok;
532 /* Add OFFSET into OP0's address. */
533 if (GET_CODE (xop0) == MEM)
534 xop0 = change_address (xop0, byte_mode,
535 plus_constant (XEXP (xop0, 0), offset));
537 /* If xop0 is a register, we need it in MAXMODE
538 to make it acceptable to the format of insv. */
539 if (GET_CODE (xop0) == SUBREG)
540 /* We can't just change the mode, because this might clobber op0,
541 and we will need the original value of op0 if insv fails. */
542 xop0 = gen_rtx_SUBREG (maxmode, SUBREG_REG (xop0), SUBREG_WORD (xop0));
543 if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode)
544 xop0 = gen_rtx_SUBREG (maxmode, xop0, 0);
546 /* On big-endian machines, we count bits from the most significant.
547 If the bit field insn does not, we must invert. */
549 if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
550 xbitpos = unit - bitsize - xbitpos;
552 /* We have been counting XBITPOS within UNIT.
553 Count instead within the size of the register. */
554 if (BITS_BIG_ENDIAN && GET_CODE (xop0) != MEM)
555 xbitpos += GET_MODE_BITSIZE (maxmode) - unit;
557 unit = GET_MODE_BITSIZE (maxmode);
559 /* Convert VALUE to maxmode (which insv insn wants) in VALUE1. */
561 if (GET_MODE (value) != maxmode)
563 if (GET_MODE_BITSIZE (GET_MODE (value)) >= bitsize)
565 /* Optimization: Don't bother really extending VALUE
566 if it has all the bits we will actually use. However,
567 if we must narrow it, be sure we do it correctly. */
569 if (GET_MODE_SIZE (GET_MODE (value)) < GET_MODE_SIZE (maxmode))
571 /* Avoid making subreg of a subreg, or of a mem. */
572 if (GET_CODE (value1) != REG)
573 value1 = copy_to_reg (value1);
574 value1 = gen_rtx_SUBREG (maxmode, value1, 0);
577 value1 = gen_lowpart (maxmode, value1);
579 else if (!CONSTANT_P (value))
580 /* Parse phase is supposed to make VALUE's data type
581 match that of the component reference, which is a type
582 at least as wide as the field; so VALUE should have
583 a mode that corresponds to that type. */
587 /* If this machine's insv insists on a register,
588 get VALUE1 into a register. */
589 if (! ((*insn_data[(int) CODE_FOR_insv].operand[3].predicate)
591 value1 = force_reg (maxmode, value1);
593 pat = gen_insv (xop0, GEN_INT (bitsize), GEN_INT (xbitpos), value1);
598 delete_insns_since (last);
599 store_fixed_bit_field (op0, offset, bitsize, bitpos, value, align);
605 /* Insv is not available; store using shifts and boolean ops. */
606 store_fixed_bit_field (op0, offset, bitsize, bitpos, value, align);
610 /* Use shifts and boolean operations to store VALUE
611 into a bit field of width BITSIZE
612 in a memory location specified by OP0 except offset by OFFSET bytes.
613 (OFFSET must be 0 if OP0 is a register.)
614 The field starts at position BITPOS within the byte.
615 (If OP0 is a register, it may be a full word or a narrower mode,
616 but BITPOS still counts within a full word,
617 which is significant on bigendian machines.)
618 STRUCT_ALIGN is the alignment the structure is known to have (in bytes).
620 Note that protect_from_queue has already been done on OP0 and VALUE. */
623 store_fixed_bit_field (op0, offset, bitsize, bitpos, value, struct_align)
625 register int offset, bitsize, bitpos;
629 register enum machine_mode mode;
630 int total_bits = BITS_PER_WORD;
635 if (! SLOW_UNALIGNED_ACCESS)
636 struct_align = BIGGEST_ALIGNMENT / BITS_PER_UNIT;
638 /* There is a case not handled here:
639 a structure with a known alignment of just a halfword
640 and a field split across two aligned halfwords within the structure.
641 Or likewise a structure with a known alignment of just a byte
642 and a field split across two bytes.
643 Such cases are not supposed to be able to occur. */
645 if (GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
649 /* Special treatment for a bit field split across two registers. */
650 if (bitsize + bitpos > BITS_PER_WORD)
652 store_split_bit_field (op0, bitsize, bitpos,
653 value, BITS_PER_WORD);
659 /* Get the proper mode to use for this field. We want a mode that
660 includes the entire field. If such a mode would be larger than
661 a word, we won't be doing the extraction the normal way. */
663 mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT,
664 struct_align * BITS_PER_UNIT, word_mode,
665 GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0));
667 if (mode == VOIDmode)
669 /* The only way this should occur is if the field spans word
671 store_split_bit_field (op0,
672 bitsize, bitpos + offset * BITS_PER_UNIT,
673 value, struct_align);
677 total_bits = GET_MODE_BITSIZE (mode);
679 /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to
680 be in the range 0 to total_bits-1, and put any excess bytes in
682 if (bitpos >= total_bits)
684 offset += (bitpos / total_bits) * (total_bits / BITS_PER_UNIT);
685 bitpos -= ((bitpos / total_bits) * (total_bits / BITS_PER_UNIT)
689 /* Get ref to an aligned byte, halfword, or word containing the field.
690 Adjust BITPOS to be position within a word,
691 and OFFSET to be the offset of that word.
692 Then alter OP0 to refer to that word. */
693 bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT;
694 offset -= (offset % (total_bits / BITS_PER_UNIT));
695 op0 = change_address (op0, mode,
696 plus_constant (XEXP (op0, 0), offset));
699 mode = GET_MODE (op0);
701 /* Now MODE is either some integral mode for a MEM as OP0,
702 or is a full-word for a REG as OP0. TOTAL_BITS corresponds.
703 The bit field is contained entirely within OP0.
704 BITPOS is the starting bit number within OP0.
705 (OP0's mode may actually be narrower than MODE.) */
707 if (BYTES_BIG_ENDIAN)
708 /* BITPOS is the distance between our msb
709 and that of the containing datum.
710 Convert it to the distance from the lsb. */
711 bitpos = total_bits - bitsize - bitpos;
713 /* Now BITPOS is always the distance between our lsb
716 /* Shift VALUE left by BITPOS bits. If VALUE is not constant,
717 we must first convert its mode to MODE. */
719 if (GET_CODE (value) == CONST_INT)
721 register HOST_WIDE_INT v = INTVAL (value);
723 if (bitsize < HOST_BITS_PER_WIDE_INT)
724 v &= ((HOST_WIDE_INT) 1 << bitsize) - 1;
728 else if ((bitsize < HOST_BITS_PER_WIDE_INT
729 && v == ((HOST_WIDE_INT) 1 << bitsize) - 1)
730 || (bitsize == HOST_BITS_PER_WIDE_INT && v == -1))
733 value = lshift_value (mode, value, bitpos, bitsize);
737 int must_and = (GET_MODE_BITSIZE (GET_MODE (value)) != bitsize
738 && bitpos + bitsize != GET_MODE_BITSIZE (mode));
740 if (GET_MODE (value) != mode)
742 if ((GET_CODE (value) == REG || GET_CODE (value) == SUBREG)
743 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (value)))
744 value = gen_lowpart (mode, value);
746 value = convert_to_mode (mode, value, 1);
750 value = expand_binop (mode, and_optab, value,
751 mask_rtx (mode, 0, bitsize, 0),
752 NULL_RTX, 1, OPTAB_LIB_WIDEN);
754 value = expand_shift (LSHIFT_EXPR, mode, value,
755 build_int_2 (bitpos, 0), NULL_RTX, 1);
758 /* Now clear the chosen bits in OP0,
759 except that if VALUE is -1 we need not bother. */
761 subtarget = (GET_CODE (op0) == REG || ! flag_force_mem) ? op0 : 0;
765 temp = expand_binop (mode, and_optab, op0,
766 mask_rtx (mode, bitpos, bitsize, 1),
767 subtarget, 1, OPTAB_LIB_WIDEN);
773 /* Now logical-or VALUE into OP0, unless it is zero. */
776 temp = expand_binop (mode, ior_optab, temp, value,
777 subtarget, 1, OPTAB_LIB_WIDEN);
779 emit_move_insn (op0, temp);
782 /* Store a bit field that is split across multiple accessible memory objects.
784 OP0 is the REG, SUBREG or MEM rtx for the first of the objects.
785 BITSIZE is the field width; BITPOS the position of its first bit
787 VALUE is the value to store.
788 ALIGN is the known alignment of OP0, measured in bytes.
789 This is also the size of the memory objects to be used.
791 This does not yet handle fields wider than BITS_PER_WORD. */
794 store_split_bit_field (op0, bitsize, bitpos, value, align)
803 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
805 if (GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
806 unit = BITS_PER_WORD;
808 unit = MIN (align * BITS_PER_UNIT, BITS_PER_WORD);
810 /* If VALUE is a constant other than a CONST_INT, get it into a register in
811 WORD_MODE. If we can do this using gen_lowpart_common, do so. Note
812 that VALUE might be a floating-point constant. */
813 if (CONSTANT_P (value) && GET_CODE (value) != CONST_INT)
815 rtx word = gen_lowpart_common (word_mode, value);
817 if (word && (value != word))
820 value = gen_lowpart_common (word_mode,
821 force_reg (GET_MODE (value) != VOIDmode
823 : word_mode, value));
825 else if (GET_CODE (value) == ADDRESSOF)
826 value = copy_to_reg (value);
828 while (bitsdone < bitsize)
835 offset = (bitpos + bitsdone) / unit;
836 thispos = (bitpos + bitsdone) % unit;
838 /* THISSIZE must not overrun a word boundary. Otherwise,
839 store_fixed_bit_field will call us again, and we will mutually
841 thissize = MIN (bitsize - bitsdone, BITS_PER_WORD);
842 thissize = MIN (thissize, unit - thispos);
844 if (BYTES_BIG_ENDIAN)
848 /* We must do an endian conversion exactly the same way as it is
849 done in extract_bit_field, so that the two calls to
850 extract_fixed_bit_field will have comparable arguments. */
851 if (GET_CODE (value) != MEM || GET_MODE (value) == BLKmode)
852 total_bits = BITS_PER_WORD;
854 total_bits = GET_MODE_BITSIZE (GET_MODE (value));
856 /* Fetch successively less significant portions. */
857 if (GET_CODE (value) == CONST_INT)
858 part = GEN_INT (((unsigned HOST_WIDE_INT) (INTVAL (value))
859 >> (bitsize - bitsdone - thissize))
860 & (((HOST_WIDE_INT) 1 << thissize) - 1));
862 /* The args are chosen so that the last part includes the
863 lsb. Give extract_bit_field the value it needs (with
864 endianness compensation) to fetch the piece we want.
866 ??? We have no idea what the alignment of VALUE is, so
867 we have to use a guess. */
869 = extract_fixed_bit_field
870 (word_mode, value, 0, thissize,
871 total_bits - bitsize + bitsdone, NULL_RTX, 1,
872 GET_MODE (value) == VOIDmode
874 : (GET_MODE (value) == BLKmode
876 : GET_MODE_ALIGNMENT (GET_MODE (value)) / BITS_PER_UNIT));
880 /* Fetch successively more significant portions. */
881 if (GET_CODE (value) == CONST_INT)
882 part = GEN_INT (((unsigned HOST_WIDE_INT) (INTVAL (value))
884 & (((HOST_WIDE_INT) 1 << thissize) - 1));
887 = extract_fixed_bit_field
888 (word_mode, value, 0, thissize, bitsdone, NULL_RTX, 1,
889 GET_MODE (value) == VOIDmode
891 : (GET_MODE (value) == BLKmode
893 : GET_MODE_ALIGNMENT (GET_MODE (value)) / BITS_PER_UNIT));
896 /* If OP0 is a register, then handle OFFSET here.
898 When handling multiword bitfields, extract_bit_field may pass
899 down a word_mode SUBREG of a larger REG for a bitfield that actually
900 crosses a word boundary. Thus, for a SUBREG, we must find
901 the current word starting from the base register. */
902 if (GET_CODE (op0) == SUBREG)
904 word = operand_subword_force (SUBREG_REG (op0),
905 SUBREG_WORD (op0) + offset,
906 GET_MODE (SUBREG_REG (op0)));
909 else if (GET_CODE (op0) == REG)
911 word = operand_subword_force (op0, offset, GET_MODE (op0));
917 /* OFFSET is in UNITs, and UNIT is in bits.
918 store_fixed_bit_field wants offset in bytes. */
919 store_fixed_bit_field (word, offset * unit / BITS_PER_UNIT,
920 thissize, thispos, part, align);
921 bitsdone += thissize;
925 /* Generate code to extract a byte-field from STR_RTX
926 containing BITSIZE bits, starting at BITNUM,
927 and put it in TARGET if possible (if TARGET is nonzero).
928 Regardless of TARGET, we return the rtx for where the value is placed.
931 STR_RTX is the structure containing the byte (a REG or MEM).
932 UNSIGNEDP is nonzero if this is an unsigned bit field.
933 MODE is the natural mode of the field value once extracted.
934 TMODE is the mode the caller would like the value to have;
935 but the value may be returned with type MODE instead.
937 ALIGN is the alignment that STR_RTX is known to have, measured in bytes.
938 TOTAL_SIZE is the size in bytes of the containing structure,
941 If a TARGET is specified and we can store in it at no extra cost,
942 we do so, and return TARGET.
943 Otherwise, we return a REG of mode TMODE or MODE, with TMODE preferred
944 if they are equally easy. */
947 extract_bit_field (str_rtx, bitsize, bitnum, unsignedp,
948 target, mode, tmode, align, total_size)
950 register int bitsize;
954 enum machine_mode mode, tmode;
958 int unit = (GET_CODE (str_rtx) == MEM) ? BITS_PER_UNIT : BITS_PER_WORD;
959 register int offset = bitnum / unit;
960 register int bitpos = bitnum % unit;
961 register rtx op0 = str_rtx;
962 rtx spec_target = target;
963 rtx spec_target_subreg = 0;
964 enum machine_mode int_mode;
967 enum machine_mode extv_mode;
971 enum machine_mode extzv_mode;
975 extv_mode = insn_data[(int) CODE_FOR_extv].operand[0].mode;
976 if (extv_mode == VOIDmode)
977 extv_mode = word_mode;
978 extv_bitsize = GET_MODE_BITSIZE (extv_mode);
982 extzv_mode = insn_data[(int) CODE_FOR_extzv].operand[0].mode;
983 if (extzv_mode == VOIDmode)
984 extzv_mode = word_mode;
985 extzv_bitsize = GET_MODE_BITSIZE (extzv_mode);
988 /* Discount the part of the structure before the desired byte.
989 We need to know how many bytes are safe to reference after it. */
991 total_size -= (bitpos / BIGGEST_ALIGNMENT
992 * (BIGGEST_ALIGNMENT / BITS_PER_UNIT));
994 if (tmode == VOIDmode)
996 while (GET_CODE (op0) == SUBREG)
998 int outer_size = GET_MODE_BITSIZE (GET_MODE (op0));
999 int inner_size = GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)));
1001 offset += SUBREG_WORD (op0);
1003 inner_size = MIN (inner_size, BITS_PER_WORD);
1005 if (BYTES_BIG_ENDIAN && (outer_size < inner_size))
1007 bitpos += inner_size - outer_size;
1010 offset += (bitpos / unit);
1015 op0 = SUBREG_REG (op0);
1018 /* Make sure we are playing with integral modes. Pun with subregs
1021 enum machine_mode imode = int_mode_for_mode (GET_MODE (op0));
1022 if (imode != GET_MODE (op0))
1024 if (GET_CODE (op0) == MEM)
1025 op0 = change_address (op0, imode, NULL_RTX);
1026 else if (imode != BLKmode)
1027 op0 = gen_lowpart (imode, op0);
1033 /* ??? We currently assume TARGET is at least as big as BITSIZE.
1034 If that's wrong, the solution is to test for it and set TARGET to 0
1037 /* If OP0 is a register, BITPOS must count within a word.
1038 But as we have it, it counts within whatever size OP0 now has.
1039 On a bigendian machine, these are not the same, so convert. */
1040 if (BYTES_BIG_ENDIAN
1041 && GET_CODE (op0) != MEM
1042 && unit > GET_MODE_BITSIZE (GET_MODE (op0)))
1043 bitpos += unit - GET_MODE_BITSIZE (GET_MODE (op0));
1045 /* Extracting a full-word or multi-word value
1046 from a structure in a register or aligned memory.
1047 This can be done with just SUBREG.
1048 So too extracting a subword value in
1049 the least significant part of the register. */
1051 if (((GET_CODE (op0) != MEM
1052 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
1053 GET_MODE_BITSIZE (GET_MODE (op0))))
1054 || (GET_CODE (op0) == MEM
1055 && (! SLOW_UNALIGNED_ACCESS
1056 || (offset * BITS_PER_UNIT % bitsize == 0
1057 && align * BITS_PER_UNIT % bitsize == 0))))
1058 && ((bitsize >= BITS_PER_WORD && bitsize == GET_MODE_BITSIZE (mode)
1059 && bitpos % BITS_PER_WORD == 0)
1060 || (mode_for_size (bitsize, GET_MODE_CLASS (tmode), 0) != BLKmode
1061 /* ??? The big endian test here is wrong. This is correct
1062 if the value is in a register, and if mode_for_size is not
1063 the same mode as op0. This causes us to get unnecessarily
1064 inefficient code from the Thumb port when -mbig-endian. */
1065 && (BYTES_BIG_ENDIAN
1066 ? bitpos + bitsize == BITS_PER_WORD
1069 enum machine_mode mode1
1070 = mode_for_size (bitsize, GET_MODE_CLASS (tmode), 0);
1072 if (mode1 != GET_MODE (op0))
1074 if (GET_CODE (op0) == SUBREG)
1076 if (GET_MODE (SUBREG_REG (op0)) == mode1
1077 || GET_MODE_CLASS (mode1) == MODE_INT
1078 || GET_MODE_CLASS (mode1) == MODE_PARTIAL_INT)
1079 op0 = SUBREG_REG (op0);
1081 /* Else we've got some float mode source being extracted into
1082 a different float mode destination -- this combination of
1083 subregs results in Severe Tire Damage. */
1086 if (GET_CODE (op0) == REG)
1087 op0 = gen_rtx_SUBREG (mode1, op0, offset);
1089 op0 = change_address (op0, mode1,
1090 plus_constant (XEXP (op0, 0), offset));
1093 return convert_to_mode (tmode, op0, unsignedp);
1097 /* Handle fields bigger than a word. */
1099 if (bitsize > BITS_PER_WORD)
1101 /* Here we transfer the words of the field
1102 in the order least significant first.
1103 This is because the most significant word is the one which may
1104 be less than full. */
1106 int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD;
1109 if (target == 0 || GET_CODE (target) != REG)
1110 target = gen_reg_rtx (mode);
1112 /* Indicate for flow that the entire target reg is being set. */
1113 emit_insn (gen_rtx_CLOBBER (VOIDmode, target));
1115 for (i = 0; i < nwords; i++)
1117 /* If I is 0, use the low-order word in both field and target;
1118 if I is 1, use the next to lowest word; and so on. */
1119 /* Word number in TARGET to use. */
1120 int wordnum = (WORDS_BIG_ENDIAN
1121 ? GET_MODE_SIZE (GET_MODE (target)) / UNITS_PER_WORD - i - 1
1123 /* Offset from start of field in OP0. */
1124 int bit_offset = (WORDS_BIG_ENDIAN
1125 ? MAX (0, bitsize - (i + 1) * BITS_PER_WORD)
1126 : i * BITS_PER_WORD);
1127 rtx target_part = operand_subword (target, wordnum, 1, VOIDmode);
1129 = extract_bit_field (op0, MIN (BITS_PER_WORD,
1130 bitsize - i * BITS_PER_WORD),
1131 bitnum + bit_offset,
1132 1, target_part, mode, word_mode,
1135 if (target_part == 0)
1138 if (result_part != target_part)
1139 emit_move_insn (target_part, result_part);
1144 /* Unless we've filled TARGET, the upper regs in a multi-reg value
1145 need to be zero'd out. */
1146 if (GET_MODE_SIZE (GET_MODE (target)) > nwords * UNITS_PER_WORD)
1150 total_words = GET_MODE_SIZE (GET_MODE (target)) / UNITS_PER_WORD;
1151 for (i = nwords; i < total_words; i++)
1153 int wordnum = WORDS_BIG_ENDIAN ? total_words - i - 1 : i;
1154 rtx target_part = operand_subword (target, wordnum, 1, VOIDmode);
1155 emit_move_insn (target_part, const0_rtx);
1161 /* Signed bit field: sign-extend with two arithmetic shifts. */
1162 target = expand_shift (LSHIFT_EXPR, mode, target,
1163 build_int_2 (GET_MODE_BITSIZE (mode) - bitsize, 0),
1165 return expand_shift (RSHIFT_EXPR, mode, target,
1166 build_int_2 (GET_MODE_BITSIZE (mode) - bitsize, 0),
1170 /* From here on we know the desired field is smaller than a word. */
1172 /* Check if there is a correspondingly-sized integer field, so we can
1173 safely extract it as one size of integer, if necessary; then
1174 truncate or extend to the size that is wanted; then use SUBREGs or
1175 convert_to_mode to get one of the modes we really wanted. */
1177 int_mode = int_mode_for_mode (tmode);
1178 if (int_mode == BLKmode)
1179 int_mode = int_mode_for_mode (mode);
1180 if (int_mode == BLKmode)
1181 abort(); /* Should probably push op0 out to memory and then
1184 /* OFFSET is the number of words or bytes (UNIT says which)
1185 from STR_RTX to the first word or byte containing part of the field. */
1187 if (GET_CODE (op0) != MEM)
1190 || GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD)
1192 if (GET_CODE (op0) != REG)
1193 op0 = copy_to_reg (op0);
1194 op0 = gen_rtx_SUBREG (mode_for_size (BITS_PER_WORD, MODE_INT, 0),
1201 op0 = protect_from_queue (str_rtx, 1);
1204 /* Now OFFSET is nonzero only for memory operands. */
1210 && (extzv_bitsize >= bitsize)
1211 && ! ((GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
1212 && (bitsize + bitpos > extzv_bitsize)))
1214 int xbitpos = bitpos, xoffset = offset;
1215 rtx bitsize_rtx, bitpos_rtx;
1216 rtx last = get_last_insn ();
1218 rtx xtarget = target;
1219 rtx xspec_target = spec_target;
1220 rtx xspec_target_subreg = spec_target_subreg;
1222 enum machine_mode maxmode;
1224 maxmode = insn_data[(int) CODE_FOR_extzv].operand[0].mode;
1225 if (maxmode == VOIDmode)
1226 maxmode = word_mode;
1228 if (GET_CODE (xop0) == MEM)
1230 int save_volatile_ok = volatile_ok;
1233 /* Is the memory operand acceptable? */
1234 if (! ((*insn_data[(int) CODE_FOR_extzv].operand[1].predicate)
1235 (xop0, GET_MODE (xop0))))
1237 /* No, load into a reg and extract from there. */
1238 enum machine_mode bestmode;
1240 /* Get the mode to use for inserting into this field. If
1241 OP0 is BLKmode, get the smallest mode consistent with the
1242 alignment. If OP0 is a non-BLKmode object that is no
1243 wider than MAXMODE, use its mode. Otherwise, use the
1244 smallest mode containing the field. */
1246 if (GET_MODE (xop0) == BLKmode
1247 || (GET_MODE_SIZE (GET_MODE (op0))
1248 > GET_MODE_SIZE (maxmode)))
1249 bestmode = get_best_mode (bitsize, bitnum,
1250 align * BITS_PER_UNIT, maxmode,
1251 MEM_VOLATILE_P (xop0));
1253 bestmode = GET_MODE (xop0);
1255 if (bestmode == VOIDmode
1256 || (SLOW_UNALIGNED_ACCESS && GET_MODE_SIZE (bestmode) > align))
1259 /* Compute offset as multiple of this unit,
1260 counting in bytes. */
1261 unit = GET_MODE_BITSIZE (bestmode);
1262 xoffset = (bitnum / unit) * GET_MODE_SIZE (bestmode);
1263 xbitpos = bitnum % unit;
1264 xop0 = change_address (xop0, bestmode,
1265 plus_constant (XEXP (xop0, 0),
1267 /* Fetch it to a register in that size. */
1268 xop0 = force_reg (bestmode, xop0);
1270 /* XBITPOS counts within UNIT, which is what is expected. */
1273 /* Get ref to first byte containing part of the field. */
1274 xop0 = change_address (xop0, byte_mode,
1275 plus_constant (XEXP (xop0, 0), xoffset));
1277 volatile_ok = save_volatile_ok;
1280 /* If op0 is a register, we need it in MAXMODE (which is usually
1281 SImode). to make it acceptable to the format of extzv. */
1282 if (GET_CODE (xop0) == SUBREG && GET_MODE (xop0) != maxmode)
1284 if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode)
1285 xop0 = gen_rtx_SUBREG (maxmode, xop0, 0);
1287 /* On big-endian machines, we count bits from the most significant.
1288 If the bit field insn does not, we must invert. */
1289 if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
1290 xbitpos = unit - bitsize - xbitpos;
1292 /* Now convert from counting within UNIT to counting in MAXMODE. */
1293 if (BITS_BIG_ENDIAN && GET_CODE (xop0) != MEM)
1294 xbitpos += GET_MODE_BITSIZE (maxmode) - unit;
1296 unit = GET_MODE_BITSIZE (maxmode);
1299 || (flag_force_mem && GET_CODE (xtarget) == MEM))
1300 xtarget = xspec_target = gen_reg_rtx (tmode);
1302 if (GET_MODE (xtarget) != maxmode)
1304 if (GET_CODE (xtarget) == REG)
1306 int wider = (GET_MODE_SIZE (maxmode)
1307 > GET_MODE_SIZE (GET_MODE (xtarget)));
1308 xtarget = gen_lowpart (maxmode, xtarget);
1310 xspec_target_subreg = xtarget;
1313 xtarget = gen_reg_rtx (maxmode);
1316 /* If this machine's extzv insists on a register target,
1317 make sure we have one. */
1318 if (! ((*insn_data[(int) CODE_FOR_extzv].operand[0].predicate)
1319 (xtarget, maxmode)))
1320 xtarget = gen_reg_rtx (maxmode);
1322 bitsize_rtx = GEN_INT (bitsize);
1323 bitpos_rtx = GEN_INT (xbitpos);
1325 pat = gen_extzv (protect_from_queue (xtarget, 1),
1326 xop0, bitsize_rtx, bitpos_rtx);
1331 spec_target = xspec_target;
1332 spec_target_subreg = xspec_target_subreg;
1336 delete_insns_since (last);
1337 target = extract_fixed_bit_field (int_mode, op0, offset, bitsize,
1338 bitpos, target, 1, align);
1344 target = extract_fixed_bit_field (int_mode, op0, offset, bitsize,
1345 bitpos, target, 1, align);
1351 && (extv_bitsize >= bitsize)
1352 && ! ((GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
1353 && (bitsize + bitpos > extv_bitsize)))
1355 int xbitpos = bitpos, xoffset = offset;
1356 rtx bitsize_rtx, bitpos_rtx;
1357 rtx last = get_last_insn ();
1358 rtx xop0 = op0, xtarget = target;
1359 rtx xspec_target = spec_target;
1360 rtx xspec_target_subreg = spec_target_subreg;
1362 enum machine_mode maxmode;
1364 maxmode = insn_data[(int) CODE_FOR_extv].operand[0].mode;
1365 if (maxmode == VOIDmode)
1366 maxmode = word_mode;
1368 if (GET_CODE (xop0) == MEM)
1370 /* Is the memory operand acceptable? */
1371 if (! ((*insn_data[(int) CODE_FOR_extv].operand[1].predicate)
1372 (xop0, GET_MODE (xop0))))
1374 /* No, load into a reg and extract from there. */
1375 enum machine_mode bestmode;
1377 /* Get the mode to use for inserting into this field. If
1378 OP0 is BLKmode, get the smallest mode consistent with the
1379 alignment. If OP0 is a non-BLKmode object that is no
1380 wider than MAXMODE, use its mode. Otherwise, use the
1381 smallest mode containing the field. */
1383 if (GET_MODE (xop0) == BLKmode
1384 || (GET_MODE_SIZE (GET_MODE (op0))
1385 > GET_MODE_SIZE (maxmode)))
1386 bestmode = get_best_mode (bitsize, bitnum,
1387 align * BITS_PER_UNIT, maxmode,
1388 MEM_VOLATILE_P (xop0));
1390 bestmode = GET_MODE (xop0);
1392 if (bestmode == VOIDmode
1393 || (SLOW_UNALIGNED_ACCESS && GET_MODE_SIZE (bestmode) > align))
1396 /* Compute offset as multiple of this unit,
1397 counting in bytes. */
1398 unit = GET_MODE_BITSIZE (bestmode);
1399 xoffset = (bitnum / unit) * GET_MODE_SIZE (bestmode);
1400 xbitpos = bitnum % unit;
1401 xop0 = change_address (xop0, bestmode,
1402 plus_constant (XEXP (xop0, 0),
1404 /* Fetch it to a register in that size. */
1405 xop0 = force_reg (bestmode, xop0);
1407 /* XBITPOS counts within UNIT, which is what is expected. */
1410 /* Get ref to first byte containing part of the field. */
1411 xop0 = change_address (xop0, byte_mode,
1412 plus_constant (XEXP (xop0, 0), xoffset));
1415 /* If op0 is a register, we need it in MAXMODE (which is usually
1416 SImode) to make it acceptable to the format of extv. */
1417 if (GET_CODE (xop0) == SUBREG && GET_MODE (xop0) != maxmode)
1419 if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode)
1420 xop0 = gen_rtx_SUBREG (maxmode, xop0, 0);
1422 /* On big-endian machines, we count bits from the most significant.
1423 If the bit field insn does not, we must invert. */
1424 if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
1425 xbitpos = unit - bitsize - xbitpos;
1427 /* XBITPOS counts within a size of UNIT.
1428 Adjust to count within a size of MAXMODE. */
1429 if (BITS_BIG_ENDIAN && GET_CODE (xop0) != MEM)
1430 xbitpos += (GET_MODE_BITSIZE (maxmode) - unit);
1432 unit = GET_MODE_BITSIZE (maxmode);
1435 || (flag_force_mem && GET_CODE (xtarget) == MEM))
1436 xtarget = xspec_target = gen_reg_rtx (tmode);
1438 if (GET_MODE (xtarget) != maxmode)
1440 if (GET_CODE (xtarget) == REG)
1442 int wider = (GET_MODE_SIZE (maxmode)
1443 > GET_MODE_SIZE (GET_MODE (xtarget)));
1444 xtarget = gen_lowpart (maxmode, xtarget);
1446 xspec_target_subreg = xtarget;
1449 xtarget = gen_reg_rtx (maxmode);
1452 /* If this machine's extv insists on a register target,
1453 make sure we have one. */
1454 if (! ((*insn_data[(int) CODE_FOR_extv].operand[0].predicate)
1455 (xtarget, maxmode)))
1456 xtarget = gen_reg_rtx (maxmode);
1458 bitsize_rtx = GEN_INT (bitsize);
1459 bitpos_rtx = GEN_INT (xbitpos);
1461 pat = gen_extv (protect_from_queue (xtarget, 1),
1462 xop0, bitsize_rtx, bitpos_rtx);
1467 spec_target = xspec_target;
1468 spec_target_subreg = xspec_target_subreg;
1472 delete_insns_since (last);
1473 target = extract_fixed_bit_field (int_mode, op0, offset, bitsize,
1474 bitpos, target, 0, align);
1480 target = extract_fixed_bit_field (int_mode, op0, offset, bitsize,
1481 bitpos, target, 0, align);
1483 if (target == spec_target)
1485 if (target == spec_target_subreg)
1487 if (GET_MODE (target) != tmode && GET_MODE (target) != mode)
1489 /* If the target mode is floating-point, first convert to the
1490 integer mode of that size and then access it as a floating-point
1491 value via a SUBREG. */
1492 if (GET_MODE_CLASS (tmode) == MODE_FLOAT)
1494 target = convert_to_mode (mode_for_size (GET_MODE_BITSIZE (tmode),
1497 if (GET_CODE (target) != REG)
1498 target = copy_to_reg (target);
1499 return gen_rtx_SUBREG (tmode, target, 0);
1502 return convert_to_mode (tmode, target, unsignedp);
1507 /* Extract a bit field using shifts and boolean operations
1508 Returns an rtx to represent the value.
1509 OP0 addresses a register (word) or memory (byte).
1510 BITPOS says which bit within the word or byte the bit field starts in.
1511 OFFSET says how many bytes farther the bit field starts;
1512 it is 0 if OP0 is a register.
1513 BITSIZE says how many bits long the bit field is.
1514 (If OP0 is a register, it may be narrower than a full word,
1515 but BITPOS still counts within a full word,
1516 which is significant on bigendian machines.)
1518 UNSIGNEDP is nonzero for an unsigned bit field (don't sign-extend value).
1519 If TARGET is nonzero, attempts to store the value there
1520 and return TARGET, but this is not guaranteed.
1521 If TARGET is not used, create a pseudo-reg of mode TMODE for the value.
1523 ALIGN is the alignment that STR_RTX is known to have, measured in bytes. */
1526 extract_fixed_bit_field (tmode, op0, offset, bitsize, bitpos,
1527 target, unsignedp, align)
1528 enum machine_mode tmode;
1529 register rtx op0, target;
1530 register int offset, bitsize, bitpos;
1534 int total_bits = BITS_PER_WORD;
1535 enum machine_mode mode;
1537 if (GET_CODE (op0) == SUBREG || GET_CODE (op0) == REG)
1539 /* Special treatment for a bit field split across two registers. */
1540 if (bitsize + bitpos > BITS_PER_WORD)
1541 return extract_split_bit_field (op0, bitsize, bitpos,
1546 /* Get the proper mode to use for this field. We want a mode that
1547 includes the entire field. If such a mode would be larger than
1548 a word, we won't be doing the extraction the normal way. */
1550 mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT,
1551 align * BITS_PER_UNIT, word_mode,
1552 GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0));
1554 if (mode == VOIDmode)
1555 /* The only way this should occur is if the field spans word
1557 return extract_split_bit_field (op0, bitsize,
1558 bitpos + offset * BITS_PER_UNIT,
1561 total_bits = GET_MODE_BITSIZE (mode);
1563 /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to
1564 be in the range 0 to total_bits-1, and put any excess bytes in
1566 if (bitpos >= total_bits)
1568 offset += (bitpos / total_bits) * (total_bits / BITS_PER_UNIT);
1569 bitpos -= ((bitpos / total_bits) * (total_bits / BITS_PER_UNIT)
1573 /* Get ref to an aligned byte, halfword, or word containing the field.
1574 Adjust BITPOS to be position within a word,
1575 and OFFSET to be the offset of that word.
1576 Then alter OP0 to refer to that word. */
1577 bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT;
1578 offset -= (offset % (total_bits / BITS_PER_UNIT));
1579 op0 = change_address (op0, mode,
1580 plus_constant (XEXP (op0, 0), offset));
1583 mode = GET_MODE (op0);
1585 if (BYTES_BIG_ENDIAN)
1587 /* BITPOS is the distance between our msb and that of OP0.
1588 Convert it to the distance from the lsb. */
1590 bitpos = total_bits - bitsize - bitpos;
1593 /* Now BITPOS is always the distance between the field's lsb and that of OP0.
1594 We have reduced the big-endian case to the little-endian case. */
1600 /* If the field does not already start at the lsb,
1601 shift it so it does. */
1602 tree amount = build_int_2 (bitpos, 0);
1603 /* Maybe propagate the target for the shift. */
1604 /* But not if we will return it--could confuse integrate.c. */
1605 rtx subtarget = (target != 0 && GET_CODE (target) == REG
1606 && !REG_FUNCTION_VALUE_P (target)
1608 if (tmode != mode) subtarget = 0;
1609 op0 = expand_shift (RSHIFT_EXPR, mode, op0, amount, subtarget, 1);
1611 /* Convert the value to the desired mode. */
1613 op0 = convert_to_mode (tmode, op0, 1);
1615 /* Unless the msb of the field used to be the msb when we shifted,
1616 mask out the upper bits. */
1618 if (GET_MODE_BITSIZE (mode) != bitpos + bitsize
1620 #ifdef SLOW_ZERO_EXTEND
1621 /* Always generate an `and' if
1622 we just zero-extended op0 and SLOW_ZERO_EXTEND, since it
1623 will combine fruitfully with the zero-extend. */
1628 return expand_binop (GET_MODE (op0), and_optab, op0,
1629 mask_rtx (GET_MODE (op0), 0, bitsize, 0),
1630 target, 1, OPTAB_LIB_WIDEN);
1634 /* To extract a signed bit-field, first shift its msb to the msb of the word,
1635 then arithmetic-shift its lsb to the lsb of the word. */
1636 op0 = force_reg (mode, op0);
1640 /* Find the narrowest integer mode that contains the field. */
1642 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode;
1643 mode = GET_MODE_WIDER_MODE (mode))
1644 if (GET_MODE_BITSIZE (mode) >= bitsize + bitpos)
1646 op0 = convert_to_mode (mode, op0, 0);
1650 if (GET_MODE_BITSIZE (mode) != (bitsize + bitpos))
1652 tree amount = build_int_2 (GET_MODE_BITSIZE (mode) - (bitsize + bitpos), 0);
1653 /* Maybe propagate the target for the shift. */
1654 /* But not if we will return the result--could confuse integrate.c. */
1655 rtx subtarget = (target != 0 && GET_CODE (target) == REG
1656 && ! REG_FUNCTION_VALUE_P (target)
1658 op0 = expand_shift (LSHIFT_EXPR, mode, op0, amount, subtarget, 1);
1661 return expand_shift (RSHIFT_EXPR, mode, op0,
1662 build_int_2 (GET_MODE_BITSIZE (mode) - bitsize, 0),
1666 /* Return a constant integer (CONST_INT or CONST_DOUBLE) mask value
1667 of mode MODE with BITSIZE ones followed by BITPOS zeros, or the
1668 complement of that if COMPLEMENT. The mask is truncated if
1669 necessary to the width of mode MODE. The mask is zero-extended if
1670 BITSIZE+BITPOS is too small for MODE. */
1673 mask_rtx (mode, bitpos, bitsize, complement)
1674 enum machine_mode mode;
1675 int bitpos, bitsize, complement;
1677 HOST_WIDE_INT masklow, maskhigh;
1679 if (bitpos < HOST_BITS_PER_WIDE_INT)
1680 masklow = (HOST_WIDE_INT) -1 << bitpos;
1684 if (bitpos + bitsize < HOST_BITS_PER_WIDE_INT)
1685 masklow &= ((unsigned HOST_WIDE_INT) -1
1686 >> (HOST_BITS_PER_WIDE_INT - bitpos - bitsize));
1688 if (bitpos <= HOST_BITS_PER_WIDE_INT)
1691 maskhigh = (HOST_WIDE_INT) -1 << (bitpos - HOST_BITS_PER_WIDE_INT);
1693 if (bitpos + bitsize > HOST_BITS_PER_WIDE_INT)
1694 maskhigh &= ((unsigned HOST_WIDE_INT) -1
1695 >> (2 * HOST_BITS_PER_WIDE_INT - bitpos - bitsize));
1701 maskhigh = ~maskhigh;
1705 return immed_double_const (masklow, maskhigh, mode);
1708 /* Return a constant integer (CONST_INT or CONST_DOUBLE) rtx with the value
1709 VALUE truncated to BITSIZE bits and then shifted left BITPOS bits. */
1712 lshift_value (mode, value, bitpos, bitsize)
1713 enum machine_mode mode;
1715 int bitpos, bitsize;
1717 unsigned HOST_WIDE_INT v = INTVAL (value);
1718 HOST_WIDE_INT low, high;
1720 if (bitsize < HOST_BITS_PER_WIDE_INT)
1721 v &= ~((HOST_WIDE_INT) -1 << bitsize);
1723 if (bitpos < HOST_BITS_PER_WIDE_INT)
1726 high = (bitpos > 0 ? (v >> (HOST_BITS_PER_WIDE_INT - bitpos)) : 0);
1731 high = v << (bitpos - HOST_BITS_PER_WIDE_INT);
1734 return immed_double_const (low, high, mode);
1737 /* Extract a bit field that is split across two words
1738 and return an RTX for the result.
1740 OP0 is the REG, SUBREG or MEM rtx for the first of the two words.
1741 BITSIZE is the field width; BITPOS, position of its first bit, in the word.
1742 UNSIGNEDP is 1 if should zero-extend the contents; else sign-extend.
1744 ALIGN is the known alignment of OP0, measured in bytes.
1745 This is also the size of the memory objects to be used. */
1748 extract_split_bit_field (op0, bitsize, bitpos, unsignedp, align)
1750 int bitsize, bitpos, unsignedp, align;
1754 rtx result = NULL_RTX;
1757 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
1759 if (GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG)
1760 unit = BITS_PER_WORD;
1762 unit = MIN (align * BITS_PER_UNIT, BITS_PER_WORD);
1764 while (bitsdone < bitsize)
1771 offset = (bitpos + bitsdone) / unit;
1772 thispos = (bitpos + bitsdone) % unit;
1774 /* THISSIZE must not overrun a word boundary. Otherwise,
1775 extract_fixed_bit_field will call us again, and we will mutually
1777 thissize = MIN (bitsize - bitsdone, BITS_PER_WORD);
1778 thissize = MIN (thissize, unit - thispos);
1780 /* If OP0 is a register, then handle OFFSET here.
1782 When handling multiword bitfields, extract_bit_field may pass
1783 down a word_mode SUBREG of a larger REG for a bitfield that actually
1784 crosses a word boundary. Thus, for a SUBREG, we must find
1785 the current word starting from the base register. */
1786 if (GET_CODE (op0) == SUBREG)
1788 word = operand_subword_force (SUBREG_REG (op0),
1789 SUBREG_WORD (op0) + offset,
1790 GET_MODE (SUBREG_REG (op0)));
1793 else if (GET_CODE (op0) == REG)
1795 word = operand_subword_force (op0, offset, GET_MODE (op0));
1801 /* Extract the parts in bit-counting order,
1802 whose meaning is determined by BYTES_PER_UNIT.
1803 OFFSET is in UNITs, and UNIT is in bits.
1804 extract_fixed_bit_field wants offset in bytes. */
1805 part = extract_fixed_bit_field (word_mode, word,
1806 offset * unit / BITS_PER_UNIT,
1807 thissize, thispos, 0, 1, align);
1808 bitsdone += thissize;
1810 /* Shift this part into place for the result. */
1811 if (BYTES_BIG_ENDIAN)
1813 if (bitsize != bitsdone)
1814 part = expand_shift (LSHIFT_EXPR, word_mode, part,
1815 build_int_2 (bitsize - bitsdone, 0), 0, 1);
1819 if (bitsdone != thissize)
1820 part = expand_shift (LSHIFT_EXPR, word_mode, part,
1821 build_int_2 (bitsdone - thissize, 0), 0, 1);
1827 /* Combine the parts with bitwise or. This works
1828 because we extracted each part as an unsigned bit field. */
1829 result = expand_binop (word_mode, ior_optab, part, result, NULL_RTX, 1,
1835 /* Unsigned bit field: we are done. */
1838 /* Signed bit field: sign-extend with two arithmetic shifts. */
1839 result = expand_shift (LSHIFT_EXPR, word_mode, result,
1840 build_int_2 (BITS_PER_WORD - bitsize, 0),
1842 return expand_shift (RSHIFT_EXPR, word_mode, result,
1843 build_int_2 (BITS_PER_WORD - bitsize, 0), NULL_RTX, 0);
1846 /* Add INC into TARGET. */
1849 expand_inc (target, inc)
1852 rtx value = expand_binop (GET_MODE (target), add_optab,
1854 target, 0, OPTAB_LIB_WIDEN);
1855 if (value != target)
1856 emit_move_insn (target, value);
1859 /* Subtract DEC from TARGET. */
1862 expand_dec (target, dec)
1865 rtx value = expand_binop (GET_MODE (target), sub_optab,
1867 target, 0, OPTAB_LIB_WIDEN);
1868 if (value != target)
1869 emit_move_insn (target, value);
1872 /* Output a shift instruction for expression code CODE,
1873 with SHIFTED being the rtx for the value to shift,
1874 and AMOUNT the tree for the amount to shift by.
1875 Store the result in the rtx TARGET, if that is convenient.
1876 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
1877 Return the rtx for where the value is. */
1880 expand_shift (code, mode, shifted, amount, target, unsignedp)
1881 enum tree_code code;
1882 register enum machine_mode mode;
1885 register rtx target;
1888 register rtx op1, temp = 0;
1889 register int left = (code == LSHIFT_EXPR || code == LROTATE_EXPR);
1890 register int rotate = (code == LROTATE_EXPR || code == RROTATE_EXPR);
1893 /* Previously detected shift-counts computed by NEGATE_EXPR
1894 and shifted in the other direction; but that does not work
1897 op1 = expand_expr (amount, NULL_RTX, VOIDmode, 0);
1899 #ifdef SHIFT_COUNT_TRUNCATED
1900 if (SHIFT_COUNT_TRUNCATED)
1902 if (GET_CODE (op1) == CONST_INT
1903 && ((unsigned HOST_WIDE_INT) INTVAL (op1) >=
1904 (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode)))
1905 op1 = GEN_INT ((unsigned HOST_WIDE_INT) INTVAL (op1)
1906 % GET_MODE_BITSIZE (mode));
1907 else if (GET_CODE (op1) == SUBREG
1908 && SUBREG_WORD (op1) == 0)
1909 op1 = SUBREG_REG (op1);
1913 if (op1 == const0_rtx)
1916 for (try = 0; temp == 0 && try < 3; try++)
1918 enum optab_methods methods;
1921 methods = OPTAB_DIRECT;
1923 methods = OPTAB_WIDEN;
1925 methods = OPTAB_LIB_WIDEN;
1929 /* Widening does not work for rotation. */
1930 if (methods == OPTAB_WIDEN)
1932 else if (methods == OPTAB_LIB_WIDEN)
1934 /* If we have been unable to open-code this by a rotation,
1935 do it as the IOR of two shifts. I.e., to rotate A
1936 by N bits, compute (A << N) | ((unsigned) A >> (C - N))
1937 where C is the bitsize of A.
1939 It is theoretically possible that the target machine might
1940 not be able to perform either shift and hence we would
1941 be making two libcalls rather than just the one for the
1942 shift (similarly if IOR could not be done). We will allow
1943 this extremely unlikely lossage to avoid complicating the
1946 rtx subtarget = target == shifted ? 0 : target;
1948 tree type = TREE_TYPE (amount);
1949 tree new_amount = make_tree (type, op1);
1951 = fold (build (MINUS_EXPR, type,
1953 build_int_2 (GET_MODE_BITSIZE (mode),
1957 shifted = force_reg (mode, shifted);
1959 temp = expand_shift (left ? LSHIFT_EXPR : RSHIFT_EXPR,
1960 mode, shifted, new_amount, subtarget, 1);
1961 temp1 = expand_shift (left ? RSHIFT_EXPR : LSHIFT_EXPR,
1962 mode, shifted, other_amount, 0, 1);
1963 return expand_binop (mode, ior_optab, temp, temp1, target,
1964 unsignedp, methods);
1967 temp = expand_binop (mode,
1968 left ? rotl_optab : rotr_optab,
1969 shifted, op1, target, unsignedp, methods);
1971 /* If we don't have the rotate, but we are rotating by a constant
1972 that is in range, try a rotate in the opposite direction. */
1974 if (temp == 0 && GET_CODE (op1) == CONST_INT
1975 && INTVAL (op1) > 0 && INTVAL (op1) < GET_MODE_BITSIZE (mode))
1976 temp = expand_binop (mode,
1977 left ? rotr_optab : rotl_optab,
1979 GEN_INT (GET_MODE_BITSIZE (mode)
1981 target, unsignedp, methods);
1984 temp = expand_binop (mode,
1985 left ? ashl_optab : lshr_optab,
1986 shifted, op1, target, unsignedp, methods);
1988 /* Do arithmetic shifts.
1989 Also, if we are going to widen the operand, we can just as well
1990 use an arithmetic right-shift instead of a logical one. */
1991 if (temp == 0 && ! rotate
1992 && (! unsignedp || (! left && methods == OPTAB_WIDEN)))
1994 enum optab_methods methods1 = methods;
1996 /* If trying to widen a log shift to an arithmetic shift,
1997 don't accept an arithmetic shift of the same size. */
1999 methods1 = OPTAB_MUST_WIDEN;
2001 /* Arithmetic shift */
2003 temp = expand_binop (mode,
2004 left ? ashl_optab : ashr_optab,
2005 shifted, op1, target, unsignedp, methods1);
2008 /* We used to try extzv here for logical right shifts, but that was
2009 only useful for one machine, the VAX, and caused poor code
2010 generation there for lshrdi3, so the code was deleted and a
2011 define_expand for lshrsi3 was added to vax.md. */
2019 enum alg_code { alg_zero, alg_m, alg_shift,
2020 alg_add_t_m2, alg_sub_t_m2,
2021 alg_add_factor, alg_sub_factor,
2022 alg_add_t2_m, alg_sub_t2_m,
2023 alg_add, alg_subtract, alg_factor, alg_shiftop };
2025 /* This structure records a sequence of operations.
2026 `ops' is the number of operations recorded.
2027 `cost' is their total cost.
2028 The operations are stored in `op' and the corresponding
2029 logarithms of the integer coefficients in `log'.
2031 These are the operations:
2032 alg_zero total := 0;
2033 alg_m total := multiplicand;
2034 alg_shift total := total * coeff
2035 alg_add_t_m2 total := total + multiplicand * coeff;
2036 alg_sub_t_m2 total := total - multiplicand * coeff;
2037 alg_add_factor total := total * coeff + total;
2038 alg_sub_factor total := total * coeff - total;
2039 alg_add_t2_m total := total * coeff + multiplicand;
2040 alg_sub_t2_m total := total * coeff - multiplicand;
2042 The first operand must be either alg_zero or alg_m. */
2048 /* The size of the OP and LOG fields are not directly related to the
2049 word size, but the worst-case algorithms will be if we have few
2050 consecutive ones or zeros, i.e., a multiplicand like 10101010101...
2051 In that case we will generate shift-by-2, add, shift-by-2, add,...,
2052 in total wordsize operations. */
2053 enum alg_code op[MAX_BITS_PER_WORD];
2054 char log[MAX_BITS_PER_WORD];
2057 static void synth_mult PROTO((struct algorithm *,
2058 unsigned HOST_WIDE_INT,
2060 static unsigned HOST_WIDE_INT choose_multiplier PROTO((unsigned HOST_WIDE_INT,
2062 unsigned HOST_WIDE_INT *,
2064 static unsigned HOST_WIDE_INT invert_mod2n PROTO((unsigned HOST_WIDE_INT,
2066 /* Compute and return the best algorithm for multiplying by T.
2067 The algorithm must cost less than cost_limit
2068 If retval.cost >= COST_LIMIT, no algorithm was found and all
2069 other field of the returned struct are undefined. */
2072 synth_mult (alg_out, t, cost_limit)
2073 struct algorithm *alg_out;
2074 unsigned HOST_WIDE_INT t;
2078 struct algorithm *alg_in, *best_alg;
2080 unsigned HOST_WIDE_INT q;
2082 /* Indicate that no algorithm is yet found. If no algorithm
2083 is found, this value will be returned and indicate failure. */
2084 alg_out->cost = cost_limit;
2086 if (cost_limit <= 0)
2089 /* t == 1 can be done in zero cost. */
2094 alg_out->op[0] = alg_m;
2098 /* t == 0 sometimes has a cost. If it does and it exceeds our limit,
2102 if (zero_cost >= cost_limit)
2107 alg_out->cost = zero_cost;
2108 alg_out->op[0] = alg_zero;
2113 /* We'll be needing a couple extra algorithm structures now. */
2115 alg_in = (struct algorithm *)alloca (sizeof (struct algorithm));
2116 best_alg = (struct algorithm *)alloca (sizeof (struct algorithm));
2118 /* If we have a group of zero bits at the low-order part of T, try
2119 multiplying by the remaining bits and then doing a shift. */
2123 m = floor_log2 (t & -t); /* m = number of low zero bits */
2125 cost = shift_cost[m];
2126 synth_mult (alg_in, q, cost_limit - cost);
2128 cost += alg_in->cost;
2129 if (cost < cost_limit)
2131 struct algorithm *x;
2132 x = alg_in, alg_in = best_alg, best_alg = x;
2133 best_alg->log[best_alg->ops] = m;
2134 best_alg->op[best_alg->ops] = alg_shift;
2139 /* If we have an odd number, add or subtract one. */
2142 unsigned HOST_WIDE_INT w;
2144 for (w = 1; (w & t) != 0; w <<= 1)
2146 /* If T was -1, then W will be zero after the loop. This is another
2147 case where T ends with ...111. Handling this with (T + 1) and
2148 subtract 1 produces slightly better code and results in algorithm
2149 selection much faster than treating it like the ...0111 case
2153 /* Reject the case where t is 3.
2154 Thus we prefer addition in that case. */
2157 /* T ends with ...111. Multiply by (T + 1) and subtract 1. */
2160 synth_mult (alg_in, t + 1, cost_limit - cost);
2162 cost += alg_in->cost;
2163 if (cost < cost_limit)
2165 struct algorithm *x;
2166 x = alg_in, alg_in = best_alg, best_alg = x;
2167 best_alg->log[best_alg->ops] = 0;
2168 best_alg->op[best_alg->ops] = alg_sub_t_m2;
2174 /* T ends with ...01 or ...011. Multiply by (T - 1) and add 1. */
2177 synth_mult (alg_in, t - 1, cost_limit - cost);
2179 cost += alg_in->cost;
2180 if (cost < cost_limit)
2182 struct algorithm *x;
2183 x = alg_in, alg_in = best_alg, best_alg = x;
2184 best_alg->log[best_alg->ops] = 0;
2185 best_alg->op[best_alg->ops] = alg_add_t_m2;
2191 /* Look for factors of t of the form
2192 t = q(2**m +- 1), 2 <= m <= floor(log2(t - 1)).
2193 If we find such a factor, we can multiply by t using an algorithm that
2194 multiplies by q, shift the result by m and add/subtract it to itself.
2196 We search for large factors first and loop down, even if large factors
2197 are less probable than small; if we find a large factor we will find a
2198 good sequence quickly, and therefore be able to prune (by decreasing
2199 COST_LIMIT) the search. */
2201 for (m = floor_log2 (t - 1); m >= 2; m--)
2203 unsigned HOST_WIDE_INT d;
2205 d = ((unsigned HOST_WIDE_INT) 1 << m) + 1;
2206 if (t % d == 0 && t > d)
2208 cost = MIN (shiftadd_cost[m], add_cost + shift_cost[m]);
2209 synth_mult (alg_in, t / d, cost_limit - cost);
2211 cost += alg_in->cost;
2212 if (cost < cost_limit)
2214 struct algorithm *x;
2215 x = alg_in, alg_in = best_alg, best_alg = x;
2216 best_alg->log[best_alg->ops] = m;
2217 best_alg->op[best_alg->ops] = alg_add_factor;
2220 /* Other factors will have been taken care of in the recursion. */
2224 d = ((unsigned HOST_WIDE_INT) 1 << m) - 1;
2225 if (t % d == 0 && t > d)
2227 cost = MIN (shiftsub_cost[m], add_cost + shift_cost[m]);
2228 synth_mult (alg_in, t / d, cost_limit - cost);
2230 cost += alg_in->cost;
2231 if (cost < cost_limit)
2233 struct algorithm *x;
2234 x = alg_in, alg_in = best_alg, best_alg = x;
2235 best_alg->log[best_alg->ops] = m;
2236 best_alg->op[best_alg->ops] = alg_sub_factor;
2243 /* Try shift-and-add (load effective address) instructions,
2244 i.e. do a*3, a*5, a*9. */
2252 cost = shiftadd_cost[m];
2253 synth_mult (alg_in, (t - 1) >> m, cost_limit - cost);
2255 cost += alg_in->cost;
2256 if (cost < cost_limit)
2258 struct algorithm *x;
2259 x = alg_in, alg_in = best_alg, best_alg = x;
2260 best_alg->log[best_alg->ops] = m;
2261 best_alg->op[best_alg->ops] = alg_add_t2_m;
2271 cost = shiftsub_cost[m];
2272 synth_mult (alg_in, (t + 1) >> m, cost_limit - cost);
2274 cost += alg_in->cost;
2275 if (cost < cost_limit)
2277 struct algorithm *x;
2278 x = alg_in, alg_in = best_alg, best_alg = x;
2279 best_alg->log[best_alg->ops] = m;
2280 best_alg->op[best_alg->ops] = alg_sub_t2_m;
2286 /* If cost_limit has not decreased since we stored it in alg_out->cost,
2287 we have not found any algorithm. */
2288 if (cost_limit == alg_out->cost)
2291 /* If we are getting a too long sequence for `struct algorithm'
2292 to record, make this search fail. */
2293 if (best_alg->ops == MAX_BITS_PER_WORD)
2296 /* Copy the algorithm from temporary space to the space at alg_out.
2297 We avoid using structure assignment because the majority of
2298 best_alg is normally undefined, and this is a critical function. */
2299 alg_out->ops = best_alg->ops + 1;
2300 alg_out->cost = cost_limit;
2301 bcopy ((char *) best_alg->op, (char *) alg_out->op,
2302 alg_out->ops * sizeof *alg_out->op);
2303 bcopy ((char *) best_alg->log, (char *) alg_out->log,
2304 alg_out->ops * sizeof *alg_out->log);
2307 /* Perform a multiplication and return an rtx for the result.
2308 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
2309 TARGET is a suggestion for where to store the result (an rtx).
2311 We check specially for a constant integer as OP1.
2312 If you want this check for OP0 as well, then before calling
2313 you should swap the two operands if OP0 would be constant. */
2316 expand_mult (mode, op0, op1, target, unsignedp)
2317 enum machine_mode mode;
2318 register rtx op0, op1, target;
2321 rtx const_op1 = op1;
2323 /* synth_mult does an `unsigned int' multiply. As long as the mode is
2324 less than or equal in size to `unsigned int' this doesn't matter.
2325 If the mode is larger than `unsigned int', then synth_mult works only
2326 if the constant value exactly fits in an `unsigned int' without any
2327 truncation. This means that multiplying by negative values does
2328 not work; results are off by 2^32 on a 32 bit machine. */
2330 /* If we are multiplying in DImode, it may still be a win
2331 to try to work with shifts and adds. */
2332 if (GET_CODE (op1) == CONST_DOUBLE
2333 && GET_MODE_CLASS (GET_MODE (op1)) == MODE_INT
2334 && HOST_BITS_PER_INT >= BITS_PER_WORD
2335 && CONST_DOUBLE_HIGH (op1) == 0)
2336 const_op1 = GEN_INT (CONST_DOUBLE_LOW (op1));
2337 else if (HOST_BITS_PER_INT < GET_MODE_BITSIZE (mode)
2338 && GET_CODE (op1) == CONST_INT
2339 && INTVAL (op1) < 0)
2342 /* We used to test optimize here, on the grounds that it's better to
2343 produce a smaller program when -O is not used.
2344 But this causes such a terrible slowdown sometimes
2345 that it seems better to use synth_mult always. */
2347 if (const_op1 && GET_CODE (const_op1) == CONST_INT)
2349 struct algorithm alg;
2350 struct algorithm alg2;
2351 HOST_WIDE_INT val = INTVAL (op1);
2352 HOST_WIDE_INT val_so_far;
2355 enum {basic_variant, negate_variant, add_variant} variant = basic_variant;
2357 /* Try to do the computation three ways: multiply by the negative of OP1
2358 and then negate, do the multiplication directly, or do multiplication
2361 mult_cost = rtx_cost (gen_rtx_MULT (mode, op0, op1), SET);
2362 mult_cost = MIN (12 * add_cost, mult_cost);
2364 synth_mult (&alg, val, mult_cost);
2366 /* This works only if the inverted value actually fits in an
2368 if (HOST_BITS_PER_INT >= GET_MODE_BITSIZE (mode))
2370 synth_mult (&alg2, - val,
2371 (alg.cost < mult_cost ? alg.cost : mult_cost) - negate_cost);
2372 if (alg2.cost + negate_cost < alg.cost)
2373 alg = alg2, variant = negate_variant;
2376 /* This proves very useful for division-by-constant. */
2377 synth_mult (&alg2, val - 1,
2378 (alg.cost < mult_cost ? alg.cost : mult_cost) - add_cost);
2379 if (alg2.cost + add_cost < alg.cost)
2380 alg = alg2, variant = add_variant;
2382 if (alg.cost < mult_cost)
2384 /* We found something cheaper than a multiply insn. */
2388 op0 = protect_from_queue (op0, 0);
2390 /* Avoid referencing memory over and over.
2391 For speed, but also for correctness when mem is volatile. */
2392 if (GET_CODE (op0) == MEM)
2393 op0 = force_reg (mode, op0);
2395 /* ACCUM starts out either as OP0 or as a zero, depending on
2396 the first operation. */
2398 if (alg.op[0] == alg_zero)
2400 accum = copy_to_mode_reg (mode, const0_rtx);
2403 else if (alg.op[0] == alg_m)
2405 accum = copy_to_mode_reg (mode, op0);
2411 for (opno = 1; opno < alg.ops; opno++)
2413 int log = alg.log[opno];
2414 int preserve = preserve_subexpressions_p ();
2415 rtx shift_subtarget = preserve ? 0 : accum;
2417 = (opno == alg.ops - 1 && target != 0 && variant != add_variant
2420 rtx accum_target = preserve ? 0 : accum;
2422 switch (alg.op[opno])
2425 accum = expand_shift (LSHIFT_EXPR, mode, accum,
2426 build_int_2 (log, 0), NULL_RTX, 0);
2431 tem = expand_shift (LSHIFT_EXPR, mode, op0,
2432 build_int_2 (log, 0), NULL_RTX, 0);
2433 accum = force_operand (gen_rtx_PLUS (mode, accum, tem),
2435 ? add_target : accum_target);
2436 val_so_far += (HOST_WIDE_INT) 1 << log;
2440 tem = expand_shift (LSHIFT_EXPR, mode, op0,
2441 build_int_2 (log, 0), NULL_RTX, 0);
2442 accum = force_operand (gen_rtx_MINUS (mode, accum, tem),
2444 ? add_target : accum_target);
2445 val_so_far -= (HOST_WIDE_INT) 1 << log;
2449 accum = expand_shift (LSHIFT_EXPR, mode, accum,
2450 build_int_2 (log, 0), shift_subtarget,
2452 accum = force_operand (gen_rtx_PLUS (mode, accum, op0),
2454 ? add_target : accum_target);
2455 val_so_far = (val_so_far << log) + 1;
2459 accum = expand_shift (LSHIFT_EXPR, mode, accum,
2460 build_int_2 (log, 0), shift_subtarget,
2462 accum = force_operand (gen_rtx_MINUS (mode, accum, op0),
2464 ? add_target : accum_target);
2465 val_so_far = (val_so_far << log) - 1;
2468 case alg_add_factor:
2469 tem = expand_shift (LSHIFT_EXPR, mode, accum,
2470 build_int_2 (log, 0), NULL_RTX, 0);
2471 accum = force_operand (gen_rtx_PLUS (mode, accum, tem),
2473 ? add_target : accum_target);
2474 val_so_far += val_so_far << log;
2477 case alg_sub_factor:
2478 tem = expand_shift (LSHIFT_EXPR, mode, accum,
2479 build_int_2 (log, 0), NULL_RTX, 0);
2480 accum = force_operand (gen_rtx_MINUS (mode, tem, accum),
2481 (add_target ? add_target
2482 : preserve ? 0 : tem));
2483 val_so_far = (val_so_far << log) - val_so_far;
2490 /* Write a REG_EQUAL note on the last insn so that we can cse
2491 multiplication sequences. */
2493 insn = get_last_insn ();
2494 set_unique_reg_note (insn,
2496 gen_rtx_MULT (mode, op0,
2497 GEN_INT (val_so_far)));
2500 if (variant == negate_variant)
2502 val_so_far = - val_so_far;
2503 accum = expand_unop (mode, neg_optab, accum, target, 0);
2505 else if (variant == add_variant)
2507 val_so_far = val_so_far + 1;
2508 accum = force_operand (gen_rtx_PLUS (mode, accum, op0), target);
2511 if (val != val_so_far)
2518 /* This used to use umul_optab if unsigned, but for non-widening multiply
2519 there is no difference between signed and unsigned. */
2520 op0 = expand_binop (mode, smul_optab,
2521 op0, op1, target, unsignedp, OPTAB_LIB_WIDEN);
2527 /* Return the smallest n such that 2**n >= X. */
2531 unsigned HOST_WIDE_INT x;
2533 return floor_log2 (x - 1) + 1;
2536 /* Choose a minimal N + 1 bit approximation to 1/D that can be used to
2537 replace division by D, and put the least significant N bits of the result
2538 in *MULTIPLIER_PTR and return the most significant bit.
2540 The width of operations is N (should be <= HOST_BITS_PER_WIDE_INT), the
2541 needed precision is in PRECISION (should be <= N).
2543 PRECISION should be as small as possible so this function can choose
2544 multiplier more freely.
2546 The rounded-up logarithm of D is placed in *lgup_ptr. A shift count that
2547 is to be used for a final right shift is placed in *POST_SHIFT_PTR.
2549 Using this function, x/D will be equal to (x * m) >> (*POST_SHIFT_PTR),
2550 where m is the full HOST_BITS_PER_WIDE_INT + 1 bit multiplier. */
2553 unsigned HOST_WIDE_INT
2554 choose_multiplier (d, n, precision, multiplier_ptr, post_shift_ptr, lgup_ptr)
2555 unsigned HOST_WIDE_INT d;
2558 unsigned HOST_WIDE_INT *multiplier_ptr;
2559 int *post_shift_ptr;
2562 unsigned HOST_WIDE_INT mhigh_hi, mhigh_lo;
2563 unsigned HOST_WIDE_INT mlow_hi, mlow_lo;
2564 int lgup, post_shift;
2566 unsigned HOST_WIDE_INT nh, nl, dummy1, dummy2;
2568 /* lgup = ceil(log2(divisor)); */
2569 lgup = ceil_log2 (d);
2575 pow2 = n + lgup - precision;
2577 if (pow == 2 * HOST_BITS_PER_WIDE_INT)
2579 /* We could handle this with some effort, but this case is much better
2580 handled directly with a scc insn, so rely on caller using that. */
2584 /* mlow = 2^(N + lgup)/d */
2585 if (pow >= HOST_BITS_PER_WIDE_INT)
2587 nh = (unsigned HOST_WIDE_INT) 1 << (pow - HOST_BITS_PER_WIDE_INT);
2593 nl = (unsigned HOST_WIDE_INT) 1 << pow;
2595 div_and_round_double (TRUNC_DIV_EXPR, 1, nl, nh, d, (HOST_WIDE_INT) 0,
2596 &mlow_lo, &mlow_hi, &dummy1, &dummy2);
2598 /* mhigh = (2^(N + lgup) + 2^N + lgup - precision)/d */
2599 if (pow2 >= HOST_BITS_PER_WIDE_INT)
2600 nh |= (unsigned HOST_WIDE_INT) 1 << (pow2 - HOST_BITS_PER_WIDE_INT);
2602 nl |= (unsigned HOST_WIDE_INT) 1 << pow2;
2603 div_and_round_double (TRUNC_DIV_EXPR, 1, nl, nh, d, (HOST_WIDE_INT) 0,
2604 &mhigh_lo, &mhigh_hi, &dummy1, &dummy2);
2606 if (mhigh_hi && nh - d >= d)
2608 if (mhigh_hi > 1 || mlow_hi > 1)
2610 /* assert that mlow < mhigh. */
2611 if (! (mlow_hi < mhigh_hi || (mlow_hi == mhigh_hi && mlow_lo < mhigh_lo)))
2614 /* If precision == N, then mlow, mhigh exceed 2^N
2615 (but they do not exceed 2^(N+1)). */
2617 /* Reduce to lowest terms */
2618 for (post_shift = lgup; post_shift > 0; post_shift--)
2620 unsigned HOST_WIDE_INT ml_lo = (mlow_hi << (HOST_BITS_PER_WIDE_INT - 1)) | (mlow_lo >> 1);
2621 unsigned HOST_WIDE_INT mh_lo = (mhigh_hi << (HOST_BITS_PER_WIDE_INT - 1)) | (mhigh_lo >> 1);
2631 *post_shift_ptr = post_shift;
2633 if (n < HOST_BITS_PER_WIDE_INT)
2635 unsigned HOST_WIDE_INT mask = ((unsigned HOST_WIDE_INT) 1 << n) - 1;
2636 *multiplier_ptr = mhigh_lo & mask;
2637 return mhigh_lo >= mask;
2641 *multiplier_ptr = mhigh_lo;
2646 /* Compute the inverse of X mod 2**n, i.e., find Y such that X * Y is
2647 congruent to 1 (mod 2**N). */
2649 static unsigned HOST_WIDE_INT
2651 unsigned HOST_WIDE_INT x;
2654 /* Solve x*y == 1 (mod 2^n), where x is odd. Return y. */
2656 /* The algorithm notes that the choice y = x satisfies
2657 x*y == 1 mod 2^3, since x is assumed odd.
2658 Each iteration doubles the number of bits of significance in y. */
2660 unsigned HOST_WIDE_INT mask;
2661 unsigned HOST_WIDE_INT y = x;
2664 mask = (n == HOST_BITS_PER_WIDE_INT
2665 ? ~(unsigned HOST_WIDE_INT) 0
2666 : ((unsigned HOST_WIDE_INT) 1 << n) - 1);
2670 y = y * (2 - x*y) & mask; /* Modulo 2^N */
2676 /* Emit code to adjust ADJ_OPERAND after multiplication of wrong signedness
2677 flavor of OP0 and OP1. ADJ_OPERAND is already the high half of the
2678 product OP0 x OP1. If UNSIGNEDP is nonzero, adjust the signed product
2679 to become unsigned, if UNSIGNEDP is zero, adjust the unsigned product to
2682 The result is put in TARGET if that is convenient.
2684 MODE is the mode of operation. */
2687 expand_mult_highpart_adjust (mode, adj_operand, op0, op1, target, unsignedp)
2688 enum machine_mode mode;
2689 register rtx adj_operand, op0, op1, target;
2693 enum rtx_code adj_code = unsignedp ? PLUS : MINUS;
2695 tem = expand_shift (RSHIFT_EXPR, mode, op0,
2696 build_int_2 (GET_MODE_BITSIZE (mode) - 1, 0),
2698 tem = expand_and (tem, op1, NULL_RTX);
2700 = force_operand (gen_rtx_fmt_ee (adj_code, mode, adj_operand, tem),
2703 tem = expand_shift (RSHIFT_EXPR, mode, op1,
2704 build_int_2 (GET_MODE_BITSIZE (mode) - 1, 0),
2706 tem = expand_and (tem, op0, NULL_RTX);
2707 target = force_operand (gen_rtx_fmt_ee (adj_code, mode, adj_operand, tem),
2713 /* Emit code to multiply OP0 and CNST1, putting the high half of the result
2714 in TARGET if that is convenient, and return where the result is. If the
2715 operation can not be performed, 0 is returned.
2717 MODE is the mode of operation and result.
2719 UNSIGNEDP nonzero means unsigned multiply.
2721 MAX_COST is the total allowed cost for the expanded RTL. */
2724 expand_mult_highpart (mode, op0, cnst1, target, unsignedp, max_cost)
2725 enum machine_mode mode;
2726 register rtx op0, target;
2727 unsigned HOST_WIDE_INT cnst1;
2731 enum machine_mode wider_mode = GET_MODE_WIDER_MODE (mode);
2732 optab mul_highpart_optab;
2735 int size = GET_MODE_BITSIZE (mode);
2738 /* We can't support modes wider than HOST_BITS_PER_INT. */
2739 if (size > HOST_BITS_PER_WIDE_INT)
2742 op1 = GEN_INT (cnst1);
2744 if (GET_MODE_BITSIZE (wider_mode) <= HOST_BITS_PER_INT)
2748 = immed_double_const (cnst1,
2751 : -(cnst1 >> (HOST_BITS_PER_WIDE_INT - 1))),
2754 /* expand_mult handles constant multiplication of word_mode
2755 or narrower. It does a poor job for large modes. */
2756 if (size < BITS_PER_WORD
2757 && mul_cost[(int) wider_mode] + shift_cost[size-1] < max_cost)
2759 /* We have to do this, since expand_binop doesn't do conversion for
2760 multiply. Maybe change expand_binop to handle widening multiply? */
2761 op0 = convert_to_mode (wider_mode, op0, unsignedp);
2763 tem = expand_mult (wider_mode, op0, wide_op1, NULL_RTX, unsignedp);
2764 tem = expand_shift (RSHIFT_EXPR, wider_mode, tem,
2765 build_int_2 (size, 0), NULL_RTX, 1);
2766 return convert_modes (mode, wider_mode, tem, unsignedp);
2770 target = gen_reg_rtx (mode);
2772 /* Firstly, try using a multiplication insn that only generates the needed
2773 high part of the product, and in the sign flavor of unsignedp. */
2774 if (mul_highpart_cost[(int) mode] < max_cost)
2776 mul_highpart_optab = unsignedp ? umul_highpart_optab : smul_highpart_optab;
2777 target = expand_binop (mode, mul_highpart_optab,
2778 op0, wide_op1, target, unsignedp, OPTAB_DIRECT);
2783 /* Secondly, same as above, but use sign flavor opposite of unsignedp.
2784 Need to adjust the result after the multiplication. */
2785 if (mul_highpart_cost[(int) mode] + 2 * shift_cost[size-1] + 4 * add_cost < max_cost)
2787 mul_highpart_optab = unsignedp ? smul_highpart_optab : umul_highpart_optab;
2788 target = expand_binop (mode, mul_highpart_optab,
2789 op0, wide_op1, target, unsignedp, OPTAB_DIRECT);
2791 /* We used the wrong signedness. Adjust the result. */
2792 return expand_mult_highpart_adjust (mode, target, op0,
2793 op1, target, unsignedp);
2796 /* Try widening multiplication. */
2797 moptab = unsignedp ? umul_widen_optab : smul_widen_optab;
2798 if (moptab->handlers[(int) wider_mode].insn_code != CODE_FOR_nothing
2799 && mul_widen_cost[(int) wider_mode] < max_cost)
2801 op1 = force_reg (mode, op1);
2805 /* Try widening the mode and perform a non-widening multiplication. */
2806 moptab = smul_optab;
2807 if (smul_optab->handlers[(int) wider_mode].insn_code != CODE_FOR_nothing
2808 && mul_cost[(int) wider_mode] + shift_cost[size-1] < max_cost)
2814 /* Try widening multiplication of opposite signedness, and adjust. */
2815 moptab = unsignedp ? smul_widen_optab : umul_widen_optab;
2816 if (moptab->handlers[(int) wider_mode].insn_code != CODE_FOR_nothing
2817 && (mul_widen_cost[(int) wider_mode]
2818 + 2 * shift_cost[size-1] + 4 * add_cost < max_cost))
2820 rtx regop1 = force_reg (mode, op1);
2821 tem = expand_binop (wider_mode, moptab, op0, regop1,
2822 NULL_RTX, ! unsignedp, OPTAB_WIDEN);
2825 /* Extract the high half of the just generated product. */
2826 tem = expand_shift (RSHIFT_EXPR, wider_mode, tem,
2827 build_int_2 (size, 0), NULL_RTX, 1);
2828 tem = convert_modes (mode, wider_mode, tem, unsignedp);
2829 /* We used the wrong signedness. Adjust the result. */
2830 return expand_mult_highpart_adjust (mode, tem, op0, op1,
2838 /* Pass NULL_RTX as target since TARGET has wrong mode. */
2839 tem = expand_binop (wider_mode, moptab, op0, op1,
2840 NULL_RTX, unsignedp, OPTAB_WIDEN);
2844 /* Extract the high half of the just generated product. */
2845 if (mode == word_mode)
2847 return gen_highpart (mode, tem);
2851 tem = expand_shift (RSHIFT_EXPR, wider_mode, tem,
2852 build_int_2 (size, 0), NULL_RTX, 1);
2853 return convert_modes (mode, wider_mode, tem, unsignedp);
2857 /* Emit the code to divide OP0 by OP1, putting the result in TARGET
2858 if that is convenient, and returning where the result is.
2859 You may request either the quotient or the remainder as the result;
2860 specify REM_FLAG nonzero to get the remainder.
2862 CODE is the expression code for which kind of division this is;
2863 it controls how rounding is done. MODE is the machine mode to use.
2864 UNSIGNEDP nonzero means do unsigned division. */
2866 /* ??? For CEIL_MOD_EXPR, can compute incorrect remainder with ANDI
2867 and then correct it by or'ing in missing high bits
2868 if result of ANDI is nonzero.
2869 For ROUND_MOD_EXPR, can use ANDI and then sign-extend the result.
2870 This could optimize to a bfexts instruction.
2871 But C doesn't use these operations, so their optimizations are
2873 /* ??? For modulo, we don't actually need the highpart of the first product,
2874 the low part will do nicely. And for small divisors, the second multiply
2875 can also be a low-part only multiply or even be completely left out.
2876 E.g. to calculate the remainder of a division by 3 with a 32 bit
2877 multiply, multiply with 0x55555556 and extract the upper two bits;
2878 the result is exact for inputs up to 0x1fffffff.
2879 The input range can be reduced by using cross-sum rules.
2880 For odd divisors >= 3, the following table gives right shift counts
2881 so that if an number is shifted by an integer multiple of the given
2882 amount, the remainder stays the same:
2883 2, 4, 3, 6, 10, 12, 4, 8, 18, 6, 11, 20, 18, 0, 5, 10, 12, 0, 12, 20,
2884 14, 12, 23, 21, 8, 0, 20, 18, 0, 0, 6, 12, 0, 22, 0, 18, 20, 30, 0, 0,
2885 0, 8, 0, 11, 12, 10, 36, 0, 30, 0, 0, 12, 0, 0, 0, 0, 44, 12, 24, 0,
2886 20, 0, 7, 14, 0, 18, 36, 0, 0, 46, 60, 0, 42, 0, 15, 24, 20, 0, 0, 33,
2887 0, 20, 0, 0, 18, 0, 60, 0, 0, 0, 0, 0, 40, 18, 0, 0, 12
2889 Cross-sum rules for even numbers can be derived by leaving as many bits
2890 to the right alone as the divisor has zeros to the right.
2891 E.g. if x is an unsigned 32 bit number:
2892 (x mod 12) == (((x & 1023) + ((x >> 8) & ~3)) * 0x15555558 >> 2 * 3) >> 28
2895 #define EXACT_POWER_OF_2_OR_ZERO_P(x) (((x) & ((x) - 1)) == 0)
2898 expand_divmod (rem_flag, code, mode, op0, op1, target, unsignedp)
2900 enum tree_code code;
2901 enum machine_mode mode;
2902 register rtx op0, op1, target;
2905 enum machine_mode compute_mode;
2906 register rtx tquotient;
2907 rtx quotient = 0, remainder = 0;
2911 optab optab1, optab2;
2912 int op1_is_constant, op1_is_pow2;
2913 int max_cost, extra_cost;
2914 static HOST_WIDE_INT last_div_const = 0;
2916 op1_is_constant = GET_CODE (op1) == CONST_INT;
2917 op1_is_pow2 = (op1_is_constant
2918 && ((EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1))
2919 || (! unsignedp && EXACT_POWER_OF_2_OR_ZERO_P (-INTVAL (op1))))));
2922 This is the structure of expand_divmod:
2924 First comes code to fix up the operands so we can perform the operations
2925 correctly and efficiently.
2927 Second comes a switch statement with code specific for each rounding mode.
2928 For some special operands this code emits all RTL for the desired
2929 operation, for other cases, it generates only a quotient and stores it in
2930 QUOTIENT. The case for trunc division/remainder might leave quotient = 0,
2931 to indicate that it has not done anything.
2933 Last comes code that finishes the operation. If QUOTIENT is set and
2934 REM_FLAG is set, the remainder is computed as OP0 - QUOTIENT * OP1. If
2935 QUOTIENT is not set, it is computed using trunc rounding.
2937 We try to generate special code for division and remainder when OP1 is a
2938 constant. If |OP1| = 2**n we can use shifts and some other fast
2939 operations. For other values of OP1, we compute a carefully selected
2940 fixed-point approximation m = 1/OP1, and generate code that multiplies OP0
2943 In all cases but EXACT_DIV_EXPR, this multiplication requires the upper
2944 half of the product. Different strategies for generating the product are
2945 implemented in expand_mult_highpart.
2947 If what we actually want is the remainder, we generate that by another
2948 by-constant multiplication and a subtraction. */
2950 /* We shouldn't be called with OP1 == const1_rtx, but some of the
2951 code below will malfunction if we are, so check here and handle
2952 the special case if so. */
2953 if (op1 == const1_rtx)
2954 return rem_flag ? const0_rtx : op0;
2957 /* Don't use the function value register as a target
2958 since we have to read it as well as write it,
2959 and function-inlining gets confused by this. */
2960 && ((REG_P (target) && REG_FUNCTION_VALUE_P (target))
2961 /* Don't clobber an operand while doing a multi-step calculation. */
2962 || ((rem_flag || op1_is_constant)
2963 && (reg_mentioned_p (target, op0)
2964 || (GET_CODE (op0) == MEM && GET_CODE (target) == MEM)))
2965 || reg_mentioned_p (target, op1)
2966 || (GET_CODE (op1) == MEM && GET_CODE (target) == MEM)))
2969 /* Get the mode in which to perform this computation. Normally it will
2970 be MODE, but sometimes we can't do the desired operation in MODE.
2971 If so, pick a wider mode in which we can do the operation. Convert
2972 to that mode at the start to avoid repeated conversions.
2974 First see what operations we need. These depend on the expression
2975 we are evaluating. (We assume that divxx3 insns exist under the
2976 same conditions that modxx3 insns and that these insns don't normally
2977 fail. If these assumptions are not correct, we may generate less
2978 efficient code in some cases.)
2980 Then see if we find a mode in which we can open-code that operation
2981 (either a division, modulus, or shift). Finally, check for the smallest
2982 mode for which we can do the operation with a library call. */
2984 /* We might want to refine this now that we have division-by-constant
2985 optimization. Since expand_mult_highpart tries so many variants, it is
2986 not straightforward to generalize this. Maybe we should make an array
2987 of possible modes in init_expmed? Save this for GCC 2.7. */
2989 optab1 = (op1_is_pow2 ? (unsignedp ? lshr_optab : ashr_optab)
2990 : (unsignedp ? udiv_optab : sdiv_optab));
2991 optab2 = (op1_is_pow2 ? optab1 : (unsignedp ? udivmod_optab : sdivmod_optab));
2993 for (compute_mode = mode; compute_mode != VOIDmode;
2994 compute_mode = GET_MODE_WIDER_MODE (compute_mode))
2995 if (optab1->handlers[(int) compute_mode].insn_code != CODE_FOR_nothing
2996 || optab2->handlers[(int) compute_mode].insn_code != CODE_FOR_nothing)
2999 if (compute_mode == VOIDmode)
3000 for (compute_mode = mode; compute_mode != VOIDmode;
3001 compute_mode = GET_MODE_WIDER_MODE (compute_mode))
3002 if (optab1->handlers[(int) compute_mode].libfunc
3003 || optab2->handlers[(int) compute_mode].libfunc)
3006 /* If we still couldn't find a mode, use MODE, but we'll probably abort
3008 if (compute_mode == VOIDmode)
3009 compute_mode = mode;
3011 if (target && GET_MODE (target) == compute_mode)
3014 tquotient = gen_reg_rtx (compute_mode);
3016 size = GET_MODE_BITSIZE (compute_mode);
3018 /* It should be possible to restrict the precision to GET_MODE_BITSIZE
3019 (mode), and thereby get better code when OP1 is a constant. Do that
3020 later. It will require going over all usages of SIZE below. */
3021 size = GET_MODE_BITSIZE (mode);
3024 /* Only deduct something for a REM if the last divide done was
3025 for a different constant. Then set the constant of the last
3027 max_cost = div_cost[(int) compute_mode]
3028 - (rem_flag && ! (last_div_const != 0 && op1_is_constant
3029 && INTVAL (op1) == last_div_const)
3030 ? mul_cost[(int) compute_mode] + add_cost : 0);
3032 last_div_const = ! rem_flag && op1_is_constant ? INTVAL (op1) : 0;
3034 /* Now convert to the best mode to use. */
3035 if (compute_mode != mode)
3037 op0 = convert_modes (compute_mode, mode, op0, unsignedp);
3038 op1 = convert_modes (compute_mode, mode, op1, unsignedp);
3040 /* convert_modes may have placed op1 into a register, so we
3041 must recompute the following. */
3042 op1_is_constant = GET_CODE (op1) == CONST_INT;
3043 op1_is_pow2 = (op1_is_constant
3044 && ((EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1))
3046 && EXACT_POWER_OF_2_OR_ZERO_P (-INTVAL (op1)))))) ;
3049 /* If one of the operands is a volatile MEM, copy it into a register. */
3051 if (GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0))
3052 op0 = force_reg (compute_mode, op0);
3053 if (GET_CODE (op1) == MEM && MEM_VOLATILE_P (op1))
3054 op1 = force_reg (compute_mode, op1);
3056 /* If we need the remainder or if OP1 is constant, we need to
3057 put OP0 in a register in case it has any queued subexpressions. */
3058 if (rem_flag || op1_is_constant)
3059 op0 = force_reg (compute_mode, op0);
3061 last = get_last_insn ();
3063 /* Promote floor rounding to trunc rounding for unsigned operations. */
3066 if (code == FLOOR_DIV_EXPR)
3067 code = TRUNC_DIV_EXPR;
3068 if (code == FLOOR_MOD_EXPR)
3069 code = TRUNC_MOD_EXPR;
3070 if (code == EXACT_DIV_EXPR && op1_is_pow2)
3071 code = TRUNC_DIV_EXPR;
3074 if (op1 != const0_rtx)
3077 case TRUNC_MOD_EXPR:
3078 case TRUNC_DIV_EXPR:
3079 if (op1_is_constant)
3083 unsigned HOST_WIDE_INT mh, ml;
3084 int pre_shift, post_shift;
3086 unsigned HOST_WIDE_INT d = INTVAL (op1);
3088 if (EXACT_POWER_OF_2_OR_ZERO_P (d))
3090 pre_shift = floor_log2 (d);
3094 = expand_binop (compute_mode, and_optab, op0,
3095 GEN_INT (((HOST_WIDE_INT) 1 << pre_shift) - 1),
3099 return gen_lowpart (mode, remainder);
3101 quotient = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3102 build_int_2 (pre_shift, 0),
3105 else if (size <= HOST_BITS_PER_WIDE_INT)
3107 if (d >= ((unsigned HOST_WIDE_INT) 1 << (size - 1)))
3109 /* Most significant bit of divisor is set; emit an scc
3111 quotient = emit_store_flag (tquotient, GEU, op0, op1,
3112 compute_mode, 1, 1);
3118 /* Find a suitable multiplier and right shift count
3119 instead of multiplying with D. */
3121 mh = choose_multiplier (d, size, size,
3122 &ml, &post_shift, &dummy);
3124 /* If the suggested multiplier is more than SIZE bits,
3125 we can do better for even divisors, using an
3126 initial right shift. */
3127 if (mh != 0 && (d & 1) == 0)
3129 pre_shift = floor_log2 (d & -d);
3130 mh = choose_multiplier (d >> pre_shift, size,
3132 &ml, &post_shift, &dummy);
3143 extra_cost = (shift_cost[post_shift - 1]
3144 + shift_cost[1] + 2 * add_cost);
3145 t1 = expand_mult_highpart (compute_mode, op0, ml,
3147 max_cost - extra_cost);
3150 t2 = force_operand (gen_rtx_MINUS (compute_mode,
3153 t3 = expand_shift (RSHIFT_EXPR, compute_mode, t2,
3154 build_int_2 (1, 0), NULL_RTX,1);
3155 t4 = force_operand (gen_rtx_PLUS (compute_mode,
3159 = expand_shift (RSHIFT_EXPR, compute_mode, t4,
3160 build_int_2 (post_shift - 1, 0),
3167 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3168 build_int_2 (pre_shift, 0),
3170 extra_cost = (shift_cost[pre_shift]
3171 + shift_cost[post_shift]);
3172 t2 = expand_mult_highpart (compute_mode, t1, ml,
3174 max_cost - extra_cost);
3178 = expand_shift (RSHIFT_EXPR, compute_mode, t2,
3179 build_int_2 (post_shift, 0),
3184 else /* Too wide mode to use tricky code */
3187 insn = get_last_insn ();
3189 && (set = single_set (insn)) != 0
3190 && SET_DEST (set) == quotient)
3191 set_unique_reg_note (insn,
3193 gen_rtx_UDIV (compute_mode, op0, op1));
3195 else /* TRUNC_DIV, signed */
3197 unsigned HOST_WIDE_INT ml;
3198 int lgup, post_shift;
3199 HOST_WIDE_INT d = INTVAL (op1);
3200 unsigned HOST_WIDE_INT abs_d = d >= 0 ? d : -d;
3202 /* n rem d = n rem -d */
3203 if (rem_flag && d < 0)
3206 op1 = GEN_INT (abs_d);
3212 quotient = expand_unop (compute_mode, neg_optab, op0,
3214 else if (abs_d == (unsigned HOST_WIDE_INT) 1 << (size - 1))
3216 /* This case is not handled correctly below. */
3217 quotient = emit_store_flag (tquotient, EQ, op0, op1,
3218 compute_mode, 1, 1);
3222 else if (EXACT_POWER_OF_2_OR_ZERO_P (d)
3223 && (rem_flag ? smod_pow2_cheap : sdiv_pow2_cheap))
3225 else if (EXACT_POWER_OF_2_OR_ZERO_P (abs_d))
3227 lgup = floor_log2 (abs_d);
3228 if (abs_d != 2 && BRANCH_COST < 3)
3230 rtx label = gen_label_rtx ();
3233 t1 = copy_to_mode_reg (compute_mode, op0);
3234 do_cmp_and_jump (t1, const0_rtx, GE,
3235 compute_mode, label);
3236 expand_inc (t1, GEN_INT (abs_d - 1));
3238 quotient = expand_shift (RSHIFT_EXPR, compute_mode, t1,
3239 build_int_2 (lgup, 0),
3245 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3246 build_int_2 (size - 1, 0),
3248 t2 = expand_shift (RSHIFT_EXPR, compute_mode, t1,
3249 build_int_2 (size - lgup, 0),
3251 t3 = force_operand (gen_rtx_PLUS (compute_mode,
3254 quotient = expand_shift (RSHIFT_EXPR, compute_mode, t3,
3255 build_int_2 (lgup, 0),
3259 /* We have computed OP0 / abs(OP1). If OP1 is negative, negate
3263 insn = get_last_insn ();
3265 && (set = single_set (insn)) != 0
3266 && SET_DEST (set) == quotient
3267 && abs_d < ((unsigned HOST_WIDE_INT) 1
3268 << (HOST_BITS_PER_WIDE_INT - 1)))
3269 set_unique_reg_note (insn,
3271 gen_rtx_DIV (compute_mode,
3275 quotient = expand_unop (compute_mode, neg_optab,
3276 quotient, quotient, 0);
3279 else if (size <= HOST_BITS_PER_WIDE_INT)
3281 choose_multiplier (abs_d, size, size - 1,
3282 &ml, &post_shift, &lgup);
3283 if (ml < (unsigned HOST_WIDE_INT) 1 << (size - 1))
3287 extra_cost = (shift_cost[post_shift]
3288 + shift_cost[size - 1] + add_cost);
3289 t1 = expand_mult_highpart (compute_mode, op0, ml,
3291 max_cost - extra_cost);
3294 t2 = expand_shift (RSHIFT_EXPR, compute_mode, t1,
3295 build_int_2 (post_shift, 0), NULL_RTX, 0);
3296 t3 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3297 build_int_2 (size - 1, 0), NULL_RTX, 0);
3300 = force_operand (gen_rtx_MINUS (compute_mode,
3305 = force_operand (gen_rtx_MINUS (compute_mode,
3313 ml |= (~(unsigned HOST_WIDE_INT) 0) << (size - 1);
3314 extra_cost = (shift_cost[post_shift]
3315 + shift_cost[size - 1] + 2 * add_cost);
3316 t1 = expand_mult_highpart (compute_mode, op0, ml,
3318 max_cost - extra_cost);
3321 t2 = force_operand (gen_rtx_PLUS (compute_mode,
3324 t3 = expand_shift (RSHIFT_EXPR, compute_mode, t2,
3325 build_int_2 (post_shift, 0),
3327 t4 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3328 build_int_2 (size - 1, 0),
3332 = force_operand (gen_rtx_MINUS (compute_mode,
3337 = force_operand (gen_rtx_MINUS (compute_mode,
3342 else /* Too wide mode to use tricky code */
3345 insn = get_last_insn ();
3347 && (set = single_set (insn)) != 0
3348 && SET_DEST (set) == quotient)
3349 set_unique_reg_note (insn,
3351 gen_rtx_DIV (compute_mode, op0, op1));
3356 delete_insns_since (last);
3359 case FLOOR_DIV_EXPR:
3360 case FLOOR_MOD_EXPR:
3361 /* We will come here only for signed operations. */
3362 if (op1_is_constant && HOST_BITS_PER_WIDE_INT >= size)
3364 unsigned HOST_WIDE_INT mh, ml;
3365 int pre_shift, lgup, post_shift;
3366 HOST_WIDE_INT d = INTVAL (op1);
3370 /* We could just as easily deal with negative constants here,
3371 but it does not seem worth the trouble for GCC 2.6. */
3372 if (EXACT_POWER_OF_2_OR_ZERO_P (d))
3374 pre_shift = floor_log2 (d);
3377 remainder = expand_binop (compute_mode, and_optab, op0,
3378 GEN_INT (((HOST_WIDE_INT) 1 << pre_shift) - 1),
3379 remainder, 0, OPTAB_LIB_WIDEN);
3381 return gen_lowpart (mode, remainder);
3383 quotient = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3384 build_int_2 (pre_shift, 0),
3391 mh = choose_multiplier (d, size, size - 1,
3392 &ml, &post_shift, &lgup);
3396 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3397 build_int_2 (size - 1, 0), NULL_RTX, 0);
3398 t2 = expand_binop (compute_mode, xor_optab, op0, t1,
3399 NULL_RTX, 0, OPTAB_WIDEN);
3400 extra_cost = (shift_cost[post_shift]
3401 + shift_cost[size - 1] + 2 * add_cost);
3402 t3 = expand_mult_highpart (compute_mode, t2, ml,
3404 max_cost - extra_cost);
3407 t4 = expand_shift (RSHIFT_EXPR, compute_mode, t3,
3408 build_int_2 (post_shift, 0),
3410 quotient = expand_binop (compute_mode, xor_optab,
3411 t4, t1, tquotient, 0,
3418 rtx nsign, t1, t2, t3, t4;
3419 t1 = force_operand (gen_rtx_PLUS (compute_mode,
3420 op0, constm1_rtx), NULL_RTX);
3421 t2 = expand_binop (compute_mode, ior_optab, op0, t1, NULL_RTX,
3423 nsign = expand_shift (RSHIFT_EXPR, compute_mode, t2,
3424 build_int_2 (size - 1, 0), NULL_RTX, 0);
3425 t3 = force_operand (gen_rtx_MINUS (compute_mode, t1, nsign),
3427 t4 = expand_divmod (0, TRUNC_DIV_EXPR, compute_mode, t3, op1,
3432 t5 = expand_unop (compute_mode, one_cmpl_optab, nsign,
3434 quotient = force_operand (gen_rtx_PLUS (compute_mode,
3443 delete_insns_since (last);
3445 /* Try using an instruction that produces both the quotient and
3446 remainder, using truncation. We can easily compensate the quotient
3447 or remainder to get floor rounding, once we have the remainder.
3448 Notice that we compute also the final remainder value here,
3449 and return the result right away. */
3450 if (target == 0 || GET_MODE (target) != compute_mode)
3451 target = gen_reg_rtx (compute_mode);
3456 = GET_CODE (target) == REG ? target : gen_reg_rtx (compute_mode);
3457 quotient = gen_reg_rtx (compute_mode);
3462 = GET_CODE (target) == REG ? target : gen_reg_rtx (compute_mode);
3463 remainder = gen_reg_rtx (compute_mode);
3466 if (expand_twoval_binop (sdivmod_optab, op0, op1,
3467 quotient, remainder, 0))
3469 /* This could be computed with a branch-less sequence.
3470 Save that for later. */
3472 rtx label = gen_label_rtx ();
3473 do_cmp_and_jump (remainder, const0_rtx, EQ, compute_mode, label);
3474 tem = expand_binop (compute_mode, xor_optab, op0, op1,
3475 NULL_RTX, 0, OPTAB_WIDEN);
3476 do_cmp_and_jump (tem, const0_rtx, GE, compute_mode, label);
3477 expand_dec (quotient, const1_rtx);
3478 expand_inc (remainder, op1);
3480 return gen_lowpart (mode, rem_flag ? remainder : quotient);
3483 /* No luck with division elimination or divmod. Have to do it
3484 by conditionally adjusting op0 *and* the result. */
3486 rtx label1, label2, label3, label4, label5;
3490 quotient = gen_reg_rtx (compute_mode);
3491 adjusted_op0 = copy_to_mode_reg (compute_mode, op0);
3492 label1 = gen_label_rtx ();
3493 label2 = gen_label_rtx ();
3494 label3 = gen_label_rtx ();
3495 label4 = gen_label_rtx ();
3496 label5 = gen_label_rtx ();
3497 do_cmp_and_jump (op1, const0_rtx, LT, compute_mode, label2);
3498 do_cmp_and_jump (adjusted_op0, const0_rtx, LT, compute_mode, label1);
3499 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
3500 quotient, 0, OPTAB_LIB_WIDEN);
3501 if (tem != quotient)
3502 emit_move_insn (quotient, tem);
3503 emit_jump_insn (gen_jump (label5));
3505 emit_label (label1);
3506 expand_inc (adjusted_op0, const1_rtx);
3507 emit_jump_insn (gen_jump (label4));
3509 emit_label (label2);
3510 do_cmp_and_jump (adjusted_op0, const0_rtx, GT, compute_mode, label3);
3511 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
3512 quotient, 0, OPTAB_LIB_WIDEN);
3513 if (tem != quotient)
3514 emit_move_insn (quotient, tem);
3515 emit_jump_insn (gen_jump (label5));
3517 emit_label (label3);
3518 expand_dec (adjusted_op0, const1_rtx);
3519 emit_label (label4);
3520 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
3521 quotient, 0, OPTAB_LIB_WIDEN);
3522 if (tem != quotient)
3523 emit_move_insn (quotient, tem);
3524 expand_dec (quotient, const1_rtx);
3525 emit_label (label5);
3533 if (op1_is_constant && EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1)))
3536 unsigned HOST_WIDE_INT d = INTVAL (op1);
3537 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3538 build_int_2 (floor_log2 (d), 0),
3540 t2 = expand_binop (compute_mode, and_optab, op0,
3542 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3543 t3 = gen_reg_rtx (compute_mode);
3544 t3 = emit_store_flag (t3, NE, t2, const0_rtx,
3545 compute_mode, 1, 1);
3549 lab = gen_label_rtx ();
3550 do_cmp_and_jump (t2, const0_rtx, EQ, compute_mode, lab);
3551 expand_inc (t1, const1_rtx);
3556 quotient = force_operand (gen_rtx_PLUS (compute_mode,
3562 /* Try using an instruction that produces both the quotient and
3563 remainder, using truncation. We can easily compensate the
3564 quotient or remainder to get ceiling rounding, once we have the
3565 remainder. Notice that we compute also the final remainder
3566 value here, and return the result right away. */
3567 if (target == 0 || GET_MODE (target) != compute_mode)
3568 target = gen_reg_rtx (compute_mode);
3572 remainder = (GET_CODE (target) == REG
3573 ? target : gen_reg_rtx (compute_mode));
3574 quotient = gen_reg_rtx (compute_mode);
3578 quotient = (GET_CODE (target) == REG
3579 ? target : gen_reg_rtx (compute_mode));
3580 remainder = gen_reg_rtx (compute_mode);
3583 if (expand_twoval_binop (udivmod_optab, op0, op1, quotient,
3586 /* This could be computed with a branch-less sequence.
3587 Save that for later. */
3588 rtx label = gen_label_rtx ();
3589 do_cmp_and_jump (remainder, const0_rtx, EQ,
3590 compute_mode, label);
3591 expand_inc (quotient, const1_rtx);
3592 expand_dec (remainder, op1);
3594 return gen_lowpart (mode, rem_flag ? remainder : quotient);
3597 /* No luck with division elimination or divmod. Have to do it
3598 by conditionally adjusting op0 *and* the result. */
3601 rtx adjusted_op0, tem;
3603 quotient = gen_reg_rtx (compute_mode);
3604 adjusted_op0 = copy_to_mode_reg (compute_mode, op0);
3605 label1 = gen_label_rtx ();
3606 label2 = gen_label_rtx ();
3607 do_cmp_and_jump (adjusted_op0, const0_rtx, NE,
3608 compute_mode, label1);
3609 emit_move_insn (quotient, const0_rtx);
3610 emit_jump_insn (gen_jump (label2));
3612 emit_label (label1);
3613 expand_dec (adjusted_op0, const1_rtx);
3614 tem = expand_binop (compute_mode, udiv_optab, adjusted_op0, op1,
3615 quotient, 1, OPTAB_LIB_WIDEN);
3616 if (tem != quotient)
3617 emit_move_insn (quotient, tem);
3618 expand_inc (quotient, const1_rtx);
3619 emit_label (label2);
3624 if (op1_is_constant && EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1))
3625 && INTVAL (op1) >= 0)
3627 /* This is extremely similar to the code for the unsigned case
3628 above. For 2.7 we should merge these variants, but for
3629 2.6.1 I don't want to touch the code for unsigned since that
3630 get used in C. The signed case will only be used by other
3634 unsigned HOST_WIDE_INT d = INTVAL (op1);
3635 t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0,
3636 build_int_2 (floor_log2 (d), 0),
3638 t2 = expand_binop (compute_mode, and_optab, op0,
3640 NULL_RTX, 1, OPTAB_LIB_WIDEN);
3641 t3 = gen_reg_rtx (compute_mode);
3642 t3 = emit_store_flag (t3, NE, t2, const0_rtx,
3643 compute_mode, 1, 1);
3647 lab = gen_label_rtx ();
3648 do_cmp_and_jump (t2, const0_rtx, EQ, compute_mode, lab);
3649 expand_inc (t1, const1_rtx);
3654 quotient = force_operand (gen_rtx_PLUS (compute_mode,
3660 /* Try using an instruction that produces both the quotient and
3661 remainder, using truncation. We can easily compensate the
3662 quotient or remainder to get ceiling rounding, once we have the
3663 remainder. Notice that we compute also the final remainder
3664 value here, and return the result right away. */
3665 if (target == 0 || GET_MODE (target) != compute_mode)
3666 target = gen_reg_rtx (compute_mode);
3669 remainder= (GET_CODE (target) == REG
3670 ? target : gen_reg_rtx (compute_mode));
3671 quotient = gen_reg_rtx (compute_mode);
3675 quotient = (GET_CODE (target) == REG
3676 ? target : gen_reg_rtx (compute_mode));
3677 remainder = gen_reg_rtx (compute_mode);
3680 if (expand_twoval_binop (sdivmod_optab, op0, op1, quotient,
3683 /* This could be computed with a branch-less sequence.
3684 Save that for later. */
3686 rtx label = gen_label_rtx ();
3687 do_cmp_and_jump (remainder, const0_rtx, EQ,
3688 compute_mode, label);
3689 tem = expand_binop (compute_mode, xor_optab, op0, op1,
3690 NULL_RTX, 0, OPTAB_WIDEN);
3691 do_cmp_and_jump (tem, const0_rtx, LT, compute_mode, label);
3692 expand_inc (quotient, const1_rtx);
3693 expand_dec (remainder, op1);
3695 return gen_lowpart (mode, rem_flag ? remainder : quotient);
3698 /* No luck with division elimination or divmod. Have to do it
3699 by conditionally adjusting op0 *and* the result. */
3701 rtx label1, label2, label3, label4, label5;
3705 quotient = gen_reg_rtx (compute_mode);
3706 adjusted_op0 = copy_to_mode_reg (compute_mode, op0);
3707 label1 = gen_label_rtx ();
3708 label2 = gen_label_rtx ();
3709 label3 = gen_label_rtx ();
3710 label4 = gen_label_rtx ();
3711 label5 = gen_label_rtx ();
3712 do_cmp_and_jump (op1, const0_rtx, LT, compute_mode, label2);
3713 do_cmp_and_jump (adjusted_op0, const0_rtx, GT,
3714 compute_mode, label1);
3715 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
3716 quotient, 0, OPTAB_LIB_WIDEN);
3717 if (tem != quotient)
3718 emit_move_insn (quotient, tem);
3719 emit_jump_insn (gen_jump (label5));
3721 emit_label (label1);
3722 expand_dec (adjusted_op0, const1_rtx);
3723 emit_jump_insn (gen_jump (label4));
3725 emit_label (label2);
3726 do_cmp_and_jump (adjusted_op0, const0_rtx, LT,
3727 compute_mode, label3);
3728 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
3729 quotient, 0, OPTAB_LIB_WIDEN);
3730 if (tem != quotient)
3731 emit_move_insn (quotient, tem);
3732 emit_jump_insn (gen_jump (label5));
3734 emit_label (label3);
3735 expand_inc (adjusted_op0, const1_rtx);
3736 emit_label (label4);
3737 tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1,
3738 quotient, 0, OPTAB_LIB_WIDEN);
3739 if (tem != quotient)
3740 emit_move_insn (quotient, tem);
3741 expand_inc (quotient, const1_rtx);
3742 emit_label (label5);
3747 case EXACT_DIV_EXPR:
3748 if (op1_is_constant && HOST_BITS_PER_WIDE_INT >= size)
3750 HOST_WIDE_INT d = INTVAL (op1);
3751 unsigned HOST_WIDE_INT ml;
3755 post_shift = floor_log2 (d & -d);
3756 ml = invert_mod2n (d >> post_shift, size);
3757 t1 = expand_mult (compute_mode, op0, GEN_INT (ml), NULL_RTX,
3759 quotient = expand_shift (RSHIFT_EXPR, compute_mode, t1,
3760 build_int_2 (post_shift, 0),
3761 NULL_RTX, unsignedp);
3763 insn = get_last_insn ();
3764 set_unique_reg_note (insn,
3766 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
3772 case ROUND_DIV_EXPR:
3773 case ROUND_MOD_EXPR:
3778 label = gen_label_rtx ();
3779 quotient = gen_reg_rtx (compute_mode);
3780 remainder = gen_reg_rtx (compute_mode);
3781 if (expand_twoval_binop (udivmod_optab, op0, op1, quotient, remainder, 1) == 0)
3784 quotient = expand_binop (compute_mode, udiv_optab, op0, op1,
3785 quotient, 1, OPTAB_LIB_WIDEN);
3786 tem = expand_mult (compute_mode, quotient, op1, NULL_RTX, 1);
3787 remainder = expand_binop (compute_mode, sub_optab, op0, tem,
3788 remainder, 1, OPTAB_LIB_WIDEN);
3790 tem = plus_constant (op1, -1);
3791 tem = expand_shift (RSHIFT_EXPR, compute_mode, tem,
3792 build_int_2 (1, 0), NULL_RTX, 1);
3793 do_cmp_and_jump (remainder, tem, LEU, compute_mode, label);
3794 expand_inc (quotient, const1_rtx);
3795 expand_dec (remainder, op1);
3800 rtx abs_rem, abs_op1, tem, mask;
3802 label = gen_label_rtx ();
3803 quotient = gen_reg_rtx (compute_mode);
3804 remainder = gen_reg_rtx (compute_mode);
3805 if (expand_twoval_binop (sdivmod_optab, op0, op1, quotient, remainder, 0) == 0)
3808 quotient = expand_binop (compute_mode, sdiv_optab, op0, op1,
3809 quotient, 0, OPTAB_LIB_WIDEN);
3810 tem = expand_mult (compute_mode, quotient, op1, NULL_RTX, 0);
3811 remainder = expand_binop (compute_mode, sub_optab, op0, tem,
3812 remainder, 0, OPTAB_LIB_WIDEN);
3814 abs_rem = expand_abs (compute_mode, remainder, NULL_RTX, 0);
3815 abs_op1 = expand_abs (compute_mode, op1, NULL_RTX, 0);
3816 tem = expand_shift (LSHIFT_EXPR, compute_mode, abs_rem,
3817 build_int_2 (1, 0), NULL_RTX, 1);
3818 do_cmp_and_jump (tem, abs_op1, LTU, compute_mode, label);
3819 tem = expand_binop (compute_mode, xor_optab, op0, op1,
3820 NULL_RTX, 0, OPTAB_WIDEN);
3821 mask = expand_shift (RSHIFT_EXPR, compute_mode, tem,
3822 build_int_2 (size - 1, 0), NULL_RTX, 0);
3823 tem = expand_binop (compute_mode, xor_optab, mask, const1_rtx,
3824 NULL_RTX, 0, OPTAB_WIDEN);
3825 tem = expand_binop (compute_mode, sub_optab, tem, mask,
3826 NULL_RTX, 0, OPTAB_WIDEN);
3827 expand_inc (quotient, tem);
3828 tem = expand_binop (compute_mode, xor_optab, mask, op1,
3829 NULL_RTX, 0, OPTAB_WIDEN);
3830 tem = expand_binop (compute_mode, sub_optab, tem, mask,
3831 NULL_RTX, 0, OPTAB_WIDEN);
3832 expand_dec (remainder, tem);
3835 return gen_lowpart (mode, rem_flag ? remainder : quotient);
3843 if (target && GET_MODE (target) != compute_mode)
3848 /* Try to produce the remainder without producing the quotient.
3849 If we seem to have a divmod patten that does not require widening,
3850 don't try windening here. We should really have an WIDEN argument
3851 to expand_twoval_binop, since what we'd really like to do here is
3852 1) try a mod insn in compute_mode
3853 2) try a divmod insn in compute_mode
3854 3) try a div insn in compute_mode and multiply-subtract to get
3856 4) try the same things with widening allowed. */
3858 = sign_expand_binop (compute_mode, umod_optab, smod_optab,
3861 ((optab2->handlers[(int) compute_mode].insn_code
3862 != CODE_FOR_nothing)
3863 ? OPTAB_DIRECT : OPTAB_WIDEN));
3866 /* No luck there. Can we do remainder and divide at once
3867 without a library call? */
3868 remainder = gen_reg_rtx (compute_mode);
3869 if (! expand_twoval_binop ((unsignedp
3873 NULL_RTX, remainder, unsignedp))
3878 return gen_lowpart (mode, remainder);
3881 /* Produce the quotient. Try a quotient insn, but not a library call.
3882 If we have a divmod in this mode, use it in preference to widening
3883 the div (for this test we assume it will not fail). Note that optab2
3884 is set to the one of the two optabs that the call below will use. */
3886 = sign_expand_binop (compute_mode, udiv_optab, sdiv_optab,
3887 op0, op1, rem_flag ? NULL_RTX : target,
3889 ((optab2->handlers[(int) compute_mode].insn_code
3890 != CODE_FOR_nothing)
3891 ? OPTAB_DIRECT : OPTAB_WIDEN));
3895 /* No luck there. Try a quotient-and-remainder insn,
3896 keeping the quotient alone. */
3897 quotient = gen_reg_rtx (compute_mode);
3898 if (! expand_twoval_binop (unsignedp ? udivmod_optab : sdivmod_optab,
3900 quotient, NULL_RTX, unsignedp))
3904 /* Still no luck. If we are not computing the remainder,
3905 use a library call for the quotient. */
3906 quotient = sign_expand_binop (compute_mode,
3907 udiv_optab, sdiv_optab,
3909 unsignedp, OPTAB_LIB_WIDEN);
3916 if (target && GET_MODE (target) != compute_mode)
3920 /* No divide instruction either. Use library for remainder. */
3921 remainder = sign_expand_binop (compute_mode, umod_optab, smod_optab,
3923 unsignedp, OPTAB_LIB_WIDEN);
3926 /* We divided. Now finish doing X - Y * (X / Y). */
3927 remainder = expand_mult (compute_mode, quotient, op1,
3928 NULL_RTX, unsignedp);
3929 remainder = expand_binop (compute_mode, sub_optab, op0,
3930 remainder, target, unsignedp,
3935 return gen_lowpart (mode, rem_flag ? remainder : quotient);
3938 /* Return a tree node with data type TYPE, describing the value of X.
3939 Usually this is an RTL_EXPR, if there is no obvious better choice.
3940 X may be an expression, however we only support those expressions
3941 generated by loop.c. */
3950 switch (GET_CODE (x))
3953 t = build_int_2 (INTVAL (x),
3954 (TREE_UNSIGNED (type)
3955 && (GET_MODE_BITSIZE (TYPE_MODE (type)) < HOST_BITS_PER_WIDE_INT))
3956 || INTVAL (x) >= 0 ? 0 : -1);
3957 TREE_TYPE (t) = type;
3961 if (GET_MODE (x) == VOIDmode)
3963 t = build_int_2 (CONST_DOUBLE_LOW (x), CONST_DOUBLE_HIGH (x));
3964 TREE_TYPE (t) = type;
3970 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
3971 t = build_real (type, d);
3977 return fold (build (PLUS_EXPR, type, make_tree (type, XEXP (x, 0)),
3978 make_tree (type, XEXP (x, 1))));
3981 return fold (build (MINUS_EXPR, type, make_tree (type, XEXP (x, 0)),
3982 make_tree (type, XEXP (x, 1))));
3985 return fold (build1 (NEGATE_EXPR, type, make_tree (type, XEXP (x, 0))));
3988 return fold (build (MULT_EXPR, type, make_tree (type, XEXP (x, 0)),
3989 make_tree (type, XEXP (x, 1))));
3992 return fold (build (LSHIFT_EXPR, type, make_tree (type, XEXP (x, 0)),
3993 make_tree (type, XEXP (x, 1))));
3996 return fold (convert (type,
3997 build (RSHIFT_EXPR, unsigned_type (type),
3998 make_tree (unsigned_type (type),
4000 make_tree (type, XEXP (x, 1)))));
4003 return fold (convert (type,
4004 build (RSHIFT_EXPR, signed_type (type),
4005 make_tree (signed_type (type), XEXP (x, 0)),
4006 make_tree (type, XEXP (x, 1)))));
4009 if (TREE_CODE (type) != REAL_TYPE)
4010 t = signed_type (type);
4014 return fold (convert (type,
4015 build (TRUNC_DIV_EXPR, t,
4016 make_tree (t, XEXP (x, 0)),
4017 make_tree (t, XEXP (x, 1)))));
4019 t = unsigned_type (type);
4020 return fold (convert (type,
4021 build (TRUNC_DIV_EXPR, t,
4022 make_tree (t, XEXP (x, 0)),
4023 make_tree (t, XEXP (x, 1)))));
4025 t = make_node (RTL_EXPR);
4026 TREE_TYPE (t) = type;
4027 RTL_EXPR_RTL (t) = x;
4028 /* There are no insns to be output
4029 when this rtl_expr is used. */
4030 RTL_EXPR_SEQUENCE (t) = 0;
4035 /* Return an rtx representing the value of X * MULT + ADD.
4036 TARGET is a suggestion for where to store the result (an rtx).
4037 MODE is the machine mode for the computation.
4038 X and MULT must have mode MODE. ADD may have a different mode.
4039 So can X (defaults to same as MODE).
4040 UNSIGNEDP is non-zero to do unsigned multiplication.
4041 This may emit insns. */
4044 expand_mult_add (x, target, mult, add, mode, unsignedp)
4045 rtx x, target, mult, add;
4046 enum machine_mode mode;
4049 tree type = type_for_mode (mode, unsignedp);
4050 tree add_type = (GET_MODE (add) == VOIDmode
4051 ? type : type_for_mode (GET_MODE (add), unsignedp));
4052 tree result = fold (build (PLUS_EXPR, type,
4053 fold (build (MULT_EXPR, type,
4054 make_tree (type, x),
4055 make_tree (type, mult))),
4056 make_tree (add_type, add)));
4058 return expand_expr (result, target, VOIDmode, 0);
4061 /* Compute the logical-and of OP0 and OP1, storing it in TARGET
4062 and returning TARGET.
4064 If TARGET is 0, a pseudo-register or constant is returned. */
4067 expand_and (op0, op1, target)
4068 rtx op0, op1, target;
4070 enum machine_mode mode = VOIDmode;
4073 if (GET_MODE (op0) != VOIDmode)
4074 mode = GET_MODE (op0);
4075 else if (GET_MODE (op1) != VOIDmode)
4076 mode = GET_MODE (op1);
4078 if (mode != VOIDmode)
4079 tem = expand_binop (mode, and_optab, op0, op1, target, 0, OPTAB_LIB_WIDEN);
4080 else if (GET_CODE (op0) == CONST_INT && GET_CODE (op1) == CONST_INT)
4081 tem = GEN_INT (INTVAL (op0) & INTVAL (op1));
4087 else if (tem != target)
4088 emit_move_insn (target, tem);
4092 /* Emit a store-flags instruction for comparison CODE on OP0 and OP1
4093 and storing in TARGET. Normally return TARGET.
4094 Return 0 if that cannot be done.
4096 MODE is the mode to use for OP0 and OP1 should they be CONST_INTs. If
4097 it is VOIDmode, they cannot both be CONST_INT.
4099 UNSIGNEDP is for the case where we have to widen the operands
4100 to perform the operation. It says to use zero-extension.
4102 NORMALIZEP is 1 if we should convert the result to be either zero
4103 or one. Normalize is -1 if we should convert the result to be
4104 either zero or -1. If NORMALIZEP is zero, the result will be left
4105 "raw" out of the scc insn. */
4108 emit_store_flag (target, code, op0, op1, mode, unsignedp, normalizep)
4112 enum machine_mode mode;
4117 enum insn_code icode;
4118 enum machine_mode compare_mode;
4119 enum machine_mode target_mode = GET_MODE (target);
4121 rtx last = get_last_insn ();
4122 rtx pattern, comparison;
4125 code = unsigned_condition (code);
4127 /* If one operand is constant, make it the second one. Only do this
4128 if the other operand is not constant as well. */
4130 if ((CONSTANT_P (op0) && ! CONSTANT_P (op1))
4131 || (GET_CODE (op0) == CONST_INT && GET_CODE (op1) != CONST_INT))
4136 code = swap_condition (code);
4139 if (mode == VOIDmode)
4140 mode = GET_MODE (op0);
4142 /* For some comparisons with 1 and -1, we can convert this to
4143 comparisons with zero. This will often produce more opportunities for
4144 store-flag insns. */
4149 if (op1 == const1_rtx)
4150 op1 = const0_rtx, code = LE;
4153 if (op1 == constm1_rtx)
4154 op1 = const0_rtx, code = LT;
4157 if (op1 == const1_rtx)
4158 op1 = const0_rtx, code = GT;
4161 if (op1 == constm1_rtx)
4162 op1 = const0_rtx, code = GE;
4165 if (op1 == const1_rtx)
4166 op1 = const0_rtx, code = NE;
4169 if (op1 == const1_rtx)
4170 op1 = const0_rtx, code = EQ;
4176 /* From now on, we won't change CODE, so set ICODE now. */
4177 icode = setcc_gen_code[(int) code];
4179 /* If this is A < 0 or A >= 0, we can do this by taking the ones
4180 complement of A (for GE) and shifting the sign bit to the low bit. */
4181 if (op1 == const0_rtx && (code == LT || code == GE)
4182 && GET_MODE_CLASS (mode) == MODE_INT
4183 && (normalizep || STORE_FLAG_VALUE == 1
4184 || (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4185 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4186 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1)))))
4190 /* If the result is to be wider than OP0, it is best to convert it
4191 first. If it is to be narrower, it is *incorrect* to convert it
4193 if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (mode))
4195 op0 = protect_from_queue (op0, 0);
4196 op0 = convert_modes (target_mode, mode, op0, 0);
4200 if (target_mode != mode)
4204 op0 = expand_unop (mode, one_cmpl_optab, op0,
4205 ((STORE_FLAG_VALUE == 1 || normalizep)
4206 ? 0 : subtarget), 0);
4208 if (STORE_FLAG_VALUE == 1 || normalizep)
4209 /* If we are supposed to produce a 0/1 value, we want to do
4210 a logical shift from the sign bit to the low-order bit; for
4211 a -1/0 value, we do an arithmetic shift. */
4212 op0 = expand_shift (RSHIFT_EXPR, mode, op0,
4213 size_int (GET_MODE_BITSIZE (mode) - 1),
4214 subtarget, normalizep != -1);
4216 if (mode != target_mode)
4217 op0 = convert_modes (target_mode, mode, op0, 0);
4222 if (icode != CODE_FOR_nothing)
4224 insn_operand_predicate_fn pred;
4226 /* We think we may be able to do this with a scc insn. Emit the
4227 comparison and then the scc insn.
4229 compare_from_rtx may call emit_queue, which would be deleted below
4230 if the scc insn fails. So call it ourselves before setting LAST.
4231 Likewise for do_pending_stack_adjust. */
4234 do_pending_stack_adjust ();
4235 last = get_last_insn ();
4238 = compare_from_rtx (op0, op1, code, unsignedp, mode, NULL_RTX, 0);
4239 if (GET_CODE (comparison) == CONST_INT)
4240 return (comparison == const0_rtx ? const0_rtx
4241 : normalizep == 1 ? const1_rtx
4242 : normalizep == -1 ? constm1_rtx
4245 /* If the code of COMPARISON doesn't match CODE, something is
4246 wrong; we can no longer be sure that we have the operation.
4247 We could handle this case, but it should not happen. */
4249 if (GET_CODE (comparison) != code)
4252 /* Get a reference to the target in the proper mode for this insn. */
4253 compare_mode = insn_data[(int) icode].operand[0].mode;
4255 pred = insn_data[(int) icode].operand[0].predicate;
4256 if (preserve_subexpressions_p ()
4257 || ! (*pred) (subtarget, compare_mode))
4258 subtarget = gen_reg_rtx (compare_mode);
4260 pattern = GEN_FCN (icode) (subtarget);
4263 emit_insn (pattern);
4265 /* If we are converting to a wider mode, first convert to
4266 TARGET_MODE, then normalize. This produces better combining
4267 opportunities on machines that have a SIGN_EXTRACT when we are
4268 testing a single bit. This mostly benefits the 68k.
4270 If STORE_FLAG_VALUE does not have the sign bit set when
4271 interpreted in COMPARE_MODE, we can do this conversion as
4272 unsigned, which is usually more efficient. */
4273 if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (compare_mode))
4275 convert_move (target, subtarget,
4276 (GET_MODE_BITSIZE (compare_mode)
4277 <= HOST_BITS_PER_WIDE_INT)
4278 && 0 == (STORE_FLAG_VALUE
4279 & ((HOST_WIDE_INT) 1
4280 << (GET_MODE_BITSIZE (compare_mode) -1))));
4282 compare_mode = target_mode;
4287 /* If we want to keep subexpressions around, don't reuse our
4290 if (preserve_subexpressions_p ())
4293 /* Now normalize to the proper value in COMPARE_MODE. Sometimes
4294 we don't have to do anything. */
4295 if (normalizep == 0 || normalizep == STORE_FLAG_VALUE)
4297 /* STORE_FLAG_VALUE might be the most negative number, so write
4298 the comparison this way to avoid a compiler-time warning. */
4299 else if (- normalizep == STORE_FLAG_VALUE)
4300 op0 = expand_unop (compare_mode, neg_optab, op0, subtarget, 0);
4302 /* We don't want to use STORE_FLAG_VALUE < 0 below since this
4303 makes it hard to use a value of just the sign bit due to
4304 ANSI integer constant typing rules. */
4305 else if (GET_MODE_BITSIZE (compare_mode) <= HOST_BITS_PER_WIDE_INT
4306 && (STORE_FLAG_VALUE
4307 & ((HOST_WIDE_INT) 1
4308 << (GET_MODE_BITSIZE (compare_mode) - 1))))
4309 op0 = expand_shift (RSHIFT_EXPR, compare_mode, op0,
4310 size_int (GET_MODE_BITSIZE (compare_mode) - 1),
4311 subtarget, normalizep == 1);
4312 else if (STORE_FLAG_VALUE & 1)
4314 op0 = expand_and (op0, const1_rtx, subtarget);
4315 if (normalizep == -1)
4316 op0 = expand_unop (compare_mode, neg_optab, op0, op0, 0);
4321 /* If we were converting to a smaller mode, do the
4323 if (target_mode != compare_mode)
4325 convert_move (target, op0, 0);
4333 delete_insns_since (last);
4335 /* If expensive optimizations, use different pseudo registers for each
4336 insn, instead of reusing the same pseudo. This leads to better CSE,
4337 but slows down the compiler, since there are more pseudos */
4338 subtarget = (!flag_expensive_optimizations
4339 && (target_mode == mode)) ? target : NULL_RTX;
4341 /* If we reached here, we can't do this with a scc insn. However, there
4342 are some comparisons that can be done directly. For example, if
4343 this is an equality comparison of integers, we can try to exclusive-or
4344 (or subtract) the two operands and use a recursive call to try the
4345 comparison with zero. Don't do any of these cases if branches are
4349 && GET_MODE_CLASS (mode) == MODE_INT && (code == EQ || code == NE)
4350 && op1 != const0_rtx)
4352 tem = expand_binop (mode, xor_optab, op0, op1, subtarget, 1,
4356 tem = expand_binop (mode, sub_optab, op0, op1, subtarget, 1,
4359 tem = emit_store_flag (target, code, tem, const0_rtx,
4360 mode, unsignedp, normalizep);
4362 delete_insns_since (last);
4366 /* Some other cases we can do are EQ, NE, LE, and GT comparisons with
4367 the constant zero. Reject all other comparisons at this point. Only
4368 do LE and GT if branches are expensive since they are expensive on
4369 2-operand machines. */
4371 if (BRANCH_COST == 0
4372 || GET_MODE_CLASS (mode) != MODE_INT || op1 != const0_rtx
4373 || (code != EQ && code != NE
4374 && (BRANCH_COST <= 1 || (code != LE && code != GT))))
4377 /* See what we need to return. We can only return a 1, -1, or the
4380 if (normalizep == 0)
4382 if (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4383 normalizep = STORE_FLAG_VALUE;
4385 else if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4386 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4387 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1)))
4393 /* Try to put the result of the comparison in the sign bit. Assume we can't
4394 do the necessary operation below. */
4398 /* To see if A <= 0, compute (A | (A - 1)). A <= 0 iff that result has
4399 the sign bit set. */
4403 /* This is destructive, so SUBTARGET can't be OP0. */
4404 if (rtx_equal_p (subtarget, op0))
4407 tem = expand_binop (mode, sub_optab, op0, const1_rtx, subtarget, 0,
4410 tem = expand_binop (mode, ior_optab, op0, tem, subtarget, 0,
4414 /* To see if A > 0, compute (((signed) A) << BITS) - A, where BITS is the
4415 number of bits in the mode of OP0, minus one. */
4419 if (rtx_equal_p (subtarget, op0))
4422 tem = expand_shift (RSHIFT_EXPR, mode, op0,
4423 size_int (GET_MODE_BITSIZE (mode) - 1),
4425 tem = expand_binop (mode, sub_optab, tem, op0, subtarget, 0,
4429 if (code == EQ || code == NE)
4431 /* For EQ or NE, one way to do the comparison is to apply an operation
4432 that converts the operand into a positive number if it is non-zero
4433 or zero if it was originally zero. Then, for EQ, we subtract 1 and
4434 for NE we negate. This puts the result in the sign bit. Then we
4435 normalize with a shift, if needed.
4437 Two operations that can do the above actions are ABS and FFS, so try
4438 them. If that doesn't work, and MODE is smaller than a full word,
4439 we can use zero-extension to the wider mode (an unsigned conversion)
4440 as the operation. */
4442 if (abs_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
4443 tem = expand_unop (mode, abs_optab, op0, subtarget, 1);
4444 else if (ffs_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
4445 tem = expand_unop (mode, ffs_optab, op0, subtarget, 1);
4446 else if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
4448 op0 = protect_from_queue (op0, 0);
4449 tem = convert_modes (word_mode, mode, op0, 1);
4456 tem = expand_binop (mode, sub_optab, tem, const1_rtx, subtarget,
4459 tem = expand_unop (mode, neg_optab, tem, subtarget, 0);
4462 /* If we couldn't do it that way, for NE we can "or" the two's complement
4463 of the value with itself. For EQ, we take the one's complement of
4464 that "or", which is an extra insn, so we only handle EQ if branches
4467 if (tem == 0 && (code == NE || BRANCH_COST > 1))
4469 if (rtx_equal_p (subtarget, op0))
4472 tem = expand_unop (mode, neg_optab, op0, subtarget, 0);
4473 tem = expand_binop (mode, ior_optab, tem, op0, subtarget, 0,
4476 if (tem && code == EQ)
4477 tem = expand_unop (mode, one_cmpl_optab, tem, subtarget, 0);
4481 if (tem && normalizep)
4482 tem = expand_shift (RSHIFT_EXPR, mode, tem,
4483 size_int (GET_MODE_BITSIZE (mode) - 1),
4484 subtarget, normalizep == 1);
4488 if (GET_MODE (tem) != target_mode)
4490 convert_move (target, tem, 0);
4493 else if (!subtarget)
4495 emit_move_insn (target, tem);
4500 delete_insns_since (last);
4505 /* Like emit_store_flag, but always succeeds. */
4508 emit_store_flag_force (target, code, op0, op1, mode, unsignedp, normalizep)
4512 enum machine_mode mode;
4518 /* First see if emit_store_flag can do the job. */
4519 tem = emit_store_flag (target, code, op0, op1, mode, unsignedp, normalizep);
4523 if (normalizep == 0)
4526 /* If this failed, we have to do this with set/compare/jump/set code. */
4528 if (GET_CODE (target) != REG
4529 || reg_mentioned_p (target, op0) || reg_mentioned_p (target, op1))
4530 target = gen_reg_rtx (GET_MODE (target));
4532 emit_move_insn (target, const1_rtx);
4533 label = gen_label_rtx ();
4534 do_compare_rtx_and_jump (op0, op1, code, unsignedp, mode, NULL_RTX, 0,
4537 emit_move_insn (target, const0_rtx);
4543 /* Perform possibly multi-word comparison and conditional jump to LABEL
4544 if ARG1 OP ARG2 true where ARG1 and ARG2 are of mode MODE
4546 The algorithm is based on the code in expr.c:do_jump.
4548 Note that this does not perform a general comparison. Only variants
4549 generated within expmed.c are correctly handled, others abort (but could
4550 be handled if needed). */
4553 do_cmp_and_jump (arg1, arg2, op, mode, label)
4554 rtx arg1, arg2, label;
4556 enum machine_mode mode;
4558 /* If this mode is an integer too wide to compare properly,
4559 compare word by word. Rely on cse to optimize constant cases. */
4561 if (GET_MODE_CLASS (mode) == MODE_INT && ! can_compare_p (mode, ccp_jump))
4563 rtx label2 = gen_label_rtx ();
4568 do_jump_by_parts_greater_rtx (mode, 1, arg2, arg1, label2, label);
4572 do_jump_by_parts_greater_rtx (mode, 1, arg1, arg2, label, label2);
4576 do_jump_by_parts_greater_rtx (mode, 0, arg2, arg1, label2, label);
4580 do_jump_by_parts_greater_rtx (mode, 0, arg1, arg2, label2, label);
4584 do_jump_by_parts_greater_rtx (mode, 0, arg2, arg1, label, label2);
4587 /* do_jump_by_parts_equality_rtx compares with zero. Luckily
4588 that's the only equality operations we do */
4590 if (arg2 != const0_rtx || mode != GET_MODE(arg1))
4592 do_jump_by_parts_equality_rtx (arg1, label2, label);
4596 if (arg2 != const0_rtx || mode != GET_MODE(arg1))
4598 do_jump_by_parts_equality_rtx (arg1, label, label2);
4605 emit_label (label2);
4609 emit_cmp_and_jump_insns (arg1, arg2, op, NULL_RTX, mode, 0, 0, label);