1 /* Emit RTL for the GCC expander.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
23 /* Middle-to-low level generation of rtx code and insns.
25 This file contains support functions for creating rtl expressions
26 and manipulating them in the doubly-linked chain of insns.
28 The patterns of the insns are created by machine-dependent
29 routines in insn-emit.c, which is generated automatically from
30 the machine description. These routines make the individual rtx's
31 of the pattern with `gen_rtx_fmt_ee' and others in genrtl.[ch],
32 which are automatically generated from rtl.def; what is machine
33 dependent is the kind of rtx's they make and what arguments they
38 #include "coretypes.h"
48 #include "hard-reg-set.h"
50 #include "insn-config.h"
54 #include "basic-block.h"
57 #include "langhooks.h"
58 #include "tree-pass.h"
61 /* Commonly used modes. */
63 enum machine_mode byte_mode; /* Mode whose width is BITS_PER_UNIT. */
64 enum machine_mode word_mode; /* Mode whose width is BITS_PER_WORD. */
65 enum machine_mode double_mode; /* Mode whose width is DOUBLE_TYPE_SIZE. */
66 enum machine_mode ptr_mode; /* Mode whose width is POINTER_SIZE. */
69 /* This is *not* reset after each function. It gives each CODE_LABEL
70 in the entire compilation a unique label number. */
72 static GTY(()) int label_num = 1;
74 /* Nonzero means do not generate NOTEs for source line numbers. */
76 static int no_line_numbers;
78 /* Commonly used rtx's, so that we only need space for one copy.
79 These are initialized once for the entire compilation.
80 All of these are unique; no other rtx-object will be equal to any
83 rtx global_rtl[GR_MAX];
85 /* Commonly used RTL for hard registers. These objects are not necessarily
86 unique, so we allocate them separately from global_rtl. They are
87 initialized once per compilation unit, then copied into regno_reg_rtx
88 at the beginning of each function. */
89 static GTY(()) rtx static_regno_reg_rtx[FIRST_PSEUDO_REGISTER];
91 /* We record floating-point CONST_DOUBLEs in each floating-point mode for
92 the values of 0, 1, and 2. For the integer entries and VOIDmode, we
93 record a copy of const[012]_rtx. */
95 rtx const_tiny_rtx[3][(int) MAX_MACHINE_MODE];
99 REAL_VALUE_TYPE dconst0;
100 REAL_VALUE_TYPE dconst1;
101 REAL_VALUE_TYPE dconst2;
102 REAL_VALUE_TYPE dconst3;
103 REAL_VALUE_TYPE dconst10;
104 REAL_VALUE_TYPE dconstm1;
105 REAL_VALUE_TYPE dconstm2;
106 REAL_VALUE_TYPE dconsthalf;
107 REAL_VALUE_TYPE dconstthird;
108 REAL_VALUE_TYPE dconstsqrt2;
109 REAL_VALUE_TYPE dconste;
111 /* All references to the following fixed hard registers go through
112 these unique rtl objects. On machines where the frame-pointer and
113 arg-pointer are the same register, they use the same unique object.
115 After register allocation, other rtl objects which used to be pseudo-regs
116 may be clobbered to refer to the frame-pointer register.
117 But references that were originally to the frame-pointer can be
118 distinguished from the others because they contain frame_pointer_rtx.
120 When to use frame_pointer_rtx and hard_frame_pointer_rtx is a little
121 tricky: until register elimination has taken place hard_frame_pointer_rtx
122 should be used if it is being set, and frame_pointer_rtx otherwise. After
123 register elimination hard_frame_pointer_rtx should always be used.
124 On machines where the two registers are same (most) then these are the
127 In an inline procedure, the stack and frame pointer rtxs may not be
128 used for anything else. */
129 rtx static_chain_rtx; /* (REG:Pmode STATIC_CHAIN_REGNUM) */
130 rtx static_chain_incoming_rtx; /* (REG:Pmode STATIC_CHAIN_INCOMING_REGNUM) */
131 rtx pic_offset_table_rtx; /* (REG:Pmode PIC_OFFSET_TABLE_REGNUM) */
133 /* This is used to implement __builtin_return_address for some machines.
134 See for instance the MIPS port. */
135 rtx return_address_pointer_rtx; /* (REG:Pmode RETURN_ADDRESS_POINTER_REGNUM) */
137 /* We make one copy of (const_int C) where C is in
138 [- MAX_SAVED_CONST_INT, MAX_SAVED_CONST_INT]
139 to save space during the compilation and simplify comparisons of
142 rtx const_int_rtx[MAX_SAVED_CONST_INT * 2 + 1];
144 /* A hash table storing CONST_INTs whose absolute value is greater
145 than MAX_SAVED_CONST_INT. */
147 static GTY ((if_marked ("ggc_marked_p"), param_is (struct rtx_def)))
148 htab_t const_int_htab;
150 /* A hash table storing memory attribute structures. */
151 static GTY ((if_marked ("ggc_marked_p"), param_is (struct mem_attrs)))
152 htab_t mem_attrs_htab;
154 /* A hash table storing register attribute structures. */
155 static GTY ((if_marked ("ggc_marked_p"), param_is (struct reg_attrs)))
156 htab_t reg_attrs_htab;
158 /* A hash table storing all CONST_DOUBLEs. */
159 static GTY ((if_marked ("ggc_marked_p"), param_is (struct rtx_def)))
160 htab_t const_double_htab;
162 #define first_insn (cfun->emit->x_first_insn)
163 #define last_insn (cfun->emit->x_last_insn)
164 #define cur_insn_uid (cfun->emit->x_cur_insn_uid)
165 #define last_location (cfun->emit->x_last_location)
166 #define first_label_num (cfun->emit->x_first_label_num)
168 static rtx make_call_insn_raw (rtx);
169 static rtx change_address_1 (rtx, enum machine_mode, rtx, int);
170 static void reset_used_decls (tree);
171 static void mark_label_nuses (rtx);
172 static hashval_t const_int_htab_hash (const void *);
173 static int const_int_htab_eq (const void *, const void *);
174 static hashval_t const_double_htab_hash (const void *);
175 static int const_double_htab_eq (const void *, const void *);
176 static rtx lookup_const_double (rtx);
177 static hashval_t mem_attrs_htab_hash (const void *);
178 static int mem_attrs_htab_eq (const void *, const void *);
179 static mem_attrs *get_mem_attrs (HOST_WIDE_INT, tree, rtx, rtx, unsigned int,
181 static hashval_t reg_attrs_htab_hash (const void *);
182 static int reg_attrs_htab_eq (const void *, const void *);
183 static reg_attrs *get_reg_attrs (tree, int);
184 static tree component_ref_for_mem_expr (tree);
185 static rtx gen_const_vector (enum machine_mode, int);
186 static void copy_rtx_if_shared_1 (rtx *orig);
188 /* Probability of the conditional branch currently proceeded by try_split.
189 Set to -1 otherwise. */
190 int split_branch_probability = -1;
192 /* Returns a hash code for X (which is a really a CONST_INT). */
195 const_int_htab_hash (const void *x)
197 return (hashval_t) INTVAL ((const_rtx) x);
200 /* Returns nonzero if the value represented by X (which is really a
201 CONST_INT) is the same as that given by Y (which is really a
205 const_int_htab_eq (const void *x, const void *y)
207 return (INTVAL ((const_rtx) x) == *((const HOST_WIDE_INT *) y));
210 /* Returns a hash code for X (which is really a CONST_DOUBLE). */
212 const_double_htab_hash (const void *x)
214 const_rtx const value = (const_rtx) x;
217 if (GET_MODE (value) == VOIDmode)
218 h = CONST_DOUBLE_LOW (value) ^ CONST_DOUBLE_HIGH (value);
221 h = real_hash (CONST_DOUBLE_REAL_VALUE (value));
222 /* MODE is used in the comparison, so it should be in the hash. */
223 h ^= GET_MODE (value);
228 /* Returns nonzero if the value represented by X (really a ...)
229 is the same as that represented by Y (really a ...) */
231 const_double_htab_eq (const void *x, const void *y)
233 const_rtx const a = (const_rtx)x, b = (const_rtx)y;
235 if (GET_MODE (a) != GET_MODE (b))
237 if (GET_MODE (a) == VOIDmode)
238 return (CONST_DOUBLE_LOW (a) == CONST_DOUBLE_LOW (b)
239 && CONST_DOUBLE_HIGH (a) == CONST_DOUBLE_HIGH (b));
241 return real_identical (CONST_DOUBLE_REAL_VALUE (a),
242 CONST_DOUBLE_REAL_VALUE (b));
245 /* Returns a hash code for X (which is a really a mem_attrs *). */
248 mem_attrs_htab_hash (const void *x)
250 const mem_attrs *const p = (const mem_attrs *) x;
252 return (p->alias ^ (p->align * 1000)
253 ^ ((p->offset ? INTVAL (p->offset) : 0) * 50000)
254 ^ ((p->size ? INTVAL (p->size) : 0) * 2500000)
255 ^ (size_t) iterative_hash_expr (p->expr, 0));
258 /* Returns nonzero if the value represented by X (which is really a
259 mem_attrs *) is the same as that given by Y (which is also really a
263 mem_attrs_htab_eq (const void *x, const void *y)
265 const mem_attrs *const p = (const mem_attrs *) x;
266 const mem_attrs *const q = (const mem_attrs *) y;
268 return (p->alias == q->alias && p->offset == q->offset
269 && p->size == q->size && p->align == q->align
270 && (p->expr == q->expr
271 || (p->expr != NULL_TREE && q->expr != NULL_TREE
272 && operand_equal_p (p->expr, q->expr, 0))));
275 /* Allocate a new mem_attrs structure and insert it into the hash table if
276 one identical to it is not already in the table. We are doing this for
280 get_mem_attrs (HOST_WIDE_INT alias, tree expr, rtx offset, rtx size,
281 unsigned int align, enum machine_mode mode)
286 /* If everything is the default, we can just return zero.
287 This must match what the corresponding MEM_* macros return when the
288 field is not present. */
289 if (alias == 0 && expr == 0 && offset == 0
291 || (mode != BLKmode && GET_MODE_SIZE (mode) == INTVAL (size)))
292 && (STRICT_ALIGNMENT && mode != BLKmode
293 ? align == GET_MODE_ALIGNMENT (mode) : align == BITS_PER_UNIT))
298 attrs.offset = offset;
302 slot = htab_find_slot (mem_attrs_htab, &attrs, INSERT);
305 *slot = ggc_alloc (sizeof (mem_attrs));
306 memcpy (*slot, &attrs, sizeof (mem_attrs));
312 /* Returns a hash code for X (which is a really a reg_attrs *). */
315 reg_attrs_htab_hash (const void *x)
317 const reg_attrs *const p = (const reg_attrs *) x;
319 return ((p->offset * 1000) ^ (long) p->decl);
322 /* Returns nonzero if the value represented by X (which is really a
323 reg_attrs *) is the same as that given by Y (which is also really a
327 reg_attrs_htab_eq (const void *x, const void *y)
329 const reg_attrs *const p = (const reg_attrs *) x;
330 const reg_attrs *const q = (const reg_attrs *) y;
332 return (p->decl == q->decl && p->offset == q->offset);
334 /* Allocate a new reg_attrs structure and insert it into the hash table if
335 one identical to it is not already in the table. We are doing this for
339 get_reg_attrs (tree decl, int offset)
344 /* If everything is the default, we can just return zero. */
345 if (decl == 0 && offset == 0)
349 attrs.offset = offset;
351 slot = htab_find_slot (reg_attrs_htab, &attrs, INSERT);
354 *slot = ggc_alloc (sizeof (reg_attrs));
355 memcpy (*slot, &attrs, sizeof (reg_attrs));
363 /* Generate an empty ASM_INPUT, which is used to block attempts to schedule
369 rtx x = gen_rtx_ASM_INPUT (VOIDmode, "");
370 MEM_VOLATILE_P (x) = true;
376 /* Generate a new REG rtx. Make sure ORIGINAL_REGNO is set properly, and
377 don't attempt to share with the various global pieces of rtl (such as
378 frame_pointer_rtx). */
381 gen_raw_REG (enum machine_mode mode, int regno)
383 rtx x = gen_rtx_raw_REG (mode, regno);
384 ORIGINAL_REGNO (x) = regno;
388 /* There are some RTL codes that require special attention; the generation
389 functions do the raw handling. If you add to this list, modify
390 special_rtx in gengenrtl.c as well. */
393 gen_rtx_CONST_INT (enum machine_mode mode ATTRIBUTE_UNUSED, HOST_WIDE_INT arg)
397 if (arg >= - MAX_SAVED_CONST_INT && arg <= MAX_SAVED_CONST_INT)
398 return const_int_rtx[arg + MAX_SAVED_CONST_INT];
400 #if STORE_FLAG_VALUE != 1 && STORE_FLAG_VALUE != -1
401 if (const_true_rtx && arg == STORE_FLAG_VALUE)
402 return const_true_rtx;
405 /* Look up the CONST_INT in the hash table. */
406 slot = htab_find_slot_with_hash (const_int_htab, &arg,
407 (hashval_t) arg, INSERT);
409 *slot = gen_rtx_raw_CONST_INT (VOIDmode, arg);
415 gen_int_mode (HOST_WIDE_INT c, enum machine_mode mode)
417 return GEN_INT (trunc_int_for_mode (c, mode));
420 /* CONST_DOUBLEs might be created from pairs of integers, or from
421 REAL_VALUE_TYPEs. Also, their length is known only at run time,
422 so we cannot use gen_rtx_raw_CONST_DOUBLE. */
424 /* Determine whether REAL, a CONST_DOUBLE, already exists in the
425 hash table. If so, return its counterpart; otherwise add it
426 to the hash table and return it. */
428 lookup_const_double (rtx real)
430 void **slot = htab_find_slot (const_double_htab, real, INSERT);
437 /* Return a CONST_DOUBLE rtx for a floating-point value specified by
438 VALUE in mode MODE. */
440 const_double_from_real_value (REAL_VALUE_TYPE value, enum machine_mode mode)
442 rtx real = rtx_alloc (CONST_DOUBLE);
443 PUT_MODE (real, mode);
447 return lookup_const_double (real);
450 /* Return a CONST_DOUBLE or CONST_INT for a value specified as a pair
451 of ints: I0 is the low-order word and I1 is the high-order word.
452 Do not use this routine for non-integer modes; convert to
453 REAL_VALUE_TYPE and use CONST_DOUBLE_FROM_REAL_VALUE. */
456 immed_double_const (HOST_WIDE_INT i0, HOST_WIDE_INT i1, enum machine_mode mode)
461 /* There are the following cases (note that there are no modes with
462 HOST_BITS_PER_WIDE_INT < GET_MODE_BITSIZE (mode) < 2 * HOST_BITS_PER_WIDE_INT):
464 1) If GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT, then we use
466 2) GET_MODE_BITSIZE (mode) == 2 * HOST_BITS_PER_WIDE_INT, but the value of
467 the integer fits into HOST_WIDE_INT anyway (i.e., i1 consists only
468 from copies of the sign bit, and sign of i0 and i1 are the same), then
469 we return a CONST_INT for i0.
470 3) Otherwise, we create a CONST_DOUBLE for i0 and i1. */
471 if (mode != VOIDmode)
473 gcc_assert (GET_MODE_CLASS (mode) == MODE_INT
474 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT
475 /* We can get a 0 for an error mark. */
476 || GET_MODE_CLASS (mode) == MODE_VECTOR_INT
477 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT);
479 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
480 return gen_int_mode (i0, mode);
482 gcc_assert (GET_MODE_BITSIZE (mode) == 2 * HOST_BITS_PER_WIDE_INT);
485 /* If this integer fits in one word, return a CONST_INT. */
486 if ((i1 == 0 && i0 >= 0) || (i1 == ~0 && i0 < 0))
489 /* We use VOIDmode for integers. */
490 value = rtx_alloc (CONST_DOUBLE);
491 PUT_MODE (value, VOIDmode);
493 CONST_DOUBLE_LOW (value) = i0;
494 CONST_DOUBLE_HIGH (value) = i1;
496 for (i = 2; i < (sizeof CONST_DOUBLE_FORMAT - 1); i++)
497 XWINT (value, i) = 0;
499 return lookup_const_double (value);
503 gen_rtx_REG (enum machine_mode mode, unsigned int regno)
505 /* In case the MD file explicitly references the frame pointer, have
506 all such references point to the same frame pointer. This is
507 used during frame pointer elimination to distinguish the explicit
508 references to these registers from pseudos that happened to be
511 If we have eliminated the frame pointer or arg pointer, we will
512 be using it as a normal register, for example as a spill
513 register. In such cases, we might be accessing it in a mode that
514 is not Pmode and therefore cannot use the pre-allocated rtx.
516 Also don't do this when we are making new REGs in reload, since
517 we don't want to get confused with the real pointers. */
519 if (mode == Pmode && !reload_in_progress)
521 if (regno == FRAME_POINTER_REGNUM
522 && (!reload_completed || frame_pointer_needed))
523 return frame_pointer_rtx;
524 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
525 if (regno == HARD_FRAME_POINTER_REGNUM
526 && (!reload_completed || frame_pointer_needed))
527 return hard_frame_pointer_rtx;
529 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM && HARD_FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
530 if (regno == ARG_POINTER_REGNUM)
531 return arg_pointer_rtx;
533 #ifdef RETURN_ADDRESS_POINTER_REGNUM
534 if (regno == RETURN_ADDRESS_POINTER_REGNUM)
535 return return_address_pointer_rtx;
537 if (regno == (unsigned) PIC_OFFSET_TABLE_REGNUM
538 && fixed_regs[PIC_OFFSET_TABLE_REGNUM])
539 return pic_offset_table_rtx;
540 if (regno == STACK_POINTER_REGNUM)
541 return stack_pointer_rtx;
545 /* If the per-function register table has been set up, try to re-use
546 an existing entry in that table to avoid useless generation of RTL.
548 This code is disabled for now until we can fix the various backends
549 which depend on having non-shared hard registers in some cases. Long
550 term we want to re-enable this code as it can significantly cut down
551 on the amount of useless RTL that gets generated.
553 We'll also need to fix some code that runs after reload that wants to
554 set ORIGINAL_REGNO. */
559 && regno < FIRST_PSEUDO_REGISTER
560 && reg_raw_mode[regno] == mode)
561 return regno_reg_rtx[regno];
564 return gen_raw_REG (mode, regno);
568 gen_rtx_MEM (enum machine_mode mode, rtx addr)
570 rtx rt = gen_rtx_raw_MEM (mode, addr);
572 /* This field is not cleared by the mere allocation of the rtx, so
579 /* Generate a memory referring to non-trapping constant memory. */
582 gen_const_mem (enum machine_mode mode, rtx addr)
584 rtx mem = gen_rtx_MEM (mode, addr);
585 MEM_READONLY_P (mem) = 1;
586 MEM_NOTRAP_P (mem) = 1;
590 /* Generate a MEM referring to fixed portions of the frame, e.g., register
594 gen_frame_mem (enum machine_mode mode, rtx addr)
596 rtx mem = gen_rtx_MEM (mode, addr);
597 MEM_NOTRAP_P (mem) = 1;
598 set_mem_alias_set (mem, get_frame_alias_set ());
602 /* Generate a MEM referring to a temporary use of the stack, not part
603 of the fixed stack frame. For example, something which is pushed
604 by a target splitter. */
606 gen_tmp_stack_mem (enum machine_mode mode, rtx addr)
608 rtx mem = gen_rtx_MEM (mode, addr);
609 MEM_NOTRAP_P (mem) = 1;
610 if (!current_function_calls_alloca)
611 set_mem_alias_set (mem, get_frame_alias_set ());
615 /* We want to create (subreg:OMODE (obj:IMODE) OFFSET). Return true if
616 this construct would be valid, and false otherwise. */
619 validate_subreg (enum machine_mode omode, enum machine_mode imode,
620 rtx reg, unsigned int offset)
622 unsigned int isize = GET_MODE_SIZE (imode);
623 unsigned int osize = GET_MODE_SIZE (omode);
625 /* All subregs must be aligned. */
626 if (offset % osize != 0)
629 /* The subreg offset cannot be outside the inner object. */
633 /* ??? This should not be here. Temporarily continue to allow word_mode
634 subregs of anything. The most common offender is (subreg:SI (reg:DF)).
635 Generally, backends are doing something sketchy but it'll take time to
637 if (omode == word_mode)
639 /* ??? Similarly, e.g. with (subreg:DF (reg:TI)). Though store_bit_field
640 is the culprit here, and not the backends. */
641 else if (osize >= UNITS_PER_WORD && isize >= osize)
643 /* Allow component subregs of complex and vector. Though given the below
644 extraction rules, it's not always clear what that means. */
645 else if ((COMPLEX_MODE_P (imode) || VECTOR_MODE_P (imode))
646 && GET_MODE_INNER (imode) == omode)
648 /* ??? x86 sse code makes heavy use of *paradoxical* vector subregs,
649 i.e. (subreg:V4SF (reg:SF) 0). This surely isn't the cleanest way to
650 represent this. It's questionable if this ought to be represented at
651 all -- why can't this all be hidden in post-reload splitters that make
652 arbitrarily mode changes to the registers themselves. */
653 else if (VECTOR_MODE_P (omode) && GET_MODE_INNER (omode) == imode)
655 /* Subregs involving floating point modes are not allowed to
656 change size. Therefore (subreg:DI (reg:DF) 0) is fine, but
657 (subreg:SI (reg:DF) 0) isn't. */
658 else if (FLOAT_MODE_P (imode) || FLOAT_MODE_P (omode))
664 /* Paradoxical subregs must have offset zero. */
668 /* This is a normal subreg. Verify that the offset is representable. */
670 /* For hard registers, we already have most of these rules collected in
671 subreg_offset_representable_p. */
672 if (reg && REG_P (reg) && HARD_REGISTER_P (reg))
674 unsigned int regno = REGNO (reg);
676 #ifdef CANNOT_CHANGE_MODE_CLASS
677 if ((COMPLEX_MODE_P (imode) || VECTOR_MODE_P (imode))
678 && GET_MODE_INNER (imode) == omode)
680 else if (REG_CANNOT_CHANGE_MODE_P (regno, imode, omode))
684 return subreg_offset_representable_p (regno, imode, offset, omode);
687 /* For pseudo registers, we want most of the same checks. Namely:
688 If the register no larger than a word, the subreg must be lowpart.
689 If the register is larger than a word, the subreg must be the lowpart
690 of a subword. A subreg does *not* perform arbitrary bit extraction.
691 Given that we've already checked mode/offset alignment, we only have
692 to check subword subregs here. */
693 if (osize < UNITS_PER_WORD)
695 enum machine_mode wmode = isize > UNITS_PER_WORD ? word_mode : imode;
696 unsigned int low_off = subreg_lowpart_offset (omode, wmode);
697 if (offset % UNITS_PER_WORD != low_off)
704 gen_rtx_SUBREG (enum machine_mode mode, rtx reg, int offset)
706 gcc_assert (validate_subreg (mode, GET_MODE (reg), reg, offset));
707 return gen_rtx_raw_SUBREG (mode, reg, offset);
710 /* Generate a SUBREG representing the least-significant part of REG if MODE
711 is smaller than mode of REG, otherwise paradoxical SUBREG. */
714 gen_lowpart_SUBREG (enum machine_mode mode, rtx reg)
716 enum machine_mode inmode;
718 inmode = GET_MODE (reg);
719 if (inmode == VOIDmode)
721 return gen_rtx_SUBREG (mode, reg,
722 subreg_lowpart_offset (mode, inmode));
725 /* gen_rtvec (n, [rt1, ..., rtn])
727 ** This routine creates an rtvec and stores within it the
728 ** pointers to rtx's which are its arguments.
733 gen_rtvec (int n, ...)
742 return NULL_RTVEC; /* Don't allocate an empty rtvec... */
744 vector = alloca (n * sizeof (rtx));
746 for (i = 0; i < n; i++)
747 vector[i] = va_arg (p, rtx);
749 /* The definition of VA_* in K&R C causes `n' to go out of scope. */
753 return gen_rtvec_v (save_n, vector);
757 gen_rtvec_v (int n, rtx *argp)
763 return NULL_RTVEC; /* Don't allocate an empty rtvec... */
765 rt_val = rtvec_alloc (n); /* Allocate an rtvec... */
767 for (i = 0; i < n; i++)
768 rt_val->elem[i] = *argp++;
773 /* Generate a REG rtx for a new pseudo register of mode MODE.
774 This pseudo is assigned the next sequential register number. */
777 gen_reg_rtx (enum machine_mode mode)
779 struct function *f = cfun;
782 gcc_assert (can_create_pseudo_p ());
784 if (generating_concat_p
785 && (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
786 || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT))
788 /* For complex modes, don't make a single pseudo.
789 Instead, make a CONCAT of two pseudos.
790 This allows noncontiguous allocation of the real and imaginary parts,
791 which makes much better code. Besides, allocating DCmode
792 pseudos overstrains reload on some machines like the 386. */
793 rtx realpart, imagpart;
794 enum machine_mode partmode = GET_MODE_INNER (mode);
796 realpart = gen_reg_rtx (partmode);
797 imagpart = gen_reg_rtx (partmode);
798 return gen_rtx_CONCAT (mode, realpart, imagpart);
801 /* Make sure regno_pointer_align, and regno_reg_rtx are large
802 enough to have an element for this pseudo reg number. */
804 if (reg_rtx_no == f->emit->regno_pointer_align_length)
806 int old_size = f->emit->regno_pointer_align_length;
810 new = ggc_realloc (f->emit->regno_pointer_align, old_size * 2);
811 memset (new + old_size, 0, old_size);
812 f->emit->regno_pointer_align = (unsigned char *) new;
814 new1 = ggc_realloc (f->emit->x_regno_reg_rtx,
815 old_size * 2 * sizeof (rtx));
816 memset (new1 + old_size, 0, old_size * sizeof (rtx));
817 regno_reg_rtx = new1;
819 f->emit->regno_pointer_align_length = old_size * 2;
822 val = gen_raw_REG (mode, reg_rtx_no);
823 regno_reg_rtx[reg_rtx_no++] = val;
827 /* Update NEW with the same attributes as REG, but offsetted by OFFSET.
828 Do the big endian correction if needed. */
831 update_reg_offset (rtx new, rtx reg, int offset)
834 HOST_WIDE_INT var_size;
836 /* PR middle-end/14084
837 The problem appears when a variable is stored in a larger register
838 and later it is used in the original mode or some mode in between
839 or some part of variable is accessed.
841 On little endian machines there is no problem because
842 the REG_OFFSET of the start of the variable is the same when
843 accessed in any mode (it is 0).
845 However, this is not true on big endian machines.
846 The offset of the start of the variable is different when accessed
848 When we are taking a part of the REG we have to change the OFFSET
849 from offset WRT size of mode of REG to offset WRT size of variable.
851 If we would not do the big endian correction the resulting REG_OFFSET
852 would be larger than the size of the DECL.
854 Examples of correction, for BYTES_BIG_ENDIAN WORDS_BIG_ENDIAN machine:
856 REG.mode MODE DECL size old offset new offset description
857 DI SI 4 4 0 int32 in SImode
858 DI SI 1 4 0 char in SImode
859 DI QI 1 7 0 char in QImode
860 DI QI 4 5 1 1st element in QImode
862 DI HI 4 6 2 1st element in HImode
865 If the size of DECL is equal or greater than the size of REG
866 we can't do this correction because the register holds the
867 whole variable or a part of the variable and thus the REG_OFFSET
868 is already correct. */
870 decl = REG_EXPR (reg);
871 if ((BYTES_BIG_ENDIAN || WORDS_BIG_ENDIAN)
874 && GET_MODE_SIZE (GET_MODE (reg)) > GET_MODE_SIZE (GET_MODE (new))
875 && ((var_size = int_size_in_bytes (TREE_TYPE (decl))) > 0
876 && var_size < GET_MODE_SIZE (GET_MODE (reg))))
880 /* Convert machine endian to little endian WRT size of mode of REG. */
881 if (WORDS_BIG_ENDIAN)
882 offset_le = ((GET_MODE_SIZE (GET_MODE (reg)) - 1 - offset)
883 / UNITS_PER_WORD) * UNITS_PER_WORD;
885 offset_le = (offset / UNITS_PER_WORD) * UNITS_PER_WORD;
887 if (BYTES_BIG_ENDIAN)
888 offset_le += ((GET_MODE_SIZE (GET_MODE (reg)) - 1 - offset)
891 offset_le += offset % UNITS_PER_WORD;
893 if (offset_le >= var_size)
895 /* MODE is wider than the variable so the new reg will cover
896 the whole variable so the resulting OFFSET should be 0. */
901 /* Convert little endian to machine endian WRT size of variable. */
902 if (WORDS_BIG_ENDIAN)
903 offset = ((var_size - 1 - offset_le)
904 / UNITS_PER_WORD) * UNITS_PER_WORD;
906 offset = (offset_le / UNITS_PER_WORD) * UNITS_PER_WORD;
908 if (BYTES_BIG_ENDIAN)
909 offset += ((var_size - 1 - offset_le)
912 offset += offset_le % UNITS_PER_WORD;
916 REG_ATTRS (new) = get_reg_attrs (REG_EXPR (reg),
917 REG_OFFSET (reg) + offset);
920 /* Generate a register with same attributes as REG, but offsetted by
924 gen_rtx_REG_offset (rtx reg, enum machine_mode mode, unsigned int regno,
927 rtx new = gen_rtx_REG (mode, regno);
929 update_reg_offset (new, reg, offset);
933 /* Generate a new pseudo-register with the same attributes as REG, but
934 offsetted by OFFSET. */
937 gen_reg_rtx_offset (rtx reg, enum machine_mode mode, int offset)
939 rtx new = gen_reg_rtx (mode);
941 update_reg_offset (new, reg, offset);
945 /* Set the decl for MEM to DECL. */
948 set_reg_attrs_from_mem (rtx reg, rtx mem)
950 if (MEM_OFFSET (mem) && GET_CODE (MEM_OFFSET (mem)) == CONST_INT)
952 = get_reg_attrs (MEM_EXPR (mem), INTVAL (MEM_OFFSET (mem)));
955 /* Set the register attributes for registers contained in PARM_RTX.
956 Use needed values from memory attributes of MEM. */
959 set_reg_attrs_for_parm (rtx parm_rtx, rtx mem)
961 if (REG_P (parm_rtx))
962 set_reg_attrs_from_mem (parm_rtx, mem);
963 else if (GET_CODE (parm_rtx) == PARALLEL)
965 /* Check for a NULL entry in the first slot, used to indicate that the
966 parameter goes both on the stack and in registers. */
967 int i = XEXP (XVECEXP (parm_rtx, 0, 0), 0) ? 0 : 1;
968 for (; i < XVECLEN (parm_rtx, 0); i++)
970 rtx x = XVECEXP (parm_rtx, 0, i);
971 if (REG_P (XEXP (x, 0)))
972 REG_ATTRS (XEXP (x, 0))
973 = get_reg_attrs (MEM_EXPR (mem),
974 INTVAL (XEXP (x, 1)));
979 /* Assign the RTX X to declaration T. */
981 set_decl_rtl (tree t, rtx x)
983 DECL_WRTL_CHECK (t)->decl_with_rtl.rtl = x;
987 /* For register, we maintain the reverse information too. */
989 REG_ATTRS (x) = get_reg_attrs (t, 0);
990 else if (GET_CODE (x) == SUBREG)
991 REG_ATTRS (SUBREG_REG (x))
992 = get_reg_attrs (t, -SUBREG_BYTE (x));
993 if (GET_CODE (x) == CONCAT)
995 if (REG_P (XEXP (x, 0)))
996 REG_ATTRS (XEXP (x, 0)) = get_reg_attrs (t, 0);
997 if (REG_P (XEXP (x, 1)))
998 REG_ATTRS (XEXP (x, 1))
999 = get_reg_attrs (t, GET_MODE_UNIT_SIZE (GET_MODE (XEXP (x, 0))));
1001 if (GET_CODE (x) == PARALLEL)
1004 for (i = 0; i < XVECLEN (x, 0); i++)
1006 rtx y = XVECEXP (x, 0, i);
1007 if (REG_P (XEXP (y, 0)))
1008 REG_ATTRS (XEXP (y, 0)) = get_reg_attrs (t, INTVAL (XEXP (y, 1)));
1013 /* Assign the RTX X to parameter declaration T. */
1015 set_decl_incoming_rtl (tree t, rtx x)
1017 DECL_INCOMING_RTL (t) = x;
1021 /* For register, we maintain the reverse information too. */
1023 REG_ATTRS (x) = get_reg_attrs (t, 0);
1024 else if (GET_CODE (x) == SUBREG)
1025 REG_ATTRS (SUBREG_REG (x))
1026 = get_reg_attrs (t, -SUBREG_BYTE (x));
1027 if (GET_CODE (x) == CONCAT)
1029 if (REG_P (XEXP (x, 0)))
1030 REG_ATTRS (XEXP (x, 0)) = get_reg_attrs (t, 0);
1031 if (REG_P (XEXP (x, 1)))
1032 REG_ATTRS (XEXP (x, 1))
1033 = get_reg_attrs (t, GET_MODE_UNIT_SIZE (GET_MODE (XEXP (x, 0))));
1035 if (GET_CODE (x) == PARALLEL)
1039 /* Check for a NULL entry, used to indicate that the parameter goes
1040 both on the stack and in registers. */
1041 if (XEXP (XVECEXP (x, 0, 0), 0))
1046 for (i = start; i < XVECLEN (x, 0); i++)
1048 rtx y = XVECEXP (x, 0, i);
1049 if (REG_P (XEXP (y, 0)))
1050 REG_ATTRS (XEXP (y, 0)) = get_reg_attrs (t, INTVAL (XEXP (y, 1)));
1055 /* Identify REG (which may be a CONCAT) as a user register. */
1058 mark_user_reg (rtx reg)
1060 if (GET_CODE (reg) == CONCAT)
1062 REG_USERVAR_P (XEXP (reg, 0)) = 1;
1063 REG_USERVAR_P (XEXP (reg, 1)) = 1;
1067 gcc_assert (REG_P (reg));
1068 REG_USERVAR_P (reg) = 1;
1072 /* Identify REG as a probable pointer register and show its alignment
1073 as ALIGN, if nonzero. */
1076 mark_reg_pointer (rtx reg, int align)
1078 if (! REG_POINTER (reg))
1080 REG_POINTER (reg) = 1;
1083 REGNO_POINTER_ALIGN (REGNO (reg)) = align;
1085 else if (align && align < REGNO_POINTER_ALIGN (REGNO (reg)))
1086 /* We can no-longer be sure just how aligned this pointer is. */
1087 REGNO_POINTER_ALIGN (REGNO (reg)) = align;
1090 /* Return 1 plus largest pseudo reg number used in the current function. */
1098 /* Return 1 + the largest label number used so far in the current function. */
1101 max_label_num (void)
1106 /* Return first label number used in this function (if any were used). */
1109 get_first_label_num (void)
1111 return first_label_num;
1114 /* If the rtx for label was created during the expansion of a nested
1115 function, then first_label_num won't include this label number.
1116 Fix this now so that array indicies work later. */
1119 maybe_set_first_label_num (rtx x)
1121 if (CODE_LABEL_NUMBER (x) < first_label_num)
1122 first_label_num = CODE_LABEL_NUMBER (x);
1125 /* Return a value representing some low-order bits of X, where the number
1126 of low-order bits is given by MODE. Note that no conversion is done
1127 between floating-point and fixed-point values, rather, the bit
1128 representation is returned.
1130 This function handles the cases in common between gen_lowpart, below,
1131 and two variants in cse.c and combine.c. These are the cases that can
1132 be safely handled at all points in the compilation.
1134 If this is not a case we can handle, return 0. */
1137 gen_lowpart_common (enum machine_mode mode, rtx x)
1139 int msize = GET_MODE_SIZE (mode);
1142 enum machine_mode innermode;
1144 /* Unfortunately, this routine doesn't take a parameter for the mode of X,
1145 so we have to make one up. Yuk. */
1146 innermode = GET_MODE (x);
1147 if (GET_CODE (x) == CONST_INT
1148 && msize * BITS_PER_UNIT <= HOST_BITS_PER_WIDE_INT)
1149 innermode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1150 else if (innermode == VOIDmode)
1151 innermode = mode_for_size (HOST_BITS_PER_WIDE_INT * 2, MODE_INT, 0);
1153 xsize = GET_MODE_SIZE (innermode);
1155 gcc_assert (innermode != VOIDmode && innermode != BLKmode);
1157 if (innermode == mode)
1160 /* MODE must occupy no more words than the mode of X. */
1161 if ((msize + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD
1162 > ((xsize + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
1165 /* Don't allow generating paradoxical FLOAT_MODE subregs. */
1166 if (SCALAR_FLOAT_MODE_P (mode) && msize > xsize)
1169 offset = subreg_lowpart_offset (mode, innermode);
1171 if ((GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND)
1172 && (GET_MODE_CLASS (mode) == MODE_INT
1173 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT))
1175 /* If we are getting the low-order part of something that has been
1176 sign- or zero-extended, we can either just use the object being
1177 extended or make a narrower extension. If we want an even smaller
1178 piece than the size of the object being extended, call ourselves
1181 This case is used mostly by combine and cse. */
1183 if (GET_MODE (XEXP (x, 0)) == mode)
1185 else if (msize < GET_MODE_SIZE (GET_MODE (XEXP (x, 0))))
1186 return gen_lowpart_common (mode, XEXP (x, 0));
1187 else if (msize < xsize)
1188 return gen_rtx_fmt_e (GET_CODE (x), mode, XEXP (x, 0));
1190 else if (GET_CODE (x) == SUBREG || REG_P (x)
1191 || GET_CODE (x) == CONCAT || GET_CODE (x) == CONST_VECTOR
1192 || GET_CODE (x) == CONST_DOUBLE || GET_CODE (x) == CONST_INT)
1193 return simplify_gen_subreg (mode, x, innermode, offset);
1195 /* Otherwise, we can't do this. */
1200 gen_highpart (enum machine_mode mode, rtx x)
1202 unsigned int msize = GET_MODE_SIZE (mode);
1205 /* This case loses if X is a subreg. To catch bugs early,
1206 complain if an invalid MODE is used even in other cases. */
1207 gcc_assert (msize <= UNITS_PER_WORD
1208 || msize == (unsigned int) GET_MODE_UNIT_SIZE (GET_MODE (x)));
1210 result = simplify_gen_subreg (mode, x, GET_MODE (x),
1211 subreg_highpart_offset (mode, GET_MODE (x)));
1212 gcc_assert (result);
1214 /* simplify_gen_subreg is not guaranteed to return a valid operand for
1215 the target if we have a MEM. gen_highpart must return a valid operand,
1216 emitting code if necessary to do so. */
1219 result = validize_mem (result);
1220 gcc_assert (result);
1226 /* Like gen_highpart, but accept mode of EXP operand in case EXP can
1227 be VOIDmode constant. */
1229 gen_highpart_mode (enum machine_mode outermode, enum machine_mode innermode, rtx exp)
1231 if (GET_MODE (exp) != VOIDmode)
1233 gcc_assert (GET_MODE (exp) == innermode);
1234 return gen_highpart (outermode, exp);
1236 return simplify_gen_subreg (outermode, exp, innermode,
1237 subreg_highpart_offset (outermode, innermode));
1240 /* Return offset in bytes to get OUTERMODE low part
1241 of the value in mode INNERMODE stored in memory in target format. */
1244 subreg_lowpart_offset (enum machine_mode outermode, enum machine_mode innermode)
1246 unsigned int offset = 0;
1247 int difference = (GET_MODE_SIZE (innermode) - GET_MODE_SIZE (outermode));
1251 if (WORDS_BIG_ENDIAN)
1252 offset += (difference / UNITS_PER_WORD) * UNITS_PER_WORD;
1253 if (BYTES_BIG_ENDIAN)
1254 offset += difference % UNITS_PER_WORD;
1260 /* Return offset in bytes to get OUTERMODE high part
1261 of the value in mode INNERMODE stored in memory in target format. */
1263 subreg_highpart_offset (enum machine_mode outermode, enum machine_mode innermode)
1265 unsigned int offset = 0;
1266 int difference = (GET_MODE_SIZE (innermode) - GET_MODE_SIZE (outermode));
1268 gcc_assert (GET_MODE_SIZE (innermode) >= GET_MODE_SIZE (outermode));
1272 if (! WORDS_BIG_ENDIAN)
1273 offset += (difference / UNITS_PER_WORD) * UNITS_PER_WORD;
1274 if (! BYTES_BIG_ENDIAN)
1275 offset += difference % UNITS_PER_WORD;
1281 /* Return 1 iff X, assumed to be a SUBREG,
1282 refers to the least significant part of its containing reg.
1283 If X is not a SUBREG, always return 1 (it is its own low part!). */
1286 subreg_lowpart_p (const_rtx x)
1288 if (GET_CODE (x) != SUBREG)
1290 else if (GET_MODE (SUBREG_REG (x)) == VOIDmode)
1293 return (subreg_lowpart_offset (GET_MODE (x), GET_MODE (SUBREG_REG (x)))
1294 == SUBREG_BYTE (x));
1297 /* Return subword OFFSET of operand OP.
1298 The word number, OFFSET, is interpreted as the word number starting
1299 at the low-order address. OFFSET 0 is the low-order word if not
1300 WORDS_BIG_ENDIAN, otherwise it is the high-order word.
1302 If we cannot extract the required word, we return zero. Otherwise,
1303 an rtx corresponding to the requested word will be returned.
1305 VALIDATE_ADDRESS is nonzero if the address should be validated. Before
1306 reload has completed, a valid address will always be returned. After
1307 reload, if a valid address cannot be returned, we return zero.
1309 If VALIDATE_ADDRESS is zero, we simply form the required address; validating
1310 it is the responsibility of the caller.
1312 MODE is the mode of OP in case it is a CONST_INT.
1314 ??? This is still rather broken for some cases. The problem for the
1315 moment is that all callers of this thing provide no 'goal mode' to
1316 tell us to work with. This exists because all callers were written
1317 in a word based SUBREG world.
1318 Now use of this function can be deprecated by simplify_subreg in most
1323 operand_subword (rtx op, unsigned int offset, int validate_address, enum machine_mode mode)
1325 if (mode == VOIDmode)
1326 mode = GET_MODE (op);
1328 gcc_assert (mode != VOIDmode);
1330 /* If OP is narrower than a word, fail. */
1332 && (GET_MODE_SIZE (mode) < UNITS_PER_WORD))
1335 /* If we want a word outside OP, return zero. */
1337 && (offset + 1) * UNITS_PER_WORD > GET_MODE_SIZE (mode))
1340 /* Form a new MEM at the requested address. */
1343 rtx new = adjust_address_nv (op, word_mode, offset * UNITS_PER_WORD);
1345 if (! validate_address)
1348 else if (reload_completed)
1350 if (! strict_memory_address_p (word_mode, XEXP (new, 0)))
1354 return replace_equiv_address (new, XEXP (new, 0));
1357 /* Rest can be handled by simplify_subreg. */
1358 return simplify_gen_subreg (word_mode, op, mode, (offset * UNITS_PER_WORD));
1361 /* Similar to `operand_subword', but never return 0. If we can't
1362 extract the required subword, put OP into a register and try again.
1363 The second attempt must succeed. We always validate the address in
1366 MODE is the mode of OP, in case it is CONST_INT. */
1369 operand_subword_force (rtx op, unsigned int offset, enum machine_mode mode)
1371 rtx result = operand_subword (op, offset, 1, mode);
1376 if (mode != BLKmode && mode != VOIDmode)
1378 /* If this is a register which can not be accessed by words, copy it
1379 to a pseudo register. */
1381 op = copy_to_reg (op);
1383 op = force_reg (mode, op);
1386 result = operand_subword (op, offset, 1, mode);
1387 gcc_assert (result);
1392 /* Within a MEM_EXPR, we care about either (1) a component ref of a decl,
1393 or (2) a component ref of something variable. Represent the later with
1394 a NULL expression. */
1397 component_ref_for_mem_expr (tree ref)
1399 tree inner = TREE_OPERAND (ref, 0);
1401 if (TREE_CODE (inner) == COMPONENT_REF)
1402 inner = component_ref_for_mem_expr (inner);
1405 /* Now remove any conversions: they don't change what the underlying
1406 object is. Likewise for SAVE_EXPR. */
1407 while (TREE_CODE (inner) == NOP_EXPR || TREE_CODE (inner) == CONVERT_EXPR
1408 || TREE_CODE (inner) == NON_LVALUE_EXPR
1409 || TREE_CODE (inner) == VIEW_CONVERT_EXPR
1410 || TREE_CODE (inner) == SAVE_EXPR)
1411 inner = TREE_OPERAND (inner, 0);
1413 if (! DECL_P (inner))
1417 if (inner == TREE_OPERAND (ref, 0))
1420 return build3 (COMPONENT_REF, TREE_TYPE (ref), inner,
1421 TREE_OPERAND (ref, 1), NULL_TREE);
1424 /* Returns 1 if both MEM_EXPR can be considered equal
1428 mem_expr_equal_p (tree expr1, tree expr2)
1433 if (! expr1 || ! expr2)
1436 if (TREE_CODE (expr1) != TREE_CODE (expr2))
1439 if (TREE_CODE (expr1) == COMPONENT_REF)
1441 mem_expr_equal_p (TREE_OPERAND (expr1, 0),
1442 TREE_OPERAND (expr2, 0))
1443 && mem_expr_equal_p (TREE_OPERAND (expr1, 1), /* field decl */
1444 TREE_OPERAND (expr2, 1));
1446 if (INDIRECT_REF_P (expr1))
1447 return mem_expr_equal_p (TREE_OPERAND (expr1, 0),
1448 TREE_OPERAND (expr2, 0));
1450 /* ARRAY_REFs, ARRAY_RANGE_REFs and BIT_FIELD_REFs should already
1451 have been resolved here. */
1452 gcc_assert (DECL_P (expr1));
1454 /* Decls with different pointers can't be equal. */
1458 /* Given REF, a MEM, and T, either the type of X or the expression
1459 corresponding to REF, set the memory attributes. OBJECTP is nonzero
1460 if we are making a new object of this type. BITPOS is nonzero if
1461 there is an offset outstanding on T that will be applied later. */
1464 set_mem_attributes_minus_bitpos (rtx ref, tree t, int objectp,
1465 HOST_WIDE_INT bitpos)
1467 HOST_WIDE_INT alias = MEM_ALIAS_SET (ref);
1468 tree expr = MEM_EXPR (ref);
1469 rtx offset = MEM_OFFSET (ref);
1470 rtx size = MEM_SIZE (ref);
1471 unsigned int align = MEM_ALIGN (ref);
1472 HOST_WIDE_INT apply_bitpos = 0;
1475 /* It can happen that type_for_mode was given a mode for which there
1476 is no language-level type. In which case it returns NULL, which
1481 type = TYPE_P (t) ? t : TREE_TYPE (t);
1482 if (type == error_mark_node)
1485 /* If we have already set DECL_RTL = ref, get_alias_set will get the
1486 wrong answer, as it assumes that DECL_RTL already has the right alias
1487 info. Callers should not set DECL_RTL until after the call to
1488 set_mem_attributes. */
1489 gcc_assert (!DECL_P (t) || ref != DECL_RTL_IF_SET (t));
1491 /* Get the alias set from the expression or type (perhaps using a
1492 front-end routine) and use it. */
1493 alias = get_alias_set (t);
1495 MEM_VOLATILE_P (ref) |= TYPE_VOLATILE (type);
1496 MEM_IN_STRUCT_P (ref)
1497 = AGGREGATE_TYPE_P (type) || TREE_CODE (type) == COMPLEX_TYPE;
1498 MEM_POINTER (ref) = POINTER_TYPE_P (type);
1500 /* If we are making an object of this type, or if this is a DECL, we know
1501 that it is a scalar if the type is not an aggregate. */
1502 if ((objectp || DECL_P (t))
1503 && ! AGGREGATE_TYPE_P (type)
1504 && TREE_CODE (type) != COMPLEX_TYPE)
1505 MEM_SCALAR_P (ref) = 1;
1507 /* We can set the alignment from the type if we are making an object,
1508 this is an INDIRECT_REF, or if TYPE_ALIGN_OK. */
1509 if (objectp || TREE_CODE (t) == INDIRECT_REF
1510 || TREE_CODE (t) == ALIGN_INDIRECT_REF
1511 || TYPE_ALIGN_OK (type))
1512 align = MAX (align, TYPE_ALIGN (type));
1514 if (TREE_CODE (t) == MISALIGNED_INDIRECT_REF)
1516 if (integer_zerop (TREE_OPERAND (t, 1)))
1517 /* We don't know anything about the alignment. */
1518 align = BITS_PER_UNIT;
1520 align = tree_low_cst (TREE_OPERAND (t, 1), 1);
1523 /* If the size is known, we can set that. */
1524 if (TYPE_SIZE_UNIT (type) && host_integerp (TYPE_SIZE_UNIT (type), 1))
1525 size = GEN_INT (tree_low_cst (TYPE_SIZE_UNIT (type), 1));
1527 /* If T is not a type, we may be able to deduce some more information about
1533 if (TREE_THIS_VOLATILE (t))
1534 MEM_VOLATILE_P (ref) = 1;
1536 /* Now remove any conversions: they don't change what the underlying
1537 object is. Likewise for SAVE_EXPR. */
1538 while (TREE_CODE (t) == NOP_EXPR || TREE_CODE (t) == CONVERT_EXPR
1539 || TREE_CODE (t) == NON_LVALUE_EXPR
1540 || TREE_CODE (t) == VIEW_CONVERT_EXPR
1541 || TREE_CODE (t) == SAVE_EXPR)
1542 t = TREE_OPERAND (t, 0);
1544 /* We may look through structure-like accesses for the purposes of
1545 examining TREE_THIS_NOTRAP, but not array-like accesses. */
1547 while (TREE_CODE (base) == COMPONENT_REF
1548 || TREE_CODE (base) == REALPART_EXPR
1549 || TREE_CODE (base) == IMAGPART_EXPR
1550 || TREE_CODE (base) == BIT_FIELD_REF)
1551 base = TREE_OPERAND (base, 0);
1555 if (CODE_CONTAINS_STRUCT (TREE_CODE (base), TS_DECL_WITH_VIS))
1556 MEM_NOTRAP_P (ref) = !DECL_WEAK (base);
1558 MEM_NOTRAP_P (ref) = 1;
1561 MEM_NOTRAP_P (ref) = TREE_THIS_NOTRAP (base);
1563 base = get_base_address (base);
1564 if (base && DECL_P (base)
1565 && TREE_READONLY (base)
1566 && (TREE_STATIC (base) || DECL_EXTERNAL (base)))
1568 tree base_type = TREE_TYPE (base);
1569 gcc_assert (!(base_type && TYPE_NEEDS_CONSTRUCTING (base_type))
1570 || DECL_ARTIFICIAL (base));
1571 MEM_READONLY_P (ref) = 1;
1574 /* If this expression uses it's parent's alias set, mark it such
1575 that we won't change it. */
1576 if (component_uses_parent_alias_set (t))
1577 MEM_KEEP_ALIAS_SET_P (ref) = 1;
1579 /* If this is a decl, set the attributes of the MEM from it. */
1583 offset = const0_rtx;
1584 apply_bitpos = bitpos;
1585 size = (DECL_SIZE_UNIT (t)
1586 && host_integerp (DECL_SIZE_UNIT (t), 1)
1587 ? GEN_INT (tree_low_cst (DECL_SIZE_UNIT (t), 1)) : 0);
1588 align = DECL_ALIGN (t);
1591 /* If this is a constant, we know the alignment. */
1592 else if (CONSTANT_CLASS_P (t))
1594 align = TYPE_ALIGN (type);
1595 #ifdef CONSTANT_ALIGNMENT
1596 align = CONSTANT_ALIGNMENT (t, align);
1600 /* If this is a field reference and not a bit-field, record it. */
1601 /* ??? There is some information that can be gleened from bit-fields,
1602 such as the word offset in the structure that might be modified.
1603 But skip it for now. */
1604 else if (TREE_CODE (t) == COMPONENT_REF
1605 && ! DECL_BIT_FIELD (TREE_OPERAND (t, 1)))
1607 expr = component_ref_for_mem_expr (t);
1608 offset = const0_rtx;
1609 apply_bitpos = bitpos;
1610 /* ??? Any reason the field size would be different than
1611 the size we got from the type? */
1614 /* If this is an array reference, look for an outer field reference. */
1615 else if (TREE_CODE (t) == ARRAY_REF)
1617 tree off_tree = size_zero_node;
1618 /* We can't modify t, because we use it at the end of the
1624 tree index = TREE_OPERAND (t2, 1);
1625 tree low_bound = array_ref_low_bound (t2);
1626 tree unit_size = array_ref_element_size (t2);
1628 /* We assume all arrays have sizes that are a multiple of a byte.
1629 First subtract the lower bound, if any, in the type of the
1630 index, then convert to sizetype and multiply by the size of
1631 the array element. */
1632 if (! integer_zerop (low_bound))
1633 index = fold_build2 (MINUS_EXPR, TREE_TYPE (index),
1636 off_tree = size_binop (PLUS_EXPR,
1637 size_binop (MULT_EXPR,
1638 fold_convert (sizetype,
1642 t2 = TREE_OPERAND (t2, 0);
1644 while (TREE_CODE (t2) == ARRAY_REF);
1650 if (host_integerp (off_tree, 1))
1652 HOST_WIDE_INT ioff = tree_low_cst (off_tree, 1);
1653 HOST_WIDE_INT aoff = (ioff & -ioff) * BITS_PER_UNIT;
1654 align = DECL_ALIGN (t2);
1655 if (aoff && (unsigned HOST_WIDE_INT) aoff < align)
1657 offset = GEN_INT (ioff);
1658 apply_bitpos = bitpos;
1661 else if (TREE_CODE (t2) == COMPONENT_REF)
1663 expr = component_ref_for_mem_expr (t2);
1664 if (host_integerp (off_tree, 1))
1666 offset = GEN_INT (tree_low_cst (off_tree, 1));
1667 apply_bitpos = bitpos;
1669 /* ??? Any reason the field size would be different than
1670 the size we got from the type? */
1672 else if (flag_argument_noalias > 1
1673 && (INDIRECT_REF_P (t2))
1674 && TREE_CODE (TREE_OPERAND (t2, 0)) == PARM_DECL)
1681 /* If this is a Fortran indirect argument reference, record the
1683 else if (flag_argument_noalias > 1
1684 && (INDIRECT_REF_P (t))
1685 && TREE_CODE (TREE_OPERAND (t, 0)) == PARM_DECL)
1692 /* If we modified OFFSET based on T, then subtract the outstanding
1693 bit position offset. Similarly, increase the size of the accessed
1694 object to contain the negative offset. */
1697 offset = plus_constant (offset, -(apply_bitpos / BITS_PER_UNIT));
1699 size = plus_constant (size, apply_bitpos / BITS_PER_UNIT);
1702 if (TREE_CODE (t) == ALIGN_INDIRECT_REF)
1704 /* Force EXPR and OFFSE to NULL, since we don't know exactly what
1705 we're overlapping. */
1710 /* Now set the attributes we computed above. */
1712 = get_mem_attrs (alias, expr, offset, size, align, GET_MODE (ref));
1714 /* If this is already known to be a scalar or aggregate, we are done. */
1715 if (MEM_IN_STRUCT_P (ref) || MEM_SCALAR_P (ref))
1718 /* If it is a reference into an aggregate, this is part of an aggregate.
1719 Otherwise we don't know. */
1720 else if (TREE_CODE (t) == COMPONENT_REF || TREE_CODE (t) == ARRAY_REF
1721 || TREE_CODE (t) == ARRAY_RANGE_REF
1722 || TREE_CODE (t) == BIT_FIELD_REF)
1723 MEM_IN_STRUCT_P (ref) = 1;
1727 set_mem_attributes (rtx ref, tree t, int objectp)
1729 set_mem_attributes_minus_bitpos (ref, t, objectp, 0);
1732 /* Set the decl for MEM to DECL. */
1735 set_mem_attrs_from_reg (rtx mem, rtx reg)
1738 = get_mem_attrs (MEM_ALIAS_SET (mem), REG_EXPR (reg),
1739 GEN_INT (REG_OFFSET (reg)),
1740 MEM_SIZE (mem), MEM_ALIGN (mem), GET_MODE (mem));
1743 /* Set the alias set of MEM to SET. */
1746 set_mem_alias_set (rtx mem, HOST_WIDE_INT set)
1748 #ifdef ENABLE_CHECKING
1749 /* If the new and old alias sets don't conflict, something is wrong. */
1750 gcc_assert (alias_sets_conflict_p (set, MEM_ALIAS_SET (mem)));
1753 MEM_ATTRS (mem) = get_mem_attrs (set, MEM_EXPR (mem), MEM_OFFSET (mem),
1754 MEM_SIZE (mem), MEM_ALIGN (mem),
1758 /* Set the alignment of MEM to ALIGN bits. */
1761 set_mem_align (rtx mem, unsigned int align)
1763 MEM_ATTRS (mem) = get_mem_attrs (MEM_ALIAS_SET (mem), MEM_EXPR (mem),
1764 MEM_OFFSET (mem), MEM_SIZE (mem), align,
1768 /* Set the expr for MEM to EXPR. */
1771 set_mem_expr (rtx mem, tree expr)
1774 = get_mem_attrs (MEM_ALIAS_SET (mem), expr, MEM_OFFSET (mem),
1775 MEM_SIZE (mem), MEM_ALIGN (mem), GET_MODE (mem));
1778 /* Set the offset of MEM to OFFSET. */
1781 set_mem_offset (rtx mem, rtx offset)
1783 MEM_ATTRS (mem) = get_mem_attrs (MEM_ALIAS_SET (mem), MEM_EXPR (mem),
1784 offset, MEM_SIZE (mem), MEM_ALIGN (mem),
1788 /* Set the size of MEM to SIZE. */
1791 set_mem_size (rtx mem, rtx size)
1793 MEM_ATTRS (mem) = get_mem_attrs (MEM_ALIAS_SET (mem), MEM_EXPR (mem),
1794 MEM_OFFSET (mem), size, MEM_ALIGN (mem),
1798 /* Return a memory reference like MEMREF, but with its mode changed to MODE
1799 and its address changed to ADDR. (VOIDmode means don't change the mode.
1800 NULL for ADDR means don't change the address.) VALIDATE is nonzero if the
1801 returned memory location is required to be valid. The memory
1802 attributes are not changed. */
1805 change_address_1 (rtx memref, enum machine_mode mode, rtx addr, int validate)
1809 gcc_assert (MEM_P (memref));
1810 if (mode == VOIDmode)
1811 mode = GET_MODE (memref);
1813 addr = XEXP (memref, 0);
1814 if (mode == GET_MODE (memref) && addr == XEXP (memref, 0)
1815 && (!validate || memory_address_p (mode, addr)))
1820 if (reload_in_progress || reload_completed)
1821 gcc_assert (memory_address_p (mode, addr));
1823 addr = memory_address (mode, addr);
1826 if (rtx_equal_p (addr, XEXP (memref, 0)) && mode == GET_MODE (memref))
1829 new = gen_rtx_MEM (mode, addr);
1830 MEM_COPY_ATTRIBUTES (new, memref);
1834 /* Like change_address_1 with VALIDATE nonzero, but we are not saying in what
1835 way we are changing MEMREF, so we only preserve the alias set. */
1838 change_address (rtx memref, enum machine_mode mode, rtx addr)
1840 rtx new = change_address_1 (memref, mode, addr, 1), size;
1841 enum machine_mode mmode = GET_MODE (new);
1844 size = mmode == BLKmode ? 0 : GEN_INT (GET_MODE_SIZE (mmode));
1845 align = mmode == BLKmode ? BITS_PER_UNIT : GET_MODE_ALIGNMENT (mmode);
1847 /* If there are no changes, just return the original memory reference. */
1850 if (MEM_ATTRS (memref) == 0
1851 || (MEM_EXPR (memref) == NULL
1852 && MEM_OFFSET (memref) == NULL
1853 && MEM_SIZE (memref) == size
1854 && MEM_ALIGN (memref) == align))
1857 new = gen_rtx_MEM (mmode, XEXP (memref, 0));
1858 MEM_COPY_ATTRIBUTES (new, memref);
1862 = get_mem_attrs (MEM_ALIAS_SET (memref), 0, 0, size, align, mmode);
1867 /* Return a memory reference like MEMREF, but with its mode changed
1868 to MODE and its address offset by OFFSET bytes. If VALIDATE is
1869 nonzero, the memory address is forced to be valid.
1870 If ADJUST is zero, OFFSET is only used to update MEM_ATTRS
1871 and caller is responsible for adjusting MEMREF base register. */
1874 adjust_address_1 (rtx memref, enum machine_mode mode, HOST_WIDE_INT offset,
1875 int validate, int adjust)
1877 rtx addr = XEXP (memref, 0);
1879 rtx memoffset = MEM_OFFSET (memref);
1881 unsigned int memalign = MEM_ALIGN (memref);
1883 /* If there are no changes, just return the original memory reference. */
1884 if (mode == GET_MODE (memref) && !offset
1885 && (!validate || memory_address_p (mode, addr)))
1888 /* ??? Prefer to create garbage instead of creating shared rtl.
1889 This may happen even if offset is nonzero -- consider
1890 (plus (plus reg reg) const_int) -- so do this always. */
1891 addr = copy_rtx (addr);
1895 /* If MEMREF is a LO_SUM and the offset is within the alignment of the
1896 object, we can merge it into the LO_SUM. */
1897 if (GET_MODE (memref) != BLKmode && GET_CODE (addr) == LO_SUM
1899 && (unsigned HOST_WIDE_INT) offset
1900 < GET_MODE_ALIGNMENT (GET_MODE (memref)) / BITS_PER_UNIT)
1901 addr = gen_rtx_LO_SUM (Pmode, XEXP (addr, 0),
1902 plus_constant (XEXP (addr, 1), offset));
1904 addr = plus_constant (addr, offset);
1907 new = change_address_1 (memref, mode, addr, validate);
1909 /* Compute the new values of the memory attributes due to this adjustment.
1910 We add the offsets and update the alignment. */
1912 memoffset = GEN_INT (offset + INTVAL (memoffset));
1914 /* Compute the new alignment by taking the MIN of the alignment and the
1915 lowest-order set bit in OFFSET, but don't change the alignment if OFFSET
1920 (unsigned HOST_WIDE_INT) (offset & -offset) * BITS_PER_UNIT);
1922 /* We can compute the size in a number of ways. */
1923 if (GET_MODE (new) != BLKmode)
1924 size = GEN_INT (GET_MODE_SIZE (GET_MODE (new)));
1925 else if (MEM_SIZE (memref))
1926 size = plus_constant (MEM_SIZE (memref), -offset);
1928 MEM_ATTRS (new) = get_mem_attrs (MEM_ALIAS_SET (memref), MEM_EXPR (memref),
1929 memoffset, size, memalign, GET_MODE (new));
1931 /* At some point, we should validate that this offset is within the object,
1932 if all the appropriate values are known. */
1936 /* Return a memory reference like MEMREF, but with its mode changed
1937 to MODE and its address changed to ADDR, which is assumed to be
1938 MEMREF offseted by OFFSET bytes. If VALIDATE is
1939 nonzero, the memory address is forced to be valid. */
1942 adjust_automodify_address_1 (rtx memref, enum machine_mode mode, rtx addr,
1943 HOST_WIDE_INT offset, int validate)
1945 memref = change_address_1 (memref, VOIDmode, addr, validate);
1946 return adjust_address_1 (memref, mode, offset, validate, 0);
1949 /* Return a memory reference like MEMREF, but whose address is changed by
1950 adding OFFSET, an RTX, to it. POW2 is the highest power of two factor
1951 known to be in OFFSET (possibly 1). */
1954 offset_address (rtx memref, rtx offset, unsigned HOST_WIDE_INT pow2)
1956 rtx new, addr = XEXP (memref, 0);
1958 new = simplify_gen_binary (PLUS, Pmode, addr, offset);
1960 /* At this point we don't know _why_ the address is invalid. It
1961 could have secondary memory references, multiplies or anything.
1963 However, if we did go and rearrange things, we can wind up not
1964 being able to recognize the magic around pic_offset_table_rtx.
1965 This stuff is fragile, and is yet another example of why it is
1966 bad to expose PIC machinery too early. */
1967 if (! memory_address_p (GET_MODE (memref), new)
1968 && GET_CODE (addr) == PLUS
1969 && XEXP (addr, 0) == pic_offset_table_rtx)
1971 addr = force_reg (GET_MODE (addr), addr);
1972 new = simplify_gen_binary (PLUS, Pmode, addr, offset);
1975 update_temp_slot_address (XEXP (memref, 0), new);
1976 new = change_address_1 (memref, VOIDmode, new, 1);
1978 /* If there are no changes, just return the original memory reference. */
1982 /* Update the alignment to reflect the offset. Reset the offset, which
1985 = get_mem_attrs (MEM_ALIAS_SET (memref), MEM_EXPR (memref), 0, 0,
1986 MIN (MEM_ALIGN (memref), pow2 * BITS_PER_UNIT),
1991 /* Return a memory reference like MEMREF, but with its address changed to
1992 ADDR. The caller is asserting that the actual piece of memory pointed
1993 to is the same, just the form of the address is being changed, such as
1994 by putting something into a register. */
1997 replace_equiv_address (rtx memref, rtx addr)
1999 /* change_address_1 copies the memory attribute structure without change
2000 and that's exactly what we want here. */
2001 update_temp_slot_address (XEXP (memref, 0), addr);
2002 return change_address_1 (memref, VOIDmode, addr, 1);
2005 /* Likewise, but the reference is not required to be valid. */
2008 replace_equiv_address_nv (rtx memref, rtx addr)
2010 return change_address_1 (memref, VOIDmode, addr, 0);
2013 /* Return a memory reference like MEMREF, but with its mode widened to
2014 MODE and offset by OFFSET. This would be used by targets that e.g.
2015 cannot issue QImode memory operations and have to use SImode memory
2016 operations plus masking logic. */
2019 widen_memory_access (rtx memref, enum machine_mode mode, HOST_WIDE_INT offset)
2021 rtx new = adjust_address_1 (memref, mode, offset, 1, 1);
2022 tree expr = MEM_EXPR (new);
2023 rtx memoffset = MEM_OFFSET (new);
2024 unsigned int size = GET_MODE_SIZE (mode);
2026 /* If there are no changes, just return the original memory reference. */
2030 /* If we don't know what offset we were at within the expression, then
2031 we can't know if we've overstepped the bounds. */
2037 if (TREE_CODE (expr) == COMPONENT_REF)
2039 tree field = TREE_OPERAND (expr, 1);
2040 tree offset = component_ref_field_offset (expr);
2042 if (! DECL_SIZE_UNIT (field))
2048 /* Is the field at least as large as the access? If so, ok,
2049 otherwise strip back to the containing structure. */
2050 if (TREE_CODE (DECL_SIZE_UNIT (field)) == INTEGER_CST
2051 && compare_tree_int (DECL_SIZE_UNIT (field), size) >= 0
2052 && INTVAL (memoffset) >= 0)
2055 if (! host_integerp (offset, 1))
2061 expr = TREE_OPERAND (expr, 0);
2063 = (GEN_INT (INTVAL (memoffset)
2064 + tree_low_cst (offset, 1)
2065 + (tree_low_cst (DECL_FIELD_BIT_OFFSET (field), 1)
2068 /* Similarly for the decl. */
2069 else if (DECL_P (expr)
2070 && DECL_SIZE_UNIT (expr)
2071 && TREE_CODE (DECL_SIZE_UNIT (expr)) == INTEGER_CST
2072 && compare_tree_int (DECL_SIZE_UNIT (expr), size) >= 0
2073 && (! memoffset || INTVAL (memoffset) >= 0))
2077 /* The widened memory access overflows the expression, which means
2078 that it could alias another expression. Zap it. */
2085 memoffset = NULL_RTX;
2087 /* The widened memory may alias other stuff, so zap the alias set. */
2088 /* ??? Maybe use get_alias_set on any remaining expression. */
2090 MEM_ATTRS (new) = get_mem_attrs (0, expr, memoffset, GEN_INT (size),
2091 MEM_ALIGN (new), mode);
2096 /* Return a newly created CODE_LABEL rtx with a unique label number. */
2099 gen_label_rtx (void)
2101 return gen_rtx_CODE_LABEL (VOIDmode, 0, NULL_RTX, NULL_RTX,
2102 NULL, label_num++, NULL);
2105 /* For procedure integration. */
2107 /* Install new pointers to the first and last insns in the chain.
2108 Also, set cur_insn_uid to one higher than the last in use.
2109 Used for an inline-procedure after copying the insn chain. */
2112 set_new_first_and_last_insn (rtx first, rtx last)
2120 for (insn = first; insn; insn = NEXT_INSN (insn))
2121 cur_insn_uid = MAX (cur_insn_uid, INSN_UID (insn));
2126 /* Go through all the RTL insn bodies and copy any invalid shared
2127 structure. This routine should only be called once. */
2130 unshare_all_rtl_1 (rtx insn)
2132 /* Unshare just about everything else. */
2133 unshare_all_rtl_in_chain (insn);
2135 /* Make sure the addresses of stack slots found outside the insn chain
2136 (such as, in DECL_RTL of a variable) are not shared
2137 with the insn chain.
2139 This special care is necessary when the stack slot MEM does not
2140 actually appear in the insn chain. If it does appear, its address
2141 is unshared from all else at that point. */
2142 stack_slot_list = copy_rtx_if_shared (stack_slot_list);
2145 /* Go through all the RTL insn bodies and copy any invalid shared
2146 structure, again. This is a fairly expensive thing to do so it
2147 should be done sparingly. */
2150 unshare_all_rtl_again (rtx insn)
2155 for (p = insn; p; p = NEXT_INSN (p))
2158 reset_used_flags (PATTERN (p));
2159 reset_used_flags (REG_NOTES (p));
2162 /* Make sure that virtual stack slots are not shared. */
2163 reset_used_decls (DECL_INITIAL (cfun->decl));
2165 /* Make sure that virtual parameters are not shared. */
2166 for (decl = DECL_ARGUMENTS (cfun->decl); decl; decl = TREE_CHAIN (decl))
2167 reset_used_flags (DECL_RTL (decl));
2169 reset_used_flags (stack_slot_list);
2171 unshare_all_rtl_1 (insn);
2175 unshare_all_rtl (void)
2177 unshare_all_rtl_1 (get_insns ());
2181 struct tree_opt_pass pass_unshare_all_rtl =
2183 "unshare", /* name */
2185 unshare_all_rtl, /* execute */
2188 0, /* static_pass_number */
2190 0, /* properties_required */
2191 0, /* properties_provided */
2192 0, /* properties_destroyed */
2193 0, /* todo_flags_start */
2194 TODO_dump_func, /* todo_flags_finish */
2199 /* Check that ORIG is not marked when it should not be and mark ORIG as in use,
2200 Recursively does the same for subexpressions. */
2203 verify_rtx_sharing (rtx orig, rtx insn)
2208 const char *format_ptr;
2213 code = GET_CODE (x);
2215 /* These types may be freely shared. */
2230 /* SCRATCH must be shared because they represent distinct values. */
2232 if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
2237 if (shared_const_p (orig))
2242 /* A MEM is allowed to be shared if its address is constant. */
2243 if (CONSTANT_ADDRESS_P (XEXP (x, 0))
2244 || reload_completed || reload_in_progress)
2253 /* This rtx may not be shared. If it has already been seen,
2254 replace it with a copy of itself. */
2255 #ifdef ENABLE_CHECKING
2256 if (RTX_FLAG (x, used))
2258 error ("invalid rtl sharing found in the insn");
2260 error ("shared rtx");
2262 internal_error ("internal consistency failure");
2265 gcc_assert (!RTX_FLAG (x, used));
2267 RTX_FLAG (x, used) = 1;
2269 /* Now scan the subexpressions recursively. */
2271 format_ptr = GET_RTX_FORMAT (code);
2273 for (i = 0; i < GET_RTX_LENGTH (code); i++)
2275 switch (*format_ptr++)
2278 verify_rtx_sharing (XEXP (x, i), insn);
2282 if (XVEC (x, i) != NULL)
2285 int len = XVECLEN (x, i);
2287 for (j = 0; j < len; j++)
2289 /* We allow sharing of ASM_OPERANDS inside single
2291 if (j && GET_CODE (XVECEXP (x, i, j)) == SET
2292 && (GET_CODE (SET_SRC (XVECEXP (x, i, j)))
2294 verify_rtx_sharing (SET_DEST (XVECEXP (x, i, j)), insn);
2296 verify_rtx_sharing (XVECEXP (x, i, j), insn);
2305 /* Go through all the RTL insn bodies and check that there is no unexpected
2306 sharing in between the subexpressions. */
2309 verify_rtl_sharing (void)
2313 for (p = get_insns (); p; p = NEXT_INSN (p))
2316 reset_used_flags (PATTERN (p));
2317 reset_used_flags (REG_NOTES (p));
2318 if (GET_CODE (PATTERN (p)) == SEQUENCE)
2321 rtx q, sequence = PATTERN (p);
2323 for (i = 0; i < XVECLEN (sequence, 0); i++)
2325 q = XVECEXP (sequence, 0, i);
2326 gcc_assert (INSN_P (q));
2327 reset_used_flags (PATTERN (q));
2328 reset_used_flags (REG_NOTES (q));
2333 for (p = get_insns (); p; p = NEXT_INSN (p))
2336 verify_rtx_sharing (PATTERN (p), p);
2337 verify_rtx_sharing (REG_NOTES (p), p);
2341 /* Go through all the RTL insn bodies and copy any invalid shared structure.
2342 Assumes the mark bits are cleared at entry. */
2345 unshare_all_rtl_in_chain (rtx insn)
2347 for (; insn; insn = NEXT_INSN (insn))
2350 PATTERN (insn) = copy_rtx_if_shared (PATTERN (insn));
2351 REG_NOTES (insn) = copy_rtx_if_shared (REG_NOTES (insn));
2355 /* Go through all virtual stack slots of a function and mark them as
2358 reset_used_decls (tree blk)
2363 for (t = BLOCK_VARS (blk); t; t = TREE_CHAIN (t))
2364 if (DECL_RTL_SET_P (t))
2365 reset_used_flags (DECL_RTL (t));
2367 /* Now process sub-blocks. */
2368 for (t = BLOCK_SUBBLOCKS (blk); t; t = TREE_CHAIN (t))
2369 reset_used_decls (t);
2372 /* Mark ORIG as in use, and return a copy of it if it was already in use.
2373 Recursively does the same for subexpressions. Uses
2374 copy_rtx_if_shared_1 to reduce stack space. */
2377 copy_rtx_if_shared (rtx orig)
2379 copy_rtx_if_shared_1 (&orig);
2383 /* Mark *ORIG1 as in use, and set it to a copy of it if it was already in
2384 use. Recursively does the same for subexpressions. */
2387 copy_rtx_if_shared_1 (rtx *orig1)
2393 const char *format_ptr;
2397 /* Repeat is used to turn tail-recursion into iteration. */
2404 code = GET_CODE (x);
2406 /* These types may be freely shared. */
2420 /* SCRATCH must be shared because they represent distinct values. */
2423 if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
2428 if (shared_const_p (x))
2437 /* The chain of insns is not being copied. */
2444 /* This rtx may not be shared. If it has already been seen,
2445 replace it with a copy of itself. */
2447 if (RTX_FLAG (x, used))
2449 x = shallow_copy_rtx (x);
2452 RTX_FLAG (x, used) = 1;
2454 /* Now scan the subexpressions recursively.
2455 We can store any replaced subexpressions directly into X
2456 since we know X is not shared! Any vectors in X
2457 must be copied if X was copied. */
2459 format_ptr = GET_RTX_FORMAT (code);
2460 length = GET_RTX_LENGTH (code);
2463 for (i = 0; i < length; i++)
2465 switch (*format_ptr++)
2469 copy_rtx_if_shared_1 (last_ptr);
2470 last_ptr = &XEXP (x, i);
2474 if (XVEC (x, i) != NULL)
2477 int len = XVECLEN (x, i);
2479 /* Copy the vector iff I copied the rtx and the length
2481 if (copied && len > 0)
2482 XVEC (x, i) = gen_rtvec_v (len, XVEC (x, i)->elem);
2484 /* Call recursively on all inside the vector. */
2485 for (j = 0; j < len; j++)
2488 copy_rtx_if_shared_1 (last_ptr);
2489 last_ptr = &XVECEXP (x, i, j);
2504 /* Clear all the USED bits in X to allow copy_rtx_if_shared to be used
2505 to look for shared sub-parts. */
2508 reset_used_flags (rtx x)
2512 const char *format_ptr;
2515 /* Repeat is used to turn tail-recursion into iteration. */
2520 code = GET_CODE (x);
2522 /* These types may be freely shared so we needn't do any resetting
2543 /* The chain of insns is not being copied. */
2550 RTX_FLAG (x, used) = 0;
2552 format_ptr = GET_RTX_FORMAT (code);
2553 length = GET_RTX_LENGTH (code);
2555 for (i = 0; i < length; i++)
2557 switch (*format_ptr++)
2565 reset_used_flags (XEXP (x, i));
2569 for (j = 0; j < XVECLEN (x, i); j++)
2570 reset_used_flags (XVECEXP (x, i, j));
2576 /* Set all the USED bits in X to allow copy_rtx_if_shared to be used
2577 to look for shared sub-parts. */
2580 set_used_flags (rtx x)
2584 const char *format_ptr;
2589 code = GET_CODE (x);
2591 /* These types may be freely shared so we needn't do any resetting
2612 /* The chain of insns is not being copied. */
2619 RTX_FLAG (x, used) = 1;
2621 format_ptr = GET_RTX_FORMAT (code);
2622 for (i = 0; i < GET_RTX_LENGTH (code); i++)
2624 switch (*format_ptr++)
2627 set_used_flags (XEXP (x, i));
2631 for (j = 0; j < XVECLEN (x, i); j++)
2632 set_used_flags (XVECEXP (x, i, j));
2638 /* Copy X if necessary so that it won't be altered by changes in OTHER.
2639 Return X or the rtx for the pseudo reg the value of X was copied into.
2640 OTHER must be valid as a SET_DEST. */
2643 make_safe_from (rtx x, rtx other)
2646 switch (GET_CODE (other))
2649 other = SUBREG_REG (other);
2651 case STRICT_LOW_PART:
2654 other = XEXP (other, 0);
2663 && GET_CODE (x) != SUBREG)
2665 && (REGNO (other) < FIRST_PSEUDO_REGISTER
2666 || reg_mentioned_p (other, x))))
2668 rtx temp = gen_reg_rtx (GET_MODE (x));
2669 emit_move_insn (temp, x);
2675 /* Emission of insns (adding them to the doubly-linked list). */
2677 /* Return the first insn of the current sequence or current function. */
2685 /* Specify a new insn as the first in the chain. */
2688 set_first_insn (rtx insn)
2690 gcc_assert (!PREV_INSN (insn));
2694 /* Return the last insn emitted in current sequence or current function. */
2697 get_last_insn (void)
2702 /* Specify a new insn as the last in the chain. */
2705 set_last_insn (rtx insn)
2707 gcc_assert (!NEXT_INSN (insn));
2711 /* Return the last insn emitted, even if it is in a sequence now pushed. */
2714 get_last_insn_anywhere (void)
2716 struct sequence_stack *stack;
2719 for (stack = seq_stack; stack; stack = stack->next)
2720 if (stack->last != 0)
2725 /* Return the first nonnote insn emitted in current sequence or current
2726 function. This routine looks inside SEQUENCEs. */
2729 get_first_nonnote_insn (void)
2731 rtx insn = first_insn;
2736 for (insn = next_insn (insn);
2737 insn && NOTE_P (insn);
2738 insn = next_insn (insn))
2742 if (NONJUMP_INSN_P (insn)
2743 && GET_CODE (PATTERN (insn)) == SEQUENCE)
2744 insn = XVECEXP (PATTERN (insn), 0, 0);
2751 /* Return the last nonnote insn emitted in current sequence or current
2752 function. This routine looks inside SEQUENCEs. */
2755 get_last_nonnote_insn (void)
2757 rtx insn = last_insn;
2762 for (insn = previous_insn (insn);
2763 insn && NOTE_P (insn);
2764 insn = previous_insn (insn))
2768 if (NONJUMP_INSN_P (insn)
2769 && GET_CODE (PATTERN (insn)) == SEQUENCE)
2770 insn = XVECEXP (PATTERN (insn), 0,
2771 XVECLEN (PATTERN (insn), 0) - 1);
2778 /* Return a number larger than any instruction's uid in this function. */
2783 return cur_insn_uid;
2786 /* Return the next insn. If it is a SEQUENCE, return the first insn
2790 next_insn (rtx insn)
2794 insn = NEXT_INSN (insn);
2795 if (insn && NONJUMP_INSN_P (insn)
2796 && GET_CODE (PATTERN (insn)) == SEQUENCE)
2797 insn = XVECEXP (PATTERN (insn), 0, 0);
2803 /* Return the previous insn. If it is a SEQUENCE, return the last insn
2807 previous_insn (rtx insn)
2811 insn = PREV_INSN (insn);
2812 if (insn && NONJUMP_INSN_P (insn)
2813 && GET_CODE (PATTERN (insn)) == SEQUENCE)
2814 insn = XVECEXP (PATTERN (insn), 0, XVECLEN (PATTERN (insn), 0) - 1);
2820 /* Return the next insn after INSN that is not a NOTE. This routine does not
2821 look inside SEQUENCEs. */
2824 next_nonnote_insn (rtx insn)
2828 insn = NEXT_INSN (insn);
2829 if (insn == 0 || !NOTE_P (insn))
2836 /* Return the previous insn before INSN that is not a NOTE. This routine does
2837 not look inside SEQUENCEs. */
2840 prev_nonnote_insn (rtx insn)
2844 insn = PREV_INSN (insn);
2845 if (insn == 0 || !NOTE_P (insn))
2852 /* Return the next INSN, CALL_INSN or JUMP_INSN after INSN;
2853 or 0, if there is none. This routine does not look inside
2857 next_real_insn (rtx insn)
2861 insn = NEXT_INSN (insn);
2862 if (insn == 0 || INSN_P (insn))
2869 /* Return the last INSN, CALL_INSN or JUMP_INSN before INSN;
2870 or 0, if there is none. This routine does not look inside
2874 prev_real_insn (rtx insn)
2878 insn = PREV_INSN (insn);
2879 if (insn == 0 || INSN_P (insn))
2886 /* Return the last CALL_INSN in the current list, or 0 if there is none.
2887 This routine does not look inside SEQUENCEs. */
2890 last_call_insn (void)
2894 for (insn = get_last_insn ();
2895 insn && !CALL_P (insn);
2896 insn = PREV_INSN (insn))
2902 /* Find the next insn after INSN that really does something. This routine
2903 does not look inside SEQUENCEs. Until reload has completed, this is the
2904 same as next_real_insn. */
2907 active_insn_p (rtx insn)
2909 return (CALL_P (insn) || JUMP_P (insn)
2910 || (NONJUMP_INSN_P (insn)
2911 && (! reload_completed
2912 || (GET_CODE (PATTERN (insn)) != USE
2913 && GET_CODE (PATTERN (insn)) != CLOBBER))));
2917 next_active_insn (rtx insn)
2921 insn = NEXT_INSN (insn);
2922 if (insn == 0 || active_insn_p (insn))
2929 /* Find the last insn before INSN that really does something. This routine
2930 does not look inside SEQUENCEs. Until reload has completed, this is the
2931 same as prev_real_insn. */
2934 prev_active_insn (rtx insn)
2938 insn = PREV_INSN (insn);
2939 if (insn == 0 || active_insn_p (insn))
2946 /* Return the next CODE_LABEL after the insn INSN, or 0 if there is none. */
2949 next_label (rtx insn)
2953 insn = NEXT_INSN (insn);
2954 if (insn == 0 || LABEL_P (insn))
2961 /* Return the last CODE_LABEL before the insn INSN, or 0 if there is none. */
2964 prev_label (rtx insn)
2968 insn = PREV_INSN (insn);
2969 if (insn == 0 || LABEL_P (insn))
2976 /* Return the last label to mark the same position as LABEL. Return null
2977 if LABEL itself is null. */
2980 skip_consecutive_labels (rtx label)
2984 for (insn = label; insn != 0 && !INSN_P (insn); insn = NEXT_INSN (insn))
2992 /* INSN uses CC0 and is being moved into a delay slot. Set up REG_CC_SETTER
2993 and REG_CC_USER notes so we can find it. */
2996 link_cc0_insns (rtx insn)
2998 rtx user = next_nonnote_insn (insn);
3000 if (NONJUMP_INSN_P (user) && GET_CODE (PATTERN (user)) == SEQUENCE)
3001 user = XVECEXP (PATTERN (user), 0, 0);
3003 REG_NOTES (user) = gen_rtx_INSN_LIST (REG_CC_SETTER, insn,
3005 REG_NOTES (insn) = gen_rtx_INSN_LIST (REG_CC_USER, user, REG_NOTES (insn));
3008 /* Return the next insn that uses CC0 after INSN, which is assumed to
3009 set it. This is the inverse of prev_cc0_setter (i.e., prev_cc0_setter
3010 applied to the result of this function should yield INSN).
3012 Normally, this is simply the next insn. However, if a REG_CC_USER note
3013 is present, it contains the insn that uses CC0.
3015 Return 0 if we can't find the insn. */
3018 next_cc0_user (rtx insn)
3020 rtx note = find_reg_note (insn, REG_CC_USER, NULL_RTX);
3023 return XEXP (note, 0);
3025 insn = next_nonnote_insn (insn);
3026 if (insn && NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE)
3027 insn = XVECEXP (PATTERN (insn), 0, 0);
3029 if (insn && INSN_P (insn) && reg_mentioned_p (cc0_rtx, PATTERN (insn)))
3035 /* Find the insn that set CC0 for INSN. Unless INSN has a REG_CC_SETTER
3036 note, it is the previous insn. */
3039 prev_cc0_setter (rtx insn)
3041 rtx note = find_reg_note (insn, REG_CC_SETTER, NULL_RTX);
3044 return XEXP (note, 0);
3046 insn = prev_nonnote_insn (insn);
3047 gcc_assert (sets_cc0_p (PATTERN (insn)));
3054 /* Find a RTX_AUTOINC class rtx which matches DATA. */
3057 find_auto_inc (rtx *xp, void *data)
3062 if (GET_RTX_CLASS (GET_CODE (x)) != RTX_AUTOINC)
3065 switch (GET_CODE (x))
3073 if (rtx_equal_p (reg, XEXP (x, 0)))
3084 /* Increment the label uses for all labels present in rtx. */
3087 mark_label_nuses (rtx x)
3093 code = GET_CODE (x);
3094 if (code == LABEL_REF && LABEL_P (XEXP (x, 0)))
3095 LABEL_NUSES (XEXP (x, 0))++;
3097 fmt = GET_RTX_FORMAT (code);
3098 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3101 mark_label_nuses (XEXP (x, i));
3102 else if (fmt[i] == 'E')
3103 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3104 mark_label_nuses (XVECEXP (x, i, j));
3109 /* Try splitting insns that can be split for better scheduling.
3110 PAT is the pattern which might split.
3111 TRIAL is the insn providing PAT.
3112 LAST is nonzero if we should return the last insn of the sequence produced.
3114 If this routine succeeds in splitting, it returns the first or last
3115 replacement insn depending on the value of LAST. Otherwise, it
3116 returns TRIAL. If the insn to be returned can be split, it will be. */
3119 try_split (rtx pat, rtx trial, int last)
3121 rtx before = PREV_INSN (trial);
3122 rtx after = NEXT_INSN (trial);
3123 int has_barrier = 0;
3127 rtx insn_last, insn;
3130 if (any_condjump_p (trial)
3131 && (note = find_reg_note (trial, REG_BR_PROB, 0)))
3132 split_branch_probability = INTVAL (XEXP (note, 0));
3133 probability = split_branch_probability;
3135 seq = split_insns (pat, trial);
3137 split_branch_probability = -1;
3139 /* If we are splitting a JUMP_INSN, it might be followed by a BARRIER.
3140 We may need to handle this specially. */
3141 if (after && BARRIER_P (after))
3144 after = NEXT_INSN (after);
3150 /* Avoid infinite loop if any insn of the result matches
3151 the original pattern. */
3155 if (INSN_P (insn_last)
3156 && rtx_equal_p (PATTERN (insn_last), pat))
3158 if (!NEXT_INSN (insn_last))
3160 insn_last = NEXT_INSN (insn_last);
3163 /* We will be adding the new sequence to the function. The splitters
3164 may have introduced invalid RTL sharing, so unshare the sequence now. */
3165 unshare_all_rtl_in_chain (seq);
3168 for (insn = insn_last; insn ; insn = PREV_INSN (insn))
3172 mark_jump_label (PATTERN (insn), insn, 0);
3174 if (probability != -1
3175 && any_condjump_p (insn)
3176 && !find_reg_note (insn, REG_BR_PROB, 0))
3178 /* We can preserve the REG_BR_PROB notes only if exactly
3179 one jump is created, otherwise the machine description
3180 is responsible for this step using
3181 split_branch_probability variable. */
3182 gcc_assert (njumps == 1);
3184 = gen_rtx_EXPR_LIST (REG_BR_PROB,
3185 GEN_INT (probability),
3191 /* If we are splitting a CALL_INSN, look for the CALL_INSN
3192 in SEQ and copy our CALL_INSN_FUNCTION_USAGE to it. */
3195 for (insn = insn_last; insn ; insn = PREV_INSN (insn))
3198 rtx *p = &CALL_INSN_FUNCTION_USAGE (insn);
3201 *p = CALL_INSN_FUNCTION_USAGE (trial);
3202 SIBLING_CALL_P (insn) = SIBLING_CALL_P (trial);
3206 /* Copy notes, particularly those related to the CFG. */
3207 for (note = REG_NOTES (trial); note; note = XEXP (note, 1))
3209 switch (REG_NOTE_KIND (note))
3212 for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn))
3215 || (flag_non_call_exceptions && INSN_P (insn)
3216 && may_trap_p (PATTERN (insn))))
3218 = gen_rtx_EXPR_LIST (REG_EH_REGION,
3226 for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn))
3230 = gen_rtx_EXPR_LIST (REG_NOTE_KIND (note),
3236 case REG_NON_LOCAL_GOTO:
3237 for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn))
3241 = gen_rtx_EXPR_LIST (REG_NOTE_KIND (note),
3249 for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn))
3251 rtx reg = XEXP (note, 0);
3252 if (!FIND_REG_INC_NOTE (insn, reg)
3253 && for_each_rtx (&PATTERN (insn), find_auto_inc, reg) > 0)
3254 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, reg,
3265 /* If there are LABELS inside the split insns increment the
3266 usage count so we don't delete the label. */
3267 if (NONJUMP_INSN_P (trial))
3270 while (insn != NULL_RTX)
3272 if (NONJUMP_INSN_P (insn))
3273 mark_label_nuses (PATTERN (insn));
3275 insn = PREV_INSN (insn);
3279 tem = emit_insn_after_setloc (seq, trial, INSN_LOCATOR (trial));
3281 delete_insn (trial);
3283 emit_barrier_after (tem);
3285 /* Recursively call try_split for each new insn created; by the
3286 time control returns here that insn will be fully split, so
3287 set LAST and continue from the insn after the one returned.
3288 We can't use next_active_insn here since AFTER may be a note.
3289 Ignore deleted insns, which can be occur if not optimizing. */
3290 for (tem = NEXT_INSN (before); tem != after; tem = NEXT_INSN (tem))
3291 if (! INSN_DELETED_P (tem) && INSN_P (tem))
3292 tem = try_split (PATTERN (tem), tem, 1);
3294 /* Return either the first or the last insn, depending on which was
3297 ? (after ? PREV_INSN (after) : last_insn)
3298 : NEXT_INSN (before);
3301 /* Make and return an INSN rtx, initializing all its slots.
3302 Store PATTERN in the pattern slots. */
3305 make_insn_raw (rtx pattern)
3309 insn = rtx_alloc (INSN);
3311 INSN_UID (insn) = cur_insn_uid++;
3312 PATTERN (insn) = pattern;
3313 INSN_CODE (insn) = -1;
3314 REG_NOTES (insn) = NULL;
3315 INSN_LOCATOR (insn) = curr_insn_locator ();
3316 BLOCK_FOR_INSN (insn) = NULL;
3318 #ifdef ENABLE_RTL_CHECKING
3321 && (returnjump_p (insn)
3322 || (GET_CODE (insn) == SET
3323 && SET_DEST (insn) == pc_rtx)))
3325 warning (0, "ICE: emit_insn used where emit_jump_insn needed:\n");
3333 /* Like `make_insn_raw' but make a JUMP_INSN instead of an insn. */
3336 make_jump_insn_raw (rtx pattern)
3340 insn = rtx_alloc (JUMP_INSN);
3341 INSN_UID (insn) = cur_insn_uid++;
3343 PATTERN (insn) = pattern;
3344 INSN_CODE (insn) = -1;
3345 REG_NOTES (insn) = NULL;
3346 JUMP_LABEL (insn) = NULL;
3347 INSN_LOCATOR (insn) = curr_insn_locator ();
3348 BLOCK_FOR_INSN (insn) = NULL;
3353 /* Like `make_insn_raw' but make a CALL_INSN instead of an insn. */
3356 make_call_insn_raw (rtx pattern)
3360 insn = rtx_alloc (CALL_INSN);
3361 INSN_UID (insn) = cur_insn_uid++;
3363 PATTERN (insn) = pattern;
3364 INSN_CODE (insn) = -1;
3365 REG_NOTES (insn) = NULL;
3366 CALL_INSN_FUNCTION_USAGE (insn) = NULL;
3367 INSN_LOCATOR (insn) = curr_insn_locator ();
3368 BLOCK_FOR_INSN (insn) = NULL;
3373 /* Add INSN to the end of the doubly-linked list.
3374 INSN may be an INSN, JUMP_INSN, CALL_INSN, CODE_LABEL, BARRIER or NOTE. */
3379 PREV_INSN (insn) = last_insn;
3380 NEXT_INSN (insn) = 0;
3382 if (NULL != last_insn)
3383 NEXT_INSN (last_insn) = insn;
3385 if (NULL == first_insn)
3391 /* Add INSN into the doubly-linked list after insn AFTER. This and
3392 the next should be the only functions called to insert an insn once
3393 delay slots have been filled since only they know how to update a
3397 add_insn_after (rtx insn, rtx after, basic_block bb)
3399 rtx next = NEXT_INSN (after);
3401 gcc_assert (!optimize || !INSN_DELETED_P (after));
3403 NEXT_INSN (insn) = next;
3404 PREV_INSN (insn) = after;
3408 PREV_INSN (next) = insn;
3409 if (NONJUMP_INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE)
3410 PREV_INSN (XVECEXP (PATTERN (next), 0, 0)) = insn;
3412 else if (last_insn == after)
3416 struct sequence_stack *stack = seq_stack;
3417 /* Scan all pending sequences too. */
3418 for (; stack; stack = stack->next)
3419 if (after == stack->last)
3428 if (!BARRIER_P (after)
3429 && !BARRIER_P (insn)
3430 && (bb = BLOCK_FOR_INSN (after)))
3432 set_block_for_insn (insn, bb);
3434 df_insn_rescan (insn);
3435 /* Should not happen as first in the BB is always
3436 either NOTE or LABEL. */
3437 if (BB_END (bb) == after
3438 /* Avoid clobbering of structure when creating new BB. */
3439 && !BARRIER_P (insn)
3440 && !NOTE_INSN_BASIC_BLOCK_P (insn))
3444 NEXT_INSN (after) = insn;
3445 if (NONJUMP_INSN_P (after) && GET_CODE (PATTERN (after)) == SEQUENCE)
3447 rtx sequence = PATTERN (after);
3448 NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = insn;
3452 /* Add INSN into the doubly-linked list before insn BEFORE. This and
3453 the previous should be the only functions called to insert an insn
3454 once delay slots have been filled since only they know how to
3455 update a SEQUENCE. If BB is NULL, an attempt is made to infer the
3459 add_insn_before (rtx insn, rtx before, basic_block bb)
3461 rtx prev = PREV_INSN (before);
3463 gcc_assert (!optimize || !INSN_DELETED_P (before));
3465 PREV_INSN (insn) = prev;
3466 NEXT_INSN (insn) = before;
3470 NEXT_INSN (prev) = insn;
3471 if (NONJUMP_INSN_P (prev) && GET_CODE (PATTERN (prev)) == SEQUENCE)
3473 rtx sequence = PATTERN (prev);
3474 NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = insn;
3477 else if (first_insn == before)
3481 struct sequence_stack *stack = seq_stack;
3482 /* Scan all pending sequences too. */
3483 for (; stack; stack = stack->next)
3484 if (before == stack->first)
3486 stack->first = insn;
3494 && !BARRIER_P (before)
3495 && !BARRIER_P (insn))
3496 bb = BLOCK_FOR_INSN (before);
3500 set_block_for_insn (insn, bb);
3502 df_insn_rescan (insn);
3503 /* Should not happen as first in the BB is always either NOTE or
3505 gcc_assert (BB_HEAD (bb) != insn
3506 /* Avoid clobbering of structure when creating new BB. */
3508 || NOTE_INSN_BASIC_BLOCK_P (insn));
3511 PREV_INSN (before) = insn;
3512 if (NONJUMP_INSN_P (before) && GET_CODE (PATTERN (before)) == SEQUENCE)
3513 PREV_INSN (XVECEXP (PATTERN (before), 0, 0)) = insn;
3517 /* Replace insn with an deleted instruction note. */
3519 void set_insn_deleted (rtx insn)
3521 df_insn_delete (BLOCK_FOR_INSN (insn), INSN_UID (insn));
3522 PUT_CODE (insn, NOTE);
3523 NOTE_KIND (insn) = NOTE_INSN_DELETED;
3527 /* Remove an insn from its doubly-linked list. This function knows how
3528 to handle sequences. */
3530 remove_insn (rtx insn)
3532 rtx next = NEXT_INSN (insn);
3533 rtx prev = PREV_INSN (insn);
3536 /* Later in the code, the block will be marked dirty. */
3537 df_insn_delete (NULL, INSN_UID (insn));
3541 NEXT_INSN (prev) = next;
3542 if (NONJUMP_INSN_P (prev) && GET_CODE (PATTERN (prev)) == SEQUENCE)
3544 rtx sequence = PATTERN (prev);
3545 NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = next;
3548 else if (first_insn == insn)
3552 struct sequence_stack *stack = seq_stack;
3553 /* Scan all pending sequences too. */
3554 for (; stack; stack = stack->next)
3555 if (insn == stack->first)
3557 stack->first = next;
3566 PREV_INSN (next) = prev;
3567 if (NONJUMP_INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE)
3568 PREV_INSN (XVECEXP (PATTERN (next), 0, 0)) = prev;
3570 else if (last_insn == insn)
3574 struct sequence_stack *stack = seq_stack;
3575 /* Scan all pending sequences too. */
3576 for (; stack; stack = stack->next)
3577 if (insn == stack->last)
3585 if (!BARRIER_P (insn)
3586 && (bb = BLOCK_FOR_INSN (insn)))
3589 df_set_bb_dirty (bb);
3590 if (BB_HEAD (bb) == insn)
3592 /* Never ever delete the basic block note without deleting whole
3594 gcc_assert (!NOTE_P (insn));
3595 BB_HEAD (bb) = next;
3597 if (BB_END (bb) == insn)
3602 /* Append CALL_FUSAGE to the CALL_INSN_FUNCTION_USAGE for CALL_INSN. */
3605 add_function_usage_to (rtx call_insn, rtx call_fusage)
3607 gcc_assert (call_insn && CALL_P (call_insn));
3609 /* Put the register usage information on the CALL. If there is already
3610 some usage information, put ours at the end. */
3611 if (CALL_INSN_FUNCTION_USAGE (call_insn))
3615 for (link = CALL_INSN_FUNCTION_USAGE (call_insn); XEXP (link, 1) != 0;
3616 link = XEXP (link, 1))
3619 XEXP (link, 1) = call_fusage;
3622 CALL_INSN_FUNCTION_USAGE (call_insn) = call_fusage;
3625 /* Delete all insns made since FROM.
3626 FROM becomes the new last instruction. */
3629 delete_insns_since (rtx from)
3634 NEXT_INSN (from) = 0;
3638 /* This function is deprecated, please use sequences instead.
3640 Move a consecutive bunch of insns to a different place in the chain.
3641 The insns to be moved are those between FROM and TO.
3642 They are moved to a new position after the insn AFTER.
3643 AFTER must not be FROM or TO or any insn in between.
3645 This function does not know about SEQUENCEs and hence should not be
3646 called after delay-slot filling has been done. */
3649 reorder_insns_nobb (rtx from, rtx to, rtx after)
3651 /* Splice this bunch out of where it is now. */
3652 if (PREV_INSN (from))
3653 NEXT_INSN (PREV_INSN (from)) = NEXT_INSN (to);
3655 PREV_INSN (NEXT_INSN (to)) = PREV_INSN (from);
3656 if (last_insn == to)
3657 last_insn = PREV_INSN (from);
3658 if (first_insn == from)
3659 first_insn = NEXT_INSN (to);
3661 /* Make the new neighbors point to it and it to them. */
3662 if (NEXT_INSN (after))
3663 PREV_INSN (NEXT_INSN (after)) = to;
3665 NEXT_INSN (to) = NEXT_INSN (after);
3666 PREV_INSN (from) = after;
3667 NEXT_INSN (after) = from;
3668 if (after == last_insn)
3672 /* Same as function above, but take care to update BB boundaries. */
3674 reorder_insns (rtx from, rtx to, rtx after)
3676 rtx prev = PREV_INSN (from);
3677 basic_block bb, bb2;
3679 reorder_insns_nobb (from, to, after);
3681 if (!BARRIER_P (after)
3682 && (bb = BLOCK_FOR_INSN (after)))
3685 df_set_bb_dirty (bb);
3687 if (!BARRIER_P (from)
3688 && (bb2 = BLOCK_FOR_INSN (from)))
3690 if (BB_END (bb2) == to)
3691 BB_END (bb2) = prev;
3692 df_set_bb_dirty (bb2);
3695 if (BB_END (bb) == after)
3698 for (x = from; x != NEXT_INSN (to); x = NEXT_INSN (x))
3701 set_block_for_insn (x, bb);
3702 df_insn_change_bb (x);
3708 /* Emit insn(s) of given code and pattern
3709 at a specified place within the doubly-linked list.
3711 All of the emit_foo global entry points accept an object
3712 X which is either an insn list or a PATTERN of a single
3715 There are thus a few canonical ways to generate code and
3716 emit it at a specific place in the instruction stream. For
3717 example, consider the instruction named SPOT and the fact that
3718 we would like to emit some instructions before SPOT. We might
3722 ... emit the new instructions ...
3723 insns_head = get_insns ();
3726 emit_insn_before (insns_head, SPOT);
3728 It used to be common to generate SEQUENCE rtl instead, but that
3729 is a relic of the past which no longer occurs. The reason is that
3730 SEQUENCE rtl results in much fragmented RTL memory since the SEQUENCE
3731 generated would almost certainly die right after it was created. */
3733 /* Make X be output before the instruction BEFORE. */
3736 emit_insn_before_noloc (rtx x, rtx before, basic_block bb)
3741 gcc_assert (before);
3746 switch (GET_CODE (x))
3757 rtx next = NEXT_INSN (insn);
3758 add_insn_before (insn, before, bb);
3764 #ifdef ENABLE_RTL_CHECKING
3771 last = make_insn_raw (x);
3772 add_insn_before (last, before, bb);
3779 /* Make an instruction with body X and code JUMP_INSN
3780 and output it before the instruction BEFORE. */
3783 emit_jump_insn_before_noloc (rtx x, rtx before)
3785 rtx insn, last = NULL_RTX;
3787 gcc_assert (before);
3789 switch (GET_CODE (x))
3800 rtx next = NEXT_INSN (insn);
3801 add_insn_before (insn, before, NULL);
3807 #ifdef ENABLE_RTL_CHECKING
3814 last = make_jump_insn_raw (x);
3815 add_insn_before (last, before, NULL);
3822 /* Make an instruction with body X and code CALL_INSN
3823 and output it before the instruction BEFORE. */
3826 emit_call_insn_before_noloc (rtx x, rtx before)
3828 rtx last = NULL_RTX, insn;
3830 gcc_assert (before);
3832 switch (GET_CODE (x))
3843 rtx next = NEXT_INSN (insn);
3844 add_insn_before (insn, before, NULL);
3850 #ifdef ENABLE_RTL_CHECKING
3857 last = make_call_insn_raw (x);
3858 add_insn_before (last, before, NULL);
3865 /* Make an insn of code BARRIER
3866 and output it before the insn BEFORE. */
3869 emit_barrier_before (rtx before)
3871 rtx insn = rtx_alloc (BARRIER);
3873 INSN_UID (insn) = cur_insn_uid++;
3875 add_insn_before (insn, before, NULL);
3879 /* Emit the label LABEL before the insn BEFORE. */
3882 emit_label_before (rtx label, rtx before)
3884 /* This can be called twice for the same label as a result of the
3885 confusion that follows a syntax error! So make it harmless. */
3886 if (INSN_UID (label) == 0)
3888 INSN_UID (label) = cur_insn_uid++;
3889 add_insn_before (label, before, NULL);
3895 /* Emit a note of subtype SUBTYPE before the insn BEFORE. */
3898 emit_note_before (enum insn_note subtype, rtx before)
3900 rtx note = rtx_alloc (NOTE);
3901 INSN_UID (note) = cur_insn_uid++;
3902 NOTE_KIND (note) = subtype;
3903 BLOCK_FOR_INSN (note) = NULL;
3904 memset (&NOTE_DATA (note), 0, sizeof (NOTE_DATA (note)));
3906 add_insn_before (note, before, NULL);
3910 /* Helper for emit_insn_after, handles lists of instructions
3914 emit_insn_after_1 (rtx first, rtx after, basic_block bb)
3918 if (!bb && !BARRIER_P (after))
3919 bb = BLOCK_FOR_INSN (after);
3923 df_set_bb_dirty (bb);
3924 for (last = first; NEXT_INSN (last); last = NEXT_INSN (last))
3925 if (!BARRIER_P (last))
3927 set_block_for_insn (last, bb);
3928 df_insn_rescan (last);
3930 if (!BARRIER_P (last))
3932 set_block_for_insn (last, bb);
3933 df_insn_rescan (last);
3935 if (BB_END (bb) == after)
3939 for (last = first; NEXT_INSN (last); last = NEXT_INSN (last))
3942 after_after = NEXT_INSN (after);
3944 NEXT_INSN (after) = first;
3945 PREV_INSN (first) = after;
3946 NEXT_INSN (last) = after_after;
3948 PREV_INSN (after_after) = last;
3950 if (after == last_insn)
3955 /* Make X be output after the insn AFTER and set the BB of insn. If
3956 BB is NULL, an attempt is made to infer the BB from AFTER. */
3959 emit_insn_after_noloc (rtx x, rtx after, basic_block bb)
3968 switch (GET_CODE (x))
3976 last = emit_insn_after_1 (x, after, bb);
3979 #ifdef ENABLE_RTL_CHECKING
3986 last = make_insn_raw (x);
3987 add_insn_after (last, after, bb);
3995 /* Make an insn of code JUMP_INSN with body X
3996 and output it after the insn AFTER. */
3999 emit_jump_insn_after_noloc (rtx x, rtx after)
4005 switch (GET_CODE (x))
4013 last = emit_insn_after_1 (x, after, NULL);
4016 #ifdef ENABLE_RTL_CHECKING
4023 last = make_jump_insn_raw (x);
4024 add_insn_after (last, after, NULL);
4031 /* Make an instruction with body X and code CALL_INSN
4032 and output it after the instruction AFTER. */
4035 emit_call_insn_after_noloc (rtx x, rtx after)
4041 switch (GET_CODE (x))
4049 last = emit_insn_after_1 (x, after, NULL);
4052 #ifdef ENABLE_RTL_CHECKING
4059 last = make_call_insn_raw (x);
4060 add_insn_after (last, after, NULL);
4067 /* Make an insn of code BARRIER
4068 and output it after the insn AFTER. */
4071 emit_barrier_after (rtx after)
4073 rtx insn = rtx_alloc (BARRIER);
4075 INSN_UID (insn) = cur_insn_uid++;
4077 add_insn_after (insn, after, NULL);
4081 /* Emit the label LABEL after the insn AFTER. */
4084 emit_label_after (rtx label, rtx after)
4086 /* This can be called twice for the same label
4087 as a result of the confusion that follows a syntax error!
4088 So make it harmless. */
4089 if (INSN_UID (label) == 0)
4091 INSN_UID (label) = cur_insn_uid++;
4092 add_insn_after (label, after, NULL);
4098 /* Emit a note of subtype SUBTYPE after the insn AFTER. */
4101 emit_note_after (enum insn_note subtype, rtx after)
4103 rtx note = rtx_alloc (NOTE);
4104 INSN_UID (note) = cur_insn_uid++;
4105 NOTE_KIND (note) = subtype;
4106 BLOCK_FOR_INSN (note) = NULL;
4107 memset (&NOTE_DATA (note), 0, sizeof (NOTE_DATA (note)));
4108 add_insn_after (note, after, NULL);
4112 /* Like emit_insn_after_noloc, but set INSN_LOCATOR according to SCOPE. */
4114 emit_insn_after_setloc (rtx pattern, rtx after, int loc)
4116 rtx last = emit_insn_after_noloc (pattern, after, NULL);
4118 if (pattern == NULL_RTX || !loc)
4121 after = NEXT_INSN (after);
4124 if (active_insn_p (after) && !INSN_LOCATOR (after))
4125 INSN_LOCATOR (after) = loc;
4128 after = NEXT_INSN (after);
4133 /* Like emit_insn_after_noloc, but set INSN_LOCATOR according to AFTER. */
4135 emit_insn_after (rtx pattern, rtx after)
4138 return emit_insn_after_setloc (pattern, after, INSN_LOCATOR (after));
4140 return emit_insn_after_noloc (pattern, after, NULL);
4143 /* Like emit_jump_insn_after_noloc, but set INSN_LOCATOR according to SCOPE. */
4145 emit_jump_insn_after_setloc (rtx pattern, rtx after, int loc)
4147 rtx last = emit_jump_insn_after_noloc (pattern, after);
4149 if (pattern == NULL_RTX || !loc)
4152 after = NEXT_INSN (after);
4155 if (active_insn_p (after) && !INSN_LOCATOR (after))
4156 INSN_LOCATOR (after) = loc;
4159 after = NEXT_INSN (after);
4164 /* Like emit_jump_insn_after_noloc, but set INSN_LOCATOR according to AFTER. */
4166 emit_jump_insn_after (rtx pattern, rtx after)
4169 return emit_jump_insn_after_setloc (pattern, after, INSN_LOCATOR (after));
4171 return emit_jump_insn_after_noloc (pattern, after);
4174 /* Like emit_call_insn_after_noloc, but set INSN_LOCATOR according to SCOPE. */
4176 emit_call_insn_after_setloc (rtx pattern, rtx after, int loc)
4178 rtx last = emit_call_insn_after_noloc (pattern, after);
4180 if (pattern == NULL_RTX || !loc)
4183 after = NEXT_INSN (after);
4186 if (active_insn_p (after) && !INSN_LOCATOR (after))
4187 INSN_LOCATOR (after) = loc;
4190 after = NEXT_INSN (after);
4195 /* Like emit_call_insn_after_noloc, but set INSN_LOCATOR according to AFTER. */
4197 emit_call_insn_after (rtx pattern, rtx after)
4200 return emit_call_insn_after_setloc (pattern, after, INSN_LOCATOR (after));
4202 return emit_call_insn_after_noloc (pattern, after);
4205 /* Like emit_insn_before_noloc, but set INSN_LOCATOR according to SCOPE. */
4207 emit_insn_before_setloc (rtx pattern, rtx before, int loc)
4209 rtx first = PREV_INSN (before);
4210 rtx last = emit_insn_before_noloc (pattern, before, NULL);
4212 if (pattern == NULL_RTX || !loc)
4216 first = get_insns ();
4218 first = NEXT_INSN (first);
4221 if (active_insn_p (first) && !INSN_LOCATOR (first))
4222 INSN_LOCATOR (first) = loc;
4225 first = NEXT_INSN (first);
4230 /* Like emit_insn_before_noloc, but set INSN_LOCATOR according to BEFORE. */
4232 emit_insn_before (rtx pattern, rtx before)
4234 if (INSN_P (before))
4235 return emit_insn_before_setloc (pattern, before, INSN_LOCATOR (before));
4237 return emit_insn_before_noloc (pattern, before, NULL);
4240 /* like emit_insn_before_noloc, but set insn_locator according to scope. */
4242 emit_jump_insn_before_setloc (rtx pattern, rtx before, int loc)
4244 rtx first = PREV_INSN (before);
4245 rtx last = emit_jump_insn_before_noloc (pattern, before);
4247 if (pattern == NULL_RTX)
4250 first = NEXT_INSN (first);
4253 if (active_insn_p (first) && !INSN_LOCATOR (first))
4254 INSN_LOCATOR (first) = loc;
4257 first = NEXT_INSN (first);
4262 /* Like emit_jump_insn_before_noloc, but set INSN_LOCATOR according to BEFORE. */
4264 emit_jump_insn_before (rtx pattern, rtx before)
4266 if (INSN_P (before))
4267 return emit_jump_insn_before_setloc (pattern, before, INSN_LOCATOR (before));
4269 return emit_jump_insn_before_noloc (pattern, before);
4272 /* like emit_insn_before_noloc, but set insn_locator according to scope. */
4274 emit_call_insn_before_setloc (rtx pattern, rtx before, int loc)
4276 rtx first = PREV_INSN (before);
4277 rtx last = emit_call_insn_before_noloc (pattern, before);
4279 if (pattern == NULL_RTX)
4282 first = NEXT_INSN (first);
4285 if (active_insn_p (first) && !INSN_LOCATOR (first))
4286 INSN_LOCATOR (first) = loc;
4289 first = NEXT_INSN (first);
4294 /* like emit_call_insn_before_noloc,
4295 but set insn_locator according to before. */
4297 emit_call_insn_before (rtx pattern, rtx before)
4299 if (INSN_P (before))
4300 return emit_call_insn_before_setloc (pattern, before, INSN_LOCATOR (before));
4302 return emit_call_insn_before_noloc (pattern, before);
4305 /* Take X and emit it at the end of the doubly-linked
4308 Returns the last insn emitted. */
4313 rtx last = last_insn;
4319 switch (GET_CODE (x))
4330 rtx next = NEXT_INSN (insn);
4337 #ifdef ENABLE_RTL_CHECKING
4344 last = make_insn_raw (x);
4352 /* Make an insn of code JUMP_INSN with pattern X
4353 and add it to the end of the doubly-linked list. */
4356 emit_jump_insn (rtx x)
4358 rtx last = NULL_RTX, insn;
4360 switch (GET_CODE (x))
4371 rtx next = NEXT_INSN (insn);
4378 #ifdef ENABLE_RTL_CHECKING
4385 last = make_jump_insn_raw (x);
4393 /* Make an insn of code CALL_INSN with pattern X
4394 and add it to the end of the doubly-linked list. */
4397 emit_call_insn (rtx x)
4401 switch (GET_CODE (x))
4409 insn = emit_insn (x);
4412 #ifdef ENABLE_RTL_CHECKING
4419 insn = make_call_insn_raw (x);
4427 /* Add the label LABEL to the end of the doubly-linked list. */
4430 emit_label (rtx label)
4432 /* This can be called twice for the same label
4433 as a result of the confusion that follows a syntax error!
4434 So make it harmless. */
4435 if (INSN_UID (label) == 0)
4437 INSN_UID (label) = cur_insn_uid++;
4443 /* Make an insn of code BARRIER
4444 and add it to the end of the doubly-linked list. */
4449 rtx barrier = rtx_alloc (BARRIER);
4450 INSN_UID (barrier) = cur_insn_uid++;
4455 /* Emit a copy of note ORIG. */
4458 emit_note_copy (rtx orig)
4462 note = rtx_alloc (NOTE);
4464 INSN_UID (note) = cur_insn_uid++;
4465 NOTE_DATA (note) = NOTE_DATA (orig);
4466 NOTE_KIND (note) = NOTE_KIND (orig);
4467 BLOCK_FOR_INSN (note) = NULL;
4473 /* Make an insn of code NOTE or type NOTE_NO
4474 and add it to the end of the doubly-linked list. */
4477 emit_note (enum insn_note kind)
4481 note = rtx_alloc (NOTE);
4482 INSN_UID (note) = cur_insn_uid++;
4483 NOTE_KIND (note) = kind;
4484 memset (&NOTE_DATA (note), 0, sizeof (NOTE_DATA (note)));
4485 BLOCK_FOR_INSN (note) = NULL;
4490 /* Cause next statement to emit a line note even if the line number
4494 force_next_line_note (void)
4496 #ifdef USE_MAPPED_LOCATION
4499 last_location.line = -1;
4503 /* Place a note of KIND on insn INSN with DATUM as the datum. If a
4504 note of this type already exists, remove it first. */
4507 set_unique_reg_note (rtx insn, enum reg_note kind, rtx datum)
4509 rtx note = find_reg_note (insn, kind, NULL_RTX);
4510 rtx new_note = NULL;
4516 /* Don't add REG_EQUAL/REG_EQUIV notes if the insn
4517 has multiple sets (some callers assume single_set
4518 means the insn only has one set, when in fact it
4519 means the insn only has one * useful * set). */
4520 if (GET_CODE (PATTERN (insn)) == PARALLEL && multiple_sets (insn))
4526 /* Don't add ASM_OPERAND REG_EQUAL/REG_EQUIV notes.
4527 It serves no useful purpose and breaks eliminate_regs. */
4528 if (GET_CODE (datum) == ASM_OPERANDS)
4533 XEXP (note, 0) = datum;
4534 df_notes_rescan (insn);
4542 XEXP (note, 0) = datum;
4548 new_note = gen_rtx_EXPR_LIST (kind, datum, REG_NOTES (insn));
4549 REG_NOTES (insn) = new_note;
4555 df_notes_rescan (insn);
4561 return REG_NOTES (insn);
4564 /* Return an indication of which type of insn should have X as a body.
4565 The value is CODE_LABEL, INSN, CALL_INSN or JUMP_INSN. */
4567 static enum rtx_code
4568 classify_insn (rtx x)
4572 if (GET_CODE (x) == CALL)
4574 if (GET_CODE (x) == RETURN)
4576 if (GET_CODE (x) == SET)
4578 if (SET_DEST (x) == pc_rtx)
4580 else if (GET_CODE (SET_SRC (x)) == CALL)
4585 if (GET_CODE (x) == PARALLEL)
4588 for (j = XVECLEN (x, 0) - 1; j >= 0; j--)
4589 if (GET_CODE (XVECEXP (x, 0, j)) == CALL)
4591 else if (GET_CODE (XVECEXP (x, 0, j)) == SET
4592 && SET_DEST (XVECEXP (x, 0, j)) == pc_rtx)
4594 else if (GET_CODE (XVECEXP (x, 0, j)) == SET
4595 && GET_CODE (SET_SRC (XVECEXP (x, 0, j))) == CALL)
4601 /* Emit the rtl pattern X as an appropriate kind of insn.
4602 If X is a label, it is simply added into the insn chain. */
4607 enum rtx_code code = classify_insn (x);
4612 return emit_label (x);
4614 return emit_insn (x);
4617 rtx insn = emit_jump_insn (x);
4618 if (any_uncondjump_p (insn) || GET_CODE (x) == RETURN)
4619 return emit_barrier ();
4623 return emit_call_insn (x);
4629 /* Space for free sequence stack entries. */
4630 static GTY ((deletable)) struct sequence_stack *free_sequence_stack;
4632 /* Begin emitting insns to a sequence. If this sequence will contain
4633 something that might cause the compiler to pop arguments to function
4634 calls (because those pops have previously been deferred; see
4635 INHIBIT_DEFER_POP for more details), use do_pending_stack_adjust
4636 before calling this function. That will ensure that the deferred
4637 pops are not accidentally emitted in the middle of this sequence. */
4640 start_sequence (void)
4642 struct sequence_stack *tem;
4644 if (free_sequence_stack != NULL)
4646 tem = free_sequence_stack;
4647 free_sequence_stack = tem->next;
4650 tem = ggc_alloc (sizeof (struct sequence_stack));
4652 tem->next = seq_stack;
4653 tem->first = first_insn;
4654 tem->last = last_insn;
4662 /* Set up the insn chain starting with FIRST as the current sequence,
4663 saving the previously current one. See the documentation for
4664 start_sequence for more information about how to use this function. */
4667 push_to_sequence (rtx first)
4673 for (last = first; last && NEXT_INSN (last); last = NEXT_INSN (last));
4679 /* Like push_to_sequence, but take the last insn as an argument to avoid
4680 looping through the list. */
4683 push_to_sequence2 (rtx first, rtx last)
4691 /* Set up the outer-level insn chain
4692 as the current sequence, saving the previously current one. */
4695 push_topmost_sequence (void)
4697 struct sequence_stack *stack, *top = NULL;
4701 for (stack = seq_stack; stack; stack = stack->next)
4704 first_insn = top->first;
4705 last_insn = top->last;
4708 /* After emitting to the outer-level insn chain, update the outer-level
4709 insn chain, and restore the previous saved state. */
4712 pop_topmost_sequence (void)
4714 struct sequence_stack *stack, *top = NULL;
4716 for (stack = seq_stack; stack; stack = stack->next)
4719 top->first = first_insn;
4720 top->last = last_insn;
4725 /* After emitting to a sequence, restore previous saved state.
4727 To get the contents of the sequence just made, you must call
4728 `get_insns' *before* calling here.
4730 If the compiler might have deferred popping arguments while
4731 generating this sequence, and this sequence will not be immediately
4732 inserted into the instruction stream, use do_pending_stack_adjust
4733 before calling get_insns. That will ensure that the deferred
4734 pops are inserted into this sequence, and not into some random
4735 location in the instruction stream. See INHIBIT_DEFER_POP for more
4736 information about deferred popping of arguments. */
4741 struct sequence_stack *tem = seq_stack;
4743 first_insn = tem->first;
4744 last_insn = tem->last;
4745 seq_stack = tem->next;
4747 memset (tem, 0, sizeof (*tem));
4748 tem->next = free_sequence_stack;
4749 free_sequence_stack = tem;
4752 /* Return 1 if currently emitting into a sequence. */
4755 in_sequence_p (void)
4757 return seq_stack != 0;
4760 /* Put the various virtual registers into REGNO_REG_RTX. */
4763 init_virtual_regs (struct emit_status *es)
4765 rtx *ptr = es->x_regno_reg_rtx;
4766 ptr[VIRTUAL_INCOMING_ARGS_REGNUM] = virtual_incoming_args_rtx;
4767 ptr[VIRTUAL_STACK_VARS_REGNUM] = virtual_stack_vars_rtx;
4768 ptr[VIRTUAL_STACK_DYNAMIC_REGNUM] = virtual_stack_dynamic_rtx;
4769 ptr[VIRTUAL_OUTGOING_ARGS_REGNUM] = virtual_outgoing_args_rtx;
4770 ptr[VIRTUAL_CFA_REGNUM] = virtual_cfa_rtx;
4774 /* Used by copy_insn_1 to avoid copying SCRATCHes more than once. */
4775 static rtx copy_insn_scratch_in[MAX_RECOG_OPERANDS];
4776 static rtx copy_insn_scratch_out[MAX_RECOG_OPERANDS];
4777 static int copy_insn_n_scratches;
4779 /* When an insn is being copied by copy_insn_1, this is nonzero if we have
4780 copied an ASM_OPERANDS.
4781 In that case, it is the original input-operand vector. */
4782 static rtvec orig_asm_operands_vector;
4784 /* When an insn is being copied by copy_insn_1, this is nonzero if we have
4785 copied an ASM_OPERANDS.
4786 In that case, it is the copied input-operand vector. */
4787 static rtvec copy_asm_operands_vector;
4789 /* Likewise for the constraints vector. */
4790 static rtvec orig_asm_constraints_vector;
4791 static rtvec copy_asm_constraints_vector;
4793 /* Recursively create a new copy of an rtx for copy_insn.
4794 This function differs from copy_rtx in that it handles SCRATCHes and
4795 ASM_OPERANDs properly.
4796 Normally, this function is not used directly; use copy_insn as front end.
4797 However, you could first copy an insn pattern with copy_insn and then use
4798 this function afterwards to properly copy any REG_NOTEs containing
4802 copy_insn_1 (rtx orig)
4807 const char *format_ptr;
4809 code = GET_CODE (orig);
4823 if (REG_P (XEXP (orig, 0)) && REGNO (XEXP (orig, 0)) < FIRST_PSEUDO_REGISTER)
4828 for (i = 0; i < copy_insn_n_scratches; i++)
4829 if (copy_insn_scratch_in[i] == orig)
4830 return copy_insn_scratch_out[i];
4834 if (shared_const_p (orig))
4838 /* A MEM with a constant address is not sharable. The problem is that
4839 the constant address may need to be reloaded. If the mem is shared,
4840 then reloading one copy of this mem will cause all copies to appear
4841 to have been reloaded. */
4847 /* Copy the various flags, fields, and other information. We assume
4848 that all fields need copying, and then clear the fields that should
4849 not be copied. That is the sensible default behavior, and forces
4850 us to explicitly document why we are *not* copying a flag. */
4851 copy = shallow_copy_rtx (orig);
4853 /* We do not copy the USED flag, which is used as a mark bit during
4854 walks over the RTL. */
4855 RTX_FLAG (copy, used) = 0;
4857 /* We do not copy JUMP, CALL, or FRAME_RELATED for INSNs. */
4860 RTX_FLAG (copy, jump) = 0;
4861 RTX_FLAG (copy, call) = 0;
4862 RTX_FLAG (copy, frame_related) = 0;
4865 format_ptr = GET_RTX_FORMAT (GET_CODE (copy));
4867 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (copy)); i++)
4868 switch (*format_ptr++)
4871 if (XEXP (orig, i) != NULL)
4872 XEXP (copy, i) = copy_insn_1 (XEXP (orig, i));
4877 if (XVEC (orig, i) == orig_asm_constraints_vector)
4878 XVEC (copy, i) = copy_asm_constraints_vector;
4879 else if (XVEC (orig, i) == orig_asm_operands_vector)
4880 XVEC (copy, i) = copy_asm_operands_vector;
4881 else if (XVEC (orig, i) != NULL)
4883 XVEC (copy, i) = rtvec_alloc (XVECLEN (orig, i));
4884 for (j = 0; j < XVECLEN (copy, i); j++)
4885 XVECEXP (copy, i, j) = copy_insn_1 (XVECEXP (orig, i, j));
4896 /* These are left unchanged. */
4903 if (code == SCRATCH)
4905 i = copy_insn_n_scratches++;
4906 gcc_assert (i < MAX_RECOG_OPERANDS);
4907 copy_insn_scratch_in[i] = orig;
4908 copy_insn_scratch_out[i] = copy;
4910 else if (code == ASM_OPERANDS)
4912 orig_asm_operands_vector = ASM_OPERANDS_INPUT_VEC (orig);
4913 copy_asm_operands_vector = ASM_OPERANDS_INPUT_VEC (copy);
4914 orig_asm_constraints_vector = ASM_OPERANDS_INPUT_CONSTRAINT_VEC (orig);
4915 copy_asm_constraints_vector = ASM_OPERANDS_INPUT_CONSTRAINT_VEC (copy);
4921 /* Create a new copy of an rtx.
4922 This function differs from copy_rtx in that it handles SCRATCHes and
4923 ASM_OPERANDs properly.
4924 INSN doesn't really have to be a full INSN; it could be just the
4927 copy_insn (rtx insn)
4929 copy_insn_n_scratches = 0;
4930 orig_asm_operands_vector = 0;
4931 orig_asm_constraints_vector = 0;
4932 copy_asm_operands_vector = 0;
4933 copy_asm_constraints_vector = 0;
4934 return copy_insn_1 (insn);
4937 /* Initialize data structures and variables in this file
4938 before generating rtl for each function. */
4943 struct function *f = cfun;
4945 f->emit = ggc_alloc (sizeof (struct emit_status));
4949 reg_rtx_no = LAST_VIRTUAL_REGISTER + 1;
4950 last_location = UNKNOWN_LOCATION;
4951 first_label_num = label_num;
4954 /* Init the tables that describe all the pseudo regs. */
4956 f->emit->regno_pointer_align_length = LAST_VIRTUAL_REGISTER + 101;
4958 f->emit->regno_pointer_align
4959 = ggc_alloc_cleared (f->emit->regno_pointer_align_length
4960 * sizeof (unsigned char));
4963 = ggc_alloc (f->emit->regno_pointer_align_length * sizeof (rtx));
4965 /* Put copies of all the hard registers into regno_reg_rtx. */
4966 memcpy (regno_reg_rtx,
4967 static_regno_reg_rtx,
4968 FIRST_PSEUDO_REGISTER * sizeof (rtx));
4970 /* Put copies of all the virtual register rtx into regno_reg_rtx. */
4971 init_virtual_regs (f->emit);
4973 /* Indicate that the virtual registers and stack locations are
4975 REG_POINTER (stack_pointer_rtx) = 1;
4976 REG_POINTER (frame_pointer_rtx) = 1;
4977 REG_POINTER (hard_frame_pointer_rtx) = 1;
4978 REG_POINTER (arg_pointer_rtx) = 1;
4980 REG_POINTER (virtual_incoming_args_rtx) = 1;
4981 REG_POINTER (virtual_stack_vars_rtx) = 1;
4982 REG_POINTER (virtual_stack_dynamic_rtx) = 1;
4983 REG_POINTER (virtual_outgoing_args_rtx) = 1;
4984 REG_POINTER (virtual_cfa_rtx) = 1;
4986 #ifdef STACK_BOUNDARY
4987 REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = STACK_BOUNDARY;
4988 REGNO_POINTER_ALIGN (FRAME_POINTER_REGNUM) = STACK_BOUNDARY;
4989 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = STACK_BOUNDARY;
4990 REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = STACK_BOUNDARY;
4992 REGNO_POINTER_ALIGN (VIRTUAL_INCOMING_ARGS_REGNUM) = STACK_BOUNDARY;
4993 REGNO_POINTER_ALIGN (VIRTUAL_STACK_VARS_REGNUM) = STACK_BOUNDARY;
4994 REGNO_POINTER_ALIGN (VIRTUAL_STACK_DYNAMIC_REGNUM) = STACK_BOUNDARY;
4995 REGNO_POINTER_ALIGN (VIRTUAL_OUTGOING_ARGS_REGNUM) = STACK_BOUNDARY;
4996 REGNO_POINTER_ALIGN (VIRTUAL_CFA_REGNUM) = BITS_PER_WORD;
4999 #ifdef INIT_EXPANDERS
5004 /* Generate a vector constant for mode MODE and constant value CONSTANT. */
5007 gen_const_vector (enum machine_mode mode, int constant)
5012 enum machine_mode inner;
5014 units = GET_MODE_NUNITS (mode);
5015 inner = GET_MODE_INNER (mode);
5017 gcc_assert (!DECIMAL_FLOAT_MODE_P (inner));
5019 v = rtvec_alloc (units);
5021 /* We need to call this function after we set the scalar const_tiny_rtx
5023 gcc_assert (const_tiny_rtx[constant][(int) inner]);
5025 for (i = 0; i < units; ++i)
5026 RTVEC_ELT (v, i) = const_tiny_rtx[constant][(int) inner];
5028 tem = gen_rtx_raw_CONST_VECTOR (mode, v);
5032 /* Generate a vector like gen_rtx_raw_CONST_VEC, but use the zero vector when
5033 all elements are zero, and the one vector when all elements are one. */
5035 gen_rtx_CONST_VECTOR (enum machine_mode mode, rtvec v)
5037 enum machine_mode inner = GET_MODE_INNER (mode);
5038 int nunits = GET_MODE_NUNITS (mode);
5042 /* Check to see if all of the elements have the same value. */
5043 x = RTVEC_ELT (v, nunits - 1);
5044 for (i = nunits - 2; i >= 0; i--)
5045 if (RTVEC_ELT (v, i) != x)
5048 /* If the values are all the same, check to see if we can use one of the
5049 standard constant vectors. */
5052 if (x == CONST0_RTX (inner))
5053 return CONST0_RTX (mode);
5054 else if (x == CONST1_RTX (inner))
5055 return CONST1_RTX (mode);
5058 return gen_rtx_raw_CONST_VECTOR (mode, v);
5061 /* Create some permanent unique rtl objects shared between all functions.
5062 LINE_NUMBERS is nonzero if line numbers are to be generated. */
5065 init_emit_once (int line_numbers)
5068 enum machine_mode mode;
5069 enum machine_mode double_mode;
5071 /* We need reg_raw_mode, so initialize the modes now. */
5072 init_reg_modes_once ();
5074 /* Initialize the CONST_INT, CONST_DOUBLE, and memory attribute hash
5076 const_int_htab = htab_create_ggc (37, const_int_htab_hash,
5077 const_int_htab_eq, NULL);
5079 const_double_htab = htab_create_ggc (37, const_double_htab_hash,
5080 const_double_htab_eq, NULL);
5082 mem_attrs_htab = htab_create_ggc (37, mem_attrs_htab_hash,
5083 mem_attrs_htab_eq, NULL);
5084 reg_attrs_htab = htab_create_ggc (37, reg_attrs_htab_hash,
5085 reg_attrs_htab_eq, NULL);
5087 no_line_numbers = ! line_numbers;
5089 /* Compute the word and byte modes. */
5091 byte_mode = VOIDmode;
5092 word_mode = VOIDmode;
5093 double_mode = VOIDmode;
5095 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
5097 mode = GET_MODE_WIDER_MODE (mode))
5099 if (GET_MODE_BITSIZE (mode) == BITS_PER_UNIT
5100 && byte_mode == VOIDmode)
5103 if (GET_MODE_BITSIZE (mode) == BITS_PER_WORD
5104 && word_mode == VOIDmode)
5108 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT);
5110 mode = GET_MODE_WIDER_MODE (mode))
5112 if (GET_MODE_BITSIZE (mode) == DOUBLE_TYPE_SIZE
5113 && double_mode == VOIDmode)
5117 ptr_mode = mode_for_size (POINTER_SIZE, GET_MODE_CLASS (Pmode), 0);
5119 /* Assign register numbers to the globally defined register rtx.
5120 This must be done at runtime because the register number field
5121 is in a union and some compilers can't initialize unions. */
5123 pc_rtx = gen_rtx_PC (VOIDmode);
5124 cc0_rtx = gen_rtx_CC0 (VOIDmode);
5125 stack_pointer_rtx = gen_raw_REG (Pmode, STACK_POINTER_REGNUM);
5126 frame_pointer_rtx = gen_raw_REG (Pmode, FRAME_POINTER_REGNUM);
5127 if (hard_frame_pointer_rtx == 0)
5128 hard_frame_pointer_rtx = gen_raw_REG (Pmode,
5129 HARD_FRAME_POINTER_REGNUM);
5130 if (arg_pointer_rtx == 0)
5131 arg_pointer_rtx = gen_raw_REG (Pmode, ARG_POINTER_REGNUM);
5132 virtual_incoming_args_rtx =
5133 gen_raw_REG (Pmode, VIRTUAL_INCOMING_ARGS_REGNUM);
5134 virtual_stack_vars_rtx =
5135 gen_raw_REG (Pmode, VIRTUAL_STACK_VARS_REGNUM);
5136 virtual_stack_dynamic_rtx =
5137 gen_raw_REG (Pmode, VIRTUAL_STACK_DYNAMIC_REGNUM);
5138 virtual_outgoing_args_rtx =
5139 gen_raw_REG (Pmode, VIRTUAL_OUTGOING_ARGS_REGNUM);
5140 virtual_cfa_rtx = gen_raw_REG (Pmode, VIRTUAL_CFA_REGNUM);
5142 /* Initialize RTL for commonly used hard registers. These are
5143 copied into regno_reg_rtx as we begin to compile each function. */
5144 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5145 static_regno_reg_rtx[i] = gen_raw_REG (reg_raw_mode[i], i);
5147 #ifdef INIT_EXPANDERS
5148 /* This is to initialize {init|mark|free}_machine_status before the first
5149 call to push_function_context_to. This is needed by the Chill front
5150 end which calls push_function_context_to before the first call to
5151 init_function_start. */
5155 /* Create the unique rtx's for certain rtx codes and operand values. */
5157 /* Don't use gen_rtx_CONST_INT here since gen_rtx_CONST_INT in this case
5158 tries to use these variables. */
5159 for (i = - MAX_SAVED_CONST_INT; i <= MAX_SAVED_CONST_INT; i++)
5160 const_int_rtx[i + MAX_SAVED_CONST_INT] =
5161 gen_rtx_raw_CONST_INT (VOIDmode, (HOST_WIDE_INT) i);
5163 if (STORE_FLAG_VALUE >= - MAX_SAVED_CONST_INT
5164 && STORE_FLAG_VALUE <= MAX_SAVED_CONST_INT)
5165 const_true_rtx = const_int_rtx[STORE_FLAG_VALUE + MAX_SAVED_CONST_INT];
5167 const_true_rtx = gen_rtx_CONST_INT (VOIDmode, STORE_FLAG_VALUE);
5169 REAL_VALUE_FROM_INT (dconst0, 0, 0, double_mode);
5170 REAL_VALUE_FROM_INT (dconst1, 1, 0, double_mode);
5171 REAL_VALUE_FROM_INT (dconst2, 2, 0, double_mode);
5172 REAL_VALUE_FROM_INT (dconst3, 3, 0, double_mode);
5173 REAL_VALUE_FROM_INT (dconst10, 10, 0, double_mode);
5174 REAL_VALUE_FROM_INT (dconstm1, -1, -1, double_mode);
5175 REAL_VALUE_FROM_INT (dconstm2, -2, -1, double_mode);
5177 dconsthalf = dconst1;
5178 SET_REAL_EXP (&dconsthalf, REAL_EXP (&dconsthalf) - 1);
5180 real_arithmetic (&dconstthird, RDIV_EXPR, &dconst1, &dconst3);
5182 /* Initialize mathematical constants for constant folding builtins.
5183 These constants need to be given to at least 160 bits precision. */
5184 real_from_string (&dconstsqrt2,
5185 "1.4142135623730950488016887242096980785696718753769480731766797379907");
5186 real_from_string (&dconste,
5187 "2.7182818284590452353602874713526624977572470936999595749669676277241");
5189 for (i = 0; i < (int) ARRAY_SIZE (const_tiny_rtx); i++)
5191 REAL_VALUE_TYPE *r =
5192 (i == 0 ? &dconst0 : i == 1 ? &dconst1 : &dconst2);
5194 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT);
5196 mode = GET_MODE_WIDER_MODE (mode))
5197 const_tiny_rtx[i][(int) mode] =
5198 CONST_DOUBLE_FROM_REAL_VALUE (*r, mode);
5200 for (mode = GET_CLASS_NARROWEST_MODE (MODE_DECIMAL_FLOAT);
5202 mode = GET_MODE_WIDER_MODE (mode))
5203 const_tiny_rtx[i][(int) mode] =
5204 CONST_DOUBLE_FROM_REAL_VALUE (*r, mode);
5206 const_tiny_rtx[i][(int) VOIDmode] = GEN_INT (i);
5208 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
5210 mode = GET_MODE_WIDER_MODE (mode))
5211 const_tiny_rtx[i][(int) mode] = GEN_INT (i);
5213 for (mode = GET_CLASS_NARROWEST_MODE (MODE_PARTIAL_INT);
5215 mode = GET_MODE_WIDER_MODE (mode))
5216 const_tiny_rtx[i][(int) mode] = GEN_INT (i);
5219 for (mode = GET_CLASS_NARROWEST_MODE (MODE_COMPLEX_INT);
5221 mode = GET_MODE_WIDER_MODE (mode))
5223 rtx inner = const_tiny_rtx[0][(int)GET_MODE_INNER (mode)];
5224 const_tiny_rtx[0][(int) mode] = gen_rtx_CONCAT (mode, inner, inner);
5227 for (mode = GET_CLASS_NARROWEST_MODE (MODE_COMPLEX_FLOAT);
5229 mode = GET_MODE_WIDER_MODE (mode))
5231 rtx inner = const_tiny_rtx[0][(int)GET_MODE_INNER (mode)];
5232 const_tiny_rtx[0][(int) mode] = gen_rtx_CONCAT (mode, inner, inner);
5235 for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_INT);
5237 mode = GET_MODE_WIDER_MODE (mode))
5239 const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0);
5240 const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1);
5243 for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FLOAT);
5245 mode = GET_MODE_WIDER_MODE (mode))
5247 const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0);
5248 const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1);
5251 for (i = (int) CCmode; i < (int) MAX_MACHINE_MODE; ++i)
5252 if (GET_MODE_CLASS ((enum machine_mode) i) == MODE_CC)
5253 const_tiny_rtx[0][i] = const0_rtx;
5255 const_tiny_rtx[0][(int) BImode] = const0_rtx;
5256 if (STORE_FLAG_VALUE == 1)
5257 const_tiny_rtx[1][(int) BImode] = const1_rtx;
5259 #ifdef RETURN_ADDRESS_POINTER_REGNUM
5260 return_address_pointer_rtx
5261 = gen_raw_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM);
5264 #ifdef STATIC_CHAIN_REGNUM
5265 static_chain_rtx = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);
5267 #ifdef STATIC_CHAIN_INCOMING_REGNUM
5268 if (STATIC_CHAIN_INCOMING_REGNUM != STATIC_CHAIN_REGNUM)
5269 static_chain_incoming_rtx
5270 = gen_rtx_REG (Pmode, STATIC_CHAIN_INCOMING_REGNUM);
5273 static_chain_incoming_rtx = static_chain_rtx;
5277 static_chain_rtx = STATIC_CHAIN;
5279 #ifdef STATIC_CHAIN_INCOMING
5280 static_chain_incoming_rtx = STATIC_CHAIN_INCOMING;
5282 static_chain_incoming_rtx = static_chain_rtx;
5286 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
5287 pic_offset_table_rtx = gen_raw_REG (Pmode, PIC_OFFSET_TABLE_REGNUM);
5290 /* Produce exact duplicate of insn INSN after AFTER.
5291 Care updating of libcall regions if present. */
5294 emit_copy_of_insn_after (rtx insn, rtx after)
5297 rtx note1, note2, link;
5299 switch (GET_CODE (insn))
5302 new = emit_insn_after (copy_insn (PATTERN (insn)), after);
5306 new = emit_jump_insn_after (copy_insn (PATTERN (insn)), after);
5310 new = emit_call_insn_after (copy_insn (PATTERN (insn)), after);
5311 if (CALL_INSN_FUNCTION_USAGE (insn))
5312 CALL_INSN_FUNCTION_USAGE (new)
5313 = copy_insn (CALL_INSN_FUNCTION_USAGE (insn));
5314 SIBLING_CALL_P (new) = SIBLING_CALL_P (insn);
5315 CONST_OR_PURE_CALL_P (new) = CONST_OR_PURE_CALL_P (insn);
5322 /* Update LABEL_NUSES. */
5323 mark_jump_label (PATTERN (new), new, 0);
5325 INSN_LOCATOR (new) = INSN_LOCATOR (insn);
5327 /* If the old insn is frame related, then so is the new one. This is
5328 primarily needed for IA-64 unwind info which marks epilogue insns,
5329 which may be duplicated by the basic block reordering code. */
5330 RTX_FRAME_RELATED_P (new) = RTX_FRAME_RELATED_P (insn);
5332 /* Copy all REG_NOTES except REG_LABEL since mark_jump_label will
5334 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
5335 if (REG_NOTE_KIND (link) != REG_LABEL)
5337 if (GET_CODE (link) == EXPR_LIST)
5339 = gen_rtx_EXPR_LIST (REG_NOTE_KIND (link),
5340 copy_insn_1 (XEXP (link, 0)), REG_NOTES (new));
5343 = gen_rtx_INSN_LIST (REG_NOTE_KIND (link),
5344 XEXP (link, 0), REG_NOTES (new));
5347 /* Fix the libcall sequences. */
5348 if ((note1 = find_reg_note (new, REG_RETVAL, NULL_RTX)) != NULL)
5351 while ((note2 = find_reg_note (p, REG_LIBCALL, NULL_RTX)) == NULL)
5353 XEXP (note1, 0) = p;
5354 XEXP (note2, 0) = new;
5356 INSN_CODE (new) = INSN_CODE (insn);
5360 static GTY((deletable)) rtx hard_reg_clobbers [NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
5362 gen_hard_reg_clobber (enum machine_mode mode, unsigned int regno)
5364 if (hard_reg_clobbers[mode][regno])
5365 return hard_reg_clobbers[mode][regno];
5367 return (hard_reg_clobbers[mode][regno] =
5368 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (mode, regno)));
5371 #include "gt-emit-rtl.h"