1 /* Emit RTL for the GNU C-Compiler expander.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 /* Middle-to-low level generation of rtx code and insns.
25 This file contains the functions `gen_rtx', `gen_reg_rtx'
26 and `gen_label_rtx' that are the usual ways of creating rtl
27 expressions for most purposes.
29 It also has the functions for creating insns and linking
30 them in the doubly-linked chain.
32 The patterns of the insns are created by machine-dependent
33 routines in insn-emit.c, which is generated automatically from
34 the machine description. These routines use `gen_rtx' to make
35 the individual rtx's of the pattern; what is machine dependent
36 is the kind of rtx's they make and what arguments they use. */
48 #include "hard-reg-set.h"
50 #include "insn-config.h"
55 #include "basic-block.h"
58 /* Commonly used modes. */
60 enum machine_mode byte_mode; /* Mode whose width is BITS_PER_UNIT. */
61 enum machine_mode word_mode; /* Mode whose width is BITS_PER_WORD. */
62 enum machine_mode double_mode; /* Mode whose width is DOUBLE_TYPE_SIZE. */
63 enum machine_mode ptr_mode; /* Mode whose width is POINTER_SIZE. */
66 /* This is *not* reset after each function. It gives each CODE_LABEL
67 in the entire compilation a unique label number. */
69 static int label_num = 1;
71 /* Highest label number in current function.
72 Zero means use the value of label_num instead.
73 This is nonzero only when belatedly compiling an inline function. */
75 static int last_label_num;
77 /* Value label_num had when set_new_first_and_last_label_number was called.
78 If label_num has not changed since then, last_label_num is valid. */
80 static int base_label_num;
82 /* Nonzero means do not generate NOTEs for source line numbers. */
84 static int no_line_numbers;
86 /* Commonly used rtx's, so that we only need space for one copy.
87 These are initialized once for the entire compilation.
88 All of these except perhaps the floating-point CONST_DOUBLEs
89 are unique; no other rtx-object will be equal to any of these. */
91 rtx global_rtl[GR_MAX];
93 /* We record floating-point CONST_DOUBLEs in each floating-point mode for
94 the values of 0, 1, and 2. For the integer entries and VOIDmode, we
95 record a copy of const[012]_rtx. */
97 rtx const_tiny_rtx[3][(int) MAX_MACHINE_MODE];
101 REAL_VALUE_TYPE dconst0;
102 REAL_VALUE_TYPE dconst1;
103 REAL_VALUE_TYPE dconst2;
104 REAL_VALUE_TYPE dconstm1;
106 /* All references to the following fixed hard registers go through
107 these unique rtl objects. On machines where the frame-pointer and
108 arg-pointer are the same register, they use the same unique object.
110 After register allocation, other rtl objects which used to be pseudo-regs
111 may be clobbered to refer to the frame-pointer register.
112 But references that were originally to the frame-pointer can be
113 distinguished from the others because they contain frame_pointer_rtx.
115 When to use frame_pointer_rtx and hard_frame_pointer_rtx is a little
116 tricky: until register elimination has taken place hard_frame_pointer_rtx
117 should be used if it is being set, and frame_pointer_rtx otherwise. After
118 register elimination hard_frame_pointer_rtx should always be used.
119 On machines where the two registers are same (most) then these are the
122 In an inline procedure, the stack and frame pointer rtxs may not be
123 used for anything else. */
124 rtx struct_value_rtx; /* (REG:Pmode STRUCT_VALUE_REGNUM) */
125 rtx struct_value_incoming_rtx; /* (REG:Pmode STRUCT_VALUE_INCOMING_REGNUM) */
126 rtx static_chain_rtx; /* (REG:Pmode STATIC_CHAIN_REGNUM) */
127 rtx static_chain_incoming_rtx; /* (REG:Pmode STATIC_CHAIN_INCOMING_REGNUM) */
128 rtx pic_offset_table_rtx; /* (REG:Pmode PIC_OFFSET_TABLE_REGNUM) */
130 /* This is used to implement __builtin_return_address for some machines.
131 See for instance the MIPS port. */
132 rtx return_address_pointer_rtx; /* (REG:Pmode RETURN_ADDRESS_POINTER_REGNUM) */
134 /* We make one copy of (const_int C) where C is in
135 [- MAX_SAVED_CONST_INT, MAX_SAVED_CONST_INT]
136 to save space during the compilation and simplify comparisons of
139 rtx const_int_rtx[MAX_SAVED_CONST_INT * 2 + 1];
141 /* A hash table storing CONST_INTs whose absolute value is greater
142 than MAX_SAVED_CONST_INT. */
144 static htab_t const_int_htab;
146 /* start_sequence and gen_sequence can make a lot of rtx expressions which are
147 shortly thrown away. We use two mechanisms to prevent this waste:
149 For sizes up to 5 elements, we keep a SEQUENCE and its associated
150 rtvec for use by gen_sequence. One entry for each size is
151 sufficient because most cases are calls to gen_sequence followed by
152 immediately emitting the SEQUENCE. Reuse is safe since emitting a
153 sequence is destructive on the insn in it anyway and hence can't be
156 We do not bother to save this cached data over nested function calls.
157 Instead, we just reinitialize them. */
159 #define SEQUENCE_RESULT_SIZE 5
161 static rtx sequence_result[SEQUENCE_RESULT_SIZE];
163 /* During RTL generation, we also keep a list of free INSN rtl codes. */
164 static rtx free_insn;
166 #define first_insn (cfun->emit->x_first_insn)
167 #define last_insn (cfun->emit->x_last_insn)
168 #define cur_insn_uid (cfun->emit->x_cur_insn_uid)
169 #define last_linenum (cfun->emit->x_last_linenum)
170 #define last_filename (cfun->emit->x_last_filename)
171 #define first_label_num (cfun->emit->x_first_label_num)
173 /* This is where the pointer to the obstack being used for RTL is stored. */
174 extern struct obstack *rtl_obstack;
176 static rtx make_jump_insn_raw PARAMS ((rtx));
177 static rtx make_call_insn_raw PARAMS ((rtx));
178 static rtx find_line_note PARAMS ((rtx));
179 static void mark_sequence_stack PARAMS ((struct sequence_stack *));
180 static void unshare_all_rtl_1 PARAMS ((rtx));
181 static hashval_t const_int_htab_hash PARAMS ((const void *));
182 static int const_int_htab_eq PARAMS ((const void *,
184 static int rtx_htab_mark_1 PARAMS ((void **, void *));
185 static void rtx_htab_mark PARAMS ((void *));
188 /* Returns a hash code for X (which is a really a CONST_INT). */
191 const_int_htab_hash (x)
194 return (hashval_t) INTVAL ((const struct rtx_def *) x);
197 /* Returns non-zero if the value represented by X (which is really a
198 CONST_INT) is the same as that given by Y (which is really a
202 const_int_htab_eq (x, y)
206 return (INTVAL ((const struct rtx_def *) x) == *((const HOST_WIDE_INT *) y));
209 /* Mark the hash-table element X (which is really a pointer to an
213 rtx_htab_mark_1 (x, data)
215 void *data ATTRIBUTE_UNUSED;
221 /* Mark all the elements of HTAB (which is really an htab_t full of
228 htab_traverse (*((htab_t *) htab), rtx_htab_mark_1, NULL);
231 /* There are some RTL codes that require special attention; the generation
232 functions do the raw handling. If you add to this list, modify
233 special_rtx in gengenrtl.c as well. */
236 gen_rtx_CONST_INT (mode, arg)
237 enum machine_mode mode ATTRIBUTE_UNUSED;
242 if (arg >= - MAX_SAVED_CONST_INT && arg <= MAX_SAVED_CONST_INT)
243 return const_int_rtx[arg + MAX_SAVED_CONST_INT];
245 #if STORE_FLAG_VALUE != 1 && STORE_FLAG_VALUE != -1
246 if (const_true_rtx && arg == STORE_FLAG_VALUE)
247 return const_true_rtx;
250 /* Look up the CONST_INT in the hash table. */
251 slot = htab_find_slot_with_hash (const_int_htab, &arg, (hashval_t) arg, 1);
256 push_obstacks_nochange ();
257 end_temporary_allocation ();
258 *slot = gen_rtx_raw_CONST_INT (VOIDmode, arg);
262 *slot = gen_rtx_raw_CONST_INT (VOIDmode, arg);
268 /* CONST_DOUBLEs needs special handling because their length is known
272 gen_rtx_CONST_DOUBLE (mode, arg0, arg1, arg2)
273 enum machine_mode mode;
275 HOST_WIDE_INT arg1, arg2;
277 rtx r = rtx_alloc (CONST_DOUBLE);
282 X0EXP (r, 1) = NULL_RTX;
286 for (i = GET_RTX_LENGTH (CONST_DOUBLE) - 1; i > 3; --i)
293 gen_rtx_REG (mode, regno)
294 enum machine_mode mode;
297 /* In case the MD file explicitly references the frame pointer, have
298 all such references point to the same frame pointer. This is
299 used during frame pointer elimination to distinguish the explicit
300 references to these registers from pseudos that happened to be
303 If we have eliminated the frame pointer or arg pointer, we will
304 be using it as a normal register, for example as a spill
305 register. In such cases, we might be accessing it in a mode that
306 is not Pmode and therefore cannot use the pre-allocated rtx.
308 Also don't do this when we are making new REGs in reload, since
309 we don't want to get confused with the real pointers. */
311 if (mode == Pmode && !reload_in_progress)
313 if (regno == FRAME_POINTER_REGNUM)
314 return frame_pointer_rtx;
315 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
316 if (regno == HARD_FRAME_POINTER_REGNUM)
317 return hard_frame_pointer_rtx;
319 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM && HARD_FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
320 if (regno == ARG_POINTER_REGNUM)
321 return arg_pointer_rtx;
323 #ifdef RETURN_ADDRESS_POINTER_REGNUM
324 if (regno == RETURN_ADDRESS_POINTER_REGNUM)
325 return return_address_pointer_rtx;
327 if (regno == STACK_POINTER_REGNUM)
328 return stack_pointer_rtx;
331 return gen_rtx_raw_REG (mode, regno);
335 gen_rtx_MEM (mode, addr)
336 enum machine_mode mode;
339 rtx rt = gen_rtx_raw_MEM (mode, addr);
341 /* This field is not cleared by the mere allocation of the rtx, so
343 MEM_ALIAS_SET (rt) = 0;
348 /* rtx gen_rtx (code, mode, [element1, ..., elementn])
350 ** This routine generates an RTX of the size specified by
351 ** <code>, which is an RTX code. The RTX structure is initialized
352 ** from the arguments <element1> through <elementn>, which are
353 ** interpreted according to the specific RTX type's format. The
354 ** special machine mode associated with the rtx (if any) is specified
357 ** gen_rtx can be invoked in a way which resembles the lisp-like
358 ** rtx it will generate. For example, the following rtx structure:
360 ** (plus:QI (mem:QI (reg:SI 1))
361 ** (mem:QI (plusw:SI (reg:SI 2) (reg:SI 3))))
363 ** ...would be generated by the following C code:
365 ** gen_rtx (PLUS, QImode,
366 ** gen_rtx (MEM, QImode,
367 ** gen_rtx (REG, SImode, 1)),
368 ** gen_rtx (MEM, QImode,
369 ** gen_rtx (PLUS, SImode,
370 ** gen_rtx (REG, SImode, 2),
371 ** gen_rtx (REG, SImode, 3)))),
376 gen_rtx VPARAMS ((enum rtx_code code, enum machine_mode mode, ...))
378 #ifndef ANSI_PROTOTYPES
380 enum machine_mode mode;
383 register int i; /* Array indices... */
384 register const char *fmt; /* Current rtx's format... */
385 register rtx rt_val; /* RTX to return to caller... */
389 #ifndef ANSI_PROTOTYPES
390 code = va_arg (p, enum rtx_code);
391 mode = va_arg (p, enum machine_mode);
397 rt_val = gen_rtx_CONST_INT (mode, va_arg (p, HOST_WIDE_INT));
402 rtx arg0 = va_arg (p, rtx);
403 HOST_WIDE_INT arg1 = va_arg (p, HOST_WIDE_INT);
404 HOST_WIDE_INT arg2 = va_arg (p, HOST_WIDE_INT);
405 rt_val = gen_rtx_CONST_DOUBLE (mode, arg0, arg1, arg2);
410 rt_val = gen_rtx_REG (mode, va_arg (p, int));
414 rt_val = gen_rtx_MEM (mode, va_arg (p, rtx));
418 rt_val = rtx_alloc (code); /* Allocate the storage space. */
419 rt_val->mode = mode; /* Store the machine mode... */
421 fmt = GET_RTX_FORMAT (code); /* Find the right format... */
422 for (i = 0; i < GET_RTX_LENGTH (code); i++)
426 case '0': /* Unused field. */
429 case 'i': /* An integer? */
430 XINT (rt_val, i) = va_arg (p, int);
433 case 'w': /* A wide integer? */
434 XWINT (rt_val, i) = va_arg (p, HOST_WIDE_INT);
437 case 's': /* A string? */
438 XSTR (rt_val, i) = va_arg (p, char *);
441 case 'e': /* An expression? */
442 case 'u': /* An insn? Same except when printing. */
443 XEXP (rt_val, i) = va_arg (p, rtx);
446 case 'E': /* An RTX vector? */
447 XVEC (rt_val, i) = va_arg (p, rtvec);
450 case 'b': /* A bitmap? */
451 XBITMAP (rt_val, i) = va_arg (p, bitmap);
454 case 't': /* A tree? */
455 XTREE (rt_val, i) = va_arg (p, tree);
469 /* gen_rtvec (n, [rt1, ..., rtn])
471 ** This routine creates an rtvec and stores within it the
472 ** pointers to rtx's which are its arguments.
477 gen_rtvec VPARAMS ((int n, ...))
479 #ifndef ANSI_PROTOTYPES
488 #ifndef ANSI_PROTOTYPES
493 return NULL_RTVEC; /* Don't allocate an empty rtvec... */
495 vector = (rtx *) alloca (n * sizeof (rtx));
497 for (i = 0; i < n; i++)
498 vector[i] = va_arg (p, rtx);
501 return gen_rtvec_v (n, vector);
505 gen_rtvec_v (n, argp)
510 register rtvec rt_val;
513 return NULL_RTVEC; /* Don't allocate an empty rtvec... */
515 rt_val = rtvec_alloc (n); /* Allocate an rtvec... */
517 for (i = 0; i < n; i++)
518 rt_val->elem[i] = *argp++;
524 /* Generate a REG rtx for a new pseudo register of mode MODE.
525 This pseudo is assigned the next sequential register number. */
529 enum machine_mode mode;
531 struct function *f = cfun;
534 /* Don't let anything called after initial flow analysis create new
539 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
540 || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
542 /* For complex modes, don't make a single pseudo.
543 Instead, make a CONCAT of two pseudos.
544 This allows noncontiguous allocation of the real and imaginary parts,
545 which makes much better code. Besides, allocating DCmode
546 pseudos overstrains reload on some machines like the 386. */
547 rtx realpart, imagpart;
548 int size = GET_MODE_UNIT_SIZE (mode);
549 enum machine_mode partmode
550 = mode_for_size (size * BITS_PER_UNIT,
551 (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
552 ? MODE_FLOAT : MODE_INT),
555 realpart = gen_reg_rtx (partmode);
556 imagpart = gen_reg_rtx (partmode);
557 return gen_rtx_CONCAT (mode, realpart, imagpart);
560 /* Make sure regno_pointer_flag and regno_reg_rtx are large
561 enough to have an element for this pseudo reg number. */
563 if (reg_rtx_no == f->emit->regno_pointer_flag_length)
565 int old_size = f->emit->regno_pointer_flag_length;
568 new = xrealloc (f->emit->regno_pointer_flag, old_size * 2);
569 memset (new + old_size, 0, old_size);
570 f->emit->regno_pointer_flag = new;
572 new = xrealloc (f->emit->regno_pointer_align, old_size * 2);
573 memset (new + old_size, 0, old_size);
574 f->emit->regno_pointer_align = new;
576 new1 = (rtx *) xrealloc (f->emit->x_regno_reg_rtx,
577 old_size * 2 * sizeof (rtx));
578 memset (new1 + old_size, 0, old_size * sizeof (rtx));
579 regno_reg_rtx = new1;
581 f->emit->regno_pointer_flag_length = old_size * 2;
584 val = gen_rtx_raw_REG (mode, reg_rtx_no);
585 regno_reg_rtx[reg_rtx_no++] = val;
589 /* Identify REG (which may be a CONCAT) as a user register. */
595 if (GET_CODE (reg) == CONCAT)
597 REG_USERVAR_P (XEXP (reg, 0)) = 1;
598 REG_USERVAR_P (XEXP (reg, 1)) = 1;
600 else if (GET_CODE (reg) == REG)
601 REG_USERVAR_P (reg) = 1;
606 /* Identify REG as a probable pointer register and show its alignment
607 as ALIGN, if nonzero. */
610 mark_reg_pointer (reg, align)
614 if (! REGNO_POINTER_FLAG (REGNO (reg)))
616 REGNO_POINTER_FLAG (REGNO (reg)) = 1;
619 REGNO_POINTER_ALIGN (REGNO (reg)) = align;
621 else if (align && align < REGNO_POINTER_ALIGN (REGNO (reg)))
622 /* We can no-longer be sure just how aligned this pointer is */
623 REGNO_POINTER_ALIGN (REGNO (reg)) = align;
626 /* Return 1 plus largest pseudo reg number used in the current function. */
634 /* Return 1 + the largest label number used so far in the current function. */
639 if (last_label_num && label_num == base_label_num)
640 return last_label_num;
644 /* Return first label number used in this function (if any were used). */
647 get_first_label_num ()
649 return first_label_num;
652 /* Return a value representing some low-order bits of X, where the number
653 of low-order bits is given by MODE. Note that no conversion is done
654 between floating-point and fixed-point values, rather, the bit
655 representation is returned.
657 This function handles the cases in common between gen_lowpart, below,
658 and two variants in cse.c and combine.c. These are the cases that can
659 be safely handled at all points in the compilation.
661 If this is not a case we can handle, return 0. */
664 gen_lowpart_common (mode, x)
665 enum machine_mode mode;
670 if (GET_MODE (x) == mode)
673 /* MODE must occupy no more words than the mode of X. */
674 if (GET_MODE (x) != VOIDmode
675 && ((GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD
676 > ((GET_MODE_SIZE (GET_MODE (x)) + (UNITS_PER_WORD - 1))
680 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
681 word = ((GET_MODE_SIZE (GET_MODE (x))
682 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
685 if ((GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND)
686 && (GET_MODE_CLASS (mode) == MODE_INT
687 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT))
689 /* If we are getting the low-order part of something that has been
690 sign- or zero-extended, we can either just use the object being
691 extended or make a narrower extension. If we want an even smaller
692 piece than the size of the object being extended, call ourselves
695 This case is used mostly by combine and cse. */
697 if (GET_MODE (XEXP (x, 0)) == mode)
699 else if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (XEXP (x, 0))))
700 return gen_lowpart_common (mode, XEXP (x, 0));
701 else if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x)))
702 return gen_rtx_fmt_e (GET_CODE (x), mode, XEXP (x, 0));
704 else if (GET_CODE (x) == SUBREG
705 && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
706 || GET_MODE_SIZE (mode) == GET_MODE_UNIT_SIZE (GET_MODE (x))))
707 return (GET_MODE (SUBREG_REG (x)) == mode && SUBREG_WORD (x) == 0
709 : gen_rtx_SUBREG (mode, SUBREG_REG (x), SUBREG_WORD (x) + word));
710 else if (GET_CODE (x) == REG)
712 /* Let the backend decide how many registers to skip. This is needed
713 in particular for Sparc64 where fp regs are smaller than a word. */
714 /* ??? Note that subregs are now ambiguous, in that those against
715 pseudos are sized by the Word Size, while those against hard
716 regs are sized by the underlying register size. Better would be
717 to always interpret the subreg offset parameter as bytes or bits. */
719 if (WORDS_BIG_ENDIAN && REGNO (x) < FIRST_PSEUDO_REGISTER)
720 word = (HARD_REGNO_NREGS (REGNO (x), GET_MODE (x))
721 - HARD_REGNO_NREGS (REGNO (x), mode));
723 /* If the register is not valid for MODE, return 0. If we don't
724 do this, there is no way to fix up the resulting REG later.
725 But we do do this if the current REG is not valid for its
726 mode. This latter is a kludge, but is required due to the
727 way that parameters are passed on some machines, most
729 if (REGNO (x) < FIRST_PSEUDO_REGISTER
730 && ! HARD_REGNO_MODE_OK (REGNO (x) + word, mode)
731 && HARD_REGNO_MODE_OK (REGNO (x), GET_MODE (x)))
733 else if (REGNO (x) < FIRST_PSEUDO_REGISTER
734 /* integrate.c can't handle parts of a return value register. */
735 && (! REG_FUNCTION_VALUE_P (x)
736 || ! rtx_equal_function_value_matters)
737 #ifdef CLASS_CANNOT_CHANGE_SIZE
738 && ! (GET_MODE_SIZE (mode) != GET_MODE_SIZE (GET_MODE (x))
739 && GET_MODE_CLASS (GET_MODE (x)) != MODE_COMPLEX_INT
740 && GET_MODE_CLASS (GET_MODE (x)) != MODE_COMPLEX_FLOAT
741 && (TEST_HARD_REG_BIT
742 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE],
745 /* We want to keep the stack, frame, and arg pointers
747 && x != frame_pointer_rtx
748 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
749 && x != arg_pointer_rtx
751 && x != stack_pointer_rtx)
752 return gen_rtx_REG (mode, REGNO (x) + word);
754 return gen_rtx_SUBREG (mode, x, word);
756 /* If X is a CONST_INT or a CONST_DOUBLE, extract the appropriate bits
757 from the low-order part of the constant. */
758 else if ((GET_MODE_CLASS (mode) == MODE_INT
759 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
760 && GET_MODE (x) == VOIDmode
761 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
763 /* If MODE is twice the host word size, X is already the desired
764 representation. Otherwise, if MODE is wider than a word, we can't
765 do this. If MODE is exactly a word, return just one CONST_INT.
766 If MODE is smaller than a word, clear the bits that don't belong
767 in our mode, unless they and our sign bit are all one. So we get
768 either a reasonable negative value or a reasonable unsigned value
771 if (GET_MODE_BITSIZE (mode) >= 2 * HOST_BITS_PER_WIDE_INT)
773 else if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
775 else if (GET_MODE_BITSIZE (mode) == HOST_BITS_PER_WIDE_INT)
776 return (GET_CODE (x) == CONST_INT ? x
777 : GEN_INT (CONST_DOUBLE_LOW (x)));
780 /* MODE must be narrower than HOST_BITS_PER_WIDE_INT. */
781 int width = GET_MODE_BITSIZE (mode);
782 HOST_WIDE_INT val = (GET_CODE (x) == CONST_INT ? INTVAL (x)
783 : CONST_DOUBLE_LOW (x));
785 /* Sign extend to HOST_WIDE_INT. */
786 val = val << (HOST_BITS_PER_WIDE_INT - width) >> (HOST_BITS_PER_WIDE_INT - width);
788 return (GET_CODE (x) == CONST_INT && INTVAL (x) == val ? x
793 /* If X is an integral constant but we want it in floating-point, it
794 must be the case that we have a union of an integer and a floating-point
795 value. If the machine-parameters allow it, simulate that union here
796 and return the result. The two-word and single-word cases are
799 else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT
800 && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
801 || flag_pretend_float)
802 && GET_MODE_CLASS (mode) == MODE_FLOAT
803 && GET_MODE_SIZE (mode) == UNITS_PER_WORD
804 && GET_CODE (x) == CONST_INT
805 && sizeof (float) * HOST_BITS_PER_CHAR == HOST_BITS_PER_WIDE_INT)
806 #ifdef REAL_ARITHMETIC
812 r = REAL_VALUE_FROM_TARGET_SINGLE (i);
813 return CONST_DOUBLE_FROM_REAL_VALUE (r, mode);
817 union {HOST_WIDE_INT i; float d; } u;
820 return CONST_DOUBLE_FROM_REAL_VALUE (u.d, mode);
823 else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT
824 && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
825 || flag_pretend_float)
826 && GET_MODE_CLASS (mode) == MODE_FLOAT
827 && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD
828 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
829 && GET_MODE (x) == VOIDmode
830 && (sizeof (double) * HOST_BITS_PER_CHAR
831 == 2 * HOST_BITS_PER_WIDE_INT))
832 #ifdef REAL_ARITHMETIC
836 HOST_WIDE_INT low, high;
838 if (GET_CODE (x) == CONST_INT)
839 low = INTVAL (x), high = low >> (HOST_BITS_PER_WIDE_INT -1);
841 low = CONST_DOUBLE_LOW (x), high = CONST_DOUBLE_HIGH (x);
843 /* REAL_VALUE_TARGET_DOUBLE takes the addressing order of the
845 if (WORDS_BIG_ENDIAN)
846 i[0] = high, i[1] = low;
848 i[0] = low, i[1] = high;
850 r = REAL_VALUE_FROM_TARGET_DOUBLE (i);
851 return CONST_DOUBLE_FROM_REAL_VALUE (r, mode);
855 union {HOST_WIDE_INT i[2]; double d; } u;
856 HOST_WIDE_INT low, high;
858 if (GET_CODE (x) == CONST_INT)
859 low = INTVAL (x), high = low >> (HOST_BITS_PER_WIDE_INT -1);
861 low = CONST_DOUBLE_LOW (x), high = CONST_DOUBLE_HIGH (x);
863 #ifdef HOST_WORDS_BIG_ENDIAN
864 u.i[0] = high, u.i[1] = low;
866 u.i[0] = low, u.i[1] = high;
869 return CONST_DOUBLE_FROM_REAL_VALUE (u.d, mode);
873 /* We need an extra case for machines where HOST_BITS_PER_WIDE_INT is the
874 same as sizeof (double) or when sizeof (float) is larger than the
875 size of a word on the target machine. */
876 #ifdef REAL_ARITHMETIC
877 else if (mode == SFmode && GET_CODE (x) == CONST_INT)
883 r = REAL_VALUE_FROM_TARGET_SINGLE (i);
884 return CONST_DOUBLE_FROM_REAL_VALUE (r, mode);
886 else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT
887 && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
888 || flag_pretend_float)
889 && GET_MODE_CLASS (mode) == MODE_FLOAT
890 && GET_MODE_SIZE (mode) == UNITS_PER_WORD
891 && GET_CODE (x) == CONST_INT
892 && (sizeof (double) * HOST_BITS_PER_CHAR
893 == HOST_BITS_PER_WIDE_INT))
899 r = REAL_VALUE_FROM_TARGET_DOUBLE (&i);
900 return CONST_DOUBLE_FROM_REAL_VALUE (r, mode);
904 /* Similarly, if this is converting a floating-point value into a
905 single-word integer. Only do this is the host and target parameters are
908 else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT
909 && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
910 || flag_pretend_float)
911 && (GET_MODE_CLASS (mode) == MODE_INT
912 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
913 && GET_CODE (x) == CONST_DOUBLE
914 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT
915 && GET_MODE_BITSIZE (mode) == BITS_PER_WORD)
916 return operand_subword (x, word, 0, GET_MODE (x));
918 /* Similarly, if this is converting a floating-point value into a
919 two-word integer, we can do this one word at a time and make an
920 integer. Only do this is the host and target parameters are
923 else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT
924 && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
925 || flag_pretend_float)
926 && (GET_MODE_CLASS (mode) == MODE_INT
927 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
928 && GET_CODE (x) == CONST_DOUBLE
929 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT
930 && GET_MODE_BITSIZE (mode) == 2 * BITS_PER_WORD)
933 = operand_subword (x, word + WORDS_BIG_ENDIAN, 0, GET_MODE (x));
935 = operand_subword (x, word + ! WORDS_BIG_ENDIAN, 0, GET_MODE (x));
937 if (lowpart && GET_CODE (lowpart) == CONST_INT
938 && highpart && GET_CODE (highpart) == CONST_INT)
939 return immed_double_const (INTVAL (lowpart), INTVAL (highpart), mode);
942 /* Otherwise, we can't do this. */
946 /* Return the real part (which has mode MODE) of a complex value X.
947 This always comes at the low address in memory. */
950 gen_realpart (mode, x)
951 enum machine_mode mode;
954 if (GET_CODE (x) == CONCAT && GET_MODE (XEXP (x, 0)) == mode)
956 else if (WORDS_BIG_ENDIAN
957 && GET_MODE_BITSIZE (mode) < BITS_PER_WORD
959 && REGNO (x) < FIRST_PSEUDO_REGISTER)
960 fatal ("Unable to access real part of complex value in a hard register on this target");
961 else if (WORDS_BIG_ENDIAN)
962 return gen_highpart (mode, x);
964 return gen_lowpart (mode, x);
967 /* Return the imaginary part (which has mode MODE) of a complex value X.
968 This always comes at the high address in memory. */
971 gen_imagpart (mode, x)
972 enum machine_mode mode;
975 if (GET_CODE (x) == CONCAT && GET_MODE (XEXP (x, 0)) == mode)
977 else if (WORDS_BIG_ENDIAN)
978 return gen_lowpart (mode, x);
979 else if (!WORDS_BIG_ENDIAN
980 && GET_MODE_BITSIZE (mode) < BITS_PER_WORD
982 && REGNO (x) < FIRST_PSEUDO_REGISTER)
983 fatal ("Unable to access imaginary part of complex value in a hard register on this target");
985 return gen_highpart (mode, x);
988 /* Return 1 iff X, assumed to be a SUBREG,
989 refers to the real part of the complex value in its containing reg.
990 Complex values are always stored with the real part in the first word,
991 regardless of WORDS_BIG_ENDIAN. */
994 subreg_realpart_p (x)
997 if (GET_CODE (x) != SUBREG)
1000 return ((unsigned int) SUBREG_WORD (x) * UNITS_PER_WORD
1001 < GET_MODE_UNIT_SIZE (GET_MODE (SUBREG_REG (x))));
1004 /* Assuming that X is an rtx (e.g., MEM, REG or SUBREG) for a value,
1005 return an rtx (MEM, SUBREG, or CONST_INT) that refers to the
1006 least-significant part of X.
1007 MODE specifies how big a part of X to return;
1008 it usually should not be larger than a word.
1009 If X is a MEM whose address is a QUEUED, the value may be so also. */
1012 gen_lowpart (mode, x)
1013 enum machine_mode mode;
1016 rtx result = gen_lowpart_common (mode, x);
1020 else if (GET_CODE (x) == REG)
1022 /* Must be a hard reg that's not valid in MODE. */
1023 result = gen_lowpart_common (mode, copy_to_reg (x));
1028 else if (GET_CODE (x) == MEM)
1030 /* The only additional case we can do is MEM. */
1031 register int offset = 0;
1032 if (WORDS_BIG_ENDIAN)
1033 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
1034 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
1036 if (BYTES_BIG_ENDIAN)
1037 /* Adjust the address so that the address-after-the-data
1039 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
1040 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
1042 return change_address (x, mode, plus_constant (XEXP (x, 0), offset));
1044 else if (GET_CODE (x) == ADDRESSOF)
1045 return gen_lowpart (mode, force_reg (GET_MODE (x), x));
1050 /* Like `gen_lowpart', but refer to the most significant part.
1051 This is used to access the imaginary part of a complex number. */
1054 gen_highpart (mode, x)
1055 enum machine_mode mode;
1058 /* This case loses if X is a subreg. To catch bugs early,
1059 complain if an invalid MODE is used even in other cases. */
1060 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
1061 && GET_MODE_SIZE (mode) != GET_MODE_UNIT_SIZE (GET_MODE (x)))
1063 if (GET_CODE (x) == CONST_DOUBLE
1064 #if !(TARGET_FLOAT_FORMAT != HOST_FLOAT_FORMAT || defined (REAL_IS_NOT_DOUBLE))
1065 && GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT
1068 return GEN_INT (CONST_DOUBLE_HIGH (x) & GET_MODE_MASK (mode));
1069 else if (GET_CODE (x) == CONST_INT)
1071 if (HOST_BITS_PER_WIDE_INT <= BITS_PER_WORD)
1073 return GEN_INT (INTVAL (x) >> (HOST_BITS_PER_WIDE_INT - BITS_PER_WORD));
1075 else if (GET_CODE (x) == MEM)
1077 register int offset = 0;
1078 if (! WORDS_BIG_ENDIAN)
1079 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
1080 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
1082 if (! BYTES_BIG_ENDIAN
1083 && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
1084 offset -= (GET_MODE_SIZE (mode)
1085 - MIN (UNITS_PER_WORD,
1086 GET_MODE_SIZE (GET_MODE (x))));
1088 return change_address (x, mode, plus_constant (XEXP (x, 0), offset));
1090 else if (GET_CODE (x) == SUBREG)
1092 /* The only time this should occur is when we are looking at a
1093 multi-word item with a SUBREG whose mode is the same as that of the
1094 item. It isn't clear what we would do if it wasn't. */
1095 if (SUBREG_WORD (x) != 0)
1097 return gen_highpart (mode, SUBREG_REG (x));
1099 else if (GET_CODE (x) == REG)
1103 /* Let the backend decide how many registers to skip. This is needed
1104 in particular for sparc64 where fp regs are smaller than a word. */
1105 /* ??? Note that subregs are now ambiguous, in that those against
1106 pseudos are sized by the word size, while those against hard
1107 regs are sized by the underlying register size. Better would be
1108 to always interpret the subreg offset parameter as bytes or bits. */
1110 if (WORDS_BIG_ENDIAN)
1112 else if (REGNO (x) < FIRST_PSEUDO_REGISTER)
1113 word = (HARD_REGNO_NREGS (REGNO (x), GET_MODE (x))
1114 - HARD_REGNO_NREGS (REGNO (x), mode));
1116 word = ((GET_MODE_SIZE (GET_MODE (x))
1117 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
1120 if (REGNO (x) < FIRST_PSEUDO_REGISTER
1121 /* integrate.c can't handle parts of a return value register. */
1122 && (! REG_FUNCTION_VALUE_P (x)
1123 || ! rtx_equal_function_value_matters)
1124 /* We want to keep the stack, frame, and arg pointers special. */
1125 && x != frame_pointer_rtx
1126 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1127 && x != arg_pointer_rtx
1129 && x != stack_pointer_rtx)
1130 return gen_rtx_REG (mode, REGNO (x) + word);
1132 return gen_rtx_SUBREG (mode, x, word);
1138 /* Return 1 iff X, assumed to be a SUBREG,
1139 refers to the least significant part of its containing reg.
1140 If X is not a SUBREG, always return 1 (it is its own low part!). */
1143 subreg_lowpart_p (x)
1146 if (GET_CODE (x) != SUBREG)
1148 else if (GET_MODE (SUBREG_REG (x)) == VOIDmode)
1151 if (WORDS_BIG_ENDIAN
1152 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) > UNITS_PER_WORD)
1153 return (SUBREG_WORD (x)
1154 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
1155 - MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD))
1158 return SUBREG_WORD (x) == 0;
1161 /* Return subword I of operand OP.
1162 The word number, I, is interpreted as the word number starting at the
1163 low-order address. Word 0 is the low-order word if not WORDS_BIG_ENDIAN,
1164 otherwise it is the high-order word.
1166 If we cannot extract the required word, we return zero. Otherwise, an
1167 rtx corresponding to the requested word will be returned.
1169 VALIDATE_ADDRESS is nonzero if the address should be validated. Before
1170 reload has completed, a valid address will always be returned. After
1171 reload, if a valid address cannot be returned, we return zero.
1173 If VALIDATE_ADDRESS is zero, we simply form the required address; validating
1174 it is the responsibility of the caller.
1176 MODE is the mode of OP in case it is a CONST_INT. */
1179 operand_subword (op, i, validate_address, mode)
1182 int validate_address;
1183 enum machine_mode mode;
1186 int size_ratio = HOST_BITS_PER_WIDE_INT / BITS_PER_WORD;
1188 if (mode == VOIDmode)
1189 mode = GET_MODE (op);
1191 if (mode == VOIDmode)
1194 /* If OP is narrower than a word, fail. */
1196 && (GET_MODE_SIZE (mode) < UNITS_PER_WORD))
1199 /* If we want a word outside OP, return zero. */
1201 && (i + 1) * UNITS_PER_WORD > GET_MODE_SIZE (mode))
1204 /* If OP is already an integer word, return it. */
1205 if (GET_MODE_CLASS (mode) == MODE_INT
1206 && GET_MODE_SIZE (mode) == UNITS_PER_WORD)
1209 /* If OP is a REG or SUBREG, we can handle it very simply. */
1210 if (GET_CODE (op) == REG)
1212 /* ??? There is a potential problem with this code. It does not
1213 properly handle extractions of a subword from a hard register
1214 that is larger than word_mode. Presumably the check for
1215 HARD_REGNO_MODE_OK catches these most of these cases. */
1217 /* If OP is a hard register, but OP + I is not a hard register,
1218 then extracting a subword is impossible.
1220 For example, consider if OP is the last hard register and it is
1221 larger than word_mode. If we wanted word N (for N > 0) because a
1222 part of that hard register was known to contain a useful value,
1223 then OP + I would refer to a pseudo, not the hard register we
1225 if (REGNO (op) < FIRST_PSEUDO_REGISTER
1226 && REGNO (op) + i >= FIRST_PSEUDO_REGISTER)
1229 /* If the register is not valid for MODE, return 0. Note we
1230 have to check both OP and OP + I since they may refer to
1231 different parts of the register file.
1233 Consider if OP refers to the last 96bit FP register and we want
1234 subword 3 because that subword is known to contain a value we
1236 if (REGNO (op) < FIRST_PSEUDO_REGISTER
1237 && (! HARD_REGNO_MODE_OK (REGNO (op), word_mode)
1238 || ! HARD_REGNO_MODE_OK (REGNO (op) + i, word_mode)))
1240 else if (REGNO (op) >= FIRST_PSEUDO_REGISTER
1241 || (REG_FUNCTION_VALUE_P (op)
1242 && rtx_equal_function_value_matters)
1243 /* We want to keep the stack, frame, and arg pointers
1245 || op == frame_pointer_rtx
1246 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1247 || op == arg_pointer_rtx
1249 || op == stack_pointer_rtx)
1250 return gen_rtx_SUBREG (word_mode, op, i);
1252 return gen_rtx_REG (word_mode, REGNO (op) + i);
1254 else if (GET_CODE (op) == SUBREG)
1255 return gen_rtx_SUBREG (word_mode, SUBREG_REG (op), i + SUBREG_WORD (op));
1256 else if (GET_CODE (op) == CONCAT)
1258 unsigned int partwords
1259 = GET_MODE_UNIT_SIZE (GET_MODE (op)) / UNITS_PER_WORD;
1262 return operand_subword (XEXP (op, 0), i, validate_address, mode);
1263 return operand_subword (XEXP (op, 1), i - partwords,
1264 validate_address, mode);
1267 /* Form a new MEM at the requested address. */
1268 if (GET_CODE (op) == MEM)
1270 rtx addr = plus_constant (XEXP (op, 0), i * UNITS_PER_WORD);
1273 if (validate_address)
1275 if (reload_completed)
1277 if (! strict_memory_address_p (word_mode, addr))
1281 addr = memory_address (word_mode, addr);
1284 new = gen_rtx_MEM (word_mode, addr);
1286 MEM_COPY_ATTRIBUTES (new, op);
1287 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (op);
1288 MEM_ALIAS_SET (new) = MEM_ALIAS_SET (op);
1293 /* The only remaining cases are when OP is a constant. If the host and
1294 target floating formats are the same, handling two-word floating
1295 constants are easy. Note that REAL_VALUE_TO_TARGET_{SINGLE,DOUBLE}
1296 are defined as returning one or two 32 bit values, respectively,
1297 and not values of BITS_PER_WORD bits. */
1298 #ifdef REAL_ARITHMETIC
1299 /* The output is some bits, the width of the target machine's word.
1300 A wider-word host can surely hold them in a CONST_INT. A narrower-word
1302 if (HOST_BITS_PER_WIDE_INT >= BITS_PER_WORD
1303 && GET_MODE_CLASS (mode) == MODE_FLOAT
1304 && GET_MODE_BITSIZE (mode) == 64
1305 && GET_CODE (op) == CONST_DOUBLE)
1310 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1311 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
1313 /* We handle 32-bit and >= 64-bit words here. Note that the order in
1314 which the words are written depends on the word endianness.
1315 ??? This is a potential portability problem and should
1316 be fixed at some point.
1318 We must excercise caution with the sign bit. By definition there
1319 are 32 significant bits in K; there may be more in a HOST_WIDE_INT.
1320 Consider a host with a 32-bit long and a 64-bit HOST_WIDE_INT.
1321 So we explicitly mask and sign-extend as necessary. */
1322 if (BITS_PER_WORD == 32)
1325 val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000;
1326 return GEN_INT (val);
1328 #if HOST_BITS_PER_WIDE_INT >= 64
1329 else if (BITS_PER_WORD >= 64 && i == 0)
1331 val = k[! WORDS_BIG_ENDIAN];
1332 val = (((val & 0xffffffff) ^ 0x80000000) - 0x80000000) << 32;
1333 val |= (HOST_WIDE_INT) k[WORDS_BIG_ENDIAN] & 0xffffffff;
1334 return GEN_INT (val);
1337 else if (BITS_PER_WORD == 16)
1340 if ((i & 1) == !WORDS_BIG_ENDIAN)
1343 return GEN_INT (val);
1348 else if (HOST_BITS_PER_WIDE_INT >= BITS_PER_WORD
1349 && GET_MODE_CLASS (mode) == MODE_FLOAT
1350 && GET_MODE_BITSIZE (mode) > 64
1351 && GET_CODE (op) == CONST_DOUBLE)
1356 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1357 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
1359 if (BITS_PER_WORD == 32)
1362 val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000;
1363 return GEN_INT (val);
1365 #if HOST_BITS_PER_WIDE_INT >= 64
1366 else if (BITS_PER_WORD >= 64 && i <= 1)
1368 val = k[i*2 + ! WORDS_BIG_ENDIAN];
1369 val = (((val & 0xffffffff) ^ 0x80000000) - 0x80000000) << 32;
1370 val |= (HOST_WIDE_INT) k[i*2 + WORDS_BIG_ENDIAN] & 0xffffffff;
1371 return GEN_INT (val);
1377 #else /* no REAL_ARITHMETIC */
1378 if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT
1379 && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
1380 || flag_pretend_float)
1381 && GET_MODE_CLASS (mode) == MODE_FLOAT
1382 && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD
1383 && GET_CODE (op) == CONST_DOUBLE)
1385 /* The constant is stored in the host's word-ordering,
1386 but we want to access it in the target's word-ordering. Some
1387 compilers don't like a conditional inside macro args, so we have two
1388 copies of the return. */
1389 #ifdef HOST_WORDS_BIG_ENDIAN
1390 return GEN_INT (i == WORDS_BIG_ENDIAN
1391 ? CONST_DOUBLE_HIGH (op) : CONST_DOUBLE_LOW (op));
1393 return GEN_INT (i != WORDS_BIG_ENDIAN
1394 ? CONST_DOUBLE_HIGH (op) : CONST_DOUBLE_LOW (op));
1397 #endif /* no REAL_ARITHMETIC */
1399 /* Single word float is a little harder, since single- and double-word
1400 values often do not have the same high-order bits. We have already
1401 verified that we want the only defined word of the single-word value. */
1402 #ifdef REAL_ARITHMETIC
1403 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1404 && GET_MODE_BITSIZE (mode) == 32
1405 && GET_CODE (op) == CONST_DOUBLE)
1410 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1411 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
1413 /* Sign extend from known 32-bit value to HOST_WIDE_INT. */
1415 val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000;
1417 if (BITS_PER_WORD == 16)
1419 if ((i & 1) == !WORDS_BIG_ENDIAN)
1424 return GEN_INT (val);
1427 if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT
1428 && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
1429 || flag_pretend_float)
1430 && sizeof (float) * 8 == HOST_BITS_PER_WIDE_INT
1431 && GET_MODE_CLASS (mode) == MODE_FLOAT
1432 && GET_MODE_SIZE (mode) == UNITS_PER_WORD
1433 && GET_CODE (op) == CONST_DOUBLE)
1436 union {float f; HOST_WIDE_INT i; } u;
1438 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
1441 return GEN_INT (u.i);
1443 if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT
1444 && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
1445 || flag_pretend_float)
1446 && sizeof (double) * 8 == HOST_BITS_PER_WIDE_INT
1447 && GET_MODE_CLASS (mode) == MODE_FLOAT
1448 && GET_MODE_SIZE (mode) == UNITS_PER_WORD
1449 && GET_CODE (op) == CONST_DOUBLE)
1452 union {double d; HOST_WIDE_INT i; } u;
1454 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
1457 return GEN_INT (u.i);
1459 #endif /* no REAL_ARITHMETIC */
1461 /* The only remaining cases that we can handle are integers.
1462 Convert to proper endianness now since these cases need it.
1463 At this point, i == 0 means the low-order word.
1465 We do not want to handle the case when BITS_PER_WORD <= HOST_BITS_PER_INT
1466 in general. However, if OP is (const_int 0), we can just return
1469 if (op == const0_rtx)
1472 if (GET_MODE_CLASS (mode) != MODE_INT
1473 || (GET_CODE (op) != CONST_INT && GET_CODE (op) != CONST_DOUBLE)
1474 || BITS_PER_WORD > HOST_BITS_PER_WIDE_INT)
1477 if (WORDS_BIG_ENDIAN)
1478 i = GET_MODE_SIZE (mode) / UNITS_PER_WORD - 1 - i;
1480 /* Find out which word on the host machine this value is in and get
1481 it from the constant. */
1482 val = (i / size_ratio == 0
1483 ? (GET_CODE (op) == CONST_INT ? INTVAL (op) : CONST_DOUBLE_LOW (op))
1484 : (GET_CODE (op) == CONST_INT
1485 ? (INTVAL (op) < 0 ? ~0 : 0) : CONST_DOUBLE_HIGH (op)));
1487 /* Get the value we want into the low bits of val. */
1488 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT)
1489 val = ((val >> ((i % size_ratio) * BITS_PER_WORD)));
1491 val = trunc_int_for_mode (val, word_mode);
1493 return GEN_INT (val);
1496 /* Similar to `operand_subword', but never return 0. If we can't extract
1497 the required subword, put OP into a register and try again. If that fails,
1498 abort. We always validate the address in this case. It is not valid
1499 to call this function after reload; it is mostly meant for RTL
1502 MODE is the mode of OP, in case it is CONST_INT. */
1505 operand_subword_force (op, i, mode)
1508 enum machine_mode mode;
1510 rtx result = operand_subword (op, i, 1, mode);
1515 if (mode != BLKmode && mode != VOIDmode)
1517 /* If this is a register which can not be accessed by words, copy it
1518 to a pseudo register. */
1519 if (GET_CODE (op) == REG)
1520 op = copy_to_reg (op);
1522 op = force_reg (mode, op);
1525 result = operand_subword (op, i, 1, mode);
1532 /* Given a compare instruction, swap the operands.
1533 A test instruction is changed into a compare of 0 against the operand. */
1536 reverse_comparison (insn)
1539 rtx body = PATTERN (insn);
1542 if (GET_CODE (body) == SET)
1543 comp = SET_SRC (body);
1545 comp = SET_SRC (XVECEXP (body, 0, 0));
1547 if (GET_CODE (comp) == COMPARE)
1549 rtx op0 = XEXP (comp, 0);
1550 rtx op1 = XEXP (comp, 1);
1551 XEXP (comp, 0) = op1;
1552 XEXP (comp, 1) = op0;
1556 rtx new = gen_rtx_COMPARE (VOIDmode,
1557 CONST0_RTX (GET_MODE (comp)), comp);
1558 if (GET_CODE (body) == SET)
1559 SET_SRC (body) = new;
1561 SET_SRC (XVECEXP (body, 0, 0)) = new;
1565 /* Return a memory reference like MEMREF, but with its mode changed
1566 to MODE and its address changed to ADDR.
1567 (VOIDmode means don't change the mode.
1568 NULL for ADDR means don't change the address.) */
1571 change_address (memref, mode, addr)
1573 enum machine_mode mode;
1578 if (GET_CODE (memref) != MEM)
1580 if (mode == VOIDmode)
1581 mode = GET_MODE (memref);
1583 addr = XEXP (memref, 0);
1585 /* If reload is in progress or has completed, ADDR must be valid.
1586 Otherwise, we can call memory_address to make it valid. */
1587 if (reload_completed || reload_in_progress)
1589 if (! memory_address_p (mode, addr))
1593 addr = memory_address (mode, addr);
1595 if (rtx_equal_p (addr, XEXP (memref, 0)) && mode == GET_MODE (memref))
1598 new = gen_rtx_MEM (mode, addr);
1599 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (memref);
1600 MEM_COPY_ATTRIBUTES (new, memref);
1601 MEM_ALIAS_SET (new) = MEM_ALIAS_SET (memref);
1605 /* Return a newly created CODE_LABEL rtx with a unique label number. */
1612 label = gen_rtx_CODE_LABEL (VOIDmode, 0, NULL_RTX,
1613 NULL_RTX, label_num++, NULL_PTR, NULL_PTR);
1615 LABEL_NUSES (label) = 0;
1616 LABEL_ALTERNATE_NAME (label) = NULL;
1620 /* For procedure integration. */
1622 /* Install new pointers to the first and last insns in the chain.
1623 Also, set cur_insn_uid to one higher than the last in use.
1624 Used for an inline-procedure after copying the insn chain. */
1627 set_new_first_and_last_insn (first, last)
1636 for (insn = first; insn; insn = NEXT_INSN (insn))
1637 cur_insn_uid = MAX (cur_insn_uid, INSN_UID (insn));
1642 /* Set the range of label numbers found in the current function.
1643 This is used when belatedly compiling an inline function. */
1646 set_new_first_and_last_label_num (first, last)
1649 base_label_num = label_num;
1650 first_label_num = first;
1651 last_label_num = last;
1654 /* Set the last label number found in the current function.
1655 This is used when belatedly compiling an inline function. */
1658 set_new_last_label_num (last)
1661 base_label_num = label_num;
1662 last_label_num = last;
1665 /* Restore all variables describing the current status from the structure *P.
1666 This is used after a nested function. */
1669 restore_emit_status (p)
1670 struct function *p ATTRIBUTE_UNUSED;
1673 clear_emit_caches ();
1676 /* Clear out all parts of the state in F that can safely be discarded
1677 after the function has been compiled, to let garbage collection
1678 reclaim the memory. */
1681 free_emit_status (f)
1684 free (f->emit->x_regno_reg_rtx);
1685 free (f->emit->regno_pointer_flag);
1686 free (f->emit->regno_pointer_align);
1691 /* Go through all the RTL insn bodies and copy any invalid shared
1692 structure. This routine should only be called once. */
1695 unshare_all_rtl (fndecl, insn)
1701 /* Make sure that virtual parameters are not shared. */
1702 for (decl = DECL_ARGUMENTS (fndecl); decl; decl = TREE_CHAIN (decl))
1703 copy_rtx_if_shared (DECL_RTL (decl));
1705 /* Unshare just about everything else. */
1706 unshare_all_rtl_1 (insn);
1708 /* Make sure the addresses of stack slots found outside the insn chain
1709 (such as, in DECL_RTL of a variable) are not shared
1710 with the insn chain.
1712 This special care is necessary when the stack slot MEM does not
1713 actually appear in the insn chain. If it does appear, its address
1714 is unshared from all else at that point. */
1715 copy_rtx_if_shared (stack_slot_list);
1718 /* Go through all the RTL insn bodies and copy any invalid shared
1719 structure, again. This is a fairly expensive thing to do so it
1720 should be done sparingly. */
1723 unshare_all_rtl_again (insn)
1729 for (p = insn; p; p = NEXT_INSN (p))
1730 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
1732 reset_used_flags (PATTERN (p));
1733 reset_used_flags (REG_NOTES (p));
1734 reset_used_flags (LOG_LINKS (p));
1737 /* Make sure that virtual parameters are not shared. */
1738 for (decl = DECL_ARGUMENTS (cfun->decl); decl; decl = TREE_CHAIN (decl))
1739 reset_used_flags (DECL_RTL (decl));
1741 reset_used_flags (stack_slot_list);
1743 unshare_all_rtl (cfun->decl, insn);
1746 /* Go through all the RTL insn bodies and copy any invalid shared structure.
1747 Assumes the mark bits are cleared at entry. */
1750 unshare_all_rtl_1 (insn)
1753 for (; insn; insn = NEXT_INSN (insn))
1754 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1756 PATTERN (insn) = copy_rtx_if_shared (PATTERN (insn));
1757 REG_NOTES (insn) = copy_rtx_if_shared (REG_NOTES (insn));
1758 LOG_LINKS (insn) = copy_rtx_if_shared (LOG_LINKS (insn));
1762 /* Mark ORIG as in use, and return a copy of it if it was already in use.
1763 Recursively does the same for subexpressions. */
1766 copy_rtx_if_shared (orig)
1769 register rtx x = orig;
1771 register enum rtx_code code;
1772 register const char *format_ptr;
1778 code = GET_CODE (x);
1780 /* These types may be freely shared. */
1793 /* SCRATCH must be shared because they represent distinct values. */
1797 /* CONST can be shared if it contains a SYMBOL_REF. If it contains
1798 a LABEL_REF, it isn't sharable. */
1799 if (GET_CODE (XEXP (x, 0)) == PLUS
1800 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
1801 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
1810 /* The chain of insns is not being copied. */
1814 /* A MEM is allowed to be shared if its address is constant.
1816 We used to allow sharing of MEMs which referenced
1817 virtual_stack_vars_rtx or virtual_incoming_args_rtx, but
1818 that can lose. instantiate_virtual_regs will not unshare
1819 the MEMs, and combine may change the structure of the address
1820 because it looks safe and profitable in one context, but
1821 in some other context it creates unrecognizable RTL. */
1822 if (CONSTANT_ADDRESS_P (XEXP (x, 0)))
1831 /* This rtx may not be shared. If it has already been seen,
1832 replace it with a copy of itself. */
1838 copy = rtx_alloc (code);
1839 bcopy ((char *) x, (char *) copy,
1840 (sizeof (*copy) - sizeof (copy->fld)
1841 + sizeof (copy->fld[0]) * GET_RTX_LENGTH (code)));
1847 /* Now scan the subexpressions recursively.
1848 We can store any replaced subexpressions directly into X
1849 since we know X is not shared! Any vectors in X
1850 must be copied if X was copied. */
1852 format_ptr = GET_RTX_FORMAT (code);
1854 for (i = 0; i < GET_RTX_LENGTH (code); i++)
1856 switch (*format_ptr++)
1859 XEXP (x, i) = copy_rtx_if_shared (XEXP (x, i));
1863 if (XVEC (x, i) != NULL)
1866 int len = XVECLEN (x, i);
1868 if (copied && len > 0)
1869 XVEC (x, i) = gen_rtvec_v (len, XVEC (x, i)->elem);
1870 for (j = 0; j < len; j++)
1871 XVECEXP (x, i, j) = copy_rtx_if_shared (XVECEXP (x, i, j));
1879 /* Clear all the USED bits in X to allow copy_rtx_if_shared to be used
1880 to look for shared sub-parts. */
1883 reset_used_flags (x)
1887 register enum rtx_code code;
1888 register const char *format_ptr;
1893 code = GET_CODE (x);
1895 /* These types may be freely shared so we needn't do any resetting
1916 /* The chain of insns is not being copied. */
1925 format_ptr = GET_RTX_FORMAT (code);
1926 for (i = 0; i < GET_RTX_LENGTH (code); i++)
1928 switch (*format_ptr++)
1931 reset_used_flags (XEXP (x, i));
1935 for (j = 0; j < XVECLEN (x, i); j++)
1936 reset_used_flags (XVECEXP (x, i, j));
1942 /* Copy X if necessary so that it won't be altered by changes in OTHER.
1943 Return X or the rtx for the pseudo reg the value of X was copied into.
1944 OTHER must be valid as a SET_DEST. */
1947 make_safe_from (x, other)
1951 switch (GET_CODE (other))
1954 other = SUBREG_REG (other);
1956 case STRICT_LOW_PART:
1959 other = XEXP (other, 0);
1965 if ((GET_CODE (other) == MEM
1967 && GET_CODE (x) != REG
1968 && GET_CODE (x) != SUBREG)
1969 || (GET_CODE (other) == REG
1970 && (REGNO (other) < FIRST_PSEUDO_REGISTER
1971 || reg_mentioned_p (other, x))))
1973 rtx temp = gen_reg_rtx (GET_MODE (x));
1974 emit_move_insn (temp, x);
1980 /* Emission of insns (adding them to the doubly-linked list). */
1982 /* Return the first insn of the current sequence or current function. */
1990 /* Return the last insn emitted in current sequence or current function. */
1998 /* Specify a new insn as the last in the chain. */
2001 set_last_insn (insn)
2004 if (NEXT_INSN (insn) != 0)
2009 /* Return the last insn emitted, even if it is in a sequence now pushed. */
2012 get_last_insn_anywhere ()
2014 struct sequence_stack *stack;
2017 for (stack = seq_stack; stack; stack = stack->next)
2018 if (stack->last != 0)
2023 /* Return a number larger than any instruction's uid in this function. */
2028 return cur_insn_uid;
2031 /* Renumber instructions so that no instruction UIDs are wasted. */
2034 renumber_insns (stream)
2039 /* If we're not supposed to renumber instructions, don't. */
2040 if (!flag_renumber_insns)
2043 /* If there aren't that many instructions, then it's not really
2044 worth renumbering them. */
2045 if (flag_renumber_insns == 1 && get_max_uid () < 25000)
2050 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
2053 fprintf (stream, "Renumbering insn %d to %d\n",
2054 INSN_UID (insn), cur_insn_uid);
2055 INSN_UID (insn) = cur_insn_uid++;
2059 /* Return the next insn. If it is a SEQUENCE, return the first insn
2068 insn = NEXT_INSN (insn);
2069 if (insn && GET_CODE (insn) == INSN
2070 && GET_CODE (PATTERN (insn)) == SEQUENCE)
2071 insn = XVECEXP (PATTERN (insn), 0, 0);
2077 /* Return the previous insn. If it is a SEQUENCE, return the last insn
2081 previous_insn (insn)
2086 insn = PREV_INSN (insn);
2087 if (insn && GET_CODE (insn) == INSN
2088 && GET_CODE (PATTERN (insn)) == SEQUENCE)
2089 insn = XVECEXP (PATTERN (insn), 0, XVECLEN (PATTERN (insn), 0) - 1);
2095 /* Return the next insn after INSN that is not a NOTE. This routine does not
2096 look inside SEQUENCEs. */
2099 next_nonnote_insn (insn)
2104 insn = NEXT_INSN (insn);
2105 if (insn == 0 || GET_CODE (insn) != NOTE)
2112 /* Return the previous insn before INSN that is not a NOTE. This routine does
2113 not look inside SEQUENCEs. */
2116 prev_nonnote_insn (insn)
2121 insn = PREV_INSN (insn);
2122 if (insn == 0 || GET_CODE (insn) != NOTE)
2129 /* Return the next INSN, CALL_INSN or JUMP_INSN after INSN;
2130 or 0, if there is none. This routine does not look inside
2134 next_real_insn (insn)
2139 insn = NEXT_INSN (insn);
2140 if (insn == 0 || GET_CODE (insn) == INSN
2141 || GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN)
2148 /* Return the last INSN, CALL_INSN or JUMP_INSN before INSN;
2149 or 0, if there is none. This routine does not look inside
2153 prev_real_insn (insn)
2158 insn = PREV_INSN (insn);
2159 if (insn == 0 || GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN
2160 || GET_CODE (insn) == JUMP_INSN)
2167 /* Find the next insn after INSN that really does something. This routine
2168 does not look inside SEQUENCEs. Until reload has completed, this is the
2169 same as next_real_insn. */
2172 active_insn_p (insn)
2175 return (GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN
2176 || (GET_CODE (insn) == INSN
2177 && (! reload_completed
2178 || (GET_CODE (PATTERN (insn)) != USE
2179 && GET_CODE (PATTERN (insn)) != CLOBBER))));
2183 next_active_insn (insn)
2188 insn = NEXT_INSN (insn);
2189 if (insn == 0 || active_insn_p (insn))
2196 /* Find the last insn before INSN that really does something. This routine
2197 does not look inside SEQUENCEs. Until reload has completed, this is the
2198 same as prev_real_insn. */
2201 prev_active_insn (insn)
2206 insn = PREV_INSN (insn);
2207 if (insn == 0 || active_insn_p (insn))
2214 /* Return the next CODE_LABEL after the insn INSN, or 0 if there is none. */
2222 insn = NEXT_INSN (insn);
2223 if (insn == 0 || GET_CODE (insn) == CODE_LABEL)
2230 /* Return the last CODE_LABEL before the insn INSN, or 0 if there is none. */
2238 insn = PREV_INSN (insn);
2239 if (insn == 0 || GET_CODE (insn) == CODE_LABEL)
2247 /* INSN uses CC0 and is being moved into a delay slot. Set up REG_CC_SETTER
2248 and REG_CC_USER notes so we can find it. */
2251 link_cc0_insns (insn)
2254 rtx user = next_nonnote_insn (insn);
2256 if (GET_CODE (user) == INSN && GET_CODE (PATTERN (user)) == SEQUENCE)
2257 user = XVECEXP (PATTERN (user), 0, 0);
2259 REG_NOTES (user) = gen_rtx_INSN_LIST (REG_CC_SETTER, insn,
2261 REG_NOTES (insn) = gen_rtx_INSN_LIST (REG_CC_USER, user, REG_NOTES (insn));
2264 /* Return the next insn that uses CC0 after INSN, which is assumed to
2265 set it. This is the inverse of prev_cc0_setter (i.e., prev_cc0_setter
2266 applied to the result of this function should yield INSN).
2268 Normally, this is simply the next insn. However, if a REG_CC_USER note
2269 is present, it contains the insn that uses CC0.
2271 Return 0 if we can't find the insn. */
2274 next_cc0_user (insn)
2277 rtx note = find_reg_note (insn, REG_CC_USER, NULL_RTX);
2280 return XEXP (note, 0);
2282 insn = next_nonnote_insn (insn);
2283 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
2284 insn = XVECEXP (PATTERN (insn), 0, 0);
2286 if (insn && GET_RTX_CLASS (GET_CODE (insn)) == 'i'
2287 && reg_mentioned_p (cc0_rtx, PATTERN (insn)))
2293 /* Find the insn that set CC0 for INSN. Unless INSN has a REG_CC_SETTER
2294 note, it is the previous insn. */
2297 prev_cc0_setter (insn)
2300 rtx note = find_reg_note (insn, REG_CC_SETTER, NULL_RTX);
2303 return XEXP (note, 0);
2305 insn = prev_nonnote_insn (insn);
2306 if (! sets_cc0_p (PATTERN (insn)))
2313 /* Try splitting insns that can be split for better scheduling.
2314 PAT is the pattern which might split.
2315 TRIAL is the insn providing PAT.
2316 LAST is non-zero if we should return the last insn of the sequence produced.
2318 If this routine succeeds in splitting, it returns the first or last
2319 replacement insn depending on the value of LAST. Otherwise, it
2320 returns TRIAL. If the insn to be returned can be split, it will be. */
2323 try_split (pat, trial, last)
2327 rtx before = PREV_INSN (trial);
2328 rtx after = NEXT_INSN (trial);
2329 rtx seq = split_insns (pat, trial);
2330 int has_barrier = 0;
2333 /* If we are splitting a JUMP_INSN, it might be followed by a BARRIER.
2334 We may need to handle this specially. */
2335 if (after && GET_CODE (after) == BARRIER)
2338 after = NEXT_INSN (after);
2343 /* SEQ can either be a SEQUENCE or the pattern of a single insn.
2344 The latter case will normally arise only when being done so that
2345 it, in turn, will be split (SFmode on the 29k is an example). */
2346 if (GET_CODE (seq) == SEQUENCE)
2350 /* Avoid infinite loop if any insn of the result matches
2351 the original pattern. */
2352 for (i = 0; i < XVECLEN (seq, 0); i++)
2353 if (GET_CODE (XVECEXP (seq, 0, i)) == INSN
2354 && rtx_equal_p (PATTERN (XVECEXP (seq, 0, i)), pat))
2357 /* If we are splitting a JUMP_INSN, look for the JUMP_INSN in
2358 SEQ and copy our JUMP_LABEL to it. If JUMP_LABEL is non-zero,
2359 increment the usage count so we don't delete the label. */
2361 if (GET_CODE (trial) == JUMP_INSN)
2362 for (i = XVECLEN (seq, 0) - 1; i >= 0; i--)
2363 if (GET_CODE (XVECEXP (seq, 0, i)) == JUMP_INSN)
2365 JUMP_LABEL (XVECEXP (seq, 0, i)) = JUMP_LABEL (trial);
2367 if (JUMP_LABEL (trial))
2368 LABEL_NUSES (JUMP_LABEL (trial))++;
2371 tem = emit_insn_after (seq, before);
2373 delete_insn (trial);
2375 emit_barrier_after (tem);
2377 /* Recursively call try_split for each new insn created; by the
2378 time control returns here that insn will be fully split, so
2379 set LAST and continue from the insn after the one returned.
2380 We can't use next_active_insn here since AFTER may be a note.
2381 Ignore deleted insns, which can be occur if not optimizing. */
2382 for (tem = NEXT_INSN (before); tem != after;
2383 tem = NEXT_INSN (tem))
2384 if (! INSN_DELETED_P (tem)
2385 && GET_RTX_CLASS (GET_CODE (tem)) == 'i')
2386 tem = try_split (PATTERN (tem), tem, 1);
2388 /* Avoid infinite loop if the result matches the original pattern. */
2389 else if (rtx_equal_p (seq, pat))
2393 PATTERN (trial) = seq;
2394 INSN_CODE (trial) = -1;
2395 try_split (seq, trial, last);
2398 /* Return either the first or the last insn, depending on which was
2401 ? (after ? prev_active_insn (after) : last_insn)
2402 : next_active_insn (before);
2408 /* Make and return an INSN rtx, initializing all its slots.
2409 Store PATTERN in the pattern slots. */
2412 make_insn_raw (pattern)
2417 /* If in RTL generation phase, see if FREE_INSN can be used. */
2418 if (!ggc_p && free_insn != 0 && rtx_equal_function_value_matters)
2421 free_insn = NEXT_INSN (free_insn);
2422 PUT_CODE (insn, INSN);
2425 insn = rtx_alloc (INSN);
2427 INSN_UID (insn) = cur_insn_uid++;
2428 PATTERN (insn) = pattern;
2429 INSN_CODE (insn) = -1;
2430 LOG_LINKS (insn) = NULL;
2431 REG_NOTES (insn) = NULL;
2433 #ifdef ENABLE_RTL_CHECKING
2435 && GET_RTX_CLASS (GET_CODE (insn)) == 'i'
2436 && (returnjump_p (insn)
2437 || (GET_CODE (insn) == SET
2438 && SET_DEST (insn) == pc_rtx)))
2440 warning ("ICE: emit_insn used where emit_jump_insn needed:\n");
2448 /* Like `make_insn' but make a JUMP_INSN instead of an insn. */
2451 make_jump_insn_raw (pattern)
2456 insn = rtx_alloc (JUMP_INSN);
2457 INSN_UID (insn) = cur_insn_uid++;
2459 PATTERN (insn) = pattern;
2460 INSN_CODE (insn) = -1;
2461 LOG_LINKS (insn) = NULL;
2462 REG_NOTES (insn) = NULL;
2463 JUMP_LABEL (insn) = NULL;
2468 /* Like `make_insn' but make a CALL_INSN instead of an insn. */
2471 make_call_insn_raw (pattern)
2476 insn = rtx_alloc (CALL_INSN);
2477 INSN_UID (insn) = cur_insn_uid++;
2479 PATTERN (insn) = pattern;
2480 INSN_CODE (insn) = -1;
2481 LOG_LINKS (insn) = NULL;
2482 REG_NOTES (insn) = NULL;
2483 CALL_INSN_FUNCTION_USAGE (insn) = NULL;
2488 /* Add INSN to the end of the doubly-linked list.
2489 INSN may be an INSN, JUMP_INSN, CALL_INSN, CODE_LABEL, BARRIER or NOTE. */
2495 PREV_INSN (insn) = last_insn;
2496 NEXT_INSN (insn) = 0;
2498 if (NULL != last_insn)
2499 NEXT_INSN (last_insn) = insn;
2501 if (NULL == first_insn)
2507 /* Add INSN into the doubly-linked list after insn AFTER. This and
2508 the next should be the only functions called to insert an insn once
2509 delay slots have been filled since only they know how to update a
2513 add_insn_after (insn, after)
2516 rtx next = NEXT_INSN (after);
2518 if (optimize && INSN_DELETED_P (after))
2521 NEXT_INSN (insn) = next;
2522 PREV_INSN (insn) = after;
2526 PREV_INSN (next) = insn;
2527 if (GET_CODE (next) == INSN && GET_CODE (PATTERN (next)) == SEQUENCE)
2528 PREV_INSN (XVECEXP (PATTERN (next), 0, 0)) = insn;
2530 else if (last_insn == after)
2534 struct sequence_stack *stack = seq_stack;
2535 /* Scan all pending sequences too. */
2536 for (; stack; stack = stack->next)
2537 if (after == stack->last)
2547 NEXT_INSN (after) = insn;
2548 if (GET_CODE (after) == INSN && GET_CODE (PATTERN (after)) == SEQUENCE)
2550 rtx sequence = PATTERN (after);
2551 NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = insn;
2555 /* Add INSN into the doubly-linked list before insn BEFORE. This and
2556 the previous should be the only functions called to insert an insn once
2557 delay slots have been filled since only they know how to update a
2561 add_insn_before (insn, before)
2564 rtx prev = PREV_INSN (before);
2566 if (optimize && INSN_DELETED_P (before))
2569 PREV_INSN (insn) = prev;
2570 NEXT_INSN (insn) = before;
2574 NEXT_INSN (prev) = insn;
2575 if (GET_CODE (prev) == INSN && GET_CODE (PATTERN (prev)) == SEQUENCE)
2577 rtx sequence = PATTERN (prev);
2578 NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = insn;
2581 else if (first_insn == before)
2585 struct sequence_stack *stack = seq_stack;
2586 /* Scan all pending sequences too. */
2587 for (; stack; stack = stack->next)
2588 if (before == stack->first)
2590 stack->first = insn;
2598 PREV_INSN (before) = insn;
2599 if (GET_CODE (before) == INSN && GET_CODE (PATTERN (before)) == SEQUENCE)
2600 PREV_INSN (XVECEXP (PATTERN (before), 0, 0)) = insn;
2603 /* Remove an insn from its doubly-linked list. This function knows how
2604 to handle sequences. */
2609 rtx next = NEXT_INSN (insn);
2610 rtx prev = PREV_INSN (insn);
2613 NEXT_INSN (prev) = next;
2614 if (GET_CODE (prev) == INSN && GET_CODE (PATTERN (prev)) == SEQUENCE)
2616 rtx sequence = PATTERN (prev);
2617 NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = next;
2620 else if (first_insn == insn)
2624 struct sequence_stack *stack = seq_stack;
2625 /* Scan all pending sequences too. */
2626 for (; stack; stack = stack->next)
2627 if (insn == stack->first)
2629 stack->first = next;
2639 PREV_INSN (next) = prev;
2640 if (GET_CODE (next) == INSN && GET_CODE (PATTERN (next)) == SEQUENCE)
2641 PREV_INSN (XVECEXP (PATTERN (next), 0, 0)) = prev;
2643 else if (last_insn == insn)
2647 struct sequence_stack *stack = seq_stack;
2648 /* Scan all pending sequences too. */
2649 for (; stack; stack = stack->next)
2650 if (insn == stack->last)
2661 /* Delete all insns made since FROM.
2662 FROM becomes the new last instruction. */
2665 delete_insns_since (from)
2671 NEXT_INSN (from) = 0;
2675 /* This function is deprecated, please use sequences instead.
2677 Move a consecutive bunch of insns to a different place in the chain.
2678 The insns to be moved are those between FROM and TO.
2679 They are moved to a new position after the insn AFTER.
2680 AFTER must not be FROM or TO or any insn in between.
2682 This function does not know about SEQUENCEs and hence should not be
2683 called after delay-slot filling has been done. */
2686 reorder_insns (from, to, after)
2687 rtx from, to, after;
2689 /* Splice this bunch out of where it is now. */
2690 if (PREV_INSN (from))
2691 NEXT_INSN (PREV_INSN (from)) = NEXT_INSN (to);
2693 PREV_INSN (NEXT_INSN (to)) = PREV_INSN (from);
2694 if (last_insn == to)
2695 last_insn = PREV_INSN (from);
2696 if (first_insn == from)
2697 first_insn = NEXT_INSN (to);
2699 /* Make the new neighbors point to it and it to them. */
2700 if (NEXT_INSN (after))
2701 PREV_INSN (NEXT_INSN (after)) = to;
2703 NEXT_INSN (to) = NEXT_INSN (after);
2704 PREV_INSN (from) = after;
2705 NEXT_INSN (after) = from;
2706 if (after == last_insn)
2710 /* Return the line note insn preceding INSN. */
2713 find_line_note (insn)
2716 if (no_line_numbers)
2719 for (; insn; insn = PREV_INSN (insn))
2720 if (GET_CODE (insn) == NOTE
2721 && NOTE_LINE_NUMBER (insn) >= 0)
2727 /* Like reorder_insns, but inserts line notes to preserve the line numbers
2728 of the moved insns when debugging. This may insert a note between AFTER
2729 and FROM, and another one after TO. */
2732 reorder_insns_with_line_notes (from, to, after)
2733 rtx from, to, after;
2735 rtx from_line = find_line_note (from);
2736 rtx after_line = find_line_note (after);
2738 reorder_insns (from, to, after);
2740 if (from_line == after_line)
2744 emit_line_note_after (NOTE_SOURCE_FILE (from_line),
2745 NOTE_LINE_NUMBER (from_line),
2748 emit_line_note_after (NOTE_SOURCE_FILE (after_line),
2749 NOTE_LINE_NUMBER (after_line),
2753 /* Remove unncessary notes from the instruction stream. */
2756 remove_unncessary_notes ()
2761 /* We must not remove the first instruction in the function because
2762 the compiler depends on the first instruction being a note. */
2763 for (insn = NEXT_INSN (get_insns ()); insn; insn = next)
2765 /* Remember what's next. */
2766 next = NEXT_INSN (insn);
2768 /* We're only interested in notes. */
2769 if (GET_CODE (insn) != NOTE)
2772 /* By now, all notes indicating lexical blocks should have
2773 NOTE_BLOCK filled in. */
2774 if ((NOTE_LINE_NUMBER (insn) == NOTE_INSN_BLOCK_BEG
2775 || NOTE_LINE_NUMBER (insn) == NOTE_INSN_BLOCK_END)
2776 && NOTE_BLOCK (insn) == NULL_TREE)
2779 /* Remove NOTE_INSN_DELETED notes. */
2780 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED)
2782 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_BLOCK_END)
2784 /* Scan back to see if there are any non-note instructions
2785 between INSN and the beginning of this block. If not,
2786 then there is no PC range in the generated code that will
2787 actually be in this block, so there's no point in
2788 remembering the existence of the block. */
2791 for (prev = PREV_INSN (insn); prev; prev = PREV_INSN (prev))
2793 /* This block contains a real instruction. Note that we
2794 don't include labels; if the only thing in the block
2795 is a label, then there are still no PC values that
2796 lie within the block. */
2797 if (GET_RTX_CLASS (GET_CODE (prev)) == 'i')
2800 /* We're only interested in NOTEs. */
2801 if (GET_CODE (prev) != NOTE)
2804 if (NOTE_LINE_NUMBER (prev) == NOTE_INSN_BLOCK_BEG)
2806 /* If the BLOCKs referred to by these notes don't
2807 match, then something is wrong with our BLOCK
2808 nesting structure. */
2809 if (NOTE_BLOCK (prev) != NOTE_BLOCK (insn))
2812 /* Never delete the BLOCK for the outermost scope
2813 of the function; we can refer to names from
2814 that scope even if the block notes are messed up. */
2815 if (! is_body_block (NOTE_BLOCK (insn)))
2817 debug_ignore_block (NOTE_BLOCK (insn));
2824 else if (NOTE_LINE_NUMBER (prev) == NOTE_INSN_BLOCK_END)
2825 /* There's a nested block. We need to leave the
2826 current block in place since otherwise the debugger
2827 wouldn't be able to show symbols from our block in
2828 the nested block. */
2836 /* Emit an insn of given code and pattern
2837 at a specified place within the doubly-linked list. */
2839 /* Make an instruction with body PATTERN
2840 and output it before the instruction BEFORE. */
2843 emit_insn_before (pattern, before)
2844 register rtx pattern, before;
2846 register rtx insn = before;
2848 if (GET_CODE (pattern) == SEQUENCE)
2852 for (i = 0; i < XVECLEN (pattern, 0); i++)
2854 insn = XVECEXP (pattern, 0, i);
2855 add_insn_before (insn, before);
2857 if (!ggc_p && XVECLEN (pattern, 0) < SEQUENCE_RESULT_SIZE)
2858 sequence_result[XVECLEN (pattern, 0)] = pattern;
2862 insn = make_insn_raw (pattern);
2863 add_insn_before (insn, before);
2869 /* Similar to emit_insn_before, but update basic block boundaries as well. */
2872 emit_block_insn_before (pattern, before, block)
2873 rtx pattern, before;
2876 rtx prev = PREV_INSN (before);
2877 rtx r = emit_insn_before (pattern, before);
2878 if (block && block->head == before)
2879 block->head = NEXT_INSN (prev);
2883 /* Make an instruction with body PATTERN and code JUMP_INSN
2884 and output it before the instruction BEFORE. */
2887 emit_jump_insn_before (pattern, before)
2888 register rtx pattern, before;
2892 if (GET_CODE (pattern) == SEQUENCE)
2893 insn = emit_insn_before (pattern, before);
2896 insn = make_jump_insn_raw (pattern);
2897 add_insn_before (insn, before);
2903 /* Make an instruction with body PATTERN and code CALL_INSN
2904 and output it before the instruction BEFORE. */
2907 emit_call_insn_before (pattern, before)
2908 register rtx pattern, before;
2912 if (GET_CODE (pattern) == SEQUENCE)
2913 insn = emit_insn_before (pattern, before);
2916 insn = make_call_insn_raw (pattern);
2917 add_insn_before (insn, before);
2918 PUT_CODE (insn, CALL_INSN);
2924 /* Make an insn of code BARRIER
2925 and output it before the insn BEFORE. */
2928 emit_barrier_before (before)
2929 register rtx before;
2931 register rtx insn = rtx_alloc (BARRIER);
2933 INSN_UID (insn) = cur_insn_uid++;
2935 add_insn_before (insn, before);
2939 /* Emit the label LABEL before the insn BEFORE. */
2942 emit_label_before (label, before)
2945 /* This can be called twice for the same label as a result of the
2946 confusion that follows a syntax error! So make it harmless. */
2947 if (INSN_UID (label) == 0)
2949 INSN_UID (label) = cur_insn_uid++;
2950 add_insn_before (label, before);
2956 /* Emit a note of subtype SUBTYPE before the insn BEFORE. */
2959 emit_note_before (subtype, before)
2963 register rtx note = rtx_alloc (NOTE);
2964 INSN_UID (note) = cur_insn_uid++;
2965 NOTE_SOURCE_FILE (note) = 0;
2966 NOTE_LINE_NUMBER (note) = subtype;
2968 add_insn_before (note, before);
2972 /* Make an insn of code INSN with body PATTERN
2973 and output it after the insn AFTER. */
2976 emit_insn_after (pattern, after)
2977 register rtx pattern, after;
2979 register rtx insn = after;
2981 if (GET_CODE (pattern) == SEQUENCE)
2985 for (i = 0; i < XVECLEN (pattern, 0); i++)
2987 insn = XVECEXP (pattern, 0, i);
2988 add_insn_after (insn, after);
2991 if (!ggc_p && XVECLEN (pattern, 0) < SEQUENCE_RESULT_SIZE)
2992 sequence_result[XVECLEN (pattern, 0)] = pattern;
2996 insn = make_insn_raw (pattern);
2997 add_insn_after (insn, after);
3003 /* Similar to emit_insn_after, except that line notes are to be inserted so
3004 as to act as if this insn were at FROM. */
3007 emit_insn_after_with_line_notes (pattern, after, from)
3008 rtx pattern, after, from;
3010 rtx from_line = find_line_note (from);
3011 rtx after_line = find_line_note (after);
3012 rtx insn = emit_insn_after (pattern, after);
3015 emit_line_note_after (NOTE_SOURCE_FILE (from_line),
3016 NOTE_LINE_NUMBER (from_line),
3020 emit_line_note_after (NOTE_SOURCE_FILE (after_line),
3021 NOTE_LINE_NUMBER (after_line),
3025 /* Similar to emit_insn_after, but update basic block boundaries as well. */
3028 emit_block_insn_after (pattern, after, block)
3032 rtx r = emit_insn_after (pattern, after);
3033 if (block && block->end == after)
3038 /* Make an insn of code JUMP_INSN with body PATTERN
3039 and output it after the insn AFTER. */
3042 emit_jump_insn_after (pattern, after)
3043 register rtx pattern, after;
3047 if (GET_CODE (pattern) == SEQUENCE)
3048 insn = emit_insn_after (pattern, after);
3051 insn = make_jump_insn_raw (pattern);
3052 add_insn_after (insn, after);
3058 /* Make an insn of code BARRIER
3059 and output it after the insn AFTER. */
3062 emit_barrier_after (after)
3065 register rtx insn = rtx_alloc (BARRIER);
3067 INSN_UID (insn) = cur_insn_uid++;
3069 add_insn_after (insn, after);
3073 /* Emit the label LABEL after the insn AFTER. */
3076 emit_label_after (label, after)
3079 /* This can be called twice for the same label
3080 as a result of the confusion that follows a syntax error!
3081 So make it harmless. */
3082 if (INSN_UID (label) == 0)
3084 INSN_UID (label) = cur_insn_uid++;
3085 add_insn_after (label, after);
3091 /* Emit a note of subtype SUBTYPE after the insn AFTER. */
3094 emit_note_after (subtype, after)
3098 register rtx note = rtx_alloc (NOTE);
3099 INSN_UID (note) = cur_insn_uid++;
3100 NOTE_SOURCE_FILE (note) = 0;
3101 NOTE_LINE_NUMBER (note) = subtype;
3102 add_insn_after (note, after);
3106 /* Emit a line note for FILE and LINE after the insn AFTER. */
3109 emit_line_note_after (file, line, after)
3116 if (no_line_numbers && line > 0)
3122 note = rtx_alloc (NOTE);
3123 INSN_UID (note) = cur_insn_uid++;
3124 NOTE_SOURCE_FILE (note) = file;
3125 NOTE_LINE_NUMBER (note) = line;
3126 add_insn_after (note, after);
3130 /* Make an insn of code INSN with pattern PATTERN
3131 and add it to the end of the doubly-linked list.
3132 If PATTERN is a SEQUENCE, take the elements of it
3133 and emit an insn for each element.
3135 Returns the last insn emitted. */
3141 rtx insn = last_insn;
3143 if (GET_CODE (pattern) == SEQUENCE)
3147 for (i = 0; i < XVECLEN (pattern, 0); i++)
3149 insn = XVECEXP (pattern, 0, i);
3152 if (!ggc_p && XVECLEN (pattern, 0) < SEQUENCE_RESULT_SIZE)
3153 sequence_result[XVECLEN (pattern, 0)] = pattern;
3157 insn = make_insn_raw (pattern);
3164 /* Emit the insns in a chain starting with INSN.
3165 Return the last insn emitted. */
3175 rtx next = NEXT_INSN (insn);
3184 /* Emit the insns in a chain starting with INSN and place them in front of
3185 the insn BEFORE. Return the last insn emitted. */
3188 emit_insns_before (insn, before)
3196 rtx next = NEXT_INSN (insn);
3197 add_insn_before (insn, before);
3205 /* Emit the insns in a chain starting with FIRST and place them in back of
3206 the insn AFTER. Return the last insn emitted. */
3209 emit_insns_after (first, after)
3214 register rtx after_after;
3222 for (last = first; NEXT_INSN (last); last = NEXT_INSN (last))
3225 after_after = NEXT_INSN (after);
3227 NEXT_INSN (after) = first;
3228 PREV_INSN (first) = after;
3229 NEXT_INSN (last) = after_after;
3231 PREV_INSN (after_after) = last;
3233 if (after == last_insn)
3238 /* Make an insn of code JUMP_INSN with pattern PATTERN
3239 and add it to the end of the doubly-linked list. */
3242 emit_jump_insn (pattern)
3245 if (GET_CODE (pattern) == SEQUENCE)
3246 return emit_insn (pattern);
3249 register rtx insn = make_jump_insn_raw (pattern);
3255 /* Make an insn of code CALL_INSN with pattern PATTERN
3256 and add it to the end of the doubly-linked list. */
3259 emit_call_insn (pattern)
3262 if (GET_CODE (pattern) == SEQUENCE)
3263 return emit_insn (pattern);
3266 register rtx insn = make_call_insn_raw (pattern);
3268 PUT_CODE (insn, CALL_INSN);
3273 /* Add the label LABEL to the end of the doubly-linked list. */
3279 /* This can be called twice for the same label
3280 as a result of the confusion that follows a syntax error!
3281 So make it harmless. */
3282 if (INSN_UID (label) == 0)
3284 INSN_UID (label) = cur_insn_uid++;
3290 /* Make an insn of code BARRIER
3291 and add it to the end of the doubly-linked list. */
3296 register rtx barrier = rtx_alloc (BARRIER);
3297 INSN_UID (barrier) = cur_insn_uid++;
3302 /* Make an insn of code NOTE
3303 with data-fields specified by FILE and LINE
3304 and add it to the end of the doubly-linked list,
3305 but only if line-numbers are desired for debugging info. */
3308 emit_line_note (file, line)
3312 set_file_and_line_for_stmt (file, line);
3315 if (no_line_numbers)
3319 return emit_note (file, line);
3322 /* Make an insn of code NOTE
3323 with data-fields specified by FILE and LINE
3324 and add it to the end of the doubly-linked list.
3325 If it is a line-number NOTE, omit it if it matches the previous one. */
3328 emit_note (file, line)
3336 if (file && last_filename && !strcmp (file, last_filename)
3337 && line == last_linenum)
3339 last_filename = file;
3340 last_linenum = line;
3343 if (no_line_numbers && line > 0)
3349 note = rtx_alloc (NOTE);
3350 INSN_UID (note) = cur_insn_uid++;
3351 NOTE_SOURCE_FILE (note) = file;
3352 NOTE_LINE_NUMBER (note) = line;
3357 /* Emit a NOTE, and don't omit it even if LINE is the previous note. */
3360 emit_line_note_force (file, line)
3365 return emit_line_note (file, line);
3368 /* Cause next statement to emit a line note even if the line number
3369 has not changed. This is used at the beginning of a function. */
3372 force_next_line_note ()
3377 /* Place a note of KIND on insn INSN with DATUM as the datum. If a
3378 note of this type already exists, remove it first. */
3381 set_unique_reg_note (insn, kind, datum)
3386 rtx note = find_reg_note (insn, kind, NULL_RTX);
3388 /* First remove the note if there already is one. */
3390 remove_note (insn, note);
3392 REG_NOTES (insn) = gen_rtx_EXPR_LIST (kind, datum, REG_NOTES (insn));
3395 /* Return an indication of which type of insn should have X as a body.
3396 The value is CODE_LABEL, INSN, CALL_INSN or JUMP_INSN. */
3402 if (GET_CODE (x) == CODE_LABEL)
3404 if (GET_CODE (x) == CALL)
3406 if (GET_CODE (x) == RETURN)
3408 if (GET_CODE (x) == SET)
3410 if (SET_DEST (x) == pc_rtx)
3412 else if (GET_CODE (SET_SRC (x)) == CALL)
3417 if (GET_CODE (x) == PARALLEL)
3420 for (j = XVECLEN (x, 0) - 1; j >= 0; j--)
3421 if (GET_CODE (XVECEXP (x, 0, j)) == CALL)
3423 else if (GET_CODE (XVECEXP (x, 0, j)) == SET
3424 && SET_DEST (XVECEXP (x, 0, j)) == pc_rtx)
3426 else if (GET_CODE (XVECEXP (x, 0, j)) == SET
3427 && GET_CODE (SET_SRC (XVECEXP (x, 0, j))) == CALL)
3433 /* Emit the rtl pattern X as an appropriate kind of insn.
3434 If X is a label, it is simply added into the insn chain. */
3440 enum rtx_code code = classify_insn (x);
3442 if (code == CODE_LABEL)
3443 return emit_label (x);
3444 else if (code == INSN)
3445 return emit_insn (x);
3446 else if (code == JUMP_INSN)
3448 register rtx insn = emit_jump_insn (x);
3449 if (simplejump_p (insn) || GET_CODE (x) == RETURN)
3450 return emit_barrier ();
3453 else if (code == CALL_INSN)
3454 return emit_call_insn (x);
3459 /* Begin emitting insns to a sequence which can be packaged in an
3460 RTL_EXPR. If this sequence will contain something that might cause
3461 the compiler to pop arguments to function calls (because those
3462 pops have previously been deferred; see INHIBIT_DEFER_POP for more
3463 details), use do_pending_stack_adjust before calling this function.
3464 That will ensure that the deferred pops are not accidentally
3465 emitted in the middel of this sequence. */
3470 struct sequence_stack *tem;
3472 tem = (struct sequence_stack *) xmalloc (sizeof (struct sequence_stack));
3474 tem->next = seq_stack;
3475 tem->first = first_insn;
3476 tem->last = last_insn;
3477 tem->sequence_rtl_expr = seq_rtl_expr;
3485 /* Similarly, but indicate that this sequence will be placed in T, an
3486 RTL_EXPR. See the documentation for start_sequence for more
3487 information about how to use this function. */
3490 start_sequence_for_rtl_expr (t)
3498 /* Set up the insn chain starting with FIRST as the current sequence,
3499 saving the previously current one. See the documentation for
3500 start_sequence for more information about how to use this function. */
3503 push_to_sequence (first)
3510 for (last = first; last && NEXT_INSN (last); last = NEXT_INSN (last));
3516 /* Set up the insn chain from a chain stort in FIRST to LAST. */
3519 push_to_full_sequence (first, last)
3525 /* We really should have the end of the insn chain here. */
3526 if (last && NEXT_INSN (last))
3530 /* Set up the outer-level insn chain
3531 as the current sequence, saving the previously current one. */
3534 push_topmost_sequence ()
3536 struct sequence_stack *stack, *top = NULL;
3540 for (stack = seq_stack; stack; stack = stack->next)
3543 first_insn = top->first;
3544 last_insn = top->last;
3545 seq_rtl_expr = top->sequence_rtl_expr;
3548 /* After emitting to the outer-level insn chain, update the outer-level
3549 insn chain, and restore the previous saved state. */
3552 pop_topmost_sequence ()
3554 struct sequence_stack *stack, *top = NULL;
3556 for (stack = seq_stack; stack; stack = stack->next)
3559 top->first = first_insn;
3560 top->last = last_insn;
3561 /* ??? Why don't we save seq_rtl_expr here? */
3566 /* After emitting to a sequence, restore previous saved state.
3568 To get the contents of the sequence just made, you must call
3569 `gen_sequence' *before* calling here.
3571 If the compiler might have deferred popping arguments while
3572 generating this sequence, and this sequence will not be immediately
3573 inserted into the instruction stream, use do_pending_stack_adjust
3574 before calling gen_sequence. That will ensure that the deferred
3575 pops are inserted into this sequence, and not into some random
3576 location in the instruction stream. See INHIBIT_DEFER_POP for more
3577 information about deferred popping of arguments. */
3582 struct sequence_stack *tem = seq_stack;
3584 first_insn = tem->first;
3585 last_insn = tem->last;
3586 seq_rtl_expr = tem->sequence_rtl_expr;
3587 seq_stack = tem->next;
3592 /* This works like end_sequence, but records the old sequence in FIRST
3596 end_full_sequence (first, last)
3599 *first = first_insn;
3604 /* Return 1 if currently emitting into a sequence. */
3609 return seq_stack != 0;
3612 /* Generate a SEQUENCE rtx containing the insns already emitted
3613 to the current sequence.
3615 This is how the gen_... function from a DEFINE_EXPAND
3616 constructs the SEQUENCE that it returns. */
3626 /* Count the insns in the chain. */
3628 for (tem = first_insn; tem; tem = NEXT_INSN (tem))
3631 /* If only one insn, return it rather than a SEQUENCE.
3632 (Now that we cache SEQUENCE expressions, it isn't worth special-casing
3633 the case of an empty list.)
3634 We only return the pattern of an insn if its code is INSN and it
3635 has no notes. This ensures that no information gets lost. */
3637 && ! RTX_FRAME_RELATED_P (first_insn)
3638 && GET_CODE (first_insn) == INSN
3639 /* Don't throw away any reg notes. */
3640 && REG_NOTES (first_insn) == 0)
3644 NEXT_INSN (first_insn) = free_insn;
3645 free_insn = first_insn;
3647 return PATTERN (first_insn);
3650 /* Put them in a vector. See if we already have a SEQUENCE of the
3651 appropriate length around. */
3652 if (!ggc_p && len < SEQUENCE_RESULT_SIZE
3653 && (result = sequence_result[len]) != 0)
3654 sequence_result[len] = 0;
3657 /* Ensure that this rtl goes in saveable_obstack, since we may
3659 push_obstacks_nochange ();
3660 rtl_in_saveable_obstack ();
3661 result = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (len));
3665 for (i = 0, tem = first_insn; tem; tem = NEXT_INSN (tem), i++)
3666 XVECEXP (result, 0, i) = tem;
3671 /* Put the various virtual registers into REGNO_REG_RTX. */
3674 init_virtual_regs (es)
3675 struct emit_status *es;
3677 rtx *ptr = es->x_regno_reg_rtx;
3678 ptr[VIRTUAL_INCOMING_ARGS_REGNUM] = virtual_incoming_args_rtx;
3679 ptr[VIRTUAL_STACK_VARS_REGNUM] = virtual_stack_vars_rtx;
3680 ptr[VIRTUAL_STACK_DYNAMIC_REGNUM] = virtual_stack_dynamic_rtx;
3681 ptr[VIRTUAL_OUTGOING_ARGS_REGNUM] = virtual_outgoing_args_rtx;
3682 ptr[VIRTUAL_CFA_REGNUM] = virtual_cfa_rtx;
3686 clear_emit_caches ()
3690 /* Clear the start_sequence/gen_sequence cache. */
3691 for (i = 0; i < SEQUENCE_RESULT_SIZE; i++)
3692 sequence_result[i] = 0;
3696 /* Used by copy_insn_1 to avoid copying SCRATCHes more than once. */
3697 static rtx copy_insn_scratch_in[MAX_RECOG_OPERANDS];
3698 static rtx copy_insn_scratch_out[MAX_RECOG_OPERANDS];
3699 static int copy_insn_n_scratches;
3701 /* When an insn is being copied by copy_insn_1, this is nonzero if we have
3702 copied an ASM_OPERANDS.
3703 In that case, it is the original input-operand vector. */
3704 static rtvec orig_asm_operands_vector;
3706 /* When an insn is being copied by copy_insn_1, this is nonzero if we have
3707 copied an ASM_OPERANDS.
3708 In that case, it is the copied input-operand vector. */
3709 static rtvec copy_asm_operands_vector;
3711 /* Likewise for the constraints vector. */
3712 static rtvec orig_asm_constraints_vector;
3713 static rtvec copy_asm_constraints_vector;
3715 /* Recursively create a new copy of an rtx for copy_insn.
3716 This function differs from copy_rtx in that it handles SCRATCHes and
3717 ASM_OPERANDs properly.
3718 Normally, this function is not used directly; use copy_insn as front end.
3719 However, you could first copy an insn pattern with copy_insn and then use
3720 this function afterwards to properly copy any REG_NOTEs containing
3729 register RTX_CODE code;
3730 register const char *format_ptr;
3732 code = GET_CODE (orig);
3748 for (i = 0; i < copy_insn_n_scratches; i++)
3749 if (copy_insn_scratch_in[i] == orig)
3750 return copy_insn_scratch_out[i];
3754 /* CONST can be shared if it contains a SYMBOL_REF. If it contains
3755 a LABEL_REF, it isn't sharable. */
3756 if (GET_CODE (XEXP (orig, 0)) == PLUS
3757 && GET_CODE (XEXP (XEXP (orig, 0), 0)) == SYMBOL_REF
3758 && GET_CODE (XEXP (XEXP (orig, 0), 1)) == CONST_INT)
3762 /* A MEM with a constant address is not sharable. The problem is that
3763 the constant address may need to be reloaded. If the mem is shared,
3764 then reloading one copy of this mem will cause all copies to appear
3765 to have been reloaded. */
3771 copy = rtx_alloc (code);
3773 /* Copy the various flags, and other information. We assume that
3774 all fields need copying, and then clear the fields that should
3775 not be copied. That is the sensible default behavior, and forces
3776 us to explicitly document why we are *not* copying a flag. */
3777 memcpy (copy, orig, sizeof (struct rtx_def) - sizeof (rtunion));
3779 /* We do not copy the USED flag, which is used as a mark bit during
3780 walks over the RTL. */
3783 /* We do not copy JUMP, CALL, or FRAME_RELATED for INSNs. */
3784 if (GET_RTX_CLASS (code) == 'i')
3788 copy->frame_related = 0;
3791 format_ptr = GET_RTX_FORMAT (GET_CODE (copy));
3793 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (copy)); i++)
3795 copy->fld[i] = orig->fld[i];
3796 switch (*format_ptr++)
3799 if (XEXP (orig, i) != NULL)
3800 XEXP (copy, i) = copy_insn_1 (XEXP (orig, i));
3805 if (XVEC (orig, i) == orig_asm_constraints_vector)
3806 XVEC (copy, i) = copy_asm_constraints_vector;
3807 else if (XVEC (orig, i) == orig_asm_operands_vector)
3808 XVEC (copy, i) = copy_asm_operands_vector;
3809 else if (XVEC (orig, i) != NULL)
3811 XVEC (copy, i) = rtvec_alloc (XVECLEN (orig, i));
3812 for (j = 0; j < XVECLEN (copy, i); j++)
3813 XVECEXP (copy, i, j) = copy_insn_1 (XVECEXP (orig, i, j));
3819 bitmap new_bits = BITMAP_OBSTACK_ALLOC (rtl_obstack);
3820 bitmap_copy (new_bits, XBITMAP (orig, i));
3821 XBITMAP (copy, i) = new_bits;
3832 /* These are left unchanged. */
3840 if (code == SCRATCH)
3842 i = copy_insn_n_scratches++;
3843 if (i >= MAX_RECOG_OPERANDS)
3845 copy_insn_scratch_in[i] = orig;
3846 copy_insn_scratch_out[i] = copy;
3848 else if (code == ASM_OPERANDS)
3850 orig_asm_operands_vector = XVEC (orig, 3);
3851 copy_asm_operands_vector = XVEC (copy, 3);
3852 orig_asm_constraints_vector = XVEC (orig, 4);
3853 copy_asm_constraints_vector = XVEC (copy, 4);
3859 /* Create a new copy of an rtx.
3860 This function differs from copy_rtx in that it handles SCRATCHes and
3861 ASM_OPERANDs properly.
3862 INSN doesn't really have to be a full INSN; it could be just the
3868 copy_insn_n_scratches = 0;
3869 orig_asm_operands_vector = 0;
3870 orig_asm_constraints_vector = 0;
3871 copy_asm_operands_vector = 0;
3872 copy_asm_constraints_vector = 0;
3873 return copy_insn_1 (insn);
3876 /* Initialize data structures and variables in this file
3877 before generating rtl for each function. */
3882 struct function *f = cfun;
3884 f->emit = (struct emit_status *) xmalloc (sizeof (struct emit_status));
3887 seq_rtl_expr = NULL;
3889 reg_rtx_no = LAST_VIRTUAL_REGISTER + 1;
3892 first_label_num = label_num;
3896 clear_emit_caches ();
3898 /* Init the tables that describe all the pseudo regs. */
3900 f->emit->regno_pointer_flag_length = LAST_VIRTUAL_REGISTER + 101;
3902 f->emit->regno_pointer_flag
3903 = (char *) xcalloc (f->emit->regno_pointer_flag_length, sizeof (char));
3905 f->emit->regno_pointer_align
3906 = (char *) xcalloc (f->emit->regno_pointer_flag_length,
3910 = (rtx *) xcalloc (f->emit->regno_pointer_flag_length * sizeof (rtx),
3913 /* Put copies of all the virtual register rtx into regno_reg_rtx. */
3914 init_virtual_regs (f->emit);
3916 /* Indicate that the virtual registers and stack locations are
3918 REGNO_POINTER_FLAG (STACK_POINTER_REGNUM) = 1;
3919 REGNO_POINTER_FLAG (FRAME_POINTER_REGNUM) = 1;
3920 REGNO_POINTER_FLAG (HARD_FRAME_POINTER_REGNUM) = 1;
3921 REGNO_POINTER_FLAG (ARG_POINTER_REGNUM) = 1;
3923 REGNO_POINTER_FLAG (VIRTUAL_INCOMING_ARGS_REGNUM) = 1;
3924 REGNO_POINTER_FLAG (VIRTUAL_STACK_VARS_REGNUM) = 1;
3925 REGNO_POINTER_FLAG (VIRTUAL_STACK_DYNAMIC_REGNUM) = 1;
3926 REGNO_POINTER_FLAG (VIRTUAL_OUTGOING_ARGS_REGNUM) = 1;
3927 REGNO_POINTER_FLAG (VIRTUAL_CFA_REGNUM) = 1;
3929 #ifdef STACK_BOUNDARY
3930 REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = STACK_BOUNDARY;
3931 REGNO_POINTER_ALIGN (FRAME_POINTER_REGNUM) = STACK_BOUNDARY;
3932 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = STACK_BOUNDARY;
3933 REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = STACK_BOUNDARY;
3935 REGNO_POINTER_ALIGN (VIRTUAL_INCOMING_ARGS_REGNUM) = STACK_BOUNDARY;
3936 REGNO_POINTER_ALIGN (VIRTUAL_STACK_VARS_REGNUM) = STACK_BOUNDARY;
3937 REGNO_POINTER_ALIGN (VIRTUAL_STACK_DYNAMIC_REGNUM) = STACK_BOUNDARY;
3938 REGNO_POINTER_ALIGN (VIRTUAL_OUTGOING_ARGS_REGNUM) = STACK_BOUNDARY;
3939 REGNO_POINTER_ALIGN (VIRTUAL_CFA_REGNUM) = BITS_PER_WORD;
3942 #ifdef INIT_EXPANDERS
3947 /* Mark SS for GC. */
3950 mark_sequence_stack (ss)
3951 struct sequence_stack *ss;
3955 ggc_mark_rtx (ss->first);
3956 ggc_mark_tree (ss->sequence_rtl_expr);
3961 /* Mark ES for GC. */
3964 mark_emit_status (es)
3965 struct emit_status *es;
3973 for (i = es->regno_pointer_flag_length, r = es->x_regno_reg_rtx;
3977 mark_sequence_stack (es->sequence_stack);
3978 ggc_mark_tree (es->sequence_rtl_expr);
3979 ggc_mark_rtx (es->x_first_insn);
3982 /* Create some permanent unique rtl objects shared between all functions.
3983 LINE_NUMBERS is nonzero if line numbers are to be generated. */
3986 init_emit_once (line_numbers)
3990 enum machine_mode mode;
3991 enum machine_mode double_mode;
3993 no_line_numbers = ! line_numbers;
3995 /* Compute the word and byte modes. */
3997 byte_mode = VOIDmode;
3998 word_mode = VOIDmode;
3999 double_mode = VOIDmode;
4001 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode;
4002 mode = GET_MODE_WIDER_MODE (mode))
4004 if (GET_MODE_BITSIZE (mode) == BITS_PER_UNIT
4005 && byte_mode == VOIDmode)
4008 if (GET_MODE_BITSIZE (mode) == BITS_PER_WORD
4009 && word_mode == VOIDmode)
4013 #ifndef DOUBLE_TYPE_SIZE
4014 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
4017 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); mode != VOIDmode;
4018 mode = GET_MODE_WIDER_MODE (mode))
4020 if (GET_MODE_BITSIZE (mode) == DOUBLE_TYPE_SIZE
4021 && double_mode == VOIDmode)
4025 ptr_mode = mode_for_size (POINTER_SIZE, GET_MODE_CLASS (Pmode), 0);
4027 /* Assign register numbers to the globally defined register rtx.
4028 This must be done at runtime because the register number field
4029 is in a union and some compilers can't initialize unions. */
4031 pc_rtx = gen_rtx (PC, VOIDmode);
4032 cc0_rtx = gen_rtx (CC0, VOIDmode);
4033 stack_pointer_rtx = gen_rtx_raw_REG (Pmode, STACK_POINTER_REGNUM);
4034 frame_pointer_rtx = gen_rtx_raw_REG (Pmode, FRAME_POINTER_REGNUM);
4035 if (hard_frame_pointer_rtx == 0)
4036 hard_frame_pointer_rtx = gen_rtx_raw_REG (Pmode,
4037 HARD_FRAME_POINTER_REGNUM);
4038 if (arg_pointer_rtx == 0)
4039 arg_pointer_rtx = gen_rtx_raw_REG (Pmode, ARG_POINTER_REGNUM);
4040 virtual_incoming_args_rtx =
4041 gen_rtx_raw_REG (Pmode, VIRTUAL_INCOMING_ARGS_REGNUM);
4042 virtual_stack_vars_rtx =
4043 gen_rtx_raw_REG (Pmode, VIRTUAL_STACK_VARS_REGNUM);
4044 virtual_stack_dynamic_rtx =
4045 gen_rtx_raw_REG (Pmode, VIRTUAL_STACK_DYNAMIC_REGNUM);
4046 virtual_outgoing_args_rtx =
4047 gen_rtx_raw_REG (Pmode, VIRTUAL_OUTGOING_ARGS_REGNUM);
4048 virtual_cfa_rtx = gen_rtx_raw_REG (Pmode, VIRTUAL_CFA_REGNUM);
4050 /* These rtx must be roots if GC is enabled. */
4052 ggc_add_rtx_root (global_rtl, GR_MAX);
4054 #ifdef INIT_EXPANDERS
4055 /* This is to initialize save_machine_status and restore_machine_status before
4056 the first call to push_function_context_to. This is needed by the Chill
4057 front end which calls push_function_context_to before the first cal to
4058 init_function_start. */
4062 /* Create the unique rtx's for certain rtx codes and operand values. */
4064 /* Don't use gen_rtx here since gen_rtx in this case
4065 tries to use these variables. */
4066 for (i = - MAX_SAVED_CONST_INT; i <= MAX_SAVED_CONST_INT; i++)
4067 const_int_rtx[i + MAX_SAVED_CONST_INT] =
4068 gen_rtx_raw_CONST_INT (VOIDmode, i);
4070 ggc_add_rtx_root (const_int_rtx, 2 * MAX_SAVED_CONST_INT + 1);
4072 if (STORE_FLAG_VALUE >= - MAX_SAVED_CONST_INT
4073 && STORE_FLAG_VALUE <= MAX_SAVED_CONST_INT)
4074 const_true_rtx = const_int_rtx[STORE_FLAG_VALUE + MAX_SAVED_CONST_INT];
4076 const_true_rtx = gen_rtx_CONST_INT (VOIDmode, STORE_FLAG_VALUE);
4078 dconst0 = REAL_VALUE_ATOF ("0", double_mode);
4079 dconst1 = REAL_VALUE_ATOF ("1", double_mode);
4080 dconst2 = REAL_VALUE_ATOF ("2", double_mode);
4081 dconstm1 = REAL_VALUE_ATOF ("-1", double_mode);
4083 for (i = 0; i <= 2; i++)
4085 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); mode != VOIDmode;
4086 mode = GET_MODE_WIDER_MODE (mode))
4088 rtx tem = rtx_alloc (CONST_DOUBLE);
4089 union real_extract u;
4091 bzero ((char *) &u, sizeof u); /* Zero any holes in a structure. */
4092 u.d = i == 0 ? dconst0 : i == 1 ? dconst1 : dconst2;
4094 bcopy ((char *) &u, (char *) &CONST_DOUBLE_LOW (tem), sizeof u);
4095 CONST_DOUBLE_MEM (tem) = cc0_rtx;
4096 PUT_MODE (tem, mode);
4098 const_tiny_rtx[i][(int) mode] = tem;
4101 const_tiny_rtx[i][(int) VOIDmode] = GEN_INT (i);
4103 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode;
4104 mode = GET_MODE_WIDER_MODE (mode))
4105 const_tiny_rtx[i][(int) mode] = GEN_INT (i);
4107 for (mode = GET_CLASS_NARROWEST_MODE (MODE_PARTIAL_INT);
4109 mode = GET_MODE_WIDER_MODE (mode))
4110 const_tiny_rtx[i][(int) mode] = GEN_INT (i);
4113 for (mode = CCmode; mode < MAX_MACHINE_MODE; ++mode)
4114 if (GET_MODE_CLASS (mode) == MODE_CC)
4115 const_tiny_rtx[0][(int) mode] = const0_rtx;
4117 ggc_add_rtx_root (&const_tiny_rtx[0][0], sizeof(const_tiny_rtx)/sizeof(rtx));
4118 ggc_add_rtx_root (&const_true_rtx, 1);
4120 #ifdef RETURN_ADDRESS_POINTER_REGNUM
4121 return_address_pointer_rtx
4122 = gen_rtx_raw_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM);
4126 struct_value_rtx = STRUCT_VALUE;
4128 struct_value_rtx = gen_rtx_REG (Pmode, STRUCT_VALUE_REGNUM);
4131 #ifdef STRUCT_VALUE_INCOMING
4132 struct_value_incoming_rtx = STRUCT_VALUE_INCOMING;
4134 #ifdef STRUCT_VALUE_INCOMING_REGNUM
4135 struct_value_incoming_rtx
4136 = gen_rtx_REG (Pmode, STRUCT_VALUE_INCOMING_REGNUM);
4138 struct_value_incoming_rtx = struct_value_rtx;
4142 #ifdef STATIC_CHAIN_REGNUM
4143 static_chain_rtx = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);
4145 #ifdef STATIC_CHAIN_INCOMING_REGNUM
4146 if (STATIC_CHAIN_INCOMING_REGNUM != STATIC_CHAIN_REGNUM)
4147 static_chain_incoming_rtx
4148 = gen_rtx_REG (Pmode, STATIC_CHAIN_INCOMING_REGNUM);
4151 static_chain_incoming_rtx = static_chain_rtx;
4155 static_chain_rtx = STATIC_CHAIN;
4157 #ifdef STATIC_CHAIN_INCOMING
4158 static_chain_incoming_rtx = STATIC_CHAIN_INCOMING;
4160 static_chain_incoming_rtx = static_chain_rtx;
4164 #ifdef PIC_OFFSET_TABLE_REGNUM
4165 pic_offset_table_rtx = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM);
4168 ggc_add_rtx_root (&pic_offset_table_rtx, 1);
4169 ggc_add_rtx_root (&struct_value_rtx, 1);
4170 ggc_add_rtx_root (&struct_value_incoming_rtx, 1);
4171 ggc_add_rtx_root (&static_chain_rtx, 1);
4172 ggc_add_rtx_root (&static_chain_incoming_rtx, 1);
4173 ggc_add_rtx_root (&return_address_pointer_rtx, 1);
4175 /* Initialize the CONST_INT hash table. */
4176 const_int_htab = htab_create (37, const_int_htab_hash,
4177 const_int_htab_eq, NULL);
4178 ggc_add_root (&const_int_htab, 1, sizeof (const_int_htab),
4182 /* Query and clear/ restore no_line_numbers. This is used by the
4183 switch / case handling in stmt.c to give proper line numbers in
4184 warnings about unreachable code. */
4187 force_line_numbers ()
4189 int old = no_line_numbers;
4191 no_line_numbers = 0;
4193 force_next_line_note ();
4198 restore_line_number_status (old_value)
4201 no_line_numbers = old_value;