1 @c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1996, 1998, 1999, 2000, 2001,
2 @c 2002, 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
3 @c This is part of the GCC manual.
4 @c For copying conditions, see the file gcc.texi.
8 @chapter Machine Descriptions
9 @cindex machine descriptions
11 A machine description has two parts: a file of instruction patterns
12 (@file{.md} file) and a C header file of macro definitions.
14 The @file{.md} file for a target machine contains a pattern for each
15 instruction that the target machine supports (or at least each instruction
16 that is worth telling the compiler about). It may also contain comments.
17 A semicolon causes the rest of the line to be a comment, unless the semicolon
18 is inside a quoted string.
20 See the next chapter for information on the C header file.
23 * Overview:: How the machine description is used.
24 * Patterns:: How to write instruction patterns.
25 * Example:: An explained example of a @code{define_insn} pattern.
26 * RTL Template:: The RTL template defines what insns match a pattern.
27 * Output Template:: The output template says how to make assembler code
29 * Output Statement:: For more generality, write C code to output
31 * Predicates:: Controlling what kinds of operands can be used
33 * Constraints:: Fine-tuning operand selection.
34 * Standard Names:: Names mark patterns to use for code generation.
35 * Pattern Ordering:: When the order of patterns makes a difference.
36 * Dependent Patterns:: Having one pattern may make you need another.
37 * Jump Patterns:: Special considerations for patterns for jump insns.
38 * Looping Patterns:: How to define patterns for special looping insns.
39 * Insn Canonicalizations::Canonicalization of Instructions
40 * Expander Definitions::Generating a sequence of several RTL insns
41 for a standard operation.
42 * Insn Splitting:: Splitting Instructions into Multiple Instructions.
43 * Including Patterns:: Including Patterns in Machine Descriptions.
44 * Peephole Definitions::Defining machine-specific peephole optimizations.
45 * Insn Attributes:: Specifying the value of attributes for generated insns.
46 * Conditional Execution::Generating @code{define_insn} patterns for
48 * Constant Definitions::Defining symbolic constants that can be used in the
50 * Iterators:: Using iterators to generate patterns from a template.
54 @section Overview of How the Machine Description is Used
56 There are three main conversions that happen in the compiler:
61 The front end reads the source code and builds a parse tree.
64 The parse tree is used to generate an RTL insn list based on named
68 The insn list is matched against the RTL templates to produce assembler
73 For the generate pass, only the names of the insns matter, from either a
74 named @code{define_insn} or a @code{define_expand}. The compiler will
75 choose the pattern with the right name and apply the operands according
76 to the documentation later in this chapter, without regard for the RTL
77 template or operand constraints. Note that the names the compiler looks
78 for are hard-coded in the compiler---it will ignore unnamed patterns and
79 patterns with names it doesn't know about, but if you don't provide a
80 named pattern it needs, it will abort.
82 If a @code{define_insn} is used, the template given is inserted into the
83 insn list. If a @code{define_expand} is used, one of three things
84 happens, based on the condition logic. The condition logic may manually
85 create new insns for the insn list, say via @code{emit_insn()}, and
86 invoke @code{DONE}. For certain named patterns, it may invoke @code{FAIL} to tell the
87 compiler to use an alternate way of performing that task. If it invokes
88 neither @code{DONE} nor @code{FAIL}, the template given in the pattern
89 is inserted, as if the @code{define_expand} were a @code{define_insn}.
91 Once the insn list is generated, various optimization passes convert,
92 replace, and rearrange the insns in the insn list. This is where the
93 @code{define_split} and @code{define_peephole} patterns get used, for
96 Finally, the insn list's RTL is matched up with the RTL templates in the
97 @code{define_insn} patterns, and those patterns are used to emit the
98 final assembly code. For this purpose, each named @code{define_insn}
99 acts like it's unnamed, since the names are ignored.
102 @section Everything about Instruction Patterns
104 @cindex instruction patterns
107 Each instruction pattern contains an incomplete RTL expression, with pieces
108 to be filled in later, operand constraints that restrict how the pieces can
109 be filled in, and an output pattern or C code to generate the assembler
110 output, all wrapped up in a @code{define_insn} expression.
112 A @code{define_insn} is an RTL expression containing four or five operands:
116 An optional name. The presence of a name indicate that this instruction
117 pattern can perform a certain standard job for the RTL-generation
118 pass of the compiler. This pass knows certain names and will use
119 the instruction patterns with those names, if the names are defined
120 in the machine description.
122 The absence of a name is indicated by writing an empty string
123 where the name should go. Nameless instruction patterns are never
124 used for generating RTL code, but they may permit several simpler insns
125 to be combined later on.
127 Names that are not thus known and used in RTL-generation have no
128 effect; they are equivalent to no name at all.
130 For the purpose of debugging the compiler, you may also specify a
131 name beginning with the @samp{*} character. Such a name is used only
132 for identifying the instruction in RTL dumps; it is entirely equivalent
133 to having a nameless pattern for all other purposes.
136 The @dfn{RTL template} (@pxref{RTL Template}) is a vector of incomplete
137 RTL expressions which show what the instruction should look like. It is
138 incomplete because it may contain @code{match_operand},
139 @code{match_operator}, and @code{match_dup} expressions that stand for
140 operands of the instruction.
142 If the vector has only one element, that element is the template for the
143 instruction pattern. If the vector has multiple elements, then the
144 instruction pattern is a @code{parallel} expression containing the
148 @cindex pattern conditions
149 @cindex conditions, in patterns
150 A condition. This is a string which contains a C expression that is
151 the final test to decide whether an insn body matches this pattern.
153 @cindex named patterns and conditions
154 For a named pattern, the condition (if present) may not depend on
155 the data in the insn being matched, but only the target-machine-type
156 flags. The compiler needs to test these conditions during
157 initialization in order to learn exactly which named instructions are
158 available in a particular run.
161 For nameless patterns, the condition is applied only when matching an
162 individual insn, and only after the insn has matched the pattern's
163 recognition template. The insn's operands may be found in the vector
164 @code{operands}. For an insn where the condition has once matched, it
165 can't be used to control register allocation, for example by excluding
166 certain hard registers or hard register combinations.
169 The @dfn{output template}: a string that says how to output matching
170 insns as assembler code. @samp{%} in this string specifies where
171 to substitute the value of an operand. @xref{Output Template}.
173 When simple substitution isn't general enough, you can specify a piece
174 of C code to compute the output. @xref{Output Statement}.
177 Optionally, a vector containing the values of attributes for insns matching
178 this pattern. @xref{Insn Attributes}.
182 @section Example of @code{define_insn}
183 @cindex @code{define_insn} example
185 Here is an actual example of an instruction pattern, for the 68000/68020.
190 (match_operand:SI 0 "general_operand" "rm"))]
194 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
196 return \"cmpl #0,%0\";
201 This can also be written using braced strings:
206 (match_operand:SI 0 "general_operand" "rm"))]
209 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
215 This is an instruction that sets the condition codes based on the value of
216 a general operand. It has no condition, so any insn whose RTL description
217 has the form shown may be handled according to this pattern. The name
218 @samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL generation
219 pass that, when it is necessary to test such a value, an insn to do so
220 can be constructed using this pattern.
222 The output control string is a piece of C code which chooses which
223 output template to return based on the kind of operand and the specific
224 type of CPU for which code is being generated.
226 @samp{"rm"} is an operand constraint. Its meaning is explained below.
229 @section RTL Template
230 @cindex RTL insn template
231 @cindex generating insns
232 @cindex insns, generating
233 @cindex recognizing insns
234 @cindex insns, recognizing
236 The RTL template is used to define which insns match the particular pattern
237 and how to find their operands. For named patterns, the RTL template also
238 says how to construct an insn from specified operands.
240 Construction involves substituting specified operands into a copy of the
241 template. Matching involves determining the values that serve as the
242 operands in the insn being matched. Both of these activities are
243 controlled by special expression types that direct matching and
244 substitution of the operands.
247 @findex match_operand
248 @item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint})
249 This expression is a placeholder for operand number @var{n} of
250 the insn. When constructing an insn, operand number @var{n}
251 will be substituted at this point. When matching an insn, whatever
252 appears at this position in the insn will be taken as operand
253 number @var{n}; but it must satisfy @var{predicate} or this instruction
254 pattern will not match at all.
256 Operand numbers must be chosen consecutively counting from zero in
257 each instruction pattern. There may be only one @code{match_operand}
258 expression in the pattern for each operand number. Usually operands
259 are numbered in the order of appearance in @code{match_operand}
260 expressions. In the case of a @code{define_expand}, any operand numbers
261 used only in @code{match_dup} expressions have higher values than all
262 other operand numbers.
264 @var{predicate} is a string that is the name of a function that
265 accepts two arguments, an expression and a machine mode.
266 @xref{Predicates}. During matching, the function will be called with
267 the putative operand as the expression and @var{m} as the mode
268 argument (if @var{m} is not specified, @code{VOIDmode} will be used,
269 which normally causes @var{predicate} to accept any mode). If it
270 returns zero, this instruction pattern fails to match.
271 @var{predicate} may be an empty string; then it means no test is to be
272 done on the operand, so anything which occurs in this position is
275 Most of the time, @var{predicate} will reject modes other than @var{m}---but
276 not always. For example, the predicate @code{address_operand} uses
277 @var{m} as the mode of memory ref that the address should be valid for.
278 Many predicates accept @code{const_int} nodes even though their mode is
281 @var{constraint} controls reloading and the choice of the best register
282 class to use for a value, as explained later (@pxref{Constraints}).
283 If the constraint would be an empty string, it can be omitted.
285 People are often unclear on the difference between the constraint and the
286 predicate. The predicate helps decide whether a given insn matches the
287 pattern. The constraint plays no role in this decision; instead, it
288 controls various decisions in the case of an insn which does match.
290 @findex match_scratch
291 @item (match_scratch:@var{m} @var{n} @var{constraint})
292 This expression is also a placeholder for operand number @var{n}
293 and indicates that operand must be a @code{scratch} or @code{reg}
296 When matching patterns, this is equivalent to
299 (match_operand:@var{m} @var{n} "scratch_operand" @var{pred})
302 but, when generating RTL, it produces a (@code{scratch}:@var{m})
305 If the last few expressions in a @code{parallel} are @code{clobber}
306 expressions whose operands are either a hard register or
307 @code{match_scratch}, the combiner can add or delete them when
308 necessary. @xref{Side Effects}.
311 @item (match_dup @var{n})
312 This expression is also a placeholder for operand number @var{n}.
313 It is used when the operand needs to appear more than once in the
316 In construction, @code{match_dup} acts just like @code{match_operand}:
317 the operand is substituted into the insn being constructed. But in
318 matching, @code{match_dup} behaves differently. It assumes that operand
319 number @var{n} has already been determined by a @code{match_operand}
320 appearing earlier in the recognition template, and it matches only an
321 identical-looking expression.
323 Note that @code{match_dup} should not be used to tell the compiler that
324 a particular register is being used for two operands (example:
325 @code{add} that adds one register to another; the second register is
326 both an input operand and the output operand). Use a matching
327 constraint (@pxref{Simple Constraints}) for those. @code{match_dup} is for the cases where one
328 operand is used in two places in the template, such as an instruction
329 that computes both a quotient and a remainder, where the opcode takes
330 two input operands but the RTL template has to refer to each of those
331 twice; once for the quotient pattern and once for the remainder pattern.
333 @findex match_operator
334 @item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}])
335 This pattern is a kind of placeholder for a variable RTL expression
338 When constructing an insn, it stands for an RTL expression whose
339 expression code is taken from that of operand @var{n}, and whose
340 operands are constructed from the patterns @var{operands}.
342 When matching an expression, it matches an expression if the function
343 @var{predicate} returns nonzero on that expression @emph{and} the
344 patterns @var{operands} match the operands of the expression.
346 Suppose that the function @code{commutative_operator} is defined as
347 follows, to match any expression whose operator is one of the
348 commutative arithmetic operators of RTL and whose mode is @var{mode}:
352 commutative_integer_operator (x, mode)
354 enum machine_mode mode;
356 enum rtx_code code = GET_CODE (x);
357 if (GET_MODE (x) != mode)
359 return (GET_RTX_CLASS (code) == RTX_COMM_ARITH
360 || code == EQ || code == NE);
364 Then the following pattern will match any RTL expression consisting
365 of a commutative operator applied to two general operands:
368 (match_operator:SI 3 "commutative_operator"
369 [(match_operand:SI 1 "general_operand" "g")
370 (match_operand:SI 2 "general_operand" "g")])
373 Here the vector @code{[@var{operands}@dots{}]} contains two patterns
374 because the expressions to be matched all contain two operands.
376 When this pattern does match, the two operands of the commutative
377 operator are recorded as operands 1 and 2 of the insn. (This is done
378 by the two instances of @code{match_operand}.) Operand 3 of the insn
379 will be the entire commutative expression: use @code{GET_CODE
380 (operands[3])} to see which commutative operator was used.
382 The machine mode @var{m} of @code{match_operator} works like that of
383 @code{match_operand}: it is passed as the second argument to the
384 predicate function, and that function is solely responsible for
385 deciding whether the expression to be matched ``has'' that mode.
387 When constructing an insn, argument 3 of the gen-function will specify
388 the operation (i.e.@: the expression code) for the expression to be
389 made. It should be an RTL expression, whose expression code is copied
390 into a new expression whose operands are arguments 1 and 2 of the
391 gen-function. The subexpressions of argument 3 are not used;
392 only its expression code matters.
394 When @code{match_operator} is used in a pattern for matching an insn,
395 it usually best if the operand number of the @code{match_operator}
396 is higher than that of the actual operands of the insn. This improves
397 register allocation because the register allocator often looks at
398 operands 1 and 2 of insns to see if it can do register tying.
400 There is no way to specify constraints in @code{match_operator}. The
401 operand of the insn which corresponds to the @code{match_operator}
402 never has any constraints because it is never reloaded as a whole.
403 However, if parts of its @var{operands} are matched by
404 @code{match_operand} patterns, those parts may have constraints of
408 @item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}])
409 Like @code{match_dup}, except that it applies to operators instead of
410 operands. When constructing an insn, operand number @var{n} will be
411 substituted at this point. But in matching, @code{match_op_dup} behaves
412 differently. It assumes that operand number @var{n} has already been
413 determined by a @code{match_operator} appearing earlier in the
414 recognition template, and it matches only an identical-looking
417 @findex match_parallel
418 @item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}])
419 This pattern is a placeholder for an insn that consists of a
420 @code{parallel} expression with a variable number of elements. This
421 expression should only appear at the top level of an insn pattern.
423 When constructing an insn, operand number @var{n} will be substituted at
424 this point. When matching an insn, it matches if the body of the insn
425 is a @code{parallel} expression with at least as many elements as the
426 vector of @var{subpat} expressions in the @code{match_parallel}, if each
427 @var{subpat} matches the corresponding element of the @code{parallel},
428 @emph{and} the function @var{predicate} returns nonzero on the
429 @code{parallel} that is the body of the insn. It is the responsibility
430 of the predicate to validate elements of the @code{parallel} beyond
431 those listed in the @code{match_parallel}.
433 A typical use of @code{match_parallel} is to match load and store
434 multiple expressions, which can contain a variable number of elements
435 in a @code{parallel}. For example,
439 [(match_parallel 0 "load_multiple_operation"
440 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
441 (match_operand:SI 2 "memory_operand" "m"))
443 (clobber (reg:SI 179))])]
448 This example comes from @file{a29k.md}. The function
449 @code{load_multiple_operation} is defined in @file{a29k.c} and checks
450 that subsequent elements in the @code{parallel} are the same as the
451 @code{set} in the pattern, except that they are referencing subsequent
452 registers and memory locations.
454 An insn that matches this pattern might look like:
458 [(set (reg:SI 20) (mem:SI (reg:SI 100)))
460 (clobber (reg:SI 179))
462 (mem:SI (plus:SI (reg:SI 100)
465 (mem:SI (plus:SI (reg:SI 100)
469 @findex match_par_dup
470 @item (match_par_dup @var{n} [@var{subpat}@dots{}])
471 Like @code{match_op_dup}, but for @code{match_parallel} instead of
472 @code{match_operator}.
476 @node Output Template
477 @section Output Templates and Operand Substitution
478 @cindex output templates
479 @cindex operand substitution
481 @cindex @samp{%} in template
483 The @dfn{output template} is a string which specifies how to output the
484 assembler code for an instruction pattern. Most of the template is a
485 fixed string which is output literally. The character @samp{%} is used
486 to specify where to substitute an operand; it can also be used to
487 identify places where different variants of the assembler require
490 In the simplest case, a @samp{%} followed by a digit @var{n} says to output
491 operand @var{n} at that point in the string.
493 @samp{%} followed by a letter and a digit says to output an operand in an
494 alternate fashion. Four letters have standard, built-in meanings described
495 below. The machine description macro @code{PRINT_OPERAND} can define
496 additional letters with nonstandard meanings.
498 @samp{%c@var{digit}} can be used to substitute an operand that is a
499 constant value without the syntax that normally indicates an immediate
502 @samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of
503 the constant is negated before printing.
505 @samp{%a@var{digit}} can be used to substitute an operand as if it were a
506 memory reference, with the actual operand treated as the address. This may
507 be useful when outputting a ``load address'' instruction, because often the
508 assembler syntax for such an instruction requires you to write the operand
509 as if it were a memory reference.
511 @samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump
514 @samp{%=} outputs a number which is unique to each instruction in the
515 entire compilation. This is useful for making local labels to be
516 referred to more than once in a single template that generates multiple
517 assembler instructions.
519 @samp{%} followed by a punctuation character specifies a substitution that
520 does not use an operand. Only one case is standard: @samp{%%} outputs a
521 @samp{%} into the assembler code. Other nonstandard cases can be
522 defined in the @code{PRINT_OPERAND} macro. You must also define
523 which punctuation characters are valid with the
524 @code{PRINT_OPERAND_PUNCT_VALID_P} macro.
528 The template may generate multiple assembler instructions. Write the text
529 for the instructions, with @samp{\;} between them.
531 @cindex matching operands
532 When the RTL contains two operands which are required by constraint to match
533 each other, the output template must refer only to the lower-numbered operand.
534 Matching operands are not always identical, and the rest of the compiler
535 arranges to put the proper RTL expression for printing into the lower-numbered
538 One use of nonstandard letters or punctuation following @samp{%} is to
539 distinguish between different assembler languages for the same machine; for
540 example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax
541 requires periods in most opcode names, while MIT syntax does not. For
542 example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola
543 syntax. The same file of patterns is used for both kinds of output syntax,
544 but the character sequence @samp{%.} is used in each place where Motorola
545 syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax
546 defines the sequence to output a period; the macro for MIT syntax defines
549 @cindex @code{#} in template
550 As a special case, a template consisting of the single character @code{#}
551 instructs the compiler to first split the insn, and then output the
552 resulting instructions separately. This helps eliminate redundancy in the
553 output templates. If you have a @code{define_insn} that needs to emit
554 multiple assembler instructions, and there is an matching @code{define_split}
555 already defined, then you can simply use @code{#} as the output template
556 instead of writing an output template that emits the multiple assembler
559 If the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct
560 of the form @samp{@{option0|option1|option2@}} in the templates. These
561 describe multiple variants of assembler language syntax.
562 @xref{Instruction Output}.
564 @node Output Statement
565 @section C Statements for Assembler Output
566 @cindex output statements
567 @cindex C statements for assembler output
568 @cindex generating assembler output
570 Often a single fixed template string cannot produce correct and efficient
571 assembler code for all the cases that are recognized by a single
572 instruction pattern. For example, the opcodes may depend on the kinds of
573 operands; or some unfortunate combinations of operands may require extra
574 machine instructions.
576 If the output control string starts with a @samp{@@}, then it is actually
577 a series of templates, each on a separate line. (Blank lines and
578 leading spaces and tabs are ignored.) The templates correspond to the
579 pattern's constraint alternatives (@pxref{Multi-Alternative}). For example,
580 if a target machine has a two-address add instruction @samp{addr} to add
581 into a register and another @samp{addm} to add a register to memory, you
582 might write this pattern:
585 (define_insn "addsi3"
586 [(set (match_operand:SI 0 "general_operand" "=r,m")
587 (plus:SI (match_operand:SI 1 "general_operand" "0,0")
588 (match_operand:SI 2 "general_operand" "g,r")))]
595 @cindex @code{*} in template
596 @cindex asterisk in template
597 If the output control string starts with a @samp{*}, then it is not an
598 output template but rather a piece of C program that should compute a
599 template. It should execute a @code{return} statement to return the
600 template-string you want. Most such templates use C string literals, which
601 require doublequote characters to delimit them. To include these
602 doublequote characters in the string, prefix each one with @samp{\}.
604 If the output control string is written as a brace block instead of a
605 double-quoted string, it is automatically assumed to be C code. In that
606 case, it is not necessary to put in a leading asterisk, or to escape the
607 doublequotes surrounding C string literals.
609 The operands may be found in the array @code{operands}, whose C data type
612 It is very common to select different ways of generating assembler code
613 based on whether an immediate operand is within a certain range. Be
614 careful when doing this, because the result of @code{INTVAL} is an
615 integer on the host machine. If the host machine has more bits in an
616 @code{int} than the target machine has in the mode in which the constant
617 will be used, then some of the bits you get from @code{INTVAL} will be
618 superfluous. For proper results, you must carefully disregard the
619 values of those bits.
621 @findex output_asm_insn
622 It is possible to output an assembler instruction and then go on to output
623 or compute more of them, using the subroutine @code{output_asm_insn}. This
624 receives two arguments: a template-string and a vector of operands. The
625 vector may be @code{operands}, or it may be another array of @code{rtx}
626 that you declare locally and initialize yourself.
628 @findex which_alternative
629 When an insn pattern has multiple alternatives in its constraints, often
630 the appearance of the assembler code is determined mostly by which alternative
631 was matched. When this is so, the C code can test the variable
632 @code{which_alternative}, which is the ordinal number of the alternative
633 that was actually satisfied (0 for the first, 1 for the second alternative,
636 For example, suppose there are two opcodes for storing zero, @samp{clrreg}
637 for registers and @samp{clrmem} for memory locations. Here is how
638 a pattern could use @code{which_alternative} to choose between them:
642 [(set (match_operand:SI 0 "general_operand" "=r,m")
646 return (which_alternative == 0
647 ? "clrreg %0" : "clrmem %0");
651 The example above, where the assembler code to generate was
652 @emph{solely} determined by the alternative, could also have been specified
653 as follows, having the output control string start with a @samp{@@}:
658 [(set (match_operand:SI 0 "general_operand" "=r,m")
670 @cindex operand predicates
671 @cindex operator predicates
673 A predicate determines whether a @code{match_operand} or
674 @code{match_operator} expression matches, and therefore whether the
675 surrounding instruction pattern will be used for that combination of
676 operands. GCC has a number of machine-independent predicates, and you
677 can define machine-specific predicates as needed. By convention,
678 predicates used with @code{match_operand} have names that end in
679 @samp{_operand}, and those used with @code{match_operator} have names
680 that end in @samp{_operator}.
682 All predicates are Boolean functions (in the mathematical sense) of
683 two arguments: the RTL expression that is being considered at that
684 position in the instruction pattern, and the machine mode that the
685 @code{match_operand} or @code{match_operator} specifies. In this
686 section, the first argument is called @var{op} and the second argument
687 @var{mode}. Predicates can be called from C as ordinary two-argument
688 functions; this can be useful in output templates or other
689 machine-specific code.
691 Operand predicates can allow operands that are not actually acceptable
692 to the hardware, as long as the constraints give reload the ability to
693 fix them up (@pxref{Constraints}). However, GCC will usually generate
694 better code if the predicates specify the requirements of the machine
695 instructions as closely as possible. Reload cannot fix up operands
696 that must be constants (``immediate operands''); you must use a
697 predicate that allows only constants, or else enforce the requirement
698 in the extra condition.
700 @cindex predicates and machine modes
701 @cindex normal predicates
702 @cindex special predicates
703 Most predicates handle their @var{mode} argument in a uniform manner.
704 If @var{mode} is @code{VOIDmode} (unspecified), then @var{op} can have
705 any mode. If @var{mode} is anything else, then @var{op} must have the
706 same mode, unless @var{op} is a @code{CONST_INT} or integer
707 @code{CONST_DOUBLE}. These RTL expressions always have
708 @code{VOIDmode}, so it would be counterproductive to check that their
709 mode matches. Instead, predicates that accept @code{CONST_INT} and/or
710 integer @code{CONST_DOUBLE} check that the value stored in the
711 constant will fit in the requested mode.
713 Predicates with this behavior are called @dfn{normal}.
714 @command{genrecog} can optimize the instruction recognizer based on
715 knowledge of how normal predicates treat modes. It can also diagnose
716 certain kinds of common errors in the use of normal predicates; for
717 instance, it is almost always an error to use a normal predicate
718 without specifying a mode.
720 Predicates that do something different with their @var{mode} argument
721 are called @dfn{special}. The generic predicates
722 @code{address_operand} and @code{pmode_register_operand} are special
723 predicates. @command{genrecog} does not do any optimizations or
724 diagnosis when special predicates are used.
727 * Machine-Independent Predicates:: Predicates available to all back ends.
728 * Defining Predicates:: How to write machine-specific predicate
732 @node Machine-Independent Predicates
733 @subsection Machine-Independent Predicates
734 @cindex machine-independent predicates
735 @cindex generic predicates
737 These are the generic predicates available to all back ends. They are
738 defined in @file{recog.c}. The first category of predicates allow
739 only constant, or @dfn{immediate}, operands.
741 @defun immediate_operand
742 This predicate allows any sort of constant that fits in @var{mode}.
743 It is an appropriate choice for instructions that take operands that
747 @defun const_int_operand
748 This predicate allows any @code{CONST_INT} expression that fits in
749 @var{mode}. It is an appropriate choice for an immediate operand that
750 does not allow a symbol or label.
753 @defun const_double_operand
754 This predicate accepts any @code{CONST_DOUBLE} expression that has
755 exactly @var{mode}. If @var{mode} is @code{VOIDmode}, it will also
756 accept @code{CONST_INT}. It is intended for immediate floating point
761 The second category of predicates allow only some kind of machine
764 @defun register_operand
765 This predicate allows any @code{REG} or @code{SUBREG} expression that
766 is valid for @var{mode}. It is often suitable for arithmetic
767 instruction operands on a RISC machine.
770 @defun pmode_register_operand
771 This is a slight variant on @code{register_operand} which works around
772 a limitation in the machine-description reader.
775 (match_operand @var{n} "pmode_register_operand" @var{constraint})
782 (match_operand:P @var{n} "register_operand" @var{constraint})
786 would mean, if the machine-description reader accepted @samp{:P}
787 mode suffixes. Unfortunately, it cannot, because @code{Pmode} is an
788 alias for some other mode, and might vary with machine-specific
789 options. @xref{Misc}.
792 @defun scratch_operand
793 This predicate allows hard registers and @code{SCRATCH} expressions,
794 but not pseudo-registers. It is used internally by @code{match_scratch};
795 it should not be used directly.
799 The third category of predicates allow only some kind of memory reference.
801 @defun memory_operand
802 This predicate allows any valid reference to a quantity of mode
803 @var{mode} in memory, as determined by the weak form of
804 @code{GO_IF_LEGITIMATE_ADDRESS} (@pxref{Addressing Modes}).
807 @defun address_operand
808 This predicate is a little unusual; it allows any operand that is a
809 valid expression for the @emph{address} of a quantity of mode
810 @var{mode}, again determined by the weak form of
811 @code{GO_IF_LEGITIMATE_ADDRESS}. To first order, if
812 @samp{@w{(mem:@var{mode} (@var{exp}))}} is acceptable to
813 @code{memory_operand}, then @var{exp} is acceptable to
814 @code{address_operand}. Note that @var{exp} does not necessarily have
818 @defun indirect_operand
819 This is a stricter form of @code{memory_operand} which allows only
820 memory references with a @code{general_operand} as the address
821 expression. New uses of this predicate are discouraged, because
822 @code{general_operand} is very permissive, so it's hard to tell what
823 an @code{indirect_operand} does or does not allow. If a target has
824 different requirements for memory operands for different instructions,
825 it is better to define target-specific predicates which enforce the
826 hardware's requirements explicitly.
830 This predicate allows a memory reference suitable for pushing a value
831 onto the stack. This will be a @code{MEM} which refers to
832 @code{stack_pointer_rtx}, with a side-effect in its address expression
833 (@pxref{Incdec}); which one is determined by the
834 @code{STACK_PUSH_CODE} macro (@pxref{Frame Layout}).
838 This predicate allows a memory reference suitable for popping a value
839 off the stack. Again, this will be a @code{MEM} referring to
840 @code{stack_pointer_rtx}, with a side-effect in its address
841 expression. However, this time @code{STACK_POP_CODE} is expected.
845 The fourth category of predicates allow some combination of the above
848 @defun nonmemory_operand
849 This predicate allows any immediate or register operand valid for @var{mode}.
852 @defun nonimmediate_operand
853 This predicate allows any register or memory operand valid for @var{mode}.
856 @defun general_operand
857 This predicate allows any immediate, register, or memory operand
858 valid for @var{mode}.
862 Finally, there is one generic operator predicate.
864 @defun comparison_operator
865 This predicate matches any expression which performs an arithmetic
866 comparison in @var{mode}; that is, @code{COMPARISON_P} is true for the
870 @node Defining Predicates
871 @subsection Defining Machine-Specific Predicates
872 @cindex defining predicates
873 @findex define_predicate
874 @findex define_special_predicate
876 Many machines have requirements for their operands that cannot be
877 expressed precisely using the generic predicates. You can define
878 additional predicates using @code{define_predicate} and
879 @code{define_special_predicate} expressions. These expressions have
884 The name of the predicate, as it will be referred to in
885 @code{match_operand} or @code{match_operator} expressions.
888 An RTL expression which evaluates to true if the predicate allows the
889 operand @var{op}, false if it does not. This expression can only use
890 the following RTL codes:
894 When written inside a predicate expression, a @code{MATCH_OPERAND}
895 expression evaluates to true if the predicate it names would allow
896 @var{op}. The operand number and constraint are ignored. Due to
897 limitations in @command{genrecog}, you can only refer to generic
898 predicates and predicates that have already been defined.
901 This expression evaluates to true if @var{op} or a specified
902 subexpression of @var{op} has one of a given list of RTX codes.
904 The first operand of this expression is a string constant containing a
905 comma-separated list of RTX code names (in lower case). These are the
906 codes for which the @code{MATCH_CODE} will be true.
908 The second operand is a string constant which indicates what
909 subexpression of @var{op} to examine. If it is absent or the empty
910 string, @var{op} itself is examined. Otherwise, the string constant
911 must be a sequence of digits and/or lowercase letters. Each character
912 indicates a subexpression to extract from the current expression; for
913 the first character this is @var{op}, for the second and subsequent
914 characters it is the result of the previous character. A digit
915 @var{n} extracts @samp{@w{XEXP (@var{e}, @var{n})}}; a letter @var{l}
916 extracts @samp{@w{XVECEXP (@var{e}, 0, @var{n})}} where @var{n} is the
917 alphabetic ordinal of @var{l} (0 for `a', 1 for 'b', and so on). The
918 @code{MATCH_CODE} then examines the RTX code of the subexpression
919 extracted by the complete string. It is not possible to extract
920 components of an @code{rtvec} that is not at position 0 within its RTX
924 This expression has one operand, a string constant containing a C
925 expression. The predicate's arguments, @var{op} and @var{mode}, are
926 available with those names in the C expression. The @code{MATCH_TEST}
927 evaluates to true if the C expression evaluates to a nonzero value.
928 @code{MATCH_TEST} expressions must not have side effects.
934 The basic @samp{MATCH_} expressions can be combined using these
935 logical operators, which have the semantics of the C operators
936 @samp{&&}, @samp{||}, @samp{!}, and @samp{@w{? :}} respectively. As
937 in Common Lisp, you may give an @code{AND} or @code{IOR} expression an
938 arbitrary number of arguments; this has exactly the same effect as
939 writing a chain of two-argument @code{AND} or @code{IOR} expressions.
943 An optional block of C code, which should execute
944 @samp{@w{return true}} if the predicate is found to match and
945 @samp{@w{return false}} if it does not. It must not have any side
946 effects. The predicate arguments, @var{op} and @var{mode}, are
947 available with those names.
949 If a code block is present in a predicate definition, then the RTL
950 expression must evaluate to true @emph{and} the code block must
951 execute @samp{@w{return true}} for the predicate to allow the operand.
952 The RTL expression is evaluated first; do not re-check anything in the
953 code block that was checked in the RTL expression.
956 The program @command{genrecog} scans @code{define_predicate} and
957 @code{define_special_predicate} expressions to determine which RTX
958 codes are possibly allowed. You should always make this explicit in
959 the RTL predicate expression, using @code{MATCH_OPERAND} and
962 Here is an example of a simple predicate definition, from the IA64
967 ;; @r{True if @var{op} is a @code{SYMBOL_REF} which refers to the sdata section.}
968 (define_predicate "small_addr_symbolic_operand"
969 (and (match_code "symbol_ref")
970 (match_test "SYMBOL_REF_SMALL_ADDR_P (op)")))
975 And here is another, showing the use of the C block.
979 ;; @r{True if @var{op} is a register operand that is (or could be) a GR reg.}
980 (define_predicate "gr_register_operand"
981 (match_operand 0 "register_operand")
984 if (GET_CODE (op) == SUBREG)
985 op = SUBREG_REG (op);
988 return (regno >= FIRST_PSEUDO_REGISTER || GENERAL_REGNO_P (regno));
993 Predicates written with @code{define_predicate} automatically include
994 a test that @var{mode} is @code{VOIDmode}, or @var{op} has the same
995 mode as @var{mode}, or @var{op} is a @code{CONST_INT} or
996 @code{CONST_DOUBLE}. They do @emph{not} check specifically for
997 integer @code{CONST_DOUBLE}, nor do they test that the value of either
998 kind of constant fits in the requested mode. This is because
999 target-specific predicates that take constants usually have to do more
1000 stringent value checks anyway. If you need the exact same treatment
1001 of @code{CONST_INT} or @code{CONST_DOUBLE} that the generic predicates
1002 provide, use a @code{MATCH_OPERAND} subexpression to call
1003 @code{const_int_operand}, @code{const_double_operand}, or
1004 @code{immediate_operand}.
1006 Predicates written with @code{define_special_predicate} do not get any
1007 automatic mode checks, and are treated as having special mode handling
1008 by @command{genrecog}.
1010 The program @command{genpreds} is responsible for generating code to
1011 test predicates. It also writes a header file containing function
1012 declarations for all machine-specific predicates. It is not necessary
1013 to declare these predicates in @file{@var{cpu}-protos.h}.
1016 @c Most of this node appears by itself (in a different place) even
1017 @c when the INTERNALS flag is clear. Passages that require the internals
1018 @c manual's context are conditionalized to appear only in the internals manual.
1021 @section Operand Constraints
1022 @cindex operand constraints
1025 Each @code{match_operand} in an instruction pattern can specify
1026 constraints for the operands allowed. The constraints allow you to
1027 fine-tune matching within the set of operands allowed by the
1033 @section Constraints for @code{asm} Operands
1034 @cindex operand constraints, @code{asm}
1035 @cindex constraints, @code{asm}
1036 @cindex @code{asm} constraints
1038 Here are specific details on what constraint letters you can use with
1039 @code{asm} operands.
1041 Constraints can say whether
1042 an operand may be in a register, and which kinds of register; whether the
1043 operand can be a memory reference, and which kinds of address; whether the
1044 operand may be an immediate constant, and which possible values it may
1045 have. Constraints can also require two operands to match.
1049 * Simple Constraints:: Basic use of constraints.
1050 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1051 * Class Preferences:: Constraints guide which hard register to put things in.
1052 * Modifiers:: More precise control over effects of constraints.
1053 * Machine Constraints:: Existing constraints for some particular machines.
1054 * Define Constraints:: How to define machine-specific constraints.
1055 * C Constraint Interface:: How to test constraints from C code.
1061 * Simple Constraints:: Basic use of constraints.
1062 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1063 * Modifiers:: More precise control over effects of constraints.
1064 * Machine Constraints:: Special constraints for some particular machines.
1068 @node Simple Constraints
1069 @subsection Simple Constraints
1070 @cindex simple constraints
1072 The simplest kind of constraint is a string full of letters, each of
1073 which describes one kind of operand that is permitted. Here are
1074 the letters that are allowed:
1078 Whitespace characters are ignored and can be inserted at any position
1079 except the first. This enables each alternative for different operands to
1080 be visually aligned in the machine description even if they have different
1081 number of constraints and modifiers.
1083 @cindex @samp{m} in constraint
1084 @cindex memory references in constraints
1086 A memory operand is allowed, with any kind of address that the machine
1087 supports in general.
1088 Note that the letter used for the general memory constraint can be
1089 re-defined by a back end using the @code{TARGET_MEM_CONSTRAINT} macro.
1091 @cindex offsettable address
1092 @cindex @samp{o} in constraint
1094 A memory operand is allowed, but only if the address is
1095 @dfn{offsettable}. This means that adding a small integer (actually,
1096 the width in bytes of the operand, as determined by its machine mode)
1097 may be added to the address and the result is also a valid memory
1100 @cindex autoincrement/decrement addressing
1101 For example, an address which is constant is offsettable; so is an
1102 address that is the sum of a register and a constant (as long as a
1103 slightly larger constant is also within the range of address-offsets
1104 supported by the machine); but an autoincrement or autodecrement
1105 address is not offsettable. More complicated indirect/indexed
1106 addresses may or may not be offsettable depending on the other
1107 addressing modes that the machine supports.
1109 Note that in an output operand which can be matched by another
1110 operand, the constraint letter @samp{o} is valid only when accompanied
1111 by both @samp{<} (if the target machine has predecrement addressing)
1112 and @samp{>} (if the target machine has preincrement addressing).
1114 @cindex @samp{V} in constraint
1116 A memory operand that is not offsettable. In other words, anything that
1117 would fit the @samp{m} constraint but not the @samp{o} constraint.
1119 @cindex @samp{<} in constraint
1121 A memory operand with autodecrement addressing (either predecrement or
1122 postdecrement) is allowed.
1124 @cindex @samp{>} in constraint
1126 A memory operand with autoincrement addressing (either preincrement or
1127 postincrement) is allowed.
1129 @cindex @samp{r} in constraint
1130 @cindex registers in constraints
1132 A register operand is allowed provided that it is in a general
1135 @cindex constants in constraints
1136 @cindex @samp{i} in constraint
1138 An immediate integer operand (one with constant value) is allowed.
1139 This includes symbolic constants whose values will be known only at
1140 assembly time or later.
1142 @cindex @samp{n} in constraint
1144 An immediate integer operand with a known numeric value is allowed.
1145 Many systems cannot support assembly-time constants for operands less
1146 than a word wide. Constraints for these operands should use @samp{n}
1147 rather than @samp{i}.
1149 @cindex @samp{I} in constraint
1150 @item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P}
1151 Other letters in the range @samp{I} through @samp{P} may be defined in
1152 a machine-dependent fashion to permit immediate integer operands with
1153 explicit integer values in specified ranges. For example, on the
1154 68000, @samp{I} is defined to stand for the range of values 1 to 8.
1155 This is the range permitted as a shift count in the shift
1158 @cindex @samp{E} in constraint
1160 An immediate floating operand (expression code @code{const_double}) is
1161 allowed, but only if the target floating point format is the same as
1162 that of the host machine (on which the compiler is running).
1164 @cindex @samp{F} in constraint
1166 An immediate floating operand (expression code @code{const_double} or
1167 @code{const_vector}) is allowed.
1169 @cindex @samp{G} in constraint
1170 @cindex @samp{H} in constraint
1171 @item @samp{G}, @samp{H}
1172 @samp{G} and @samp{H} may be defined in a machine-dependent fashion to
1173 permit immediate floating operands in particular ranges of values.
1175 @cindex @samp{s} in constraint
1177 An immediate integer operand whose value is not an explicit integer is
1180 This might appear strange; if an insn allows a constant operand with a
1181 value not known at compile time, it certainly must allow any known
1182 value. So why use @samp{s} instead of @samp{i}? Sometimes it allows
1183 better code to be generated.
1185 For example, on the 68000 in a fullword instruction it is possible to
1186 use an immediate operand; but if the immediate value is between @minus{}128
1187 and 127, better code results from loading the value into a register and
1188 using the register. This is because the load into the register can be
1189 done with a @samp{moveq} instruction. We arrange for this to happen
1190 by defining the letter @samp{K} to mean ``any integer outside the
1191 range @minus{}128 to 127'', and then specifying @samp{Ks} in the operand
1194 @cindex @samp{g} in constraint
1196 Any register, memory or immediate integer operand is allowed, except for
1197 registers that are not general registers.
1199 @cindex @samp{X} in constraint
1202 Any operand whatsoever is allowed, even if it does not satisfy
1203 @code{general_operand}. This is normally used in the constraint of
1204 a @code{match_scratch} when certain alternatives will not actually
1205 require a scratch register.
1208 Any operand whatsoever is allowed.
1211 @cindex @samp{0} in constraint
1212 @cindex digits in constraint
1213 @item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9}
1214 An operand that matches the specified operand number is allowed. If a
1215 digit is used together with letters within the same alternative, the
1216 digit should come last.
1218 This number is allowed to be more than a single digit. If multiple
1219 digits are encountered consecutively, they are interpreted as a single
1220 decimal integer. There is scant chance for ambiguity, since to-date
1221 it has never been desirable that @samp{10} be interpreted as matching
1222 either operand 1 @emph{or} operand 0. Should this be desired, one
1223 can use multiple alternatives instead.
1225 @cindex matching constraint
1226 @cindex constraint, matching
1227 This is called a @dfn{matching constraint} and what it really means is
1228 that the assembler has only a single operand that fills two roles
1230 considered separate in the RTL insn. For example, an add insn has two
1231 input operands and one output operand in the RTL, but on most CISC
1234 which @code{asm} distinguishes. For example, an add instruction uses
1235 two input operands and an output operand, but on most CISC
1237 machines an add instruction really has only two operands, one of them an
1238 input-output operand:
1244 Matching constraints are used in these circumstances.
1245 More precisely, the two operands that match must include one input-only
1246 operand and one output-only operand. Moreover, the digit must be a
1247 smaller number than the number of the operand that uses it in the
1251 For operands to match in a particular case usually means that they
1252 are identical-looking RTL expressions. But in a few special cases
1253 specific kinds of dissimilarity are allowed. For example, @code{*x}
1254 as an input operand will match @code{*x++} as an output operand.
1255 For proper results in such cases, the output template should always
1256 use the output-operand's number when printing the operand.
1259 @cindex load address instruction
1260 @cindex push address instruction
1261 @cindex address constraints
1262 @cindex @samp{p} in constraint
1264 An operand that is a valid memory address is allowed. This is
1265 for ``load address'' and ``push address'' instructions.
1267 @findex address_operand
1268 @samp{p} in the constraint must be accompanied by @code{address_operand}
1269 as the predicate in the @code{match_operand}. This predicate interprets
1270 the mode specified in the @code{match_operand} as the mode of the memory
1271 reference for which the address would be valid.
1273 @cindex other register constraints
1274 @cindex extensible constraints
1275 @item @var{other-letters}
1276 Other letters can be defined in machine-dependent fashion to stand for
1277 particular classes of registers or other arbitrary operand types.
1278 @samp{d}, @samp{a} and @samp{f} are defined on the 68000/68020 to stand
1279 for data, address and floating point registers.
1283 In order to have valid assembler code, each operand must satisfy
1284 its constraint. But a failure to do so does not prevent the pattern
1285 from applying to an insn. Instead, it directs the compiler to modify
1286 the code so that the constraint will be satisfied. Usually this is
1287 done by copying an operand into a register.
1289 Contrast, therefore, the two instruction patterns that follow:
1293 [(set (match_operand:SI 0 "general_operand" "=r")
1294 (plus:SI (match_dup 0)
1295 (match_operand:SI 1 "general_operand" "r")))]
1301 which has two operands, one of which must appear in two places, and
1305 [(set (match_operand:SI 0 "general_operand" "=r")
1306 (plus:SI (match_operand:SI 1 "general_operand" "0")
1307 (match_operand:SI 2 "general_operand" "r")))]
1313 which has three operands, two of which are required by a constraint to be
1314 identical. If we are considering an insn of the form
1317 (insn @var{n} @var{prev} @var{next}
1319 (plus:SI (reg:SI 6) (reg:SI 109)))
1324 the first pattern would not apply at all, because this insn does not
1325 contain two identical subexpressions in the right place. The pattern would
1326 say, ``That does not look like an add instruction; try other patterns''.
1327 The second pattern would say, ``Yes, that's an add instruction, but there
1328 is something wrong with it''. It would direct the reload pass of the
1329 compiler to generate additional insns to make the constraint true. The
1330 results might look like this:
1333 (insn @var{n2} @var{prev} @var{n}
1334 (set (reg:SI 3) (reg:SI 6))
1337 (insn @var{n} @var{n2} @var{next}
1339 (plus:SI (reg:SI 3) (reg:SI 109)))
1343 It is up to you to make sure that each operand, in each pattern, has
1344 constraints that can handle any RTL expression that could be present for
1345 that operand. (When multiple alternatives are in use, each pattern must,
1346 for each possible combination of operand expressions, have at least one
1347 alternative which can handle that combination of operands.) The
1348 constraints don't need to @emph{allow} any possible operand---when this is
1349 the case, they do not constrain---but they must at least point the way to
1350 reloading any possible operand so that it will fit.
1354 If the constraint accepts whatever operands the predicate permits,
1355 there is no problem: reloading is never necessary for this operand.
1357 For example, an operand whose constraints permit everything except
1358 registers is safe provided its predicate rejects registers.
1360 An operand whose predicate accepts only constant values is safe
1361 provided its constraints include the letter @samp{i}. If any possible
1362 constant value is accepted, then nothing less than @samp{i} will do;
1363 if the predicate is more selective, then the constraints may also be
1367 Any operand expression can be reloaded by copying it into a register.
1368 So if an operand's constraints allow some kind of register, it is
1369 certain to be safe. It need not permit all classes of registers; the
1370 compiler knows how to copy a register into another register of the
1371 proper class in order to make an instruction valid.
1373 @cindex nonoffsettable memory reference
1374 @cindex memory reference, nonoffsettable
1376 A nonoffsettable memory reference can be reloaded by copying the
1377 address into a register. So if the constraint uses the letter
1378 @samp{o}, all memory references are taken care of.
1381 A constant operand can be reloaded by allocating space in memory to
1382 hold it as preinitialized data. Then the memory reference can be used
1383 in place of the constant. So if the constraint uses the letters
1384 @samp{o} or @samp{m}, constant operands are not a problem.
1387 If the constraint permits a constant and a pseudo register used in an insn
1388 was not allocated to a hard register and is equivalent to a constant,
1389 the register will be replaced with the constant. If the predicate does
1390 not permit a constant and the insn is re-recognized for some reason, the
1391 compiler will crash. Thus the predicate must always recognize any
1392 objects allowed by the constraint.
1395 If the operand's predicate can recognize registers, but the constraint does
1396 not permit them, it can make the compiler crash. When this operand happens
1397 to be a register, the reload pass will be stymied, because it does not know
1398 how to copy a register temporarily into memory.
1400 If the predicate accepts a unary operator, the constraint applies to the
1401 operand. For example, the MIPS processor at ISA level 3 supports an
1402 instruction which adds two registers in @code{SImode} to produce a
1403 @code{DImode} result, but only if the registers are correctly sign
1404 extended. This predicate for the input operands accepts a
1405 @code{sign_extend} of an @code{SImode} register. Write the constraint
1406 to indicate the type of register that is required for the operand of the
1410 @node Multi-Alternative
1411 @subsection Multiple Alternative Constraints
1412 @cindex multiple alternative constraints
1414 Sometimes a single instruction has multiple alternative sets of possible
1415 operands. For example, on the 68000, a logical-or instruction can combine
1416 register or an immediate value into memory, or it can combine any kind of
1417 operand into a register; but it cannot combine one memory location into
1420 These constraints are represented as multiple alternatives. An alternative
1421 can be described by a series of letters for each operand. The overall
1422 constraint for an operand is made from the letters for this operand
1423 from the first alternative, a comma, the letters for this operand from
1424 the second alternative, a comma, and so on until the last alternative.
1426 Here is how it is done for fullword logical-or on the 68000:
1429 (define_insn "iorsi3"
1430 [(set (match_operand:SI 0 "general_operand" "=m,d")
1431 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
1432 (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
1436 The first alternative has @samp{m} (memory) for operand 0, @samp{0} for
1437 operand 1 (meaning it must match operand 0), and @samp{dKs} for operand
1438 2. The second alternative has @samp{d} (data register) for operand 0,
1439 @samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and
1440 @samp{%} in the constraints apply to all the alternatives; their
1441 meaning is explained in the next section (@pxref{Class Preferences}).
1444 @c FIXME Is this ? and ! stuff of use in asm()? If not, hide unless INTERNAL
1445 If all the operands fit any one alternative, the instruction is valid.
1446 Otherwise, for each alternative, the compiler counts how many instructions
1447 must be added to copy the operands so that that alternative applies.
1448 The alternative requiring the least copying is chosen. If two alternatives
1449 need the same amount of copying, the one that comes first is chosen.
1450 These choices can be altered with the @samp{?} and @samp{!} characters:
1453 @cindex @samp{?} in constraint
1454 @cindex question mark
1456 Disparage slightly the alternative that the @samp{?} appears in,
1457 as a choice when no alternative applies exactly. The compiler regards
1458 this alternative as one unit more costly for each @samp{?} that appears
1461 @cindex @samp{!} in constraint
1462 @cindex exclamation point
1464 Disparage severely the alternative that the @samp{!} appears in.
1465 This alternative can still be used if it fits without reloading,
1466 but if reloading is needed, some other alternative will be used.
1470 When an insn pattern has multiple alternatives in its constraints, often
1471 the appearance of the assembler code is determined mostly by which
1472 alternative was matched. When this is so, the C code for writing the
1473 assembler code can use the variable @code{which_alternative}, which is
1474 the ordinal number of the alternative that was actually satisfied (0 for
1475 the first, 1 for the second alternative, etc.). @xref{Output Statement}.
1479 @node Class Preferences
1480 @subsection Register Class Preferences
1481 @cindex class preference constraints
1482 @cindex register class preference constraints
1484 @cindex voting between constraint alternatives
1485 The operand constraints have another function: they enable the compiler
1486 to decide which kind of hardware register a pseudo register is best
1487 allocated to. The compiler examines the constraints that apply to the
1488 insns that use the pseudo register, looking for the machine-dependent
1489 letters such as @samp{d} and @samp{a} that specify classes of registers.
1490 The pseudo register is put in whichever class gets the most ``votes''.
1491 The constraint letters @samp{g} and @samp{r} also vote: they vote in
1492 favor of a general register. The machine description says which registers
1493 are considered general.
1495 Of course, on some machines all registers are equivalent, and no register
1496 classes are defined. Then none of this complexity is relevant.
1500 @subsection Constraint Modifier Characters
1501 @cindex modifiers in constraints
1502 @cindex constraint modifier characters
1504 @c prevent bad page break with this line
1505 Here are constraint modifier characters.
1508 @cindex @samp{=} in constraint
1510 Means that this operand is write-only for this instruction: the previous
1511 value is discarded and replaced by output data.
1513 @cindex @samp{+} in constraint
1515 Means that this operand is both read and written by the instruction.
1517 When the compiler fixes up the operands to satisfy the constraints,
1518 it needs to know which operands are inputs to the instruction and
1519 which are outputs from it. @samp{=} identifies an output; @samp{+}
1520 identifies an operand that is both input and output; all other operands
1521 are assumed to be input only.
1523 If you specify @samp{=} or @samp{+} in a constraint, you put it in the
1524 first character of the constraint string.
1526 @cindex @samp{&} in constraint
1527 @cindex earlyclobber operand
1529 Means (in a particular alternative) that this operand is an
1530 @dfn{earlyclobber} operand, which is modified before the instruction is
1531 finished using the input operands. Therefore, this operand may not lie
1532 in a register that is used as an input operand or as part of any memory
1535 @samp{&} applies only to the alternative in which it is written. In
1536 constraints with multiple alternatives, sometimes one alternative
1537 requires @samp{&} while others do not. See, for example, the
1538 @samp{movdf} insn of the 68000.
1540 An input operand can be tied to an earlyclobber operand if its only
1541 use as an input occurs before the early result is written. Adding
1542 alternatives of this form often allows GCC to produce better code
1543 when only some of the inputs can be affected by the earlyclobber.
1544 See, for example, the @samp{mulsi3} insn of the ARM@.
1546 @samp{&} does not obviate the need to write @samp{=}.
1548 @cindex @samp{%} in constraint
1550 Declares the instruction to be commutative for this operand and the
1551 following operand. This means that the compiler may interchange the
1552 two operands if that is the cheapest way to make all operands fit the
1555 This is often used in patterns for addition instructions
1556 that really have only two operands: the result must go in one of the
1557 arguments. Here for example, is how the 68000 halfword-add
1558 instruction is defined:
1561 (define_insn "addhi3"
1562 [(set (match_operand:HI 0 "general_operand" "=m,r")
1563 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
1564 (match_operand:HI 2 "general_operand" "di,g")))]
1568 GCC can only handle one commutative pair in an asm; if you use more,
1569 the compiler may fail. Note that you need not use the modifier if
1570 the two alternatives are strictly identical; this would only waste
1571 time in the reload pass. The modifier is not operational after
1572 register allocation, so the result of @code{define_peephole2}
1573 and @code{define_split}s performed after reload cannot rely on
1574 @samp{%} to make the intended insn match.
1576 @cindex @samp{#} in constraint
1578 Says that all following characters, up to the next comma, are to be
1579 ignored as a constraint. They are significant only for choosing
1580 register preferences.
1582 @cindex @samp{*} in constraint
1584 Says that the following character should be ignored when choosing
1585 register preferences. @samp{*} has no effect on the meaning of the
1586 constraint as a constraint, and no effect on reloading.
1589 Here is an example: the 68000 has an instruction to sign-extend a
1590 halfword in a data register, and can also sign-extend a value by
1591 copying it into an address register. While either kind of register is
1592 acceptable, the constraints on an address-register destination are
1593 less strict, so it is best if register allocation makes an address
1594 register its goal. Therefore, @samp{*} is used so that the @samp{d}
1595 constraint letter (for data register) is ignored when computing
1596 register preferences.
1599 (define_insn "extendhisi2"
1600 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1602 (match_operand:HI 1 "general_operand" "0,g")))]
1608 @node Machine Constraints
1609 @subsection Constraints for Particular Machines
1610 @cindex machine specific constraints
1611 @cindex constraints, machine specific
1613 Whenever possible, you should use the general-purpose constraint letters
1614 in @code{asm} arguments, since they will convey meaning more readily to
1615 people reading your code. Failing that, use the constraint letters
1616 that usually have very similar meanings across architectures. The most
1617 commonly used constraints are @samp{m} and @samp{r} (for memory and
1618 general-purpose registers respectively; @pxref{Simple Constraints}), and
1619 @samp{I}, usually the letter indicating the most common
1620 immediate-constant format.
1622 Each architecture defines additional constraints. These constraints
1623 are used by the compiler itself for instruction generation, as well as
1624 for @code{asm} statements; therefore, some of the constraints are not
1625 particularly useful for @code{asm}. Here is a summary of some of the
1626 machine-dependent constraints available on some particular machines;
1627 it includes both constraints that are useful for @code{asm} and
1628 constraints that aren't. The compiler source file mentioned in the
1629 table heading for each architecture is the definitive reference for
1630 the meanings of that architecture's constraints.
1633 @item ARM family---@file{config/arm/arm.h}
1636 Floating-point register
1639 VFP floating-point register
1642 One of the floating-point constants 0.0, 0.5, 1.0, 2.0, 3.0, 4.0, 5.0
1646 Floating-point constant that would satisfy the constraint @samp{F} if it
1650 Integer that is valid as an immediate operand in a data processing
1651 instruction. That is, an integer in the range 0 to 255 rotated by a
1655 Integer in the range @minus{}4095 to 4095
1658 Integer that satisfies constraint @samp{I} when inverted (ones complement)
1661 Integer that satisfies constraint @samp{I} when negated (twos complement)
1664 Integer in the range 0 to 32
1667 A memory reference where the exact address is in a single register
1668 (`@samp{m}' is preferable for @code{asm} statements)
1671 An item in the constant pool
1674 A symbol in the text segment of the current file
1677 A memory reference suitable for VFP load/store insns (reg+constant offset)
1680 A memory reference suitable for iWMMXt load/store instructions.
1683 A memory reference suitable for the ARMv4 ldrsb instruction.
1686 @item AVR family---@file{config/avr/constraints.md}
1689 Registers from r0 to r15
1692 Registers from r16 to r23
1695 Registers from r16 to r31
1698 Registers from r24 to r31. These registers can be used in @samp{adiw} command
1701 Pointer register (r26--r31)
1704 Base pointer register (r28--r31)
1707 Stack pointer register (SPH:SPL)
1710 Temporary register r0
1713 Register pair X (r27:r26)
1716 Register pair Y (r29:r28)
1719 Register pair Z (r31:r30)
1722 Constant greater than @minus{}1, less than 64
1725 Constant greater than @minus{}64, less than 1
1734 Constant that fits in 8 bits
1737 Constant integer @minus{}1
1740 Constant integer 8, 16, or 24
1746 A floating point constant 0.0
1749 Integer constant in the range -6 @dots{} 5.
1752 A memory address based on Y or Z pointer with displacement.
1755 @item CRX Architecture---@file{config/crx/crx.h}
1759 Registers from r0 to r14 (registers without stack pointer)
1762 Register r16 (64-bit accumulator lo register)
1765 Register r17 (64-bit accumulator hi register)
1768 Register pair r16-r17. (64-bit accumulator lo-hi pair)
1771 Constant that fits in 3 bits
1774 Constant that fits in 4 bits
1777 Constant that fits in 5 bits
1780 Constant that is one of -1, 4, -4, 7, 8, 12, 16, 20, 32, 48
1783 Floating point constant that is legal for store immediate
1786 @item Hewlett-Packard PA-RISC---@file{config/pa/pa.h}
1792 Floating point register
1795 Shift amount register
1798 Floating point register (deprecated)
1801 Upper floating point register (32-bit), floating point register (64-bit)
1807 Signed 11-bit integer constant
1810 Signed 14-bit integer constant
1813 Integer constant that can be deposited with a @code{zdepi} instruction
1816 Signed 5-bit integer constant
1822 Integer constant that can be loaded with a @code{ldil} instruction
1825 Integer constant whose value plus one is a power of 2
1828 Integer constant that can be used for @code{and} operations in @code{depi}
1829 and @code{extru} instructions
1838 Floating-point constant 0.0
1841 A @code{lo_sum} data-linkage-table memory operand
1844 A memory operand that can be used as the destination operand of an
1845 integer store instruction
1848 A scaled or unscaled indexed memory operand
1851 A memory operand for floating-point loads and stores
1854 A register indirect memory operand
1857 @item PowerPC and IBM RS6000---@file{config/rs6000/rs6000.h}
1860 Address base register
1863 Floating point register
1869 @samp{MQ}, @samp{CTR}, or @samp{LINK} register
1878 @samp{LINK} register
1881 @samp{CR} register (condition register) number 0
1884 @samp{CR} register (condition register)
1887 @samp{FPMEM} stack memory for FPR-GPR transfers
1890 Signed 16-bit constant
1893 Unsigned 16-bit constant shifted left 16 bits (use @samp{L} instead for
1894 @code{SImode} constants)
1897 Unsigned 16-bit constant
1900 Signed 16-bit constant shifted left 16 bits
1903 Constant larger than 31
1912 Constant whose negation is a signed 16-bit constant
1915 Floating point constant that can be loaded into a register with one
1916 instruction per word
1919 Integer/Floating point constant that can be loaded into a register using
1923 Memory operand that is an offset from a register (@samp{m} is preferable
1924 for @code{asm} statements)
1927 Memory operand that is an indexed or indirect from a register (@samp{m} is
1928 preferable for @code{asm} statements)
1934 Address operand that is an indexed or indirect from a register (@samp{p} is
1935 preferable for @code{asm} statements)
1938 Constant suitable as a 64-bit mask operand
1941 Constant suitable as a 32-bit mask operand
1944 System V Release 4 small data area reference
1947 AND masks that can be performed by two rldic@{l, r@} instructions
1950 Vector constant that does not require memory
1954 @item MorphoTech family---@file{config/mt/mt.h}
1957 Constant for an arithmetic insn (16-bit signed integer).
1963 Constant for a logical insn (16-bit zero-extended integer).
1966 A constant that can be loaded with @code{lui} (i.e.@: the bottom 16
1970 A constant that takes two words to load (i.e.@: not matched by
1971 @code{I}, @code{K}, or @code{L}).
1974 Negative 16-bit constants other than -65536.
1977 A 15-bit signed integer constant.
1980 A positive 16-bit constant.
1983 @item Intel 386---@file{config/i386/constraints.md}
1986 Legacy register---the eight integer registers available on all
1987 i386 processors (@code{a}, @code{b}, @code{c}, @code{d},
1988 @code{si}, @code{di}, @code{bp}, @code{sp}).
1991 Any register accessible as @code{@var{r}l}. In 32-bit mode, @code{a},
1992 @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.
1995 Any register accessible as @code{@var{r}h}: @code{a}, @code{b},
1996 @code{c}, and @code{d}.
2000 Any register that can be used as the index in a base+index memory
2001 access: that is, any general register except the stack pointer.
2005 The @code{a} register.
2008 The @code{b} register.
2011 The @code{c} register.
2014 The @code{d} register.
2017 The @code{si} register.
2020 The @code{di} register.
2023 The @code{a} and @code{d} registers, as a pair (for instructions that
2024 return half the result in one and half in the other).
2027 Any 80387 floating-point (stack) register.
2030 Top of 80387 floating-point stack (@code{%st(0)}).
2033 Second from top of 80387 floating-point stack (@code{%st(1)}).
2047 Integer constant in the range 0 @dots{} 31, for 32-bit shifts.
2050 Integer constant in the range 0 @dots{} 63, for 64-bit shifts.
2053 Signed 8-bit integer constant.
2056 @code{0xFF} or @code{0xFFFF}, for andsi as a zero-extending move.
2059 0, 1, 2, or 3 (shifts for the @code{lea} instruction).
2062 Unsigned 8-bit integer constant (for @code{in} and @code{out}
2067 Integer constant in the range 0 @dots{} 127, for 128-bit shifts.
2071 Standard 80387 floating point constant.
2074 Standard SSE floating point constant.
2077 32-bit signed integer constant, or a symbolic reference known
2078 to fit that range (for immediate operands in sign-extending x86-64
2082 32-bit unsigned integer constant, or a symbolic reference known
2083 to fit that range (for immediate operands in zero-extending x86-64
2088 @item Intel IA-64---@file{config/ia64/ia64.h}
2091 General register @code{r0} to @code{r3} for @code{addl} instruction
2097 Predicate register (@samp{c} as in ``conditional'')
2100 Application register residing in M-unit
2103 Application register residing in I-unit
2106 Floating-point register
2110 Remember that @samp{m} allows postincrement and postdecrement which
2111 require printing with @samp{%Pn} on IA-64.
2112 Use @samp{S} to disallow postincrement and postdecrement.
2115 Floating-point constant 0.0 or 1.0
2118 14-bit signed integer constant
2121 22-bit signed integer constant
2124 8-bit signed integer constant for logical instructions
2127 8-bit adjusted signed integer constant for compare pseudo-ops
2130 6-bit unsigned integer constant for shift counts
2133 9-bit signed integer constant for load and store postincrements
2139 0 or @minus{}1 for @code{dep} instruction
2142 Non-volatile memory for floating-point loads and stores
2145 Integer constant in the range 1 to 4 for @code{shladd} instruction
2148 Memory operand except postincrement and postdecrement
2151 @item FRV---@file{config/frv/frv.h}
2154 Register in the class @code{ACC_REGS} (@code{acc0} to @code{acc7}).
2157 Register in the class @code{EVEN_ACC_REGS} (@code{acc0} to @code{acc7}).
2160 Register in the class @code{CC_REGS} (@code{fcc0} to @code{fcc3} and
2161 @code{icc0} to @code{icc3}).
2164 Register in the class @code{GPR_REGS} (@code{gr0} to @code{gr63}).
2167 Register in the class @code{EVEN_REGS} (@code{gr0} to @code{gr63}).
2168 Odd registers are excluded not in the class but through the use of a machine
2169 mode larger than 4 bytes.
2172 Register in the class @code{FPR_REGS} (@code{fr0} to @code{fr63}).
2175 Register in the class @code{FEVEN_REGS} (@code{fr0} to @code{fr63}).
2176 Odd registers are excluded not in the class but through the use of a machine
2177 mode larger than 4 bytes.
2180 Register in the class @code{LR_REG} (the @code{lr} register).
2183 Register in the class @code{QUAD_REGS} (@code{gr2} to @code{gr63}).
2184 Register numbers not divisible by 4 are excluded not in the class but through
2185 the use of a machine mode larger than 8 bytes.
2188 Register in the class @code{ICC_REGS} (@code{icc0} to @code{icc3}).
2191 Register in the class @code{FCC_REGS} (@code{fcc0} to @code{fcc3}).
2194 Register in the class @code{ICR_REGS} (@code{cc4} to @code{cc7}).
2197 Register in the class @code{FCR_REGS} (@code{cc0} to @code{cc3}).
2200 Register in the class @code{QUAD_FPR_REGS} (@code{fr0} to @code{fr63}).
2201 Register numbers not divisible by 4 are excluded not in the class but through
2202 the use of a machine mode larger than 8 bytes.
2205 Register in the class @code{SPR_REGS} (@code{lcr} and @code{lr}).
2208 Register in the class @code{QUAD_ACC_REGS} (@code{acc0} to @code{acc7}).
2211 Register in the class @code{ACCG_REGS} (@code{accg0} to @code{accg7}).
2214 Register in the class @code{CR_REGS} (@code{cc0} to @code{cc7}).
2217 Floating point constant zero
2220 6-bit signed integer constant
2223 10-bit signed integer constant
2226 16-bit signed integer constant
2229 16-bit unsigned integer constant
2232 12-bit signed integer constant that is negative---i.e.@: in the
2233 range of @minus{}2048 to @minus{}1
2239 12-bit signed integer constant that is greater than zero---i.e.@: in the
2244 @item Blackfin family---@file{config/bfin/constraints.md}
2253 A call clobbered P register.
2256 A single register. If @var{n} is in the range 0 to 7, the corresponding D
2257 register. If it is @code{A}, then the register P0.
2260 Even-numbered D register
2263 Odd-numbered D register
2266 Accumulator register.
2269 Even-numbered accumulator register.
2272 Odd-numbered accumulator register.
2284 Registers used for circular buffering, i.e. I, B, or L registers.
2299 Any D, P, B, M, I or L register.
2302 Additional registers typically used only in prologues and epilogues: RETS,
2303 RETN, RETI, RETX, RETE, ASTAT, SEQSTAT and USP.
2306 Any register except accumulators or CC.
2309 Signed 16 bit integer (in the range -32768 to 32767)
2312 Unsigned 16 bit integer (in the range 0 to 65535)
2315 Signed 7 bit integer (in the range -64 to 63)
2318 Unsigned 7 bit integer (in the range 0 to 127)
2321 Unsigned 5 bit integer (in the range 0 to 31)
2324 Signed 4 bit integer (in the range -8 to 7)
2327 Signed 3 bit integer (in the range -3 to 4)
2330 Unsigned 3 bit integer (in the range 0 to 7)
2333 Constant @var{n}, where @var{n} is a single-digit constant in the range 0 to 4.
2336 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2337 use with either accumulator.
2340 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2341 use only with accumulator A1.
2350 An integer constant with exactly a single bit set.
2353 An integer constant with all bits set except exactly one.
2361 @item M32C---@file{config/m32c/m32c.c}
2366 @samp{$sp}, @samp{$fb}, @samp{$sb}.
2369 Any control register, when they're 16 bits wide (nothing if control
2370 registers are 24 bits wide)
2373 Any control register, when they're 24 bits wide.
2382 $r0 or $r2, or $r2r0 for 32 bit values.
2385 $r1 or $r3, or $r3r1 for 32 bit values.
2388 A register that can hold a 64 bit value.
2391 $r0 or $r1 (registers with addressable high/low bytes)
2400 Address registers when they're 16 bits wide.
2403 Address registers when they're 24 bits wide.
2406 Registers that can hold QI values.
2409 Registers that can be used with displacements ($a0, $a1, $sb).
2412 Registers that can hold 32 bit values.
2415 Registers that can hold 16 bit values.
2418 Registers chat can hold 16 bit values, including all control
2422 $r0 through R1, plus $a0 and $a1.
2428 The memory-based pseudo-registers $mem0 through $mem15.
2431 Registers that can hold pointers (16 bit registers for r8c, m16c; 24
2432 bit registers for m32cm, m32c).
2435 Matches multiple registers in a PARALLEL to form a larger register.
2436 Used to match function return values.
2445 -32768 @dots{} 32767
2451 -8 @dots{} -1 or 1 @dots{} 8
2454 -16 @dots{} -1 or 1 @dots{} 16
2457 -32 @dots{} -1 or 1 @dots{} 32
2463 An 8 bit value with exactly one bit set.
2466 A 16 bit value with exactly one bit set.
2469 The common src/dest memory addressing modes.
2472 Memory addressed using $a0 or $a1.
2475 Memory addressed with immediate addresses.
2478 Memory addressed using the stack pointer ($sp).
2481 Memory addressed using the frame base register ($fb).
2484 Memory addressed using the small base register ($sb).
2490 @item MIPS---@file{config/mips/constraints.md}
2493 An address register. This is equivalent to @code{r} unless
2494 generating MIPS16 code.
2497 A floating-point register (if available).
2500 The @code{hi} register.
2503 The @code{lo} register.
2506 The @code{hi} and @code{lo} registers.
2509 A register suitable for use in an indirect jump. This will always be
2510 @code{$25} for @option{-mabicalls}.
2513 Equivalent to @code{r}; retained for backwards compatibility.
2516 A floating-point condition code register.
2519 A signed 16-bit constant (for arithmetic instructions).
2525 An unsigned 16-bit constant (for logic instructions).
2528 A signed 32-bit constant in which the lower 16 bits are zero.
2529 Such constants can be loaded using @code{lui}.
2532 A constant that cannot be loaded using @code{lui}, @code{addiu}
2536 A constant in the range -65535 to -1 (inclusive).
2539 A signed 15-bit constant.
2542 A constant in the range 1 to 65535 (inclusive).
2545 Floating-point zero.
2548 An address that can be used in a non-macro load or store.
2551 @item Motorola 680x0---@file{config/m68k/constraints.md}
2560 68881 floating-point register, if available
2563 Integer in the range 1 to 8
2566 16-bit signed number
2569 Signed number whose magnitude is greater than 0x80
2572 Integer in the range @minus{}8 to @minus{}1
2575 Signed number whose magnitude is greater than 0x100
2578 Range 24 to 31, rotatert:SI 8 to 1 expressed as rotate
2581 16 (for rotate using swap)
2584 Range 8 to 15, rotatert:HI 8 to 1 expressed as rotate
2587 Numbers that mov3q can handle
2590 Floating point constant that is not a 68881 constant
2593 Operands that satisfy 'm' when -mpcrel is in effect
2596 Operands that satisfy 's' when -mpcrel is not in effect
2599 Address register indirect addressing mode
2602 Register offset addressing
2617 Range of signed numbers that don't fit in 16 bits
2620 Integers valid for mvq
2623 Integers valid for a moveq followed by a swap
2626 Integers valid for mvz
2629 Integers valid for mvs
2635 Non-register operands allowed in clr
2639 @item Motorola 68HC11 & 68HC12 families---@file{config/m68hc11/m68hc11.h}
2654 Temporary soft register _.tmp
2657 A soft register _.d1 to _.d31
2660 Stack pointer register
2669 Pseudo register `z' (replaced by `x' or `y' at the end)
2672 An address register: x, y or z
2675 An address register: x or y
2678 Register pair (x:d) to form a 32-bit value
2681 Constants in the range @minus{}65536 to 65535
2684 Constants whose 16-bit low part is zero
2687 Constant integer 1 or @minus{}1
2693 Constants in the range @minus{}8 to 2
2698 @item SPARC---@file{config/sparc/sparc.h}
2701 Floating-point register on the SPARC-V8 architecture and
2702 lower floating-point register on the SPARC-V9 architecture.
2705 Floating-point register. It is equivalent to @samp{f} on the
2706 SPARC-V8 architecture and contains both lower and upper
2707 floating-point registers on the SPARC-V9 architecture.
2710 Floating-point condition code register.
2713 Lower floating-point register. It is only valid on the SPARC-V9
2714 architecture when the Visual Instruction Set is available.
2717 Floating-point register. It is only valid on the SPARC-V9 architecture
2718 when the Visual Instruction Set is available.
2721 64-bit global or out register for the SPARC-V8+ architecture.
2724 Signed 13-bit constant
2730 32-bit constant with the low 12 bits clear (a constant that can be
2731 loaded with the @code{sethi} instruction)
2734 A constant in the range supported by @code{movcc} instructions
2737 A constant in the range supported by @code{movrcc} instructions
2740 Same as @samp{K}, except that it verifies that bits that are not in the
2741 lower 32-bit range are all zero. Must be used instead of @samp{K} for
2742 modes wider than @code{SImode}
2751 Signed 13-bit constant, sign-extended to 32 or 64 bits
2754 Floating-point constant whose integral representation can
2755 be moved into an integer register using a single sethi
2759 Floating-point constant whose integral representation can
2760 be moved into an integer register using a single mov
2764 Floating-point constant whose integral representation can
2765 be moved into an integer register using a high/lo_sum
2766 instruction sequence
2769 Memory address aligned to an 8-byte boundary
2775 Memory address for @samp{e} constraint registers
2782 @item SPU---@file{config/spu/spu.h}
2785 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 64 bit value.
2788 An immediate for and/xor/or instructions. const_int is treated as a 64 bit value.
2791 An immediate for the @code{iohl} instruction. const_int is treated as a 64 bit value.
2794 An immediate which can be loaded with @code{fsmbi}.
2797 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 32 bit value.
2800 An immediate for most arithmetic instructions. const_int is treated as a 32 bit value.
2803 An immediate for and/xor/or instructions. const_int is treated as a 32 bit value.
2806 An immediate for the @code{iohl} instruction. const_int is treated as a 32 bit value.
2809 A constant in the range [-64, 63] for shift/rotate instructions.
2812 An unsigned 7-bit constant for conversion/nop/channel instructions.
2815 A signed 10-bit constant for most arithmetic instructions.
2818 A signed 16 bit immediate for @code{stop}.
2821 An unsigned 16-bit constant for @code{iohl} and @code{fsmbi}.
2824 An unsigned 7-bit constant whose 3 least significant bits are 0.
2827 An unsigned 3-bit constant for 16-byte rotates and shifts
2830 Call operand, reg, for indirect calls
2833 Call operand, symbol, for relative calls.
2836 Call operand, const_int, for absolute calls.
2839 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is sign extended to 128 bit.
2842 An immediate for shift and rotate instructions. const_int is treated as a 32 bit value.
2845 An immediate for and/xor/or instructions. const_int is sign extended as a 128 bit.
2848 An immediate for the @code{iohl} instruction. const_int is sign extended to 128 bit.
2852 @item S/390 and zSeries---@file{config/s390/s390.h}
2855 Address register (general purpose register except r0)
2858 Condition code register
2861 Data register (arbitrary general purpose register)
2864 Floating-point register
2867 Unsigned 8-bit constant (0--255)
2870 Unsigned 12-bit constant (0--4095)
2873 Signed 16-bit constant (@minus{}32768--32767)
2876 Value appropriate as displacement.
2879 for short displacement
2880 @item (-524288..524287)
2881 for long displacement
2885 Constant integer with a value of 0x7fffffff.
2888 Multiple letter constraint followed by 4 parameter letters.
2891 number of the part counting from most to least significant
2895 mode of the containing operand
2897 value of the other parts (F---all bits set)
2899 The constraint matches if the specified part of a constant
2900 has a value different from its other parts.
2903 Memory reference without index register and with short displacement.
2906 Memory reference with index register and short displacement.
2909 Memory reference without index register but with long displacement.
2912 Memory reference with index register and long displacement.
2915 Pointer with short displacement.
2918 Pointer with long displacement.
2921 Shift count operand.
2925 @item Score family---@file{config/score/score.h}
2928 Registers from r0 to r32.
2931 Registers from r0 to r16.
2934 r8---r11 or r22---r27 registers.
2955 cnt + lcb + scb register.
2958 cr0---cr15 register.
2970 cp1 + cp2 + cp3 registers.
2973 High 16-bit constant (32-bit constant with 16 LSBs zero).
2976 Unsigned 5 bit integer (in the range 0 to 31).
2979 Unsigned 16 bit integer (in the range 0 to 65535).
2982 Signed 16 bit integer (in the range @minus{}32768 to 32767).
2985 Unsigned 14 bit integer (in the range 0 to 16383).
2988 Signed 14 bit integer (in the range @minus{}8192 to 8191).
2994 @item Xstormy16---@file{config/stormy16/stormy16.h}
3009 Registers r0 through r7.
3012 Registers r0 and r1.
3018 Registers r8 and r9.
3021 A constant between 0 and 3 inclusive.
3024 A constant that has exactly one bit set.
3027 A constant that has exactly one bit clear.
3030 A constant between 0 and 255 inclusive.
3033 A constant between @minus{}255 and 0 inclusive.
3036 A constant between @minus{}3 and 0 inclusive.
3039 A constant between 1 and 4 inclusive.
3042 A constant between @minus{}4 and @minus{}1 inclusive.
3045 A memory reference that is a stack push.
3048 A memory reference that is a stack pop.
3051 A memory reference that refers to a constant address of known value.
3054 The register indicated by Rx (not implemented yet).
3057 A constant that is not between 2 and 15 inclusive.
3064 @item Xtensa---@file{config/xtensa/constraints.md}
3067 General-purpose 32-bit register
3070 One-bit boolean register
3073 MAC16 40-bit accumulator register
3076 Signed 12-bit integer constant, for use in MOVI instructions
3079 Signed 8-bit integer constant, for use in ADDI instructions
3082 Integer constant valid for BccI instructions
3085 Unsigned constant valid for BccUI instructions
3092 @node Define Constraints
3093 @subsection Defining Machine-Specific Constraints
3094 @cindex defining constraints
3095 @cindex constraints, defining
3097 Machine-specific constraints fall into two categories: register and
3098 non-register constraints. Within the latter category, constraints
3099 which allow subsets of all possible memory or address operands should
3100 be specially marked, to give @code{reload} more information.
3102 Machine-specific constraints can be given names of arbitrary length,
3103 but they must be entirely composed of letters, digits, underscores
3104 (@samp{_}), and angle brackets (@samp{< >}). Like C identifiers, they
3105 must begin with a letter or underscore.
3107 In order to avoid ambiguity in operand constraint strings, no
3108 constraint can have a name that begins with any other constraint's
3109 name. For example, if @code{x} is defined as a constraint name,
3110 @code{xy} may not be, and vice versa. As a consequence of this rule,
3111 no constraint may begin with one of the generic constraint letters:
3112 @samp{E F V X g i m n o p r s}.
3114 Register constraints correspond directly to register classes.
3115 @xref{Register Classes}. There is thus not much flexibility in their
3118 @deffn {MD Expression} define_register_constraint name regclass docstring
3119 All three arguments are string constants.
3120 @var{name} is the name of the constraint, as it will appear in
3121 @code{match_operand} expressions. If @var{name} is a multi-letter
3122 constraint its length shall be the same for all constraints starting
3123 with the same letter. @var{regclass} can be either the
3124 name of the corresponding register class (@pxref{Register Classes}),
3125 or a C expression which evaluates to the appropriate register class.
3126 If it is an expression, it must have no side effects, and it cannot
3127 look at the operand. The usual use of expressions is to map some
3128 register constraints to @code{NO_REGS} when the register class
3129 is not available on a given subarchitecture.
3131 @var{docstring} is a sentence documenting the meaning of the
3132 constraint. Docstrings are explained further below.
3135 Non-register constraints are more like predicates: the constraint
3136 definition gives a Boolean expression which indicates whether the
3139 @deffn {MD Expression} define_constraint name docstring exp
3140 The @var{name} and @var{docstring} arguments are the same as for
3141 @code{define_register_constraint}, but note that the docstring comes
3142 immediately after the name for these expressions. @var{exp} is an RTL
3143 expression, obeying the same rules as the RTL expressions in predicate
3144 definitions. @xref{Defining Predicates}, for details. If it
3145 evaluates true, the constraint matches; if it evaluates false, it
3146 doesn't. Constraint expressions should indicate which RTL codes they
3147 might match, just like predicate expressions.
3149 @code{match_test} C expressions have access to the
3150 following variables:
3154 The RTL object defining the operand.
3156 The machine mode of @var{op}.
3158 @samp{INTVAL (@var{op})}, if @var{op} is a @code{const_int}.
3160 @samp{CONST_DOUBLE_HIGH (@var{op})}, if @var{op} is an integer
3161 @code{const_double}.
3163 @samp{CONST_DOUBLE_LOW (@var{op})}, if @var{op} is an integer
3164 @code{const_double}.
3166 @samp{CONST_DOUBLE_REAL_VALUE (@var{op})}, if @var{op} is a floating-point
3167 @code{const_double}.
3170 The @var{*val} variables should only be used once another piece of the
3171 expression has verified that @var{op} is the appropriate kind of RTL
3175 Most non-register constraints should be defined with
3176 @code{define_constraint}. The remaining two definition expressions
3177 are only appropriate for constraints that should be handled specially
3178 by @code{reload} if they fail to match.
3180 @deffn {MD Expression} define_memory_constraint name docstring exp
3181 Use this expression for constraints that match a subset of all memory
3182 operands: that is, @code{reload} can make them match by converting the
3183 operand to the form @samp{@w{(mem (reg @var{X}))}}, where @var{X} is a
3184 base register (from the register class specified by
3185 @code{BASE_REG_CLASS}, @pxref{Register Classes}).
3187 For example, on the S/390, some instructions do not accept arbitrary
3188 memory references, but only those that do not make use of an index
3189 register. The constraint letter @samp{Q} is defined to represent a
3190 memory address of this type. If @samp{Q} is defined with
3191 @code{define_memory_constraint}, a @samp{Q} constraint can handle any
3192 memory operand, because @code{reload} knows it can simply copy the
3193 memory address into a base register if required. This is analogous to
3194 the way a @samp{o} constraint can handle any memory operand.
3196 The syntax and semantics are otherwise identical to
3197 @code{define_constraint}.
3200 @deffn {MD Expression} define_address_constraint name docstring exp
3201 Use this expression for constraints that match a subset of all address
3202 operands: that is, @code{reload} can make the constraint match by
3203 converting the operand to the form @samp{@w{(reg @var{X})}}, again
3204 with @var{X} a base register.
3206 Constraints defined with @code{define_address_constraint} can only be
3207 used with the @code{address_operand} predicate, or machine-specific
3208 predicates that work the same way. They are treated analogously to
3209 the generic @samp{p} constraint.
3211 The syntax and semantics are otherwise identical to
3212 @code{define_constraint}.
3215 For historical reasons, names beginning with the letters @samp{G H}
3216 are reserved for constraints that match only @code{const_double}s, and
3217 names beginning with the letters @samp{I J K L M N O P} are reserved
3218 for constraints that match only @code{const_int}s. This may change in
3219 the future. For the time being, constraints with these names must be
3220 written in a stylized form, so that @code{genpreds} can tell you did
3225 (define_constraint "[@var{GHIJKLMNOP}]@dots{}"
3227 (and (match_code "const_int") ; @r{@code{const_double} for G/H}
3228 @var{condition}@dots{})) ; @r{usually a @code{match_test}}
3231 @c the semicolons line up in the formatted manual
3233 It is fine to use names beginning with other letters for constraints
3234 that match @code{const_double}s or @code{const_int}s.
3236 Each docstring in a constraint definition should be one or more complete
3237 sentences, marked up in Texinfo format. @emph{They are currently unused.}
3238 In the future they will be copied into the GCC manual, in @ref{Machine
3239 Constraints}, replacing the hand-maintained tables currently found in
3240 that section. Also, in the future the compiler may use this to give
3241 more helpful diagnostics when poor choice of @code{asm} constraints
3242 causes a reload failure.
3244 If you put the pseudo-Texinfo directive @samp{@@internal} at the
3245 beginning of a docstring, then (in the future) it will appear only in
3246 the internals manual's version of the machine-specific constraint tables.
3247 Use this for constraints that should not appear in @code{asm} statements.
3249 @node C Constraint Interface
3250 @subsection Testing constraints from C
3251 @cindex testing constraints
3252 @cindex constraints, testing
3254 It is occasionally useful to test a constraint from C code rather than
3255 implicitly via the constraint string in a @code{match_operand}. The
3256 generated file @file{tm_p.h} declares a few interfaces for working
3257 with machine-specific constraints. None of these interfaces work with
3258 the generic constraints described in @ref{Simple Constraints}. This
3259 may change in the future.
3261 @strong{Warning:} @file{tm_p.h} may declare other functions that
3262 operate on constraints, besides the ones documented here. Do not use
3263 those functions from machine-dependent code. They exist to implement
3264 the old constraint interface that machine-independent components of
3265 the compiler still expect. They will change or disappear in the
3268 Some valid constraint names are not valid C identifiers, so there is a
3269 mangling scheme for referring to them from C@. Constraint names that
3270 do not contain angle brackets or underscores are left unchanged.
3271 Underscores are doubled, each @samp{<} is replaced with @samp{_l}, and
3272 each @samp{>} with @samp{_g}. Here are some examples:
3274 @c the @c's prevent double blank lines in the printed manual.
3276 @multitable {Original} {Mangled}
3277 @item @strong{Original} @tab @strong{Mangled} @c
3278 @item @code{x} @tab @code{x} @c
3279 @item @code{P42x} @tab @code{P42x} @c
3280 @item @code{P4_x} @tab @code{P4__x} @c
3281 @item @code{P4>x} @tab @code{P4_gx} @c
3282 @item @code{P4>>} @tab @code{P4_g_g} @c
3283 @item @code{P4_g>} @tab @code{P4__g_g} @c
3287 Throughout this section, the variable @var{c} is either a constraint
3288 in the abstract sense, or a constant from @code{enum constraint_num};
3289 the variable @var{m} is a mangled constraint name (usually as part of
3290 a larger identifier).
3292 @deftp Enum constraint_num
3293 For each machine-specific constraint, there is a corresponding
3294 enumeration constant: @samp{CONSTRAINT_} plus the mangled name of the
3295 constraint. Functions that take an @code{enum constraint_num} as an
3296 argument expect one of these constants.
3298 Machine-independent constraints do not have associated constants.
3299 This may change in the future.
3302 @deftypefun {inline bool} satisfies_constraint_@var{m} (rtx @var{exp})
3303 For each machine-specific, non-register constraint @var{m}, there is
3304 one of these functions; it returns @code{true} if @var{exp} satisfies the
3305 constraint. These functions are only visible if @file{rtl.h} was included
3306 before @file{tm_p.h}.
3309 @deftypefun bool constraint_satisfied_p (rtx @var{exp}, enum constraint_num @var{c})
3310 Like the @code{satisfies_constraint_@var{m}} functions, but the
3311 constraint to test is given as an argument, @var{c}. If @var{c}
3312 specifies a register constraint, this function will always return
3316 @deftypefun {enum reg_class} regclass_for_constraint (enum constraint_num @var{c})
3317 Returns the register class associated with @var{c}. If @var{c} is not
3318 a register constraint, or those registers are not available for the
3319 currently selected subtarget, returns @code{NO_REGS}.
3322 Here is an example use of @code{satisfies_constraint_@var{m}}. In
3323 peephole optimizations (@pxref{Peephole Definitions}), operand
3324 constraint strings are ignored, so if there are relevant constraints,
3325 they must be tested in the C condition. In the example, the
3326 optimization is applied if operand 2 does @emph{not} satisfy the
3327 @samp{K} constraint. (This is a simplified version of a peephole
3328 definition from the i386 machine description.)
3332 [(match_scratch:SI 3 "r")
3333 (set (match_operand:SI 0 "register_operand" "")
3334 (mult:SI (match_operand:SI 1 "memory_operand" "")
3335 (match_operand:SI 2 "immediate_operand" "")))]
3337 "!satisfies_constraint_K (operands[2])"
3339 [(set (match_dup 3) (match_dup 1))
3340 (set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))]
3345 @node Standard Names
3346 @section Standard Pattern Names For Generation
3347 @cindex standard pattern names
3348 @cindex pattern names
3349 @cindex names, pattern
3351 Here is a table of the instruction names that are meaningful in the RTL
3352 generation pass of the compiler. Giving one of these names to an
3353 instruction pattern tells the RTL generation pass that it can use the
3354 pattern to accomplish a certain task.
3357 @cindex @code{mov@var{m}} instruction pattern
3358 @item @samp{mov@var{m}}
3359 Here @var{m} stands for a two-letter machine mode name, in lowercase.
3360 This instruction pattern moves data with that machine mode from operand
3361 1 to operand 0. For example, @samp{movsi} moves full-word data.
3363 If operand 0 is a @code{subreg} with mode @var{m} of a register whose
3364 own mode is wider than @var{m}, the effect of this instruction is
3365 to store the specified value in the part of the register that corresponds
3366 to mode @var{m}. Bits outside of @var{m}, but which are within the
3367 same target word as the @code{subreg} are undefined. Bits which are
3368 outside the target word are left unchanged.
3370 This class of patterns is special in several ways. First of all, each
3371 of these names up to and including full word size @emph{must} be defined,
3372 because there is no other way to copy a datum from one place to another.
3373 If there are patterns accepting operands in larger modes,
3374 @samp{mov@var{m}} must be defined for integer modes of those sizes.
3376 Second, these patterns are not used solely in the RTL generation pass.
3377 Even the reload pass can generate move insns to copy values from stack
3378 slots into temporary registers. When it does so, one of the operands is
3379 a hard register and the other is an operand that can need to be reloaded
3383 Therefore, when given such a pair of operands, the pattern must generate
3384 RTL which needs no reloading and needs no temporary registers---no
3385 registers other than the operands. For example, if you support the
3386 pattern with a @code{define_expand}, then in such a case the
3387 @code{define_expand} mustn't call @code{force_reg} or any other such
3388 function which might generate new pseudo registers.
3390 This requirement exists even for subword modes on a RISC machine where
3391 fetching those modes from memory normally requires several insns and
3392 some temporary registers.
3394 @findex change_address
3395 During reload a memory reference with an invalid address may be passed
3396 as an operand. Such an address will be replaced with a valid address
3397 later in the reload pass. In this case, nothing may be done with the
3398 address except to use it as it stands. If it is copied, it will not be
3399 replaced with a valid address. No attempt should be made to make such
3400 an address into a valid address and no routine (such as
3401 @code{change_address}) that will do so may be called. Note that
3402 @code{general_operand} will fail when applied to such an address.
3404 @findex reload_in_progress
3405 The global variable @code{reload_in_progress} (which must be explicitly
3406 declared if required) can be used to determine whether such special
3407 handling is required.
3409 The variety of operands that have reloads depends on the rest of the
3410 machine description, but typically on a RISC machine these can only be
3411 pseudo registers that did not get hard registers, while on other
3412 machines explicit memory references will get optional reloads.
3414 If a scratch register is required to move an object to or from memory,
3415 it can be allocated using @code{gen_reg_rtx} prior to life analysis.
3417 If there are cases which need scratch registers during or after reload,
3418 you must provide an appropriate secondary_reload target hook.
3420 @findex can_create_pseudo_p
3421 The macro @code{can_create_pseudo_p} can be used to determine if it
3422 is unsafe to create new pseudo registers. If this variable is nonzero, then
3423 it is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo.
3425 The constraints on a @samp{mov@var{m}} must permit moving any hard
3426 register to any other hard register provided that
3427 @code{HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and
3428 @code{REGISTER_MOVE_COST} applied to their classes returns a value of 2.
3430 It is obligatory to support floating point @samp{mov@var{m}}
3431 instructions into and out of any registers that can hold fixed point
3432 values, because unions and structures (which have modes @code{SImode} or
3433 @code{DImode}) can be in those registers and they may have floating
3436 There may also be a need to support fixed point @samp{mov@var{m}}
3437 instructions in and out of floating point registers. Unfortunately, I
3438 have forgotten why this was so, and I don't know whether it is still
3439 true. If @code{HARD_REGNO_MODE_OK} rejects fixed point values in
3440 floating point registers, then the constraints of the fixed point
3441 @samp{mov@var{m}} instructions must be designed to avoid ever trying to
3442 reload into a floating point register.
3444 @cindex @code{reload_in} instruction pattern
3445 @cindex @code{reload_out} instruction pattern
3446 @item @samp{reload_in@var{m}}
3447 @itemx @samp{reload_out@var{m}}
3448 These named patterns have been obsoleted by the target hook
3449 @code{secondary_reload}.
3451 Like @samp{mov@var{m}}, but used when a scratch register is required to
3452 move between operand 0 and operand 1. Operand 2 describes the scratch
3453 register. See the discussion of the @code{SECONDARY_RELOAD_CLASS}
3454 macro in @pxref{Register Classes}.
3456 There are special restrictions on the form of the @code{match_operand}s
3457 used in these patterns. First, only the predicate for the reload
3458 operand is examined, i.e., @code{reload_in} examines operand 1, but not
3459 the predicates for operand 0 or 2. Second, there may be only one
3460 alternative in the constraints. Third, only a single register class
3461 letter may be used for the constraint; subsequent constraint letters
3462 are ignored. As a special exception, an empty constraint string
3463 matches the @code{ALL_REGS} register class. This may relieve ports
3464 of the burden of defining an @code{ALL_REGS} constraint letter just
3467 @cindex @code{movstrict@var{m}} instruction pattern
3468 @item @samp{movstrict@var{m}}
3469 Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg}
3470 with mode @var{m} of a register whose natural mode is wider,
3471 the @samp{movstrict@var{m}} instruction is guaranteed not to alter
3472 any of the register except the part which belongs to mode @var{m}.
3474 @cindex @code{movmisalign@var{m}} instruction pattern
3475 @item @samp{movmisalign@var{m}}
3476 This variant of a move pattern is designed to load or store a value
3477 from a memory address that is not naturally aligned for its mode.
3478 For a store, the memory will be in operand 0; for a load, the memory
3479 will be in operand 1. The other operand is guaranteed not to be a
3480 memory, so that it's easy to tell whether this is a load or store.
3482 This pattern is used by the autovectorizer, and when expanding a
3483 @code{MISALIGNED_INDIRECT_REF} expression.
3485 @cindex @code{load_multiple} instruction pattern
3486 @item @samp{load_multiple}
3487 Load several consecutive memory locations into consecutive registers.
3488 Operand 0 is the first of the consecutive registers, operand 1
3489 is the first memory location, and operand 2 is a constant: the
3490 number of consecutive registers.
3492 Define this only if the target machine really has such an instruction;
3493 do not define this if the most efficient way of loading consecutive
3494 registers from memory is to do them one at a time.
3496 On some machines, there are restrictions as to which consecutive
3497 registers can be stored into memory, such as particular starting or
3498 ending register numbers or only a range of valid counts. For those
3499 machines, use a @code{define_expand} (@pxref{Expander Definitions})
3500 and make the pattern fail if the restrictions are not met.
3502 Write the generated insn as a @code{parallel} with elements being a
3503 @code{set} of one register from the appropriate memory location (you may
3504 also need @code{use} or @code{clobber} elements). Use a
3505 @code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See
3506 @file{rs6000.md} for examples of the use of this insn pattern.
3508 @cindex @samp{store_multiple} instruction pattern
3509 @item @samp{store_multiple}
3510 Similar to @samp{load_multiple}, but store several consecutive registers
3511 into consecutive memory locations. Operand 0 is the first of the
3512 consecutive memory locations, operand 1 is the first register, and
3513 operand 2 is a constant: the number of consecutive registers.
3515 @cindex @code{vec_set@var{m}} instruction pattern
3516 @item @samp{vec_set@var{m}}
3517 Set given field in the vector value. Operand 0 is the vector to modify,
3518 operand 1 is new value of field and operand 2 specify the field index.
3520 @cindex @code{vec_extract@var{m}} instruction pattern
3521 @item @samp{vec_extract@var{m}}
3522 Extract given field from the vector value. Operand 1 is the vector, operand 2
3523 specify field index and operand 0 place to store value into.
3525 @cindex @code{vec_extract_even@var{m}} instruction pattern
3526 @item @samp{vec_extract_even@var{m}}
3527 Extract even elements from the input vectors (operand 1 and operand 2).
3528 The even elements of operand 2 are concatenated to the even elements of operand
3529 1 in their original order. The result is stored in operand 0.
3530 The output and input vectors should have the same modes.
3532 @cindex @code{vec_extract_odd@var{m}} instruction pattern
3533 @item @samp{vec_extract_odd@var{m}}
3534 Extract odd elements from the input vectors (operand 1 and operand 2).
3535 The odd elements of operand 2 are concatenated to the odd elements of operand
3536 1 in their original order. The result is stored in operand 0.
3537 The output and input vectors should have the same modes.
3539 @cindex @code{vec_interleave_high@var{m}} instruction pattern
3540 @item @samp{vec_interleave_high@var{m}}
3541 Merge high elements of the two input vectors into the output vector. The output
3542 and input vectors should have the same modes (@code{N} elements). The high
3543 @code{N/2} elements of the first input vector are interleaved with the high
3544 @code{N/2} elements of the second input vector.
3546 @cindex @code{vec_interleave_low@var{m}} instruction pattern
3547 @item @samp{vec_interleave_low@var{m}}
3548 Merge low elements of the two input vectors into the output vector. The output
3549 and input vectors should have the same modes (@code{N} elements). The low
3550 @code{N/2} elements of the first input vector are interleaved with the low
3551 @code{N/2} elements of the second input vector.
3553 @cindex @code{vec_init@var{m}} instruction pattern
3554 @item @samp{vec_init@var{m}}
3555 Initialize the vector to given values. Operand 0 is the vector to initialize
3556 and operand 1 is parallel containing values for individual fields.
3558 @cindex @code{push@var{m}1} instruction pattern
3559 @item @samp{push@var{m}1}
3560 Output a push instruction. Operand 0 is value to push. Used only when
3561 @code{PUSH_ROUNDING} is defined. For historical reason, this pattern may be
3562 missing and in such case an @code{mov} expander is used instead, with a
3563 @code{MEM} expression forming the push operation. The @code{mov} expander
3564 method is deprecated.
3566 @cindex @code{add@var{m}3} instruction pattern
3567 @item @samp{add@var{m}3}
3568 Add operand 2 and operand 1, storing the result in operand 0. All operands
3569 must have mode @var{m}. This can be used even on two-address machines, by
3570 means of constraints requiring operands 1 and 0 to be the same location.
3572 @cindex @code{ssadd@var{m}3} instruction pattern
3573 @cindex @code{usadd@var{m}3} instruction pattern
3574 @cindex @code{sub@var{m}3} instruction pattern
3575 @cindex @code{sssub@var{m}3} instruction pattern
3576 @cindex @code{ussub@var{m}3} instruction pattern
3577 @cindex @code{mul@var{m}3} instruction pattern
3578 @cindex @code{ssmul@var{m}3} instruction pattern
3579 @cindex @code{usmul@var{m}3} instruction pattern
3580 @cindex @code{div@var{m}3} instruction pattern
3581 @cindex @code{ssdiv@var{m}3} instruction pattern
3582 @cindex @code{udiv@var{m}3} instruction pattern
3583 @cindex @code{usdiv@var{m}3} instruction pattern
3584 @cindex @code{mod@var{m}3} instruction pattern
3585 @cindex @code{umod@var{m}3} instruction pattern
3586 @cindex @code{umin@var{m}3} instruction pattern
3587 @cindex @code{umax@var{m}3} instruction pattern
3588 @cindex @code{and@var{m}3} instruction pattern
3589 @cindex @code{ior@var{m}3} instruction pattern
3590 @cindex @code{xor@var{m}3} instruction pattern
3591 @item @samp{ssadd@var{m}3}, @samp{usadd@var{m}3}
3592 @item @samp{sub@var{m}3}, @samp{sssub@var{m}3}, @samp{ussub@var{m}3}
3593 @item @samp{mul@var{m}3}, @samp{ssmul@var{m}3}, @samp{usmul@var{m}3}
3594 @itemx @samp{div@var{m}3}, @samp{ssdiv@var{m}3}
3595 @itemx @samp{udiv@var{m}3}, @samp{usdiv@var{m}3}
3596 @itemx @samp{mod@var{m}3}, @samp{umod@var{m}3}
3597 @itemx @samp{umin@var{m}3}, @samp{umax@var{m}3}
3598 @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3}
3599 Similar, for other arithmetic operations.
3601 @cindex @code{min@var{m}3} instruction pattern
3602 @cindex @code{max@var{m}3} instruction pattern
3603 @item @samp{smin@var{m}3}, @samp{smax@var{m}3}
3604 Signed minimum and maximum operations. When used with floating point,
3605 if both operands are zeros, or if either operand is @code{NaN}, then
3606 it is unspecified which of the two operands is returned as the result.
3608 @cindex @code{reduc_smin_@var{m}} instruction pattern
3609 @cindex @code{reduc_smax_@var{m}} instruction pattern
3610 @item @samp{reduc_smin_@var{m}}, @samp{reduc_smax_@var{m}}
3611 Find the signed minimum/maximum of the elements of a vector. The vector is
3612 operand 1, and the scalar result is stored in the least significant bits of
3613 operand 0 (also a vector). The output and input vector should have the same
3616 @cindex @code{reduc_umin_@var{m}} instruction pattern
3617 @cindex @code{reduc_umax_@var{m}} instruction pattern
3618 @item @samp{reduc_umin_@var{m}}, @samp{reduc_umax_@var{m}}
3619 Find the unsigned minimum/maximum of the elements of a vector. The vector is
3620 operand 1, and the scalar result is stored in the least significant bits of
3621 operand 0 (also a vector). The output and input vector should have the same
3624 @cindex @code{reduc_splus_@var{m}} instruction pattern
3625 @item @samp{reduc_splus_@var{m}}
3626 Compute the sum of the signed elements of a vector. The vector is operand 1,
3627 and the scalar result is stored in the least significant bits of operand 0
3628 (also a vector). The output and input vector should have the same modes.
3630 @cindex @code{reduc_uplus_@var{m}} instruction pattern
3631 @item @samp{reduc_uplus_@var{m}}
3632 Compute the sum of the unsigned elements of a vector. The vector is operand 1,
3633 and the scalar result is stored in the least significant bits of operand 0
3634 (also a vector). The output and input vector should have the same modes.
3636 @cindex @code{sdot_prod@var{m}} instruction pattern
3637 @item @samp{sdot_prod@var{m}}
3638 @cindex @code{udot_prod@var{m}} instruction pattern
3639 @item @samp{udot_prod@var{m}}
3640 Compute the sum of the products of two signed/unsigned elements.
3641 Operand 1 and operand 2 are of the same mode. Their product, which is of a
3642 wider mode, is computed and added to operand 3. Operand 3 is of a mode equal or
3643 wider than the mode of the product. The result is placed in operand 0, which
3644 is of the same mode as operand 3.
3646 @cindex @code{ssum_widen@var{m3}} instruction pattern
3647 @item @samp{ssum_widen@var{m3}}
3648 @cindex @code{usum_widen@var{m3}} instruction pattern
3649 @item @samp{usum_widen@var{m3}}
3650 Operands 0 and 2 are of the same mode, which is wider than the mode of
3651 operand 1. Add operand 1 to operand 2 and place the widened result in
3652 operand 0. (This is used express accumulation of elements into an accumulator
3655 @cindex @code{vec_shl_@var{m}} instruction pattern
3656 @cindex @code{vec_shr_@var{m}} instruction pattern
3657 @item @samp{vec_shl_@var{m}}, @samp{vec_shr_@var{m}}
3658 Whole vector left/right shift in bits.
3659 Operand 1 is a vector to be shifted.
3660 Operand 2 is an integer shift amount in bits.
3661 Operand 0 is where the resulting shifted vector is stored.
3662 The output and input vectors should have the same modes.
3664 @cindex @code{vec_pack_trunc_@var{m}} instruction pattern
3665 @item @samp{vec_pack_trunc_@var{m}}
3666 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
3667 are vectors of the same mode having N integral or floating point elements
3668 of size S@. Operand 0 is the resulting vector in which 2*N elements of
3669 size N/2 are concatenated after narrowing them down using truncation.
3671 @cindex @code{vec_pack_ssat_@var{m}} instruction pattern
3672 @cindex @code{vec_pack_usat_@var{m}} instruction pattern
3673 @item @samp{vec_pack_ssat_@var{m}}, @samp{vec_pack_usat_@var{m}}
3674 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
3675 are vectors of the same mode having N integral elements of size S.
3676 Operand 0 is the resulting vector in which the elements of the two input
3677 vectors are concatenated after narrowing them down using signed/unsigned
3678 saturating arithmetic.
3680 @cindex @code{vec_pack_sfix_trunc_@var{m}} instruction pattern
3681 @cindex @code{vec_pack_ufix_trunc_@var{m}} instruction pattern
3682 @item @samp{vec_pack_sfix_trunc_@var{m}}, @samp{vec_pack_ufix_trunc_@var{m}}
3683 Narrow, convert to signed/unsigned integral type and merge the elements
3684 of two vectors. Operands 1 and 2 are vectors of the same mode having N
3685 floating point elements of size S@. Operand 0 is the resulting vector
3686 in which 2*N elements of size N/2 are concatenated.
3688 @cindex @code{vec_unpacks_hi_@var{m}} instruction pattern
3689 @cindex @code{vec_unpacks_lo_@var{m}} instruction pattern
3690 @item @samp{vec_unpacks_hi_@var{m}}, @samp{vec_unpacks_lo_@var{m}}
3691 Extract and widen (promote) the high/low part of a vector of signed
3692 integral or floating point elements. The input vector (operand 1) has N
3693 elements of size S@. Widen (promote) the high/low elements of the vector
3694 using signed or floating point extension and place the resulting N/2
3695 values of size 2*S in the output vector (operand 0).
3697 @cindex @code{vec_unpacku_hi_@var{m}} instruction pattern
3698 @cindex @code{vec_unpacku_lo_@var{m}} instruction pattern
3699 @item @samp{vec_unpacku_hi_@var{m}}, @samp{vec_unpacku_lo_@var{m}}
3700 Extract and widen (promote) the high/low part of a vector of unsigned
3701 integral elements. The input vector (operand 1) has N elements of size S.
3702 Widen (promote) the high/low elements of the vector using zero extension and
3703 place the resulting N/2 values of size 2*S in the output vector (operand 0).
3705 @cindex @code{vec_unpacks_float_hi_@var{m}} instruction pattern
3706 @cindex @code{vec_unpacks_float_lo_@var{m}} instruction pattern
3707 @cindex @code{vec_unpacku_float_hi_@var{m}} instruction pattern
3708 @cindex @code{vec_unpacku_float_lo_@var{m}} instruction pattern
3709 @item @samp{vec_unpacks_float_hi_@var{m}}, @samp{vec_unpacks_float_lo_@var{m}}
3710 @itemx @samp{vec_unpacku_float_hi_@var{m}}, @samp{vec_unpacku_float_lo_@var{m}}
3711 Extract, convert to floating point type and widen the high/low part of a
3712 vector of signed/unsigned integral elements. The input vector (operand 1)
3713 has N elements of size S@. Convert the high/low elements of the vector using
3714 floating point conversion and place the resulting N/2 values of size 2*S in
3715 the output vector (operand 0).
3717 @cindex @code{vec_widen_umult_hi_@var{m}} instruction pattern
3718 @cindex @code{vec_widen_umult_lo__@var{m}} instruction pattern
3719 @cindex @code{vec_widen_smult_hi_@var{m}} instruction pattern
3720 @cindex @code{vec_widen_smult_lo_@var{m}} instruction pattern
3721 @item @samp{vec_widen_umult_hi_@var{m}}, @samp{vec_widen_umult_lo_@var{m}}
3722 @itemx @samp{vec_widen_smult_hi_@var{m}}, @samp{vec_widen_smult_lo_@var{m}}
3723 Signed/Unsigned widening multiplication. The two inputs (operands 1 and 2)
3724 are vectors with N signed/unsigned elements of size S@. Multiply the high/low
3725 elements of the two vectors, and put the N/2 products of size 2*S in the
3726 output vector (operand 0).
3728 @cindex @code{mulhisi3} instruction pattern
3729 @item @samp{mulhisi3}
3730 Multiply operands 1 and 2, which have mode @code{HImode}, and store
3731 a @code{SImode} product in operand 0.
3733 @cindex @code{mulqihi3} instruction pattern
3734 @cindex @code{mulsidi3} instruction pattern
3735 @item @samp{mulqihi3}, @samp{mulsidi3}
3736 Similar widening-multiplication instructions of other widths.
3738 @cindex @code{umulqihi3} instruction pattern
3739 @cindex @code{umulhisi3} instruction pattern
3740 @cindex @code{umulsidi3} instruction pattern
3741 @item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3}
3742 Similar widening-multiplication instructions that do unsigned
3745 @cindex @code{usmulqihi3} instruction pattern
3746 @cindex @code{usmulhisi3} instruction pattern
3747 @cindex @code{usmulsidi3} instruction pattern
3748 @item @samp{usmulqihi3}, @samp{usmulhisi3}, @samp{usmulsidi3}
3749 Similar widening-multiplication instructions that interpret the first
3750 operand as unsigned and the second operand as signed, then do a signed
3753 @cindex @code{smul@var{m}3_highpart} instruction pattern
3754 @item @samp{smul@var{m}3_highpart}
3755 Perform a signed multiplication of operands 1 and 2, which have mode
3756 @var{m}, and store the most significant half of the product in operand 0.
3757 The least significant half of the product is discarded.
3759 @cindex @code{umul@var{m}3_highpart} instruction pattern
3760 @item @samp{umul@var{m}3_highpart}
3761 Similar, but the multiplication is unsigned.
3763 @cindex @code{madd@var{m}@var{n}4} instruction pattern
3764 @item @samp{madd@var{m}@var{n}4}
3765 Multiply operands 1 and 2, sign-extend them to mode @var{n}, add
3766 operand 3, and store the result in operand 0. Operands 1 and 2
3767 have mode @var{m} and operands 0 and 3 have mode @var{n}.
3768 Both modes must be integer or fixed-point modes and @var{n} must be twice
3769 the size of @var{m}.
3771 In other words, @code{madd@var{m}@var{n}4} is like
3772 @code{mul@var{m}@var{n}3} except that it also adds operand 3.
3774 These instructions are not allowed to @code{FAIL}.
3776 @cindex @code{umadd@var{m}@var{n}4} instruction pattern
3777 @item @samp{umadd@var{m}@var{n}4}
3778 Like @code{madd@var{m}@var{n}4}, but zero-extend the multiplication
3779 operands instead of sign-extending them.
3781 @cindex @code{ssmadd@var{m}@var{n}4} instruction pattern
3782 @item @samp{ssmadd@var{m}@var{n}4}
3783 Like @code{madd@var{m}@var{n}4}, but all involved operations must be
3786 @cindex @code{usmadd@var{m}@var{n}4} instruction pattern
3787 @item @samp{usmadd@var{m}@var{n}4}
3788 Like @code{umadd@var{m}@var{n}4}, but all involved operations must be
3789 unsigned-saturating.
3791 @cindex @code{msub@var{m}@var{n}4} instruction pattern
3792 @item @samp{msub@var{m}@var{n}4}
3793 Multiply operands 1 and 2, sign-extend them to mode @var{n}, subtract the
3794 result from operand 3, and store the result in operand 0. Operands 1 and 2
3795 have mode @var{m} and operands 0 and 3 have mode @var{n}.
3796 Both modes must be integer or fixed-point modes and @var{n} must be twice
3797 the size of @var{m}.
3799 In other words, @code{msub@var{m}@var{n}4} is like
3800 @code{mul@var{m}@var{n}3} except that it also subtracts the result
3803 These instructions are not allowed to @code{FAIL}.
3805 @cindex @code{umsub@var{m}@var{n}4} instruction pattern
3806 @item @samp{umsub@var{m}@var{n}4}
3807 Like @code{msub@var{m}@var{n}4}, but zero-extend the multiplication
3808 operands instead of sign-extending them.
3810 @cindex @code{ssmsub@var{m}@var{n}4} instruction pattern
3811 @item @samp{ssmsub@var{m}@var{n}4}
3812 Like @code{msub@var{m}@var{n}4}, but all involved operations must be
3815 @cindex @code{usmsub@var{m}@var{n}4} instruction pattern
3816 @item @samp{usmsub@var{m}@var{n}4}
3817 Like @code{umsub@var{m}@var{n}4}, but all involved operations must be
3818 unsigned-saturating.
3820 @cindex @code{divmod@var{m}4} instruction pattern
3821 @item @samp{divmod@var{m}4}
3822 Signed division that produces both a quotient and a remainder.
3823 Operand 1 is divided by operand 2 to produce a quotient stored
3824 in operand 0 and a remainder stored in operand 3.
3826 For machines with an instruction that produces both a quotient and a
3827 remainder, provide a pattern for @samp{divmod@var{m}4} but do not
3828 provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This
3829 allows optimization in the relatively common case when both the quotient
3830 and remainder are computed.
3832 If an instruction that just produces a quotient or just a remainder
3833 exists and is more efficient than the instruction that produces both,
3834 write the output routine of @samp{divmod@var{m}4} to call
3835 @code{find_reg_note} and look for a @code{REG_UNUSED} note on the
3836 quotient or remainder and generate the appropriate instruction.
3838 @cindex @code{udivmod@var{m}4} instruction pattern
3839 @item @samp{udivmod@var{m}4}
3840 Similar, but does unsigned division.
3842 @anchor{shift patterns}
3843 @cindex @code{ashl@var{m}3} instruction pattern
3844 @cindex @code{ssashl@var{m}3} instruction pattern
3845 @cindex @code{usashl@var{m}3} instruction pattern
3846 @item @samp{ashl@var{m}3}, @samp{ssashl@var{m}3}, @samp{usashl@var{m}3}
3847 Arithmetic-shift operand 1 left by a number of bits specified by operand
3848 2, and store the result in operand 0. Here @var{m} is the mode of
3849 operand 0 and operand 1; operand 2's mode is specified by the
3850 instruction pattern, and the compiler will convert the operand to that
3851 mode before generating the instruction. The meaning of out-of-range shift
3852 counts can optionally be specified by @code{TARGET_SHIFT_TRUNCATION_MASK}.
3853 @xref{TARGET_SHIFT_TRUNCATION_MASK}. Operand 2 is always a scalar type.
3855 @cindex @code{ashr@var{m}3} instruction pattern
3856 @cindex @code{lshr@var{m}3} instruction pattern
3857 @cindex @code{rotl@var{m}3} instruction pattern
3858 @cindex @code{rotr@var{m}3} instruction pattern
3859 @item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3}
3860 Other shift and rotate instructions, analogous to the
3861 @code{ashl@var{m}3} instructions. Operand 2 is always a scalar type.
3863 @cindex @code{vashl@var{m}3} instruction pattern
3864 @cindex @code{vashr@var{m}3} instruction pattern
3865 @cindex @code{vlshr@var{m}3} instruction pattern
3866 @cindex @code{vrotl@var{m}3} instruction pattern
3867 @cindex @code{vrotr@var{m}3} instruction pattern
3868 @item @samp{vashl@var{m}3}, @samp{vashr@var{m}3}, @samp{vlshr@var{m}3}, @samp{vrotl@var{m}3}, @samp{vrotr@var{m}3}
3869 Vector shift and rotate instructions that take vectors as operand 2
3870 instead of a scalar type.
3872 @cindex @code{neg@var{m}2} instruction pattern
3873 @cindex @code{ssneg@var{m}2} instruction pattern
3874 @cindex @code{usneg@var{m}2} instruction pattern
3875 @item @samp{neg@var{m}2}, @samp{ssneg@var{m}2}, @samp{usneg@var{m}2}
3876 Negate operand 1 and store the result in operand 0.
3878 @cindex @code{abs@var{m}2} instruction pattern
3879 @item @samp{abs@var{m}2}
3880 Store the absolute value of operand 1 into operand 0.
3882 @cindex @code{sqrt@var{m}2} instruction pattern
3883 @item @samp{sqrt@var{m}2}
3884 Store the square root of operand 1 into operand 0.
3886 The @code{sqrt} built-in function of C always uses the mode which
3887 corresponds to the C data type @code{double} and the @code{sqrtf}
3888 built-in function uses the mode which corresponds to the C data
3891 @cindex @code{fmod@var{m}3} instruction pattern
3892 @item @samp{fmod@var{m}3}
3893 Store the remainder of dividing operand 1 by operand 2 into
3894 operand 0, rounded towards zero to an integer.
3896 The @code{fmod} built-in function of C always uses the mode which
3897 corresponds to the C data type @code{double} and the @code{fmodf}
3898 built-in function uses the mode which corresponds to the C data
3901 @cindex @code{remainder@var{m}3} instruction pattern
3902 @item @samp{remainder@var{m}3}
3903 Store the remainder of dividing operand 1 by operand 2 into
3904 operand 0, rounded to the nearest integer.
3906 The @code{remainder} built-in function of C always uses the mode
3907 which corresponds to the C data type @code{double} and the
3908 @code{remainderf} built-in function uses the mode which corresponds
3909 to the C data type @code{float}.
3911 @cindex @code{cos@var{m}2} instruction pattern
3912 @item @samp{cos@var{m}2}
3913 Store the cosine of operand 1 into operand 0.
3915 The @code{cos} built-in function of C always uses the mode which
3916 corresponds to the C data type @code{double} and the @code{cosf}
3917 built-in function uses the mode which corresponds to the C data
3920 @cindex @code{sin@var{m}2} instruction pattern
3921 @item @samp{sin@var{m}2}
3922 Store the sine of operand 1 into operand 0.
3924 The @code{sin} built-in function of C always uses the mode which
3925 corresponds to the C data type @code{double} and the @code{sinf}
3926 built-in function uses the mode which corresponds to the C data
3929 @cindex @code{exp@var{m}2} instruction pattern
3930 @item @samp{exp@var{m}2}
3931 Store the exponential of operand 1 into operand 0.
3933 The @code{exp} built-in function of C always uses the mode which
3934 corresponds to the C data type @code{double} and the @code{expf}
3935 built-in function uses the mode which corresponds to the C data
3938 @cindex @code{log@var{m}2} instruction pattern
3939 @item @samp{log@var{m}2}
3940 Store the natural logarithm of operand 1 into operand 0.
3942 The @code{log} built-in function of C always uses the mode which
3943 corresponds to the C data type @code{double} and the @code{logf}
3944 built-in function uses the mode which corresponds to the C data
3947 @cindex @code{pow@var{m}3} instruction pattern
3948 @item @samp{pow@var{m}3}
3949 Store the value of operand 1 raised to the exponent operand 2
3952 The @code{pow} built-in function of C always uses the mode which
3953 corresponds to the C data type @code{double} and the @code{powf}
3954 built-in function uses the mode which corresponds to the C data
3957 @cindex @code{atan2@var{m}3} instruction pattern
3958 @item @samp{atan2@var{m}3}
3959 Store the arc tangent (inverse tangent) of operand 1 divided by
3960 operand 2 into operand 0, using the signs of both arguments to
3961 determine the quadrant of the result.
3963 The @code{atan2} built-in function of C always uses the mode which
3964 corresponds to the C data type @code{double} and the @code{atan2f}
3965 built-in function uses the mode which corresponds to the C data
3968 @cindex @code{floor@var{m}2} instruction pattern
3969 @item @samp{floor@var{m}2}
3970 Store the largest integral value not greater than argument.
3972 The @code{floor} built-in function of C always uses the mode which
3973 corresponds to the C data type @code{double} and the @code{floorf}
3974 built-in function uses the mode which corresponds to the C data
3977 @cindex @code{btrunc@var{m}2} instruction pattern
3978 @item @samp{btrunc@var{m}2}
3979 Store the argument rounded to integer towards zero.
3981 The @code{trunc} built-in function of C always uses the mode which
3982 corresponds to the C data type @code{double} and the @code{truncf}
3983 built-in function uses the mode which corresponds to the C data
3986 @cindex @code{round@var{m}2} instruction pattern
3987 @item @samp{round@var{m}2}
3988 Store the argument rounded to integer away from zero.
3990 The @code{round} built-in function of C always uses the mode which
3991 corresponds to the C data type @code{double} and the @code{roundf}
3992 built-in function uses the mode which corresponds to the C data
3995 @cindex @code{ceil@var{m}2} instruction pattern
3996 @item @samp{ceil@var{m}2}
3997 Store the argument rounded to integer away from zero.
3999 The @code{ceil} built-in function of C always uses the mode which
4000 corresponds to the C data type @code{double} and the @code{ceilf}
4001 built-in function uses the mode which corresponds to the C data
4004 @cindex @code{nearbyint@var{m}2} instruction pattern
4005 @item @samp{nearbyint@var{m}2}
4006 Store the argument rounded according to the default rounding mode
4008 The @code{nearbyint} built-in function of C always uses the mode which
4009 corresponds to the C data type @code{double} and the @code{nearbyintf}
4010 built-in function uses the mode which corresponds to the C data
4013 @cindex @code{rint@var{m}2} instruction pattern
4014 @item @samp{rint@var{m}2}
4015 Store the argument rounded according to the default rounding mode and
4016 raise the inexact exception when the result differs in value from
4019 The @code{rint} built-in function of C always uses the mode which
4020 corresponds to the C data type @code{double} and the @code{rintf}
4021 built-in function uses the mode which corresponds to the C data
4024 @cindex @code{lrint@var{m}@var{n}2}
4025 @item @samp{lrint@var{m}@var{n}2}
4026 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4027 point mode @var{n} as a signed number according to the current
4028 rounding mode and store in operand 0 (which has mode @var{n}).
4030 @cindex @code{lround@var{m}@var{n}2}
4031 @item @samp{lround@var{m}2}
4032 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4033 point mode @var{n} as a signed number rounding to nearest and away
4034 from zero and store in operand 0 (which has mode @var{n}).
4036 @cindex @code{lfloor@var{m}@var{n}2}
4037 @item @samp{lfloor@var{m}2}
4038 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4039 point mode @var{n} as a signed number rounding down and store in
4040 operand 0 (which has mode @var{n}).
4042 @cindex @code{lceil@var{m}@var{n}2}
4043 @item @samp{lceil@var{m}2}
4044 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4045 point mode @var{n} as a signed number rounding up and store in
4046 operand 0 (which has mode @var{n}).
4048 @cindex @code{copysign@var{m}3} instruction pattern
4049 @item @samp{copysign@var{m}3}
4050 Store a value with the magnitude of operand 1 and the sign of operand
4053 The @code{copysign} built-in function of C always uses the mode which
4054 corresponds to the C data type @code{double} and the @code{copysignf}
4055 built-in function uses the mode which corresponds to the C data
4058 @cindex @code{ffs@var{m}2} instruction pattern
4059 @item @samp{ffs@var{m}2}
4060 Store into operand 0 one plus the index of the least significant 1-bit
4061 of operand 1. If operand 1 is zero, store zero. @var{m} is the mode
4062 of operand 0; operand 1's mode is specified by the instruction
4063 pattern, and the compiler will convert the operand to that mode before
4064 generating the instruction.
4066 The @code{ffs} built-in function of C always uses the mode which
4067 corresponds to the C data type @code{int}.
4069 @cindex @code{clz@var{m}2} instruction pattern
4070 @item @samp{clz@var{m}2}
4071 Store into operand 0 the number of leading 0-bits in @var{x}, starting
4072 at the most significant bit position. If @var{x} is 0, the
4073 @code{CLZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
4074 the result is undefined or has a useful value.
4075 @var{m} is the mode of operand 0; operand 1's mode is
4076 specified by the instruction pattern, and the compiler will convert the
4077 operand to that mode before generating the instruction.
4079 @cindex @code{ctz@var{m}2} instruction pattern
4080 @item @samp{ctz@var{m}2}
4081 Store into operand 0 the number of trailing 0-bits in @var{x}, starting
4082 at the least significant bit position. If @var{x} is 0, the
4083 @code{CTZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
4084 the result is undefined or has a useful value.
4085 @var{m} is the mode of operand 0; operand 1's mode is
4086 specified by the instruction pattern, and the compiler will convert the
4087 operand to that mode before generating the instruction.
4089 @cindex @code{popcount@var{m}2} instruction pattern
4090 @item @samp{popcount@var{m}2}
4091 Store into operand 0 the number of 1-bits in @var{x}. @var{m} is the
4092 mode of operand 0; operand 1's mode is specified by the instruction
4093 pattern, and the compiler will convert the operand to that mode before
4094 generating the instruction.
4096 @cindex @code{parity@var{m}2} instruction pattern
4097 @item @samp{parity@var{m}2}
4098 Store into operand 0 the parity of @var{x}, i.e.@: the number of 1-bits
4099 in @var{x} modulo 2. @var{m} is the mode of operand 0; operand 1's mode
4100 is specified by the instruction pattern, and the compiler will convert
4101 the operand to that mode before generating the instruction.
4103 @cindex @code{one_cmpl@var{m}2} instruction pattern
4104 @item @samp{one_cmpl@var{m}2}
4105 Store the bitwise-complement of operand 1 into operand 0.
4107 @cindex @code{cmp@var{m}} instruction pattern
4108 @item @samp{cmp@var{m}}
4109 Compare operand 0 and operand 1, and set the condition codes.
4110 The RTL pattern should look like this:
4113 (set (cc0) (compare (match_operand:@var{m} 0 @dots{})
4114 (match_operand:@var{m} 1 @dots{})))
4117 @cindex @code{tst@var{m}} instruction pattern
4118 @item @samp{tst@var{m}}
4119 Compare operand 0 against zero, and set the condition codes.
4120 The RTL pattern should look like this:
4123 (set (cc0) (match_operand:@var{m} 0 @dots{}))
4126 @samp{tst@var{m}} patterns should not be defined for machines that do
4127 not use @code{(cc0)}. Doing so would confuse the optimizer since it
4128 would no longer be clear which @code{set} operations were comparisons.
4129 The @samp{cmp@var{m}} patterns should be used instead.
4131 @cindex @code{movmem@var{m}} instruction pattern
4132 @item @samp{movmem@var{m}}
4133 Block move instruction. The destination and source blocks of memory
4134 are the first two operands, and both are @code{mem:BLK}s with an
4135 address in mode @code{Pmode}.
4137 The number of bytes to move is the third operand, in mode @var{m}.
4138 Usually, you specify @code{word_mode} for @var{m}. However, if you can
4139 generate better code knowing the range of valid lengths is smaller than
4140 those representable in a full word, you should provide a pattern with a
4141 mode corresponding to the range of values you can handle efficiently
4142 (e.g., @code{QImode} for values in the range 0--127; note we avoid numbers
4143 that appear negative) and also a pattern with @code{word_mode}.
4145 The fourth operand is the known shared alignment of the source and
4146 destination, in the form of a @code{const_int} rtx. Thus, if the
4147 compiler knows that both source and destination are word-aligned,
4148 it may provide the value 4 for this operand.
4150 Optional operands 5 and 6 specify expected alignment and size of block
4151 respectively. The expected alignment differs from alignment in operand 4
4152 in a way that the blocks are not required to be aligned according to it in
4153 all cases. Expected size, when unknown, is set to @code{(const_int -1)}.
4155 Descriptions of multiple @code{movmem@var{m}} patterns can only be
4156 beneficial if the patterns for smaller modes have fewer restrictions
4157 on their first, second and fourth operands. Note that the mode @var{m}
4158 in @code{movmem@var{m}} does not impose any restriction on the mode of
4159 individually moved data units in the block.
4161 These patterns need not give special consideration to the possibility
4162 that the source and destination strings might overlap.
4164 @cindex @code{movstr} instruction pattern
4166 String copy instruction, with @code{stpcpy} semantics. Operand 0 is
4167 an output operand in mode @code{Pmode}. The addresses of the
4168 destination and source strings are operands 1 and 2, and both are
4169 @code{mem:BLK}s with addresses in mode @code{Pmode}. The execution of
4170 the expansion of this pattern should store in operand 0 the address in
4171 which the @code{NUL} terminator was stored in the destination string.
4173 @cindex @code{setmem@var{m}} instruction pattern
4174 @item @samp{setmem@var{m}}
4175 Block set instruction. The destination string is the first operand,
4176 given as a @code{mem:BLK} whose address is in mode @code{Pmode}. The
4177 number of bytes to set is the second operand, in mode @var{m}. The value to
4178 initialize the memory with is the third operand. Targets that only support the
4179 clearing of memory should reject any value that is not the constant 0. See
4180 @samp{movmem@var{m}} for a discussion of the choice of mode.
4182 The fourth operand is the known alignment of the destination, in the form
4183 of a @code{const_int} rtx. Thus, if the compiler knows that the
4184 destination is word-aligned, it may provide the value 4 for this
4187 Optional operands 5 and 6 specify expected alignment and size of block
4188 respectively. The expected alignment differs from alignment in operand 4
4189 in a way that the blocks are not required to be aligned according to it in
4190 all cases. Expected size, when unknown, is set to @code{(const_int -1)}.
4192 The use for multiple @code{setmem@var{m}} is as for @code{movmem@var{m}}.
4194 @cindex @code{cmpstrn@var{m}} instruction pattern
4195 @item @samp{cmpstrn@var{m}}
4196 String compare instruction, with five operands. Operand 0 is the output;
4197 it has mode @var{m}. The remaining four operands are like the operands
4198 of @samp{movmem@var{m}}. The two memory blocks specified are compared
4199 byte by byte in lexicographic order starting at the beginning of each
4200 string. The instruction is not allowed to prefetch more than one byte
4201 at a time since either string may end in the first byte and reading past
4202 that may access an invalid page or segment and cause a fault. The
4203 effect of the instruction is to store a value in operand 0 whose sign
4204 indicates the result of the comparison.
4206 @cindex @code{cmpstr@var{m}} instruction pattern
4207 @item @samp{cmpstr@var{m}}
4208 String compare instruction, without known maximum length. Operand 0 is the
4209 output; it has mode @var{m}. The second and third operand are the blocks of
4210 memory to be compared; both are @code{mem:BLK} with an address in mode
4213 The fourth operand is the known shared alignment of the source and
4214 destination, in the form of a @code{const_int} rtx. Thus, if the
4215 compiler knows that both source and destination are word-aligned,
4216 it may provide the value 4 for this operand.
4218 The two memory blocks specified are compared byte by byte in lexicographic
4219 order starting at the beginning of each string. The instruction is not allowed
4220 to prefetch more than one byte at a time since either string may end in the
4221 first byte and reading past that may access an invalid page or segment and
4222 cause a fault. The effect of the instruction is to store a value in operand 0
4223 whose sign indicates the result of the comparison.
4225 @cindex @code{cmpmem@var{m}} instruction pattern
4226 @item @samp{cmpmem@var{m}}
4227 Block compare instruction, with five operands like the operands
4228 of @samp{cmpstr@var{m}}. The two memory blocks specified are compared
4229 byte by byte in lexicographic order starting at the beginning of each
4230 block. Unlike @samp{cmpstr@var{m}} the instruction can prefetch
4231 any bytes in the two memory blocks. The effect of the instruction is
4232 to store a value in operand 0 whose sign indicates the result of the
4235 @cindex @code{strlen@var{m}} instruction pattern
4236 @item @samp{strlen@var{m}}
4237 Compute the length of a string, with three operands.
4238 Operand 0 is the result (of mode @var{m}), operand 1 is
4239 a @code{mem} referring to the first character of the string,
4240 operand 2 is the character to search for (normally zero),
4241 and operand 3 is a constant describing the known alignment
4242 of the beginning of the string.
4244 @cindex @code{float@var{mn}2} instruction pattern
4245 @item @samp{float@var{m}@var{n}2}
4246 Convert signed integer operand 1 (valid for fixed point mode @var{m}) to
4247 floating point mode @var{n} and store in operand 0 (which has mode
4250 @cindex @code{floatuns@var{mn}2} instruction pattern
4251 @item @samp{floatuns@var{m}@var{n}2}
4252 Convert unsigned integer operand 1 (valid for fixed point mode @var{m})
4253 to floating point mode @var{n} and store in operand 0 (which has mode
4256 @cindex @code{fix@var{mn}2} instruction pattern
4257 @item @samp{fix@var{m}@var{n}2}
4258 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4259 point mode @var{n} as a signed number and store in operand 0 (which
4260 has mode @var{n}). This instruction's result is defined only when
4261 the value of operand 1 is an integer.
4263 If the machine description defines this pattern, it also needs to
4264 define the @code{ftrunc} pattern.
4266 @cindex @code{fixuns@var{mn}2} instruction pattern
4267 @item @samp{fixuns@var{m}@var{n}2}
4268 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4269 point mode @var{n} as an unsigned number and store in operand 0 (which
4270 has mode @var{n}). This instruction's result is defined only when the
4271 value of operand 1 is an integer.
4273 @cindex @code{ftrunc@var{m}2} instruction pattern
4274 @item @samp{ftrunc@var{m}2}
4275 Convert operand 1 (valid for floating point mode @var{m}) to an
4276 integer value, still represented in floating point mode @var{m}, and
4277 store it in operand 0 (valid for floating point mode @var{m}).
4279 @cindex @code{fix_trunc@var{mn}2} instruction pattern
4280 @item @samp{fix_trunc@var{m}@var{n}2}
4281 Like @samp{fix@var{m}@var{n}2} but works for any floating point value
4282 of mode @var{m} by converting the value to an integer.
4284 @cindex @code{fixuns_trunc@var{mn}2} instruction pattern
4285 @item @samp{fixuns_trunc@var{m}@var{n}2}
4286 Like @samp{fixuns@var{m}@var{n}2} but works for any floating point
4287 value of mode @var{m} by converting the value to an integer.
4289 @cindex @code{trunc@var{mn}2} instruction pattern
4290 @item @samp{trunc@var{m}@var{n}2}
4291 Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and
4292 store in operand 0 (which has mode @var{n}). Both modes must be fixed
4293 point or both floating point.
4295 @cindex @code{extend@var{mn}2} instruction pattern
4296 @item @samp{extend@var{m}@var{n}2}
4297 Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
4298 store in operand 0 (which has mode @var{n}). Both modes must be fixed
4299 point or both floating point.
4301 @cindex @code{zero_extend@var{mn}2} instruction pattern
4302 @item @samp{zero_extend@var{m}@var{n}2}
4303 Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
4304 store in operand 0 (which has mode @var{n}). Both modes must be fixed
4307 @cindex @code{fract@var{mn}2} instruction pattern
4308 @item @samp{fract@var{m}@var{n}2}
4309 Convert operand 1 of mode @var{m} to mode @var{n} and store in
4310 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
4311 could be fixed-point to fixed-point, signed integer to fixed-point,
4312 fixed-point to signed integer, floating-point to fixed-point,
4313 or fixed-point to floating-point.
4314 When overflows or underflows happen, the results are undefined.
4316 @cindex @code{satfract@var{mn}2} instruction pattern
4317 @item @samp{satfract@var{m}@var{n}2}
4318 Convert operand 1 of mode @var{m} to mode @var{n} and store in
4319 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
4320 could be fixed-point to fixed-point, signed integer to fixed-point,
4321 or floating-point to fixed-point.
4322 When overflows or underflows happen, the instruction saturates the
4323 results to the maximum or the minimum.
4325 @cindex @code{fractuns@var{mn}2} instruction pattern
4326 @item @samp{fractuns@var{m}@var{n}2}
4327 Convert operand 1 of mode @var{m} to mode @var{n} and store in
4328 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
4329 could be unsigned integer to fixed-point, or
4330 fixed-point to unsigned integer.
4331 When overflows or underflows happen, the results are undefined.
4333 @cindex @code{satfractuns@var{mn}2} instruction pattern
4334 @item @samp{satfractuns@var{m}@var{n}2}
4335 Convert unsigned integer operand 1 of mode @var{m} to fixed-point mode
4336 @var{n} and store in operand 0 (which has mode @var{n}).
4337 When overflows or underflows happen, the instruction saturates the
4338 results to the maximum or the minimum.
4340 @cindex @code{extv} instruction pattern
4342 Extract a bit-field from operand 1 (a register or memory operand), where
4343 operand 2 specifies the width in bits and operand 3 the starting bit,
4344 and store it in operand 0. Operand 0 must have mode @code{word_mode}.
4345 Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often
4346 @code{word_mode} is allowed only for registers. Operands 2 and 3 must
4347 be valid for @code{word_mode}.
4349 The RTL generation pass generates this instruction only with constants
4350 for operands 2 and 3 and the constant is never zero for operand 2.
4352 The bit-field value is sign-extended to a full word integer
4353 before it is stored in operand 0.
4355 @cindex @code{extzv} instruction pattern
4357 Like @samp{extv} except that the bit-field value is zero-extended.
4359 @cindex @code{insv} instruction pattern
4361 Store operand 3 (which must be valid for @code{word_mode}) into a
4362 bit-field in operand 0, where operand 1 specifies the width in bits and
4363 operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or
4364 @code{word_mode}; often @code{word_mode} is allowed only for registers.
4365 Operands 1 and 2 must be valid for @code{word_mode}.
4367 The RTL generation pass generates this instruction only with constants
4368 for operands 1 and 2 and the constant is never zero for operand 1.
4370 @cindex @code{mov@var{mode}cc} instruction pattern
4371 @item @samp{mov@var{mode}cc}
4372 Conditionally move operand 2 or operand 3 into operand 0 according to the
4373 comparison in operand 1. If the comparison is true, operand 2 is moved
4374 into operand 0, otherwise operand 3 is moved.
4376 The mode of the operands being compared need not be the same as the operands
4377 being moved. Some machines, sparc64 for example, have instructions that
4378 conditionally move an integer value based on the floating point condition
4379 codes and vice versa.
4381 If the machine does not have conditional move instructions, do not
4382 define these patterns.
4384 @cindex @code{add@var{mode}cc} instruction pattern
4385 @item @samp{add@var{mode}cc}
4386 Similar to @samp{mov@var{mode}cc} but for conditional addition. Conditionally
4387 move operand 2 or (operands 2 + operand 3) into operand 0 according to the
4388 comparison in operand 1. If the comparison is true, operand 2 is moved into
4389 operand 0, otherwise (operand 2 + operand 3) is moved.
4391 @cindex @code{s@var{cond}} instruction pattern
4392 @item @samp{s@var{cond}}
4393 Store zero or nonzero in the operand according to the condition codes.
4394 Value stored is nonzero iff the condition @var{cond} is true.
4395 @var{cond} is the name of a comparison operation expression code, such
4396 as @code{eq}, @code{lt} or @code{leu}.
4398 You specify the mode that the operand must have when you write the
4399 @code{match_operand} expression. The compiler automatically sees
4400 which mode you have used and supplies an operand of that mode.
4402 The value stored for a true condition must have 1 as its low bit, or
4403 else must be negative. Otherwise the instruction is not suitable and
4404 you should omit it from the machine description. You describe to the
4405 compiler exactly which value is stored by defining the macro
4406 @code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be
4407 found that can be used for all the @samp{s@var{cond}} patterns, you
4408 should omit those operations from the machine description.
4410 These operations may fail, but should do so only in relatively
4411 uncommon cases; if they would fail for common cases involving
4412 integer comparisons, it is best to omit these patterns.
4414 If these operations are omitted, the compiler will usually generate code
4415 that copies the constant one to the target and branches around an
4416 assignment of zero to the target. If this code is more efficient than
4417 the potential instructions used for the @samp{s@var{cond}} pattern
4418 followed by those required to convert the result into a 1 or a zero in
4419 @code{SImode}, you should omit the @samp{s@var{cond}} operations from
4420 the machine description.
4422 @cindex @code{b@var{cond}} instruction pattern
4423 @item @samp{b@var{cond}}
4424 Conditional branch instruction. Operand 0 is a @code{label_ref} that
4425 refers to the label to jump to. Jump if the condition codes meet
4426 condition @var{cond}.
4428 Some machines do not follow the model assumed here where a comparison
4429 instruction is followed by a conditional branch instruction. In that
4430 case, the @samp{cmp@var{m}} (and @samp{tst@var{m}}) patterns should
4431 simply store the operands away and generate all the required insns in a
4432 @code{define_expand} (@pxref{Expander Definitions}) for the conditional
4433 branch operations. All calls to expand @samp{b@var{cond}} patterns are
4434 immediately preceded by calls to expand either a @samp{cmp@var{m}}
4435 pattern or a @samp{tst@var{m}} pattern.
4437 Machines that use a pseudo register for the condition code value, or
4438 where the mode used for the comparison depends on the condition being
4439 tested, should also use the above mechanism. @xref{Jump Patterns}.
4441 The above discussion also applies to the @samp{mov@var{mode}cc} and
4442 @samp{s@var{cond}} patterns.
4444 @cindex @code{cbranch@var{mode}4} instruction pattern
4445 @item @samp{cbranch@var{mode}4}
4446 Conditional branch instruction combined with a compare instruction.
4447 Operand 0 is a comparison operator. Operand 1 and operand 2 are the
4448 first and second operands of the comparison, respectively. Operand 3
4449 is a @code{label_ref} that refers to the label to jump to.
4451 @cindex @code{jump} instruction pattern
4453 A jump inside a function; an unconditional branch. Operand 0 is the
4454 @code{label_ref} of the label to jump to. This pattern name is mandatory
4457 @cindex @code{call} instruction pattern
4459 Subroutine call instruction returning no value. Operand 0 is the
4460 function to call; operand 1 is the number of bytes of arguments pushed
4461 as a @code{const_int}; operand 2 is the number of registers used as
4464 On most machines, operand 2 is not actually stored into the RTL
4465 pattern. It is supplied for the sake of some RISC machines which need
4466 to put this information into the assembler code; they can put it in
4467 the RTL instead of operand 1.
4469 Operand 0 should be a @code{mem} RTX whose address is the address of the
4470 function. Note, however, that this address can be a @code{symbol_ref}
4471 expression even if it would not be a legitimate memory address on the
4472 target machine. If it is also not a valid argument for a call
4473 instruction, the pattern for this operation should be a
4474 @code{define_expand} (@pxref{Expander Definitions}) that places the
4475 address into a register and uses that register in the call instruction.
4477 @cindex @code{call_value} instruction pattern
4478 @item @samp{call_value}
4479 Subroutine call instruction returning a value. Operand 0 is the hard
4480 register in which the value is returned. There are three more
4481 operands, the same as the three operands of the @samp{call}
4482 instruction (but with numbers increased by one).
4484 Subroutines that return @code{BLKmode} objects use the @samp{call}
4487 @cindex @code{call_pop} instruction pattern
4488 @cindex @code{call_value_pop} instruction pattern
4489 @item @samp{call_pop}, @samp{call_value_pop}
4490 Similar to @samp{call} and @samp{call_value}, except used if defined and
4491 if @code{RETURN_POPS_ARGS} is nonzero. They should emit a @code{parallel}
4492 that contains both the function call and a @code{set} to indicate the
4493 adjustment made to the frame pointer.
4495 For machines where @code{RETURN_POPS_ARGS} can be nonzero, the use of these
4496 patterns increases the number of functions for which the frame pointer
4497 can be eliminated, if desired.
4499 @cindex @code{untyped_call} instruction pattern
4500 @item @samp{untyped_call}
4501 Subroutine call instruction returning a value of any type. Operand 0 is
4502 the function to call; operand 1 is a memory location where the result of
4503 calling the function is to be stored; operand 2 is a @code{parallel}
4504 expression where each element is a @code{set} expression that indicates
4505 the saving of a function return value into the result block.
4507 This instruction pattern should be defined to support
4508 @code{__builtin_apply} on machines where special instructions are needed
4509 to call a subroutine with arbitrary arguments or to save the value
4510 returned. This instruction pattern is required on machines that have
4511 multiple registers that can hold a return value
4512 (i.e.@: @code{FUNCTION_VALUE_REGNO_P} is true for more than one register).
4514 @cindex @code{return} instruction pattern
4516 Subroutine return instruction. This instruction pattern name should be
4517 defined only if a single instruction can do all the work of returning
4520 Like the @samp{mov@var{m}} patterns, this pattern is also used after the
4521 RTL generation phase. In this case it is to support machines where
4522 multiple instructions are usually needed to return from a function, but
4523 some class of functions only requires one instruction to implement a
4524 return. Normally, the applicable functions are those which do not need
4525 to save any registers or allocate stack space.
4527 @findex reload_completed
4528 @findex leaf_function_p
4529 For such machines, the condition specified in this pattern should only
4530 be true when @code{reload_completed} is nonzero and the function's
4531 epilogue would only be a single instruction. For machines with register
4532 windows, the routine @code{leaf_function_p} may be used to determine if
4533 a register window push is required.
4535 Machines that have conditional return instructions should define patterns
4541 (if_then_else (match_operator
4542 0 "comparison_operator"
4543 [(cc0) (const_int 0)])
4550 where @var{condition} would normally be the same condition specified on the
4551 named @samp{return} pattern.
4553 @cindex @code{untyped_return} instruction pattern
4554 @item @samp{untyped_return}
4555 Untyped subroutine return instruction. This instruction pattern should
4556 be defined to support @code{__builtin_return} on machines where special
4557 instructions are needed to return a value of any type.
4559 Operand 0 is a memory location where the result of calling a function
4560 with @code{__builtin_apply} is stored; operand 1 is a @code{parallel}
4561 expression where each element is a @code{set} expression that indicates
4562 the restoring of a function return value from the result block.
4564 @cindex @code{nop} instruction pattern
4566 No-op instruction. This instruction pattern name should always be defined
4567 to output a no-op in assembler code. @code{(const_int 0)} will do as an
4570 @cindex @code{indirect_jump} instruction pattern
4571 @item @samp{indirect_jump}
4572 An instruction to jump to an address which is operand zero.
4573 This pattern name is mandatory on all machines.
4575 @cindex @code{casesi} instruction pattern
4577 Instruction to jump through a dispatch table, including bounds checking.
4578 This instruction takes five operands:
4582 The index to dispatch on, which has mode @code{SImode}.
4585 The lower bound for indices in the table, an integer constant.
4588 The total range of indices in the table---the largest index
4589 minus the smallest one (both inclusive).
4592 A label that precedes the table itself.
4595 A label to jump to if the index has a value outside the bounds.
4598 The table is a @code{addr_vec} or @code{addr_diff_vec} inside of a
4599 @code{jump_insn}. The number of elements in the table is one plus the
4600 difference between the upper bound and the lower bound.
4602 @cindex @code{tablejump} instruction pattern
4603 @item @samp{tablejump}
4604 Instruction to jump to a variable address. This is a low-level
4605 capability which can be used to implement a dispatch table when there
4606 is no @samp{casesi} pattern.
4608 This pattern requires two operands: the address or offset, and a label
4609 which should immediately precede the jump table. If the macro
4610 @code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first
4611 operand is an offset which counts from the address of the table; otherwise,
4612 it is an absolute address to jump to. In either case, the first operand has
4615 The @samp{tablejump} insn is always the last insn before the jump
4616 table it uses. Its assembler code normally has no need to use the
4617 second operand, but you should incorporate it in the RTL pattern so
4618 that the jump optimizer will not delete the table as unreachable code.
4621 @cindex @code{decrement_and_branch_until_zero} instruction pattern
4622 @item @samp{decrement_and_branch_until_zero}
4623 Conditional branch instruction that decrements a register and
4624 jumps if the register is nonzero. Operand 0 is the register to
4625 decrement and test; operand 1 is the label to jump to if the
4626 register is nonzero. @xref{Looping Patterns}.
4628 This optional instruction pattern is only used by the combiner,
4629 typically for loops reversed by the loop optimizer when strength
4630 reduction is enabled.
4632 @cindex @code{doloop_end} instruction pattern
4633 @item @samp{doloop_end}
4634 Conditional branch instruction that decrements a register and jumps if
4635 the register is nonzero. This instruction takes five operands: Operand
4636 0 is the register to decrement and test; operand 1 is the number of loop
4637 iterations as a @code{const_int} or @code{const0_rtx} if this cannot be
4638 determined until run-time; operand 2 is the actual or estimated maximum
4639 number of iterations as a @code{const_int}; operand 3 is the number of
4640 enclosed loops as a @code{const_int} (an innermost loop has a value of
4641 1); operand 4 is the label to jump to if the register is nonzero.
4642 @xref{Looping Patterns}.
4644 This optional instruction pattern should be defined for machines with
4645 low-overhead looping instructions as the loop optimizer will try to
4646 modify suitable loops to utilize it. If nested low-overhead looping is
4647 not supported, use a @code{define_expand} (@pxref{Expander Definitions})
4648 and make the pattern fail if operand 3 is not @code{const1_rtx}.
4649 Similarly, if the actual or estimated maximum number of iterations is
4650 too large for this instruction, make it fail.
4652 @cindex @code{doloop_begin} instruction pattern
4653 @item @samp{doloop_begin}
4654 Companion instruction to @code{doloop_end} required for machines that
4655 need to perform some initialization, such as loading special registers
4656 used by a low-overhead looping instruction. If initialization insns do
4657 not always need to be emitted, use a @code{define_expand}
4658 (@pxref{Expander Definitions}) and make it fail.
4661 @cindex @code{canonicalize_funcptr_for_compare} instruction pattern
4662 @item @samp{canonicalize_funcptr_for_compare}
4663 Canonicalize the function pointer in operand 1 and store the result
4666 Operand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1
4667 may be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc
4668 and also has mode @code{Pmode}.
4670 Canonicalization of a function pointer usually involves computing
4671 the address of the function which would be called if the function
4672 pointer were used in an indirect call.
4674 Only define this pattern if function pointers on the target machine
4675 can have different values but still call the same function when
4676 used in an indirect call.
4678 @cindex @code{save_stack_block} instruction pattern
4679 @cindex @code{save_stack_function} instruction pattern
4680 @cindex @code{save_stack_nonlocal} instruction pattern
4681 @cindex @code{restore_stack_block} instruction pattern
4682 @cindex @code{restore_stack_function} instruction pattern
4683 @cindex @code{restore_stack_nonlocal} instruction pattern
4684 @item @samp{save_stack_block}
4685 @itemx @samp{save_stack_function}
4686 @itemx @samp{save_stack_nonlocal}
4687 @itemx @samp{restore_stack_block}
4688 @itemx @samp{restore_stack_function}
4689 @itemx @samp{restore_stack_nonlocal}
4690 Most machines save and restore the stack pointer by copying it to or
4691 from an object of mode @code{Pmode}. Do not define these patterns on
4694 Some machines require special handling for stack pointer saves and
4695 restores. On those machines, define the patterns corresponding to the
4696 non-standard cases by using a @code{define_expand} (@pxref{Expander
4697 Definitions}) that produces the required insns. The three types of
4698 saves and restores are:
4702 @samp{save_stack_block} saves the stack pointer at the start of a block
4703 that allocates a variable-sized object, and @samp{restore_stack_block}
4704 restores the stack pointer when the block is exited.
4707 @samp{save_stack_function} and @samp{restore_stack_function} do a
4708 similar job for the outermost block of a function and are used when the
4709 function allocates variable-sized objects or calls @code{alloca}. Only
4710 the epilogue uses the restored stack pointer, allowing a simpler save or
4711 restore sequence on some machines.
4714 @samp{save_stack_nonlocal} is used in functions that contain labels
4715 branched to by nested functions. It saves the stack pointer in such a
4716 way that the inner function can use @samp{restore_stack_nonlocal} to
4717 restore the stack pointer. The compiler generates code to restore the
4718 frame and argument pointer registers, but some machines require saving
4719 and restoring additional data such as register window information or
4720 stack backchains. Place insns in these patterns to save and restore any
4724 When saving the stack pointer, operand 0 is the save area and operand 1
4725 is the stack pointer. The mode used to allocate the save area defaults
4726 to @code{Pmode} but you can override that choice by defining the
4727 @code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must
4728 specify an integral mode, or @code{VOIDmode} if no save area is needed
4729 for a particular type of save (either because no save is needed or
4730 because a machine-specific save area can be used). Operand 0 is the
4731 stack pointer and operand 1 is the save area for restore operations. If
4732 @samp{save_stack_block} is defined, operand 0 must not be
4733 @code{VOIDmode} since these saves can be arbitrarily nested.
4735 A save area is a @code{mem} that is at a constant offset from
4736 @code{virtual_stack_vars_rtx} when the stack pointer is saved for use by
4737 nonlocal gotos and a @code{reg} in the other two cases.
4739 @cindex @code{allocate_stack} instruction pattern
4740 @item @samp{allocate_stack}
4741 Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from
4742 the stack pointer to create space for dynamically allocated data.
4744 Store the resultant pointer to this space into operand 0. If you
4745 are allocating space from the main stack, do this by emitting a
4746 move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0.
4747 If you are allocating the space elsewhere, generate code to copy the
4748 location of the space to operand 0. In the latter case, you must
4749 ensure this space gets freed when the corresponding space on the main
4752 Do not define this pattern if all that must be done is the subtraction.
4753 Some machines require other operations such as stack probes or
4754 maintaining the back chain. Define this pattern to emit those
4755 operations in addition to updating the stack pointer.
4757 @cindex @code{check_stack} instruction pattern
4758 @item @samp{check_stack}
4759 If stack checking cannot be done on your system by probing the stack with
4760 a load or store instruction (@pxref{Stack Checking}), define this pattern
4761 to perform the needed check and signaling an error if the stack
4762 has overflowed. The single operand is the location in the stack furthest
4763 from the current stack pointer that you need to validate. Normally,
4764 on machines where this pattern is needed, you would obtain the stack
4765 limit from a global or thread-specific variable or register.
4767 @cindex @code{nonlocal_goto} instruction pattern
4768 @item @samp{nonlocal_goto}
4769 Emit code to generate a non-local goto, e.g., a jump from one function
4770 to a label in an outer function. This pattern has four arguments,
4771 each representing a value to be used in the jump. The first
4772 argument is to be loaded into the frame pointer, the second is
4773 the address to branch to (code to dispatch to the actual label),
4774 the third is the address of a location where the stack is saved,
4775 and the last is the address of the label, to be placed in the
4776 location for the incoming static chain.
4778 On most machines you need not define this pattern, since GCC will
4779 already generate the correct code, which is to load the frame pointer
4780 and static chain, restore the stack (using the
4781 @samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly
4782 to the dispatcher. You need only define this pattern if this code will
4783 not work on your machine.
4785 @cindex @code{nonlocal_goto_receiver} instruction pattern
4786 @item @samp{nonlocal_goto_receiver}
4787 This pattern, if defined, contains code needed at the target of a
4788 nonlocal goto after the code already generated by GCC@. You will not
4789 normally need to define this pattern. A typical reason why you might
4790 need this pattern is if some value, such as a pointer to a global table,
4791 must be restored when the frame pointer is restored. Note that a nonlocal
4792 goto only occurs within a unit-of-translation, so a global table pointer
4793 that is shared by all functions of a given module need not be restored.
4794 There are no arguments.
4796 @cindex @code{exception_receiver} instruction pattern
4797 @item @samp{exception_receiver}
4798 This pattern, if defined, contains code needed at the site of an
4799 exception handler that isn't needed at the site of a nonlocal goto. You
4800 will not normally need to define this pattern. A typical reason why you
4801 might need this pattern is if some value, such as a pointer to a global
4802 table, must be restored after control flow is branched to the handler of
4803 an exception. There are no arguments.
4805 @cindex @code{builtin_setjmp_setup} instruction pattern
4806 @item @samp{builtin_setjmp_setup}
4807 This pattern, if defined, contains additional code needed to initialize
4808 the @code{jmp_buf}. You will not normally need to define this pattern.
4809 A typical reason why you might need this pattern is if some value, such
4810 as a pointer to a global table, must be restored. Though it is
4811 preferred that the pointer value be recalculated if possible (given the
4812 address of a label for instance). The single argument is a pointer to
4813 the @code{jmp_buf}. Note that the buffer is five words long and that
4814 the first three are normally used by the generic mechanism.
4816 @cindex @code{builtin_setjmp_receiver} instruction pattern
4817 @item @samp{builtin_setjmp_receiver}
4818 This pattern, if defined, contains code needed at the site of an
4819 built-in setjmp that isn't needed at the site of a nonlocal goto. You
4820 will not normally need to define this pattern. A typical reason why you
4821 might need this pattern is if some value, such as a pointer to a global
4822 table, must be restored. It takes one argument, which is the label
4823 to which builtin_longjmp transfered control; this pattern may be emitted
4824 at a small offset from that label.
4826 @cindex @code{builtin_longjmp} instruction pattern
4827 @item @samp{builtin_longjmp}
4828 This pattern, if defined, performs the entire action of the longjmp.
4829 You will not normally need to define this pattern unless you also define
4830 @code{builtin_setjmp_setup}. The single argument is a pointer to the
4833 @cindex @code{eh_return} instruction pattern
4834 @item @samp{eh_return}
4835 This pattern, if defined, affects the way @code{__builtin_eh_return},
4836 and thence the call frame exception handling library routines, are
4837 built. It is intended to handle non-trivial actions needed along
4838 the abnormal return path.
4840 The address of the exception handler to which the function should return
4841 is passed as operand to this pattern. It will normally need to copied by
4842 the pattern to some special register or memory location.
4843 If the pattern needs to determine the location of the target call
4844 frame in order to do so, it may use @code{EH_RETURN_STACKADJ_RTX},
4845 if defined; it will have already been assigned.
4847 If this pattern is not defined, the default action will be to simply
4848 copy the return address to @code{EH_RETURN_HANDLER_RTX}. Either
4849 that macro or this pattern needs to be defined if call frame exception
4850 handling is to be used.
4852 @cindex @code{prologue} instruction pattern
4853 @anchor{prologue instruction pattern}
4854 @item @samp{prologue}
4855 This pattern, if defined, emits RTL for entry to a function. The function
4856 entry is responsible for setting up the stack frame, initializing the frame
4857 pointer register, saving callee saved registers, etc.
4859 Using a prologue pattern is generally preferred over defining
4860 @code{TARGET_ASM_FUNCTION_PROLOGUE} to emit assembly code for the prologue.
4862 The @code{prologue} pattern is particularly useful for targets which perform
4863 instruction scheduling.
4865 @cindex @code{epilogue} instruction pattern
4866 @anchor{epilogue instruction pattern}
4867 @item @samp{epilogue}
4868 This pattern emits RTL for exit from a function. The function
4869 exit is responsible for deallocating the stack frame, restoring callee saved
4870 registers and emitting the return instruction.
4872 Using an epilogue pattern is generally preferred over defining
4873 @code{TARGET_ASM_FUNCTION_EPILOGUE} to emit assembly code for the epilogue.
4875 The @code{epilogue} pattern is particularly useful for targets which perform
4876 instruction scheduling or which have delay slots for their return instruction.
4878 @cindex @code{sibcall_epilogue} instruction pattern
4879 @item @samp{sibcall_epilogue}
4880 This pattern, if defined, emits RTL for exit from a function without the final
4881 branch back to the calling function. This pattern will be emitted before any
4882 sibling call (aka tail call) sites.
4884 The @code{sibcall_epilogue} pattern must not clobber any arguments used for
4885 parameter passing or any stack slots for arguments passed to the current
4888 @cindex @code{trap} instruction pattern
4890 This pattern, if defined, signals an error, typically by causing some
4891 kind of signal to be raised. Among other places, it is used by the Java
4892 front end to signal `invalid array index' exceptions.
4894 @cindex @code{conditional_trap} instruction pattern
4895 @item @samp{conditional_trap}
4896 Conditional trap instruction. Operand 0 is a piece of RTL which
4897 performs a comparison. Operand 1 is the trap code, an integer.
4899 A typical @code{conditional_trap} pattern looks like
4902 (define_insn "conditional_trap"
4903 [(trap_if (match_operator 0 "trap_operator"
4904 [(cc0) (const_int 0)])
4905 (match_operand 1 "const_int_operand" "i"))]
4910 @cindex @code{prefetch} instruction pattern
4911 @item @samp{prefetch}
4913 This pattern, if defined, emits code for a non-faulting data prefetch
4914 instruction. Operand 0 is the address of the memory to prefetch. Operand 1
4915 is a constant 1 if the prefetch is preparing for a write to the memory
4916 address, or a constant 0 otherwise. Operand 2 is the expected degree of
4917 temporal locality of the data and is a value between 0 and 3, inclusive; 0
4918 means that the data has no temporal locality, so it need not be left in the
4919 cache after the access; 3 means that the data has a high degree of temporal
4920 locality and should be left in all levels of cache possible; 1 and 2 mean,
4921 respectively, a low or moderate degree of temporal locality.
4923 Targets that do not support write prefetches or locality hints can ignore
4924 the values of operands 1 and 2.
4926 @cindex @code{blockage} instruction pattern
4927 @item @samp{blockage}
4929 This pattern defines a pseudo insn that prevents the instruction
4930 scheduler from moving instructions across the boundary defined by the
4931 blockage insn. Normally an UNSPEC_VOLATILE pattern.
4933 @cindex @code{memory_barrier} instruction pattern
4934 @item @samp{memory_barrier}
4936 If the target memory model is not fully synchronous, then this pattern
4937 should be defined to an instruction that orders both loads and stores
4938 before the instruction with respect to loads and stores after the instruction.
4939 This pattern has no operands.
4941 @cindex @code{sync_compare_and_swap@var{mode}} instruction pattern
4942 @item @samp{sync_compare_and_swap@var{mode}}
4944 This pattern, if defined, emits code for an atomic compare-and-swap
4945 operation. Operand 1 is the memory on which the atomic operation is
4946 performed. Operand 2 is the ``old'' value to be compared against the
4947 current contents of the memory location. Operand 3 is the ``new'' value
4948 to store in the memory if the compare succeeds. Operand 0 is the result
4949 of the operation; it should contain the contents of the memory
4950 before the operation. If the compare succeeds, this should obviously be
4951 a copy of operand 2.
4953 This pattern must show that both operand 0 and operand 1 are modified.
4955 This pattern must issue any memory barrier instructions such that all
4956 memory operations before the atomic operation occur before the atomic
4957 operation and all memory operations after the atomic operation occur
4958 after the atomic operation.
4960 @cindex @code{sync_compare_and_swap_cc@var{mode}} instruction pattern
4961 @item @samp{sync_compare_and_swap_cc@var{mode}}
4963 This pattern is just like @code{sync_compare_and_swap@var{mode}}, except
4964 it should act as if compare part of the compare-and-swap were issued via
4965 @code{cmp@var{m}}. This comparison will only be used with @code{EQ} and
4966 @code{NE} branches and @code{setcc} operations.
4968 Some targets do expose the success or failure of the compare-and-swap
4969 operation via the status flags. Ideally we wouldn't need a separate
4970 named pattern in order to take advantage of this, but the combine pass
4971 does not handle patterns with multiple sets, which is required by
4972 definition for @code{sync_compare_and_swap@var{mode}}.
4974 @cindex @code{sync_add@var{mode}} instruction pattern
4975 @cindex @code{sync_sub@var{mode}} instruction pattern
4976 @cindex @code{sync_ior@var{mode}} instruction pattern
4977 @cindex @code{sync_and@var{mode}} instruction pattern
4978 @cindex @code{sync_xor@var{mode}} instruction pattern
4979 @cindex @code{sync_nand@var{mode}} instruction pattern
4980 @item @samp{sync_add@var{mode}}, @samp{sync_sub@var{mode}}
4981 @itemx @samp{sync_ior@var{mode}}, @samp{sync_and@var{mode}}
4982 @itemx @samp{sync_xor@var{mode}}, @samp{sync_nand@var{mode}}
4984 These patterns emit code for an atomic operation on memory.
4985 Operand 0 is the memory on which the atomic operation is performed.
4986 Operand 1 is the second operand to the binary operator.
4988 The ``nand'' operation is @code{~op0 & op1}.
4990 This pattern must issue any memory barrier instructions such that all
4991 memory operations before the atomic operation occur before the atomic
4992 operation and all memory operations after the atomic operation occur
4993 after the atomic operation.
4995 If these patterns are not defined, the operation will be constructed
4996 from a compare-and-swap operation, if defined.
4998 @cindex @code{sync_old_add@var{mode}} instruction pattern
4999 @cindex @code{sync_old_sub@var{mode}} instruction pattern
5000 @cindex @code{sync_old_ior@var{mode}} instruction pattern
5001 @cindex @code{sync_old_and@var{mode}} instruction pattern
5002 @cindex @code{sync_old_xor@var{mode}} instruction pattern
5003 @cindex @code{sync_old_nand@var{mode}} instruction pattern
5004 @item @samp{sync_old_add@var{mode}}, @samp{sync_old_sub@var{mode}}
5005 @itemx @samp{sync_old_ior@var{mode}}, @samp{sync_old_and@var{mode}}
5006 @itemx @samp{sync_old_xor@var{mode}}, @samp{sync_old_nand@var{mode}}
5008 These patterns are emit code for an atomic operation on memory,
5009 and return the value that the memory contained before the operation.
5010 Operand 0 is the result value, operand 1 is the memory on which the
5011 atomic operation is performed, and operand 2 is the second operand
5012 to the binary operator.
5014 This pattern must issue any memory barrier instructions such that all
5015 memory operations before the atomic operation occur before the atomic
5016 operation and all memory operations after the atomic operation occur
5017 after the atomic operation.
5019 If these patterns are not defined, the operation will be constructed
5020 from a compare-and-swap operation, if defined.
5022 @cindex @code{sync_new_add@var{mode}} instruction pattern
5023 @cindex @code{sync_new_sub@var{mode}} instruction pattern
5024 @cindex @code{sync_new_ior@var{mode}} instruction pattern
5025 @cindex @code{sync_new_and@var{mode}} instruction pattern
5026 @cindex @code{sync_new_xor@var{mode}} instruction pattern
5027 @cindex @code{sync_new_nand@var{mode}} instruction pattern
5028 @item @samp{sync_new_add@var{mode}}, @samp{sync_new_sub@var{mode}}
5029 @itemx @samp{sync_new_ior@var{mode}}, @samp{sync_new_and@var{mode}}
5030 @itemx @samp{sync_new_xor@var{mode}}, @samp{sync_new_nand@var{mode}}
5032 These patterns are like their @code{sync_old_@var{op}} counterparts,
5033 except that they return the value that exists in the memory location
5034 after the operation, rather than before the operation.
5036 @cindex @code{sync_lock_test_and_set@var{mode}} instruction pattern
5037 @item @samp{sync_lock_test_and_set@var{mode}}
5039 This pattern takes two forms, based on the capabilities of the target.
5040 In either case, operand 0 is the result of the operand, operand 1 is
5041 the memory on which the atomic operation is performed, and operand 2
5042 is the value to set in the lock.
5044 In the ideal case, this operation is an atomic exchange operation, in
5045 which the previous value in memory operand is copied into the result
5046 operand, and the value operand is stored in the memory operand.
5048 For less capable targets, any value operand that is not the constant 1
5049 should be rejected with @code{FAIL}. In this case the target may use
5050 an atomic test-and-set bit operation. The result operand should contain
5051 1 if the bit was previously set and 0 if the bit was previously clear.
5052 The true contents of the memory operand are implementation defined.
5054 This pattern must issue any memory barrier instructions such that the
5055 pattern as a whole acts as an acquire barrier, that is all memory
5056 operations after the pattern do not occur until the lock is acquired.
5058 If this pattern is not defined, the operation will be constructed from
5059 a compare-and-swap operation, if defined.
5061 @cindex @code{sync_lock_release@var{mode}} instruction pattern
5062 @item @samp{sync_lock_release@var{mode}}
5064 This pattern, if defined, releases a lock set by
5065 @code{sync_lock_test_and_set@var{mode}}. Operand 0 is the memory
5066 that contains the lock; operand 1 is the value to store in the lock.
5068 If the target doesn't implement full semantics for
5069 @code{sync_lock_test_and_set@var{mode}}, any value operand which is not
5070 the constant 0 should be rejected with @code{FAIL}, and the true contents
5071 of the memory operand are implementation defined.
5073 This pattern must issue any memory barrier instructions such that the
5074 pattern as a whole acts as a release barrier, that is the lock is
5075 released only after all previous memory operations have completed.
5077 If this pattern is not defined, then a @code{memory_barrier} pattern
5078 will be emitted, followed by a store of the value to the memory operand.
5080 @cindex @code{stack_protect_set} instruction pattern
5081 @item @samp{stack_protect_set}
5083 This pattern, if defined, moves a @code{Pmode} value from the memory
5084 in operand 1 to the memory in operand 0 without leaving the value in
5085 a register afterward. This is to avoid leaking the value some place
5086 that an attacker might use to rewrite the stack guard slot after
5087 having clobbered it.
5089 If this pattern is not defined, then a plain move pattern is generated.
5091 @cindex @code{stack_protect_test} instruction pattern
5092 @item @samp{stack_protect_test}
5094 This pattern, if defined, compares a @code{Pmode} value from the
5095 memory in operand 1 with the memory in operand 0 without leaving the
5096 value in a register afterward and branches to operand 2 if the values
5099 If this pattern is not defined, then a plain compare pattern and
5100 conditional branch pattern is used.
5102 @cindex @code{clear_cache} instruction pattern
5103 @item @samp{clear_cache}
5105 This pattern, if defined, flushes the instruction cache for a region of
5106 memory. The region is bounded to by the Pmode pointers in operand 0
5107 inclusive and operand 1 exclusive.
5109 If this pattern is not defined, a call to the library function
5110 @code{__clear_cache} is used.
5115 @c Each of the following nodes are wrapped in separate
5116 @c "@ifset INTERNALS" to work around memory limits for the default
5117 @c configuration in older tetex distributions. Known to not work:
5118 @c tetex-1.0.7, known to work: tetex-2.0.2.
5120 @node Pattern Ordering
5121 @section When the Order of Patterns Matters
5122 @cindex Pattern Ordering
5123 @cindex Ordering of Patterns
5125 Sometimes an insn can match more than one instruction pattern. Then the
5126 pattern that appears first in the machine description is the one used.
5127 Therefore, more specific patterns (patterns that will match fewer things)
5128 and faster instructions (those that will produce better code when they
5129 do match) should usually go first in the description.
5131 In some cases the effect of ordering the patterns can be used to hide
5132 a pattern when it is not valid. For example, the 68000 has an
5133 instruction for converting a fullword to floating point and another
5134 for converting a byte to floating point. An instruction converting
5135 an integer to floating point could match either one. We put the
5136 pattern to convert the fullword first to make sure that one will
5137 be used rather than the other. (Otherwise a large integer might
5138 be generated as a single-byte immediate quantity, which would not work.)
5139 Instead of using this pattern ordering it would be possible to make the
5140 pattern for convert-a-byte smart enough to deal properly with any
5145 @node Dependent Patterns
5146 @section Interdependence of Patterns
5147 @cindex Dependent Patterns
5148 @cindex Interdependence of Patterns
5150 Every machine description must have a named pattern for each of the
5151 conditional branch names @samp{b@var{cond}}. The recognition template
5152 must always have the form
5156 (if_then_else (@var{cond} (cc0) (const_int 0))
5157 (label_ref (match_operand 0 "" ""))
5162 In addition, every machine description must have an anonymous pattern
5163 for each of the possible reverse-conditional branches. Their templates
5168 (if_then_else (@var{cond} (cc0) (const_int 0))
5170 (label_ref (match_operand 0 "" ""))))
5174 They are necessary because jump optimization can turn direct-conditional
5175 branches into reverse-conditional branches.
5177 It is often convenient to use the @code{match_operator} construct to
5178 reduce the number of patterns that must be specified for branches. For
5184 (if_then_else (match_operator 0 "comparison_operator"
5185 [(cc0) (const_int 0)])
5187 (label_ref (match_operand 1 "" ""))))]
5192 In some cases machines support instructions identical except for the
5193 machine mode of one or more operands. For example, there may be
5194 ``sign-extend halfword'' and ``sign-extend byte'' instructions whose
5198 (set (match_operand:SI 0 @dots{})
5199 (extend:SI (match_operand:HI 1 @dots{})))
5201 (set (match_operand:SI 0 @dots{})
5202 (extend:SI (match_operand:QI 1 @dots{})))
5206 Constant integers do not specify a machine mode, so an instruction to
5207 extend a constant value could match either pattern. The pattern it
5208 actually will match is the one that appears first in the file. For correct
5209 results, this must be the one for the widest possible mode (@code{HImode},
5210 here). If the pattern matches the @code{QImode} instruction, the results
5211 will be incorrect if the constant value does not actually fit that mode.
5213 Such instructions to extend constants are rarely generated because they are
5214 optimized away, but they do occasionally happen in nonoptimized
5217 If a constraint in a pattern allows a constant, the reload pass may
5218 replace a register with a constant permitted by the constraint in some
5219 cases. Similarly for memory references. Because of this substitution,
5220 you should not provide separate patterns for increment and decrement
5221 instructions. Instead, they should be generated from the same pattern
5222 that supports register-register add insns by examining the operands and
5223 generating the appropriate machine instruction.
5228 @section Defining Jump Instruction Patterns
5229 @cindex jump instruction patterns
5230 @cindex defining jump instruction patterns
5232 For most machines, GCC assumes that the machine has a condition code.
5233 A comparison insn sets the condition code, recording the results of both
5234 signed and unsigned comparison of the given operands. A separate branch
5235 insn tests the condition code and branches or not according its value.
5236 The branch insns come in distinct signed and unsigned flavors. Many
5237 common machines, such as the VAX, the 68000 and the 32000, work this
5240 Some machines have distinct signed and unsigned compare instructions, and
5241 only one set of conditional branch instructions. The easiest way to handle
5242 these machines is to treat them just like the others until the final stage
5243 where assembly code is written. At this time, when outputting code for the
5244 compare instruction, peek ahead at the following branch using
5245 @code{next_cc0_user (insn)}. (The variable @code{insn} refers to the insn
5246 being output, in the output-writing code in an instruction pattern.) If
5247 the RTL says that is an unsigned branch, output an unsigned compare;
5248 otherwise output a signed compare. When the branch itself is output, you
5249 can treat signed and unsigned branches identically.
5251 The reason you can do this is that GCC always generates a pair of
5252 consecutive RTL insns, possibly separated by @code{note} insns, one to
5253 set the condition code and one to test it, and keeps the pair inviolate
5256 To go with this technique, you must define the machine-description macro
5257 @code{NOTICE_UPDATE_CC} to do @code{CC_STATUS_INIT}; in other words, no
5258 compare instruction is superfluous.
5260 Some machines have compare-and-branch instructions and no condition code.
5261 A similar technique works for them. When it is time to ``output'' a
5262 compare instruction, record its operands in two static variables. When
5263 outputting the branch-on-condition-code instruction that follows, actually
5264 output a compare-and-branch instruction that uses the remembered operands.
5266 It also works to define patterns for compare-and-branch instructions.
5267 In optimizing compilation, the pair of compare and branch instructions
5268 will be combined according to these patterns. But this does not happen
5269 if optimization is not requested. So you must use one of the solutions
5270 above in addition to any special patterns you define.
5272 In many RISC machines, most instructions do not affect the condition
5273 code and there may not even be a separate condition code register. On
5274 these machines, the restriction that the definition and use of the
5275 condition code be adjacent insns is not necessary and can prevent
5276 important optimizations. For example, on the IBM RS/6000, there is a
5277 delay for taken branches unless the condition code register is set three
5278 instructions earlier than the conditional branch. The instruction
5279 scheduler cannot perform this optimization if it is not permitted to
5280 separate the definition and use of the condition code register.
5282 On these machines, do not use @code{(cc0)}, but instead use a register
5283 to represent the condition code. If there is a specific condition code
5284 register in the machine, use a hard register. If the condition code or
5285 comparison result can be placed in any general register, or if there are
5286 multiple condition registers, use a pseudo register.
5288 @findex prev_cc0_setter
5289 @findex next_cc0_user
5290 On some machines, the type of branch instruction generated may depend on
5291 the way the condition code was produced; for example, on the 68k and
5292 SPARC, setting the condition code directly from an add or subtract
5293 instruction does not clear the overflow bit the way that a test
5294 instruction does, so a different branch instruction must be used for
5295 some conditional branches. For machines that use @code{(cc0)}, the set
5296 and use of the condition code must be adjacent (separated only by
5297 @code{note} insns) allowing flags in @code{cc_status} to be used.
5298 (@xref{Condition Code}.) Also, the comparison and branch insns can be
5299 located from each other by using the functions @code{prev_cc0_setter}
5300 and @code{next_cc0_user}.
5302 However, this is not true on machines that do not use @code{(cc0)}. On
5303 those machines, no assumptions can be made about the adjacency of the
5304 compare and branch insns and the above methods cannot be used. Instead,
5305 we use the machine mode of the condition code register to record
5306 different formats of the condition code register.
5308 Registers used to store the condition code value should have a mode that
5309 is in class @code{MODE_CC}. Normally, it will be @code{CCmode}. If
5310 additional modes are required (as for the add example mentioned above in
5311 the SPARC), define them in @file{@var{machine}-modes.def}
5312 (@pxref{Condition Code}). Also define @code{SELECT_CC_MODE} to choose
5313 a mode given an operand of a compare.
5315 If it is known during RTL generation that a different mode will be
5316 required (for example, if the machine has separate compare instructions
5317 for signed and unsigned quantities, like most IBM processors), they can
5318 be specified at that time.
5320 If the cases that require different modes would be made by instruction
5321 combination, the macro @code{SELECT_CC_MODE} determines which machine
5322 mode should be used for the comparison result. The patterns should be
5323 written using that mode. To support the case of the add on the SPARC
5324 discussed above, we have the pattern
5328 [(set (reg:CC_NOOV 0)
5330 (plus:SI (match_operand:SI 0 "register_operand" "%r")
5331 (match_operand:SI 1 "arith_operand" "rI"))
5337 The @code{SELECT_CC_MODE} macro on the SPARC returns @code{CC_NOOVmode}
5338 for comparisons whose argument is a @code{plus}.
5342 @node Looping Patterns
5343 @section Defining Looping Instruction Patterns
5344 @cindex looping instruction patterns
5345 @cindex defining looping instruction patterns
5347 Some machines have special jump instructions that can be utilized to
5348 make loops more efficient. A common example is the 68000 @samp{dbra}
5349 instruction which performs a decrement of a register and a branch if the
5350 result was greater than zero. Other machines, in particular digital
5351 signal processors (DSPs), have special block repeat instructions to
5352 provide low-overhead loop support. For example, the TI TMS320C3x/C4x
5353 DSPs have a block repeat instruction that loads special registers to
5354 mark the top and end of a loop and to count the number of loop
5355 iterations. This avoids the need for fetching and executing a
5356 @samp{dbra}-like instruction and avoids pipeline stalls associated with
5359 GCC has three special named patterns to support low overhead looping.
5360 They are @samp{decrement_and_branch_until_zero}, @samp{doloop_begin},
5361 and @samp{doloop_end}. The first pattern,
5362 @samp{decrement_and_branch_until_zero}, is not emitted during RTL
5363 generation but may be emitted during the instruction combination phase.
5364 This requires the assistance of the loop optimizer, using information
5365 collected during strength reduction, to reverse a loop to count down to
5366 zero. Some targets also require the loop optimizer to add a
5367 @code{REG_NONNEG} note to indicate that the iteration count is always
5368 positive. This is needed if the target performs a signed loop
5369 termination test. For example, the 68000 uses a pattern similar to the
5370 following for its @code{dbra} instruction:
5374 (define_insn "decrement_and_branch_until_zero"
5377 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
5380 (label_ref (match_operand 1 "" ""))
5383 (plus:SI (match_dup 0)
5385 "find_reg_note (insn, REG_NONNEG, 0)"
5390 Note that since the insn is both a jump insn and has an output, it must
5391 deal with its own reloads, hence the `m' constraints. Also note that
5392 since this insn is generated by the instruction combination phase
5393 combining two sequential insns together into an implicit parallel insn,
5394 the iteration counter needs to be biased by the same amount as the
5395 decrement operation, in this case @minus{}1. Note that the following similar
5396 pattern will not be matched by the combiner.
5400 (define_insn "decrement_and_branch_until_zero"
5403 (ge (match_operand:SI 0 "general_operand" "+d*am")
5405 (label_ref (match_operand 1 "" ""))
5408 (plus:SI (match_dup 0)
5410 "find_reg_note (insn, REG_NONNEG, 0)"
5415 The other two special looping patterns, @samp{doloop_begin} and
5416 @samp{doloop_end}, are emitted by the loop optimizer for certain
5417 well-behaved loops with a finite number of loop iterations using
5418 information collected during strength reduction.
5420 The @samp{doloop_end} pattern describes the actual looping instruction
5421 (or the implicit looping operation) and the @samp{doloop_begin} pattern
5422 is an optional companion pattern that can be used for initialization
5423 needed for some low-overhead looping instructions.
5425 Note that some machines require the actual looping instruction to be
5426 emitted at the top of the loop (e.g., the TMS320C3x/C4x DSPs). Emitting
5427 the true RTL for a looping instruction at the top of the loop can cause
5428 problems with flow analysis. So instead, a dummy @code{doloop} insn is
5429 emitted at the end of the loop. The machine dependent reorg pass checks
5430 for the presence of this @code{doloop} insn and then searches back to
5431 the top of the loop, where it inserts the true looping insn (provided
5432 there are no instructions in the loop which would cause problems). Any
5433 additional labels can be emitted at this point. In addition, if the
5434 desired special iteration counter register was not allocated, this
5435 machine dependent reorg pass could emit a traditional compare and jump
5438 The essential difference between the
5439 @samp{decrement_and_branch_until_zero} and the @samp{doloop_end}
5440 patterns is that the loop optimizer allocates an additional pseudo
5441 register for the latter as an iteration counter. This pseudo register
5442 cannot be used within the loop (i.e., general induction variables cannot
5443 be derived from it), however, in many cases the loop induction variable
5444 may become redundant and removed by the flow pass.
5449 @node Insn Canonicalizations
5450 @section Canonicalization of Instructions
5451 @cindex canonicalization of instructions
5452 @cindex insn canonicalization
5454 There are often cases where multiple RTL expressions could represent an
5455 operation performed by a single machine instruction. This situation is
5456 most commonly encountered with logical, branch, and multiply-accumulate
5457 instructions. In such cases, the compiler attempts to convert these
5458 multiple RTL expressions into a single canonical form to reduce the
5459 number of insn patterns required.
5461 In addition to algebraic simplifications, following canonicalizations
5466 For commutative and comparison operators, a constant is always made the
5467 second operand. If a machine only supports a constant as the second
5468 operand, only patterns that match a constant in the second operand need
5472 For associative operators, a sequence of operators will always chain
5473 to the left; for instance, only the left operand of an integer @code{plus}
5474 can itself be a @code{plus}. @code{and}, @code{ior}, @code{xor},
5475 @code{plus}, @code{mult}, @code{smin}, @code{smax}, @code{umin}, and
5476 @code{umax} are associative when applied to integers, and sometimes to
5480 @cindex @code{neg}, canonicalization of
5481 @cindex @code{not}, canonicalization of
5482 @cindex @code{mult}, canonicalization of
5483 @cindex @code{plus}, canonicalization of
5484 @cindex @code{minus}, canonicalization of
5485 For these operators, if only one operand is a @code{neg}, @code{not},
5486 @code{mult}, @code{plus}, or @code{minus} expression, it will be the
5490 In combinations of @code{neg}, @code{mult}, @code{plus}, and
5491 @code{minus}, the @code{neg} operations (if any) will be moved inside
5492 the operations as far as possible. For instance,
5493 @code{(neg (mult A B))} is canonicalized as @code{(mult (neg A) B)}, but
5494 @code{(plus (mult (neg A) B) C)} is canonicalized as
5495 @code{(minus A (mult B C))}.
5497 @cindex @code{compare}, canonicalization of
5499 For the @code{compare} operator, a constant is always the second operand
5500 on machines where @code{cc0} is used (@pxref{Jump Patterns}). On other
5501 machines, there are rare cases where the compiler might want to construct
5502 a @code{compare} with a constant as the first operand. However, these
5503 cases are not common enough for it to be worthwhile to provide a pattern
5504 matching a constant as the first operand unless the machine actually has
5505 such an instruction.
5507 An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or
5508 @code{minus} is made the first operand under the same conditions as
5512 @code{(ltu (plus @var{a} @var{b}) @var{b})} is converted to
5513 @code{(ltu (plus @var{a} @var{b}) @var{a})}. Likewise with @code{geu} instead
5517 @code{(minus @var{x} (const_int @var{n}))} is converted to
5518 @code{(plus @var{x} (const_int @var{-n}))}.
5521 Within address computations (i.e., inside @code{mem}), a left shift is
5522 converted into the appropriate multiplication by a power of two.
5524 @cindex @code{ior}, canonicalization of
5525 @cindex @code{and}, canonicalization of
5526 @cindex De Morgan's law
5528 De Morgan's Law is used to move bitwise negation inside a bitwise
5529 logical-and or logical-or operation. If this results in only one
5530 operand being a @code{not} expression, it will be the first one.
5532 A machine that has an instruction that performs a bitwise logical-and of one
5533 operand with the bitwise negation of the other should specify the pattern
5534 for that instruction as
5538 [(set (match_operand:@var{m} 0 @dots{})
5539 (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
5540 (match_operand:@var{m} 2 @dots{})))]
5546 Similarly, a pattern for a ``NAND'' instruction should be written
5550 [(set (match_operand:@var{m} 0 @dots{})
5551 (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
5552 (not:@var{m} (match_operand:@var{m} 2 @dots{}))))]
5557 In both cases, it is not necessary to include patterns for the many
5558 logically equivalent RTL expressions.
5560 @cindex @code{xor}, canonicalization of
5562 The only possible RTL expressions involving both bitwise exclusive-or
5563 and bitwise negation are @code{(xor:@var{m} @var{x} @var{y})}
5564 and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}.
5567 The sum of three items, one of which is a constant, will only appear in
5571 (plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant})
5575 On machines that do not use @code{cc0},
5576 @code{(compare @var{x} (const_int 0))} will be converted to
5579 @cindex @code{zero_extract}, canonicalization of
5580 @cindex @code{sign_extract}, canonicalization of
5582 Equality comparisons of a group of bits (usually a single bit) with zero
5583 will be written using @code{zero_extract} rather than the equivalent
5584 @code{and} or @code{sign_extract} operations.
5588 Further canonicalization rules are defined in the function
5589 @code{commutative_operand_precedence} in @file{gcc/rtlanal.c}.
5593 @node Expander Definitions
5594 @section Defining RTL Sequences for Code Generation
5595 @cindex expander definitions
5596 @cindex code generation RTL sequences
5597 @cindex defining RTL sequences for code generation
5599 On some target machines, some standard pattern names for RTL generation
5600 cannot be handled with single insn, but a sequence of RTL insns can
5601 represent them. For these target machines, you can write a
5602 @code{define_expand} to specify how to generate the sequence of RTL@.
5604 @findex define_expand
5605 A @code{define_expand} is an RTL expression that looks almost like a
5606 @code{define_insn}; but, unlike the latter, a @code{define_expand} is used
5607 only for RTL generation and it can produce more than one RTL insn.
5609 A @code{define_expand} RTX has four operands:
5613 The name. Each @code{define_expand} must have a name, since the only
5614 use for it is to refer to it by name.
5617 The RTL template. This is a vector of RTL expressions representing
5618 a sequence of separate instructions. Unlike @code{define_insn}, there
5619 is no implicit surrounding @code{PARALLEL}.
5622 The condition, a string containing a C expression. This expression is
5623 used to express how the availability of this pattern depends on
5624 subclasses of target machine, selected by command-line options when GCC
5625 is run. This is just like the condition of a @code{define_insn} that
5626 has a standard name. Therefore, the condition (if present) may not
5627 depend on the data in the insn being matched, but only the
5628 target-machine-type flags. The compiler needs to test these conditions
5629 during initialization in order to learn exactly which named instructions
5630 are available in a particular run.
5633 The preparation statements, a string containing zero or more C
5634 statements which are to be executed before RTL code is generated from
5637 Usually these statements prepare temporary registers for use as
5638 internal operands in the RTL template, but they can also generate RTL
5639 insns directly by calling routines such as @code{emit_insn}, etc.
5640 Any such insns precede the ones that come from the RTL template.
5643 Every RTL insn emitted by a @code{define_expand} must match some
5644 @code{define_insn} in the machine description. Otherwise, the compiler
5645 will crash when trying to generate code for the insn or trying to optimize
5648 The RTL template, in addition to controlling generation of RTL insns,
5649 also describes the operands that need to be specified when this pattern
5650 is used. In particular, it gives a predicate for each operand.
5652 A true operand, which needs to be specified in order to generate RTL from
5653 the pattern, should be described with a @code{match_operand} in its first
5654 occurrence in the RTL template. This enters information on the operand's
5655 predicate into the tables that record such things. GCC uses the
5656 information to preload the operand into a register if that is required for
5657 valid RTL code. If the operand is referred to more than once, subsequent
5658 references should use @code{match_dup}.
5660 The RTL template may also refer to internal ``operands'' which are
5661 temporary registers or labels used only within the sequence made by the
5662 @code{define_expand}. Internal operands are substituted into the RTL
5663 template with @code{match_dup}, never with @code{match_operand}. The
5664 values of the internal operands are not passed in as arguments by the
5665 compiler when it requests use of this pattern. Instead, they are computed
5666 within the pattern, in the preparation statements. These statements
5667 compute the values and store them into the appropriate elements of
5668 @code{operands} so that @code{match_dup} can find them.
5670 There are two special macros defined for use in the preparation statements:
5671 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
5678 Use the @code{DONE} macro to end RTL generation for the pattern. The
5679 only RTL insns resulting from the pattern on this occasion will be
5680 those already emitted by explicit calls to @code{emit_insn} within the
5681 preparation statements; the RTL template will not be generated.
5685 Make the pattern fail on this occasion. When a pattern fails, it means
5686 that the pattern was not truly available. The calling routines in the
5687 compiler will try other strategies for code generation using other patterns.
5689 Failure is currently supported only for binary (addition, multiplication,
5690 shifting, etc.) and bit-field (@code{extv}, @code{extzv}, and @code{insv})
5694 If the preparation falls through (invokes neither @code{DONE} nor
5695 @code{FAIL}), then the @code{define_expand} acts like a
5696 @code{define_insn} in that the RTL template is used to generate the
5699 The RTL template is not used for matching, only for generating the
5700 initial insn list. If the preparation statement always invokes
5701 @code{DONE} or @code{FAIL}, the RTL template may be reduced to a simple
5702 list of operands, such as this example:
5706 (define_expand "addsi3"
5707 [(match_operand:SI 0 "register_operand" "")
5708 (match_operand:SI 1 "register_operand" "")
5709 (match_operand:SI 2 "register_operand" "")]
5715 handle_add (operands[0], operands[1], operands[2]);
5721 Here is an example, the definition of left-shift for the SPUR chip:
5725 (define_expand "ashlsi3"
5726 [(set (match_operand:SI 0 "register_operand" "")
5730 (match_operand:SI 1 "register_operand" "")
5731 (match_operand:SI 2 "nonmemory_operand" "")))]
5740 if (GET_CODE (operands[2]) != CONST_INT
5741 || (unsigned) INTVAL (operands[2]) > 3)
5748 This example uses @code{define_expand} so that it can generate an RTL insn
5749 for shifting when the shift-count is in the supported range of 0 to 3 but
5750 fail in other cases where machine insns aren't available. When it fails,
5751 the compiler tries another strategy using different patterns (such as, a
5754 If the compiler were able to handle nontrivial condition-strings in
5755 patterns with names, then it would be possible to use a
5756 @code{define_insn} in that case. Here is another case (zero-extension
5757 on the 68000) which makes more use of the power of @code{define_expand}:
5760 (define_expand "zero_extendhisi2"
5761 [(set (match_operand:SI 0 "general_operand" "")
5763 (set (strict_low_part
5767 (match_operand:HI 1 "general_operand" ""))]
5769 "operands[1] = make_safe_from (operands[1], operands[0]);")
5773 @findex make_safe_from
5774 Here two RTL insns are generated, one to clear the entire output operand
5775 and the other to copy the input operand into its low half. This sequence
5776 is incorrect if the input operand refers to [the old value of] the output
5777 operand, so the preparation statement makes sure this isn't so. The
5778 function @code{make_safe_from} copies the @code{operands[1]} into a
5779 temporary register if it refers to @code{operands[0]}. It does this
5780 by emitting another RTL insn.
5782 Finally, a third example shows the use of an internal operand.
5783 Zero-extension on the SPUR chip is done by @code{and}-ing the result
5784 against a halfword mask. But this mask cannot be represented by a
5785 @code{const_int} because the constant value is too large to be legitimate
5786 on this machine. So it must be copied into a register with
5787 @code{force_reg} and then the register used in the @code{and}.
5790 (define_expand "zero_extendhisi2"
5791 [(set (match_operand:SI 0 "register_operand" "")
5793 (match_operand:HI 1 "register_operand" "")
5798 = force_reg (SImode, GEN_INT (65535)); ")
5801 @emph{Note:} If the @code{define_expand} is used to serve a
5802 standard binary or unary arithmetic operation or a bit-field operation,
5803 then the last insn it generates must not be a @code{code_label},
5804 @code{barrier} or @code{note}. It must be an @code{insn},
5805 @code{jump_insn} or @code{call_insn}. If you don't need a real insn
5806 at the end, emit an insn to copy the result of the operation into
5807 itself. Such an insn will generate no code, but it can avoid problems
5812 @node Insn Splitting
5813 @section Defining How to Split Instructions
5814 @cindex insn splitting
5815 @cindex instruction splitting
5816 @cindex splitting instructions
5818 There are two cases where you should specify how to split a pattern
5819 into multiple insns. On machines that have instructions requiring
5820 delay slots (@pxref{Delay Slots}) or that have instructions whose
5821 output is not available for multiple cycles (@pxref{Processor pipeline
5822 description}), the compiler phases that optimize these cases need to
5823 be able to move insns into one-instruction delay slots. However, some
5824 insns may generate more than one machine instruction. These insns
5825 cannot be placed into a delay slot.
5827 Often you can rewrite the single insn as a list of individual insns,
5828 each corresponding to one machine instruction. The disadvantage of
5829 doing so is that it will cause the compilation to be slower and require
5830 more space. If the resulting insns are too complex, it may also
5831 suppress some optimizations. The compiler splits the insn if there is a
5832 reason to believe that it might improve instruction or delay slot
5835 The insn combiner phase also splits putative insns. If three insns are
5836 merged into one insn with a complex expression that cannot be matched by
5837 some @code{define_insn} pattern, the combiner phase attempts to split
5838 the complex pattern into two insns that are recognized. Usually it can
5839 break the complex pattern into two patterns by splitting out some
5840 subexpression. However, in some other cases, such as performing an
5841 addition of a large constant in two insns on a RISC machine, the way to
5842 split the addition into two insns is machine-dependent.
5844 @findex define_split
5845 The @code{define_split} definition tells the compiler how to split a
5846 complex insn into several simpler insns. It looks like this:
5850 [@var{insn-pattern}]
5852 [@var{new-insn-pattern-1}
5853 @var{new-insn-pattern-2}
5855 "@var{preparation-statements}")
5858 @var{insn-pattern} is a pattern that needs to be split and
5859 @var{condition} is the final condition to be tested, as in a
5860 @code{define_insn}. When an insn matching @var{insn-pattern} and
5861 satisfying @var{condition} is found, it is replaced in the insn list
5862 with the insns given by @var{new-insn-pattern-1},
5863 @var{new-insn-pattern-2}, etc.
5865 The @var{preparation-statements} are similar to those statements that
5866 are specified for @code{define_expand} (@pxref{Expander Definitions})
5867 and are executed before the new RTL is generated to prepare for the
5868 generated code or emit some insns whose pattern is not fixed. Unlike
5869 those in @code{define_expand}, however, these statements must not
5870 generate any new pseudo-registers. Once reload has completed, they also
5871 must not allocate any space in the stack frame.
5873 Patterns are matched against @var{insn-pattern} in two different
5874 circumstances. If an insn needs to be split for delay slot scheduling
5875 or insn scheduling, the insn is already known to be valid, which means
5876 that it must have been matched by some @code{define_insn} and, if
5877 @code{reload_completed} is nonzero, is known to satisfy the constraints
5878 of that @code{define_insn}. In that case, the new insn patterns must
5879 also be insns that are matched by some @code{define_insn} and, if
5880 @code{reload_completed} is nonzero, must also satisfy the constraints
5881 of those definitions.
5883 As an example of this usage of @code{define_split}, consider the following
5884 example from @file{a29k.md}, which splits a @code{sign_extend} from
5885 @code{HImode} to @code{SImode} into a pair of shift insns:
5889 [(set (match_operand:SI 0 "gen_reg_operand" "")
5890 (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
5893 (ashift:SI (match_dup 1)
5896 (ashiftrt:SI (match_dup 0)
5899 @{ operands[1] = gen_lowpart (SImode, operands[1]); @}")
5902 When the combiner phase tries to split an insn pattern, it is always the
5903 case that the pattern is @emph{not} matched by any @code{define_insn}.
5904 The combiner pass first tries to split a single @code{set} expression
5905 and then the same @code{set} expression inside a @code{parallel}, but
5906 followed by a @code{clobber} of a pseudo-reg to use as a scratch
5907 register. In these cases, the combiner expects exactly two new insn
5908 patterns to be generated. It will verify that these patterns match some
5909 @code{define_insn} definitions, so you need not do this test in the
5910 @code{define_split} (of course, there is no point in writing a
5911 @code{define_split} that will never produce insns that match).
5913 Here is an example of this use of @code{define_split}, taken from
5918 [(set (match_operand:SI 0 "gen_reg_operand" "")
5919 (plus:SI (match_operand:SI 1 "gen_reg_operand" "")
5920 (match_operand:SI 2 "non_add_cint_operand" "")))]
5922 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
5923 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
5926 int low = INTVAL (operands[2]) & 0xffff;
5927 int high = (unsigned) INTVAL (operands[2]) >> 16;
5930 high++, low |= 0xffff0000;
5932 operands[3] = GEN_INT (high << 16);
5933 operands[4] = GEN_INT (low);
5937 Here the predicate @code{non_add_cint_operand} matches any
5938 @code{const_int} that is @emph{not} a valid operand of a single add
5939 insn. The add with the smaller displacement is written so that it
5940 can be substituted into the address of a subsequent operation.
5942 An example that uses a scratch register, from the same file, generates
5943 an equality comparison of a register and a large constant:
5947 [(set (match_operand:CC 0 "cc_reg_operand" "")
5948 (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
5949 (match_operand:SI 2 "non_short_cint_operand" "")))
5950 (clobber (match_operand:SI 3 "gen_reg_operand" ""))]
5951 "find_single_use (operands[0], insn, 0)
5952 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
5953 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
5954 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
5955 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
5958 /* @r{Get the constant we are comparing against, C, and see what it
5959 looks like sign-extended to 16 bits. Then see what constant
5960 could be XOR'ed with C to get the sign-extended value.} */
5962 int c = INTVAL (operands[2]);
5963 int sextc = (c << 16) >> 16;
5964 int xorv = c ^ sextc;
5966 operands[4] = GEN_INT (xorv);
5967 operands[5] = GEN_INT (sextc);
5971 To avoid confusion, don't write a single @code{define_split} that
5972 accepts some insns that match some @code{define_insn} as well as some
5973 insns that don't. Instead, write two separate @code{define_split}
5974 definitions, one for the insns that are valid and one for the insns that
5977 The splitter is allowed to split jump instructions into sequence of
5978 jumps or create new jumps in while splitting non-jump instructions. As
5979 the central flowgraph and branch prediction information needs to be updated,
5980 several restriction apply.
5982 Splitting of jump instruction into sequence that over by another jump
5983 instruction is always valid, as compiler expect identical behavior of new
5984 jump. When new sequence contains multiple jump instructions or new labels,
5985 more assistance is needed. Splitter is required to create only unconditional
5986 jumps, or simple conditional jump instructions. Additionally it must attach a
5987 @code{REG_BR_PROB} note to each conditional jump. A global variable
5988 @code{split_branch_probability} holds the probability of the original branch in case
5989 it was an simple conditional jump, @minus{}1 otherwise. To simplify
5990 recomputing of edge frequencies, the new sequence is required to have only
5991 forward jumps to the newly created labels.
5993 @findex define_insn_and_split
5994 For the common case where the pattern of a define_split exactly matches the
5995 pattern of a define_insn, use @code{define_insn_and_split}. It looks like
5999 (define_insn_and_split
6000 [@var{insn-pattern}]
6002 "@var{output-template}"
6003 "@var{split-condition}"
6004 [@var{new-insn-pattern-1}
6005 @var{new-insn-pattern-2}
6007 "@var{preparation-statements}"
6008 [@var{insn-attributes}])
6012 @var{insn-pattern}, @var{condition}, @var{output-template}, and
6013 @var{insn-attributes} are used as in @code{define_insn}. The
6014 @var{new-insn-pattern} vector and the @var{preparation-statements} are used as
6015 in a @code{define_split}. The @var{split-condition} is also used as in
6016 @code{define_split}, with the additional behavior that if the condition starts
6017 with @samp{&&}, the condition used for the split will be the constructed as a
6018 logical ``and'' of the split condition with the insn condition. For example,
6022 (define_insn_and_split "zero_extendhisi2_and"
6023 [(set (match_operand:SI 0 "register_operand" "=r")
6024 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
6025 (clobber (reg:CC 17))]
6026 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
6028 "&& reload_completed"
6029 [(parallel [(set (match_dup 0)
6030 (and:SI (match_dup 0) (const_int 65535)))
6031 (clobber (reg:CC 17))])]
6033 [(set_attr "type" "alu1")])
6037 In this case, the actual split condition will be
6038 @samp{TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed}.
6040 The @code{define_insn_and_split} construction provides exactly the same
6041 functionality as two separate @code{define_insn} and @code{define_split}
6042 patterns. It exists for compactness, and as a maintenance tool to prevent
6043 having to ensure the two patterns' templates match.
6047 @node Including Patterns
6048 @section Including Patterns in Machine Descriptions.
6049 @cindex insn includes
6052 The @code{include} pattern tells the compiler tools where to
6053 look for patterns that are in files other than in the file
6054 @file{.md}. This is used only at build time and there is no preprocessing allowed.
6068 (include "filestuff")
6072 Where @var{pathname} is a string that specifies the location of the file,
6073 specifies the include file to be in @file{gcc/config/target/filestuff}. The
6074 directory @file{gcc/config/target} is regarded as the default directory.
6077 Machine descriptions may be split up into smaller more manageable subsections
6078 and placed into subdirectories.
6084 (include "BOGUS/filestuff")
6088 the include file is specified to be in @file{gcc/config/@var{target}/BOGUS/filestuff}.
6090 Specifying an absolute path for the include file such as;
6093 (include "/u2/BOGUS/filestuff")
6096 is permitted but is not encouraged.
6098 @subsection RTL Generation Tool Options for Directory Search
6099 @cindex directory options .md
6100 @cindex options, directory search
6101 @cindex search options
6103 The @option{-I@var{dir}} option specifies directories to search for machine descriptions.
6108 genrecog -I/p1/abc/proc1 -I/p2/abcd/pro2 target.md
6113 Add the directory @var{dir} to the head of the list of directories to be
6114 searched for header files. This can be used to override a system machine definition
6115 file, substituting your own version, since these directories are
6116 searched before the default machine description file directories. If you use more than
6117 one @option{-I} option, the directories are scanned in left-to-right
6118 order; the standard default directory come after.
6123 @node Peephole Definitions
6124 @section Machine-Specific Peephole Optimizers
6125 @cindex peephole optimizer definitions
6126 @cindex defining peephole optimizers
6128 In addition to instruction patterns the @file{md} file may contain
6129 definitions of machine-specific peephole optimizations.
6131 The combiner does not notice certain peephole optimizations when the data
6132 flow in the program does not suggest that it should try them. For example,
6133 sometimes two consecutive insns related in purpose can be combined even
6134 though the second one does not appear to use a register computed in the
6135 first one. A machine-specific peephole optimizer can detect such
6138 There are two forms of peephole definitions that may be used. The
6139 original @code{define_peephole} is run at assembly output time to
6140 match insns and substitute assembly text. Use of @code{define_peephole}
6143 A newer @code{define_peephole2} matches insns and substitutes new
6144 insns. The @code{peephole2} pass is run after register allocation
6145 but before scheduling, which may result in much better code for
6146 targets that do scheduling.
6149 * define_peephole:: RTL to Text Peephole Optimizers
6150 * define_peephole2:: RTL to RTL Peephole Optimizers
6155 @node define_peephole
6156 @subsection RTL to Text Peephole Optimizers
6157 @findex define_peephole
6160 A definition looks like this:
6164 [@var{insn-pattern-1}
6165 @var{insn-pattern-2}
6169 "@var{optional-insn-attributes}")
6173 The last string operand may be omitted if you are not using any
6174 machine-specific information in this machine description. If present,
6175 it must obey the same rules as in a @code{define_insn}.
6177 In this skeleton, @var{insn-pattern-1} and so on are patterns to match
6178 consecutive insns. The optimization applies to a sequence of insns when
6179 @var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches
6180 the next, and so on.
6182 Each of the insns matched by a peephole must also match a
6183 @code{define_insn}. Peepholes are checked only at the last stage just
6184 before code generation, and only optionally. Therefore, any insn which
6185 would match a peephole but no @code{define_insn} will cause a crash in code
6186 generation in an unoptimized compilation, or at various optimization
6189 The operands of the insns are matched with @code{match_operands},
6190 @code{match_operator}, and @code{match_dup}, as usual. What is not
6191 usual is that the operand numbers apply to all the insn patterns in the
6192 definition. So, you can check for identical operands in two insns by
6193 using @code{match_operand} in one insn and @code{match_dup} in the
6196 The operand constraints used in @code{match_operand} patterns do not have
6197 any direct effect on the applicability of the peephole, but they will
6198 be validated afterward, so make sure your constraints are general enough
6199 to apply whenever the peephole matches. If the peephole matches
6200 but the constraints are not satisfied, the compiler will crash.
6202 It is safe to omit constraints in all the operands of the peephole; or
6203 you can write constraints which serve as a double-check on the criteria
6206 Once a sequence of insns matches the patterns, the @var{condition} is
6207 checked. This is a C expression which makes the final decision whether to
6208 perform the optimization (we do so if the expression is nonzero). If
6209 @var{condition} is omitted (in other words, the string is empty) then the
6210 optimization is applied to every sequence of insns that matches the
6213 The defined peephole optimizations are applied after register allocation
6214 is complete. Therefore, the peephole definition can check which
6215 operands have ended up in which kinds of registers, just by looking at
6218 @findex prev_active_insn
6219 The way to refer to the operands in @var{condition} is to write
6220 @code{operands[@var{i}]} for operand number @var{i} (as matched by
6221 @code{(match_operand @var{i} @dots{})}). Use the variable @code{insn}
6222 to refer to the last of the insns being matched; use
6223 @code{prev_active_insn} to find the preceding insns.
6225 @findex dead_or_set_p
6226 When optimizing computations with intermediate results, you can use
6227 @var{condition} to match only when the intermediate results are not used
6228 elsewhere. Use the C expression @code{dead_or_set_p (@var{insn},
6229 @var{op})}, where @var{insn} is the insn in which you expect the value
6230 to be used for the last time (from the value of @code{insn}, together
6231 with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate
6232 value (from @code{operands[@var{i}]}).
6234 Applying the optimization means replacing the sequence of insns with one
6235 new insn. The @var{template} controls ultimate output of assembler code
6236 for this combined insn. It works exactly like the template of a
6237 @code{define_insn}. Operand numbers in this template are the same ones
6238 used in matching the original sequence of insns.
6240 The result of a defined peephole optimizer does not need to match any of
6241 the insn patterns in the machine description; it does not even have an
6242 opportunity to match them. The peephole optimizer definition itself serves
6243 as the insn pattern to control how the insn is output.
6245 Defined peephole optimizers are run as assembler code is being output,
6246 so the insns they produce are never combined or rearranged in any way.
6248 Here is an example, taken from the 68000 machine description:
6252 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
6253 (set (match_operand:DF 0 "register_operand" "=f")
6254 (match_operand:DF 1 "register_operand" "ad"))]
6255 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
6258 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
6260 output_asm_insn ("move.l %1,(sp)", xoperands);
6261 output_asm_insn ("move.l %1,-(sp)", operands);
6262 return "fmove.d (sp)+,%0";
6264 output_asm_insn ("movel %1,sp@@", xoperands);
6265 output_asm_insn ("movel %1,sp@@-", operands);
6266 return "fmoved sp@@+,%0";
6272 The effect of this optimization is to change
6298 If a peephole matches a sequence including one or more jump insns, you must
6299 take account of the flags such as @code{CC_REVERSED} which specify that the
6300 condition codes are represented in an unusual manner. The compiler
6301 automatically alters any ordinary conditional jumps which occur in such
6302 situations, but the compiler cannot alter jumps which have been replaced by
6303 peephole optimizations. So it is up to you to alter the assembler code
6304 that the peephole produces. Supply C code to write the assembler output,
6305 and in this C code check the condition code status flags and change the
6306 assembler code as appropriate.
6309 @var{insn-pattern-1} and so on look @emph{almost} like the second
6310 operand of @code{define_insn}. There is one important difference: the
6311 second operand of @code{define_insn} consists of one or more RTX's
6312 enclosed in square brackets. Usually, there is only one: then the same
6313 action can be written as an element of a @code{define_peephole}. But
6314 when there are multiple actions in a @code{define_insn}, they are
6315 implicitly enclosed in a @code{parallel}. Then you must explicitly
6316 write the @code{parallel}, and the square brackets within it, in the
6317 @code{define_peephole}. Thus, if an insn pattern looks like this,
6320 (define_insn "divmodsi4"
6321 [(set (match_operand:SI 0 "general_operand" "=d")
6322 (div:SI (match_operand:SI 1 "general_operand" "0")
6323 (match_operand:SI 2 "general_operand" "dmsK")))
6324 (set (match_operand:SI 3 "general_operand" "=d")
6325 (mod:SI (match_dup 1) (match_dup 2)))]
6327 "divsl%.l %2,%3:%0")
6331 then the way to mention this insn in a peephole is as follows:
6337 [(set (match_operand:SI 0 "general_operand" "=d")
6338 (div:SI (match_operand:SI 1 "general_operand" "0")
6339 (match_operand:SI 2 "general_operand" "dmsK")))
6340 (set (match_operand:SI 3 "general_operand" "=d")
6341 (mod:SI (match_dup 1) (match_dup 2)))])
6348 @node define_peephole2
6349 @subsection RTL to RTL Peephole Optimizers
6350 @findex define_peephole2
6352 The @code{define_peephole2} definition tells the compiler how to
6353 substitute one sequence of instructions for another sequence,
6354 what additional scratch registers may be needed and what their
6359 [@var{insn-pattern-1}
6360 @var{insn-pattern-2}
6363 [@var{new-insn-pattern-1}
6364 @var{new-insn-pattern-2}
6366 "@var{preparation-statements}")
6369 The definition is almost identical to @code{define_split}
6370 (@pxref{Insn Splitting}) except that the pattern to match is not a
6371 single instruction, but a sequence of instructions.
6373 It is possible to request additional scratch registers for use in the
6374 output template. If appropriate registers are not free, the pattern
6375 will simply not match.
6377 @findex match_scratch
6379 Scratch registers are requested with a @code{match_scratch} pattern at
6380 the top level of the input pattern. The allocated register (initially) will
6381 be dead at the point requested within the original sequence. If the scratch
6382 is used at more than a single point, a @code{match_dup} pattern at the
6383 top level of the input pattern marks the last position in the input sequence
6384 at which the register must be available.
6386 Here is an example from the IA-32 machine description:
6390 [(match_scratch:SI 2 "r")
6391 (parallel [(set (match_operand:SI 0 "register_operand" "")
6392 (match_operator:SI 3 "arith_or_logical_operator"
6394 (match_operand:SI 1 "memory_operand" "")]))
6395 (clobber (reg:CC 17))])]
6396 "! optimize_size && ! TARGET_READ_MODIFY"
6397 [(set (match_dup 2) (match_dup 1))
6398 (parallel [(set (match_dup 0)
6399 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
6400 (clobber (reg:CC 17))])]
6405 This pattern tries to split a load from its use in the hopes that we'll be
6406 able to schedule around the memory load latency. It allocates a single
6407 @code{SImode} register of class @code{GENERAL_REGS} (@code{"r"}) that needs
6408 to be live only at the point just before the arithmetic.
6410 A real example requiring extended scratch lifetimes is harder to come by,
6411 so here's a silly made-up example:
6415 [(match_scratch:SI 4 "r")
6416 (set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
6417 (set (match_operand:SI 2 "" "") (match_dup 1))
6419 (set (match_operand:SI 3 "" "") (match_dup 1))]
6420 "/* @r{determine 1 does not overlap 0 and 2} */"
6421 [(set (match_dup 4) (match_dup 1))
6422 (set (match_dup 0) (match_dup 4))
6423 (set (match_dup 2) (match_dup 4))]
6424 (set (match_dup 3) (match_dup 4))]
6429 If we had not added the @code{(match_dup 4)} in the middle of the input
6430 sequence, it might have been the case that the register we chose at the
6431 beginning of the sequence is killed by the first or second @code{set}.
6435 @node Insn Attributes
6436 @section Instruction Attributes
6437 @cindex insn attributes
6438 @cindex instruction attributes
6440 In addition to describing the instruction supported by the target machine,
6441 the @file{md} file also defines a group of @dfn{attributes} and a set of
6442 values for each. Every generated insn is assigned a value for each attribute.
6443 One possible attribute would be the effect that the insn has on the machine's
6444 condition code. This attribute can then be used by @code{NOTICE_UPDATE_CC}
6445 to track the condition codes.
6448 * Defining Attributes:: Specifying attributes and their values.
6449 * Expressions:: Valid expressions for attribute values.
6450 * Tagging Insns:: Assigning attribute values to insns.
6451 * Attr Example:: An example of assigning attributes.
6452 * Insn Lengths:: Computing the length of insns.
6453 * Constant Attributes:: Defining attributes that are constant.
6454 * Delay Slots:: Defining delay slots required for a machine.
6455 * Processor pipeline description:: Specifying information for insn scheduling.
6460 @node Defining Attributes
6461 @subsection Defining Attributes and their Values
6462 @cindex defining attributes and their values
6463 @cindex attributes, defining
6466 The @code{define_attr} expression is used to define each attribute required
6467 by the target machine. It looks like:
6470 (define_attr @var{name} @var{list-of-values} @var{default})
6473 @var{name} is a string specifying the name of the attribute being defined.
6475 @var{list-of-values} is either a string that specifies a comma-separated
6476 list of values that can be assigned to the attribute, or a null string to
6477 indicate that the attribute takes numeric values.
6479 @var{default} is an attribute expression that gives the value of this
6480 attribute for insns that match patterns whose definition does not include
6481 an explicit value for this attribute. @xref{Attr Example}, for more
6482 information on the handling of defaults. @xref{Constant Attributes},
6483 for information on attributes that do not depend on any particular insn.
6486 For each defined attribute, a number of definitions are written to the
6487 @file{insn-attr.h} file. For cases where an explicit set of values is
6488 specified for an attribute, the following are defined:
6492 A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}.
6495 An enumerated class is defined for @samp{attr_@var{name}} with
6496 elements of the form @samp{@var{upper-name}_@var{upper-value}} where
6497 the attribute name and value are first converted to uppercase.
6500 A function @samp{get_attr_@var{name}} is defined that is passed an insn and
6501 returns the attribute value for that insn.
6504 For example, if the following is present in the @file{md} file:
6507 (define_attr "type" "branch,fp,load,store,arith" @dots{})
6511 the following lines will be written to the file @file{insn-attr.h}.
6514 #define HAVE_ATTR_type
6515 enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD,
6516 TYPE_STORE, TYPE_ARITH@};
6517 extern enum attr_type get_attr_type ();
6520 If the attribute takes numeric values, no @code{enum} type will be
6521 defined and the function to obtain the attribute's value will return
6527 @subsection Attribute Expressions
6528 @cindex attribute expressions
6530 RTL expressions used to define attributes use the codes described above
6531 plus a few specific to attribute definitions, to be discussed below.
6532 Attribute value expressions must have one of the following forms:
6535 @cindex @code{const_int} and attributes
6536 @item (const_int @var{i})
6537 The integer @var{i} specifies the value of a numeric attribute. @var{i}
6538 must be non-negative.
6540 The value of a numeric attribute can be specified either with a
6541 @code{const_int}, or as an integer represented as a string in
6542 @code{const_string}, @code{eq_attr} (see below), @code{attr},
6543 @code{symbol_ref}, simple arithmetic expressions, and @code{set_attr}
6544 overrides on specific instructions (@pxref{Tagging Insns}).
6546 @cindex @code{const_string} and attributes
6547 @item (const_string @var{value})
6548 The string @var{value} specifies a constant attribute value.
6549 If @var{value} is specified as @samp{"*"}, it means that the default value of
6550 the attribute is to be used for the insn containing this expression.
6551 @samp{"*"} obviously cannot be used in the @var{default} expression
6552 of a @code{define_attr}.
6554 If the attribute whose value is being specified is numeric, @var{value}
6555 must be a string containing a non-negative integer (normally
6556 @code{const_int} would be used in this case). Otherwise, it must
6557 contain one of the valid values for the attribute.
6559 @cindex @code{if_then_else} and attributes
6560 @item (if_then_else @var{test} @var{true-value} @var{false-value})
6561 @var{test} specifies an attribute test, whose format is defined below.
6562 The value of this expression is @var{true-value} if @var{test} is true,
6563 otherwise it is @var{false-value}.
6565 @cindex @code{cond} and attributes
6566 @item (cond [@var{test1} @var{value1} @dots{}] @var{default})
6567 The first operand of this expression is a vector containing an even
6568 number of expressions and consisting of pairs of @var{test} and @var{value}
6569 expressions. The value of the @code{cond} expression is that of the
6570 @var{value} corresponding to the first true @var{test} expression. If
6571 none of the @var{test} expressions are true, the value of the @code{cond}
6572 expression is that of the @var{default} expression.
6575 @var{test} expressions can have one of the following forms:
6578 @cindex @code{const_int} and attribute tests
6579 @item (const_int @var{i})
6580 This test is true if @var{i} is nonzero and false otherwise.
6582 @cindex @code{not} and attributes
6583 @cindex @code{ior} and attributes
6584 @cindex @code{and} and attributes
6585 @item (not @var{test})
6586 @itemx (ior @var{test1} @var{test2})
6587 @itemx (and @var{test1} @var{test2})
6588 These tests are true if the indicated logical function is true.
6590 @cindex @code{match_operand} and attributes
6591 @item (match_operand:@var{m} @var{n} @var{pred} @var{constraints})
6592 This test is true if operand @var{n} of the insn whose attribute value
6593 is being determined has mode @var{m} (this part of the test is ignored
6594 if @var{m} is @code{VOIDmode}) and the function specified by the string
6595 @var{pred} returns a nonzero value when passed operand @var{n} and mode
6596 @var{m} (this part of the test is ignored if @var{pred} is the null
6599 The @var{constraints} operand is ignored and should be the null string.
6601 @cindex @code{le} and attributes
6602 @cindex @code{leu} and attributes
6603 @cindex @code{lt} and attributes
6604 @cindex @code{gt} and attributes
6605 @cindex @code{gtu} and attributes
6606 @cindex @code{ge} and attributes
6607 @cindex @code{geu} and attributes
6608 @cindex @code{ne} and attributes
6609 @cindex @code{eq} and attributes
6610 @cindex @code{plus} and attributes
6611 @cindex @code{minus} and attributes
6612 @cindex @code{mult} and attributes
6613 @cindex @code{div} and attributes
6614 @cindex @code{mod} and attributes
6615 @cindex @code{abs} and attributes
6616 @cindex @code{neg} and attributes
6617 @cindex @code{ashift} and attributes
6618 @cindex @code{lshiftrt} and attributes
6619 @cindex @code{ashiftrt} and attributes
6620 @item (le @var{arith1} @var{arith2})
6621 @itemx (leu @var{arith1} @var{arith2})
6622 @itemx (lt @var{arith1} @var{arith2})
6623 @itemx (ltu @var{arith1} @var{arith2})
6624 @itemx (gt @var{arith1} @var{arith2})
6625 @itemx (gtu @var{arith1} @var{arith2})
6626 @itemx (ge @var{arith1} @var{arith2})
6627 @itemx (geu @var{arith1} @var{arith2})
6628 @itemx (ne @var{arith1} @var{arith2})
6629 @itemx (eq @var{arith1} @var{arith2})
6630 These tests are true if the indicated comparison of the two arithmetic
6631 expressions is true. Arithmetic expressions are formed with
6632 @code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod},
6633 @code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not},
6634 @code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions.
6637 @code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn
6638 Lengths},for additional forms). @code{symbol_ref} is a string
6639 denoting a C expression that yields an @code{int} when evaluated by the
6640 @samp{get_attr_@dots{}} routine. It should normally be a global
6644 @item (eq_attr @var{name} @var{value})
6645 @var{name} is a string specifying the name of an attribute.
6647 @var{value} is a string that is either a valid value for attribute
6648 @var{name}, a comma-separated list of values, or @samp{!} followed by a
6649 value or list. If @var{value} does not begin with a @samp{!}, this
6650 test is true if the value of the @var{name} attribute of the current
6651 insn is in the list specified by @var{value}. If @var{value} begins
6652 with a @samp{!}, this test is true if the attribute's value is
6653 @emph{not} in the specified list.
6658 (eq_attr "type" "load,store")
6665 (ior (eq_attr "type" "load") (eq_attr "type" "store"))
6668 If @var{name} specifies an attribute of @samp{alternative}, it refers to the
6669 value of the compiler variable @code{which_alternative}
6670 (@pxref{Output Statement}) and the values must be small integers. For
6674 (eq_attr "alternative" "2,3")
6681 (ior (eq (symbol_ref "which_alternative") (const_int 2))
6682 (eq (symbol_ref "which_alternative") (const_int 3)))
6685 Note that, for most attributes, an @code{eq_attr} test is simplified in cases
6686 where the value of the attribute being tested is known for all insns matching
6687 a particular pattern. This is by far the most common case.
6690 @item (attr_flag @var{name})
6691 The value of an @code{attr_flag} expression is true if the flag
6692 specified by @var{name} is true for the @code{insn} currently being
6695 @var{name} is a string specifying one of a fixed set of flags to test.
6696 Test the flags @code{forward} and @code{backward} to determine the
6697 direction of a conditional branch. Test the flags @code{very_likely},
6698 @code{likely}, @code{very_unlikely}, and @code{unlikely} to determine
6699 if a conditional branch is expected to be taken.
6701 If the @code{very_likely} flag is true, then the @code{likely} flag is also
6702 true. Likewise for the @code{very_unlikely} and @code{unlikely} flags.
6704 This example describes a conditional branch delay slot which
6705 can be nullified for forward branches that are taken (annul-true) or
6706 for backward branches which are not taken (annul-false).
6709 (define_delay (eq_attr "type" "cbranch")
6710 [(eq_attr "in_branch_delay" "true")
6711 (and (eq_attr "in_branch_delay" "true")
6712 (attr_flag "forward"))
6713 (and (eq_attr "in_branch_delay" "true")
6714 (attr_flag "backward"))])
6717 The @code{forward} and @code{backward} flags are false if the current
6718 @code{insn} being scheduled is not a conditional branch.
6720 The @code{very_likely} and @code{likely} flags are true if the
6721 @code{insn} being scheduled is not a conditional branch.
6722 The @code{very_unlikely} and @code{unlikely} flags are false if the
6723 @code{insn} being scheduled is not a conditional branch.
6725 @code{attr_flag} is only used during delay slot scheduling and has no
6726 meaning to other passes of the compiler.
6729 @item (attr @var{name})
6730 The value of another attribute is returned. This is most useful
6731 for numeric attributes, as @code{eq_attr} and @code{attr_flag}
6732 produce more efficient code for non-numeric attributes.
6738 @subsection Assigning Attribute Values to Insns
6739 @cindex tagging insns
6740 @cindex assigning attribute values to insns
6742 The value assigned to an attribute of an insn is primarily determined by
6743 which pattern is matched by that insn (or which @code{define_peephole}
6744 generated it). Every @code{define_insn} and @code{define_peephole} can
6745 have an optional last argument to specify the values of attributes for
6746 matching insns. The value of any attribute not specified in a particular
6747 insn is set to the default value for that attribute, as specified in its
6748 @code{define_attr}. Extensive use of default values for attributes
6749 permits the specification of the values for only one or two attributes
6750 in the definition of most insn patterns, as seen in the example in the
6753 The optional last argument of @code{define_insn} and
6754 @code{define_peephole} is a vector of expressions, each of which defines
6755 the value for a single attribute. The most general way of assigning an
6756 attribute's value is to use a @code{set} expression whose first operand is an
6757 @code{attr} expression giving the name of the attribute being set. The
6758 second operand of the @code{set} is an attribute expression
6759 (@pxref{Expressions}) giving the value of the attribute.
6761 When the attribute value depends on the @samp{alternative} attribute
6762 (i.e., which is the applicable alternative in the constraint of the
6763 insn), the @code{set_attr_alternative} expression can be used. It
6764 allows the specification of a vector of attribute expressions, one for
6768 When the generality of arbitrary attribute expressions is not required,
6769 the simpler @code{set_attr} expression can be used, which allows
6770 specifying a string giving either a single attribute value or a list
6771 of attribute values, one for each alternative.
6773 The form of each of the above specifications is shown below. In each case,
6774 @var{name} is a string specifying the attribute to be set.
6777 @item (set_attr @var{name} @var{value-string})
6778 @var{value-string} is either a string giving the desired attribute value,
6779 or a string containing a comma-separated list giving the values for
6780 succeeding alternatives. The number of elements must match the number
6781 of alternatives in the constraint of the insn pattern.
6783 Note that it may be useful to specify @samp{*} for some alternative, in
6784 which case the attribute will assume its default value for insns matching
6787 @findex set_attr_alternative
6788 @item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}])
6789 Depending on the alternative of the insn, the value will be one of the
6790 specified values. This is a shorthand for using a @code{cond} with
6791 tests on the @samp{alternative} attribute.
6794 @item (set (attr @var{name}) @var{value})
6795 The first operand of this @code{set} must be the special RTL expression
6796 @code{attr}, whose sole operand is a string giving the name of the
6797 attribute being set. @var{value} is the value of the attribute.
6800 The following shows three different ways of representing the same
6801 attribute value specification:
6804 (set_attr "type" "load,store,arith")
6806 (set_attr_alternative "type"
6807 [(const_string "load") (const_string "store")
6808 (const_string "arith")])
6811 (cond [(eq_attr "alternative" "1") (const_string "load")
6812 (eq_attr "alternative" "2") (const_string "store")]
6813 (const_string "arith")))
6817 @findex define_asm_attributes
6818 The @code{define_asm_attributes} expression provides a mechanism to
6819 specify the attributes assigned to insns produced from an @code{asm}
6820 statement. It has the form:
6823 (define_asm_attributes [@var{attr-sets}])
6827 where @var{attr-sets} is specified the same as for both the
6828 @code{define_insn} and the @code{define_peephole} expressions.
6830 These values will typically be the ``worst case'' attribute values. For
6831 example, they might indicate that the condition code will be clobbered.
6833 A specification for a @code{length} attribute is handled specially. The
6834 way to compute the length of an @code{asm} insn is to multiply the
6835 length specified in the expression @code{define_asm_attributes} by the
6836 number of machine instructions specified in the @code{asm} statement,
6837 determined by counting the number of semicolons and newlines in the
6838 string. Therefore, the value of the @code{length} attribute specified
6839 in a @code{define_asm_attributes} should be the maximum possible length
6840 of a single machine instruction.
6845 @subsection Example of Attribute Specifications
6846 @cindex attribute specifications example
6847 @cindex attribute specifications
6849 The judicious use of defaulting is important in the efficient use of
6850 insn attributes. Typically, insns are divided into @dfn{types} and an
6851 attribute, customarily called @code{type}, is used to represent this
6852 value. This attribute is normally used only to define the default value
6853 for other attributes. An example will clarify this usage.
6855 Assume we have a RISC machine with a condition code and in which only
6856 full-word operations are performed in registers. Let us assume that we
6857 can divide all insns into loads, stores, (integer) arithmetic
6858 operations, floating point operations, and branches.
6860 Here we will concern ourselves with determining the effect of an insn on
6861 the condition code and will limit ourselves to the following possible
6862 effects: The condition code can be set unpredictably (clobbered), not
6863 be changed, be set to agree with the results of the operation, or only
6864 changed if the item previously set into the condition code has been
6867 Here is part of a sample @file{md} file for such a machine:
6870 (define_attr "type" "load,store,arith,fp,branch" (const_string "arith"))
6872 (define_attr "cc" "clobber,unchanged,set,change0"
6873 (cond [(eq_attr "type" "load")
6874 (const_string "change0")
6875 (eq_attr "type" "store,branch")
6876 (const_string "unchanged")
6877 (eq_attr "type" "arith")
6878 (if_then_else (match_operand:SI 0 "" "")
6879 (const_string "set")
6880 (const_string "clobber"))]
6881 (const_string "clobber")))
6884 [(set (match_operand:SI 0 "general_operand" "=r,r,m")
6885 (match_operand:SI 1 "general_operand" "r,m,r"))]
6891 [(set_attr "type" "arith,load,store")])
6894 Note that we assume in the above example that arithmetic operations
6895 performed on quantities smaller than a machine word clobber the condition
6896 code since they will set the condition code to a value corresponding to the
6902 @subsection Computing the Length of an Insn
6903 @cindex insn lengths, computing
6904 @cindex computing the length of an insn
6906 For many machines, multiple types of branch instructions are provided, each
6907 for different length branch displacements. In most cases, the assembler
6908 will choose the correct instruction to use. However, when the assembler
6909 cannot do so, GCC can when a special attribute, the @code{length}
6910 attribute, is defined. This attribute must be defined to have numeric
6911 values by specifying a null string in its @code{define_attr}.
6913 In the case of the @code{length} attribute, two additional forms of
6914 arithmetic terms are allowed in test expressions:
6917 @cindex @code{match_dup} and attributes
6918 @item (match_dup @var{n})
6919 This refers to the address of operand @var{n} of the current insn, which
6920 must be a @code{label_ref}.
6922 @cindex @code{pc} and attributes
6924 This refers to the address of the @emph{current} insn. It might have
6925 been more consistent with other usage to make this the address of the
6926 @emph{next} insn but this would be confusing because the length of the
6927 current insn is to be computed.
6930 @cindex @code{addr_vec}, length of
6931 @cindex @code{addr_diff_vec}, length of
6932 For normal insns, the length will be determined by value of the
6933 @code{length} attribute. In the case of @code{addr_vec} and
6934 @code{addr_diff_vec} insn patterns, the length is computed as
6935 the number of vectors multiplied by the size of each vector.
6937 Lengths are measured in addressable storage units (bytes).
6939 The following macros can be used to refine the length computation:
6942 @findex ADJUST_INSN_LENGTH
6943 @item ADJUST_INSN_LENGTH (@var{insn}, @var{length})
6944 If defined, modifies the length assigned to instruction @var{insn} as a
6945 function of the context in which it is used. @var{length} is an lvalue
6946 that contains the initially computed length of the insn and should be
6947 updated with the correct length of the insn.
6949 This macro will normally not be required. A case in which it is
6950 required is the ROMP@. On this machine, the size of an @code{addr_vec}
6951 insn must be increased by two to compensate for the fact that alignment
6955 @findex get_attr_length
6956 The routine that returns @code{get_attr_length} (the value of the
6957 @code{length} attribute) can be used by the output routine to
6958 determine the form of the branch instruction to be written, as the
6959 example below illustrates.
6961 As an example of the specification of variable-length branches, consider
6962 the IBM 360. If we adopt the convention that a register will be set to
6963 the starting address of a function, we can jump to labels within 4k of
6964 the start using a four-byte instruction. Otherwise, we need a six-byte
6965 sequence to load the address from memory and then branch to it.
6967 On such a machine, a pattern for a branch instruction might be specified
6973 (label_ref (match_operand 0 "" "")))]
6976 return (get_attr_length (insn) == 4
6977 ? "b %l0" : "l r15,=a(%l0); br r15");
6979 [(set (attr "length")
6980 (if_then_else (lt (match_dup 0) (const_int 4096))
6987 @node Constant Attributes
6988 @subsection Constant Attributes
6989 @cindex constant attributes
6991 A special form of @code{define_attr}, where the expression for the
6992 default value is a @code{const} expression, indicates an attribute that
6993 is constant for a given run of the compiler. Constant attributes may be
6994 used to specify which variety of processor is used. For example,
6997 (define_attr "cpu" "m88100,m88110,m88000"
6999 (cond [(symbol_ref "TARGET_88100") (const_string "m88100")
7000 (symbol_ref "TARGET_88110") (const_string "m88110")]
7001 (const_string "m88000"))))
7003 (define_attr "memory" "fast,slow"
7005 (if_then_else (symbol_ref "TARGET_FAST_MEM")
7006 (const_string "fast")
7007 (const_string "slow"))))
7010 The routine generated for constant attributes has no parameters as it
7011 does not depend on any particular insn. RTL expressions used to define
7012 the value of a constant attribute may use the @code{symbol_ref} form,
7013 but may not use either the @code{match_operand} form or @code{eq_attr}
7014 forms involving insn attributes.
7019 @subsection Delay Slot Scheduling
7020 @cindex delay slots, defining
7022 The insn attribute mechanism can be used to specify the requirements for
7023 delay slots, if any, on a target machine. An instruction is said to
7024 require a @dfn{delay slot} if some instructions that are physically
7025 after the instruction are executed as if they were located before it.
7026 Classic examples are branch and call instructions, which often execute
7027 the following instruction before the branch or call is performed.
7029 On some machines, conditional branch instructions can optionally
7030 @dfn{annul} instructions in the delay slot. This means that the
7031 instruction will not be executed for certain branch outcomes. Both
7032 instructions that annul if the branch is true and instructions that
7033 annul if the branch is false are supported.
7035 Delay slot scheduling differs from instruction scheduling in that
7036 determining whether an instruction needs a delay slot is dependent only
7037 on the type of instruction being generated, not on data flow between the
7038 instructions. See the next section for a discussion of data-dependent
7039 instruction scheduling.
7041 @findex define_delay
7042 The requirement of an insn needing one or more delay slots is indicated
7043 via the @code{define_delay} expression. It has the following form:
7046 (define_delay @var{test}
7047 [@var{delay-1} @var{annul-true-1} @var{annul-false-1}
7048 @var{delay-2} @var{annul-true-2} @var{annul-false-2}
7052 @var{test} is an attribute test that indicates whether this
7053 @code{define_delay} applies to a particular insn. If so, the number of
7054 required delay slots is determined by the length of the vector specified
7055 as the second argument. An insn placed in delay slot @var{n} must
7056 satisfy attribute test @var{delay-n}. @var{annul-true-n} is an
7057 attribute test that specifies which insns may be annulled if the branch
7058 is true. Similarly, @var{annul-false-n} specifies which insns in the
7059 delay slot may be annulled if the branch is false. If annulling is not
7060 supported for that delay slot, @code{(nil)} should be coded.
7062 For example, in the common case where branch and call insns require
7063 a single delay slot, which may contain any insn other than a branch or
7064 call, the following would be placed in the @file{md} file:
7067 (define_delay (eq_attr "type" "branch,call")
7068 [(eq_attr "type" "!branch,call") (nil) (nil)])
7071 Multiple @code{define_delay} expressions may be specified. In this
7072 case, each such expression specifies different delay slot requirements
7073 and there must be no insn for which tests in two @code{define_delay}
7074 expressions are both true.
7076 For example, if we have a machine that requires one delay slot for branches
7077 but two for calls, no delay slot can contain a branch or call insn,
7078 and any valid insn in the delay slot for the branch can be annulled if the
7079 branch is true, we might represent this as follows:
7082 (define_delay (eq_attr "type" "branch")
7083 [(eq_attr "type" "!branch,call")
7084 (eq_attr "type" "!branch,call")
7087 (define_delay (eq_attr "type" "call")
7088 [(eq_attr "type" "!branch,call") (nil) (nil)
7089 (eq_attr "type" "!branch,call") (nil) (nil)])
7091 @c the above is *still* too long. --mew 4feb93
7095 @node Processor pipeline description
7096 @subsection Specifying processor pipeline description
7097 @cindex processor pipeline description
7098 @cindex processor functional units
7099 @cindex instruction latency time
7100 @cindex interlock delays
7101 @cindex data dependence delays
7102 @cindex reservation delays
7103 @cindex pipeline hazard recognizer
7104 @cindex automaton based pipeline description
7105 @cindex regular expressions
7106 @cindex deterministic finite state automaton
7107 @cindex automaton based scheduler
7111 To achieve better performance, most modern processors
7112 (super-pipelined, superscalar @acronym{RISC}, and @acronym{VLIW}
7113 processors) have many @dfn{functional units} on which several
7114 instructions can be executed simultaneously. An instruction starts
7115 execution if its issue conditions are satisfied. If not, the
7116 instruction is stalled until its conditions are satisfied. Such
7117 @dfn{interlock (pipeline) delay} causes interruption of the fetching
7118 of successor instructions (or demands nop instructions, e.g.@: for some
7121 There are two major kinds of interlock delays in modern processors.
7122 The first one is a data dependence delay determining @dfn{instruction
7123 latency time}. The instruction execution is not started until all
7124 source data have been evaluated by prior instructions (there are more
7125 complex cases when the instruction execution starts even when the data
7126 are not available but will be ready in given time after the
7127 instruction execution start). Taking the data dependence delays into
7128 account is simple. The data dependence (true, output, and
7129 anti-dependence) delay between two instructions is given by a
7130 constant. In most cases this approach is adequate. The second kind
7131 of interlock delays is a reservation delay. The reservation delay
7132 means that two instructions under execution will be in need of shared
7133 processors resources, i.e.@: buses, internal registers, and/or
7134 functional units, which are reserved for some time. Taking this kind
7135 of delay into account is complex especially for modern @acronym{RISC}
7138 The task of exploiting more processor parallelism is solved by an
7139 instruction scheduler. For a better solution to this problem, the
7140 instruction scheduler has to have an adequate description of the
7141 processor parallelism (or @dfn{pipeline description}). GCC
7142 machine descriptions describe processor parallelism and functional
7143 unit reservations for groups of instructions with the aid of
7144 @dfn{regular expressions}.
7146 The GCC instruction scheduler uses a @dfn{pipeline hazard recognizer} to
7147 figure out the possibility of the instruction issue by the processor
7148 on a given simulated processor cycle. The pipeline hazard recognizer is
7149 automatically generated from the processor pipeline description. The
7150 pipeline hazard recognizer generated from the machine description
7151 is based on a deterministic finite state automaton (@acronym{DFA}):
7152 the instruction issue is possible if there is a transition from one
7153 automaton state to another one. This algorithm is very fast, and
7154 furthermore, its speed is not dependent on processor
7155 complexity@footnote{However, the size of the automaton depends on
7156 processor complexity. To limit this effect, machine descriptions
7157 can split orthogonal parts of the machine description among several
7158 automata: but then, since each of these must be stepped independently,
7159 this does cause a small decrease in the algorithm's performance.}.
7161 @cindex automaton based pipeline description
7162 The rest of this section describes the directives that constitute
7163 an automaton-based processor pipeline description. The order of
7164 these constructions within the machine description file is not
7167 @findex define_automaton
7168 @cindex pipeline hazard recognizer
7169 The following optional construction describes names of automata
7170 generated and used for the pipeline hazards recognition. Sometimes
7171 the generated finite state automaton used by the pipeline hazard
7172 recognizer is large. If we use more than one automaton and bind functional
7173 units to the automata, the total size of the automata is usually
7174 less than the size of the single automaton. If there is no one such
7175 construction, only one finite state automaton is generated.
7178 (define_automaton @var{automata-names})
7181 @var{automata-names} is a string giving names of the automata. The
7182 names are separated by commas. All the automata should have unique names.
7183 The automaton name is used in the constructions @code{define_cpu_unit} and
7184 @code{define_query_cpu_unit}.
7186 @findex define_cpu_unit
7187 @cindex processor functional units
7188 Each processor functional unit used in the description of instruction
7189 reservations should be described by the following construction.
7192 (define_cpu_unit @var{unit-names} [@var{automaton-name}])
7195 @var{unit-names} is a string giving the names of the functional units
7196 separated by commas. Don't use name @samp{nothing}, it is reserved
7199 @var{automaton-name} is a string giving the name of the automaton with
7200 which the unit is bound. The automaton should be described in
7201 construction @code{define_automaton}. You should give
7202 @dfn{automaton-name}, if there is a defined automaton.
7204 The assignment of units to automata are constrained by the uses of the
7205 units in insn reservations. The most important constraint is: if a
7206 unit reservation is present on a particular cycle of an alternative
7207 for an insn reservation, then some unit from the same automaton must
7208 be present on the same cycle for the other alternatives of the insn
7209 reservation. The rest of the constraints are mentioned in the
7210 description of the subsequent constructions.
7212 @findex define_query_cpu_unit
7213 @cindex querying function unit reservations
7214 The following construction describes CPU functional units analogously
7215 to @code{define_cpu_unit}. The reservation of such units can be
7216 queried for an automaton state. The instruction scheduler never
7217 queries reservation of functional units for given automaton state. So
7218 as a rule, you don't need this construction. This construction could
7219 be used for future code generation goals (e.g.@: to generate
7220 @acronym{VLIW} insn templates).
7223 (define_query_cpu_unit @var{unit-names} [@var{automaton-name}])
7226 @var{unit-names} is a string giving names of the functional units
7227 separated by commas.
7229 @var{automaton-name} is a string giving the name of the automaton with
7230 which the unit is bound.
7232 @findex define_insn_reservation
7233 @cindex instruction latency time
7234 @cindex regular expressions
7236 The following construction is the major one to describe pipeline
7237 characteristics of an instruction.
7240 (define_insn_reservation @var{insn-name} @var{default_latency}
7241 @var{condition} @var{regexp})
7244 @var{default_latency} is a number giving latency time of the
7245 instruction. There is an important difference between the old
7246 description and the automaton based pipeline description. The latency
7247 time is used for all dependencies when we use the old description. In
7248 the automaton based pipeline description, the given latency time is only
7249 used for true dependencies. The cost of anti-dependencies is always
7250 zero and the cost of output dependencies is the difference between
7251 latency times of the producing and consuming insns (if the difference
7252 is negative, the cost is considered to be zero). You can always
7253 change the default costs for any description by using the target hook
7254 @code{TARGET_SCHED_ADJUST_COST} (@pxref{Scheduling}).
7256 @var{insn-name} is a string giving the internal name of the insn. The
7257 internal names are used in constructions @code{define_bypass} and in
7258 the automaton description file generated for debugging. The internal
7259 name has nothing in common with the names in @code{define_insn}. It is a
7260 good practice to use insn classes described in the processor manual.
7262 @var{condition} defines what RTL insns are described by this
7263 construction. You should remember that you will be in trouble if
7264 @var{condition} for two or more different
7265 @code{define_insn_reservation} constructions is TRUE for an insn. In
7266 this case what reservation will be used for the insn is not defined.
7267 Such cases are not checked during generation of the pipeline hazards
7268 recognizer because in general recognizing that two conditions may have
7269 the same value is quite difficult (especially if the conditions
7270 contain @code{symbol_ref}). It is also not checked during the
7271 pipeline hazard recognizer work because it would slow down the
7272 recognizer considerably.
7274 @var{regexp} is a string describing the reservation of the cpu's functional
7275 units by the instruction. The reservations are described by a regular
7276 expression according to the following syntax:
7279 regexp = regexp "," oneof
7282 oneof = oneof "|" allof
7285 allof = allof "+" repeat
7288 repeat = element "*" number
7291 element = cpu_function_unit_name
7300 @samp{,} is used for describing the start of the next cycle in
7304 @samp{|} is used for describing a reservation described by the first
7305 regular expression @strong{or} a reservation described by the second
7306 regular expression @strong{or} etc.
7309 @samp{+} is used for describing a reservation described by the first
7310 regular expression @strong{and} a reservation described by the
7311 second regular expression @strong{and} etc.
7314 @samp{*} is used for convenience and simply means a sequence in which
7315 the regular expression are repeated @var{number} times with cycle
7316 advancing (see @samp{,}).
7319 @samp{cpu_function_unit_name} denotes reservation of the named
7323 @samp{reservation_name} --- see description of construction
7324 @samp{define_reservation}.
7327 @samp{nothing} denotes no unit reservations.
7330 @findex define_reservation
7331 Sometimes unit reservations for different insns contain common parts.
7332 In such case, you can simplify the pipeline description by describing
7333 the common part by the following construction
7336 (define_reservation @var{reservation-name} @var{regexp})
7339 @var{reservation-name} is a string giving name of @var{regexp}.
7340 Functional unit names and reservation names are in the same name
7341 space. So the reservation names should be different from the
7342 functional unit names and can not be the reserved name @samp{nothing}.
7344 @findex define_bypass
7345 @cindex instruction latency time
7347 The following construction is used to describe exceptions in the
7348 latency time for given instruction pair. This is so called bypasses.
7351 (define_bypass @var{number} @var{out_insn_names} @var{in_insn_names}
7355 @var{number} defines when the result generated by the instructions
7356 given in string @var{out_insn_names} will be ready for the
7357 instructions given in string @var{in_insn_names}. The instructions in
7358 the string are separated by commas.
7360 @var{guard} is an optional string giving the name of a C function which
7361 defines an additional guard for the bypass. The function will get the
7362 two insns as parameters. If the function returns zero the bypass will
7363 be ignored for this case. The additional guard is necessary to
7364 recognize complicated bypasses, e.g.@: when the consumer is only an address
7365 of insn @samp{store} (not a stored value).
7367 @findex exclusion_set
7368 @findex presence_set
7369 @findex final_presence_set
7371 @findex final_absence_set
7374 The following five constructions are usually used to describe
7375 @acronym{VLIW} processors, or more precisely, to describe a placement
7376 of small instructions into @acronym{VLIW} instruction slots. They
7377 can be used for @acronym{RISC} processors, too.
7380 (exclusion_set @var{unit-names} @var{unit-names})
7381 (presence_set @var{unit-names} @var{patterns})
7382 (final_presence_set @var{unit-names} @var{patterns})
7383 (absence_set @var{unit-names} @var{patterns})
7384 (final_absence_set @var{unit-names} @var{patterns})
7387 @var{unit-names} is a string giving names of functional units
7388 separated by commas.
7390 @var{patterns} is a string giving patterns of functional units
7391 separated by comma. Currently pattern is one unit or units
7392 separated by white-spaces.
7394 The first construction (@samp{exclusion_set}) means that each
7395 functional unit in the first string can not be reserved simultaneously
7396 with a unit whose name is in the second string and vice versa. For
7397 example, the construction is useful for describing processors
7398 (e.g.@: some SPARC processors) with a fully pipelined floating point
7399 functional unit which can execute simultaneously only single floating
7400 point insns or only double floating point insns.
7402 The second construction (@samp{presence_set}) means that each
7403 functional unit in the first string can not be reserved unless at
7404 least one of pattern of units whose names are in the second string is
7405 reserved. This is an asymmetric relation. For example, it is useful
7406 for description that @acronym{VLIW} @samp{slot1} is reserved after
7407 @samp{slot0} reservation. We could describe it by the following
7411 (presence_set "slot1" "slot0")
7414 Or @samp{slot1} is reserved only after @samp{slot0} and unit @samp{b0}
7415 reservation. In this case we could write
7418 (presence_set "slot1" "slot0 b0")
7421 The third construction (@samp{final_presence_set}) is analogous to
7422 @samp{presence_set}. The difference between them is when checking is
7423 done. When an instruction is issued in given automaton state
7424 reflecting all current and planned unit reservations, the automaton
7425 state is changed. The first state is a source state, the second one
7426 is a result state. Checking for @samp{presence_set} is done on the
7427 source state reservation, checking for @samp{final_presence_set} is
7428 done on the result reservation. This construction is useful to
7429 describe a reservation which is actually two subsequent reservations.
7430 For example, if we use
7433 (presence_set "slot1" "slot0")
7436 the following insn will be never issued (because @samp{slot1} requires
7437 @samp{slot0} which is absent in the source state).
7440 (define_reservation "insn_and_nop" "slot0 + slot1")
7443 but it can be issued if we use analogous @samp{final_presence_set}.
7445 The forth construction (@samp{absence_set}) means that each functional
7446 unit in the first string can be reserved only if each pattern of units
7447 whose names are in the second string is not reserved. This is an
7448 asymmetric relation (actually @samp{exclusion_set} is analogous to
7449 this one but it is symmetric). For example it might be useful in a
7450 @acronym{VLIW} description to say that @samp{slot0} cannot be reserved
7451 after either @samp{slot1} or @samp{slot2} have been reserved. This
7452 can be described as:
7455 (absence_set "slot0" "slot1, slot2")
7458 Or @samp{slot2} can not be reserved if @samp{slot0} and unit @samp{b0}
7459 are reserved or @samp{slot1} and unit @samp{b1} are reserved. In
7460 this case we could write
7463 (absence_set "slot2" "slot0 b0, slot1 b1")
7466 All functional units mentioned in a set should belong to the same
7469 The last construction (@samp{final_absence_set}) is analogous to
7470 @samp{absence_set} but checking is done on the result (state)
7471 reservation. See comments for @samp{final_presence_set}.
7473 @findex automata_option
7474 @cindex deterministic finite state automaton
7475 @cindex nondeterministic finite state automaton
7476 @cindex finite state automaton minimization
7477 You can control the generator of the pipeline hazard recognizer with
7478 the following construction.
7481 (automata_option @var{options})
7484 @var{options} is a string giving options which affect the generated
7485 code. Currently there are the following options:
7489 @dfn{no-minimization} makes no minimization of the automaton. This is
7490 only worth to do when we are debugging the description and need to
7491 look more accurately at reservations of states.
7494 @dfn{time} means printing time statistics about the generation of
7498 @dfn{stats} means printing statistics about the generated automata
7499 such as the number of DFA states, NDFA states and arcs.
7502 @dfn{v} means a generation of the file describing the result automata.
7503 The file has suffix @samp{.dfa} and can be used for the description
7504 verification and debugging.
7507 @dfn{w} means a generation of warning instead of error for
7508 non-critical errors.
7511 @dfn{ndfa} makes nondeterministic finite state automata. This affects
7512 the treatment of operator @samp{|} in the regular expressions. The
7513 usual treatment of the operator is to try the first alternative and,
7514 if the reservation is not possible, the second alternative. The
7515 nondeterministic treatment means trying all alternatives, some of them
7516 may be rejected by reservations in the subsequent insns.
7519 @dfn{progress} means output of a progress bar showing how many states
7520 were generated so far for automaton being processed. This is useful
7521 during debugging a @acronym{DFA} description. If you see too many
7522 generated states, you could interrupt the generator of the pipeline
7523 hazard recognizer and try to figure out a reason for generation of the
7527 As an example, consider a superscalar @acronym{RISC} machine which can
7528 issue three insns (two integer insns and one floating point insn) on
7529 the cycle but can finish only two insns. To describe this, we define
7530 the following functional units.
7533 (define_cpu_unit "i0_pipeline, i1_pipeline, f_pipeline")
7534 (define_cpu_unit "port0, port1")
7537 All simple integer insns can be executed in any integer pipeline and
7538 their result is ready in two cycles. The simple integer insns are
7539 issued into the first pipeline unless it is reserved, otherwise they
7540 are issued into the second pipeline. Integer division and
7541 multiplication insns can be executed only in the second integer
7542 pipeline and their results are ready correspondingly in 8 and 4
7543 cycles. The integer division is not pipelined, i.e.@: the subsequent
7544 integer division insn can not be issued until the current division
7545 insn finished. Floating point insns are fully pipelined and their
7546 results are ready in 3 cycles. Where the result of a floating point
7547 insn is used by an integer insn, an additional delay of one cycle is
7548 incurred. To describe all of this we could specify
7551 (define_cpu_unit "div")
7553 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
7554 "(i0_pipeline | i1_pipeline), (port0 | port1)")
7556 (define_insn_reservation "mult" 4 (eq_attr "type" "mult")
7557 "i1_pipeline, nothing*2, (port0 | port1)")
7559 (define_insn_reservation "div" 8 (eq_attr "type" "div")
7560 "i1_pipeline, div*7, div + (port0 | port1)")
7562 (define_insn_reservation "float" 3 (eq_attr "type" "float")
7563 "f_pipeline, nothing, (port0 | port1))
7565 (define_bypass 4 "float" "simple,mult,div")
7568 To simplify the description we could describe the following reservation
7571 (define_reservation "finish" "port0|port1")
7574 and use it in all @code{define_insn_reservation} as in the following
7578 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
7579 "(i0_pipeline | i1_pipeline), finish")
7585 @node Conditional Execution
7586 @section Conditional Execution
7587 @cindex conditional execution
7590 A number of architectures provide for some form of conditional
7591 execution, or predication. The hallmark of this feature is the
7592 ability to nullify most of the instructions in the instruction set.
7593 When the instruction set is large and not entirely symmetric, it
7594 can be quite tedious to describe these forms directly in the
7595 @file{.md} file. An alternative is the @code{define_cond_exec} template.
7597 @findex define_cond_exec
7600 [@var{predicate-pattern}]
7602 "@var{output-template}")
7605 @var{predicate-pattern} is the condition that must be true for the
7606 insn to be executed at runtime and should match a relational operator.
7607 One can use @code{match_operator} to match several relational operators
7608 at once. Any @code{match_operand} operands must have no more than one
7611 @var{condition} is a C expression that must be true for the generated
7614 @findex current_insn_predicate
7615 @var{output-template} is a string similar to the @code{define_insn}
7616 output template (@pxref{Output Template}), except that the @samp{*}
7617 and @samp{@@} special cases do not apply. This is only useful if the
7618 assembly text for the predicate is a simple prefix to the main insn.
7619 In order to handle the general case, there is a global variable
7620 @code{current_insn_predicate} that will contain the entire predicate
7621 if the current insn is predicated, and will otherwise be @code{NULL}.
7623 When @code{define_cond_exec} is used, an implicit reference to
7624 the @code{predicable} instruction attribute is made.
7625 @xref{Insn Attributes}. This attribute must be boolean (i.e.@: have
7626 exactly two elements in its @var{list-of-values}). Further, it must
7627 not be used with complex expressions. That is, the default and all
7628 uses in the insns must be a simple constant, not dependent on the
7629 alternative or anything else.
7631 For each @code{define_insn} for which the @code{predicable}
7632 attribute is true, a new @code{define_insn} pattern will be
7633 generated that matches a predicated version of the instruction.
7637 (define_insn "addsi"
7638 [(set (match_operand:SI 0 "register_operand" "r")
7639 (plus:SI (match_operand:SI 1 "register_operand" "r")
7640 (match_operand:SI 2 "register_operand" "r")))]
7645 [(ne (match_operand:CC 0 "register_operand" "c")
7652 generates a new pattern
7657 (ne (match_operand:CC 3 "register_operand" "c") (const_int 0))
7658 (set (match_operand:SI 0 "register_operand" "r")
7659 (plus:SI (match_operand:SI 1 "register_operand" "r")
7660 (match_operand:SI 2 "register_operand" "r"))))]
7661 "(@var{test2}) && (@var{test1})"
7662 "(%3) add %2,%1,%0")
7667 @node Constant Definitions
7668 @section Constant Definitions
7669 @cindex constant definitions
7670 @findex define_constants
7672 Using literal constants inside instruction patterns reduces legibility and
7673 can be a maintenance problem.
7675 To overcome this problem, you may use the @code{define_constants}
7676 expression. It contains a vector of name-value pairs. From that
7677 point on, wherever any of the names appears in the MD file, it is as
7678 if the corresponding value had been written instead. You may use
7679 @code{define_constants} multiple times; each appearance adds more
7680 constants to the table. It is an error to redefine a constant with
7683 To come back to the a29k load multiple example, instead of
7687 [(match_parallel 0 "load_multiple_operation"
7688 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
7689 (match_operand:SI 2 "memory_operand" "m"))
7691 (clobber (reg:SI 179))])]
7707 [(match_parallel 0 "load_multiple_operation"
7708 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
7709 (match_operand:SI 2 "memory_operand" "m"))
7711 (clobber (reg:SI R_CR))])]
7716 The constants that are defined with a define_constant are also output
7717 in the insn-codes.h header file as #defines.
7722 @cindex iterators in @file{.md} files
7724 Ports often need to define similar patterns for more than one machine
7725 mode or for more than one rtx code. GCC provides some simple iterator
7726 facilities to make this process easier.
7729 * Mode Iterators:: Generating variations of patterns for different modes.
7730 * Code Iterators:: Doing the same for codes.
7733 @node Mode Iterators
7734 @subsection Mode Iterators
7735 @cindex mode iterators in @file{.md} files
7737 Ports often need to define similar patterns for two or more different modes.
7742 If a processor has hardware support for both single and double
7743 floating-point arithmetic, the @code{SFmode} patterns tend to be
7744 very similar to the @code{DFmode} ones.
7747 If a port uses @code{SImode} pointers in one configuration and
7748 @code{DImode} pointers in another, it will usually have very similar
7749 @code{SImode} and @code{DImode} patterns for manipulating pointers.
7752 Mode iterators allow several patterns to be instantiated from one
7753 @file{.md} file template. They can be used with any type of
7754 rtx-based construct, such as a @code{define_insn},
7755 @code{define_split}, or @code{define_peephole2}.
7758 * Defining Mode Iterators:: Defining a new mode iterator.
7759 * Substitutions:: Combining mode iterators with substitutions
7760 * Examples:: Examples
7763 @node Defining Mode Iterators
7764 @subsubsection Defining Mode Iterators
7765 @findex define_mode_iterator
7767 The syntax for defining a mode iterator is:
7770 (define_mode_iterator @var{name} [(@var{mode1} "@var{cond1}") @dots{} (@var{moden} "@var{condn}")])
7773 This allows subsequent @file{.md} file constructs to use the mode suffix
7774 @code{:@var{name}}. Every construct that does so will be expanded
7775 @var{n} times, once with every use of @code{:@var{name}} replaced by
7776 @code{:@var{mode1}}, once with every use replaced by @code{:@var{mode2}},
7777 and so on. In the expansion for a particular @var{modei}, every
7778 C condition will also require that @var{condi} be true.
7783 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
7786 defines a new mode suffix @code{:P}. Every construct that uses
7787 @code{:P} will be expanded twice, once with every @code{:P} replaced
7788 by @code{:SI} and once with every @code{:P} replaced by @code{:DI}.
7789 The @code{:SI} version will only apply if @code{Pmode == SImode} and
7790 the @code{:DI} version will only apply if @code{Pmode == DImode}.
7792 As with other @file{.md} conditions, an empty string is treated
7793 as ``always true''. @code{(@var{mode} "")} can also be abbreviated
7794 to @code{@var{mode}}. For example:
7797 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
7800 means that the @code{:DI} expansion only applies if @code{TARGET_64BIT}
7801 but that the @code{:SI} expansion has no such constraint.
7803 Iterators are applied in the order they are defined. This can be
7804 significant if two iterators are used in a construct that requires
7805 substitutions. @xref{Substitutions}.
7808 @subsubsection Substitution in Mode Iterators
7809 @findex define_mode_attr
7811 If an @file{.md} file construct uses mode iterators, each version of the
7812 construct will often need slightly different strings or modes. For
7817 When a @code{define_expand} defines several @code{add@var{m}3} patterns
7818 (@pxref{Standard Names}), each expander will need to use the
7819 appropriate mode name for @var{m}.
7822 When a @code{define_insn} defines several instruction patterns,
7823 each instruction will often use a different assembler mnemonic.
7826 When a @code{define_insn} requires operands with different modes,
7827 using an iterator for one of the operand modes usually requires a specific
7828 mode for the other operand(s).
7831 GCC supports such variations through a system of ``mode attributes''.
7832 There are two standard attributes: @code{mode}, which is the name of
7833 the mode in lower case, and @code{MODE}, which is the same thing in
7834 upper case. You can define other attributes using:
7837 (define_mode_attr @var{name} [(@var{mode1} "@var{value1}") @dots{} (@var{moden} "@var{valuen}")])
7840 where @var{name} is the name of the attribute and @var{valuei}
7841 is the value associated with @var{modei}.
7843 When GCC replaces some @var{:iterator} with @var{:mode}, it will scan
7844 each string and mode in the pattern for sequences of the form
7845 @code{<@var{iterator}:@var{attr}>}, where @var{attr} is the name of a
7846 mode attribute. If the attribute is defined for @var{mode}, the whole
7847 @code{<@dots{}>} sequence will be replaced by the appropriate attribute
7850 For example, suppose an @file{.md} file has:
7853 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
7854 (define_mode_attr load [(SI "lw") (DI "ld")])
7857 If one of the patterns that uses @code{:P} contains the string
7858 @code{"<P:load>\t%0,%1"}, the @code{SI} version of that pattern
7859 will use @code{"lw\t%0,%1"} and the @code{DI} version will use
7862 Here is an example of using an attribute for a mode:
7865 (define_mode_iterator LONG [SI DI])
7866 (define_mode_attr SHORT [(SI "HI") (DI "SI")])
7867 (define_insn @dots{}
7868 (sign_extend:LONG (match_operand:<LONG:SHORT> @dots{})) @dots{})
7871 The @code{@var{iterator}:} prefix may be omitted, in which case the
7872 substitution will be attempted for every iterator expansion.
7875 @subsubsection Mode Iterator Examples
7877 Here is an example from the MIPS port. It defines the following
7878 modes and attributes (among others):
7881 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
7882 (define_mode_attr d [(SI "") (DI "d")])
7885 and uses the following template to define both @code{subsi3}
7889 (define_insn "sub<mode>3"
7890 [(set (match_operand:GPR 0 "register_operand" "=d")
7891 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
7892 (match_operand:GPR 2 "register_operand" "d")))]
7895 [(set_attr "type" "arith")
7896 (set_attr "mode" "<MODE>")])
7899 This is exactly equivalent to:
7902 (define_insn "subsi3"
7903 [(set (match_operand:SI 0 "register_operand" "=d")
7904 (minus:SI (match_operand:SI 1 "register_operand" "d")
7905 (match_operand:SI 2 "register_operand" "d")))]
7908 [(set_attr "type" "arith")
7909 (set_attr "mode" "SI")])
7911 (define_insn "subdi3"
7912 [(set (match_operand:DI 0 "register_operand" "=d")
7913 (minus:DI (match_operand:DI 1 "register_operand" "d")
7914 (match_operand:DI 2 "register_operand" "d")))]
7917 [(set_attr "type" "arith")
7918 (set_attr "mode" "DI")])
7921 @node Code Iterators
7922 @subsection Code Iterators
7923 @cindex code iterators in @file{.md} files
7924 @findex define_code_iterator
7925 @findex define_code_attr
7927 Code iterators operate in a similar way to mode iterators. @xref{Mode Iterators}.
7932 (define_code_iterator @var{name} [(@var{code1} "@var{cond1}") @dots{} (@var{coden} "@var{condn}")])
7935 defines a pseudo rtx code @var{name} that can be instantiated as
7936 @var{codei} if condition @var{condi} is true. Each @var{codei}
7937 must have the same rtx format. @xref{RTL Classes}.
7939 As with mode iterators, each pattern that uses @var{name} will be
7940 expanded @var{n} times, once with all uses of @var{name} replaced by
7941 @var{code1}, once with all uses replaced by @var{code2}, and so on.
7942 @xref{Defining Mode Iterators}.
7944 It is possible to define attributes for codes as well as for modes.
7945 There are two standard code attributes: @code{code}, the name of the
7946 code in lower case, and @code{CODE}, the name of the code in upper case.
7947 Other attributes are defined using:
7950 (define_code_attr @var{name} [(@var{code1} "@var{value1}") @dots{} (@var{coden} "@var{valuen}")])
7953 Here's an example of code iterators in action, taken from the MIPS port:
7956 (define_code_iterator any_cond [unordered ordered unlt unge uneq ltgt unle ungt
7957 eq ne gt ge lt le gtu geu ltu leu])
7959 (define_expand "b<code>"
7961 (if_then_else (any_cond:CC (cc0)
7963 (label_ref (match_operand 0 ""))
7967 gen_conditional_branch (operands, <CODE>);
7972 This is equivalent to:
7975 (define_expand "bunordered"
7977 (if_then_else (unordered:CC (cc0)
7979 (label_ref (match_operand 0 ""))
7983 gen_conditional_branch (operands, UNORDERED);
7987 (define_expand "bordered"
7989 (if_then_else (ordered:CC (cc0)
7991 (label_ref (match_operand 0 ""))
7995 gen_conditional_branch (operands, ORDERED);