1 @c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1996, 1998, 1999, 2000, 2001,
2 @c 2002, 2003, 2004 Free Software Foundation, Inc.
3 @c This is part of the GCC manual.
4 @c For copying conditions, see the file gcc.texi.
8 @chapter Machine Descriptions
9 @cindex machine descriptions
11 A machine description has two parts: a file of instruction patterns
12 (@file{.md} file) and a C header file of macro definitions.
14 The @file{.md} file for a target machine contains a pattern for each
15 instruction that the target machine supports (or at least each instruction
16 that is worth telling the compiler about). It may also contain comments.
17 A semicolon causes the rest of the line to be a comment, unless the semicolon
18 is inside a quoted string.
20 See the next chapter for information on the C header file.
23 * Overview:: How the machine description is used.
24 * Patterns:: How to write instruction patterns.
25 * Example:: An explained example of a @code{define_insn} pattern.
26 * RTL Template:: The RTL template defines what insns match a pattern.
27 * Output Template:: The output template says how to make assembler code
29 * Output Statement:: For more generality, write C code to output
31 * Predicates:: Controlling what kinds of operands can be used
33 * Constraints:: Fine-tuning operand selection.
34 * Standard Names:: Names mark patterns to use for code generation.
35 * Pattern Ordering:: When the order of patterns makes a difference.
36 * Dependent Patterns:: Having one pattern may make you need another.
37 * Jump Patterns:: Special considerations for patterns for jump insns.
38 * Looping Patterns:: How to define patterns for special looping insns.
39 * Insn Canonicalizations::Canonicalization of Instructions
40 * Expander Definitions::Generating a sequence of several RTL insns
41 for a standard operation.
42 * Insn Splitting:: Splitting Instructions into Multiple Instructions.
43 * Including Patterns:: Including Patterns in Machine Descriptions.
44 * Peephole Definitions::Defining machine-specific peephole optimizations.
45 * Insn Attributes:: Specifying the value of attributes for generated insns.
46 * Conditional Execution::Generating @code{define_insn} patterns for
48 * Constant Definitions::Defining symbolic constants that can be used in the
53 @section Overview of How the Machine Description is Used
55 There are three main conversions that happen in the compiler:
60 The front end reads the source code and builds a parse tree.
63 The parse tree is used to generate an RTL insn list based on named
67 The insn list is matched against the RTL templates to produce assembler
72 For the generate pass, only the names of the insns matter, from either a
73 named @code{define_insn} or a @code{define_expand}. The compiler will
74 choose the pattern with the right name and apply the operands according
75 to the documentation later in this chapter, without regard for the RTL
76 template or operand constraints. Note that the names the compiler looks
77 for are hard-coded in the compiler---it will ignore unnamed patterns and
78 patterns with names it doesn't know about, but if you don't provide a
79 named pattern it needs, it will abort.
81 If a @code{define_insn} is used, the template given is inserted into the
82 insn list. If a @code{define_expand} is used, one of three things
83 happens, based on the condition logic. The condition logic may manually
84 create new insns for the insn list, say via @code{emit_insn()}, and
85 invoke @code{DONE}. For certain named patterns, it may invoke @code{FAIL} to tell the
86 compiler to use an alternate way of performing that task. If it invokes
87 neither @code{DONE} nor @code{FAIL}, the template given in the pattern
88 is inserted, as if the @code{define_expand} were a @code{define_insn}.
90 Once the insn list is generated, various optimization passes convert,
91 replace, and rearrange the insns in the insn list. This is where the
92 @code{define_split} and @code{define_peephole} patterns get used, for
95 Finally, the insn list's RTL is matched up with the RTL templates in the
96 @code{define_insn} patterns, and those patterns are used to emit the
97 final assembly code. For this purpose, each named @code{define_insn}
98 acts like it's unnamed, since the names are ignored.
101 @section Everything about Instruction Patterns
103 @cindex instruction patterns
106 Each instruction pattern contains an incomplete RTL expression, with pieces
107 to be filled in later, operand constraints that restrict how the pieces can
108 be filled in, and an output pattern or C code to generate the assembler
109 output, all wrapped up in a @code{define_insn} expression.
111 A @code{define_insn} is an RTL expression containing four or five operands:
115 An optional name. The presence of a name indicate that this instruction
116 pattern can perform a certain standard job for the RTL-generation
117 pass of the compiler. This pass knows certain names and will use
118 the instruction patterns with those names, if the names are defined
119 in the machine description.
121 The absence of a name is indicated by writing an empty string
122 where the name should go. Nameless instruction patterns are never
123 used for generating RTL code, but they may permit several simpler insns
124 to be combined later on.
126 Names that are not thus known and used in RTL-generation have no
127 effect; they are equivalent to no name at all.
129 For the purpose of debugging the compiler, you may also specify a
130 name beginning with the @samp{*} character. Such a name is used only
131 for identifying the instruction in RTL dumps; it is entirely equivalent
132 to having a nameless pattern for all other purposes.
135 The @dfn{RTL template} (@pxref{RTL Template}) is a vector of incomplete
136 RTL expressions which show what the instruction should look like. It is
137 incomplete because it may contain @code{match_operand},
138 @code{match_operator}, and @code{match_dup} expressions that stand for
139 operands of the instruction.
141 If the vector has only one element, that element is the template for the
142 instruction pattern. If the vector has multiple elements, then the
143 instruction pattern is a @code{parallel} expression containing the
147 @cindex pattern conditions
148 @cindex conditions, in patterns
149 A condition. This is a string which contains a C expression that is
150 the final test to decide whether an insn body matches this pattern.
152 @cindex named patterns and conditions
153 For a named pattern, the condition (if present) may not depend on
154 the data in the insn being matched, but only the target-machine-type
155 flags. The compiler needs to test these conditions during
156 initialization in order to learn exactly which named instructions are
157 available in a particular run.
160 For nameless patterns, the condition is applied only when matching an
161 individual insn, and only after the insn has matched the pattern's
162 recognition template. The insn's operands may be found in the vector
163 @code{operands}. For an insn where the condition has once matched, it
164 can't be used to control register allocation, for example by excluding
165 certain hard registers or hard register combinations.
168 The @dfn{output template}: a string that says how to output matching
169 insns as assembler code. @samp{%} in this string specifies where
170 to substitute the value of an operand. @xref{Output Template}.
172 When simple substitution isn't general enough, you can specify a piece
173 of C code to compute the output. @xref{Output Statement}.
176 Optionally, a vector containing the values of attributes for insns matching
177 this pattern. @xref{Insn Attributes}.
181 @section Example of @code{define_insn}
182 @cindex @code{define_insn} example
184 Here is an actual example of an instruction pattern, for the 68000/68020.
189 (match_operand:SI 0 "general_operand" "rm"))]
193 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
195 return \"cmpl #0,%0\";
200 This can also be written using braced strings:
205 (match_operand:SI 0 "general_operand" "rm"))]
208 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
214 This is an instruction that sets the condition codes based on the value of
215 a general operand. It has no condition, so any insn whose RTL description
216 has the form shown may be handled according to this pattern. The name
217 @samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL generation
218 pass that, when it is necessary to test such a value, an insn to do so
219 can be constructed using this pattern.
221 The output control string is a piece of C code which chooses which
222 output template to return based on the kind of operand and the specific
223 type of CPU for which code is being generated.
225 @samp{"rm"} is an operand constraint. Its meaning is explained below.
228 @section RTL Template
229 @cindex RTL insn template
230 @cindex generating insns
231 @cindex insns, generating
232 @cindex recognizing insns
233 @cindex insns, recognizing
235 The RTL template is used to define which insns match the particular pattern
236 and how to find their operands. For named patterns, the RTL template also
237 says how to construct an insn from specified operands.
239 Construction involves substituting specified operands into a copy of the
240 template. Matching involves determining the values that serve as the
241 operands in the insn being matched. Both of these activities are
242 controlled by special expression types that direct matching and
243 substitution of the operands.
246 @findex match_operand
247 @item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint})
248 This expression is a placeholder for operand number @var{n} of
249 the insn. When constructing an insn, operand number @var{n}
250 will be substituted at this point. When matching an insn, whatever
251 appears at this position in the insn will be taken as operand
252 number @var{n}; but it must satisfy @var{predicate} or this instruction
253 pattern will not match at all.
255 Operand numbers must be chosen consecutively counting from zero in
256 each instruction pattern. There may be only one @code{match_operand}
257 expression in the pattern for each operand number. Usually operands
258 are numbered in the order of appearance in @code{match_operand}
259 expressions. In the case of a @code{define_expand}, any operand numbers
260 used only in @code{match_dup} expressions have higher values than all
261 other operand numbers.
263 @var{predicate} is a string that is the name of a function that
264 accepts two arguments, an expression and a machine mode.
265 @xref{Predicates}. During matching, the function will be called with
266 the putative operand as the expression and @var{m} as the mode
267 argument (if @var{m} is not specified, @code{VOIDmode} will be used,
268 which normally causes @var{predicate} to accept any mode). If it
269 returns zero, this instruction pattern fails to match.
270 @var{predicate} may be an empty string; then it means no test is to be
271 done on the operand, so anything which occurs in this position is
274 Most of the time, @var{predicate} will reject modes other than @var{m}---but
275 not always. For example, the predicate @code{address_operand} uses
276 @var{m} as the mode of memory ref that the address should be valid for.
277 Many predicates accept @code{const_int} nodes even though their mode is
280 @var{constraint} controls reloading and the choice of the best register
281 class to use for a value, as explained later (@pxref{Constraints}).
282 If the constraint would be an empty string, it can be omitted.
284 People are often unclear on the difference between the constraint and the
285 predicate. The predicate helps decide whether a given insn matches the
286 pattern. The constraint plays no role in this decision; instead, it
287 controls various decisions in the case of an insn which does match.
289 @findex match_scratch
290 @item (match_scratch:@var{m} @var{n} @var{constraint})
291 This expression is also a placeholder for operand number @var{n}
292 and indicates that operand must be a @code{scratch} or @code{reg}
295 When matching patterns, this is equivalent to
298 (match_operand:@var{m} @var{n} "scratch_operand" @var{pred})
301 but, when generating RTL, it produces a (@code{scratch}:@var{m})
304 If the last few expressions in a @code{parallel} are @code{clobber}
305 expressions whose operands are either a hard register or
306 @code{match_scratch}, the combiner can add or delete them when
307 necessary. @xref{Side Effects}.
310 @item (match_dup @var{n})
311 This expression is also a placeholder for operand number @var{n}.
312 It is used when the operand needs to appear more than once in the
315 In construction, @code{match_dup} acts just like @code{match_operand}:
316 the operand is substituted into the insn being constructed. But in
317 matching, @code{match_dup} behaves differently. It assumes that operand
318 number @var{n} has already been determined by a @code{match_operand}
319 appearing earlier in the recognition template, and it matches only an
320 identical-looking expression.
322 Note that @code{match_dup} should not be used to tell the compiler that
323 a particular register is being used for two operands (example:
324 @code{add} that adds one register to another; the second register is
325 both an input operand and the output operand). Use a matching
326 constraint (@pxref{Simple Constraints}) for those. @code{match_dup} is for the cases where one
327 operand is used in two places in the template, such as an instruction
328 that computes both a quotient and a remainder, where the opcode takes
329 two input operands but the RTL template has to refer to each of those
330 twice; once for the quotient pattern and once for the remainder pattern.
332 @findex match_operator
333 @item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}])
334 This pattern is a kind of placeholder for a variable RTL expression
337 When constructing an insn, it stands for an RTL expression whose
338 expression code is taken from that of operand @var{n}, and whose
339 operands are constructed from the patterns @var{operands}.
341 When matching an expression, it matches an expression if the function
342 @var{predicate} returns nonzero on that expression @emph{and} the
343 patterns @var{operands} match the operands of the expression.
345 Suppose that the function @code{commutative_operator} is defined as
346 follows, to match any expression whose operator is one of the
347 commutative arithmetic operators of RTL and whose mode is @var{mode}:
351 commutative_integer_operator (x, mode)
353 enum machine_mode mode;
355 enum rtx_code code = GET_CODE (x);
356 if (GET_MODE (x) != mode)
358 return (GET_RTX_CLASS (code) == RTX_COMM_ARITH
359 || code == EQ || code == NE);
363 Then the following pattern will match any RTL expression consisting
364 of a commutative operator applied to two general operands:
367 (match_operator:SI 3 "commutative_operator"
368 [(match_operand:SI 1 "general_operand" "g")
369 (match_operand:SI 2 "general_operand" "g")])
372 Here the vector @code{[@var{operands}@dots{}]} contains two patterns
373 because the expressions to be matched all contain two operands.
375 When this pattern does match, the two operands of the commutative
376 operator are recorded as operands 1 and 2 of the insn. (This is done
377 by the two instances of @code{match_operand}.) Operand 3 of the insn
378 will be the entire commutative expression: use @code{GET_CODE
379 (operands[3])} to see which commutative operator was used.
381 The machine mode @var{m} of @code{match_operator} works like that of
382 @code{match_operand}: it is passed as the second argument to the
383 predicate function, and that function is solely responsible for
384 deciding whether the expression to be matched ``has'' that mode.
386 When constructing an insn, argument 3 of the gen-function will specify
387 the operation (i.e.@: the expression code) for the expression to be
388 made. It should be an RTL expression, whose expression code is copied
389 into a new expression whose operands are arguments 1 and 2 of the
390 gen-function. The subexpressions of argument 3 are not used;
391 only its expression code matters.
393 When @code{match_operator} is used in a pattern for matching an insn,
394 it usually best if the operand number of the @code{match_operator}
395 is higher than that of the actual operands of the insn. This improves
396 register allocation because the register allocator often looks at
397 operands 1 and 2 of insns to see if it can do register tying.
399 There is no way to specify constraints in @code{match_operator}. The
400 operand of the insn which corresponds to the @code{match_operator}
401 never has any constraints because it is never reloaded as a whole.
402 However, if parts of its @var{operands} are matched by
403 @code{match_operand} patterns, those parts may have constraints of
407 @item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}])
408 Like @code{match_dup}, except that it applies to operators instead of
409 operands. When constructing an insn, operand number @var{n} will be
410 substituted at this point. But in matching, @code{match_op_dup} behaves
411 differently. It assumes that operand number @var{n} has already been
412 determined by a @code{match_operator} appearing earlier in the
413 recognition template, and it matches only an identical-looking
416 @findex match_parallel
417 @item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}])
418 This pattern is a placeholder for an insn that consists of a
419 @code{parallel} expression with a variable number of elements. This
420 expression should only appear at the top level of an insn pattern.
422 When constructing an insn, operand number @var{n} will be substituted at
423 this point. When matching an insn, it matches if the body of the insn
424 is a @code{parallel} expression with at least as many elements as the
425 vector of @var{subpat} expressions in the @code{match_parallel}, if each
426 @var{subpat} matches the corresponding element of the @code{parallel},
427 @emph{and} the function @var{predicate} returns nonzero on the
428 @code{parallel} that is the body of the insn. It is the responsibility
429 of the predicate to validate elements of the @code{parallel} beyond
430 those listed in the @code{match_parallel}.
432 A typical use of @code{match_parallel} is to match load and store
433 multiple expressions, which can contain a variable number of elements
434 in a @code{parallel}. For example,
438 [(match_parallel 0 "load_multiple_operation"
439 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
440 (match_operand:SI 2 "memory_operand" "m"))
442 (clobber (reg:SI 179))])]
447 This example comes from @file{a29k.md}. The function
448 @code{load_multiple_operation} is defined in @file{a29k.c} and checks
449 that subsequent elements in the @code{parallel} are the same as the
450 @code{set} in the pattern, except that they are referencing subsequent
451 registers and memory locations.
453 An insn that matches this pattern might look like:
457 [(set (reg:SI 20) (mem:SI (reg:SI 100)))
459 (clobber (reg:SI 179))
461 (mem:SI (plus:SI (reg:SI 100)
464 (mem:SI (plus:SI (reg:SI 100)
468 @findex match_par_dup
469 @item (match_par_dup @var{n} [@var{subpat}@dots{}])
470 Like @code{match_op_dup}, but for @code{match_parallel} instead of
471 @code{match_operator}.
475 @node Output Template
476 @section Output Templates and Operand Substitution
477 @cindex output templates
478 @cindex operand substitution
480 @cindex @samp{%} in template
482 The @dfn{output template} is a string which specifies how to output the
483 assembler code for an instruction pattern. Most of the template is a
484 fixed string which is output literally. The character @samp{%} is used
485 to specify where to substitute an operand; it can also be used to
486 identify places where different variants of the assembler require
489 In the simplest case, a @samp{%} followed by a digit @var{n} says to output
490 operand @var{n} at that point in the string.
492 @samp{%} followed by a letter and a digit says to output an operand in an
493 alternate fashion. Four letters have standard, built-in meanings described
494 below. The machine description macro @code{PRINT_OPERAND} can define
495 additional letters with nonstandard meanings.
497 @samp{%c@var{digit}} can be used to substitute an operand that is a
498 constant value without the syntax that normally indicates an immediate
501 @samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of
502 the constant is negated before printing.
504 @samp{%a@var{digit}} can be used to substitute an operand as if it were a
505 memory reference, with the actual operand treated as the address. This may
506 be useful when outputting a ``load address'' instruction, because often the
507 assembler syntax for such an instruction requires you to write the operand
508 as if it were a memory reference.
510 @samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump
513 @samp{%=} outputs a number which is unique to each instruction in the
514 entire compilation. This is useful for making local labels to be
515 referred to more than once in a single template that generates multiple
516 assembler instructions.
518 @samp{%} followed by a punctuation character specifies a substitution that
519 does not use an operand. Only one case is standard: @samp{%%} outputs a
520 @samp{%} into the assembler code. Other nonstandard cases can be
521 defined in the @code{PRINT_OPERAND} macro. You must also define
522 which punctuation characters are valid with the
523 @code{PRINT_OPERAND_PUNCT_VALID_P} macro.
527 The template may generate multiple assembler instructions. Write the text
528 for the instructions, with @samp{\;} between them.
530 @cindex matching operands
531 When the RTL contains two operands which are required by constraint to match
532 each other, the output template must refer only to the lower-numbered operand.
533 Matching operands are not always identical, and the rest of the compiler
534 arranges to put the proper RTL expression for printing into the lower-numbered
537 One use of nonstandard letters or punctuation following @samp{%} is to
538 distinguish between different assembler languages for the same machine; for
539 example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax
540 requires periods in most opcode names, while MIT syntax does not. For
541 example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola
542 syntax. The same file of patterns is used for both kinds of output syntax,
543 but the character sequence @samp{%.} is used in each place where Motorola
544 syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax
545 defines the sequence to output a period; the macro for MIT syntax defines
548 @cindex @code{#} in template
549 As a special case, a template consisting of the single character @code{#}
550 instructs the compiler to first split the insn, and then output the
551 resulting instructions separately. This helps eliminate redundancy in the
552 output templates. If you have a @code{define_insn} that needs to emit
553 multiple assembler instructions, and there is an matching @code{define_split}
554 already defined, then you can simply use @code{#} as the output template
555 instead of writing an output template that emits the multiple assembler
558 If the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct
559 of the form @samp{@{option0|option1|option2@}} in the templates. These
560 describe multiple variants of assembler language syntax.
561 @xref{Instruction Output}.
563 @node Output Statement
564 @section C Statements for Assembler Output
565 @cindex output statements
566 @cindex C statements for assembler output
567 @cindex generating assembler output
569 Often a single fixed template string cannot produce correct and efficient
570 assembler code for all the cases that are recognized by a single
571 instruction pattern. For example, the opcodes may depend on the kinds of
572 operands; or some unfortunate combinations of operands may require extra
573 machine instructions.
575 If the output control string starts with a @samp{@@}, then it is actually
576 a series of templates, each on a separate line. (Blank lines and
577 leading spaces and tabs are ignored.) The templates correspond to the
578 pattern's constraint alternatives (@pxref{Multi-Alternative}). For example,
579 if a target machine has a two-address add instruction @samp{addr} to add
580 into a register and another @samp{addm} to add a register to memory, you
581 might write this pattern:
584 (define_insn "addsi3"
585 [(set (match_operand:SI 0 "general_operand" "=r,m")
586 (plus:SI (match_operand:SI 1 "general_operand" "0,0")
587 (match_operand:SI 2 "general_operand" "g,r")))]
594 @cindex @code{*} in template
595 @cindex asterisk in template
596 If the output control string starts with a @samp{*}, then it is not an
597 output template but rather a piece of C program that should compute a
598 template. It should execute a @code{return} statement to return the
599 template-string you want. Most such templates use C string literals, which
600 require doublequote characters to delimit them. To include these
601 doublequote characters in the string, prefix each one with @samp{\}.
603 If the output control string is written as a brace block instead of a
604 double-quoted string, it is automatically assumed to be C code. In that
605 case, it is not necessary to put in a leading asterisk, or to escape the
606 doublequotes surrounding C string literals.
608 The operands may be found in the array @code{operands}, whose C data type
611 It is very common to select different ways of generating assembler code
612 based on whether an immediate operand is within a certain range. Be
613 careful when doing this, because the result of @code{INTVAL} is an
614 integer on the host machine. If the host machine has more bits in an
615 @code{int} than the target machine has in the mode in which the constant
616 will be used, then some of the bits you get from @code{INTVAL} will be
617 superfluous. For proper results, you must carefully disregard the
618 values of those bits.
620 @findex output_asm_insn
621 It is possible to output an assembler instruction and then go on to output
622 or compute more of them, using the subroutine @code{output_asm_insn}. This
623 receives two arguments: a template-string and a vector of operands. The
624 vector may be @code{operands}, or it may be another array of @code{rtx}
625 that you declare locally and initialize yourself.
627 @findex which_alternative
628 When an insn pattern has multiple alternatives in its constraints, often
629 the appearance of the assembler code is determined mostly by which alternative
630 was matched. When this is so, the C code can test the variable
631 @code{which_alternative}, which is the ordinal number of the alternative
632 that was actually satisfied (0 for the first, 1 for the second alternative,
635 For example, suppose there are two opcodes for storing zero, @samp{clrreg}
636 for registers and @samp{clrmem} for memory locations. Here is how
637 a pattern could use @code{which_alternative} to choose between them:
641 [(set (match_operand:SI 0 "general_operand" "=r,m")
645 return (which_alternative == 0
646 ? "clrreg %0" : "clrmem %0");
650 The example above, where the assembler code to generate was
651 @emph{solely} determined by the alternative, could also have been specified
652 as follows, having the output control string start with a @samp{@@}:
657 [(set (match_operand:SI 0 "general_operand" "=r,m")
669 @cindex operand predicates
670 @cindex operator predicates
672 A predicate determines whether a @code{match_operand} or
673 @code{match_operator} expression matches, and therefore whether the
674 surrounding instruction pattern will be used for that combination of
675 operands. GCC has a number of machine-independent predicates, and you
676 can define machine-specific predicates as needed. By convention,
677 predicates used with @code{match_operand} have names that end in
678 @samp{_operand}, and those used with @code{match_operator} have names
679 that end in @samp{_operator}.
681 All predicates are Boolean functions (in the mathematical sense) of
682 two arguments: the RTL expression that is being considered at that
683 position in the instruction pattern, and the machine mode that the
684 @code{match_operand} or @code{match_operator} specifies. In this
685 section, the first argument is called @var{op} and the second argument
686 @var{mode}. Predicates can be called from C as ordinary two-argument
687 functions; this can be useful in output templates or other
688 machine-specific code.
690 Operand predicates can allow operands that are not actually acceptable
691 to the hardware, as long as the constraints give reload the ability to
692 fix them up (@pxref{Constraints}). However, GCC will usually generate
693 better code if the predicates specify the requirements of the machine
694 instructions as closely as possible. Reload cannot fix up operands
695 that must be constants (``immediate operands''); you must use a
696 predicate that allows only constants, or else enforce the requirement
697 in the extra condition.
699 @cindex predicates and machine modes
700 @cindex normal predicates
701 @cindex special predicates
702 Most predicates handle their @var{mode} argument in a uniform manner.
703 If @var{mode} is @code{VOIDmode} (unspecified), then @var{op} can have
704 any mode. If @var{mode} is anything else, then @var{op} must have the
705 same mode, unless @var{op} is a @code{CONST_INT} or integer
706 @code{CONST_DOUBLE}. These RTL expressions always have
707 @code{VOIDmode}, so it would be counterproductive to check that their
708 mode matches. Instead, predicates that accept @code{CONST_INT} and/or
709 integer @code{CONST_DOUBLE} check that the value stored in the
710 constant will fit in the requested mode.
712 Predicates with this behavior are called @dfn{normal}.
713 @command{genrecog} can optimize the instruction recognizer based on
714 knowledge of how normal predicates treat modes. It can also diagnose
715 certain kinds of common errors in the use of normal predicates; for
716 instance, it is almost always an error to use a normal predicate
717 without specifying a mode.
719 Predicates that do something different with their @var{mode} argument
720 are called @dfn{special}. The generic predicates
721 @code{address_operand} and @code{pmode_register_operand} are special
722 predicates. @command{genrecog} does not do any optimizations or
723 diagnosis when special predicates are used.
726 * Machine-Independent Predicates:: Predicates available to all back ends.
727 * Defining Predicates:: How to write machine-specific predicate
731 @node Machine-Independent Predicates
732 @subsection Machine-Independent Predicates
733 @cindex machine-independent predicates
734 @cindex generic predicates
736 These are the generic predicates available to all back ends. They are
737 defined in @file{recog.c}. The first category of predicates allow
738 only constant, or @dfn{immediate}, operands.
740 @defun immediate_operand
741 This predicate allows any sort of constant that fits in @var{mode}.
742 It is an appropriate choice for instructions that take operands that
746 @defun const_int_operand
747 This predicate allows any @code{CONST_INT} expression that fits in
748 @var{mode}. It is an appropriate choice for an immediate operand that
749 does not allow a symbol or label.
752 @defun const_double_operand
753 This predicate accepts any @code{CONST_DOUBLE} expression that has
754 exactly @var{mode}. If @var{mode} is @code{VOIDmode}, it will also
755 accept @code{CONST_INT}. It is intended for immediate floating point
760 The second category of predicates allow only some kind of machine
763 @defun register_operand
764 This predicate allows any @code{REG} or @code{SUBREG} expression that
765 is valid for @var{mode}. It is often suitable for arithmetic
766 instruction operands on a RISC machine.
769 @defun pmode_register_operand
770 This is a slight variant on @code{register_operand} which works around
771 a limitation in the machine-description reader.
774 (match_operand @var{n} "pmode_register_operand" @var{constraint})
781 (match_operand:P @var{n} "register_operand" @var{constraint})
785 would mean, if the machine-description reader accepted @samp{:P}
786 mode suffixes. Unfortunately, it cannot, because @code{Pmode} is an
787 alias for some other mode, and might vary with machine-specific
788 options. @xref{Misc}.
791 @defun scratch_operand
792 This predicate allows hard registers and @code{SCRATCH} expressions,
793 but not pseudo-registers. It is used internally by @code{match_scratch};
794 it should not be used directly.
798 The third category of predicates allow only some kind of memory reference.
800 @defun memory_operand
801 This predicate allows any valid reference to a quantity of mode
802 @var{mode} in memory, as determined by the weak form of
803 @code{GO_IF_LEGITIMATE_ADDRESS} (@pxref{Addressing Modes}).
806 @defun address_operand
807 This predicate is a little unusual; it allows any operand that is a
808 valid expression for the @emph{address} of a quantity of mode
809 @var{mode}, again determined by the weak form of
810 @code{GO_IF_LEGITIMATE_ADDRESS}. To first order, if
811 @samp{@w{(mem:@var{mode} (@var{exp}))}} is acceptable to
812 @code{memory_operand}, then @var{exp} is acceptable to
813 @code{address_operand}. Note that @var{exp} does not necessarily have
817 @defun indirect_operand
818 This is a stricter form of @code{memory_operand} which allows only
819 memory references with a @code{general_operand} as the address
820 expression. New uses of this predicate are discouraged, because
821 @code{general_operand} is very permissive, so it's hard to tell what
822 an @code{indirect_operand} does or does not allow. If a target has
823 different requirements for memory operands for different instructions,
824 it is better to define target-specific predicates which enforce the
825 hardware's requirements explicitly.
829 This predicate allows a memory reference suitable for pushing a value
830 onto the stack. This will be a @code{MEM} which refers to
831 @code{stack_pointer_rtx}, with a side-effect in its address expression
832 (@pxref{Incdec}); which one is determined by the
833 @code{STACK_PUSH_CODE} macro (@pxref{Frame Layout}).
837 This predicate allows a memory reference suitable for popping a value
838 off the stack. Again, this will be a @code{MEM} referring to
839 @code{stack_pointer_rtx}, with a side-effect in its address
840 expression. However, this time @code{STACK_POP_CODE} is expected.
844 The fourth category of predicates allow some combination of the above
847 @defun nonmemory_operand
848 This predicate allows any immediate or register operand valid for @var{mode}.
851 @defun nonimmediate_operand
852 This predicate allows any register or memory operand valid for @var{mode}.
855 @defun general_operand
856 This predicate allows any immediate, register, or memory operand
857 valid for @var{mode}.
861 Finally, there is one generic operator predicate.
863 @defun comparison_operator
864 This predicate matches any expression which performs an arithmetic
865 comparison in @var{mode}; that is, @code{COMPARISON_P} is true for the
869 @node Defining Predicates
870 @subsection Defining Machine-Specific Predicates
871 @cindex defining predicates
872 @findex define_predicate
873 @findex define_special_predicate
875 Many machines have requirements for their operands that cannot be
876 expressed precisely using the generic predicates. You can define
877 additional predicates using @code{define_predicate} and
878 @code{define_special_predicate} expressions. These expressions have
883 The name of the predicate, as it will be referred to in
884 @code{match_operand} or @code{match_operator} expressions.
887 An RTL expression which evaluates to true if the predicate allows the
888 operand @var{op}, false if it does not. This expression can only use
889 the following RTL codes:
893 When written inside a predicate expression, a @code{MATCH_OPERAND}
894 expression evaluates to true if the predicate it names would allow
895 @var{op}. The operand number and constraint are ignored. Due to
896 limitations in @command{genrecog}, you can only refer to generic
897 predicates and predicates that have already been defined.
900 This expression has one operand, a string constant containing a
901 comma-separated list of RTX code names (in lower case). It evaluates
902 to true if @var{op} has any of the listed codes.
905 This expression has one operand, a string constant containing a C
906 expression. The predicate's arguments, @var{op} and @var{mode}, are
907 available with those names in the C expression. The @code{MATCH_TEST}
908 evaluates to true if the C expression evaluates to a nonzero value.
909 @code{MATCH_TEST} expressions must not have side effects.
915 The basic @samp{MATCH_} expressions can be combined using these
916 logical operators, which have the semantics of the C operators
917 @samp{&&}, @samp{||}, @samp{!}, and @samp{@w{? :}} respectively.
921 An optional block of C code, which should execute
922 @samp{@w{return true}} if the predicate is found to match and
923 @samp{@w{return false}} if it does not. It must not have any side
924 effects. The predicate arguments, @var{op} and @var{mode}, are
925 available with those names.
927 If a code block is present in a predicate definition, then the RTL
928 expression must evaluate to true @emph{and} the code block must
929 execute @samp{@w{return true}} for the predicate to allow the operand.
930 The RTL expression is evaluated first; do not re-check anything in the
931 code block that was checked in the RTL expression.
934 The program @command{genrecog} scans @code{define_predicate} and
935 @code{define_special_predicate} expressions to determine which RTX
936 codes are possibly allowed. You should always make this explicit in
937 the RTL predicate expression, using @code{MATCH_OPERAND} and
940 Here is an example of a simple predicate definition, from the IA64
945 ;; @r{True if @var{op} is a @code{SYMBOL_REF} which refers to the sdata section.}
946 (define_predicate "small_addr_symbolic_operand"
947 (and (match_code "symbol_ref")
948 (match_test "SYMBOL_REF_SMALL_ADDR_P (op)")))
953 And here is another, showing the use of the C block.
957 ;; @r{True if @var{op} is a register operand that is (or could be) a GR reg.}
958 (define_predicate "gr_register_operand"
959 (match_operand 0 "register_operand")
962 if (GET_CODE (op) == SUBREG)
963 op = SUBREG_REG (op);
966 return (regno >= FIRST_PSEUDO_REGISTER || GENERAL_REGNO_P (regno));
971 Predicates written with @code{define_predicate} automatically include
972 a test that @var{mode} is @code{VOIDmode}, or @var{op} has the same
973 mode as @var{mode}, or @var{op} is a @code{CONST_INT} or
974 @code{CONST_DOUBLE}. They do @emph{not} check specifically for
975 integer @code{CONST_DOUBLE}, nor do they test that the value of either
976 kind of constant fits in the requested mode. This is because
977 target-specific predicates that take constants usually have to do more
978 stringent value checks anyway. If you need the exact same treatment
979 of @code{CONST_INT} or @code{CONST_DOUBLE} that the generic predicates
980 provide, use a @code{MATCH_OPERAND} subexpression to call
981 @code{const_int_operand}, @code{const_double_operand}, or
982 @code{immediate_operand}.
984 Predicates written with @code{define_special_predicate} do not get any
985 automatic mode checks, and are treated as having special mode handling
986 by @command{genrecog}.
988 The program @command{genpreds} is responsible for generating code to
989 test predicates. It also writes a header file containing function
990 declarations for all machine-specific predicates. It is not necessary
991 to declare these predicates in @file{@var{cpu}-protos.h}.
994 @c Most of this node appears by itself (in a different place) even
995 @c when the INTERNALS flag is clear. Passages that require the internals
996 @c manual's context are conditionalized to appear only in the internals manual.
999 @section Operand Constraints
1000 @cindex operand constraints
1003 Each @code{match_operand} in an instruction pattern can specify
1004 constraints for the operands allowed. The constraints allow you to
1005 fine-tune matching within the set of operands allowed by the
1011 @section Constraints for @code{asm} Operands
1012 @cindex operand constraints, @code{asm}
1013 @cindex constraints, @code{asm}
1014 @cindex @code{asm} constraints
1016 Here are specific details on what constraint letters you can use with
1017 @code{asm} operands.
1019 Constraints can say whether
1020 an operand may be in a register, and which kinds of register; whether the
1021 operand can be a memory reference, and which kinds of address; whether the
1022 operand may be an immediate constant, and which possible values it may
1023 have. Constraints can also require two operands to match.
1027 * Simple Constraints:: Basic use of constraints.
1028 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1029 * Class Preferences:: Constraints guide which hard register to put things in.
1030 * Modifiers:: More precise control over effects of constraints.
1031 * Machine Constraints:: Existing constraints for some particular machines.
1037 * Simple Constraints:: Basic use of constraints.
1038 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1039 * Modifiers:: More precise control over effects of constraints.
1040 * Machine Constraints:: Special constraints for some particular machines.
1044 @node Simple Constraints
1045 @subsection Simple Constraints
1046 @cindex simple constraints
1048 The simplest kind of constraint is a string full of letters, each of
1049 which describes one kind of operand that is permitted. Here are
1050 the letters that are allowed:
1054 Whitespace characters are ignored and can be inserted at any position
1055 except the first. This enables each alternative for different operands to
1056 be visually aligned in the machine description even if they have different
1057 number of constraints and modifiers.
1059 @cindex @samp{m} in constraint
1060 @cindex memory references in constraints
1062 A memory operand is allowed, with any kind of address that the machine
1063 supports in general.
1065 @cindex offsettable address
1066 @cindex @samp{o} in constraint
1068 A memory operand is allowed, but only if the address is
1069 @dfn{offsettable}. This means that adding a small integer (actually,
1070 the width in bytes of the operand, as determined by its machine mode)
1071 may be added to the address and the result is also a valid memory
1074 @cindex autoincrement/decrement addressing
1075 For example, an address which is constant is offsettable; so is an
1076 address that is the sum of a register and a constant (as long as a
1077 slightly larger constant is also within the range of address-offsets
1078 supported by the machine); but an autoincrement or autodecrement
1079 address is not offsettable. More complicated indirect/indexed
1080 addresses may or may not be offsettable depending on the other
1081 addressing modes that the machine supports.
1083 Note that in an output operand which can be matched by another
1084 operand, the constraint letter @samp{o} is valid only when accompanied
1085 by both @samp{<} (if the target machine has predecrement addressing)
1086 and @samp{>} (if the target machine has preincrement addressing).
1088 @cindex @samp{V} in constraint
1090 A memory operand that is not offsettable. In other words, anything that
1091 would fit the @samp{m} constraint but not the @samp{o} constraint.
1093 @cindex @samp{<} in constraint
1095 A memory operand with autodecrement addressing (either predecrement or
1096 postdecrement) is allowed.
1098 @cindex @samp{>} in constraint
1100 A memory operand with autoincrement addressing (either preincrement or
1101 postincrement) is allowed.
1103 @cindex @samp{r} in constraint
1104 @cindex registers in constraints
1106 A register operand is allowed provided that it is in a general
1109 @cindex constants in constraints
1110 @cindex @samp{i} in constraint
1112 An immediate integer operand (one with constant value) is allowed.
1113 This includes symbolic constants whose values will be known only at
1114 assembly time or later.
1116 @cindex @samp{n} in constraint
1118 An immediate integer operand with a known numeric value is allowed.
1119 Many systems cannot support assembly-time constants for operands less
1120 than a word wide. Constraints for these operands should use @samp{n}
1121 rather than @samp{i}.
1123 @cindex @samp{I} in constraint
1124 @item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P}
1125 Other letters in the range @samp{I} through @samp{P} may be defined in
1126 a machine-dependent fashion to permit immediate integer operands with
1127 explicit integer values in specified ranges. For example, on the
1128 68000, @samp{I} is defined to stand for the range of values 1 to 8.
1129 This is the range permitted as a shift count in the shift
1132 @cindex @samp{E} in constraint
1134 An immediate floating operand (expression code @code{const_double}) is
1135 allowed, but only if the target floating point format is the same as
1136 that of the host machine (on which the compiler is running).
1138 @cindex @samp{F} in constraint
1140 An immediate floating operand (expression code @code{const_double} or
1141 @code{const_vector}) is allowed.
1143 @cindex @samp{G} in constraint
1144 @cindex @samp{H} in constraint
1145 @item @samp{G}, @samp{H}
1146 @samp{G} and @samp{H} may be defined in a machine-dependent fashion to
1147 permit immediate floating operands in particular ranges of values.
1149 @cindex @samp{s} in constraint
1151 An immediate integer operand whose value is not an explicit integer is
1154 This might appear strange; if an insn allows a constant operand with a
1155 value not known at compile time, it certainly must allow any known
1156 value. So why use @samp{s} instead of @samp{i}? Sometimes it allows
1157 better code to be generated.
1159 For example, on the 68000 in a fullword instruction it is possible to
1160 use an immediate operand; but if the immediate value is between @minus{}128
1161 and 127, better code results from loading the value into a register and
1162 using the register. This is because the load into the register can be
1163 done with a @samp{moveq} instruction. We arrange for this to happen
1164 by defining the letter @samp{K} to mean ``any integer outside the
1165 range @minus{}128 to 127'', and then specifying @samp{Ks} in the operand
1168 @cindex @samp{g} in constraint
1170 Any register, memory or immediate integer operand is allowed, except for
1171 registers that are not general registers.
1173 @cindex @samp{X} in constraint
1176 Any operand whatsoever is allowed, even if it does not satisfy
1177 @code{general_operand}. This is normally used in the constraint of
1178 a @code{match_scratch} when certain alternatives will not actually
1179 require a scratch register.
1182 Any operand whatsoever is allowed.
1185 @cindex @samp{0} in constraint
1186 @cindex digits in constraint
1187 @item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9}
1188 An operand that matches the specified operand number is allowed. If a
1189 digit is used together with letters within the same alternative, the
1190 digit should come last.
1192 This number is allowed to be more than a single digit. If multiple
1193 digits are encountered consecutively, they are interpreted as a single
1194 decimal integer. There is scant chance for ambiguity, since to-date
1195 it has never been desirable that @samp{10} be interpreted as matching
1196 either operand 1 @emph{or} operand 0. Should this be desired, one
1197 can use multiple alternatives instead.
1199 @cindex matching constraint
1200 @cindex constraint, matching
1201 This is called a @dfn{matching constraint} and what it really means is
1202 that the assembler has only a single operand that fills two roles
1204 considered separate in the RTL insn. For example, an add insn has two
1205 input operands and one output operand in the RTL, but on most CISC
1208 which @code{asm} distinguishes. For example, an add instruction uses
1209 two input operands and an output operand, but on most CISC
1211 machines an add instruction really has only two operands, one of them an
1212 input-output operand:
1218 Matching constraints are used in these circumstances.
1219 More precisely, the two operands that match must include one input-only
1220 operand and one output-only operand. Moreover, the digit must be a
1221 smaller number than the number of the operand that uses it in the
1225 For operands to match in a particular case usually means that they
1226 are identical-looking RTL expressions. But in a few special cases
1227 specific kinds of dissimilarity are allowed. For example, @code{*x}
1228 as an input operand will match @code{*x++} as an output operand.
1229 For proper results in such cases, the output template should always
1230 use the output-operand's number when printing the operand.
1233 @cindex load address instruction
1234 @cindex push address instruction
1235 @cindex address constraints
1236 @cindex @samp{p} in constraint
1238 An operand that is a valid memory address is allowed. This is
1239 for ``load address'' and ``push address'' instructions.
1241 @findex address_operand
1242 @samp{p} in the constraint must be accompanied by @code{address_operand}
1243 as the predicate in the @code{match_operand}. This predicate interprets
1244 the mode specified in the @code{match_operand} as the mode of the memory
1245 reference for which the address would be valid.
1247 @cindex other register constraints
1248 @cindex extensible constraints
1249 @item @var{other-letters}
1250 Other letters can be defined in machine-dependent fashion to stand for
1251 particular classes of registers or other arbitrary operand types.
1252 @samp{d}, @samp{a} and @samp{f} are defined on the 68000/68020 to stand
1253 for data, address and floating point registers.
1256 The machine description macro @code{REG_CLASS_FROM_LETTER} has first
1257 cut at the otherwise unused letters. If it evaluates to @code{NO_REGS},
1258 then @code{EXTRA_CONSTRAINT} is evaluated.
1260 A typical use for @code{EXTRA_CONSTRAINT} would be to distinguish certain
1261 types of memory references that affect other insn operands.
1266 In order to have valid assembler code, each operand must satisfy
1267 its constraint. But a failure to do so does not prevent the pattern
1268 from applying to an insn. Instead, it directs the compiler to modify
1269 the code so that the constraint will be satisfied. Usually this is
1270 done by copying an operand into a register.
1272 Contrast, therefore, the two instruction patterns that follow:
1276 [(set (match_operand:SI 0 "general_operand" "=r")
1277 (plus:SI (match_dup 0)
1278 (match_operand:SI 1 "general_operand" "r")))]
1284 which has two operands, one of which must appear in two places, and
1288 [(set (match_operand:SI 0 "general_operand" "=r")
1289 (plus:SI (match_operand:SI 1 "general_operand" "0")
1290 (match_operand:SI 2 "general_operand" "r")))]
1296 which has three operands, two of which are required by a constraint to be
1297 identical. If we are considering an insn of the form
1300 (insn @var{n} @var{prev} @var{next}
1302 (plus:SI (reg:SI 6) (reg:SI 109)))
1307 the first pattern would not apply at all, because this insn does not
1308 contain two identical subexpressions in the right place. The pattern would
1309 say, ``That does not look like an add instruction; try other patterns.''
1310 The second pattern would say, ``Yes, that's an add instruction, but there
1311 is something wrong with it.'' It would direct the reload pass of the
1312 compiler to generate additional insns to make the constraint true. The
1313 results might look like this:
1316 (insn @var{n2} @var{prev} @var{n}
1317 (set (reg:SI 3) (reg:SI 6))
1320 (insn @var{n} @var{n2} @var{next}
1322 (plus:SI (reg:SI 3) (reg:SI 109)))
1326 It is up to you to make sure that each operand, in each pattern, has
1327 constraints that can handle any RTL expression that could be present for
1328 that operand. (When multiple alternatives are in use, each pattern must,
1329 for each possible combination of operand expressions, have at least one
1330 alternative which can handle that combination of operands.) The
1331 constraints don't need to @emph{allow} any possible operand---when this is
1332 the case, they do not constrain---but they must at least point the way to
1333 reloading any possible operand so that it will fit.
1337 If the constraint accepts whatever operands the predicate permits,
1338 there is no problem: reloading is never necessary for this operand.
1340 For example, an operand whose constraints permit everything except
1341 registers is safe provided its predicate rejects registers.
1343 An operand whose predicate accepts only constant values is safe
1344 provided its constraints include the letter @samp{i}. If any possible
1345 constant value is accepted, then nothing less than @samp{i} will do;
1346 if the predicate is more selective, then the constraints may also be
1350 Any operand expression can be reloaded by copying it into a register.
1351 So if an operand's constraints allow some kind of register, it is
1352 certain to be safe. It need not permit all classes of registers; the
1353 compiler knows how to copy a register into another register of the
1354 proper class in order to make an instruction valid.
1356 @cindex nonoffsettable memory reference
1357 @cindex memory reference, nonoffsettable
1359 A nonoffsettable memory reference can be reloaded by copying the
1360 address into a register. So if the constraint uses the letter
1361 @samp{o}, all memory references are taken care of.
1364 A constant operand can be reloaded by allocating space in memory to
1365 hold it as preinitialized data. Then the memory reference can be used
1366 in place of the constant. So if the constraint uses the letters
1367 @samp{o} or @samp{m}, constant operands are not a problem.
1370 If the constraint permits a constant and a pseudo register used in an insn
1371 was not allocated to a hard register and is equivalent to a constant,
1372 the register will be replaced with the constant. If the predicate does
1373 not permit a constant and the insn is re-recognized for some reason, the
1374 compiler will crash. Thus the predicate must always recognize any
1375 objects allowed by the constraint.
1378 If the operand's predicate can recognize registers, but the constraint does
1379 not permit them, it can make the compiler crash. When this operand happens
1380 to be a register, the reload pass will be stymied, because it does not know
1381 how to copy a register temporarily into memory.
1383 If the predicate accepts a unary operator, the constraint applies to the
1384 operand. For example, the MIPS processor at ISA level 3 supports an
1385 instruction which adds two registers in @code{SImode} to produce a
1386 @code{DImode} result, but only if the registers are correctly sign
1387 extended. This predicate for the input operands accepts a
1388 @code{sign_extend} of an @code{SImode} register. Write the constraint
1389 to indicate the type of register that is required for the operand of the
1393 @node Multi-Alternative
1394 @subsection Multiple Alternative Constraints
1395 @cindex multiple alternative constraints
1397 Sometimes a single instruction has multiple alternative sets of possible
1398 operands. For example, on the 68000, a logical-or instruction can combine
1399 register or an immediate value into memory, or it can combine any kind of
1400 operand into a register; but it cannot combine one memory location into
1403 These constraints are represented as multiple alternatives. An alternative
1404 can be described by a series of letters for each operand. The overall
1405 constraint for an operand is made from the letters for this operand
1406 from the first alternative, a comma, the letters for this operand from
1407 the second alternative, a comma, and so on until the last alternative.
1409 Here is how it is done for fullword logical-or on the 68000:
1412 (define_insn "iorsi3"
1413 [(set (match_operand:SI 0 "general_operand" "=m,d")
1414 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
1415 (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
1419 The first alternative has @samp{m} (memory) for operand 0, @samp{0} for
1420 operand 1 (meaning it must match operand 0), and @samp{dKs} for operand
1421 2. The second alternative has @samp{d} (data register) for operand 0,
1422 @samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and
1423 @samp{%} in the constraints apply to all the alternatives; their
1424 meaning is explained in the next section (@pxref{Class Preferences}).
1427 @c FIXME Is this ? and ! stuff of use in asm()? If not, hide unless INTERNAL
1428 If all the operands fit any one alternative, the instruction is valid.
1429 Otherwise, for each alternative, the compiler counts how many instructions
1430 must be added to copy the operands so that that alternative applies.
1431 The alternative requiring the least copying is chosen. If two alternatives
1432 need the same amount of copying, the one that comes first is chosen.
1433 These choices can be altered with the @samp{?} and @samp{!} characters:
1436 @cindex @samp{?} in constraint
1437 @cindex question mark
1439 Disparage slightly the alternative that the @samp{?} appears in,
1440 as a choice when no alternative applies exactly. The compiler regards
1441 this alternative as one unit more costly for each @samp{?} that appears
1444 @cindex @samp{!} in constraint
1445 @cindex exclamation point
1447 Disparage severely the alternative that the @samp{!} appears in.
1448 This alternative can still be used if it fits without reloading,
1449 but if reloading is needed, some other alternative will be used.
1453 When an insn pattern has multiple alternatives in its constraints, often
1454 the appearance of the assembler code is determined mostly by which
1455 alternative was matched. When this is so, the C code for writing the
1456 assembler code can use the variable @code{which_alternative}, which is
1457 the ordinal number of the alternative that was actually satisfied (0 for
1458 the first, 1 for the second alternative, etc.). @xref{Output Statement}.
1462 @node Class Preferences
1463 @subsection Register Class Preferences
1464 @cindex class preference constraints
1465 @cindex register class preference constraints
1467 @cindex voting between constraint alternatives
1468 The operand constraints have another function: they enable the compiler
1469 to decide which kind of hardware register a pseudo register is best
1470 allocated to. The compiler examines the constraints that apply to the
1471 insns that use the pseudo register, looking for the machine-dependent
1472 letters such as @samp{d} and @samp{a} that specify classes of registers.
1473 The pseudo register is put in whichever class gets the most ``votes''.
1474 The constraint letters @samp{g} and @samp{r} also vote: they vote in
1475 favor of a general register. The machine description says which registers
1476 are considered general.
1478 Of course, on some machines all registers are equivalent, and no register
1479 classes are defined. Then none of this complexity is relevant.
1483 @subsection Constraint Modifier Characters
1484 @cindex modifiers in constraints
1485 @cindex constraint modifier characters
1487 @c prevent bad page break with this line
1488 Here are constraint modifier characters.
1491 @cindex @samp{=} in constraint
1493 Means that this operand is write-only for this instruction: the previous
1494 value is discarded and replaced by output data.
1496 @cindex @samp{+} in constraint
1498 Means that this operand is both read and written by the instruction.
1500 When the compiler fixes up the operands to satisfy the constraints,
1501 it needs to know which operands are inputs to the instruction and
1502 which are outputs from it. @samp{=} identifies an output; @samp{+}
1503 identifies an operand that is both input and output; all other operands
1504 are assumed to be input only.
1506 If you specify @samp{=} or @samp{+} in a constraint, you put it in the
1507 first character of the constraint string.
1509 @cindex @samp{&} in constraint
1510 @cindex earlyclobber operand
1512 Means (in a particular alternative) that this operand is an
1513 @dfn{earlyclobber} operand, which is modified before the instruction is
1514 finished using the input operands. Therefore, this operand may not lie
1515 in a register that is used as an input operand or as part of any memory
1518 @samp{&} applies only to the alternative in which it is written. In
1519 constraints with multiple alternatives, sometimes one alternative
1520 requires @samp{&} while others do not. See, for example, the
1521 @samp{movdf} insn of the 68000.
1523 An input operand can be tied to an earlyclobber operand if its only
1524 use as an input occurs before the early result is written. Adding
1525 alternatives of this form often allows GCC to produce better code
1526 when only some of the inputs can be affected by the earlyclobber.
1527 See, for example, the @samp{mulsi3} insn of the ARM@.
1529 @samp{&} does not obviate the need to write @samp{=}.
1531 @cindex @samp{%} in constraint
1533 Declares the instruction to be commutative for this operand and the
1534 following operand. This means that the compiler may interchange the
1535 two operands if that is the cheapest way to make all operands fit the
1538 This is often used in patterns for addition instructions
1539 that really have only two operands: the result must go in one of the
1540 arguments. Here for example, is how the 68000 halfword-add
1541 instruction is defined:
1544 (define_insn "addhi3"
1545 [(set (match_operand:HI 0 "general_operand" "=m,r")
1546 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
1547 (match_operand:HI 2 "general_operand" "di,g")))]
1551 GCC can only handle one commutative pair in an asm; if you use more,
1552 the compiler may fail.
1554 @cindex @samp{#} in constraint
1556 Says that all following characters, up to the next comma, are to be
1557 ignored as a constraint. They are significant only for choosing
1558 register preferences.
1560 @cindex @samp{*} in constraint
1562 Says that the following character should be ignored when choosing
1563 register preferences. @samp{*} has no effect on the meaning of the
1564 constraint as a constraint, and no effect on reloading.
1567 Here is an example: the 68000 has an instruction to sign-extend a
1568 halfword in a data register, and can also sign-extend a value by
1569 copying it into an address register. While either kind of register is
1570 acceptable, the constraints on an address-register destination are
1571 less strict, so it is best if register allocation makes an address
1572 register its goal. Therefore, @samp{*} is used so that the @samp{d}
1573 constraint letter (for data register) is ignored when computing
1574 register preferences.
1577 (define_insn "extendhisi2"
1578 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1580 (match_operand:HI 1 "general_operand" "0,g")))]
1586 @node Machine Constraints
1587 @subsection Constraints for Particular Machines
1588 @cindex machine specific constraints
1589 @cindex constraints, machine specific
1591 Whenever possible, you should use the general-purpose constraint letters
1592 in @code{asm} arguments, since they will convey meaning more readily to
1593 people reading your code. Failing that, use the constraint letters
1594 that usually have very similar meanings across architectures. The most
1595 commonly used constraints are @samp{m} and @samp{r} (for memory and
1596 general-purpose registers respectively; @pxref{Simple Constraints}), and
1597 @samp{I}, usually the letter indicating the most common
1598 immediate-constant format.
1600 For each machine architecture, the
1601 @file{config/@var{machine}/@var{machine}.h} file defines additional
1602 constraints. These constraints are used by the compiler itself for
1603 instruction generation, as well as for @code{asm} statements; therefore,
1604 some of the constraints are not particularly interesting for @code{asm}.
1605 The constraints are defined through these macros:
1608 @item REG_CLASS_FROM_LETTER
1609 Register class constraints (usually lowercase).
1611 @item CONST_OK_FOR_LETTER_P
1612 Immediate constant constraints, for non-floating point constants of
1613 word size or smaller precision (usually uppercase).
1615 @item CONST_DOUBLE_OK_FOR_LETTER_P
1616 Immediate constant constraints, for all floating point constants and for
1617 constants of greater than word size precision (usually uppercase).
1619 @item EXTRA_CONSTRAINT
1620 Special cases of registers or memory. This macro is not required, and
1621 is only defined for some machines.
1624 Inspecting these macro definitions in the compiler source for your
1625 machine is the best way to be certain you have the right constraints.
1626 However, here is a summary of the machine-dependent constraints
1627 available on some particular machines.
1630 @item ARM family---@file{arm.h}
1633 Floating-point register
1636 VFP floating-point register
1639 One of the floating-point constants 0.0, 0.5, 1.0, 2.0, 3.0, 4.0, 5.0
1643 Floating-point constant that would satisfy the constraint @samp{F} if it
1647 Integer that is valid as an immediate operand in a data processing
1648 instruction. That is, an integer in the range 0 to 255 rotated by a
1652 Integer in the range @minus{}4095 to 4095
1655 Integer that satisfies constraint @samp{I} when inverted (ones complement)
1658 Integer that satisfies constraint @samp{I} when negated (twos complement)
1661 Integer in the range 0 to 32
1664 A memory reference where the exact address is in a single register
1665 (`@samp{m}' is preferable for @code{asm} statements)
1668 An item in the constant pool
1671 A symbol in the text segment of the current file
1675 A memory reference suitable for VFP load/store insns (reg+constant offset)
1678 A memory reference suitable for iWMMXt load/store instructions.
1681 A memory reference suitable for for the ARMv4 ldrsb instruction.
1683 @item AVR family---@file{avr.h}
1686 Registers from r0 to r15
1689 Registers from r16 to r23
1692 Registers from r16 to r31
1695 Registers from r24 to r31. These registers can be used in @samp{adiw} command
1698 Pointer register (r26--r31)
1701 Base pointer register (r28--r31)
1704 Stack pointer register (SPH:SPL)
1707 Temporary register r0
1710 Register pair X (r27:r26)
1713 Register pair Y (r29:r28)
1716 Register pair Z (r31:r30)
1719 Constant greater than @minus{}1, less than 64
1722 Constant greater than @minus{}64, less than 1
1731 Constant that fits in 8 bits
1734 Constant integer @minus{}1
1737 Constant integer 8, 16, or 24
1743 A floating point constant 0.0
1746 @item PowerPC and IBM RS6000---@file{rs6000.h}
1749 Address base register
1752 Floating point register
1758 @samp{MQ}, @samp{CTR}, or @samp{LINK} register
1767 @samp{LINK} register
1770 @samp{CR} register (condition register) number 0
1773 @samp{CR} register (condition register)
1776 @samp{FPMEM} stack memory for FPR-GPR transfers
1779 Signed 16-bit constant
1782 Unsigned 16-bit constant shifted left 16 bits (use @samp{L} instead for
1783 @code{SImode} constants)
1786 Unsigned 16-bit constant
1789 Signed 16-bit constant shifted left 16 bits
1792 Constant larger than 31
1801 Constant whose negation is a signed 16-bit constant
1804 Floating point constant that can be loaded into a register with one
1805 instruction per word
1808 Memory operand that is an offset from a register (@samp{m} is preferable
1809 for @code{asm} statements)
1815 Constant suitable as a 64-bit mask operand
1818 Constant suitable as a 32-bit mask operand
1821 System V Release 4 small data area reference
1824 @item Intel 386---@file{i386.h}
1827 @samp{a}, @code{b}, @code{c}, or @code{d} register for the i386.
1828 For x86-64 it is equivalent to @samp{r} class. (for 8-bit instructions that
1829 do not use upper halves)
1832 @samp{a}, @code{b}, @code{c}, or @code{d} register. (for 8-bit instructions,
1833 that do use upper halves)
1836 Legacy register---equivalent to @code{r} class in i386 mode.
1837 (for non-8-bit registers used together with 8-bit upper halves in a single
1841 Specifies the @samp{a} or @samp{d} registers. This is primarily useful
1842 for 64-bit integer values (when in 32-bit mode) intended to be returned
1843 with the @samp{d} register holding the most significant bits and the
1844 @samp{a} register holding the least significant bits.
1847 Floating point register
1850 First (top of stack) floating point register
1853 Second floating point register
1865 Specifies constant that can be easily constructed in SSE register without
1866 loading it from memory.
1878 @samp{xmm} SSE register
1884 Constant in range 0 to 31 (for 32-bit shifts)
1887 Constant in range 0 to 63 (for 64-bit shifts)
1896 0, 1, 2, or 3 (shifts for @code{lea} instruction)
1899 Constant in range 0 to 255 (for @code{out} instruction)
1902 Constant in range 0 to @code{0xffffffff} or symbolic reference known to fit specified range.
1903 (for using immediates in zero extending 32-bit to 64-bit x86-64 instructions)
1906 Constant in range @minus{}2147483648 to 2147483647 or symbolic reference known to fit specified range.
1907 (for using immediates in 64-bit x86-64 instructions)
1910 Standard 80387 floating point constant
1913 @item Intel IA-64---@file{ia64.h}
1916 General register @code{r0} to @code{r3} for @code{addl} instruction
1922 Predicate register (@samp{c} as in ``conditional'')
1925 Application register residing in M-unit
1928 Application register residing in I-unit
1931 Floating-point register
1935 Remember that @samp{m} allows postincrement and postdecrement which
1936 require printing with @samp{%Pn} on IA-64.
1937 Use @samp{S} to disallow postincrement and postdecrement.
1940 Floating-point constant 0.0 or 1.0
1943 14-bit signed integer constant
1946 22-bit signed integer constant
1949 8-bit signed integer constant for logical instructions
1952 8-bit adjusted signed integer constant for compare pseudo-ops
1955 6-bit unsigned integer constant for shift counts
1958 9-bit signed integer constant for load and store postincrements
1964 0 or -1 for @code{dep} instruction
1967 Non-volatile memory for floating-point loads and stores
1970 Integer constant in the range 1 to 4 for @code{shladd} instruction
1973 Memory operand except postincrement and postdecrement
1976 @item FRV---@file{frv.h}
1979 Register in the class @code{ACC_REGS} (@code{acc0} to @code{acc7}).
1982 Register in the class @code{EVEN_ACC_REGS} (@code{acc0} to @code{acc7}).
1985 Register in the class @code{CC_REGS} (@code{fcc0} to @code{fcc3} and
1986 @code{icc0} to @code{icc3}).
1989 Register in the class @code{GPR_REGS} (@code{gr0} to @code{gr63}).
1992 Register in the class @code{EVEN_REGS} (@code{gr0} to @code{gr63}).
1993 Odd registers are excluded not in the class but through the use of a machine
1994 mode larger than 4 bytes.
1997 Register in the class @code{FPR_REGS} (@code{fr0} to @code{fr63}).
2000 Register in the class @code{FEVEN_REGS} (@code{fr0} to @code{fr63}).
2001 Odd registers are excluded not in the class but through the use of a machine
2002 mode larger than 4 bytes.
2005 Register in the class @code{LR_REG} (the @code{lr} register).
2008 Register in the class @code{QUAD_REGS} (@code{gr2} to @code{gr63}).
2009 Register numbers not divisible by 4 are excluded not in the class but through
2010 the use of a machine mode larger than 8 bytes.
2013 Register in the class @code{ICC_REGS} (@code{icc0} to @code{icc3}).
2016 Register in the class @code{FCC_REGS} (@code{fcc0} to @code{fcc3}).
2019 Register in the class @code{ICR_REGS} (@code{cc4} to @code{cc7}).
2022 Register in the class @code{FCR_REGS} (@code{cc0} to @code{cc3}).
2025 Register in the class @code{QUAD_FPR_REGS} (@code{fr0} to @code{fr63}).
2026 Register numbers not divisible by 4 are excluded not in the class but through
2027 the use of a machine mode larger than 8 bytes.
2030 Register in the class @code{SPR_REGS} (@code{lcr} and @code{lr}).
2033 Register in the class @code{QUAD_ACC_REGS} (@code{acc0} to @code{acc7}).
2036 Register in the class @code{ACCG_REGS} (@code{accg0} to @code{accg7}).
2039 Register in the class @code{CR_REGS} (@code{cc0} to @code{cc7}).
2042 Floating point constant zero
2045 6-bit signed integer constant
2048 10-bit signed integer constant
2051 16-bit signed integer constant
2054 16-bit unsigned integer constant
2057 12-bit signed integer constant that is negative---i.e.@: in the
2058 range of @minus{}2048 to @minus{}1
2064 12-bit signed integer constant that is greater than zero---i.e.@: in the
2069 @item IP2K---@file{ip2k.h}
2072 @samp{DP} or @samp{IP} registers (general address)
2096 @samp{DP} or @samp{SP} registers (offsettable address)
2099 Non-pointer registers (not @samp{SP}, @samp{DP}, @samp{IP})
2102 Non-SP registers (everything except @samp{SP})
2105 Indirect through @samp{IP} - Avoid this except for @code{QImode}, since we
2106 can't access extra bytes
2109 Indirect through @samp{SP} or @samp{DP} with short displacement (0..127)
2112 Data-section immediate value
2115 Integers from @minus{}255 to @minus{}1
2118 Integers from 0 to 7---valid bit number in a register
2121 Integers from 0 to 127---valid displacement for addressing mode
2124 Integers from 1 to 127
2136 Integers from 0 to 255
2139 @item MIPS---@file{mips.h}
2142 General-purpose integer register
2145 Floating-point register (if available)
2154 @samp{Hi} or @samp{Lo} register
2157 General-purpose integer register
2160 Floating-point status register
2163 Signed 16-bit constant (for arithmetic instructions)
2169 Zero-extended 16-bit constant (for logic instructions)
2172 Constant with low 16 bits zero (can be loaded with @code{lui})
2175 32-bit constant which requires two instructions to load (a constant
2176 which is not @samp{I}, @samp{K}, or @samp{L})
2179 Negative 16-bit constant
2185 Positive 16-bit constant
2191 Memory reference that can be loaded with more than one instruction
2192 (@samp{m} is preferable for @code{asm} statements)
2195 Memory reference that can be loaded with one instruction
2196 (@samp{m} is preferable for @code{asm} statements)
2199 Memory reference in external OSF/rose PIC format
2200 (@samp{m} is preferable for @code{asm} statements)
2203 @item Motorola 680x0---@file{m68k.h}
2212 68881 floating-point register, if available
2215 Integer in the range 1 to 8
2218 16-bit signed number
2221 Signed number whose magnitude is greater than 0x80
2224 Integer in the range @minus{}8 to @minus{}1
2227 Signed number whose magnitude is greater than 0x100
2230 Floating point constant that is not a 68881 constant
2233 @item Motorola 68HC11 & 68HC12 families---@file{m68hc11.h}
2248 Temporary soft register _.tmp
2251 A soft register _.d1 to _.d31
2254 Stack pointer register
2263 Pseudo register 'z' (replaced by 'x' or 'y' at the end)
2266 An address register: x, y or z
2269 An address register: x or y
2272 Register pair (x:d) to form a 32-bit value
2275 Constants in the range @minus{}65536 to 65535
2278 Constants whose 16-bit low part is zero
2281 Constant integer 1 or @minus{}1
2287 Constants in the range @minus{}8 to 2
2292 @item SPARC---@file{sparc.h}
2295 Floating-point register on the SPARC-V8 architecture and
2296 lower floating-point register on the SPARC-V9 architecture.
2299 Floating-point register. It is equivalent to @samp{f} on the
2300 SPARC-V8 architecture and contains both lower and upper
2301 floating-point registers on the SPARC-V9 architecture.
2304 Floating-point condition code register.
2307 Lower floating-point register. It is only valid on the SPARC-V9
2308 architecture when the Visual Instruction Set is available.
2311 Floating-point register. It is only valid on the SPARC-V9 architecture
2312 when the Visual Instruction Set is available.
2315 64-bit global or out register for the SPARC-V8+ architecture.
2318 Signed 13-bit constant
2324 32-bit constant with the low 12 bits clear (a constant that can be
2325 loaded with the @code{sethi} instruction)
2328 A constant in the range supported by @code{movcc} instructions
2331 A constant in the range supported by @code{movrcc} instructions
2334 Same as @samp{K}, except that it verifies that bits that are not in the
2335 lower 32-bit range are all zero. Must be used instead of @samp{K} for
2336 modes wider than @code{SImode}
2345 Signed 13-bit constant, sign-extended to 32 or 64 bits
2348 Floating-point constant whose integral representation can
2349 be moved into an integer register using a single sethi
2353 Floating-point constant whose integral representation can
2354 be moved into an integer register using a single mov
2358 Floating-point constant whose integral representation can
2359 be moved into an integer register using a high/lo_sum
2360 instruction sequence
2363 Memory address aligned to an 8-byte boundary
2369 Memory address for @samp{e} constraint registers.
2373 @item TMS320C3x/C4x---@file{c4x.h}
2376 Auxiliary (address) register (ar0-ar7)
2379 Stack pointer register (sp)
2382 Standard (32-bit) precision integer register
2385 Extended (40-bit) precision register (r0-r11)
2388 Block count register (bk)
2391 Extended (40-bit) precision low register (r0-r7)
2394 Extended (40-bit) precision register (r0-r1)
2397 Extended (40-bit) precision register (r2-r3)
2400 Repeat count register (rc)
2403 Index register (ir0-ir1)
2406 Status (condition code) register (st)
2409 Data page register (dp)
2415 Immediate 16-bit floating-point constant
2418 Signed 16-bit constant
2421 Signed 8-bit constant
2424 Signed 5-bit constant
2427 Unsigned 16-bit constant
2430 Unsigned 8-bit constant
2433 Ones complement of unsigned 16-bit constant
2436 High 16-bit constant (32-bit constant with 16 LSBs zero)
2439 Indirect memory reference with signed 8-bit or index register displacement
2442 Indirect memory reference with unsigned 5-bit displacement
2445 Indirect memory reference with 1 bit or index register displacement
2448 Direct memory reference
2455 @item S/390 and zSeries---@file{s390.h}
2458 Address register (general purpose register except r0)
2461 Data register (arbitrary general purpose register)
2464 Floating-point register
2467 Unsigned 8-bit constant (0--255)
2470 Unsigned 12-bit constant (0--4095)
2473 Signed 16-bit constant (@minus{}32768--32767)
2476 Value appropriate as displacement.
2479 for short displacement
2480 @item (-524288..524287)
2481 for long displacement
2485 Constant integer with a value of 0x7fffffff.
2488 Multiple letter constraint followed by 4 parameter letters.
2491 number of the part counting from most to least significant
2495 mode of the containing operand
2497 value of the other parts (F - all bits set)
2499 The constraint matches if the specified part of a constant
2500 has a value different from it's other parts.
2503 Memory reference without index register and with short displacement.
2506 Memory reference with index register and short displacement.
2509 Memory reference without index register but with long displacement.
2512 Memory reference with index register and long displacement.
2515 Pointer with short displacement.
2518 Pointer with long displacement.
2521 Shift count operand.
2525 @item Xstormy16---@file{stormy16.h}
2540 Registers r0 through r7.
2543 Registers r0 and r1.
2549 Registers r8 and r9.
2552 A constant between 0 and 3 inclusive.
2555 A constant that has exactly one bit set.
2558 A constant that has exactly one bit clear.
2561 A constant between 0 and 255 inclusive.
2564 A constant between @minus{}255 and 0 inclusive.
2567 A constant between @minus{}3 and 0 inclusive.
2570 A constant between 1 and 4 inclusive.
2573 A constant between @minus{}4 and @minus{}1 inclusive.
2576 A memory reference that is a stack push.
2579 A memory reference that is a stack pop.
2582 A memory reference that refers to a constant address of known value.
2585 The register indicated by Rx (not implemented yet).
2588 A constant that is not between 2 and 15 inclusive.
2595 @item Xtensa---@file{xtensa.h}
2598 General-purpose 32-bit register
2601 One-bit boolean register
2604 MAC16 40-bit accumulator register
2607 Signed 12-bit integer constant, for use in MOVI instructions
2610 Signed 8-bit integer constant, for use in ADDI instructions
2613 Integer constant valid for BccI instructions
2616 Unsigned constant valid for BccUI instructions
2623 @node Standard Names
2624 @section Standard Pattern Names For Generation
2625 @cindex standard pattern names
2626 @cindex pattern names
2627 @cindex names, pattern
2629 Here is a table of the instruction names that are meaningful in the RTL
2630 generation pass of the compiler. Giving one of these names to an
2631 instruction pattern tells the RTL generation pass that it can use the
2632 pattern to accomplish a certain task.
2635 @cindex @code{mov@var{m}} instruction pattern
2636 @item @samp{mov@var{m}}
2637 Here @var{m} stands for a two-letter machine mode name, in lowercase.
2638 This instruction pattern moves data with that machine mode from operand
2639 1 to operand 0. For example, @samp{movsi} moves full-word data.
2641 If operand 0 is a @code{subreg} with mode @var{m} of a register whose
2642 own mode is wider than @var{m}, the effect of this instruction is
2643 to store the specified value in the part of the register that corresponds
2644 to mode @var{m}. Bits outside of @var{m}, but which are within the
2645 same target word as the @code{subreg} are undefined. Bits which are
2646 outside the target word are left unchanged.
2648 This class of patterns is special in several ways. First of all, each
2649 of these names up to and including full word size @emph{must} be defined,
2650 because there is no other way to copy a datum from one place to another.
2651 If there are patterns accepting operands in larger modes,
2652 @samp{mov@var{m}} must be defined for integer modes of those sizes.
2654 Second, these patterns are not used solely in the RTL generation pass.
2655 Even the reload pass can generate move insns to copy values from stack
2656 slots into temporary registers. When it does so, one of the operands is
2657 a hard register and the other is an operand that can need to be reloaded
2661 Therefore, when given such a pair of operands, the pattern must generate
2662 RTL which needs no reloading and needs no temporary registers---no
2663 registers other than the operands. For example, if you support the
2664 pattern with a @code{define_expand}, then in such a case the
2665 @code{define_expand} mustn't call @code{force_reg} or any other such
2666 function which might generate new pseudo registers.
2668 This requirement exists even for subword modes on a RISC machine where
2669 fetching those modes from memory normally requires several insns and
2670 some temporary registers.
2672 @findex change_address
2673 During reload a memory reference with an invalid address may be passed
2674 as an operand. Such an address will be replaced with a valid address
2675 later in the reload pass. In this case, nothing may be done with the
2676 address except to use it as it stands. If it is copied, it will not be
2677 replaced with a valid address. No attempt should be made to make such
2678 an address into a valid address and no routine (such as
2679 @code{change_address}) that will do so may be called. Note that
2680 @code{general_operand} will fail when applied to such an address.
2682 @findex reload_in_progress
2683 The global variable @code{reload_in_progress} (which must be explicitly
2684 declared if required) can be used to determine whether such special
2685 handling is required.
2687 The variety of operands that have reloads depends on the rest of the
2688 machine description, but typically on a RISC machine these can only be
2689 pseudo registers that did not get hard registers, while on other
2690 machines explicit memory references will get optional reloads.
2692 If a scratch register is required to move an object to or from memory,
2693 it can be allocated using @code{gen_reg_rtx} prior to life analysis.
2695 If there are cases which need scratch registers during or after reload,
2696 you must define @code{SECONDARY_INPUT_RELOAD_CLASS} and/or
2697 @code{SECONDARY_OUTPUT_RELOAD_CLASS} to detect them, and provide
2698 patterns @samp{reload_in@var{m}} or @samp{reload_out@var{m}} to handle
2699 them. @xref{Register Classes}.
2701 @findex no_new_pseudos
2702 The global variable @code{no_new_pseudos} can be used to determine if it
2703 is unsafe to create new pseudo registers. If this variable is nonzero, then
2704 it is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo.
2706 The constraints on a @samp{mov@var{m}} must permit moving any hard
2707 register to any other hard register provided that
2708 @code{HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and
2709 @code{REGISTER_MOVE_COST} applied to their classes returns a value of 2.
2711 It is obligatory to support floating point @samp{mov@var{m}}
2712 instructions into and out of any registers that can hold fixed point
2713 values, because unions and structures (which have modes @code{SImode} or
2714 @code{DImode}) can be in those registers and they may have floating
2717 There may also be a need to support fixed point @samp{mov@var{m}}
2718 instructions in and out of floating point registers. Unfortunately, I
2719 have forgotten why this was so, and I don't know whether it is still
2720 true. If @code{HARD_REGNO_MODE_OK} rejects fixed point values in
2721 floating point registers, then the constraints of the fixed point
2722 @samp{mov@var{m}} instructions must be designed to avoid ever trying to
2723 reload into a floating point register.
2725 @cindex @code{reload_in} instruction pattern
2726 @cindex @code{reload_out} instruction pattern
2727 @item @samp{reload_in@var{m}}
2728 @itemx @samp{reload_out@var{m}}
2729 Like @samp{mov@var{m}}, but used when a scratch register is required to
2730 move between operand 0 and operand 1. Operand 2 describes the scratch
2731 register. See the discussion of the @code{SECONDARY_RELOAD_CLASS}
2732 macro in @pxref{Register Classes}.
2734 There are special restrictions on the form of the @code{match_operand}s
2735 used in these patterns. First, only the predicate for the reload
2736 operand is examined, i.e., @code{reload_in} examines operand 1, but not
2737 the predicates for operand 0 or 2. Second, there may be only one
2738 alternative in the constraints. Third, only a single register class
2739 letter may be used for the constraint; subsequent constraint letters
2740 are ignored. As a special exception, an empty constraint string
2741 matches the @code{ALL_REGS} register class. This may relieve ports
2742 of the burden of defining an @code{ALL_REGS} constraint letter just
2745 @cindex @code{movstrict@var{m}} instruction pattern
2746 @item @samp{movstrict@var{m}}
2747 Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg}
2748 with mode @var{m} of a register whose natural mode is wider,
2749 the @samp{movstrict@var{m}} instruction is guaranteed not to alter
2750 any of the register except the part which belongs to mode @var{m}.
2752 @cindex @code{load_multiple} instruction pattern
2753 @item @samp{load_multiple}
2754 Load several consecutive memory locations into consecutive registers.
2755 Operand 0 is the first of the consecutive registers, operand 1
2756 is the first memory location, and operand 2 is a constant: the
2757 number of consecutive registers.
2759 Define this only if the target machine really has such an instruction;
2760 do not define this if the most efficient way of loading consecutive
2761 registers from memory is to do them one at a time.
2763 On some machines, there are restrictions as to which consecutive
2764 registers can be stored into memory, such as particular starting or
2765 ending register numbers or only a range of valid counts. For those
2766 machines, use a @code{define_expand} (@pxref{Expander Definitions})
2767 and make the pattern fail if the restrictions are not met.
2769 Write the generated insn as a @code{parallel} with elements being a
2770 @code{set} of one register from the appropriate memory location (you may
2771 also need @code{use} or @code{clobber} elements). Use a
2772 @code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See
2773 @file{rs6000.md} for examples of the use of this insn pattern.
2775 @cindex @samp{store_multiple} instruction pattern
2776 @item @samp{store_multiple}
2777 Similar to @samp{load_multiple}, but store several consecutive registers
2778 into consecutive memory locations. Operand 0 is the first of the
2779 consecutive memory locations, operand 1 is the first register, and
2780 operand 2 is a constant: the number of consecutive registers.
2782 @cindex @code{vec_set@var{m}} instruction pattern
2783 @item @samp{vec_set@var{m}}
2784 Set given field in the vector value. Operand 0 is the vector to modify,
2785 operand 1 is new value of field and operand 2 specify the field index.
2787 @cindex @code{vec_extract@var{m}} instruction pattern
2788 @item @samp{vec_extract@var{m}}
2789 Extract given field from the vector value. Operand 1 is the vector, operand 2
2790 specify field index and operand 0 place to store value into.
2792 @cindex @code{vec_init@var{m}} instruction pattern
2793 @item @samp{vec_init@var{m}}
2794 Initialize the vector to given values. Operand 0 is the vector to initialize
2795 and operand 1 is parallel containing values for individual fields.
2797 @cindex @code{push@var{m}} instruction pattern
2798 @item @samp{push@var{m}}
2799 Output a push instruction. Operand 0 is value to push. Used only when
2800 @code{PUSH_ROUNDING} is defined. For historical reason, this pattern may be
2801 missing and in such case an @code{mov} expander is used instead, with a
2802 @code{MEM} expression forming the push operation. The @code{mov} expander
2803 method is deprecated.
2805 @cindex @code{add@var{m}3} instruction pattern
2806 @item @samp{add@var{m}3}
2807 Add operand 2 and operand 1, storing the result in operand 0. All operands
2808 must have mode @var{m}. This can be used even on two-address machines, by
2809 means of constraints requiring operands 1 and 0 to be the same location.
2811 @cindex @code{sub@var{m}3} instruction pattern
2812 @cindex @code{mul@var{m}3} instruction pattern
2813 @cindex @code{div@var{m}3} instruction pattern
2814 @cindex @code{udiv@var{m}3} instruction pattern
2815 @cindex @code{mod@var{m}3} instruction pattern
2816 @cindex @code{umod@var{m}3} instruction pattern
2817 @cindex @code{smin@var{m}3} instruction pattern
2818 @cindex @code{smax@var{m}3} instruction pattern
2819 @cindex @code{umin@var{m}3} instruction pattern
2820 @cindex @code{umax@var{m}3} instruction pattern
2821 @cindex @code{and@var{m}3} instruction pattern
2822 @cindex @code{ior@var{m}3} instruction pattern
2823 @cindex @code{xor@var{m}3} instruction pattern
2824 @item @samp{sub@var{m}3}, @samp{mul@var{m}3}
2825 @itemx @samp{div@var{m}3}, @samp{udiv@var{m}3}, @samp{mod@var{m}3}, @samp{umod@var{m}3}
2826 @itemx @samp{smin@var{m}3}, @samp{smax@var{m}3}, @samp{umin@var{m}3}, @samp{umax@var{m}3}
2827 @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3}
2828 Similar, for other arithmetic operations.
2829 @cindex @code{min@var{m}3} instruction pattern
2830 @cindex @code{max@var{m}3} instruction pattern
2831 @itemx @samp{min@var{m}3}, @samp{max@var{m}3}
2832 Floating point min and max operations. If both operands are zeros,
2833 or if either operand is NaN, then it is unspecified which of the two
2834 operands is returned as the result.
2837 @cindex @code{mulhisi3} instruction pattern
2838 @item @samp{mulhisi3}
2839 Multiply operands 1 and 2, which have mode @code{HImode}, and store
2840 a @code{SImode} product in operand 0.
2842 @cindex @code{mulqihi3} instruction pattern
2843 @cindex @code{mulsidi3} instruction pattern
2844 @item @samp{mulqihi3}, @samp{mulsidi3}
2845 Similar widening-multiplication instructions of other widths.
2847 @cindex @code{umulqihi3} instruction pattern
2848 @cindex @code{umulhisi3} instruction pattern
2849 @cindex @code{umulsidi3} instruction pattern
2850 @item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3}
2851 Similar widening-multiplication instructions that do unsigned
2854 @cindex @code{smul@var{m}3_highpart} instruction pattern
2855 @item @samp{smul@var{m}3_highpart}
2856 Perform a signed multiplication of operands 1 and 2, which have mode
2857 @var{m}, and store the most significant half of the product in operand 0.
2858 The least significant half of the product is discarded.
2860 @cindex @code{umul@var{m}3_highpart} instruction pattern
2861 @item @samp{umul@var{m}3_highpart}
2862 Similar, but the multiplication is unsigned.
2864 @cindex @code{divmod@var{m}4} instruction pattern
2865 @item @samp{divmod@var{m}4}
2866 Signed division that produces both a quotient and a remainder.
2867 Operand 1 is divided by operand 2 to produce a quotient stored
2868 in operand 0 and a remainder stored in operand 3.
2870 For machines with an instruction that produces both a quotient and a
2871 remainder, provide a pattern for @samp{divmod@var{m}4} but do not
2872 provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This
2873 allows optimization in the relatively common case when both the quotient
2874 and remainder are computed.
2876 If an instruction that just produces a quotient or just a remainder
2877 exists and is more efficient than the instruction that produces both,
2878 write the output routine of @samp{divmod@var{m}4} to call
2879 @code{find_reg_note} and look for a @code{REG_UNUSED} note on the
2880 quotient or remainder and generate the appropriate instruction.
2882 @cindex @code{udivmod@var{m}4} instruction pattern
2883 @item @samp{udivmod@var{m}4}
2884 Similar, but does unsigned division.
2886 @cindex @code{ashl@var{m}3} instruction pattern
2887 @item @samp{ashl@var{m}3}
2888 Arithmetic-shift operand 1 left by a number of bits specified by operand
2889 2, and store the result in operand 0. Here @var{m} is the mode of
2890 operand 0 and operand 1; operand 2's mode is specified by the
2891 instruction pattern, and the compiler will convert the operand to that
2892 mode before generating the instruction.
2894 @cindex @code{ashr@var{m}3} instruction pattern
2895 @cindex @code{lshr@var{m}3} instruction pattern
2896 @cindex @code{rotl@var{m}3} instruction pattern
2897 @cindex @code{rotr@var{m}3} instruction pattern
2898 @item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3}
2899 Other shift and rotate instructions, analogous to the
2900 @code{ashl@var{m}3} instructions.
2902 @cindex @code{neg@var{m}2} instruction pattern
2903 @item @samp{neg@var{m}2}
2904 Negate operand 1 and store the result in operand 0.
2906 @cindex @code{abs@var{m}2} instruction pattern
2907 @item @samp{abs@var{m}2}
2908 Store the absolute value of operand 1 into operand 0.
2910 @cindex @code{sqrt@var{m}2} instruction pattern
2911 @item @samp{sqrt@var{m}2}
2912 Store the square root of operand 1 into operand 0.
2914 The @code{sqrt} built-in function of C always uses the mode which
2915 corresponds to the C data type @code{double} and the @code{sqrtf}
2916 built-in function uses the mode which corresponds to the C data
2919 @cindex @code{cos@var{m}2} instruction pattern
2920 @item @samp{cos@var{m}2}
2921 Store the cosine of operand 1 into operand 0.
2923 The @code{cos} built-in function of C always uses the mode which
2924 corresponds to the C data type @code{double} and the @code{cosf}
2925 built-in function uses the mode which corresponds to the C data
2928 @cindex @code{sin@var{m}2} instruction pattern
2929 @item @samp{sin@var{m}2}
2930 Store the sine of operand 1 into operand 0.
2932 The @code{sin} built-in function of C always uses the mode which
2933 corresponds to the C data type @code{double} and the @code{sinf}
2934 built-in function uses the mode which corresponds to the C data
2937 @cindex @code{exp@var{m}2} instruction pattern
2938 @item @samp{exp@var{m}2}
2939 Store the exponential of operand 1 into operand 0.
2941 The @code{exp} built-in function of C always uses the mode which
2942 corresponds to the C data type @code{double} and the @code{expf}
2943 built-in function uses the mode which corresponds to the C data
2946 @cindex @code{log@var{m}2} instruction pattern
2947 @item @samp{log@var{m}2}
2948 Store the natural logarithm of operand 1 into operand 0.
2950 The @code{log} built-in function of C always uses the mode which
2951 corresponds to the C data type @code{double} and the @code{logf}
2952 built-in function uses the mode which corresponds to the C data
2955 @cindex @code{pow@var{m}3} instruction pattern
2956 @item @samp{pow@var{m}3}
2957 Store the value of operand 1 raised to the exponent operand 2
2960 The @code{pow} built-in function of C always uses the mode which
2961 corresponds to the C data type @code{double} and the @code{powf}
2962 built-in function uses the mode which corresponds to the C data
2965 @cindex @code{atan2@var{m}3} instruction pattern
2966 @item @samp{atan2@var{m}3}
2967 Store the arc tangent (inverse tangent) of operand 1 divided by
2968 operand 2 into operand 0, using the signs of both arguments to
2969 determine the quadrant of the result.
2971 The @code{atan2} built-in function of C always uses the mode which
2972 corresponds to the C data type @code{double} and the @code{atan2f}
2973 built-in function uses the mode which corresponds to the C data
2976 @cindex @code{floor@var{m}2} instruction pattern
2977 @item @samp{floor@var{m}2}
2978 Store the largest integral value not greater than argument.
2980 The @code{floor} built-in function of C always uses the mode which
2981 corresponds to the C data type @code{double} and the @code{floorf}
2982 built-in function uses the mode which corresponds to the C data
2985 @cindex @code{trunc@var{m}2} instruction pattern
2986 @item @samp{trunc@var{m}2}
2987 Store the argument rounded to integer towards zero.
2989 The @code{trunc} built-in function of C always uses the mode which
2990 corresponds to the C data type @code{double} and the @code{truncf}
2991 built-in function uses the mode which corresponds to the C data
2994 @cindex @code{round@var{m}2} instruction pattern
2995 @item @samp{round@var{m}2}
2996 Store the argument rounded to integer away from zero.
2998 The @code{round} built-in function of C always uses the mode which
2999 corresponds to the C data type @code{double} and the @code{roundf}
3000 built-in function uses the mode which corresponds to the C data
3003 @cindex @code{ceil@var{m}2} instruction pattern
3004 @item @samp{ceil@var{m}2}
3005 Store the argument rounded to integer away from zero.
3007 The @code{ceil} built-in function of C always uses the mode which
3008 corresponds to the C data type @code{double} and the @code{ceilf}
3009 built-in function uses the mode which corresponds to the C data
3012 @cindex @code{nearbyint@var{m}2} instruction pattern
3013 @item @samp{nearbyint@var{m}2}
3014 Store the argument rounded according to the default rounding mode
3016 The @code{nearbyint} built-in function of C always uses the mode which
3017 corresponds to the C data type @code{double} and the @code{nearbyintf}
3018 built-in function uses the mode which corresponds to the C data
3021 @cindex @code{ffs@var{m}2} instruction pattern
3022 @item @samp{ffs@var{m}2}
3023 Store into operand 0 one plus the index of the least significant 1-bit
3024 of operand 1. If operand 1 is zero, store zero. @var{m} is the mode
3025 of operand 0; operand 1's mode is specified by the instruction
3026 pattern, and the compiler will convert the operand to that mode before
3027 generating the instruction.
3029 The @code{ffs} built-in function of C always uses the mode which
3030 corresponds to the C data type @code{int}.
3032 @cindex @code{clz@var{m}2} instruction pattern
3033 @item @samp{clz@var{m}2}
3034 Store into operand 0 the number of leading 0-bits in @var{x}, starting
3035 at the most significant bit position. If @var{x} is 0, the result is
3036 undefined. @var{m} is the mode of operand 0; operand 1's mode is
3037 specified by the instruction pattern, and the compiler will convert the
3038 operand to that mode before generating the instruction.
3040 @cindex @code{ctz@var{m}2} instruction pattern
3041 @item @samp{ctz@var{m}2}
3042 Store into operand 0 the number of trailing 0-bits in @var{x}, starting
3043 at the least significant bit position. If @var{x} is 0, the result is
3044 undefined. @var{m} is the mode of operand 0; operand 1's mode is
3045 specified by the instruction pattern, and the compiler will convert the
3046 operand to that mode before generating the instruction.
3048 @cindex @code{popcount@var{m}2} instruction pattern
3049 @item @samp{popcount@var{m}2}
3050 Store into operand 0 the number of 1-bits in @var{x}. @var{m} is the
3051 mode of operand 0; operand 1's mode is specified by the instruction
3052 pattern, and the compiler will convert the operand to that mode before
3053 generating the instruction.
3055 @cindex @code{parity@var{m}2} instruction pattern
3056 @item @samp{parity@var{m}2}
3057 Store into operand 0 the parity of @var{x}, i.@:e. the number of 1-bits
3058 in @var{x} modulo 2. @var{m} is the mode of operand 0; operand 1's mode
3059 is specified by the instruction pattern, and the compiler will convert
3060 the operand to that mode before generating the instruction.
3062 @cindex @code{one_cmpl@var{m}2} instruction pattern
3063 @item @samp{one_cmpl@var{m}2}
3064 Store the bitwise-complement of operand 1 into operand 0.
3066 @cindex @code{cmp@var{m}} instruction pattern
3067 @item @samp{cmp@var{m}}
3068 Compare operand 0 and operand 1, and set the condition codes.
3069 The RTL pattern should look like this:
3072 (set (cc0) (compare (match_operand:@var{m} 0 @dots{})
3073 (match_operand:@var{m} 1 @dots{})))
3076 @cindex @code{tst@var{m}} instruction pattern
3077 @item @samp{tst@var{m}}
3078 Compare operand 0 against zero, and set the condition codes.
3079 The RTL pattern should look like this:
3082 (set (cc0) (match_operand:@var{m} 0 @dots{}))
3085 @samp{tst@var{m}} patterns should not be defined for machines that do
3086 not use @code{(cc0)}. Doing so would confuse the optimizer since it
3087 would no longer be clear which @code{set} operations were comparisons.
3088 The @samp{cmp@var{m}} patterns should be used instead.
3090 @cindex @code{movmem@var{m}} instruction pattern
3091 @item @samp{movmem@var{m}}
3092 Block move instruction. The destination and source blocks of memory
3093 are the first two operands, and both are @code{mem:BLK}s with an
3094 address in mode @code{Pmode}.
3096 The number of bytes to move is the third operand, in mode @var{m}.
3097 Usually, you specify @code{word_mode} for @var{m}. However, if you can
3098 generate better code knowing the range of valid lengths is smaller than
3099 those representable in a full word, you should provide a pattern with a
3100 mode corresponding to the range of values you can handle efficiently
3101 (e.g., @code{QImode} for values in the range 0--127; note we avoid numbers
3102 that appear negative) and also a pattern with @code{word_mode}.
3104 The fourth operand is the known shared alignment of the source and
3105 destination, in the form of a @code{const_int} rtx. Thus, if the
3106 compiler knows that both source and destination are word-aligned,
3107 it may provide the value 4 for this operand.
3109 Descriptions of multiple @code{movmem@var{m}} patterns can only be
3110 beneficial if the patterns for smaller modes have fewer restrictions
3111 on their first, second and fourth operands. Note that the mode @var{m}
3112 in @code{movmem@var{m}} does not impose any restriction on the mode of
3113 individually moved data units in the block.
3115 These patterns need not give special consideration to the possibility
3116 that the source and destination strings might overlap.
3118 @cindex @code{movstr} instruction pattern
3120 String copy instruction, with @code{stpcpy} semantics. Operand 0 is
3121 an output operand in mode @code{Pmode}. The addresses of the
3122 destination and source strings are operands 1 and 2, and both are
3123 @code{mem:BLK}s with addresses in mode @code{Pmode}. The execution of
3124 the expansion of this pattern should store in operand 0 the address in
3125 which the @code{NUL} terminator was stored in the destination string.
3127 @cindex @code{clrmem@var{m}} instruction pattern
3128 @item @samp{clrmem@var{m}}
3129 Block clear instruction. The destination string is the first operand,
3130 given as a @code{mem:BLK} whose address is in mode @code{Pmode}. The
3131 number of bytes to clear is the second operand, in mode @var{m}. See
3132 @samp{movmem@var{m}} for a discussion of the choice of mode.
3134 The third operand is the known alignment of the destination, in the form
3135 of a @code{const_int} rtx. Thus, if the compiler knows that the
3136 destination is word-aligned, it may provide the value 4 for this
3139 The use for multiple @code{clrmem@var{m}} is as for @code{movmem@var{m}}.
3141 @cindex @code{cmpstr@var{m}} instruction pattern
3142 @item @samp{cmpstr@var{m}}
3143 String compare instruction, with five operands. Operand 0 is the output;
3144 it has mode @var{m}. The remaining four operands are like the operands
3145 of @samp{movmem@var{m}}. The two memory blocks specified are compared
3146 byte by byte in lexicographic order starting at the beginning of each
3147 string. The instruction is not allowed to prefetch more than one byte
3148 at a time since either string may end in the first byte and reading past
3149 that may access an invalid page or segment and cause a fault. The
3150 effect of the instruction is to store a value in operand 0 whose sign
3151 indicates the result of the comparison.
3153 @cindex @code{cmpmem@var{m}} instruction pattern
3154 @item @samp{cmpmem@var{m}}
3155 Block compare instruction, with five operands like the operands
3156 of @samp{cmpstr@var{m}}. The two memory blocks specified are compared
3157 byte by byte in lexicographic order starting at the beginning of each
3158 block. Unlike @samp{cmpstr@var{m}} the instruction can prefetch
3159 any bytes in the two memory blocks. The effect of the instruction is
3160 to store a value in operand 0 whose sign indicates the result of the
3163 @cindex @code{strlen@var{m}} instruction pattern
3164 @item @samp{strlen@var{m}}
3165 Compute the length of a string, with three operands.
3166 Operand 0 is the result (of mode @var{m}), operand 1 is
3167 a @code{mem} referring to the first character of the string,
3168 operand 2 is the character to search for (normally zero),
3169 and operand 3 is a constant describing the known alignment
3170 of the beginning of the string.
3172 @cindex @code{float@var{mn}2} instruction pattern
3173 @item @samp{float@var{m}@var{n}2}
3174 Convert signed integer operand 1 (valid for fixed point mode @var{m}) to
3175 floating point mode @var{n} and store in operand 0 (which has mode
3178 @cindex @code{floatuns@var{mn}2} instruction pattern
3179 @item @samp{floatuns@var{m}@var{n}2}
3180 Convert unsigned integer operand 1 (valid for fixed point mode @var{m})
3181 to floating point mode @var{n} and store in operand 0 (which has mode
3184 @cindex @code{fix@var{mn}2} instruction pattern
3185 @item @samp{fix@var{m}@var{n}2}
3186 Convert operand 1 (valid for floating point mode @var{m}) to fixed
3187 point mode @var{n} as a signed number and store in operand 0 (which
3188 has mode @var{n}). This instruction's result is defined only when
3189 the value of operand 1 is an integer.
3191 If the machine description defines this pattern, it also needs to
3192 define the @code{ftrunc} pattern.
3194 @cindex @code{fixuns@var{mn}2} instruction pattern
3195 @item @samp{fixuns@var{m}@var{n}2}
3196 Convert operand 1 (valid for floating point mode @var{m}) to fixed
3197 point mode @var{n} as an unsigned number and store in operand 0 (which
3198 has mode @var{n}). This instruction's result is defined only when the
3199 value of operand 1 is an integer.
3201 @cindex @code{ftrunc@var{m}2} instruction pattern
3202 @item @samp{ftrunc@var{m}2}
3203 Convert operand 1 (valid for floating point mode @var{m}) to an
3204 integer value, still represented in floating point mode @var{m}, and
3205 store it in operand 0 (valid for floating point mode @var{m}).
3207 @cindex @code{fix_trunc@var{mn}2} instruction pattern
3208 @item @samp{fix_trunc@var{m}@var{n}2}
3209 Like @samp{fix@var{m}@var{n}2} but works for any floating point value
3210 of mode @var{m} by converting the value to an integer.
3212 @cindex @code{fixuns_trunc@var{mn}2} instruction pattern
3213 @item @samp{fixuns_trunc@var{m}@var{n}2}
3214 Like @samp{fixuns@var{m}@var{n}2} but works for any floating point
3215 value of mode @var{m} by converting the value to an integer.
3217 @cindex @code{trunc@var{mn}2} instruction pattern
3218 @item @samp{trunc@var{m}@var{n}2}
3219 Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and
3220 store in operand 0 (which has mode @var{n}). Both modes must be fixed
3221 point or both floating point.
3223 @cindex @code{extend@var{mn}2} instruction pattern
3224 @item @samp{extend@var{m}@var{n}2}
3225 Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
3226 store in operand 0 (which has mode @var{n}). Both modes must be fixed
3227 point or both floating point.
3229 @cindex @code{zero_extend@var{mn}2} instruction pattern
3230 @item @samp{zero_extend@var{m}@var{n}2}
3231 Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
3232 store in operand 0 (which has mode @var{n}). Both modes must be fixed
3235 @cindex @code{extv} instruction pattern
3237 Extract a bit-field from operand 1 (a register or memory operand), where
3238 operand 2 specifies the width in bits and operand 3 the starting bit,
3239 and store it in operand 0. Operand 0 must have mode @code{word_mode}.
3240 Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often
3241 @code{word_mode} is allowed only for registers. Operands 2 and 3 must
3242 be valid for @code{word_mode}.
3244 The RTL generation pass generates this instruction only with constants
3245 for operands 2 and 3.
3247 The bit-field value is sign-extended to a full word integer
3248 before it is stored in operand 0.
3250 @cindex @code{extzv} instruction pattern
3252 Like @samp{extv} except that the bit-field value is zero-extended.
3254 @cindex @code{insv} instruction pattern
3256 Store operand 3 (which must be valid for @code{word_mode}) into a
3257 bit-field in operand 0, where operand 1 specifies the width in bits and
3258 operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or
3259 @code{word_mode}; often @code{word_mode} is allowed only for registers.
3260 Operands 1 and 2 must be valid for @code{word_mode}.
3262 The RTL generation pass generates this instruction only with constants
3263 for operands 1 and 2.
3265 @cindex @code{mov@var{mode}cc} instruction pattern
3266 @item @samp{mov@var{mode}cc}
3267 Conditionally move operand 2 or operand 3 into operand 0 according to the
3268 comparison in operand 1. If the comparison is true, operand 2 is moved
3269 into operand 0, otherwise operand 3 is moved.
3271 The mode of the operands being compared need not be the same as the operands
3272 being moved. Some machines, sparc64 for example, have instructions that
3273 conditionally move an integer value based on the floating point condition
3274 codes and vice versa.
3276 If the machine does not have conditional move instructions, do not
3277 define these patterns.
3279 @cindex @code{add@var{mode}cc} instruction pattern
3280 @item @samp{add@var{mode}cc}
3281 Similar to @samp{mov@var{mode}cc} but for conditional addition. Conditionally
3282 move operand 2 or (operands 2 + operand 3) into operand 0 according to the
3283 comparison in operand 1. If the comparison is true, operand 2 is moved into
3284 operand 0, otherwise (operand 2 + operand 3) is moved.
3286 @cindex @code{s@var{cond}} instruction pattern
3287 @item @samp{s@var{cond}}
3288 Store zero or nonzero in the operand according to the condition codes.
3289 Value stored is nonzero iff the condition @var{cond} is true.
3290 @var{cond} is the name of a comparison operation expression code, such
3291 as @code{eq}, @code{lt} or @code{leu}.
3293 You specify the mode that the operand must have when you write the
3294 @code{match_operand} expression. The compiler automatically sees
3295 which mode you have used and supplies an operand of that mode.
3297 The value stored for a true condition must have 1 as its low bit, or
3298 else must be negative. Otherwise the instruction is not suitable and
3299 you should omit it from the machine description. You describe to the
3300 compiler exactly which value is stored by defining the macro
3301 @code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be
3302 found that can be used for all the @samp{s@var{cond}} patterns, you
3303 should omit those operations from the machine description.
3305 These operations may fail, but should do so only in relatively
3306 uncommon cases; if they would fail for common cases involving
3307 integer comparisons, it is best to omit these patterns.
3309 If these operations are omitted, the compiler will usually generate code
3310 that copies the constant one to the target and branches around an
3311 assignment of zero to the target. If this code is more efficient than
3312 the potential instructions used for the @samp{s@var{cond}} pattern
3313 followed by those required to convert the result into a 1 or a zero in
3314 @code{SImode}, you should omit the @samp{s@var{cond}} operations from
3315 the machine description.
3317 @cindex @code{b@var{cond}} instruction pattern
3318 @item @samp{b@var{cond}}
3319 Conditional branch instruction. Operand 0 is a @code{label_ref} that
3320 refers to the label to jump to. Jump if the condition codes meet
3321 condition @var{cond}.
3323 Some machines do not follow the model assumed here where a comparison
3324 instruction is followed by a conditional branch instruction. In that
3325 case, the @samp{cmp@var{m}} (and @samp{tst@var{m}}) patterns should
3326 simply store the operands away and generate all the required insns in a
3327 @code{define_expand} (@pxref{Expander Definitions}) for the conditional
3328 branch operations. All calls to expand @samp{b@var{cond}} patterns are
3329 immediately preceded by calls to expand either a @samp{cmp@var{m}}
3330 pattern or a @samp{tst@var{m}} pattern.
3332 Machines that use a pseudo register for the condition code value, or
3333 where the mode used for the comparison depends on the condition being
3334 tested, should also use the above mechanism. @xref{Jump Patterns}.
3336 The above discussion also applies to the @samp{mov@var{mode}cc} and
3337 @samp{s@var{cond}} patterns.
3339 @cindex @code{cbranch@var{mode}4} instruction pattern
3340 @item @samp{cbranch@var{mode}4}
3341 Conditional branch instruction combined with a compare instruction.
3342 Operand 0 is a comparison operator. Operand 1 and operand 2 are the
3343 first and second operands of the comparison, respectively. Operand 3
3344 is a @code{label_ref} that refers to the label to jump to.
3346 @cindex @code{jump} instruction pattern
3348 A jump inside a function; an unconditional branch. Operand 0 is the
3349 @code{label_ref} of the label to jump to. This pattern name is mandatory
3352 @cindex @code{call} instruction pattern
3354 Subroutine call instruction returning no value. Operand 0 is the
3355 function to call; operand 1 is the number of bytes of arguments pushed
3356 as a @code{const_int}; operand 2 is the number of registers used as
3359 On most machines, operand 2 is not actually stored into the RTL
3360 pattern. It is supplied for the sake of some RISC machines which need
3361 to put this information into the assembler code; they can put it in
3362 the RTL instead of operand 1.
3364 Operand 0 should be a @code{mem} RTX whose address is the address of the
3365 function. Note, however, that this address can be a @code{symbol_ref}
3366 expression even if it would not be a legitimate memory address on the
3367 target machine. If it is also not a valid argument for a call
3368 instruction, the pattern for this operation should be a
3369 @code{define_expand} (@pxref{Expander Definitions}) that places the
3370 address into a register and uses that register in the call instruction.
3372 @cindex @code{call_value} instruction pattern
3373 @item @samp{call_value}
3374 Subroutine call instruction returning a value. Operand 0 is the hard
3375 register in which the value is returned. There are three more
3376 operands, the same as the three operands of the @samp{call}
3377 instruction (but with numbers increased by one).
3379 Subroutines that return @code{BLKmode} objects use the @samp{call}
3382 @cindex @code{call_pop} instruction pattern
3383 @cindex @code{call_value_pop} instruction pattern
3384 @item @samp{call_pop}, @samp{call_value_pop}
3385 Similar to @samp{call} and @samp{call_value}, except used if defined and
3386 if @code{RETURN_POPS_ARGS} is nonzero. They should emit a @code{parallel}
3387 that contains both the function call and a @code{set} to indicate the
3388 adjustment made to the frame pointer.
3390 For machines where @code{RETURN_POPS_ARGS} can be nonzero, the use of these
3391 patterns increases the number of functions for which the frame pointer
3392 can be eliminated, if desired.
3394 @cindex @code{untyped_call} instruction pattern
3395 @item @samp{untyped_call}
3396 Subroutine call instruction returning a value of any type. Operand 0 is
3397 the function to call; operand 1 is a memory location where the result of
3398 calling the function is to be stored; operand 2 is a @code{parallel}
3399 expression where each element is a @code{set} expression that indicates
3400 the saving of a function return value into the result block.
3402 This instruction pattern should be defined to support
3403 @code{__builtin_apply} on machines where special instructions are needed
3404 to call a subroutine with arbitrary arguments or to save the value
3405 returned. This instruction pattern is required on machines that have
3406 multiple registers that can hold a return value
3407 (i.e.@: @code{FUNCTION_VALUE_REGNO_P} is true for more than one register).
3409 @cindex @code{return} instruction pattern
3411 Subroutine return instruction. This instruction pattern name should be
3412 defined only if a single instruction can do all the work of returning
3415 Like the @samp{mov@var{m}} patterns, this pattern is also used after the
3416 RTL generation phase. In this case it is to support machines where
3417 multiple instructions are usually needed to return from a function, but
3418 some class of functions only requires one instruction to implement a
3419 return. Normally, the applicable functions are those which do not need
3420 to save any registers or allocate stack space.
3422 @findex reload_completed
3423 @findex leaf_function_p
3424 For such machines, the condition specified in this pattern should only
3425 be true when @code{reload_completed} is nonzero and the function's
3426 epilogue would only be a single instruction. For machines with register
3427 windows, the routine @code{leaf_function_p} may be used to determine if
3428 a register window push is required.
3430 Machines that have conditional return instructions should define patterns
3436 (if_then_else (match_operator
3437 0 "comparison_operator"
3438 [(cc0) (const_int 0)])
3445 where @var{condition} would normally be the same condition specified on the
3446 named @samp{return} pattern.
3448 @cindex @code{untyped_return} instruction pattern
3449 @item @samp{untyped_return}
3450 Untyped subroutine return instruction. This instruction pattern should
3451 be defined to support @code{__builtin_return} on machines where special
3452 instructions are needed to return a value of any type.
3454 Operand 0 is a memory location where the result of calling a function
3455 with @code{__builtin_apply} is stored; operand 1 is a @code{parallel}
3456 expression where each element is a @code{set} expression that indicates
3457 the restoring of a function return value from the result block.
3459 @cindex @code{nop} instruction pattern
3461 No-op instruction. This instruction pattern name should always be defined
3462 to output a no-op in assembler code. @code{(const_int 0)} will do as an
3465 @cindex @code{indirect_jump} instruction pattern
3466 @item @samp{indirect_jump}
3467 An instruction to jump to an address which is operand zero.
3468 This pattern name is mandatory on all machines.
3470 @cindex @code{casesi} instruction pattern
3472 Instruction to jump through a dispatch table, including bounds checking.
3473 This instruction takes five operands:
3477 The index to dispatch on, which has mode @code{SImode}.
3480 The lower bound for indices in the table, an integer constant.
3483 The total range of indices in the table---the largest index
3484 minus the smallest one (both inclusive).
3487 A label that precedes the table itself.
3490 A label to jump to if the index has a value outside the bounds.
3491 (If the machine-description macro @code{CASE_DROPS_THROUGH} is defined,
3492 then an out-of-bounds index drops through to the code following
3493 the jump table instead of jumping to this label. In that case,
3494 this label is not actually used by the @samp{casesi} instruction,
3495 but it is always provided as an operand.)
3498 The table is a @code{addr_vec} or @code{addr_diff_vec} inside of a
3499 @code{jump_insn}. The number of elements in the table is one plus the
3500 difference between the upper bound and the lower bound.
3502 @cindex @code{tablejump} instruction pattern
3503 @item @samp{tablejump}
3504 Instruction to jump to a variable address. This is a low-level
3505 capability which can be used to implement a dispatch table when there
3506 is no @samp{casesi} pattern.
3508 This pattern requires two operands: the address or offset, and a label
3509 which should immediately precede the jump table. If the macro
3510 @code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first
3511 operand is an offset which counts from the address of the table; otherwise,
3512 it is an absolute address to jump to. In either case, the first operand has
3515 The @samp{tablejump} insn is always the last insn before the jump
3516 table it uses. Its assembler code normally has no need to use the
3517 second operand, but you should incorporate it in the RTL pattern so
3518 that the jump optimizer will not delete the table as unreachable code.
3521 @cindex @code{decrement_and_branch_until_zero} instruction pattern
3522 @item @samp{decrement_and_branch_until_zero}
3523 Conditional branch instruction that decrements a register and
3524 jumps if the register is nonzero. Operand 0 is the register to
3525 decrement and test; operand 1 is the label to jump to if the
3526 register is nonzero. @xref{Looping Patterns}.
3528 This optional instruction pattern is only used by the combiner,
3529 typically for loops reversed by the loop optimizer when strength
3530 reduction is enabled.
3532 @cindex @code{doloop_end} instruction pattern
3533 @item @samp{doloop_end}
3534 Conditional branch instruction that decrements a register and jumps if
3535 the register is nonzero. This instruction takes five operands: Operand
3536 0 is the register to decrement and test; operand 1 is the number of loop
3537 iterations as a @code{const_int} or @code{const0_rtx} if this cannot be
3538 determined until run-time; operand 2 is the actual or estimated maximum
3539 number of iterations as a @code{const_int}; operand 3 is the number of
3540 enclosed loops as a @code{const_int} (an innermost loop has a value of
3541 1); operand 4 is the label to jump to if the register is nonzero.
3542 @xref{Looping Patterns}.
3544 This optional instruction pattern should be defined for machines with
3545 low-overhead looping instructions as the loop optimizer will try to
3546 modify suitable loops to utilize it. If nested low-overhead looping is
3547 not supported, use a @code{define_expand} (@pxref{Expander Definitions})
3548 and make the pattern fail if operand 3 is not @code{const1_rtx}.
3549 Similarly, if the actual or estimated maximum number of iterations is
3550 too large for this instruction, make it fail.
3552 @cindex @code{doloop_begin} instruction pattern
3553 @item @samp{doloop_begin}
3554 Companion instruction to @code{doloop_end} required for machines that
3555 need to perform some initialization, such as loading special registers
3556 used by a low-overhead looping instruction. If initialization insns do
3557 not always need to be emitted, use a @code{define_expand}
3558 (@pxref{Expander Definitions}) and make it fail.
3561 @cindex @code{canonicalize_funcptr_for_compare} instruction pattern
3562 @item @samp{canonicalize_funcptr_for_compare}
3563 Canonicalize the function pointer in operand 1 and store the result
3566 Operand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1
3567 may be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc
3568 and also has mode @code{Pmode}.
3570 Canonicalization of a function pointer usually involves computing
3571 the address of the function which would be called if the function
3572 pointer were used in an indirect call.
3574 Only define this pattern if function pointers on the target machine
3575 can have different values but still call the same function when
3576 used in an indirect call.
3578 @cindex @code{save_stack_block} instruction pattern
3579 @cindex @code{save_stack_function} instruction pattern
3580 @cindex @code{save_stack_nonlocal} instruction pattern
3581 @cindex @code{restore_stack_block} instruction pattern
3582 @cindex @code{restore_stack_function} instruction pattern
3583 @cindex @code{restore_stack_nonlocal} instruction pattern
3584 @item @samp{save_stack_block}
3585 @itemx @samp{save_stack_function}
3586 @itemx @samp{save_stack_nonlocal}
3587 @itemx @samp{restore_stack_block}
3588 @itemx @samp{restore_stack_function}
3589 @itemx @samp{restore_stack_nonlocal}
3590 Most machines save and restore the stack pointer by copying it to or
3591 from an object of mode @code{Pmode}. Do not define these patterns on
3594 Some machines require special handling for stack pointer saves and
3595 restores. On those machines, define the patterns corresponding to the
3596 non-standard cases by using a @code{define_expand} (@pxref{Expander
3597 Definitions}) that produces the required insns. The three types of
3598 saves and restores are:
3602 @samp{save_stack_block} saves the stack pointer at the start of a block
3603 that allocates a variable-sized object, and @samp{restore_stack_block}
3604 restores the stack pointer when the block is exited.
3607 @samp{save_stack_function} and @samp{restore_stack_function} do a
3608 similar job for the outermost block of a function and are used when the
3609 function allocates variable-sized objects or calls @code{alloca}. Only
3610 the epilogue uses the restored stack pointer, allowing a simpler save or
3611 restore sequence on some machines.
3614 @samp{save_stack_nonlocal} is used in functions that contain labels
3615 branched to by nested functions. It saves the stack pointer in such a
3616 way that the inner function can use @samp{restore_stack_nonlocal} to
3617 restore the stack pointer. The compiler generates code to restore the
3618 frame and argument pointer registers, but some machines require saving
3619 and restoring additional data such as register window information or
3620 stack backchains. Place insns in these patterns to save and restore any
3624 When saving the stack pointer, operand 0 is the save area and operand 1
3625 is the stack pointer. The mode used to allocate the save area defaults
3626 to @code{Pmode} but you can override that choice by defining the
3627 @code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must
3628 specify an integral mode, or @code{VOIDmode} if no save area is needed
3629 for a particular type of save (either because no save is needed or
3630 because a machine-specific save area can be used). Operand 0 is the
3631 stack pointer and operand 1 is the save area for restore operations. If
3632 @samp{save_stack_block} is defined, operand 0 must not be
3633 @code{VOIDmode} since these saves can be arbitrarily nested.
3635 A save area is a @code{mem} that is at a constant offset from
3636 @code{virtual_stack_vars_rtx} when the stack pointer is saved for use by
3637 nonlocal gotos and a @code{reg} in the other two cases.
3639 @cindex @code{allocate_stack} instruction pattern
3640 @item @samp{allocate_stack}
3641 Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from
3642 the stack pointer to create space for dynamically allocated data.
3644 Store the resultant pointer to this space into operand 0. If you
3645 are allocating space from the main stack, do this by emitting a
3646 move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0.
3647 If you are allocating the space elsewhere, generate code to copy the
3648 location of the space to operand 0. In the latter case, you must
3649 ensure this space gets freed when the corresponding space on the main
3652 Do not define this pattern if all that must be done is the subtraction.
3653 Some machines require other operations such as stack probes or
3654 maintaining the back chain. Define this pattern to emit those
3655 operations in addition to updating the stack pointer.
3657 @cindex @code{check_stack} instruction pattern
3658 @item @samp{check_stack}
3659 If stack checking cannot be done on your system by probing the stack with
3660 a load or store instruction (@pxref{Stack Checking}), define this pattern
3661 to perform the needed check and signaling an error if the stack
3662 has overflowed. The single operand is the location in the stack furthest
3663 from the current stack pointer that you need to validate. Normally,
3664 on machines where this pattern is needed, you would obtain the stack
3665 limit from a global or thread-specific variable or register.
3667 @cindex @code{nonlocal_goto} instruction pattern
3668 @item @samp{nonlocal_goto}
3669 Emit code to generate a non-local goto, e.g., a jump from one function
3670 to a label in an outer function. This pattern has four arguments,
3671 each representing a value to be used in the jump. The first
3672 argument is to be loaded into the frame pointer, the second is
3673 the address to branch to (code to dispatch to the actual label),
3674 the third is the address of a location where the stack is saved,
3675 and the last is the address of the label, to be placed in the
3676 location for the incoming static chain.
3678 On most machines you need not define this pattern, since GCC will
3679 already generate the correct code, which is to load the frame pointer
3680 and static chain, restore the stack (using the
3681 @samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly
3682 to the dispatcher. You need only define this pattern if this code will
3683 not work on your machine.
3685 @cindex @code{nonlocal_goto_receiver} instruction pattern
3686 @item @samp{nonlocal_goto_receiver}
3687 This pattern, if defined, contains code needed at the target of a
3688 nonlocal goto after the code already generated by GCC@. You will not
3689 normally need to define this pattern. A typical reason why you might
3690 need this pattern is if some value, such as a pointer to a global table,
3691 must be restored when the frame pointer is restored. Note that a nonlocal
3692 goto only occurs within a unit-of-translation, so a global table pointer
3693 that is shared by all functions of a given module need not be restored.
3694 There are no arguments.
3696 @cindex @code{exception_receiver} instruction pattern
3697 @item @samp{exception_receiver}
3698 This pattern, if defined, contains code needed at the site of an
3699 exception handler that isn't needed at the site of a nonlocal goto. You
3700 will not normally need to define this pattern. A typical reason why you
3701 might need this pattern is if some value, such as a pointer to a global
3702 table, must be restored after control flow is branched to the handler of
3703 an exception. There are no arguments.
3705 @cindex @code{builtin_setjmp_setup} instruction pattern
3706 @item @samp{builtin_setjmp_setup}
3707 This pattern, if defined, contains additional code needed to initialize
3708 the @code{jmp_buf}. You will not normally need to define this pattern.
3709 A typical reason why you might need this pattern is if some value, such
3710 as a pointer to a global table, must be restored. Though it is
3711 preferred that the pointer value be recalculated if possible (given the
3712 address of a label for instance). The single argument is a pointer to
3713 the @code{jmp_buf}. Note that the buffer is five words long and that
3714 the first three are normally used by the generic mechanism.
3716 @cindex @code{builtin_setjmp_receiver} instruction pattern
3717 @item @samp{builtin_setjmp_receiver}
3718 This pattern, if defined, contains code needed at the site of an
3719 built-in setjmp that isn't needed at the site of a nonlocal goto. You
3720 will not normally need to define this pattern. A typical reason why you
3721 might need this pattern is if some value, such as a pointer to a global
3722 table, must be restored. It takes one argument, which is the label
3723 to which builtin_longjmp transfered control; this pattern may be emitted
3724 at a small offset from that label.
3726 @cindex @code{builtin_longjmp} instruction pattern
3727 @item @samp{builtin_longjmp}
3728 This pattern, if defined, performs the entire action of the longjmp.
3729 You will not normally need to define this pattern unless you also define
3730 @code{builtin_setjmp_setup}. The single argument is a pointer to the
3733 @cindex @code{eh_return} instruction pattern
3734 @item @samp{eh_return}
3735 This pattern, if defined, affects the way @code{__builtin_eh_return},
3736 and thence the call frame exception handling library routines, are
3737 built. It is intended to handle non-trivial actions needed along
3738 the abnormal return path.
3740 The address of the exception handler to which the function should return
3741 is passed as operand to this pattern. It will normally need to copied by
3742 the pattern to some special register or memory location.
3743 If the pattern needs to determine the location of the target call
3744 frame in order to do so, it may use @code{EH_RETURN_STACKADJ_RTX},
3745 if defined; it will have already been assigned.
3747 If this pattern is not defined, the default action will be to simply
3748 copy the return address to @code{EH_RETURN_HANDLER_RTX}. Either
3749 that macro or this pattern needs to be defined if call frame exception
3750 handling is to be used.
3752 @cindex @code{prologue} instruction pattern
3753 @anchor{prologue instruction pattern}
3754 @item @samp{prologue}
3755 This pattern, if defined, emits RTL for entry to a function. The function
3756 entry is responsible for setting up the stack frame, initializing the frame
3757 pointer register, saving callee saved registers, etc.
3759 Using a prologue pattern is generally preferred over defining
3760 @code{TARGET_ASM_FUNCTION_PROLOGUE} to emit assembly code for the prologue.
3762 The @code{prologue} pattern is particularly useful for targets which perform
3763 instruction scheduling.
3765 @cindex @code{epilogue} instruction pattern
3766 @anchor{epilogue instruction pattern}
3767 @item @samp{epilogue}
3768 This pattern emits RTL for exit from a function. The function
3769 exit is responsible for deallocating the stack frame, restoring callee saved
3770 registers and emitting the return instruction.
3772 Using an epilogue pattern is generally preferred over defining
3773 @code{TARGET_ASM_FUNCTION_EPILOGUE} to emit assembly code for the epilogue.
3775 The @code{epilogue} pattern is particularly useful for targets which perform
3776 instruction scheduling or which have delay slots for their return instruction.
3778 @cindex @code{sibcall_epilogue} instruction pattern
3779 @item @samp{sibcall_epilogue}
3780 This pattern, if defined, emits RTL for exit from a function without the final
3781 branch back to the calling function. This pattern will be emitted before any
3782 sibling call (aka tail call) sites.
3784 The @code{sibcall_epilogue} pattern must not clobber any arguments used for
3785 parameter passing or any stack slots for arguments passed to the current
3788 @cindex @code{trap} instruction pattern
3790 This pattern, if defined, signals an error, typically by causing some
3791 kind of signal to be raised. Among other places, it is used by the Java
3792 front end to signal `invalid array index' exceptions.
3794 @cindex @code{conditional_trap} instruction pattern
3795 @item @samp{conditional_trap}
3796 Conditional trap instruction. Operand 0 is a piece of RTL which
3797 performs a comparison. Operand 1 is the trap code, an integer.
3799 A typical @code{conditional_trap} pattern looks like
3802 (define_insn "conditional_trap"
3803 [(trap_if (match_operator 0 "trap_operator"
3804 [(cc0) (const_int 0)])
3805 (match_operand 1 "const_int_operand" "i"))]
3810 @cindex @code{prefetch} instruction pattern
3811 @item @samp{prefetch}
3813 This pattern, if defined, emits code for a non-faulting data prefetch
3814 instruction. Operand 0 is the address of the memory to prefetch. Operand 1
3815 is a constant 1 if the prefetch is preparing for a write to the memory
3816 address, or a constant 0 otherwise. Operand 2 is the expected degree of
3817 temporal locality of the data and is a value between 0 and 3, inclusive; 0
3818 means that the data has no temporal locality, so it need not be left in the
3819 cache after the access; 3 means that the data has a high degree of temporal
3820 locality and should be left in all levels of cache possible; 1 and 2 mean,
3821 respectively, a low or moderate degree of temporal locality.
3823 Targets that do not support write prefetches or locality hints can ignore
3824 the values of operands 1 and 2.
3829 @c Each of the following nodes are wrapped in separate
3830 @c "@ifset INTERNALS" to work around memory limits for the default
3831 @c configuration in older tetex distributions. Known to not work:
3832 @c tetex-1.0.7, known to work: tetex-2.0.2.
3834 @node Pattern Ordering
3835 @section When the Order of Patterns Matters
3836 @cindex Pattern Ordering
3837 @cindex Ordering of Patterns
3839 Sometimes an insn can match more than one instruction pattern. Then the
3840 pattern that appears first in the machine description is the one used.
3841 Therefore, more specific patterns (patterns that will match fewer things)
3842 and faster instructions (those that will produce better code when they
3843 do match) should usually go first in the description.
3845 In some cases the effect of ordering the patterns can be used to hide
3846 a pattern when it is not valid. For example, the 68000 has an
3847 instruction for converting a fullword to floating point and another
3848 for converting a byte to floating point. An instruction converting
3849 an integer to floating point could match either one. We put the
3850 pattern to convert the fullword first to make sure that one will
3851 be used rather than the other. (Otherwise a large integer might
3852 be generated as a single-byte immediate quantity, which would not work.)
3853 Instead of using this pattern ordering it would be possible to make the
3854 pattern for convert-a-byte smart enough to deal properly with any
3859 @node Dependent Patterns
3860 @section Interdependence of Patterns
3861 @cindex Dependent Patterns
3862 @cindex Interdependence of Patterns
3864 Every machine description must have a named pattern for each of the
3865 conditional branch names @samp{b@var{cond}}. The recognition template
3866 must always have the form
3870 (if_then_else (@var{cond} (cc0) (const_int 0))
3871 (label_ref (match_operand 0 "" ""))
3876 In addition, every machine description must have an anonymous pattern
3877 for each of the possible reverse-conditional branches. Their templates
3882 (if_then_else (@var{cond} (cc0) (const_int 0))
3884 (label_ref (match_operand 0 "" ""))))
3888 They are necessary because jump optimization can turn direct-conditional
3889 branches into reverse-conditional branches.
3891 It is often convenient to use the @code{match_operator} construct to
3892 reduce the number of patterns that must be specified for branches. For
3898 (if_then_else (match_operator 0 "comparison_operator"
3899 [(cc0) (const_int 0)])
3901 (label_ref (match_operand 1 "" ""))))]
3906 In some cases machines support instructions identical except for the
3907 machine mode of one or more operands. For example, there may be
3908 ``sign-extend halfword'' and ``sign-extend byte'' instructions whose
3912 (set (match_operand:SI 0 @dots{})
3913 (extend:SI (match_operand:HI 1 @dots{})))
3915 (set (match_operand:SI 0 @dots{})
3916 (extend:SI (match_operand:QI 1 @dots{})))
3920 Constant integers do not specify a machine mode, so an instruction to
3921 extend a constant value could match either pattern. The pattern it
3922 actually will match is the one that appears first in the file. For correct
3923 results, this must be the one for the widest possible mode (@code{HImode},
3924 here). If the pattern matches the @code{QImode} instruction, the results
3925 will be incorrect if the constant value does not actually fit that mode.
3927 Such instructions to extend constants are rarely generated because they are
3928 optimized away, but they do occasionally happen in nonoptimized
3931 If a constraint in a pattern allows a constant, the reload pass may
3932 replace a register with a constant permitted by the constraint in some
3933 cases. Similarly for memory references. Because of this substitution,
3934 you should not provide separate patterns for increment and decrement
3935 instructions. Instead, they should be generated from the same pattern
3936 that supports register-register add insns by examining the operands and
3937 generating the appropriate machine instruction.
3942 @section Defining Jump Instruction Patterns
3943 @cindex jump instruction patterns
3944 @cindex defining jump instruction patterns
3946 For most machines, GCC assumes that the machine has a condition code.
3947 A comparison insn sets the condition code, recording the results of both
3948 signed and unsigned comparison of the given operands. A separate branch
3949 insn tests the condition code and branches or not according its value.
3950 The branch insns come in distinct signed and unsigned flavors. Many
3951 common machines, such as the VAX, the 68000 and the 32000, work this
3954 Some machines have distinct signed and unsigned compare instructions, and
3955 only one set of conditional branch instructions. The easiest way to handle
3956 these machines is to treat them just like the others until the final stage
3957 where assembly code is written. At this time, when outputting code for the
3958 compare instruction, peek ahead at the following branch using
3959 @code{next_cc0_user (insn)}. (The variable @code{insn} refers to the insn
3960 being output, in the output-writing code in an instruction pattern.) If
3961 the RTL says that is an unsigned branch, output an unsigned compare;
3962 otherwise output a signed compare. When the branch itself is output, you
3963 can treat signed and unsigned branches identically.
3965 The reason you can do this is that GCC always generates a pair of
3966 consecutive RTL insns, possibly separated by @code{note} insns, one to
3967 set the condition code and one to test it, and keeps the pair inviolate
3970 To go with this technique, you must define the machine-description macro
3971 @code{NOTICE_UPDATE_CC} to do @code{CC_STATUS_INIT}; in other words, no
3972 compare instruction is superfluous.
3974 Some machines have compare-and-branch instructions and no condition code.
3975 A similar technique works for them. When it is time to ``output'' a
3976 compare instruction, record its operands in two static variables. When
3977 outputting the branch-on-condition-code instruction that follows, actually
3978 output a compare-and-branch instruction that uses the remembered operands.
3980 It also works to define patterns for compare-and-branch instructions.
3981 In optimizing compilation, the pair of compare and branch instructions
3982 will be combined according to these patterns. But this does not happen
3983 if optimization is not requested. So you must use one of the solutions
3984 above in addition to any special patterns you define.
3986 In many RISC machines, most instructions do not affect the condition
3987 code and there may not even be a separate condition code register. On
3988 these machines, the restriction that the definition and use of the
3989 condition code be adjacent insns is not necessary and can prevent
3990 important optimizations. For example, on the IBM RS/6000, there is a
3991 delay for taken branches unless the condition code register is set three
3992 instructions earlier than the conditional branch. The instruction
3993 scheduler cannot perform this optimization if it is not permitted to
3994 separate the definition and use of the condition code register.
3996 On these machines, do not use @code{(cc0)}, but instead use a register
3997 to represent the condition code. If there is a specific condition code
3998 register in the machine, use a hard register. If the condition code or
3999 comparison result can be placed in any general register, or if there are
4000 multiple condition registers, use a pseudo register.
4002 @findex prev_cc0_setter
4003 @findex next_cc0_user
4004 On some machines, the type of branch instruction generated may depend on
4005 the way the condition code was produced; for example, on the 68k and
4006 SPARC, setting the condition code directly from an add or subtract
4007 instruction does not clear the overflow bit the way that a test
4008 instruction does, so a different branch instruction must be used for
4009 some conditional branches. For machines that use @code{(cc0)}, the set
4010 and use of the condition code must be adjacent (separated only by
4011 @code{note} insns) allowing flags in @code{cc_status} to be used.
4012 (@xref{Condition Code}.) Also, the comparison and branch insns can be
4013 located from each other by using the functions @code{prev_cc0_setter}
4014 and @code{next_cc0_user}.
4016 However, this is not true on machines that do not use @code{(cc0)}. On
4017 those machines, no assumptions can be made about the adjacency of the
4018 compare and branch insns and the above methods cannot be used. Instead,
4019 we use the machine mode of the condition code register to record
4020 different formats of the condition code register.
4022 Registers used to store the condition code value should have a mode that
4023 is in class @code{MODE_CC}. Normally, it will be @code{CCmode}. If
4024 additional modes are required (as for the add example mentioned above in
4025 the SPARC), define the macro @code{EXTRA_CC_MODES} to list the
4026 additional modes required (@pxref{Condition Code}). Also define
4027 @code{SELECT_CC_MODE} to choose a mode given an operand of a compare.
4029 If it is known during RTL generation that a different mode will be
4030 required (for example, if the machine has separate compare instructions
4031 for signed and unsigned quantities, like most IBM processors), they can
4032 be specified at that time.
4034 If the cases that require different modes would be made by instruction
4035 combination, the macro @code{SELECT_CC_MODE} determines which machine
4036 mode should be used for the comparison result. The patterns should be
4037 written using that mode. To support the case of the add on the SPARC
4038 discussed above, we have the pattern
4042 [(set (reg:CC_NOOV 0)
4044 (plus:SI (match_operand:SI 0 "register_operand" "%r")
4045 (match_operand:SI 1 "arith_operand" "rI"))
4051 The @code{SELECT_CC_MODE} macro on the SPARC returns @code{CC_NOOVmode}
4052 for comparisons whose argument is a @code{plus}.
4056 @node Looping Patterns
4057 @section Defining Looping Instruction Patterns
4058 @cindex looping instruction patterns
4059 @cindex defining looping instruction patterns
4061 Some machines have special jump instructions that can be utilized to
4062 make loops more efficient. A common example is the 68000 @samp{dbra}
4063 instruction which performs a decrement of a register and a branch if the
4064 result was greater than zero. Other machines, in particular digital
4065 signal processors (DSPs), have special block repeat instructions to
4066 provide low-overhead loop support. For example, the TI TMS320C3x/C4x
4067 DSPs have a block repeat instruction that loads special registers to
4068 mark the top and end of a loop and to count the number of loop
4069 iterations. This avoids the need for fetching and executing a
4070 @samp{dbra}-like instruction and avoids pipeline stalls associated with
4073 GCC has three special named patterns to support low overhead looping.
4074 They are @samp{decrement_and_branch_until_zero}, @samp{doloop_begin},
4075 and @samp{doloop_end}. The first pattern,
4076 @samp{decrement_and_branch_until_zero}, is not emitted during RTL
4077 generation but may be emitted during the instruction combination phase.
4078 This requires the assistance of the loop optimizer, using information
4079 collected during strength reduction, to reverse a loop to count down to
4080 zero. Some targets also require the loop optimizer to add a
4081 @code{REG_NONNEG} note to indicate that the iteration count is always
4082 positive. This is needed if the target performs a signed loop
4083 termination test. For example, the 68000 uses a pattern similar to the
4084 following for its @code{dbra} instruction:
4088 (define_insn "decrement_and_branch_until_zero"
4091 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
4094 (label_ref (match_operand 1 "" ""))
4097 (plus:SI (match_dup 0)
4099 "find_reg_note (insn, REG_NONNEG, 0)"
4104 Note that since the insn is both a jump insn and has an output, it must
4105 deal with its own reloads, hence the `m' constraints. Also note that
4106 since this insn is generated by the instruction combination phase
4107 combining two sequential insns together into an implicit parallel insn,
4108 the iteration counter needs to be biased by the same amount as the
4109 decrement operation, in this case @minus{}1. Note that the following similar
4110 pattern will not be matched by the combiner.
4114 (define_insn "decrement_and_branch_until_zero"
4117 (ge (match_operand:SI 0 "general_operand" "+d*am")
4119 (label_ref (match_operand 1 "" ""))
4122 (plus:SI (match_dup 0)
4124 "find_reg_note (insn, REG_NONNEG, 0)"
4129 The other two special looping patterns, @samp{doloop_begin} and
4130 @samp{doloop_end}, are emitted by the loop optimizer for certain
4131 well-behaved loops with a finite number of loop iterations using
4132 information collected during strength reduction.
4134 The @samp{doloop_end} pattern describes the actual looping instruction
4135 (or the implicit looping operation) and the @samp{doloop_begin} pattern
4136 is an optional companion pattern that can be used for initialization
4137 needed for some low-overhead looping instructions.
4139 Note that some machines require the actual looping instruction to be
4140 emitted at the top of the loop (e.g., the TMS320C3x/C4x DSPs). Emitting
4141 the true RTL for a looping instruction at the top of the loop can cause
4142 problems with flow analysis. So instead, a dummy @code{doloop} insn is
4143 emitted at the end of the loop. The machine dependent reorg pass checks
4144 for the presence of this @code{doloop} insn and then searches back to
4145 the top of the loop, where it inserts the true looping insn (provided
4146 there are no instructions in the loop which would cause problems). Any
4147 additional labels can be emitted at this point. In addition, if the
4148 desired special iteration counter register was not allocated, this
4149 machine dependent reorg pass could emit a traditional compare and jump
4152 The essential difference between the
4153 @samp{decrement_and_branch_until_zero} and the @samp{doloop_end}
4154 patterns is that the loop optimizer allocates an additional pseudo
4155 register for the latter as an iteration counter. This pseudo register
4156 cannot be used within the loop (i.e., general induction variables cannot
4157 be derived from it), however, in many cases the loop induction variable
4158 may become redundant and removed by the flow pass.
4163 @node Insn Canonicalizations
4164 @section Canonicalization of Instructions
4165 @cindex canonicalization of instructions
4166 @cindex insn canonicalization
4168 There are often cases where multiple RTL expressions could represent an
4169 operation performed by a single machine instruction. This situation is
4170 most commonly encountered with logical, branch, and multiply-accumulate
4171 instructions. In such cases, the compiler attempts to convert these
4172 multiple RTL expressions into a single canonical form to reduce the
4173 number of insn patterns required.
4175 In addition to algebraic simplifications, following canonicalizations
4180 For commutative and comparison operators, a constant is always made the
4181 second operand. If a machine only supports a constant as the second
4182 operand, only patterns that match a constant in the second operand need
4186 For associative operators, a sequence of operators will always chain
4187 to the left; for instance, only the left operand of an integer @code{plus}
4188 can itself be a @code{plus}. @code{and}, @code{ior}, @code{xor},
4189 @code{plus}, @code{mult}, @code{smin}, @code{smax}, @code{umin}, and
4190 @code{umax} are associative when applied to integers, and sometimes to
4194 @cindex @code{neg}, canonicalization of
4195 @cindex @code{not}, canonicalization of
4196 @cindex @code{mult}, canonicalization of
4197 @cindex @code{plus}, canonicalization of
4198 @cindex @code{minus}, canonicalization of
4199 For these operators, if only one operand is a @code{neg}, @code{not},
4200 @code{mult}, @code{plus}, or @code{minus} expression, it will be the
4204 In combinations of @code{neg}, @code{mult}, @code{plus}, and
4205 @code{minus}, the @code{neg} operations (if any) will be moved inside
4206 the operations as far as possible. For instance,
4207 @code{(neg (mult A B))} is canonicalized as @code{(mult (neg A) B)}, but
4208 @code{(plus (mult (neg A) B) C)} is canonicalized as
4209 @code{(minus A (mult B C))}.
4211 @cindex @code{compare}, canonicalization of
4213 For the @code{compare} operator, a constant is always the second operand
4214 on machines where @code{cc0} is used (@pxref{Jump Patterns}). On other
4215 machines, there are rare cases where the compiler might want to construct
4216 a @code{compare} with a constant as the first operand. However, these
4217 cases are not common enough for it to be worthwhile to provide a pattern
4218 matching a constant as the first operand unless the machine actually has
4219 such an instruction.
4221 An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or
4222 @code{minus} is made the first operand under the same conditions as
4226 @code{(minus @var{x} (const_int @var{n}))} is converted to
4227 @code{(plus @var{x} (const_int @var{-n}))}.
4230 Within address computations (i.e., inside @code{mem}), a left shift is
4231 converted into the appropriate multiplication by a power of two.
4233 @cindex @code{ior}, canonicalization of
4234 @cindex @code{and}, canonicalization of
4235 @cindex De Morgan's law
4237 De`Morgan's Law is used to move bitwise negation inside a bitwise
4238 logical-and or logical-or operation. If this results in only one
4239 operand being a @code{not} expression, it will be the first one.
4241 A machine that has an instruction that performs a bitwise logical-and of one
4242 operand with the bitwise negation of the other should specify the pattern
4243 for that instruction as
4247 [(set (match_operand:@var{m} 0 @dots{})
4248 (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
4249 (match_operand:@var{m} 2 @dots{})))]
4255 Similarly, a pattern for a ``NAND'' instruction should be written
4259 [(set (match_operand:@var{m} 0 @dots{})
4260 (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
4261 (not:@var{m} (match_operand:@var{m} 2 @dots{}))))]
4266 In both cases, it is not necessary to include patterns for the many
4267 logically equivalent RTL expressions.
4269 @cindex @code{xor}, canonicalization of
4271 The only possible RTL expressions involving both bitwise exclusive-or
4272 and bitwise negation are @code{(xor:@var{m} @var{x} @var{y})}
4273 and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}.
4276 The sum of three items, one of which is a constant, will only appear in
4280 (plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant})
4284 On machines that do not use @code{cc0},
4285 @code{(compare @var{x} (const_int 0))} will be converted to
4288 @cindex @code{zero_extract}, canonicalization of
4289 @cindex @code{sign_extract}, canonicalization of
4291 Equality comparisons of a group of bits (usually a single bit) with zero
4292 will be written using @code{zero_extract} rather than the equivalent
4293 @code{and} or @code{sign_extract} operations.
4299 @node Expander Definitions
4300 @section Defining RTL Sequences for Code Generation
4301 @cindex expander definitions
4302 @cindex code generation RTL sequences
4303 @cindex defining RTL sequences for code generation
4305 On some target machines, some standard pattern names for RTL generation
4306 cannot be handled with single insn, but a sequence of RTL insns can
4307 represent them. For these target machines, you can write a
4308 @code{define_expand} to specify how to generate the sequence of RTL@.
4310 @findex define_expand
4311 A @code{define_expand} is an RTL expression that looks almost like a
4312 @code{define_insn}; but, unlike the latter, a @code{define_expand} is used
4313 only for RTL generation and it can produce more than one RTL insn.
4315 A @code{define_expand} RTX has four operands:
4319 The name. Each @code{define_expand} must have a name, since the only
4320 use for it is to refer to it by name.
4323 The RTL template. This is a vector of RTL expressions representing
4324 a sequence of separate instructions. Unlike @code{define_insn}, there
4325 is no implicit surrounding @code{PARALLEL}.
4328 The condition, a string containing a C expression. This expression is
4329 used to express how the availability of this pattern depends on
4330 subclasses of target machine, selected by command-line options when GCC
4331 is run. This is just like the condition of a @code{define_insn} that
4332 has a standard name. Therefore, the condition (if present) may not
4333 depend on the data in the insn being matched, but only the
4334 target-machine-type flags. The compiler needs to test these conditions
4335 during initialization in order to learn exactly which named instructions
4336 are available in a particular run.
4339 The preparation statements, a string containing zero or more C
4340 statements which are to be executed before RTL code is generated from
4343 Usually these statements prepare temporary registers for use as
4344 internal operands in the RTL template, but they can also generate RTL
4345 insns directly by calling routines such as @code{emit_insn}, etc.
4346 Any such insns precede the ones that come from the RTL template.
4349 Every RTL insn emitted by a @code{define_expand} must match some
4350 @code{define_insn} in the machine description. Otherwise, the compiler
4351 will crash when trying to generate code for the insn or trying to optimize
4354 The RTL template, in addition to controlling generation of RTL insns,
4355 also describes the operands that need to be specified when this pattern
4356 is used. In particular, it gives a predicate for each operand.
4358 A true operand, which needs to be specified in order to generate RTL from
4359 the pattern, should be described with a @code{match_operand} in its first
4360 occurrence in the RTL template. This enters information on the operand's
4361 predicate into the tables that record such things. GCC uses the
4362 information to preload the operand into a register if that is required for
4363 valid RTL code. If the operand is referred to more than once, subsequent
4364 references should use @code{match_dup}.
4366 The RTL template may also refer to internal ``operands'' which are
4367 temporary registers or labels used only within the sequence made by the
4368 @code{define_expand}. Internal operands are substituted into the RTL
4369 template with @code{match_dup}, never with @code{match_operand}. The
4370 values of the internal operands are not passed in as arguments by the
4371 compiler when it requests use of this pattern. Instead, they are computed
4372 within the pattern, in the preparation statements. These statements
4373 compute the values and store them into the appropriate elements of
4374 @code{operands} so that @code{match_dup} can find them.
4376 There are two special macros defined for use in the preparation statements:
4377 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
4384 Use the @code{DONE} macro to end RTL generation for the pattern. The
4385 only RTL insns resulting from the pattern on this occasion will be
4386 those already emitted by explicit calls to @code{emit_insn} within the
4387 preparation statements; the RTL template will not be generated.
4391 Make the pattern fail on this occasion. When a pattern fails, it means
4392 that the pattern was not truly available. The calling routines in the
4393 compiler will try other strategies for code generation using other patterns.
4395 Failure is currently supported only for binary (addition, multiplication,
4396 shifting, etc.) and bit-field (@code{extv}, @code{extzv}, and @code{insv})
4400 If the preparation falls through (invokes neither @code{DONE} nor
4401 @code{FAIL}), then the @code{define_expand} acts like a
4402 @code{define_insn} in that the RTL template is used to generate the
4405 The RTL template is not used for matching, only for generating the
4406 initial insn list. If the preparation statement always invokes
4407 @code{DONE} or @code{FAIL}, the RTL template may be reduced to a simple
4408 list of operands, such as this example:
4412 (define_expand "addsi3"
4413 [(match_operand:SI 0 "register_operand" "")
4414 (match_operand:SI 1 "register_operand" "")
4415 (match_operand:SI 2 "register_operand" "")]
4421 handle_add (operands[0], operands[1], operands[2]);
4427 Here is an example, the definition of left-shift for the SPUR chip:
4431 (define_expand "ashlsi3"
4432 [(set (match_operand:SI 0 "register_operand" "")
4436 (match_operand:SI 1 "register_operand" "")
4437 (match_operand:SI 2 "nonmemory_operand" "")))]
4446 if (GET_CODE (operands[2]) != CONST_INT
4447 || (unsigned) INTVAL (operands[2]) > 3)
4454 This example uses @code{define_expand} so that it can generate an RTL insn
4455 for shifting when the shift-count is in the supported range of 0 to 3 but
4456 fail in other cases where machine insns aren't available. When it fails,
4457 the compiler tries another strategy using different patterns (such as, a
4460 If the compiler were able to handle nontrivial condition-strings in
4461 patterns with names, then it would be possible to use a
4462 @code{define_insn} in that case. Here is another case (zero-extension
4463 on the 68000) which makes more use of the power of @code{define_expand}:
4466 (define_expand "zero_extendhisi2"
4467 [(set (match_operand:SI 0 "general_operand" "")
4469 (set (strict_low_part
4473 (match_operand:HI 1 "general_operand" ""))]
4475 "operands[1] = make_safe_from (operands[1], operands[0]);")
4479 @findex make_safe_from
4480 Here two RTL insns are generated, one to clear the entire output operand
4481 and the other to copy the input operand into its low half. This sequence
4482 is incorrect if the input operand refers to [the old value of] the output
4483 operand, so the preparation statement makes sure this isn't so. The
4484 function @code{make_safe_from} copies the @code{operands[1]} into a
4485 temporary register if it refers to @code{operands[0]}. It does this
4486 by emitting another RTL insn.
4488 Finally, a third example shows the use of an internal operand.
4489 Zero-extension on the SPUR chip is done by @code{and}-ing the result
4490 against a halfword mask. But this mask cannot be represented by a
4491 @code{const_int} because the constant value is too large to be legitimate
4492 on this machine. So it must be copied into a register with
4493 @code{force_reg} and then the register used in the @code{and}.
4496 (define_expand "zero_extendhisi2"
4497 [(set (match_operand:SI 0 "register_operand" "")
4499 (match_operand:HI 1 "register_operand" "")
4504 = force_reg (SImode, GEN_INT (65535)); ")
4507 @strong{Note:} If the @code{define_expand} is used to serve a
4508 standard binary or unary arithmetic operation or a bit-field operation,
4509 then the last insn it generates must not be a @code{code_label},
4510 @code{barrier} or @code{note}. It must be an @code{insn},
4511 @code{jump_insn} or @code{call_insn}. If you don't need a real insn
4512 at the end, emit an insn to copy the result of the operation into
4513 itself. Such an insn will generate no code, but it can avoid problems
4518 @node Insn Splitting
4519 @section Defining How to Split Instructions
4520 @cindex insn splitting
4521 @cindex instruction splitting
4522 @cindex splitting instructions
4524 There are two cases where you should specify how to split a pattern
4525 into multiple insns. On machines that have instructions requiring
4526 delay slots (@pxref{Delay Slots}) or that have instructions whose
4527 output is not available for multiple cycles (@pxref{Processor pipeline
4528 description}), the compiler phases that optimize these cases need to
4529 be able to move insns into one-instruction delay slots. However, some
4530 insns may generate more than one machine instruction. These insns
4531 cannot be placed into a delay slot.
4533 Often you can rewrite the single insn as a list of individual insns,
4534 each corresponding to one machine instruction. The disadvantage of
4535 doing so is that it will cause the compilation to be slower and require
4536 more space. If the resulting insns are too complex, it may also
4537 suppress some optimizations. The compiler splits the insn if there is a
4538 reason to believe that it might improve instruction or delay slot
4541 The insn combiner phase also splits putative insns. If three insns are
4542 merged into one insn with a complex expression that cannot be matched by
4543 some @code{define_insn} pattern, the combiner phase attempts to split
4544 the complex pattern into two insns that are recognized. Usually it can
4545 break the complex pattern into two patterns by splitting out some
4546 subexpression. However, in some other cases, such as performing an
4547 addition of a large constant in two insns on a RISC machine, the way to
4548 split the addition into two insns is machine-dependent.
4550 @findex define_split
4551 The @code{define_split} definition tells the compiler how to split a
4552 complex insn into several simpler insns. It looks like this:
4556 [@var{insn-pattern}]
4558 [@var{new-insn-pattern-1}
4559 @var{new-insn-pattern-2}
4561 "@var{preparation-statements}")
4564 @var{insn-pattern} is a pattern that needs to be split and
4565 @var{condition} is the final condition to be tested, as in a
4566 @code{define_insn}. When an insn matching @var{insn-pattern} and
4567 satisfying @var{condition} is found, it is replaced in the insn list
4568 with the insns given by @var{new-insn-pattern-1},
4569 @var{new-insn-pattern-2}, etc.
4571 The @var{preparation-statements} are similar to those statements that
4572 are specified for @code{define_expand} (@pxref{Expander Definitions})
4573 and are executed before the new RTL is generated to prepare for the
4574 generated code or emit some insns whose pattern is not fixed. Unlike
4575 those in @code{define_expand}, however, these statements must not
4576 generate any new pseudo-registers. Once reload has completed, they also
4577 must not allocate any space in the stack frame.
4579 Patterns are matched against @var{insn-pattern} in two different
4580 circumstances. If an insn needs to be split for delay slot scheduling
4581 or insn scheduling, the insn is already known to be valid, which means
4582 that it must have been matched by some @code{define_insn} and, if
4583 @code{reload_completed} is nonzero, is known to satisfy the constraints
4584 of that @code{define_insn}. In that case, the new insn patterns must
4585 also be insns that are matched by some @code{define_insn} and, if
4586 @code{reload_completed} is nonzero, must also satisfy the constraints
4587 of those definitions.
4589 As an example of this usage of @code{define_split}, consider the following
4590 example from @file{a29k.md}, which splits a @code{sign_extend} from
4591 @code{HImode} to @code{SImode} into a pair of shift insns:
4595 [(set (match_operand:SI 0 "gen_reg_operand" "")
4596 (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
4599 (ashift:SI (match_dup 1)
4602 (ashiftrt:SI (match_dup 0)
4605 @{ operands[1] = gen_lowpart (SImode, operands[1]); @}")
4608 When the combiner phase tries to split an insn pattern, it is always the
4609 case that the pattern is @emph{not} matched by any @code{define_insn}.
4610 The combiner pass first tries to split a single @code{set} expression
4611 and then the same @code{set} expression inside a @code{parallel}, but
4612 followed by a @code{clobber} of a pseudo-reg to use as a scratch
4613 register. In these cases, the combiner expects exactly two new insn
4614 patterns to be generated. It will verify that these patterns match some
4615 @code{define_insn} definitions, so you need not do this test in the
4616 @code{define_split} (of course, there is no point in writing a
4617 @code{define_split} that will never produce insns that match).
4619 Here is an example of this use of @code{define_split}, taken from
4624 [(set (match_operand:SI 0 "gen_reg_operand" "")
4625 (plus:SI (match_operand:SI 1 "gen_reg_operand" "")
4626 (match_operand:SI 2 "non_add_cint_operand" "")))]
4628 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
4629 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
4632 int low = INTVAL (operands[2]) & 0xffff;
4633 int high = (unsigned) INTVAL (operands[2]) >> 16;
4636 high++, low |= 0xffff0000;
4638 operands[3] = GEN_INT (high << 16);
4639 operands[4] = GEN_INT (low);
4643 Here the predicate @code{non_add_cint_operand} matches any
4644 @code{const_int} that is @emph{not} a valid operand of a single add
4645 insn. The add with the smaller displacement is written so that it
4646 can be substituted into the address of a subsequent operation.
4648 An example that uses a scratch register, from the same file, generates
4649 an equality comparison of a register and a large constant:
4653 [(set (match_operand:CC 0 "cc_reg_operand" "")
4654 (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
4655 (match_operand:SI 2 "non_short_cint_operand" "")))
4656 (clobber (match_operand:SI 3 "gen_reg_operand" ""))]
4657 "find_single_use (operands[0], insn, 0)
4658 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
4659 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
4660 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
4661 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
4664 /* Get the constant we are comparing against, C, and see what it
4665 looks like sign-extended to 16 bits. Then see what constant
4666 could be XOR'ed with C to get the sign-extended value. */
4668 int c = INTVAL (operands[2]);
4669 int sextc = (c << 16) >> 16;
4670 int xorv = c ^ sextc;
4672 operands[4] = GEN_INT (xorv);
4673 operands[5] = GEN_INT (sextc);
4677 To avoid confusion, don't write a single @code{define_split} that
4678 accepts some insns that match some @code{define_insn} as well as some
4679 insns that don't. Instead, write two separate @code{define_split}
4680 definitions, one for the insns that are valid and one for the insns that
4683 The splitter is allowed to split jump instructions into sequence of
4684 jumps or create new jumps in while splitting non-jump instructions. As
4685 the central flowgraph and branch prediction information needs to be updated,
4686 several restriction apply.
4688 Splitting of jump instruction into sequence that over by another jump
4689 instruction is always valid, as compiler expect identical behavior of new
4690 jump. When new sequence contains multiple jump instructions or new labels,
4691 more assistance is needed. Splitter is required to create only unconditional
4692 jumps, or simple conditional jump instructions. Additionally it must attach a
4693 @code{REG_BR_PROB} note to each conditional jump. A global variable
4694 @code{split_branch_probability} hold the probability of original branch in case
4695 it was an simple conditional jump, @minus{}1 otherwise. To simplify
4696 recomputing of edge frequencies, new sequence is required to have only
4697 forward jumps to the newly created labels.
4699 @findex define_insn_and_split
4700 For the common case where the pattern of a define_split exactly matches the
4701 pattern of a define_insn, use @code{define_insn_and_split}. It looks like
4705 (define_insn_and_split
4706 [@var{insn-pattern}]
4708 "@var{output-template}"
4709 "@var{split-condition}"
4710 [@var{new-insn-pattern-1}
4711 @var{new-insn-pattern-2}
4713 "@var{preparation-statements}"
4714 [@var{insn-attributes}])
4718 @var{insn-pattern}, @var{condition}, @var{output-template}, and
4719 @var{insn-attributes} are used as in @code{define_insn}. The
4720 @var{new-insn-pattern} vector and the @var{preparation-statements} are used as
4721 in a @code{define_split}. The @var{split-condition} is also used as in
4722 @code{define_split}, with the additional behavior that if the condition starts
4723 with @samp{&&}, the condition used for the split will be the constructed as a
4724 logical ``and'' of the split condition with the insn condition. For example,
4728 (define_insn_and_split "zero_extendhisi2_and"
4729 [(set (match_operand:SI 0 "register_operand" "=r")
4730 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
4731 (clobber (reg:CC 17))]
4732 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
4734 "&& reload_completed"
4735 [(parallel [(set (match_dup 0)
4736 (and:SI (match_dup 0) (const_int 65535)))
4737 (clobber (reg:CC 17))])]
4739 [(set_attr "type" "alu1")])
4743 In this case, the actual split condition will be
4744 @samp{TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed}.
4746 The @code{define_insn_and_split} construction provides exactly the same
4747 functionality as two separate @code{define_insn} and @code{define_split}
4748 patterns. It exists for compactness, and as a maintenance tool to prevent
4749 having to ensure the two patterns' templates match.
4753 @node Including Patterns
4754 @section Including Patterns in Machine Descriptions.
4755 @cindex insn includes
4758 The @code{include} pattern tells the compiler tools where to
4759 look for patterns that are in files other than in the file
4760 @file{.md}. This is used only at build time and there is no preprocessing allowed.
4774 (include "filestuff")
4778 Where @var{pathname} is a string that specifies the location of the file,
4779 specifies the include file to be in @file{gcc/config/target/filestuff}. The
4780 directory @file{gcc/config/target} is regarded as the default directory.
4783 Machine descriptions may be split up into smaller more manageable subsections
4784 and placed into subdirectories.
4790 (include "BOGUS/filestuff")
4794 the include file is specified to be in @file{gcc/config/@var{target}/BOGUS/filestuff}.
4796 Specifying an absolute path for the include file such as;
4799 (include "/u2/BOGUS/filestuff")
4802 is permitted but is not encouraged.
4804 @subsection RTL Generation Tool Options for Directory Search
4805 @cindex directory options .md
4806 @cindex options, directory search
4807 @cindex search options
4809 The @option{-I@var{dir}} option specifies directories to search for machine descriptions.
4814 genrecog -I/p1/abc/proc1 -I/p2/abcd/pro2 target.md
4819 Add the directory @var{dir} to the head of the list of directories to be
4820 searched for header files. This can be used to override a system machine definition
4821 file, substituting your own version, since these directories are
4822 searched before the default machine description file directories. If you use more than
4823 one @option{-I} option, the directories are scanned in left-to-right
4824 order; the standard default directory come after.
4829 @node Peephole Definitions
4830 @section Machine-Specific Peephole Optimizers
4831 @cindex peephole optimizer definitions
4832 @cindex defining peephole optimizers
4834 In addition to instruction patterns the @file{md} file may contain
4835 definitions of machine-specific peephole optimizations.
4837 The combiner does not notice certain peephole optimizations when the data
4838 flow in the program does not suggest that it should try them. For example,
4839 sometimes two consecutive insns related in purpose can be combined even
4840 though the second one does not appear to use a register computed in the
4841 first one. A machine-specific peephole optimizer can detect such
4844 There are two forms of peephole definitions that may be used. The
4845 original @code{define_peephole} is run at assembly output time to
4846 match insns and substitute assembly text. Use of @code{define_peephole}
4849 A newer @code{define_peephole2} matches insns and substitutes new
4850 insns. The @code{peephole2} pass is run after register allocation
4851 but before scheduling, which may result in much better code for
4852 targets that do scheduling.
4855 * define_peephole:: RTL to Text Peephole Optimizers
4856 * define_peephole2:: RTL to RTL Peephole Optimizers
4861 @node define_peephole
4862 @subsection RTL to Text Peephole Optimizers
4863 @findex define_peephole
4866 A definition looks like this:
4870 [@var{insn-pattern-1}
4871 @var{insn-pattern-2}
4875 "@var{optional-insn-attributes}")
4879 The last string operand may be omitted if you are not using any
4880 machine-specific information in this machine description. If present,
4881 it must obey the same rules as in a @code{define_insn}.
4883 In this skeleton, @var{insn-pattern-1} and so on are patterns to match
4884 consecutive insns. The optimization applies to a sequence of insns when
4885 @var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches
4886 the next, and so on.
4888 Each of the insns matched by a peephole must also match a
4889 @code{define_insn}. Peepholes are checked only at the last stage just
4890 before code generation, and only optionally. Therefore, any insn which
4891 would match a peephole but no @code{define_insn} will cause a crash in code
4892 generation in an unoptimized compilation, or at various optimization
4895 The operands of the insns are matched with @code{match_operands},
4896 @code{match_operator}, and @code{match_dup}, as usual. What is not
4897 usual is that the operand numbers apply to all the insn patterns in the
4898 definition. So, you can check for identical operands in two insns by
4899 using @code{match_operand} in one insn and @code{match_dup} in the
4902 The operand constraints used in @code{match_operand} patterns do not have
4903 any direct effect on the applicability of the peephole, but they will
4904 be validated afterward, so make sure your constraints are general enough
4905 to apply whenever the peephole matches. If the peephole matches
4906 but the constraints are not satisfied, the compiler will crash.
4908 It is safe to omit constraints in all the operands of the peephole; or
4909 you can write constraints which serve as a double-check on the criteria
4912 Once a sequence of insns matches the patterns, the @var{condition} is
4913 checked. This is a C expression which makes the final decision whether to
4914 perform the optimization (we do so if the expression is nonzero). If
4915 @var{condition} is omitted (in other words, the string is empty) then the
4916 optimization is applied to every sequence of insns that matches the
4919 The defined peephole optimizations are applied after register allocation
4920 is complete. Therefore, the peephole definition can check which
4921 operands have ended up in which kinds of registers, just by looking at
4924 @findex prev_active_insn
4925 The way to refer to the operands in @var{condition} is to write
4926 @code{operands[@var{i}]} for operand number @var{i} (as matched by
4927 @code{(match_operand @var{i} @dots{})}). Use the variable @code{insn}
4928 to refer to the last of the insns being matched; use
4929 @code{prev_active_insn} to find the preceding insns.
4931 @findex dead_or_set_p
4932 When optimizing computations with intermediate results, you can use
4933 @var{condition} to match only when the intermediate results are not used
4934 elsewhere. Use the C expression @code{dead_or_set_p (@var{insn},
4935 @var{op})}, where @var{insn} is the insn in which you expect the value
4936 to be used for the last time (from the value of @code{insn}, together
4937 with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate
4938 value (from @code{operands[@var{i}]}).
4940 Applying the optimization means replacing the sequence of insns with one
4941 new insn. The @var{template} controls ultimate output of assembler code
4942 for this combined insn. It works exactly like the template of a
4943 @code{define_insn}. Operand numbers in this template are the same ones
4944 used in matching the original sequence of insns.
4946 The result of a defined peephole optimizer does not need to match any of
4947 the insn patterns in the machine description; it does not even have an
4948 opportunity to match them. The peephole optimizer definition itself serves
4949 as the insn pattern to control how the insn is output.
4951 Defined peephole optimizers are run as assembler code is being output,
4952 so the insns they produce are never combined or rearranged in any way.
4954 Here is an example, taken from the 68000 machine description:
4958 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
4959 (set (match_operand:DF 0 "register_operand" "=f")
4960 (match_operand:DF 1 "register_operand" "ad"))]
4961 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
4964 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4966 output_asm_insn ("move.l %1,(sp)", xoperands);
4967 output_asm_insn ("move.l %1,-(sp)", operands);
4968 return "fmove.d (sp)+,%0";
4970 output_asm_insn ("movel %1,sp@@", xoperands);
4971 output_asm_insn ("movel %1,sp@@-", operands);
4972 return "fmoved sp@@+,%0";
4978 The effect of this optimization is to change
5004 If a peephole matches a sequence including one or more jump insns, you must
5005 take account of the flags such as @code{CC_REVERSED} which specify that the
5006 condition codes are represented in an unusual manner. The compiler
5007 automatically alters any ordinary conditional jumps which occur in such
5008 situations, but the compiler cannot alter jumps which have been replaced by
5009 peephole optimizations. So it is up to you to alter the assembler code
5010 that the peephole produces. Supply C code to write the assembler output,
5011 and in this C code check the condition code status flags and change the
5012 assembler code as appropriate.
5015 @var{insn-pattern-1} and so on look @emph{almost} like the second
5016 operand of @code{define_insn}. There is one important difference: the
5017 second operand of @code{define_insn} consists of one or more RTX's
5018 enclosed in square brackets. Usually, there is only one: then the same
5019 action can be written as an element of a @code{define_peephole}. But
5020 when there are multiple actions in a @code{define_insn}, they are
5021 implicitly enclosed in a @code{parallel}. Then you must explicitly
5022 write the @code{parallel}, and the square brackets within it, in the
5023 @code{define_peephole}. Thus, if an insn pattern looks like this,
5026 (define_insn "divmodsi4"
5027 [(set (match_operand:SI 0 "general_operand" "=d")
5028 (div:SI (match_operand:SI 1 "general_operand" "0")
5029 (match_operand:SI 2 "general_operand" "dmsK")))
5030 (set (match_operand:SI 3 "general_operand" "=d")
5031 (mod:SI (match_dup 1) (match_dup 2)))]
5033 "divsl%.l %2,%3:%0")
5037 then the way to mention this insn in a peephole is as follows:
5043 [(set (match_operand:SI 0 "general_operand" "=d")
5044 (div:SI (match_operand:SI 1 "general_operand" "0")
5045 (match_operand:SI 2 "general_operand" "dmsK")))
5046 (set (match_operand:SI 3 "general_operand" "=d")
5047 (mod:SI (match_dup 1) (match_dup 2)))])
5054 @node define_peephole2
5055 @subsection RTL to RTL Peephole Optimizers
5056 @findex define_peephole2
5058 The @code{define_peephole2} definition tells the compiler how to
5059 substitute one sequence of instructions for another sequence,
5060 what additional scratch registers may be needed and what their
5065 [@var{insn-pattern-1}
5066 @var{insn-pattern-2}
5069 [@var{new-insn-pattern-1}
5070 @var{new-insn-pattern-2}
5072 "@var{preparation-statements}")
5075 The definition is almost identical to @code{define_split}
5076 (@pxref{Insn Splitting}) except that the pattern to match is not a
5077 single instruction, but a sequence of instructions.
5079 It is possible to request additional scratch registers for use in the
5080 output template. If appropriate registers are not free, the pattern
5081 will simply not match.
5083 @findex match_scratch
5085 Scratch registers are requested with a @code{match_scratch} pattern at
5086 the top level of the input pattern. The allocated register (initially) will
5087 be dead at the point requested within the original sequence. If the scratch
5088 is used at more than a single point, a @code{match_dup} pattern at the
5089 top level of the input pattern marks the last position in the input sequence
5090 at which the register must be available.
5092 Here is an example from the IA-32 machine description:
5096 [(match_scratch:SI 2 "r")
5097 (parallel [(set (match_operand:SI 0 "register_operand" "")
5098 (match_operator:SI 3 "arith_or_logical_operator"
5100 (match_operand:SI 1 "memory_operand" "")]))
5101 (clobber (reg:CC 17))])]
5102 "! optimize_size && ! TARGET_READ_MODIFY"
5103 [(set (match_dup 2) (match_dup 1))
5104 (parallel [(set (match_dup 0)
5105 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
5106 (clobber (reg:CC 17))])]
5111 This pattern tries to split a load from its use in the hopes that we'll be
5112 able to schedule around the memory load latency. It allocates a single
5113 @code{SImode} register of class @code{GENERAL_REGS} (@code{"r"}) that needs
5114 to be live only at the point just before the arithmetic.
5116 A real example requiring extended scratch lifetimes is harder to come by,
5117 so here's a silly made-up example:
5121 [(match_scratch:SI 4 "r")
5122 (set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
5123 (set (match_operand:SI 2 "" "") (match_dup 1))
5125 (set (match_operand:SI 3 "" "") (match_dup 1))]
5126 "/* @r{determine 1 does not overlap 0 and 2} */"
5127 [(set (match_dup 4) (match_dup 1))
5128 (set (match_dup 0) (match_dup 4))
5129 (set (match_dup 2) (match_dup 4))]
5130 (set (match_dup 3) (match_dup 4))]
5135 If we had not added the @code{(match_dup 4)} in the middle of the input
5136 sequence, it might have been the case that the register we chose at the
5137 beginning of the sequence is killed by the first or second @code{set}.
5141 @node Insn Attributes
5142 @section Instruction Attributes
5143 @cindex insn attributes
5144 @cindex instruction attributes
5146 In addition to describing the instruction supported by the target machine,
5147 the @file{md} file also defines a group of @dfn{attributes} and a set of
5148 values for each. Every generated insn is assigned a value for each attribute.
5149 One possible attribute would be the effect that the insn has on the machine's
5150 condition code. This attribute can then be used by @code{NOTICE_UPDATE_CC}
5151 to track the condition codes.
5154 * Defining Attributes:: Specifying attributes and their values.
5155 * Expressions:: Valid expressions for attribute values.
5156 * Tagging Insns:: Assigning attribute values to insns.
5157 * Attr Example:: An example of assigning attributes.
5158 * Insn Lengths:: Computing the length of insns.
5159 * Constant Attributes:: Defining attributes that are constant.
5160 * Delay Slots:: Defining delay slots required for a machine.
5161 * Processor pipeline description:: Specifying information for insn scheduling.
5166 @node Defining Attributes
5167 @subsection Defining Attributes and their Values
5168 @cindex defining attributes and their values
5169 @cindex attributes, defining
5172 The @code{define_attr} expression is used to define each attribute required
5173 by the target machine. It looks like:
5176 (define_attr @var{name} @var{list-of-values} @var{default})
5179 @var{name} is a string specifying the name of the attribute being defined.
5181 @var{list-of-values} is either a string that specifies a comma-separated
5182 list of values that can be assigned to the attribute, or a null string to
5183 indicate that the attribute takes numeric values.
5185 @var{default} is an attribute expression that gives the value of this
5186 attribute for insns that match patterns whose definition does not include
5187 an explicit value for this attribute. @xref{Attr Example}, for more
5188 information on the handling of defaults. @xref{Constant Attributes},
5189 for information on attributes that do not depend on any particular insn.
5192 For each defined attribute, a number of definitions are written to the
5193 @file{insn-attr.h} file. For cases where an explicit set of values is
5194 specified for an attribute, the following are defined:
5198 A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}.
5201 An enumerated class is defined for @samp{attr_@var{name}} with
5202 elements of the form @samp{@var{upper-name}_@var{upper-value}} where
5203 the attribute name and value are first converted to uppercase.
5206 A function @samp{get_attr_@var{name}} is defined that is passed an insn and
5207 returns the attribute value for that insn.
5210 For example, if the following is present in the @file{md} file:
5213 (define_attr "type" "branch,fp,load,store,arith" @dots{})
5217 the following lines will be written to the file @file{insn-attr.h}.
5220 #define HAVE_ATTR_type
5221 enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD,
5222 TYPE_STORE, TYPE_ARITH@};
5223 extern enum attr_type get_attr_type ();
5226 If the attribute takes numeric values, no @code{enum} type will be
5227 defined and the function to obtain the attribute's value will return
5233 @subsection Attribute Expressions
5234 @cindex attribute expressions
5236 RTL expressions used to define attributes use the codes described above
5237 plus a few specific to attribute definitions, to be discussed below.
5238 Attribute value expressions must have one of the following forms:
5241 @cindex @code{const_int} and attributes
5242 @item (const_int @var{i})
5243 The integer @var{i} specifies the value of a numeric attribute. @var{i}
5244 must be non-negative.
5246 The value of a numeric attribute can be specified either with a
5247 @code{const_int}, or as an integer represented as a string in
5248 @code{const_string}, @code{eq_attr} (see below), @code{attr},
5249 @code{symbol_ref}, simple arithmetic expressions, and @code{set_attr}
5250 overrides on specific instructions (@pxref{Tagging Insns}).
5252 @cindex @code{const_string} and attributes
5253 @item (const_string @var{value})
5254 The string @var{value} specifies a constant attribute value.
5255 If @var{value} is specified as @samp{"*"}, it means that the default value of
5256 the attribute is to be used for the insn containing this expression.
5257 @samp{"*"} obviously cannot be used in the @var{default} expression
5258 of a @code{define_attr}.
5260 If the attribute whose value is being specified is numeric, @var{value}
5261 must be a string containing a non-negative integer (normally
5262 @code{const_int} would be used in this case). Otherwise, it must
5263 contain one of the valid values for the attribute.
5265 @cindex @code{if_then_else} and attributes
5266 @item (if_then_else @var{test} @var{true-value} @var{false-value})
5267 @var{test} specifies an attribute test, whose format is defined below.
5268 The value of this expression is @var{true-value} if @var{test} is true,
5269 otherwise it is @var{false-value}.
5271 @cindex @code{cond} and attributes
5272 @item (cond [@var{test1} @var{value1} @dots{}] @var{default})
5273 The first operand of this expression is a vector containing an even
5274 number of expressions and consisting of pairs of @var{test} and @var{value}
5275 expressions. The value of the @code{cond} expression is that of the
5276 @var{value} corresponding to the first true @var{test} expression. If
5277 none of the @var{test} expressions are true, the value of the @code{cond}
5278 expression is that of the @var{default} expression.
5281 @var{test} expressions can have one of the following forms:
5284 @cindex @code{const_int} and attribute tests
5285 @item (const_int @var{i})
5286 This test is true if @var{i} is nonzero and false otherwise.
5288 @cindex @code{not} and attributes
5289 @cindex @code{ior} and attributes
5290 @cindex @code{and} and attributes
5291 @item (not @var{test})
5292 @itemx (ior @var{test1} @var{test2})
5293 @itemx (and @var{test1} @var{test2})
5294 These tests are true if the indicated logical function is true.
5296 @cindex @code{match_operand} and attributes
5297 @item (match_operand:@var{m} @var{n} @var{pred} @var{constraints})
5298 This test is true if operand @var{n} of the insn whose attribute value
5299 is being determined has mode @var{m} (this part of the test is ignored
5300 if @var{m} is @code{VOIDmode}) and the function specified by the string
5301 @var{pred} returns a nonzero value when passed operand @var{n} and mode
5302 @var{m} (this part of the test is ignored if @var{pred} is the null
5305 The @var{constraints} operand is ignored and should be the null string.
5307 @cindex @code{le} and attributes
5308 @cindex @code{leu} and attributes
5309 @cindex @code{lt} and attributes
5310 @cindex @code{gt} and attributes
5311 @cindex @code{gtu} and attributes
5312 @cindex @code{ge} and attributes
5313 @cindex @code{geu} and attributes
5314 @cindex @code{ne} and attributes
5315 @cindex @code{eq} and attributes
5316 @cindex @code{plus} and attributes
5317 @cindex @code{minus} and attributes
5318 @cindex @code{mult} and attributes
5319 @cindex @code{div} and attributes
5320 @cindex @code{mod} and attributes
5321 @cindex @code{abs} and attributes
5322 @cindex @code{neg} and attributes
5323 @cindex @code{ashift} and attributes
5324 @cindex @code{lshiftrt} and attributes
5325 @cindex @code{ashiftrt} and attributes
5326 @item (le @var{arith1} @var{arith2})
5327 @itemx (leu @var{arith1} @var{arith2})
5328 @itemx (lt @var{arith1} @var{arith2})
5329 @itemx (ltu @var{arith1} @var{arith2})
5330 @itemx (gt @var{arith1} @var{arith2})
5331 @itemx (gtu @var{arith1} @var{arith2})
5332 @itemx (ge @var{arith1} @var{arith2})
5333 @itemx (geu @var{arith1} @var{arith2})
5334 @itemx (ne @var{arith1} @var{arith2})
5335 @itemx (eq @var{arith1} @var{arith2})
5336 These tests are true if the indicated comparison of the two arithmetic
5337 expressions is true. Arithmetic expressions are formed with
5338 @code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod},
5339 @code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not},
5340 @code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions.
5343 @code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn
5344 Lengths},for additional forms). @code{symbol_ref} is a string
5345 denoting a C expression that yields an @code{int} when evaluated by the
5346 @samp{get_attr_@dots{}} routine. It should normally be a global
5350 @item (eq_attr @var{name} @var{value})
5351 @var{name} is a string specifying the name of an attribute.
5353 @var{value} is a string that is either a valid value for attribute
5354 @var{name}, a comma-separated list of values, or @samp{!} followed by a
5355 value or list. If @var{value} does not begin with a @samp{!}, this
5356 test is true if the value of the @var{name} attribute of the current
5357 insn is in the list specified by @var{value}. If @var{value} begins
5358 with a @samp{!}, this test is true if the attribute's value is
5359 @emph{not} in the specified list.
5364 (eq_attr "type" "load,store")
5371 (ior (eq_attr "type" "load") (eq_attr "type" "store"))
5374 If @var{name} specifies an attribute of @samp{alternative}, it refers to the
5375 value of the compiler variable @code{which_alternative}
5376 (@pxref{Output Statement}) and the values must be small integers. For
5380 (eq_attr "alternative" "2,3")
5387 (ior (eq (symbol_ref "which_alternative") (const_int 2))
5388 (eq (symbol_ref "which_alternative") (const_int 3)))
5391 Note that, for most attributes, an @code{eq_attr} test is simplified in cases
5392 where the value of the attribute being tested is known for all insns matching
5393 a particular pattern. This is by far the most common case.
5396 @item (attr_flag @var{name})
5397 The value of an @code{attr_flag} expression is true if the flag
5398 specified by @var{name} is true for the @code{insn} currently being
5401 @var{name} is a string specifying one of a fixed set of flags to test.
5402 Test the flags @code{forward} and @code{backward} to determine the
5403 direction of a conditional branch. Test the flags @code{very_likely},
5404 @code{likely}, @code{very_unlikely}, and @code{unlikely} to determine
5405 if a conditional branch is expected to be taken.
5407 If the @code{very_likely} flag is true, then the @code{likely} flag is also
5408 true. Likewise for the @code{very_unlikely} and @code{unlikely} flags.
5410 This example describes a conditional branch delay slot which
5411 can be nullified for forward branches that are taken (annul-true) or
5412 for backward branches which are not taken (annul-false).
5415 (define_delay (eq_attr "type" "cbranch")
5416 [(eq_attr "in_branch_delay" "true")
5417 (and (eq_attr "in_branch_delay" "true")
5418 (attr_flag "forward"))
5419 (and (eq_attr "in_branch_delay" "true")
5420 (attr_flag "backward"))])
5423 The @code{forward} and @code{backward} flags are false if the current
5424 @code{insn} being scheduled is not a conditional branch.
5426 The @code{very_likely} and @code{likely} flags are true if the
5427 @code{insn} being scheduled is not a conditional branch.
5428 The @code{very_unlikely} and @code{unlikely} flags are false if the
5429 @code{insn} being scheduled is not a conditional branch.
5431 @code{attr_flag} is only used during delay slot scheduling and has no
5432 meaning to other passes of the compiler.
5435 @item (attr @var{name})
5436 The value of another attribute is returned. This is most useful
5437 for numeric attributes, as @code{eq_attr} and @code{attr_flag}
5438 produce more efficient code for non-numeric attributes.
5444 @subsection Assigning Attribute Values to Insns
5445 @cindex tagging insns
5446 @cindex assigning attribute values to insns
5448 The value assigned to an attribute of an insn is primarily determined by
5449 which pattern is matched by that insn (or which @code{define_peephole}
5450 generated it). Every @code{define_insn} and @code{define_peephole} can
5451 have an optional last argument to specify the values of attributes for
5452 matching insns. The value of any attribute not specified in a particular
5453 insn is set to the default value for that attribute, as specified in its
5454 @code{define_attr}. Extensive use of default values for attributes
5455 permits the specification of the values for only one or two attributes
5456 in the definition of most insn patterns, as seen in the example in the
5459 The optional last argument of @code{define_insn} and
5460 @code{define_peephole} is a vector of expressions, each of which defines
5461 the value for a single attribute. The most general way of assigning an
5462 attribute's value is to use a @code{set} expression whose first operand is an
5463 @code{attr} expression giving the name of the attribute being set. The
5464 second operand of the @code{set} is an attribute expression
5465 (@pxref{Expressions}) giving the value of the attribute.
5467 When the attribute value depends on the @samp{alternative} attribute
5468 (i.e., which is the applicable alternative in the constraint of the
5469 insn), the @code{set_attr_alternative} expression can be used. It
5470 allows the specification of a vector of attribute expressions, one for
5474 When the generality of arbitrary attribute expressions is not required,
5475 the simpler @code{set_attr} expression can be used, which allows
5476 specifying a string giving either a single attribute value or a list
5477 of attribute values, one for each alternative.
5479 The form of each of the above specifications is shown below. In each case,
5480 @var{name} is a string specifying the attribute to be set.
5483 @item (set_attr @var{name} @var{value-string})
5484 @var{value-string} is either a string giving the desired attribute value,
5485 or a string containing a comma-separated list giving the values for
5486 succeeding alternatives. The number of elements must match the number
5487 of alternatives in the constraint of the insn pattern.
5489 Note that it may be useful to specify @samp{*} for some alternative, in
5490 which case the attribute will assume its default value for insns matching
5493 @findex set_attr_alternative
5494 @item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}])
5495 Depending on the alternative of the insn, the value will be one of the
5496 specified values. This is a shorthand for using a @code{cond} with
5497 tests on the @samp{alternative} attribute.
5500 @item (set (attr @var{name}) @var{value})
5501 The first operand of this @code{set} must be the special RTL expression
5502 @code{attr}, whose sole operand is a string giving the name of the
5503 attribute being set. @var{value} is the value of the attribute.
5506 The following shows three different ways of representing the same
5507 attribute value specification:
5510 (set_attr "type" "load,store,arith")
5512 (set_attr_alternative "type"
5513 [(const_string "load") (const_string "store")
5514 (const_string "arith")])
5517 (cond [(eq_attr "alternative" "1") (const_string "load")
5518 (eq_attr "alternative" "2") (const_string "store")]
5519 (const_string "arith")))
5523 @findex define_asm_attributes
5524 The @code{define_asm_attributes} expression provides a mechanism to
5525 specify the attributes assigned to insns produced from an @code{asm}
5526 statement. It has the form:
5529 (define_asm_attributes [@var{attr-sets}])
5533 where @var{attr-sets} is specified the same as for both the
5534 @code{define_insn} and the @code{define_peephole} expressions.
5536 These values will typically be the ``worst case'' attribute values. For
5537 example, they might indicate that the condition code will be clobbered.
5539 A specification for a @code{length} attribute is handled specially. The
5540 way to compute the length of an @code{asm} insn is to multiply the
5541 length specified in the expression @code{define_asm_attributes} by the
5542 number of machine instructions specified in the @code{asm} statement,
5543 determined by counting the number of semicolons and newlines in the
5544 string. Therefore, the value of the @code{length} attribute specified
5545 in a @code{define_asm_attributes} should be the maximum possible length
5546 of a single machine instruction.
5551 @subsection Example of Attribute Specifications
5552 @cindex attribute specifications example
5553 @cindex attribute specifications
5555 The judicious use of defaulting is important in the efficient use of
5556 insn attributes. Typically, insns are divided into @dfn{types} and an
5557 attribute, customarily called @code{type}, is used to represent this
5558 value. This attribute is normally used only to define the default value
5559 for other attributes. An example will clarify this usage.
5561 Assume we have a RISC machine with a condition code and in which only
5562 full-word operations are performed in registers. Let us assume that we
5563 can divide all insns into loads, stores, (integer) arithmetic
5564 operations, floating point operations, and branches.
5566 Here we will concern ourselves with determining the effect of an insn on
5567 the condition code and will limit ourselves to the following possible
5568 effects: The condition code can be set unpredictably (clobbered), not
5569 be changed, be set to agree with the results of the operation, or only
5570 changed if the item previously set into the condition code has been
5573 Here is part of a sample @file{md} file for such a machine:
5576 (define_attr "type" "load,store,arith,fp,branch" (const_string "arith"))
5578 (define_attr "cc" "clobber,unchanged,set,change0"
5579 (cond [(eq_attr "type" "load")
5580 (const_string "change0")
5581 (eq_attr "type" "store,branch")
5582 (const_string "unchanged")
5583 (eq_attr "type" "arith")
5584 (if_then_else (match_operand:SI 0 "" "")
5585 (const_string "set")
5586 (const_string "clobber"))]
5587 (const_string "clobber")))
5590 [(set (match_operand:SI 0 "general_operand" "=r,r,m")
5591 (match_operand:SI 1 "general_operand" "r,m,r"))]
5597 [(set_attr "type" "arith,load,store")])
5600 Note that we assume in the above example that arithmetic operations
5601 performed on quantities smaller than a machine word clobber the condition
5602 code since they will set the condition code to a value corresponding to the
5608 @subsection Computing the Length of an Insn
5609 @cindex insn lengths, computing
5610 @cindex computing the length of an insn
5612 For many machines, multiple types of branch instructions are provided, each
5613 for different length branch displacements. In most cases, the assembler
5614 will choose the correct instruction to use. However, when the assembler
5615 cannot do so, GCC can when a special attribute, the @samp{length}
5616 attribute, is defined. This attribute must be defined to have numeric
5617 values by specifying a null string in its @code{define_attr}.
5619 In the case of the @samp{length} attribute, two additional forms of
5620 arithmetic terms are allowed in test expressions:
5623 @cindex @code{match_dup} and attributes
5624 @item (match_dup @var{n})
5625 This refers to the address of operand @var{n} of the current insn, which
5626 must be a @code{label_ref}.
5628 @cindex @code{pc} and attributes
5630 This refers to the address of the @emph{current} insn. It might have
5631 been more consistent with other usage to make this the address of the
5632 @emph{next} insn but this would be confusing because the length of the
5633 current insn is to be computed.
5636 @cindex @code{addr_vec}, length of
5637 @cindex @code{addr_diff_vec}, length of
5638 For normal insns, the length will be determined by value of the
5639 @samp{length} attribute. In the case of @code{addr_vec} and
5640 @code{addr_diff_vec} insn patterns, the length is computed as
5641 the number of vectors multiplied by the size of each vector.
5643 Lengths are measured in addressable storage units (bytes).
5645 The following macros can be used to refine the length computation:
5648 @findex ADJUST_INSN_LENGTH
5649 @item ADJUST_INSN_LENGTH (@var{insn}, @var{length})
5650 If defined, modifies the length assigned to instruction @var{insn} as a
5651 function of the context in which it is used. @var{length} is an lvalue
5652 that contains the initially computed length of the insn and should be
5653 updated with the correct length of the insn.
5655 This macro will normally not be required. A case in which it is
5656 required is the ROMP@. On this machine, the size of an @code{addr_vec}
5657 insn must be increased by two to compensate for the fact that alignment
5661 @findex get_attr_length
5662 The routine that returns @code{get_attr_length} (the value of the
5663 @code{length} attribute) can be used by the output routine to
5664 determine the form of the branch instruction to be written, as the
5665 example below illustrates.
5667 As an example of the specification of variable-length branches, consider
5668 the IBM 360. If we adopt the convention that a register will be set to
5669 the starting address of a function, we can jump to labels within 4k of
5670 the start using a four-byte instruction. Otherwise, we need a six-byte
5671 sequence to load the address from memory and then branch to it.
5673 On such a machine, a pattern for a branch instruction might be specified
5679 (label_ref (match_operand 0 "" "")))]
5682 return (get_attr_length (insn) == 4
5683 ? "b %l0" : "l r15,=a(%l0); br r15");
5685 [(set (attr "length")
5686 (if_then_else (lt (match_dup 0) (const_int 4096))
5693 @node Constant Attributes
5694 @subsection Constant Attributes
5695 @cindex constant attributes
5697 A special form of @code{define_attr}, where the expression for the
5698 default value is a @code{const} expression, indicates an attribute that
5699 is constant for a given run of the compiler. Constant attributes may be
5700 used to specify which variety of processor is used. For example,
5703 (define_attr "cpu" "m88100,m88110,m88000"
5705 (cond [(symbol_ref "TARGET_88100") (const_string "m88100")
5706 (symbol_ref "TARGET_88110") (const_string "m88110")]
5707 (const_string "m88000"))))
5709 (define_attr "memory" "fast,slow"
5711 (if_then_else (symbol_ref "TARGET_FAST_MEM")
5712 (const_string "fast")
5713 (const_string "slow"))))
5716 The routine generated for constant attributes has no parameters as it
5717 does not depend on any particular insn. RTL expressions used to define
5718 the value of a constant attribute may use the @code{symbol_ref} form,
5719 but may not use either the @code{match_operand} form or @code{eq_attr}
5720 forms involving insn attributes.
5725 @subsection Delay Slot Scheduling
5726 @cindex delay slots, defining
5728 The insn attribute mechanism can be used to specify the requirements for
5729 delay slots, if any, on a target machine. An instruction is said to
5730 require a @dfn{delay slot} if some instructions that are physically
5731 after the instruction are executed as if they were located before it.
5732 Classic examples are branch and call instructions, which often execute
5733 the following instruction before the branch or call is performed.
5735 On some machines, conditional branch instructions can optionally
5736 @dfn{annul} instructions in the delay slot. This means that the
5737 instruction will not be executed for certain branch outcomes. Both
5738 instructions that annul if the branch is true and instructions that
5739 annul if the branch is false are supported.
5741 Delay slot scheduling differs from instruction scheduling in that
5742 determining whether an instruction needs a delay slot is dependent only
5743 on the type of instruction being generated, not on data flow between the
5744 instructions. See the next section for a discussion of data-dependent
5745 instruction scheduling.
5747 @findex define_delay
5748 The requirement of an insn needing one or more delay slots is indicated
5749 via the @code{define_delay} expression. It has the following form:
5752 (define_delay @var{test}
5753 [@var{delay-1} @var{annul-true-1} @var{annul-false-1}
5754 @var{delay-2} @var{annul-true-2} @var{annul-false-2}
5758 @var{test} is an attribute test that indicates whether this
5759 @code{define_delay} applies to a particular insn. If so, the number of
5760 required delay slots is determined by the length of the vector specified
5761 as the second argument. An insn placed in delay slot @var{n} must
5762 satisfy attribute test @var{delay-n}. @var{annul-true-n} is an
5763 attribute test that specifies which insns may be annulled if the branch
5764 is true. Similarly, @var{annul-false-n} specifies which insns in the
5765 delay slot may be annulled if the branch is false. If annulling is not
5766 supported for that delay slot, @code{(nil)} should be coded.
5768 For example, in the common case where branch and call insns require
5769 a single delay slot, which may contain any insn other than a branch or
5770 call, the following would be placed in the @file{md} file:
5773 (define_delay (eq_attr "type" "branch,call")
5774 [(eq_attr "type" "!branch,call") (nil) (nil)])
5777 Multiple @code{define_delay} expressions may be specified. In this
5778 case, each such expression specifies different delay slot requirements
5779 and there must be no insn for which tests in two @code{define_delay}
5780 expressions are both true.
5782 For example, if we have a machine that requires one delay slot for branches
5783 but two for calls, no delay slot can contain a branch or call insn,
5784 and any valid insn in the delay slot for the branch can be annulled if the
5785 branch is true, we might represent this as follows:
5788 (define_delay (eq_attr "type" "branch")
5789 [(eq_attr "type" "!branch,call")
5790 (eq_attr "type" "!branch,call")
5793 (define_delay (eq_attr "type" "call")
5794 [(eq_attr "type" "!branch,call") (nil) (nil)
5795 (eq_attr "type" "!branch,call") (nil) (nil)])
5797 @c the above is *still* too long. --mew 4feb93
5801 @node Processor pipeline description
5802 @subsection Specifying processor pipeline description
5803 @cindex processor pipeline description
5804 @cindex processor functional units
5805 @cindex instruction latency time
5806 @cindex interlock delays
5807 @cindex data dependence delays
5808 @cindex reservation delays
5809 @cindex pipeline hazard recognizer
5810 @cindex automaton based pipeline description
5811 @cindex regular expressions
5812 @cindex deterministic finite state automaton
5813 @cindex automaton based scheduler
5817 To achieve better performance, most modern processors
5818 (super-pipelined, superscalar @acronym{RISC}, and @acronym{VLIW}
5819 processors) have many @dfn{functional units} on which several
5820 instructions can be executed simultaneously. An instruction starts
5821 execution if its issue conditions are satisfied. If not, the
5822 instruction is stalled until its conditions are satisfied. Such
5823 @dfn{interlock (pipeline) delay} causes interruption of the fetching
5824 of successor instructions (or demands nop instructions, e.g. for some
5827 There are two major kinds of interlock delays in modern processors.
5828 The first one is a data dependence delay determining @dfn{instruction
5829 latency time}. The instruction execution is not started until all
5830 source data have been evaluated by prior instructions (there are more
5831 complex cases when the instruction execution starts even when the data
5832 are not available but will be ready in given time after the
5833 instruction execution start). Taking the data dependence delays into
5834 account is simple. The data dependence (true, output, and
5835 anti-dependence) delay between two instructions is given by a
5836 constant. In most cases this approach is adequate. The second kind
5837 of interlock delays is a reservation delay. The reservation delay
5838 means that two instructions under execution will be in need of shared
5839 processors resources, i.e. buses, internal registers, and/or
5840 functional units, which are reserved for some time. Taking this kind
5841 of delay into account is complex especially for modern @acronym{RISC}
5844 The task of exploiting more processor parallelism is solved by an
5845 instruction scheduler. For a better solution to this problem, the
5846 instruction scheduler has to have an adequate description of the
5847 processor parallelism (or @dfn{pipeline description}). GCC
5848 machine descriptions describe processor parallelism and functional
5849 unit reservations for groups of instructions with the aid of
5850 @dfn{regular expressions}.
5852 The GCC instruction scheduler uses a @dfn{pipeline hazard recognizer} to
5853 figure out the possibility of the instruction issue by the processor
5854 on a given simulated processor cycle. The pipeline hazard recognizer is
5855 automatically generated from the processor pipeline description. The
5856 pipeline hazard recognizer generated from the machine description
5857 is based on a deterministic finite state automaton (@acronym{DFA}):
5858 the instruction issue is possible if there is a transition from one
5859 automaton state to another one. This algorithm is very fast, and
5860 furthermore, its speed is not dependent on processor
5861 complexity@footnote{However, the size of the automaton depends on
5862 processor complexity. To limit this effect, machine descriptions
5863 can split orthogonal parts of the machine description among several
5864 automata: but then, since each of these must be stepped independently,
5865 this does cause a small decrease in the algorithm's performance.}.
5867 @cindex automaton based pipeline description
5868 The rest of this section describes the directives that constitute
5869 an automaton-based processor pipeline description. The order of
5870 these constructions within the machine description file is not
5873 @findex define_automaton
5874 @cindex pipeline hazard recognizer
5875 The following optional construction describes names of automata
5876 generated and used for the pipeline hazards recognition. Sometimes
5877 the generated finite state automaton used by the pipeline hazard
5878 recognizer is large. If we use more than one automaton and bind functional
5879 units to the automata, the total size of the automata is usually
5880 less than the size of the single automaton. If there is no one such
5881 construction, only one finite state automaton is generated.
5884 (define_automaton @var{automata-names})
5887 @var{automata-names} is a string giving names of the automata. The
5888 names are separated by commas. All the automata should have unique names.
5889 The automaton name is used in the constructions @code{define_cpu_unit} and
5890 @code{define_query_cpu_unit}.
5892 @findex define_cpu_unit
5893 @cindex processor functional units
5894 Each processor functional unit used in the description of instruction
5895 reservations should be described by the following construction.
5898 (define_cpu_unit @var{unit-names} [@var{automaton-name}])
5901 @var{unit-names} is a string giving the names of the functional units
5902 separated by commas. Don't use name @samp{nothing}, it is reserved
5905 @var{automaton-name} is a string giving the name of the automaton with
5906 which the unit is bound. The automaton should be described in
5907 construction @code{define_automaton}. You should give
5908 @dfn{automaton-name}, if there is a defined automaton.
5910 The assignment of units to automata are constrained by the uses of the
5911 units in insn reservations. The most important constraint is: if a
5912 unit reservation is present on a particular cycle of an alternative
5913 for an insn reservation, then some unit from the same automaton must
5914 be present on the same cycle for the other alternatives of the insn
5915 reservation. The rest of the constraints are mentioned in the
5916 description of the subsequent constructions.
5918 @findex define_query_cpu_unit
5919 @cindex querying function unit reservations
5920 The following construction describes CPU functional units analogously
5921 to @code{define_cpu_unit}. The reservation of such units can be
5922 queried for an automaton state. The instruction scheduler never
5923 queries reservation of functional units for given automaton state. So
5924 as a rule, you don't need this construction. This construction could
5925 be used for future code generation goals (e.g. to generate
5926 @acronym{VLIW} insn templates).
5929 (define_query_cpu_unit @var{unit-names} [@var{automaton-name}])
5932 @var{unit-names} is a string giving names of the functional units
5933 separated by commas.
5935 @var{automaton-name} is a string giving the name of the automaton with
5936 which the unit is bound.
5938 @findex define_insn_reservation
5939 @cindex instruction latency time
5940 @cindex regular expressions
5942 The following construction is the major one to describe pipeline
5943 characteristics of an instruction.
5946 (define_insn_reservation @var{insn-name} @var{default_latency}
5947 @var{condition} @var{regexp})
5950 @var{default_latency} is a number giving latency time of the
5951 instruction. There is an important difference between the old
5952 description and the automaton based pipeline description. The latency
5953 time is used for all dependencies when we use the old description. In
5954 the automaton based pipeline description, the given latency time is only
5955 used for true dependencies. The cost of anti-dependencies is always
5956 zero and the cost of output dependencies is the difference between
5957 latency times of the producing and consuming insns (if the difference
5958 is negative, the cost is considered to be zero). You can always
5959 change the default costs for any description by using the target hook
5960 @code{TARGET_SCHED_ADJUST_COST} (@pxref{Scheduling}).
5962 @var{insn-name} is a string giving the internal name of the insn. The
5963 internal names are used in constructions @code{define_bypass} and in
5964 the automaton description file generated for debugging. The internal
5965 name has nothing in common with the names in @code{define_insn}. It is a
5966 good practice to use insn classes described in the processor manual.
5968 @var{condition} defines what RTL insns are described by this
5969 construction. You should remember that you will be in trouble if
5970 @var{condition} for two or more different
5971 @code{define_insn_reservation} constructions is TRUE for an insn. In
5972 this case what reservation will be used for the insn is not defined.
5973 Such cases are not checked during generation of the pipeline hazards
5974 recognizer because in general recognizing that two conditions may have
5975 the same value is quite difficult (especially if the conditions
5976 contain @code{symbol_ref}). It is also not checked during the
5977 pipeline hazard recognizer work because it would slow down the
5978 recognizer considerably.
5980 @var{regexp} is a string describing the reservation of the cpu's functional
5981 units by the instruction. The reservations are described by a regular
5982 expression according to the following syntax:
5985 regexp = regexp "," oneof
5988 oneof = oneof "|" allof
5991 allof = allof "+" repeat
5994 repeat = element "*" number
5997 element = cpu_function_unit_name
6006 @samp{,} is used for describing the start of the next cycle in
6010 @samp{|} is used for describing a reservation described by the first
6011 regular expression @strong{or} a reservation described by the second
6012 regular expression @strong{or} etc.
6015 @samp{+} is used for describing a reservation described by the first
6016 regular expression @strong{and} a reservation described by the
6017 second regular expression @strong{and} etc.
6020 @samp{*} is used for convenience and simply means a sequence in which
6021 the regular expression are repeated @var{number} times with cycle
6022 advancing (see @samp{,}).
6025 @samp{cpu_function_unit_name} denotes reservation of the named
6029 @samp{reservation_name} --- see description of construction
6030 @samp{define_reservation}.
6033 @samp{nothing} denotes no unit reservations.
6036 @findex define_reservation
6037 Sometimes unit reservations for different insns contain common parts.
6038 In such case, you can simplify the pipeline description by describing
6039 the common part by the following construction
6042 (define_reservation @var{reservation-name} @var{regexp})
6045 @var{reservation-name} is a string giving name of @var{regexp}.
6046 Functional unit names and reservation names are in the same name
6047 space. So the reservation names should be different from the
6048 functional unit names and can not be the reserved name @samp{nothing}.
6050 @findex define_bypass
6051 @cindex instruction latency time
6053 The following construction is used to describe exceptions in the
6054 latency time for given instruction pair. This is so called bypasses.
6057 (define_bypass @var{number} @var{out_insn_names} @var{in_insn_names}
6061 @var{number} defines when the result generated by the instructions
6062 given in string @var{out_insn_names} will be ready for the
6063 instructions given in string @var{in_insn_names}. The instructions in
6064 the string are separated by commas.
6066 @var{guard} is an optional string giving the name of a C function which
6067 defines an additional guard for the bypass. The function will get the
6068 two insns as parameters. If the function returns zero the bypass will
6069 be ignored for this case. The additional guard is necessary to
6070 recognize complicated bypasses, e.g. when the consumer is only an address
6071 of insn @samp{store} (not a stored value).
6073 @findex exclusion_set
6074 @findex presence_set
6075 @findex final_presence_set
6077 @findex final_absence_set
6080 The following five constructions are usually used to describe
6081 @acronym{VLIW} processors, or more precisely, to describe a placement
6082 of small instructions into @acronym{VLIW} instruction slots. They
6083 can be used for @acronym{RISC} processors, too.
6086 (exclusion_set @var{unit-names} @var{unit-names})
6087 (presence_set @var{unit-names} @var{patterns})
6088 (final_presence_set @var{unit-names} @var{patterns})
6089 (absence_set @var{unit-names} @var{patterns})
6090 (final_absence_set @var{unit-names} @var{patterns})
6093 @var{unit-names} is a string giving names of functional units
6094 separated by commas.
6096 @var{patterns} is a string giving patterns of functional units
6097 separated by comma. Currently pattern is is one unit or units
6098 separated by white-spaces.
6100 The first construction (@samp{exclusion_set}) means that each
6101 functional unit in the first string can not be reserved simultaneously
6102 with a unit whose name is in the second string and vice versa. For
6103 example, the construction is useful for describing processors
6104 (e.g. some SPARC processors) with a fully pipelined floating point
6105 functional unit which can execute simultaneously only single floating
6106 point insns or only double floating point insns.
6108 The second construction (@samp{presence_set}) means that each
6109 functional unit in the first string can not be reserved unless at
6110 least one of pattern of units whose names are in the second string is
6111 reserved. This is an asymmetric relation. For example, it is useful
6112 for description that @acronym{VLIW} @samp{slot1} is reserved after
6113 @samp{slot0} reservation. We could describe it by the following
6117 (presence_set "slot1" "slot0")
6120 Or @samp{slot1} is reserved only after @samp{slot0} and unit @samp{b0}
6121 reservation. In this case we could write
6124 (presence_set "slot1" "slot0 b0")
6127 The third construction (@samp{final_presence_set}) is analogous to
6128 @samp{presence_set}. The difference between them is when checking is
6129 done. When an instruction is issued in given automaton state
6130 reflecting all current and planned unit reservations, the automaton
6131 state is changed. The first state is a source state, the second one
6132 is a result state. Checking for @samp{presence_set} is done on the
6133 source state reservation, checking for @samp{final_presence_set} is
6134 done on the result reservation. This construction is useful to
6135 describe a reservation which is actually two subsequent reservations.
6136 For example, if we use
6139 (presence_set "slot1" "slot0")
6142 the following insn will be never issued (because @samp{slot1} requires
6143 @samp{slot0} which is absent in the source state).
6146 (define_reservation "insn_and_nop" "slot0 + slot1")
6149 but it can be issued if we use analogous @samp{final_presence_set}.
6151 The forth construction (@samp{absence_set}) means that each functional
6152 unit in the first string can be reserved only if each pattern of units
6153 whose names are in the second string is not reserved. This is an
6154 asymmetric relation (actually @samp{exclusion_set} is analogous to
6155 this one but it is symmetric). For example, it is useful for
6156 description that @acronym{VLIW} @samp{slot0} can not be reserved after
6157 @samp{slot1} or @samp{slot2} reservation. We could describe it by the
6158 following construction
6161 (absence_set "slot2" "slot0, slot1")
6164 Or @samp{slot2} can not be reserved if @samp{slot0} and unit @samp{b0}
6165 are reserved or @samp{slot1} and unit @samp{b1} are reserved. In
6166 this case we could write
6169 (absence_set "slot2" "slot0 b0, slot1 b1")
6172 All functional units mentioned in a set should belong to the same
6175 The last construction (@samp{final_absence_set}) is analogous to
6176 @samp{absence_set} but checking is done on the result (state)
6177 reservation. See comments for @samp{final_presence_set}.
6179 @findex automata_option
6180 @cindex deterministic finite state automaton
6181 @cindex nondeterministic finite state automaton
6182 @cindex finite state automaton minimization
6183 You can control the generator of the pipeline hazard recognizer with
6184 the following construction.
6187 (automata_option @var{options})
6190 @var{options} is a string giving options which affect the generated
6191 code. Currently there are the following options:
6195 @dfn{no-minimization} makes no minimization of the automaton. This is
6196 only worth to do when we are debugging the description and need to
6197 look more accurately at reservations of states.
6200 @dfn{time} means printing additional time statistics about
6201 generation of automata.
6204 @dfn{v} means a generation of the file describing the result automata.
6205 The file has suffix @samp{.dfa} and can be used for the description
6206 verification and debugging.
6209 @dfn{w} means a generation of warning instead of error for
6210 non-critical errors.
6213 @dfn{ndfa} makes nondeterministic finite state automata. This affects
6214 the treatment of operator @samp{|} in the regular expressions. The
6215 usual treatment of the operator is to try the first alternative and,
6216 if the reservation is not possible, the second alternative. The
6217 nondeterministic treatment means trying all alternatives, some of them
6218 may be rejected by reservations in the subsequent insns. You can not
6219 query functional unit reservations in nondeterministic automaton
6223 @dfn{progress} means output of a progress bar showing how many states
6224 were generated so far for automaton being processed. This is useful
6225 during debugging a @acronym{DFA} description. If you see too many
6226 generated states, you could interrupt the generator of the pipeline
6227 hazard recognizer and try to figure out a reason for generation of the
6231 As an example, consider a superscalar @acronym{RISC} machine which can
6232 issue three insns (two integer insns and one floating point insn) on
6233 the cycle but can finish only two insns. To describe this, we define
6234 the following functional units.
6237 (define_cpu_unit "i0_pipeline, i1_pipeline, f_pipeline")
6238 (define_cpu_unit "port0, port1")
6241 All simple integer insns can be executed in any integer pipeline and
6242 their result is ready in two cycles. The simple integer insns are
6243 issued into the first pipeline unless it is reserved, otherwise they
6244 are issued into the second pipeline. Integer division and
6245 multiplication insns can be executed only in the second integer
6246 pipeline and their results are ready correspondingly in 8 and 4
6247 cycles. The integer division is not pipelined, i.e. the subsequent
6248 integer division insn can not be issued until the current division
6249 insn finished. Floating point insns are fully pipelined and their
6250 results are ready in 3 cycles. Where the result of a floating point
6251 insn is used by an integer insn, an additional delay of one cycle is
6252 incurred. To describe all of this we could specify
6255 (define_cpu_unit "div")
6257 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
6258 "(i0_pipeline | i1_pipeline), (port0 | port1)")
6260 (define_insn_reservation "mult" 4 (eq_attr "type" "mult")
6261 "i1_pipeline, nothing*2, (port0 | port1)")
6263 (define_insn_reservation "div" 8 (eq_attr "type" "div")
6264 "i1_pipeline, div*7, div + (port0 | port1)")
6266 (define_insn_reservation "float" 3 (eq_attr "type" "float")
6267 "f_pipeline, nothing, (port0 | port1))
6269 (define_bypass 4 "float" "simple,mult,div")
6272 To simplify the description we could describe the following reservation
6275 (define_reservation "finish" "port0|port1")
6278 and use it in all @code{define_insn_reservation} as in the following
6282 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
6283 "(i0_pipeline | i1_pipeline), finish")
6289 @node Conditional Execution
6290 @section Conditional Execution
6291 @cindex conditional execution
6294 A number of architectures provide for some form of conditional
6295 execution, or predication. The hallmark of this feature is the
6296 ability to nullify most of the instructions in the instruction set.
6297 When the instruction set is large and not entirely symmetric, it
6298 can be quite tedious to describe these forms directly in the
6299 @file{.md} file. An alternative is the @code{define_cond_exec} template.
6301 @findex define_cond_exec
6304 [@var{predicate-pattern}]
6306 "@var{output-template}")
6309 @var{predicate-pattern} is the condition that must be true for the
6310 insn to be executed at runtime and should match a relational operator.
6311 One can use @code{match_operator} to match several relational operators
6312 at once. Any @code{match_operand} operands must have no more than one
6315 @var{condition} is a C expression that must be true for the generated
6318 @findex current_insn_predicate
6319 @var{output-template} is a string similar to the @code{define_insn}
6320 output template (@pxref{Output Template}), except that the @samp{*}
6321 and @samp{@@} special cases do not apply. This is only useful if the
6322 assembly text for the predicate is a simple prefix to the main insn.
6323 In order to handle the general case, there is a global variable
6324 @code{current_insn_predicate} that will contain the entire predicate
6325 if the current insn is predicated, and will otherwise be @code{NULL}.
6327 When @code{define_cond_exec} is used, an implicit reference to
6328 the @code{predicable} instruction attribute is made.
6329 @xref{Insn Attributes}. This attribute must be boolean (i.e.@: have
6330 exactly two elements in its @var{list-of-values}). Further, it must
6331 not be used with complex expressions. That is, the default and all
6332 uses in the insns must be a simple constant, not dependent on the
6333 alternative or anything else.
6335 For each @code{define_insn} for which the @code{predicable}
6336 attribute is true, a new @code{define_insn} pattern will be
6337 generated that matches a predicated version of the instruction.
6341 (define_insn "addsi"
6342 [(set (match_operand:SI 0 "register_operand" "r")
6343 (plus:SI (match_operand:SI 1 "register_operand" "r")
6344 (match_operand:SI 2 "register_operand" "r")))]
6349 [(ne (match_operand:CC 0 "register_operand" "c")
6356 generates a new pattern
6361 (ne (match_operand:CC 3 "register_operand" "c") (const_int 0))
6362 (set (match_operand:SI 0 "register_operand" "r")
6363 (plus:SI (match_operand:SI 1 "register_operand" "r")
6364 (match_operand:SI 2 "register_operand" "r"))))]
6365 "(@var{test2}) && (@var{test1})"
6366 "(%3) add %2,%1,%0")
6371 @node Constant Definitions
6372 @section Constant Definitions
6373 @cindex constant definitions
6374 @findex define_constants
6376 Using literal constants inside instruction patterns reduces legibility and
6377 can be a maintenance problem.
6379 To overcome this problem, you may use the @code{define_constants}
6380 expression. It contains a vector of name-value pairs. From that
6381 point on, wherever any of the names appears in the MD file, it is as
6382 if the corresponding value had been written instead. You may use
6383 @code{define_constants} multiple times; each appearance adds more
6384 constants to the table. It is an error to redefine a constant with
6387 To come back to the a29k load multiple example, instead of
6391 [(match_parallel 0 "load_multiple_operation"
6392 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
6393 (match_operand:SI 2 "memory_operand" "m"))
6395 (clobber (reg:SI 179))])]
6411 [(match_parallel 0 "load_multiple_operation"
6412 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
6413 (match_operand:SI 2 "memory_operand" "m"))
6415 (clobber (reg:SI R_CR))])]
6420 The constants that are defined with a define_constant are also output
6421 in the insn-codes.h header file as #defines.