1 @c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1996, 1998, 1999, 2000, 2001,
2 @c 2002, 2003, 2004 Free Software Foundation, Inc.
3 @c This is part of the GCC manual.
4 @c For copying conditions, see the file gcc.texi.
8 @chapter Machine Descriptions
9 @cindex machine descriptions
11 A machine description has two parts: a file of instruction patterns
12 (@file{.md} file) and a C header file of macro definitions.
14 The @file{.md} file for a target machine contains a pattern for each
15 instruction that the target machine supports (or at least each instruction
16 that is worth telling the compiler about). It may also contain comments.
17 A semicolon causes the rest of the line to be a comment, unless the semicolon
18 is inside a quoted string.
20 See the next chapter for information on the C header file.
23 * Overview:: How the machine description is used.
24 * Patterns:: How to write instruction patterns.
25 * Example:: An explained example of a @code{define_insn} pattern.
26 * RTL Template:: The RTL template defines what insns match a pattern.
27 * Output Template:: The output template says how to make assembler code
29 * Output Statement:: For more generality, write C code to output
31 * Constraints:: When not all operands are general operands.
32 * Standard Names:: Names mark patterns to use for code generation.
33 * Pattern Ordering:: When the order of patterns makes a difference.
34 * Dependent Patterns:: Having one pattern may make you need another.
35 * Jump Patterns:: Special considerations for patterns for jump insns.
36 * Looping Patterns:: How to define patterns for special looping insns.
37 * Insn Canonicalizations::Canonicalization of Instructions
38 * Expander Definitions::Generating a sequence of several RTL insns
39 for a standard operation.
40 * Insn Splitting:: Splitting Instructions into Multiple Instructions.
41 * Including Patterns:: Including Patterns in Machine Descriptions.
42 * Peephole Definitions::Defining machine-specific peephole optimizations.
43 * Insn Attributes:: Specifying the value of attributes for generated insns.
44 * Conditional Execution::Generating @code{define_insn} patterns for
46 * Constant Definitions::Defining symbolic constants that can be used in the
51 @section Overview of How the Machine Description is Used
53 There are three main conversions that happen in the compiler:
58 The front end reads the source code and builds a parse tree.
61 The parse tree is used to generate an RTL insn list based on named
65 The insn list is matched against the RTL templates to produce assembler
70 For the generate pass, only the names of the insns matter, from either a
71 named @code{define_insn} or a @code{define_expand}. The compiler will
72 choose the pattern with the right name and apply the operands according
73 to the documentation later in this chapter, without regard for the RTL
74 template or operand constraints. Note that the names the compiler looks
75 for are hard-coded in the compiler---it will ignore unnamed patterns and
76 patterns with names it doesn't know about, but if you don't provide a
77 named pattern it needs, it will abort.
79 If a @code{define_insn} is used, the template given is inserted into the
80 insn list. If a @code{define_expand} is used, one of three things
81 happens, based on the condition logic. The condition logic may manually
82 create new insns for the insn list, say via @code{emit_insn()}, and
83 invoke @code{DONE}. For certain named patterns, it may invoke @code{FAIL} to tell the
84 compiler to use an alternate way of performing that task. If it invokes
85 neither @code{DONE} nor @code{FAIL}, the template given in the pattern
86 is inserted, as if the @code{define_expand} were a @code{define_insn}.
88 Once the insn list is generated, various optimization passes convert,
89 replace, and rearrange the insns in the insn list. This is where the
90 @code{define_split} and @code{define_peephole} patterns get used, for
93 Finally, the insn list's RTL is matched up with the RTL templates in the
94 @code{define_insn} patterns, and those patterns are used to emit the
95 final assembly code. For this purpose, each named @code{define_insn}
96 acts like it's unnamed, since the names are ignored.
99 @section Everything about Instruction Patterns
101 @cindex instruction patterns
104 Each instruction pattern contains an incomplete RTL expression, with pieces
105 to be filled in later, operand constraints that restrict how the pieces can
106 be filled in, and an output pattern or C code to generate the assembler
107 output, all wrapped up in a @code{define_insn} expression.
109 A @code{define_insn} is an RTL expression containing four or five operands:
113 An optional name. The presence of a name indicate that this instruction
114 pattern can perform a certain standard job for the RTL-generation
115 pass of the compiler. This pass knows certain names and will use
116 the instruction patterns with those names, if the names are defined
117 in the machine description.
119 The absence of a name is indicated by writing an empty string
120 where the name should go. Nameless instruction patterns are never
121 used for generating RTL code, but they may permit several simpler insns
122 to be combined later on.
124 Names that are not thus known and used in RTL-generation have no
125 effect; they are equivalent to no name at all.
127 For the purpose of debugging the compiler, you may also specify a
128 name beginning with the @samp{*} character. Such a name is used only
129 for identifying the instruction in RTL dumps; it is entirely equivalent
130 to having a nameless pattern for all other purposes.
133 The @dfn{RTL template} (@pxref{RTL Template}) is a vector of incomplete
134 RTL expressions which show what the instruction should look like. It is
135 incomplete because it may contain @code{match_operand},
136 @code{match_operator}, and @code{match_dup} expressions that stand for
137 operands of the instruction.
139 If the vector has only one element, that element is the template for the
140 instruction pattern. If the vector has multiple elements, then the
141 instruction pattern is a @code{parallel} expression containing the
145 @cindex pattern conditions
146 @cindex conditions, in patterns
147 A condition. This is a string which contains a C expression that is
148 the final test to decide whether an insn body matches this pattern.
150 @cindex named patterns and conditions
151 For a named pattern, the condition (if present) may not depend on
152 the data in the insn being matched, but only the target-machine-type
153 flags. The compiler needs to test these conditions during
154 initialization in order to learn exactly which named instructions are
155 available in a particular run.
158 For nameless patterns, the condition is applied only when matching an
159 individual insn, and only after the insn has matched the pattern's
160 recognition template. The insn's operands may be found in the vector
161 @code{operands}. For an insn where the condition has once matched, it
162 can't be used to control register allocation, for example by excluding
163 certain hard registers or hard register combinations.
166 The @dfn{output template}: a string that says how to output matching
167 insns as assembler code. @samp{%} in this string specifies where
168 to substitute the value of an operand. @xref{Output Template}.
170 When simple substitution isn't general enough, you can specify a piece
171 of C code to compute the output. @xref{Output Statement}.
174 Optionally, a vector containing the values of attributes for insns matching
175 this pattern. @xref{Insn Attributes}.
179 @section Example of @code{define_insn}
180 @cindex @code{define_insn} example
182 Here is an actual example of an instruction pattern, for the 68000/68020.
187 (match_operand:SI 0 "general_operand" "rm"))]
191 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
193 return \"cmpl #0,%0\";
198 This can also be written using braced strings:
203 (match_operand:SI 0 "general_operand" "rm"))]
206 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
212 This is an instruction that sets the condition codes based on the value of
213 a general operand. It has no condition, so any insn whose RTL description
214 has the form shown may be handled according to this pattern. The name
215 @samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL generation
216 pass that, when it is necessary to test such a value, an insn to do so
217 can be constructed using this pattern.
219 The output control string is a piece of C code which chooses which
220 output template to return based on the kind of operand and the specific
221 type of CPU for which code is being generated.
223 @samp{"rm"} is an operand constraint. Its meaning is explained below.
226 @section RTL Template
227 @cindex RTL insn template
228 @cindex generating insns
229 @cindex insns, generating
230 @cindex recognizing insns
231 @cindex insns, recognizing
233 The RTL template is used to define which insns match the particular pattern
234 and how to find their operands. For named patterns, the RTL template also
235 says how to construct an insn from specified operands.
237 Construction involves substituting specified operands into a copy of the
238 template. Matching involves determining the values that serve as the
239 operands in the insn being matched. Both of these activities are
240 controlled by special expression types that direct matching and
241 substitution of the operands.
244 @findex match_operand
245 @item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint})
246 This expression is a placeholder for operand number @var{n} of
247 the insn. When constructing an insn, operand number @var{n}
248 will be substituted at this point. When matching an insn, whatever
249 appears at this position in the insn will be taken as operand
250 number @var{n}; but it must satisfy @var{predicate} or this instruction
251 pattern will not match at all.
253 Operand numbers must be chosen consecutively counting from zero in
254 each instruction pattern. There may be only one @code{match_operand}
255 expression in the pattern for each operand number. Usually operands
256 are numbered in the order of appearance in @code{match_operand}
257 expressions. In the case of a @code{define_expand}, any operand numbers
258 used only in @code{match_dup} expressions have higher values than all
259 other operand numbers.
261 @var{predicate} is a string that is the name of a C function that accepts two
262 arguments, an expression and a machine mode. During matching, the
263 function will be called with the putative operand as the expression and
264 @var{m} as the mode argument (if @var{m} is not specified,
265 @code{VOIDmode} will be used, which normally causes @var{predicate} to accept
266 any mode). If it returns zero, this instruction pattern fails to match.
267 @var{predicate} may be an empty string; then it means no test is to be done
268 on the operand, so anything which occurs in this position is valid.
270 Most of the time, @var{predicate} will reject modes other than @var{m}---but
271 not always. For example, the predicate @code{address_operand} uses
272 @var{m} as the mode of memory ref that the address should be valid for.
273 Many predicates accept @code{const_int} nodes even though their mode is
276 @var{constraint} controls reloading and the choice of the best register
277 class to use for a value, as explained later (@pxref{Constraints}).
279 People are often unclear on the difference between the constraint and the
280 predicate. The predicate helps decide whether a given insn matches the
281 pattern. The constraint plays no role in this decision; instead, it
282 controls various decisions in the case of an insn which does match.
284 @findex general_operand
285 On CISC machines, the most common @var{predicate} is
286 @code{"general_operand"}. This function checks that the putative
287 operand is either a constant, a register or a memory reference, and that
288 it is valid for mode @var{m}.
290 @findex register_operand
291 For an operand that must be a register, @var{predicate} should be
292 @code{"register_operand"}. Using @code{"general_operand"} would be
293 valid, since the reload pass would copy any non-register operands
294 through registers, but this would make GCC do extra work, it would
295 prevent invariant operands (such as constant) from being removed from
296 loops, and it would prevent the register allocator from doing the best
297 possible job. On RISC machines, it is usually most efficient to allow
298 @var{predicate} to accept only objects that the constraints allow.
300 @findex immediate_operand
301 For an operand that must be a constant, you must be sure to either use
302 @code{"immediate_operand"} for @var{predicate}, or make the instruction
303 pattern's extra condition require a constant, or both. You cannot
304 expect the constraints to do this work! If the constraints allow only
305 constants, but the predicate allows something else, the compiler will
306 crash when that case arises.
308 @findex match_scratch
309 @item (match_scratch:@var{m} @var{n} @var{constraint})
310 This expression is also a placeholder for operand number @var{n}
311 and indicates that operand must be a @code{scratch} or @code{reg}
314 When matching patterns, this is equivalent to
317 (match_operand:@var{m} @var{n} "scratch_operand" @var{pred})
320 but, when generating RTL, it produces a (@code{scratch}:@var{m})
323 If the last few expressions in a @code{parallel} are @code{clobber}
324 expressions whose operands are either a hard register or
325 @code{match_scratch}, the combiner can add or delete them when
326 necessary. @xref{Side Effects}.
329 @item (match_dup @var{n})
330 This expression is also a placeholder for operand number @var{n}.
331 It is used when the operand needs to appear more than once in the
334 In construction, @code{match_dup} acts just like @code{match_operand}:
335 the operand is substituted into the insn being constructed. But in
336 matching, @code{match_dup} behaves differently. It assumes that operand
337 number @var{n} has already been determined by a @code{match_operand}
338 appearing earlier in the recognition template, and it matches only an
339 identical-looking expression.
341 Note that @code{match_dup} should not be used to tell the compiler that
342 a particular register is being used for two operands (example:
343 @code{add} that adds one register to another; the second register is
344 both an input operand and the output operand). Use a matching
345 constraint (@pxref{Simple Constraints}) for those. @code{match_dup} is for the cases where one
346 operand is used in two places in the template, such as an instruction
347 that computes both a quotient and a remainder, where the opcode takes
348 two input operands but the RTL template has to refer to each of those
349 twice; once for the quotient pattern and once for the remainder pattern.
351 @findex match_operator
352 @item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}])
353 This pattern is a kind of placeholder for a variable RTL expression
356 When constructing an insn, it stands for an RTL expression whose
357 expression code is taken from that of operand @var{n}, and whose
358 operands are constructed from the patterns @var{operands}.
360 When matching an expression, it matches an expression if the function
361 @var{predicate} returns nonzero on that expression @emph{and} the
362 patterns @var{operands} match the operands of the expression.
364 Suppose that the function @code{commutative_operator} is defined as
365 follows, to match any expression whose operator is one of the
366 commutative arithmetic operators of RTL and whose mode is @var{mode}:
370 commutative_operator (x, mode)
372 enum machine_mode mode;
374 enum rtx_code code = GET_CODE (x);
375 if (GET_MODE (x) != mode)
377 return (GET_RTX_CLASS (code) == 'c'
378 || code == EQ || code == NE);
382 Then the following pattern will match any RTL expression consisting
383 of a commutative operator applied to two general operands:
386 (match_operator:SI 3 "commutative_operator"
387 [(match_operand:SI 1 "general_operand" "g")
388 (match_operand:SI 2 "general_operand" "g")])
391 Here the vector @code{[@var{operands}@dots{}]} contains two patterns
392 because the expressions to be matched all contain two operands.
394 When this pattern does match, the two operands of the commutative
395 operator are recorded as operands 1 and 2 of the insn. (This is done
396 by the two instances of @code{match_operand}.) Operand 3 of the insn
397 will be the entire commutative expression: use @code{GET_CODE
398 (operands[3])} to see which commutative operator was used.
400 The machine mode @var{m} of @code{match_operator} works like that of
401 @code{match_operand}: it is passed as the second argument to the
402 predicate function, and that function is solely responsible for
403 deciding whether the expression to be matched ``has'' that mode.
405 When constructing an insn, argument 3 of the gen-function will specify
406 the operation (i.e.@: the expression code) for the expression to be
407 made. It should be an RTL expression, whose expression code is copied
408 into a new expression whose operands are arguments 1 and 2 of the
409 gen-function. The subexpressions of argument 3 are not used;
410 only its expression code matters.
412 When @code{match_operator} is used in a pattern for matching an insn,
413 it usually best if the operand number of the @code{match_operator}
414 is higher than that of the actual operands of the insn. This improves
415 register allocation because the register allocator often looks at
416 operands 1 and 2 of insns to see if it can do register tying.
418 There is no way to specify constraints in @code{match_operator}. The
419 operand of the insn which corresponds to the @code{match_operator}
420 never has any constraints because it is never reloaded as a whole.
421 However, if parts of its @var{operands} are matched by
422 @code{match_operand} patterns, those parts may have constraints of
426 @item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}])
427 Like @code{match_dup}, except that it applies to operators instead of
428 operands. When constructing an insn, operand number @var{n} will be
429 substituted at this point. But in matching, @code{match_op_dup} behaves
430 differently. It assumes that operand number @var{n} has already been
431 determined by a @code{match_operator} appearing earlier in the
432 recognition template, and it matches only an identical-looking
435 @findex match_parallel
436 @item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}])
437 This pattern is a placeholder for an insn that consists of a
438 @code{parallel} expression with a variable number of elements. This
439 expression should only appear at the top level of an insn pattern.
441 When constructing an insn, operand number @var{n} will be substituted at
442 this point. When matching an insn, it matches if the body of the insn
443 is a @code{parallel} expression with at least as many elements as the
444 vector of @var{subpat} expressions in the @code{match_parallel}, if each
445 @var{subpat} matches the corresponding element of the @code{parallel},
446 @emph{and} the function @var{predicate} returns nonzero on the
447 @code{parallel} that is the body of the insn. It is the responsibility
448 of the predicate to validate elements of the @code{parallel} beyond
449 those listed in the @code{match_parallel}.
451 A typical use of @code{match_parallel} is to match load and store
452 multiple expressions, which can contain a variable number of elements
453 in a @code{parallel}. For example,
457 [(match_parallel 0 "load_multiple_operation"
458 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
459 (match_operand:SI 2 "memory_operand" "m"))
461 (clobber (reg:SI 179))])]
466 This example comes from @file{a29k.md}. The function
467 @code{load_multiple_operation} is defined in @file{a29k.c} and checks
468 that subsequent elements in the @code{parallel} are the same as the
469 @code{set} in the pattern, except that they are referencing subsequent
470 registers and memory locations.
472 An insn that matches this pattern might look like:
476 [(set (reg:SI 20) (mem:SI (reg:SI 100)))
478 (clobber (reg:SI 179))
480 (mem:SI (plus:SI (reg:SI 100)
483 (mem:SI (plus:SI (reg:SI 100)
487 @findex match_par_dup
488 @item (match_par_dup @var{n} [@var{subpat}@dots{}])
489 Like @code{match_op_dup}, but for @code{match_parallel} instead of
490 @code{match_operator}.
494 @node Output Template
495 @section Output Templates and Operand Substitution
496 @cindex output templates
497 @cindex operand substitution
499 @cindex @samp{%} in template
501 The @dfn{output template} is a string which specifies how to output the
502 assembler code for an instruction pattern. Most of the template is a
503 fixed string which is output literally. The character @samp{%} is used
504 to specify where to substitute an operand; it can also be used to
505 identify places where different variants of the assembler require
508 In the simplest case, a @samp{%} followed by a digit @var{n} says to output
509 operand @var{n} at that point in the string.
511 @samp{%} followed by a letter and a digit says to output an operand in an
512 alternate fashion. Four letters have standard, built-in meanings described
513 below. The machine description macro @code{PRINT_OPERAND} can define
514 additional letters with nonstandard meanings.
516 @samp{%c@var{digit}} can be used to substitute an operand that is a
517 constant value without the syntax that normally indicates an immediate
520 @samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of
521 the constant is negated before printing.
523 @samp{%a@var{digit}} can be used to substitute an operand as if it were a
524 memory reference, with the actual operand treated as the address. This may
525 be useful when outputting a ``load address'' instruction, because often the
526 assembler syntax for such an instruction requires you to write the operand
527 as if it were a memory reference.
529 @samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump
532 @samp{%=} outputs a number which is unique to each instruction in the
533 entire compilation. This is useful for making local labels to be
534 referred to more than once in a single template that generates multiple
535 assembler instructions.
537 @samp{%} followed by a punctuation character specifies a substitution that
538 does not use an operand. Only one case is standard: @samp{%%} outputs a
539 @samp{%} into the assembler code. Other nonstandard cases can be
540 defined in the @code{PRINT_OPERAND} macro. You must also define
541 which punctuation characters are valid with the
542 @code{PRINT_OPERAND_PUNCT_VALID_P} macro.
546 The template may generate multiple assembler instructions. Write the text
547 for the instructions, with @samp{\;} between them.
549 @cindex matching operands
550 When the RTL contains two operands which are required by constraint to match
551 each other, the output template must refer only to the lower-numbered operand.
552 Matching operands are not always identical, and the rest of the compiler
553 arranges to put the proper RTL expression for printing into the lower-numbered
556 One use of nonstandard letters or punctuation following @samp{%} is to
557 distinguish between different assembler languages for the same machine; for
558 example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax
559 requires periods in most opcode names, while MIT syntax does not. For
560 example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola
561 syntax. The same file of patterns is used for both kinds of output syntax,
562 but the character sequence @samp{%.} is used in each place where Motorola
563 syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax
564 defines the sequence to output a period; the macro for MIT syntax defines
567 @cindex @code{#} in template
568 As a special case, a template consisting of the single character @code{#}
569 instructs the compiler to first split the insn, and then output the
570 resulting instructions separately. This helps eliminate redundancy in the
571 output templates. If you have a @code{define_insn} that needs to emit
572 multiple assembler instructions, and there is an matching @code{define_split}
573 already defined, then you can simply use @code{#} as the output template
574 instead of writing an output template that emits the multiple assembler
577 If the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct
578 of the form @samp{@{option0|option1|option2@}} in the templates. These
579 describe multiple variants of assembler language syntax.
580 @xref{Instruction Output}.
582 @node Output Statement
583 @section C Statements for Assembler Output
584 @cindex output statements
585 @cindex C statements for assembler output
586 @cindex generating assembler output
588 Often a single fixed template string cannot produce correct and efficient
589 assembler code for all the cases that are recognized by a single
590 instruction pattern. For example, the opcodes may depend on the kinds of
591 operands; or some unfortunate combinations of operands may require extra
592 machine instructions.
594 If the output control string starts with a @samp{@@}, then it is actually
595 a series of templates, each on a separate line. (Blank lines and
596 leading spaces and tabs are ignored.) The templates correspond to the
597 pattern's constraint alternatives (@pxref{Multi-Alternative}). For example,
598 if a target machine has a two-address add instruction @samp{addr} to add
599 into a register and another @samp{addm} to add a register to memory, you
600 might write this pattern:
603 (define_insn "addsi3"
604 [(set (match_operand:SI 0 "general_operand" "=r,m")
605 (plus:SI (match_operand:SI 1 "general_operand" "0,0")
606 (match_operand:SI 2 "general_operand" "g,r")))]
613 @cindex @code{*} in template
614 @cindex asterisk in template
615 If the output control string starts with a @samp{*}, then it is not an
616 output template but rather a piece of C program that should compute a
617 template. It should execute a @code{return} statement to return the
618 template-string you want. Most such templates use C string literals, which
619 require doublequote characters to delimit them. To include these
620 doublequote characters in the string, prefix each one with @samp{\}.
622 If the output control string is written as a brace block instead of a
623 double-quoted string, it is automatically assumed to be C code. In that
624 case, it is not necessary to put in a leading asterisk, or to escape the
625 doublequotes surrounding C string literals.
627 The operands may be found in the array @code{operands}, whose C data type
630 It is very common to select different ways of generating assembler code
631 based on whether an immediate operand is within a certain range. Be
632 careful when doing this, because the result of @code{INTVAL} is an
633 integer on the host machine. If the host machine has more bits in an
634 @code{int} than the target machine has in the mode in which the constant
635 will be used, then some of the bits you get from @code{INTVAL} will be
636 superfluous. For proper results, you must carefully disregard the
637 values of those bits.
639 @findex output_asm_insn
640 It is possible to output an assembler instruction and then go on to output
641 or compute more of them, using the subroutine @code{output_asm_insn}. This
642 receives two arguments: a template-string and a vector of operands. The
643 vector may be @code{operands}, or it may be another array of @code{rtx}
644 that you declare locally and initialize yourself.
646 @findex which_alternative
647 When an insn pattern has multiple alternatives in its constraints, often
648 the appearance of the assembler code is determined mostly by which alternative
649 was matched. When this is so, the C code can test the variable
650 @code{which_alternative}, which is the ordinal number of the alternative
651 that was actually satisfied (0 for the first, 1 for the second alternative,
654 For example, suppose there are two opcodes for storing zero, @samp{clrreg}
655 for registers and @samp{clrmem} for memory locations. Here is how
656 a pattern could use @code{which_alternative} to choose between them:
660 [(set (match_operand:SI 0 "general_operand" "=r,m")
664 return (which_alternative == 0
665 ? "clrreg %0" : "clrmem %0");
669 The example above, where the assembler code to generate was
670 @emph{solely} determined by the alternative, could also have been specified
671 as follows, having the output control string start with a @samp{@@}:
676 [(set (match_operand:SI 0 "general_operand" "=r,m")
686 @c Most of this node appears by itself (in a different place) even
687 @c when the INTERNALS flag is clear. Passages that require the internals
688 @c manual's context are conditionalized to appear only in the internals manual.
691 @section Operand Constraints
692 @cindex operand constraints
695 Each @code{match_operand} in an instruction pattern can specify a
696 constraint for the type of operands allowed.
700 @section Constraints for @code{asm} Operands
701 @cindex operand constraints, @code{asm}
702 @cindex constraints, @code{asm}
703 @cindex @code{asm} constraints
705 Here are specific details on what constraint letters you can use with
708 Constraints can say whether
709 an operand may be in a register, and which kinds of register; whether the
710 operand can be a memory reference, and which kinds of address; whether the
711 operand may be an immediate constant, and which possible values it may
712 have. Constraints can also require two operands to match.
716 * Simple Constraints:: Basic use of constraints.
717 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
718 * Class Preferences:: Constraints guide which hard register to put things in.
719 * Modifiers:: More precise control over effects of constraints.
720 * Machine Constraints:: Existing constraints for some particular machines.
726 * Simple Constraints:: Basic use of constraints.
727 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
728 * Modifiers:: More precise control over effects of constraints.
729 * Machine Constraints:: Special constraints for some particular machines.
733 @node Simple Constraints
734 @subsection Simple Constraints
735 @cindex simple constraints
737 The simplest kind of constraint is a string full of letters, each of
738 which describes one kind of operand that is permitted. Here are
739 the letters that are allowed:
743 Whitespace characters are ignored and can be inserted at any position
744 except the first. This enables each alternative for different operands to
745 be visually aligned in the machine description even if they have different
746 number of constraints and modifiers.
748 @cindex @samp{m} in constraint
749 @cindex memory references in constraints
751 A memory operand is allowed, with any kind of address that the machine
754 @cindex offsettable address
755 @cindex @samp{o} in constraint
757 A memory operand is allowed, but only if the address is
758 @dfn{offsettable}. This means that adding a small integer (actually,
759 the width in bytes of the operand, as determined by its machine mode)
760 may be added to the address and the result is also a valid memory
763 @cindex autoincrement/decrement addressing
764 For example, an address which is constant is offsettable; so is an
765 address that is the sum of a register and a constant (as long as a
766 slightly larger constant is also within the range of address-offsets
767 supported by the machine); but an autoincrement or autodecrement
768 address is not offsettable. More complicated indirect/indexed
769 addresses may or may not be offsettable depending on the other
770 addressing modes that the machine supports.
772 Note that in an output operand which can be matched by another
773 operand, the constraint letter @samp{o} is valid only when accompanied
774 by both @samp{<} (if the target machine has predecrement addressing)
775 and @samp{>} (if the target machine has preincrement addressing).
777 @cindex @samp{V} in constraint
779 A memory operand that is not offsettable. In other words, anything that
780 would fit the @samp{m} constraint but not the @samp{o} constraint.
782 @cindex @samp{<} in constraint
784 A memory operand with autodecrement addressing (either predecrement or
785 postdecrement) is allowed.
787 @cindex @samp{>} in constraint
789 A memory operand with autoincrement addressing (either preincrement or
790 postincrement) is allowed.
792 @cindex @samp{r} in constraint
793 @cindex registers in constraints
795 A register operand is allowed provided that it is in a general
798 @cindex constants in constraints
799 @cindex @samp{i} in constraint
801 An immediate integer operand (one with constant value) is allowed.
802 This includes symbolic constants whose values will be known only at
805 @cindex @samp{n} in constraint
807 An immediate integer operand with a known numeric value is allowed.
808 Many systems cannot support assembly-time constants for operands less
809 than a word wide. Constraints for these operands should use @samp{n}
810 rather than @samp{i}.
812 @cindex @samp{I} in constraint
813 @item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P}
814 Other letters in the range @samp{I} through @samp{P} may be defined in
815 a machine-dependent fashion to permit immediate integer operands with
816 explicit integer values in specified ranges. For example, on the
817 68000, @samp{I} is defined to stand for the range of values 1 to 8.
818 This is the range permitted as a shift count in the shift
821 @cindex @samp{E} in constraint
823 An immediate floating operand (expression code @code{const_double}) is
824 allowed, but only if the target floating point format is the same as
825 that of the host machine (on which the compiler is running).
827 @cindex @samp{F} in constraint
829 An immediate floating operand (expression code @code{const_double} or
830 @code{const_vector}) is allowed.
832 @cindex @samp{G} in constraint
833 @cindex @samp{H} in constraint
834 @item @samp{G}, @samp{H}
835 @samp{G} and @samp{H} may be defined in a machine-dependent fashion to
836 permit immediate floating operands in particular ranges of values.
838 @cindex @samp{s} in constraint
840 An immediate integer operand whose value is not an explicit integer is
843 This might appear strange; if an insn allows a constant operand with a
844 value not known at compile time, it certainly must allow any known
845 value. So why use @samp{s} instead of @samp{i}? Sometimes it allows
846 better code to be generated.
848 For example, on the 68000 in a fullword instruction it is possible to
849 use an immediate operand; but if the immediate value is between @minus{}128
850 and 127, better code results from loading the value into a register and
851 using the register. This is because the load into the register can be
852 done with a @samp{moveq} instruction. We arrange for this to happen
853 by defining the letter @samp{K} to mean ``any integer outside the
854 range @minus{}128 to 127'', and then specifying @samp{Ks} in the operand
857 @cindex @samp{g} in constraint
859 Any register, memory or immediate integer operand is allowed, except for
860 registers that are not general registers.
862 @cindex @samp{X} in constraint
865 Any operand whatsoever is allowed, even if it does not satisfy
866 @code{general_operand}. This is normally used in the constraint of
867 a @code{match_scratch} when certain alternatives will not actually
868 require a scratch register.
871 Any operand whatsoever is allowed.
874 @cindex @samp{0} in constraint
875 @cindex digits in constraint
876 @item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9}
877 An operand that matches the specified operand number is allowed. If a
878 digit is used together with letters within the same alternative, the
879 digit should come last.
881 This number is allowed to be more than a single digit. If multiple
882 digits are encountered consecutively, they are interpreted as a single
883 decimal integer. There is scant chance for ambiguity, since to-date
884 it has never been desirable that @samp{10} be interpreted as matching
885 either operand 1 @emph{or} operand 0. Should this be desired, one
886 can use multiple alternatives instead.
888 @cindex matching constraint
889 @cindex constraint, matching
890 This is called a @dfn{matching constraint} and what it really means is
891 that the assembler has only a single operand that fills two roles
893 considered separate in the RTL insn. For example, an add insn has two
894 input operands and one output operand in the RTL, but on most CISC
897 which @code{asm} distinguishes. For example, an add instruction uses
898 two input operands and an output operand, but on most CISC
900 machines an add instruction really has only two operands, one of them an
901 input-output operand:
907 Matching constraints are used in these circumstances.
908 More precisely, the two operands that match must include one input-only
909 operand and one output-only operand. Moreover, the digit must be a
910 smaller number than the number of the operand that uses it in the
914 For operands to match in a particular case usually means that they
915 are identical-looking RTL expressions. But in a few special cases
916 specific kinds of dissimilarity are allowed. For example, @code{*x}
917 as an input operand will match @code{*x++} as an output operand.
918 For proper results in such cases, the output template should always
919 use the output-operand's number when printing the operand.
922 @cindex load address instruction
923 @cindex push address instruction
924 @cindex address constraints
925 @cindex @samp{p} in constraint
927 An operand that is a valid memory address is allowed. This is
928 for ``load address'' and ``push address'' instructions.
930 @findex address_operand
931 @samp{p} in the constraint must be accompanied by @code{address_operand}
932 as the predicate in the @code{match_operand}. This predicate interprets
933 the mode specified in the @code{match_operand} as the mode of the memory
934 reference for which the address would be valid.
936 @cindex other register constraints
937 @cindex extensible constraints
938 @item @var{other-letters}
939 Other letters can be defined in machine-dependent fashion to stand for
940 particular classes of registers or other arbitrary operand types.
941 @samp{d}, @samp{a} and @samp{f} are defined on the 68000/68020 to stand
942 for data, address and floating point registers.
945 The machine description macro @code{REG_CLASS_FROM_LETTER} has first
946 cut at the otherwise unused letters. If it evaluates to @code{NO_REGS},
947 then @code{EXTRA_CONSTRAINT} is evaluated.
949 A typical use for @code{EXTRA_CONSTRAINT} would be to distinguish certain
950 types of memory references that affect other insn operands.
955 In order to have valid assembler code, each operand must satisfy
956 its constraint. But a failure to do so does not prevent the pattern
957 from applying to an insn. Instead, it directs the compiler to modify
958 the code so that the constraint will be satisfied. Usually this is
959 done by copying an operand into a register.
961 Contrast, therefore, the two instruction patterns that follow:
965 [(set (match_operand:SI 0 "general_operand" "=r")
966 (plus:SI (match_dup 0)
967 (match_operand:SI 1 "general_operand" "r")))]
973 which has two operands, one of which must appear in two places, and
977 [(set (match_operand:SI 0 "general_operand" "=r")
978 (plus:SI (match_operand:SI 1 "general_operand" "0")
979 (match_operand:SI 2 "general_operand" "r")))]
985 which has three operands, two of which are required by a constraint to be
986 identical. If we are considering an insn of the form
989 (insn @var{n} @var{prev} @var{next}
991 (plus:SI (reg:SI 6) (reg:SI 109)))
996 the first pattern would not apply at all, because this insn does not
997 contain two identical subexpressions in the right place. The pattern would
998 say, ``That does not look like an add instruction; try other patterns.''
999 The second pattern would say, ``Yes, that's an add instruction, but there
1000 is something wrong with it.'' It would direct the reload pass of the
1001 compiler to generate additional insns to make the constraint true. The
1002 results might look like this:
1005 (insn @var{n2} @var{prev} @var{n}
1006 (set (reg:SI 3) (reg:SI 6))
1009 (insn @var{n} @var{n2} @var{next}
1011 (plus:SI (reg:SI 3) (reg:SI 109)))
1015 It is up to you to make sure that each operand, in each pattern, has
1016 constraints that can handle any RTL expression that could be present for
1017 that operand. (When multiple alternatives are in use, each pattern must,
1018 for each possible combination of operand expressions, have at least one
1019 alternative which can handle that combination of operands.) The
1020 constraints don't need to @emph{allow} any possible operand---when this is
1021 the case, they do not constrain---but they must at least point the way to
1022 reloading any possible operand so that it will fit.
1026 If the constraint accepts whatever operands the predicate permits,
1027 there is no problem: reloading is never necessary for this operand.
1029 For example, an operand whose constraints permit everything except
1030 registers is safe provided its predicate rejects registers.
1032 An operand whose predicate accepts only constant values is safe
1033 provided its constraints include the letter @samp{i}. If any possible
1034 constant value is accepted, then nothing less than @samp{i} will do;
1035 if the predicate is more selective, then the constraints may also be
1039 Any operand expression can be reloaded by copying it into a register.
1040 So if an operand's constraints allow some kind of register, it is
1041 certain to be safe. It need not permit all classes of registers; the
1042 compiler knows how to copy a register into another register of the
1043 proper class in order to make an instruction valid.
1045 @cindex nonoffsettable memory reference
1046 @cindex memory reference, nonoffsettable
1048 A nonoffsettable memory reference can be reloaded by copying the
1049 address into a register. So if the constraint uses the letter
1050 @samp{o}, all memory references are taken care of.
1053 A constant operand can be reloaded by allocating space in memory to
1054 hold it as preinitialized data. Then the memory reference can be used
1055 in place of the constant. So if the constraint uses the letters
1056 @samp{o} or @samp{m}, constant operands are not a problem.
1059 If the constraint permits a constant and a pseudo register used in an insn
1060 was not allocated to a hard register and is equivalent to a constant,
1061 the register will be replaced with the constant. If the predicate does
1062 not permit a constant and the insn is re-recognized for some reason, the
1063 compiler will crash. Thus the predicate must always recognize any
1064 objects allowed by the constraint.
1067 If the operand's predicate can recognize registers, but the constraint does
1068 not permit them, it can make the compiler crash. When this operand happens
1069 to be a register, the reload pass will be stymied, because it does not know
1070 how to copy a register temporarily into memory.
1072 If the predicate accepts a unary operator, the constraint applies to the
1073 operand. For example, the MIPS processor at ISA level 3 supports an
1074 instruction which adds two registers in @code{SImode} to produce a
1075 @code{DImode} result, but only if the registers are correctly sign
1076 extended. This predicate for the input operands accepts a
1077 @code{sign_extend} of an @code{SImode} register. Write the constraint
1078 to indicate the type of register that is required for the operand of the
1082 @node Multi-Alternative
1083 @subsection Multiple Alternative Constraints
1084 @cindex multiple alternative constraints
1086 Sometimes a single instruction has multiple alternative sets of possible
1087 operands. For example, on the 68000, a logical-or instruction can combine
1088 register or an immediate value into memory, or it can combine any kind of
1089 operand into a register; but it cannot combine one memory location into
1092 These constraints are represented as multiple alternatives. An alternative
1093 can be described by a series of letters for each operand. The overall
1094 constraint for an operand is made from the letters for this operand
1095 from the first alternative, a comma, the letters for this operand from
1096 the second alternative, a comma, and so on until the last alternative.
1098 Here is how it is done for fullword logical-or on the 68000:
1101 (define_insn "iorsi3"
1102 [(set (match_operand:SI 0 "general_operand" "=m,d")
1103 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
1104 (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
1108 The first alternative has @samp{m} (memory) for operand 0, @samp{0} for
1109 operand 1 (meaning it must match operand 0), and @samp{dKs} for operand
1110 2. The second alternative has @samp{d} (data register) for operand 0,
1111 @samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and
1112 @samp{%} in the constraints apply to all the alternatives; their
1113 meaning is explained in the next section (@pxref{Class Preferences}).
1116 @c FIXME Is this ? and ! stuff of use in asm()? If not, hide unless INTERNAL
1117 If all the operands fit any one alternative, the instruction is valid.
1118 Otherwise, for each alternative, the compiler counts how many instructions
1119 must be added to copy the operands so that that alternative applies.
1120 The alternative requiring the least copying is chosen. If two alternatives
1121 need the same amount of copying, the one that comes first is chosen.
1122 These choices can be altered with the @samp{?} and @samp{!} characters:
1125 @cindex @samp{?} in constraint
1126 @cindex question mark
1128 Disparage slightly the alternative that the @samp{?} appears in,
1129 as a choice when no alternative applies exactly. The compiler regards
1130 this alternative as one unit more costly for each @samp{?} that appears
1133 @cindex @samp{!} in constraint
1134 @cindex exclamation point
1136 Disparage severely the alternative that the @samp{!} appears in.
1137 This alternative can still be used if it fits without reloading,
1138 but if reloading is needed, some other alternative will be used.
1142 When an insn pattern has multiple alternatives in its constraints, often
1143 the appearance of the assembler code is determined mostly by which
1144 alternative was matched. When this is so, the C code for writing the
1145 assembler code can use the variable @code{which_alternative}, which is
1146 the ordinal number of the alternative that was actually satisfied (0 for
1147 the first, 1 for the second alternative, etc.). @xref{Output Statement}.
1151 @node Class Preferences
1152 @subsection Register Class Preferences
1153 @cindex class preference constraints
1154 @cindex register class preference constraints
1156 @cindex voting between constraint alternatives
1157 The operand constraints have another function: they enable the compiler
1158 to decide which kind of hardware register a pseudo register is best
1159 allocated to. The compiler examines the constraints that apply to the
1160 insns that use the pseudo register, looking for the machine-dependent
1161 letters such as @samp{d} and @samp{a} that specify classes of registers.
1162 The pseudo register is put in whichever class gets the most ``votes''.
1163 The constraint letters @samp{g} and @samp{r} also vote: they vote in
1164 favor of a general register. The machine description says which registers
1165 are considered general.
1167 Of course, on some machines all registers are equivalent, and no register
1168 classes are defined. Then none of this complexity is relevant.
1172 @subsection Constraint Modifier Characters
1173 @cindex modifiers in constraints
1174 @cindex constraint modifier characters
1176 @c prevent bad page break with this line
1177 Here are constraint modifier characters.
1180 @cindex @samp{=} in constraint
1182 Means that this operand is write-only for this instruction: the previous
1183 value is discarded and replaced by output data.
1185 @cindex @samp{+} in constraint
1187 Means that this operand is both read and written by the instruction.
1189 When the compiler fixes up the operands to satisfy the constraints,
1190 it needs to know which operands are inputs to the instruction and
1191 which are outputs from it. @samp{=} identifies an output; @samp{+}
1192 identifies an operand that is both input and output; all other operands
1193 are assumed to be input only.
1195 If you specify @samp{=} or @samp{+} in a constraint, you put it in the
1196 first character of the constraint string.
1198 @cindex @samp{&} in constraint
1199 @cindex earlyclobber operand
1201 Means (in a particular alternative) that this operand is an
1202 @dfn{earlyclobber} operand, which is modified before the instruction is
1203 finished using the input operands. Therefore, this operand may not lie
1204 in a register that is used as an input operand or as part of any memory
1207 @samp{&} applies only to the alternative in which it is written. In
1208 constraints with multiple alternatives, sometimes one alternative
1209 requires @samp{&} while others do not. See, for example, the
1210 @samp{movdf} insn of the 68000.
1212 An input operand can be tied to an earlyclobber operand if its only
1213 use as an input occurs before the early result is written. Adding
1214 alternatives of this form often allows GCC to produce better code
1215 when only some of the inputs can be affected by the earlyclobber.
1216 See, for example, the @samp{mulsi3} insn of the ARM@.
1218 @samp{&} does not obviate the need to write @samp{=}.
1220 @cindex @samp{%} in constraint
1222 Declares the instruction to be commutative for this operand and the
1223 following operand. This means that the compiler may interchange the
1224 two operands if that is the cheapest way to make all operands fit the
1227 This is often used in patterns for addition instructions
1228 that really have only two operands: the result must go in one of the
1229 arguments. Here for example, is how the 68000 halfword-add
1230 instruction is defined:
1233 (define_insn "addhi3"
1234 [(set (match_operand:HI 0 "general_operand" "=m,r")
1235 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
1236 (match_operand:HI 2 "general_operand" "di,g")))]
1240 GCC can only handle one commutative pair in an asm; if you use more,
1241 the compiler may fail.
1243 @cindex @samp{#} in constraint
1245 Says that all following characters, up to the next comma, are to be
1246 ignored as a constraint. They are significant only for choosing
1247 register preferences.
1249 @cindex @samp{*} in constraint
1251 Says that the following character should be ignored when choosing
1252 register preferences. @samp{*} has no effect on the meaning of the
1253 constraint as a constraint, and no effect on reloading.
1256 Here is an example: the 68000 has an instruction to sign-extend a
1257 halfword in a data register, and can also sign-extend a value by
1258 copying it into an address register. While either kind of register is
1259 acceptable, the constraints on an address-register destination are
1260 less strict, so it is best if register allocation makes an address
1261 register its goal. Therefore, @samp{*} is used so that the @samp{d}
1262 constraint letter (for data register) is ignored when computing
1263 register preferences.
1266 (define_insn "extendhisi2"
1267 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1269 (match_operand:HI 1 "general_operand" "0,g")))]
1275 @node Machine Constraints
1276 @subsection Constraints for Particular Machines
1277 @cindex machine specific constraints
1278 @cindex constraints, machine specific
1280 Whenever possible, you should use the general-purpose constraint letters
1281 in @code{asm} arguments, since they will convey meaning more readily to
1282 people reading your code. Failing that, use the constraint letters
1283 that usually have very similar meanings across architectures. The most
1284 commonly used constraints are @samp{m} and @samp{r} (for memory and
1285 general-purpose registers respectively; @pxref{Simple Constraints}), and
1286 @samp{I}, usually the letter indicating the most common
1287 immediate-constant format.
1289 For each machine architecture, the
1290 @file{config/@var{machine}/@var{machine}.h} file defines additional
1291 constraints. These constraints are used by the compiler itself for
1292 instruction generation, as well as for @code{asm} statements; therefore,
1293 some of the constraints are not particularly interesting for @code{asm}.
1294 The constraints are defined through these macros:
1297 @item REG_CLASS_FROM_LETTER
1298 Register class constraints (usually lowercase).
1300 @item CONST_OK_FOR_LETTER_P
1301 Immediate constant constraints, for non-floating point constants of
1302 word size or smaller precision (usually uppercase).
1304 @item CONST_DOUBLE_OK_FOR_LETTER_P
1305 Immediate constant constraints, for all floating point constants and for
1306 constants of greater than word size precision (usually uppercase).
1308 @item EXTRA_CONSTRAINT
1309 Special cases of registers or memory. This macro is not required, and
1310 is only defined for some machines.
1313 Inspecting these macro definitions in the compiler source for your
1314 machine is the best way to be certain you have the right constraints.
1315 However, here is a summary of the machine-dependent constraints
1316 available on some particular machines.
1319 @item ARM family---@file{arm.h}
1322 Floating-point register
1325 VFP floating-point register
1328 One of the floating-point constants 0.0, 0.5, 1.0, 2.0, 3.0, 4.0, 5.0
1332 Floating-point constant that would satisfy the constraint @samp{F} if it
1336 Integer that is valid as an immediate operand in a data processing
1337 instruction. That is, an integer in the range 0 to 255 rotated by a
1341 Integer in the range @minus{}4095 to 4095
1344 Integer that satisfies constraint @samp{I} when inverted (ones complement)
1347 Integer that satisfies constraint @samp{I} when negated (twos complement)
1350 Integer in the range 0 to 32
1353 A memory reference where the exact address is in a single register
1354 (`@samp{m}' is preferable for @code{asm} statements)
1357 An item in the constant pool
1360 A symbol in the text segment of the current file
1364 A memory reference suitable for VFP load/store insns (reg+constant offset)
1366 @item AVR family---@file{avr.h}
1369 Registers from r0 to r15
1372 Registers from r16 to r23
1375 Registers from r16 to r31
1378 Registers from r24 to r31. These registers can be used in @samp{adiw} command
1381 Pointer register (r26--r31)
1384 Base pointer register (r28--r31)
1387 Stack pointer register (SPH:SPL)
1390 Temporary register r0
1393 Register pair X (r27:r26)
1396 Register pair Y (r29:r28)
1399 Register pair Z (r31:r30)
1402 Constant greater than @minus{}1, less than 64
1405 Constant greater than @minus{}64, less than 1
1414 Constant that fits in 8 bits
1417 Constant integer @minus{}1
1420 Constant integer 8, 16, or 24
1426 A floating point constant 0.0
1429 @item PowerPC and IBM RS6000---@file{rs6000.h}
1432 Address base register
1435 Floating point register
1441 @samp{MQ}, @samp{CTR}, or @samp{LINK} register
1450 @samp{LINK} register
1453 @samp{CR} register (condition register) number 0
1456 @samp{CR} register (condition register)
1459 @samp{FPMEM} stack memory for FPR-GPR transfers
1462 Signed 16-bit constant
1465 Unsigned 16-bit constant shifted left 16 bits (use @samp{L} instead for
1466 @code{SImode} constants)
1469 Unsigned 16-bit constant
1472 Signed 16-bit constant shifted left 16 bits
1475 Constant larger than 31
1484 Constant whose negation is a signed 16-bit constant
1487 Floating point constant that can be loaded into a register with one
1488 instruction per word
1491 Memory operand that is an offset from a register (@samp{m} is preferable
1492 for @code{asm} statements)
1498 Constant suitable as a 64-bit mask operand
1501 Constant suitable as a 32-bit mask operand
1504 System V Release 4 small data area reference
1507 @item Intel 386---@file{i386.h}
1510 @samp{a}, @code{b}, @code{c}, or @code{d} register for the i386.
1511 For x86-64 it is equivalent to @samp{r} class. (for 8-bit instructions that
1512 do not use upper halves)
1515 @samp{a}, @code{b}, @code{c}, or @code{d} register. (for 8-bit instructions,
1516 that do use upper halves)
1519 Legacy register---equivalent to @code{r} class in i386 mode.
1520 (for non-8-bit registers used together with 8-bit upper halves in a single
1524 Specifies the @samp{a} or @samp{d} registers. This is primarily useful
1525 for 64-bit integer values (when in 32-bit mode) intended to be returned
1526 with the @samp{d} register holding the most significant bits and the
1527 @samp{a} register holding the least significant bits.
1530 Floating point register
1533 First (top of stack) floating point register
1536 Second floating point register
1548 Specifies constant that can be easily constructed in SSE register without
1549 loading it from memory.
1561 @samp{xmm} SSE register
1567 Constant in range 0 to 31 (for 32-bit shifts)
1570 Constant in range 0 to 63 (for 64-bit shifts)
1579 0, 1, 2, or 3 (shifts for @code{lea} instruction)
1582 Constant in range 0 to 255 (for @code{out} instruction)
1585 Constant in range 0 to @code{0xffffffff} or symbolic reference known to fit specified range.
1586 (for using immediates in zero extending 32-bit to 64-bit x86-64 instructions)
1589 Constant in range @minus{}2147483648 to 2147483647 or symbolic reference known to fit specified range.
1590 (for using immediates in 64-bit x86-64 instructions)
1593 Standard 80387 floating point constant
1596 @item Intel IA-64---@file{ia64.h}
1599 General register @code{r0} to @code{r3} for @code{addl} instruction
1605 Predicate register (@samp{c} as in ``conditional'')
1608 Application register residing in M-unit
1611 Application register residing in I-unit
1614 Floating-point register
1618 Remember that @samp{m} allows postincrement and postdecrement which
1619 require printing with @samp{%Pn} on IA-64.
1620 Use @samp{S} to disallow postincrement and postdecrement.
1623 Floating-point constant 0.0 or 1.0
1626 14-bit signed integer constant
1629 22-bit signed integer constant
1632 8-bit signed integer constant for logical instructions
1635 8-bit adjusted signed integer constant for compare pseudo-ops
1638 6-bit unsigned integer constant for shift counts
1641 9-bit signed integer constant for load and store postincrements
1647 0 or -1 for @code{dep} instruction
1650 Non-volatile memory for floating-point loads and stores
1653 Integer constant in the range 1 to 4 for @code{shladd} instruction
1656 Memory operand except postincrement and postdecrement
1659 @item FRV---@file{frv.h}
1662 Register in the class @code{ACC_REGS} (@code{acc0} to @code{acc7}).
1665 Register in the class @code{EVEN_ACC_REGS} (@code{acc0} to @code{acc7}).
1668 Register in the class @code{CC_REGS} (@code{fcc0} to @code{fcc3} and
1669 @code{icc0} to @code{icc3}).
1672 Register in the class @code{GPR_REGS} (@code{gr0} to @code{gr63}).
1675 Register in the class @code{EVEN_REGS} (@code{gr0} to @code{gr63}).
1676 Odd registers are excluded not in the class but through the use of a machine
1677 mode larger than 4 bytes.
1680 Register in the class @code{FPR_REGS} (@code{fr0} to @code{fr63}).
1683 Register in the class @code{FEVEN_REGS} (@code{fr0} to @code{fr63}).
1684 Odd registers are excluded not in the class but through the use of a machine
1685 mode larger than 4 bytes.
1688 Register in the class @code{LR_REG} (the @code{lr} register).
1691 Register in the class @code{QUAD_REGS} (@code{gr2} to @code{gr63}).
1692 Register numbers not divisible by 4 are excluded not in the class but through
1693 the use of a machine mode larger than 8 bytes.
1696 Register in the class @code{ICC_REGS} (@code{icc0} to @code{icc3}).
1699 Register in the class @code{FCC_REGS} (@code{fcc0} to @code{fcc3}).
1702 Register in the class @code{ICR_REGS} (@code{cc4} to @code{cc7}).
1705 Register in the class @code{FCR_REGS} (@code{cc0} to @code{cc3}).
1708 Register in the class @code{QUAD_FPR_REGS} (@code{fr0} to @code{fr63}).
1709 Register numbers not divisible by 4 are excluded not in the class but through
1710 the use of a machine mode larger than 8 bytes.
1713 Register in the class @code{SPR_REGS} (@code{lcr} and @code{lr}).
1716 Register in the class @code{QUAD_ACC_REGS} (@code{acc0} to @code{acc7}).
1719 Register in the class @code{ACCG_REGS} (@code{accg0} to @code{accg7}).
1722 Register in the class @code{CR_REGS} (@code{cc0} to @code{cc7}).
1725 Floating point constant zero
1728 6-bit signed integer constant
1731 10-bit signed integer constant
1734 16-bit signed integer constant
1737 16-bit unsigned integer constant
1740 12-bit signed integer constant that is negative---i.e.@: in the
1741 range of @minus{}2048 to @minus{}1
1747 12-bit signed integer constant that is greater than zero---i.e.@: in the
1752 @item IP2K---@file{ip2k.h}
1755 @samp{DP} or @samp{IP} registers (general address)
1779 @samp{DP} or @samp{SP} registers (offsettable address)
1782 Non-pointer registers (not @samp{SP}, @samp{DP}, @samp{IP})
1785 Non-SP registers (everything except @samp{SP})
1788 Indirect through @samp{IP} - Avoid this except for @code{QImode}, since we
1789 can't access extra bytes
1792 Indirect through @samp{SP} or @samp{DP} with short displacement (0..127)
1795 Data-section immediate value
1798 Integers from @minus{}255 to @minus{}1
1801 Integers from 0 to 7---valid bit number in a register
1804 Integers from 0 to 127---valid displacement for addressing mode
1807 Integers from 1 to 127
1819 Integers from 0 to 255
1822 @item MIPS---@file{mips.h}
1825 General-purpose integer register
1828 Floating-point register (if available)
1837 @samp{Hi} or @samp{Lo} register
1840 General-purpose integer register
1843 Floating-point status register
1846 Signed 16-bit constant (for arithmetic instructions)
1852 Zero-extended 16-bit constant (for logic instructions)
1855 Constant with low 16 bits zero (can be loaded with @code{lui})
1858 32-bit constant which requires two instructions to load (a constant
1859 which is not @samp{I}, @samp{K}, or @samp{L})
1862 Negative 16-bit constant
1868 Positive 16-bit constant
1874 Memory reference that can be loaded with more than one instruction
1875 (@samp{m} is preferable for @code{asm} statements)
1878 Memory reference that can be loaded with one instruction
1879 (@samp{m} is preferable for @code{asm} statements)
1882 Memory reference in external OSF/rose PIC format
1883 (@samp{m} is preferable for @code{asm} statements)
1886 @item Motorola 680x0---@file{m68k.h}
1895 68881 floating-point register, if available
1898 Integer in the range 1 to 8
1901 16-bit signed number
1904 Signed number whose magnitude is greater than 0x80
1907 Integer in the range @minus{}8 to @minus{}1
1910 Signed number whose magnitude is greater than 0x100
1913 Floating point constant that is not a 68881 constant
1916 @item Motorola 68HC11 & 68HC12 families---@file{m68hc11.h}
1931 Temporary soft register _.tmp
1934 A soft register _.d1 to _.d31
1937 Stack pointer register
1946 Pseudo register 'z' (replaced by 'x' or 'y' at the end)
1949 An address register: x, y or z
1952 An address register: x or y
1955 Register pair (x:d) to form a 32-bit value
1958 Constants in the range @minus{}65536 to 65535
1961 Constants whose 16-bit low part is zero
1964 Constant integer 1 or @minus{}1
1970 Constants in the range @minus{}8 to 2
1975 @item SPARC---@file{sparc.h}
1978 Floating-point register on the SPARC-V8 architecture and
1979 lower floating-point register on the SPARC-V9 architecture.
1982 Floating-point register. It is equivalent to @samp{f} on the
1983 SPARC-V8 architecture and contains both lower and upper
1984 floating-point registers on the SPARC-V9 architecture.
1987 Floating-point condition code register.
1990 Lower floating-point register. It is only valid on the SPARC-V9
1991 architecture when the Visual Instruction Set is available.
1994 Floating-point register. It is only valid on the SPARC-V9 architecture
1995 when the Visual Instruction Set is available.
1998 64-bit global or out register for the SPARC-V8+ architecture.
2001 Signed 13-bit constant
2007 32-bit constant with the low 12 bits clear (a constant that can be
2008 loaded with the @code{sethi} instruction)
2011 A constant in the range supported by @code{movcc} instructions
2014 A constant in the range supported by @code{movrcc} instructions
2017 Same as @samp{K}, except that it verifies that bits that are not in the
2018 lower 32-bit range are all zero. Must be used instead of @samp{K} for
2019 modes wider than @code{SImode}
2028 Signed 13-bit constant, sign-extended to 32 or 64 bits
2031 Floating-point constant whose integral representation can
2032 be moved into an integer register using a single sethi
2036 Floating-point constant whose integral representation can
2037 be moved into an integer register using a single mov
2041 Floating-point constant whose integral representation can
2042 be moved into an integer register using a high/lo_sum
2043 instruction sequence
2046 Memory address aligned to an 8-byte boundary
2052 Memory address for @samp{e} constraint registers.
2056 @item TMS320C3x/C4x---@file{c4x.h}
2059 Auxiliary (address) register (ar0-ar7)
2062 Stack pointer register (sp)
2065 Standard (32-bit) precision integer register
2068 Extended (40-bit) precision register (r0-r11)
2071 Block count register (bk)
2074 Extended (40-bit) precision low register (r0-r7)
2077 Extended (40-bit) precision register (r0-r1)
2080 Extended (40-bit) precision register (r2-r3)
2083 Repeat count register (rc)
2086 Index register (ir0-ir1)
2089 Status (condition code) register (st)
2092 Data page register (dp)
2098 Immediate 16-bit floating-point constant
2101 Signed 16-bit constant
2104 Signed 8-bit constant
2107 Signed 5-bit constant
2110 Unsigned 16-bit constant
2113 Unsigned 8-bit constant
2116 Ones complement of unsigned 16-bit constant
2119 High 16-bit constant (32-bit constant with 16 LSBs zero)
2122 Indirect memory reference with signed 8-bit or index register displacement
2125 Indirect memory reference with unsigned 5-bit displacement
2128 Indirect memory reference with 1 bit or index register displacement
2131 Direct memory reference
2138 @item S/390 and zSeries---@file{s390.h}
2141 Address register (general purpose register except r0)
2144 Data register (arbitrary general purpose register)
2147 Floating-point register
2150 Unsigned 8-bit constant (0--255)
2153 Unsigned 12-bit constant (0--4095)
2156 Signed 16-bit constant (@minus{}32768--32767)
2159 Value appropriate as displacement.
2162 for short displacement
2163 @item (-524288..524287)
2164 for long displacement
2168 Constant integer with a value of 0x7fffffff.
2171 Multiple letter constraint followed by 4 parameter letters.
2174 number of the part counting from most to least significant
2178 mode of the containing operand
2180 value of the other parts (F - all bits set)
2182 The constraint matches if the specified part of a constant
2183 has a value different from it's other parts.
2186 Memory reference without index register and with short displacement.
2189 Memory reference with index register and short displacement.
2192 Memory reference without index register but with long displacement.
2195 Memory reference with index register and long displacement.
2198 Pointer with short displacement.
2201 Pointer with long displacement.
2204 Shift count operand.
2208 @item Xstormy16---@file{stormy16.h}
2223 Registers r0 through r7.
2226 Registers r0 and r1.
2232 Registers r8 and r9.
2235 A constant between 0 and 3 inclusive.
2238 A constant that has exactly one bit set.
2241 A constant that has exactly one bit clear.
2244 A constant between 0 and 255 inclusive.
2247 A constant between @minus{}255 and 0 inclusive.
2250 A constant between @minus{}3 and 0 inclusive.
2253 A constant between 1 and 4 inclusive.
2256 A constant between @minus{}4 and @minus{}1 inclusive.
2259 A memory reference that is a stack push.
2262 A memory reference that is a stack pop.
2265 A memory reference that refers to a constant address of known value.
2268 The register indicated by Rx (not implemented yet).
2271 A constant that is not between 2 and 15 inclusive.
2278 @item Xtensa---@file{xtensa.h}
2281 General-purpose 32-bit register
2284 One-bit boolean register
2287 MAC16 40-bit accumulator register
2290 Signed 12-bit integer constant, for use in MOVI instructions
2293 Signed 8-bit integer constant, for use in ADDI instructions
2296 Integer constant valid for BccI instructions
2299 Unsigned constant valid for BccUI instructions
2306 @node Standard Names
2307 @section Standard Pattern Names For Generation
2308 @cindex standard pattern names
2309 @cindex pattern names
2310 @cindex names, pattern
2312 Here is a table of the instruction names that are meaningful in the RTL
2313 generation pass of the compiler. Giving one of these names to an
2314 instruction pattern tells the RTL generation pass that it can use the
2315 pattern to accomplish a certain task.
2318 @cindex @code{mov@var{m}} instruction pattern
2319 @item @samp{mov@var{m}}
2320 Here @var{m} stands for a two-letter machine mode name, in lowercase.
2321 This instruction pattern moves data with that machine mode from operand
2322 1 to operand 0. For example, @samp{movsi} moves full-word data.
2324 If operand 0 is a @code{subreg} with mode @var{m} of a register whose
2325 own mode is wider than @var{m}, the effect of this instruction is
2326 to store the specified value in the part of the register that corresponds
2327 to mode @var{m}. Bits outside of @var{m}, but which are within the
2328 same target word as the @code{subreg} are undefined. Bits which are
2329 outside the target word are left unchanged.
2331 This class of patterns is special in several ways. First of all, each
2332 of these names up to and including full word size @emph{must} be defined,
2333 because there is no other way to copy a datum from one place to another.
2334 If there are patterns accepting operands in larger modes,
2335 @samp{mov@var{m}} must be defined for integer modes of those sizes.
2337 Second, these patterns are not used solely in the RTL generation pass.
2338 Even the reload pass can generate move insns to copy values from stack
2339 slots into temporary registers. When it does so, one of the operands is
2340 a hard register and the other is an operand that can need to be reloaded
2344 Therefore, when given such a pair of operands, the pattern must generate
2345 RTL which needs no reloading and needs no temporary registers---no
2346 registers other than the operands. For example, if you support the
2347 pattern with a @code{define_expand}, then in such a case the
2348 @code{define_expand} mustn't call @code{force_reg} or any other such
2349 function which might generate new pseudo registers.
2351 This requirement exists even for subword modes on a RISC machine where
2352 fetching those modes from memory normally requires several insns and
2353 some temporary registers.
2355 @findex change_address
2356 During reload a memory reference with an invalid address may be passed
2357 as an operand. Such an address will be replaced with a valid address
2358 later in the reload pass. In this case, nothing may be done with the
2359 address except to use it as it stands. If it is copied, it will not be
2360 replaced with a valid address. No attempt should be made to make such
2361 an address into a valid address and no routine (such as
2362 @code{change_address}) that will do so may be called. Note that
2363 @code{general_operand} will fail when applied to such an address.
2365 @findex reload_in_progress
2366 The global variable @code{reload_in_progress} (which must be explicitly
2367 declared if required) can be used to determine whether such special
2368 handling is required.
2370 The variety of operands that have reloads depends on the rest of the
2371 machine description, but typically on a RISC machine these can only be
2372 pseudo registers that did not get hard registers, while on other
2373 machines explicit memory references will get optional reloads.
2375 If a scratch register is required to move an object to or from memory,
2376 it can be allocated using @code{gen_reg_rtx} prior to life analysis.
2378 If there are cases which need scratch registers during or after reload,
2379 you must define @code{SECONDARY_INPUT_RELOAD_CLASS} and/or
2380 @code{SECONDARY_OUTPUT_RELOAD_CLASS} to detect them, and provide
2381 patterns @samp{reload_in@var{m}} or @samp{reload_out@var{m}} to handle
2382 them. @xref{Register Classes}.
2384 @findex no_new_pseudos
2385 The global variable @code{no_new_pseudos} can be used to determine if it
2386 is unsafe to create new pseudo registers. If this variable is nonzero, then
2387 it is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo.
2389 The constraints on a @samp{mov@var{m}} must permit moving any hard
2390 register to any other hard register provided that
2391 @code{HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and
2392 @code{REGISTER_MOVE_COST} applied to their classes returns a value of 2.
2394 It is obligatory to support floating point @samp{mov@var{m}}
2395 instructions into and out of any registers that can hold fixed point
2396 values, because unions and structures (which have modes @code{SImode} or
2397 @code{DImode}) can be in those registers and they may have floating
2400 There may also be a need to support fixed point @samp{mov@var{m}}
2401 instructions in and out of floating point registers. Unfortunately, I
2402 have forgotten why this was so, and I don't know whether it is still
2403 true. If @code{HARD_REGNO_MODE_OK} rejects fixed point values in
2404 floating point registers, then the constraints of the fixed point
2405 @samp{mov@var{m}} instructions must be designed to avoid ever trying to
2406 reload into a floating point register.
2408 @cindex @code{reload_in} instruction pattern
2409 @cindex @code{reload_out} instruction pattern
2410 @item @samp{reload_in@var{m}}
2411 @itemx @samp{reload_out@var{m}}
2412 Like @samp{mov@var{m}}, but used when a scratch register is required to
2413 move between operand 0 and operand 1. Operand 2 describes the scratch
2414 register. See the discussion of the @code{SECONDARY_RELOAD_CLASS}
2415 macro in @pxref{Register Classes}.
2417 There are special restrictions on the form of the @code{match_operand}s
2418 used in these patterns. First, only the predicate for the reload
2419 operand is examined, i.e., @code{reload_in} examines operand 1, but not
2420 the predicates for operand 0 or 2. Second, there may be only one
2421 alternative in the constraints. Third, only a single register class
2422 letter may be used for the constraint; subsequent constraint letters
2423 are ignored. As a special exception, an empty constraint string
2424 matches the @code{ALL_REGS} register class. This may relieve ports
2425 of the burden of defining an @code{ALL_REGS} constraint letter just
2428 @cindex @code{movstrict@var{m}} instruction pattern
2429 @item @samp{movstrict@var{m}}
2430 Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg}
2431 with mode @var{m} of a register whose natural mode is wider,
2432 the @samp{movstrict@var{m}} instruction is guaranteed not to alter
2433 any of the register except the part which belongs to mode @var{m}.
2435 @cindex @code{load_multiple} instruction pattern
2436 @item @samp{load_multiple}
2437 Load several consecutive memory locations into consecutive registers.
2438 Operand 0 is the first of the consecutive registers, operand 1
2439 is the first memory location, and operand 2 is a constant: the
2440 number of consecutive registers.
2442 Define this only if the target machine really has such an instruction;
2443 do not define this if the most efficient way of loading consecutive
2444 registers from memory is to do them one at a time.
2446 On some machines, there are restrictions as to which consecutive
2447 registers can be stored into memory, such as particular starting or
2448 ending register numbers or only a range of valid counts. For those
2449 machines, use a @code{define_expand} (@pxref{Expander Definitions})
2450 and make the pattern fail if the restrictions are not met.
2452 Write the generated insn as a @code{parallel} with elements being a
2453 @code{set} of one register from the appropriate memory location (you may
2454 also need @code{use} or @code{clobber} elements). Use a
2455 @code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See
2456 @file{rs6000.md} for examples of the use of this insn pattern.
2458 @cindex @samp{store_multiple} instruction pattern
2459 @item @samp{store_multiple}
2460 Similar to @samp{load_multiple}, but store several consecutive registers
2461 into consecutive memory locations. Operand 0 is the first of the
2462 consecutive memory locations, operand 1 is the first register, and
2463 operand 2 is a constant: the number of consecutive registers.
2465 @cindex @code{push@var{m}} instruction pattern
2466 @item @samp{push@var{m}}
2467 Output a push instruction. Operand 0 is value to push. Used only when
2468 @code{PUSH_ROUNDING} is defined. For historical reason, this pattern may be
2469 missing and in such case an @code{mov} expander is used instead, with a
2470 @code{MEM} expression forming the push operation. The @code{mov} expander
2471 method is deprecated.
2473 @cindex @code{add@var{m}3} instruction pattern
2474 @item @samp{add@var{m}3}
2475 Add operand 2 and operand 1, storing the result in operand 0. All operands
2476 must have mode @var{m}. This can be used even on two-address machines, by
2477 means of constraints requiring operands 1 and 0 to be the same location.
2479 @cindex @code{sub@var{m}3} instruction pattern
2480 @cindex @code{mul@var{m}3} instruction pattern
2481 @cindex @code{div@var{m}3} instruction pattern
2482 @cindex @code{udiv@var{m}3} instruction pattern
2483 @cindex @code{mod@var{m}3} instruction pattern
2484 @cindex @code{umod@var{m}3} instruction pattern
2485 @cindex @code{smin@var{m}3} instruction pattern
2486 @cindex @code{smax@var{m}3} instruction pattern
2487 @cindex @code{umin@var{m}3} instruction pattern
2488 @cindex @code{umax@var{m}3} instruction pattern
2489 @cindex @code{and@var{m}3} instruction pattern
2490 @cindex @code{ior@var{m}3} instruction pattern
2491 @cindex @code{xor@var{m}3} instruction pattern
2492 @item @samp{sub@var{m}3}, @samp{mul@var{m}3}
2493 @itemx @samp{div@var{m}3}, @samp{udiv@var{m}3}, @samp{mod@var{m}3}, @samp{umod@var{m}3}
2494 @itemx @samp{smin@var{m}3}, @samp{smax@var{m}3}, @samp{umin@var{m}3}, @samp{umax@var{m}3}
2495 @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3}
2496 Similar, for other arithmetic operations.
2497 @cindex @code{min@var{m}3} instruction pattern
2498 @cindex @code{max@var{m}3} instruction pattern
2499 @itemx @samp{min@var{m}3}, @samp{max@var{m}3}
2500 Floating point min and max operations. If both operands are zeros,
2501 or if either operand is NaN, then it is unspecified which of the two
2502 operands is returned as the result.
2505 @cindex @code{mulhisi3} instruction pattern
2506 @item @samp{mulhisi3}
2507 Multiply operands 1 and 2, which have mode @code{HImode}, and store
2508 a @code{SImode} product in operand 0.
2510 @cindex @code{mulqihi3} instruction pattern
2511 @cindex @code{mulsidi3} instruction pattern
2512 @item @samp{mulqihi3}, @samp{mulsidi3}
2513 Similar widening-multiplication instructions of other widths.
2515 @cindex @code{umulqihi3} instruction pattern
2516 @cindex @code{umulhisi3} instruction pattern
2517 @cindex @code{umulsidi3} instruction pattern
2518 @item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3}
2519 Similar widening-multiplication instructions that do unsigned
2522 @cindex @code{smul@var{m}3_highpart} instruction pattern
2523 @item @samp{smul@var{m}3_highpart}
2524 Perform a signed multiplication of operands 1 and 2, which have mode
2525 @var{m}, and store the most significant half of the product in operand 0.
2526 The least significant half of the product is discarded.
2528 @cindex @code{umul@var{m}3_highpart} instruction pattern
2529 @item @samp{umul@var{m}3_highpart}
2530 Similar, but the multiplication is unsigned.
2532 @cindex @code{divmod@var{m}4} instruction pattern
2533 @item @samp{divmod@var{m}4}
2534 Signed division that produces both a quotient and a remainder.
2535 Operand 1 is divided by operand 2 to produce a quotient stored
2536 in operand 0 and a remainder stored in operand 3.
2538 For machines with an instruction that produces both a quotient and a
2539 remainder, provide a pattern for @samp{divmod@var{m}4} but do not
2540 provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This
2541 allows optimization in the relatively common case when both the quotient
2542 and remainder are computed.
2544 If an instruction that just produces a quotient or just a remainder
2545 exists and is more efficient than the instruction that produces both,
2546 write the output routine of @samp{divmod@var{m}4} to call
2547 @code{find_reg_note} and look for a @code{REG_UNUSED} note on the
2548 quotient or remainder and generate the appropriate instruction.
2550 @cindex @code{udivmod@var{m}4} instruction pattern
2551 @item @samp{udivmod@var{m}4}
2552 Similar, but does unsigned division.
2554 @cindex @code{ashl@var{m}3} instruction pattern
2555 @item @samp{ashl@var{m}3}
2556 Arithmetic-shift operand 1 left by a number of bits specified by operand
2557 2, and store the result in operand 0. Here @var{m} is the mode of
2558 operand 0 and operand 1; operand 2's mode is specified by the
2559 instruction pattern, and the compiler will convert the operand to that
2560 mode before generating the instruction.
2562 @cindex @code{ashr@var{m}3} instruction pattern
2563 @cindex @code{lshr@var{m}3} instruction pattern
2564 @cindex @code{rotl@var{m}3} instruction pattern
2565 @cindex @code{rotr@var{m}3} instruction pattern
2566 @item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3}
2567 Other shift and rotate instructions, analogous to the
2568 @code{ashl@var{m}3} instructions.
2570 @cindex @code{neg@var{m}2} instruction pattern
2571 @item @samp{neg@var{m}2}
2572 Negate operand 1 and store the result in operand 0.
2574 @cindex @code{abs@var{m}2} instruction pattern
2575 @item @samp{abs@var{m}2}
2576 Store the absolute value of operand 1 into operand 0.
2578 @cindex @code{sqrt@var{m}2} instruction pattern
2579 @item @samp{sqrt@var{m}2}
2580 Store the square root of operand 1 into operand 0.
2582 The @code{sqrt} built-in function of C always uses the mode which
2583 corresponds to the C data type @code{double} and the @code{sqrtf}
2584 built-in function uses the mode which corresponds to the C data
2587 @cindex @code{cos@var{m}2} instruction pattern
2588 @item @samp{cos@var{m}2}
2589 Store the cosine of operand 1 into operand 0.
2591 The @code{cos} built-in function of C always uses the mode which
2592 corresponds to the C data type @code{double} and the @code{cosf}
2593 built-in function uses the mode which corresponds to the C data
2596 @cindex @code{sin@var{m}2} instruction pattern
2597 @item @samp{sin@var{m}2}
2598 Store the sine of operand 1 into operand 0.
2600 The @code{sin} built-in function of C always uses the mode which
2601 corresponds to the C data type @code{double} and the @code{sinf}
2602 built-in function uses the mode which corresponds to the C data
2605 @cindex @code{exp@var{m}2} instruction pattern
2606 @item @samp{exp@var{m}2}
2607 Store the exponential of operand 1 into operand 0.
2609 The @code{exp} built-in function of C always uses the mode which
2610 corresponds to the C data type @code{double} and the @code{expf}
2611 built-in function uses the mode which corresponds to the C data
2614 @cindex @code{log@var{m}2} instruction pattern
2615 @item @samp{log@var{m}2}
2616 Store the natural logarithm of operand 1 into operand 0.
2618 The @code{log} built-in function of C always uses the mode which
2619 corresponds to the C data type @code{double} and the @code{logf}
2620 built-in function uses the mode which corresponds to the C data
2623 @cindex @code{pow@var{m}3} instruction pattern
2624 @item @samp{pow@var{m}3}
2625 Store the value of operand 1 raised to the exponent operand 2
2628 The @code{pow} built-in function of C always uses the mode which
2629 corresponds to the C data type @code{double} and the @code{powf}
2630 built-in function uses the mode which corresponds to the C data
2633 @cindex @code{atan2@var{m}3} instruction pattern
2634 @item @samp{atan2@var{m}3}
2635 Store the arc tangent (inverse tangent) of operand 1 divided by
2636 operand 2 into operand 0, using the signs of both arguments to
2637 determine the quadrant of the result.
2639 The @code{atan2} built-in function of C always uses the mode which
2640 corresponds to the C data type @code{double} and the @code{atan2f}
2641 built-in function uses the mode which corresponds to the C data
2644 @cindex @code{floor@var{m}2} instruction pattern
2645 @item @samp{floor@var{m}2}
2646 Store the largest integral value not greater than argument.
2648 The @code{floor} built-in function of C always uses the mode which
2649 corresponds to the C data type @code{double} and the @code{floorf}
2650 built-in function uses the mode which corresponds to the C data
2653 @cindex @code{trunc@var{m}2} instruction pattern
2654 @item @samp{trunc@var{m}2}
2655 Store the argument rounded to integer towards zero.
2657 The @code{trunc} built-in function of C always uses the mode which
2658 corresponds to the C data type @code{double} and the @code{truncf}
2659 built-in function uses the mode which corresponds to the C data
2662 @cindex @code{round@var{m}2} instruction pattern
2663 @item @samp{round@var{m}2}
2664 Store the argument rounded to integer away from zero.
2666 The @code{round} built-in function of C always uses the mode which
2667 corresponds to the C data type @code{double} and the @code{roundf}
2668 built-in function uses the mode which corresponds to the C data
2671 @cindex @code{ceil@var{m}2} instruction pattern
2672 @item @samp{ceil@var{m}2}
2673 Store the argument rounded to integer away from zero.
2675 The @code{ceil} built-in function of C always uses the mode which
2676 corresponds to the C data type @code{double} and the @code{ceilf}
2677 built-in function uses the mode which corresponds to the C data
2680 @cindex @code{nearbyint@var{m}2} instruction pattern
2681 @item @samp{nearbyint@var{m}2}
2682 Store the argument rounded according to the default rounding mode
2684 The @code{nearbyint} built-in function of C always uses the mode which
2685 corresponds to the C data type @code{double} and the @code{nearbyintf}
2686 built-in function uses the mode which corresponds to the C data
2689 @cindex @code{ffs@var{m}2} instruction pattern
2690 @item @samp{ffs@var{m}2}
2691 Store into operand 0 one plus the index of the least significant 1-bit
2692 of operand 1. If operand 1 is zero, store zero. @var{m} is the mode
2693 of operand 0; operand 1's mode is specified by the instruction
2694 pattern, and the compiler will convert the operand to that mode before
2695 generating the instruction.
2697 The @code{ffs} built-in function of C always uses the mode which
2698 corresponds to the C data type @code{int}.
2700 @cindex @code{clz@var{m}2} instruction pattern
2701 @item @samp{clz@var{m}2}
2702 Store into operand 0 the number of leading 0-bits in @var{x}, starting
2703 at the most significant bit position. If @var{x} is 0, the result is
2704 undefined. @var{m} is the mode of operand 0; operand 1's mode is
2705 specified by the instruction pattern, and the compiler will convert the
2706 operand to that mode before generating the instruction.
2708 @cindex @code{ctz@var{m}2} instruction pattern
2709 @item @samp{ctz@var{m}2}
2710 Store into operand 0 the number of trailing 0-bits in @var{x}, starting
2711 at the least significant bit position. If @var{x} is 0, the result is
2712 undefined. @var{m} is the mode of operand 0; operand 1's mode is
2713 specified by the instruction pattern, and the compiler will convert the
2714 operand to that mode before generating the instruction.
2716 @cindex @code{popcount@var{m}2} instruction pattern
2717 @item @samp{popcount@var{m}2}
2718 Store into operand 0 the number of 1-bits in @var{x}. @var{m} is the
2719 mode of operand 0; operand 1's mode is specified by the instruction
2720 pattern, and the compiler will convert the operand to that mode before
2721 generating the instruction.
2723 @cindex @code{parity@var{m}2} instruction pattern
2724 @item @samp{parity@var{m}2}
2725 Store into operand 0 the parity of @var{x}, i.@:e. the number of 1-bits
2726 in @var{x} modulo 2. @var{m} is the mode of operand 0; operand 1's mode
2727 is specified by the instruction pattern, and the compiler will convert
2728 the operand to that mode before generating the instruction.
2730 @cindex @code{one_cmpl@var{m}2} instruction pattern
2731 @item @samp{one_cmpl@var{m}2}
2732 Store the bitwise-complement of operand 1 into operand 0.
2734 @cindex @code{cmp@var{m}} instruction pattern
2735 @item @samp{cmp@var{m}}
2736 Compare operand 0 and operand 1, and set the condition codes.
2737 The RTL pattern should look like this:
2740 (set (cc0) (compare (match_operand:@var{m} 0 @dots{})
2741 (match_operand:@var{m} 1 @dots{})))
2744 @cindex @code{tst@var{m}} instruction pattern
2745 @item @samp{tst@var{m}}
2746 Compare operand 0 against zero, and set the condition codes.
2747 The RTL pattern should look like this:
2750 (set (cc0) (match_operand:@var{m} 0 @dots{}))
2753 @samp{tst@var{m}} patterns should not be defined for machines that do
2754 not use @code{(cc0)}. Doing so would confuse the optimizer since it
2755 would no longer be clear which @code{set} operations were comparisons.
2756 The @samp{cmp@var{m}} patterns should be used instead.
2758 @cindex @code{movstr@var{m}} instruction pattern
2759 @item @samp{movstr@var{m}}
2760 Block move instruction. The addresses of the destination and source
2761 strings are the first two operands, and both are in mode @code{Pmode}.
2763 The number of bytes to move is the third operand, in mode @var{m}.
2764 Usually, you specify @code{word_mode} for @var{m}. However, if you can
2765 generate better code knowing the range of valid lengths is smaller than
2766 those representable in a full word, you should provide a pattern with a
2767 mode corresponding to the range of values you can handle efficiently
2768 (e.g., @code{QImode} for values in the range 0--127; note we avoid numbers
2769 that appear negative) and also a pattern with @code{word_mode}.
2771 The fourth operand is the known shared alignment of the source and
2772 destination, in the form of a @code{const_int} rtx. Thus, if the
2773 compiler knows that both source and destination are word-aligned,
2774 it may provide the value 4 for this operand.
2776 Descriptions of multiple @code{movstr@var{m}} patterns can only be
2777 beneficial if the patterns for smaller modes have fewer restrictions
2778 on their first, second and fourth operands. Note that the mode @var{m}
2779 in @code{movstr@var{m}} does not impose any restriction on the mode of
2780 individually moved data units in the block.
2782 These patterns need not give special consideration to the possibility
2783 that the source and destination strings might overlap.
2785 @cindex @code{clrstr@var{m}} instruction pattern
2786 @item @samp{clrstr@var{m}}
2787 Block clear instruction. The addresses of the destination string is the
2788 first operand, in mode @code{Pmode}. The number of bytes to clear is
2789 the second operand, in mode @var{m}. See @samp{movstr@var{m}} for
2790 a discussion of the choice of mode.
2792 The third operand is the known alignment of the destination, in the form
2793 of a @code{const_int} rtx. Thus, if the compiler knows that the
2794 destination is word-aligned, it may provide the value 4 for this
2797 The use for multiple @code{clrstr@var{m}} is as for @code{movstr@var{m}}.
2799 @cindex @code{cmpstr@var{m}} instruction pattern
2800 @item @samp{cmpstr@var{m}}
2801 String compare instruction, with five operands. Operand 0 is the output;
2802 it has mode @var{m}. The remaining four operands are like the operands
2803 of @samp{movstr@var{m}}. The two memory blocks specified are compared
2804 byte by byte in lexicographic order starting at the beginning of each
2805 string. The instruction is not allowed to prefetch more than one byte
2806 at a time since either string may end in the first byte and reading past
2807 that may access an invalid page or segment and cause a fault. The
2808 effect of the instruction is to store a value in operand 0 whose sign
2809 indicates the result of the comparison.
2811 @cindex @code{cmpmem@var{m}} instruction pattern
2812 @item @samp{cmpmem@var{m}}
2813 Block compare instruction, with five operands like the operands
2814 of @samp{cmpstr@var{m}}. The two memory blocks specified are compared
2815 byte by byte in lexicographic order starting at the beginning of each
2816 block. Unlike @samp{cmpstr@var{m}} the instruction can prefetch
2817 any bytes in the two memory blocks. The effect of the instruction is
2818 to store a value in operand 0 whose sign indicates the result of the
2821 @cindex @code{strlen@var{m}} instruction pattern
2822 @item @samp{strlen@var{m}}
2823 Compute the length of a string, with three operands.
2824 Operand 0 is the result (of mode @var{m}), operand 1 is
2825 a @code{mem} referring to the first character of the string,
2826 operand 2 is the character to search for (normally zero),
2827 and operand 3 is a constant describing the known alignment
2828 of the beginning of the string.
2830 @cindex @code{float@var{mn}2} instruction pattern
2831 @item @samp{float@var{m}@var{n}2}
2832 Convert signed integer operand 1 (valid for fixed point mode @var{m}) to
2833 floating point mode @var{n} and store in operand 0 (which has mode
2836 @cindex @code{floatuns@var{mn}2} instruction pattern
2837 @item @samp{floatuns@var{m}@var{n}2}
2838 Convert unsigned integer operand 1 (valid for fixed point mode @var{m})
2839 to floating point mode @var{n} and store in operand 0 (which has mode
2842 @cindex @code{fix@var{mn}2} instruction pattern
2843 @item @samp{fix@var{m}@var{n}2}
2844 Convert operand 1 (valid for floating point mode @var{m}) to fixed
2845 point mode @var{n} as a signed number and store in operand 0 (which
2846 has mode @var{n}). This instruction's result is defined only when
2847 the value of operand 1 is an integer.
2849 If the machine description defines this pattern, it also needs to
2850 define the @code{ftrunc} pattern.
2852 @cindex @code{fixuns@var{mn}2} instruction pattern
2853 @item @samp{fixuns@var{m}@var{n}2}
2854 Convert operand 1 (valid for floating point mode @var{m}) to fixed
2855 point mode @var{n} as an unsigned number and store in operand 0 (which
2856 has mode @var{n}). This instruction's result is defined only when the
2857 value of operand 1 is an integer.
2859 @cindex @code{ftrunc@var{m}2} instruction pattern
2860 @item @samp{ftrunc@var{m}2}
2861 Convert operand 1 (valid for floating point mode @var{m}) to an
2862 integer value, still represented in floating point mode @var{m}, and
2863 store it in operand 0 (valid for floating point mode @var{m}).
2865 @cindex @code{fix_trunc@var{mn}2} instruction pattern
2866 @item @samp{fix_trunc@var{m}@var{n}2}
2867 Like @samp{fix@var{m}@var{n}2} but works for any floating point value
2868 of mode @var{m} by converting the value to an integer.
2870 @cindex @code{fixuns_trunc@var{mn}2} instruction pattern
2871 @item @samp{fixuns_trunc@var{m}@var{n}2}
2872 Like @samp{fixuns@var{m}@var{n}2} but works for any floating point
2873 value of mode @var{m} by converting the value to an integer.
2875 @cindex @code{trunc@var{mn}2} instruction pattern
2876 @item @samp{trunc@var{m}@var{n}2}
2877 Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and
2878 store in operand 0 (which has mode @var{n}). Both modes must be fixed
2879 point or both floating point.
2881 @cindex @code{extend@var{mn}2} instruction pattern
2882 @item @samp{extend@var{m}@var{n}2}
2883 Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
2884 store in operand 0 (which has mode @var{n}). Both modes must be fixed
2885 point or both floating point.
2887 @cindex @code{zero_extend@var{mn}2} instruction pattern
2888 @item @samp{zero_extend@var{m}@var{n}2}
2889 Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
2890 store in operand 0 (which has mode @var{n}). Both modes must be fixed
2893 @cindex @code{extv} instruction pattern
2895 Extract a bit-field from operand 1 (a register or memory operand), where
2896 operand 2 specifies the width in bits and operand 3 the starting bit,
2897 and store it in operand 0. Operand 0 must have mode @code{word_mode}.
2898 Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often
2899 @code{word_mode} is allowed only for registers. Operands 2 and 3 must
2900 be valid for @code{word_mode}.
2902 The RTL generation pass generates this instruction only with constants
2903 for operands 2 and 3.
2905 The bit-field value is sign-extended to a full word integer
2906 before it is stored in operand 0.
2908 @cindex @code{extzv} instruction pattern
2910 Like @samp{extv} except that the bit-field value is zero-extended.
2912 @cindex @code{insv} instruction pattern
2914 Store operand 3 (which must be valid for @code{word_mode}) into a
2915 bit-field in operand 0, where operand 1 specifies the width in bits and
2916 operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or
2917 @code{word_mode}; often @code{word_mode} is allowed only for registers.
2918 Operands 1 and 2 must be valid for @code{word_mode}.
2920 The RTL generation pass generates this instruction only with constants
2921 for operands 1 and 2.
2923 @cindex @code{mov@var{mode}cc} instruction pattern
2924 @item @samp{mov@var{mode}cc}
2925 Conditionally move operand 2 or operand 3 into operand 0 according to the
2926 comparison in operand 1. If the comparison is true, operand 2 is moved
2927 into operand 0, otherwise operand 3 is moved.
2929 The mode of the operands being compared need not be the same as the operands
2930 being moved. Some machines, sparc64 for example, have instructions that
2931 conditionally move an integer value based on the floating point condition
2932 codes and vice versa.
2934 If the machine does not have conditional move instructions, do not
2935 define these patterns.
2937 @cindex @code{add@var{mode}cc} instruction pattern
2938 @item @samp{add@var{mode}cc}
2939 Similar to @samp{mov@var{mode}cc} but for conditional addition. Conditionally
2940 move operand 2 or (operands 2 + operand 3) into operand 0 according to the
2941 comparison in operand 1. If the comparison is true, operand 2 is moved into
2942 operand 0, otherwise (operand 2 + operand 3) is moved.
2944 @cindex @code{s@var{cond}} instruction pattern
2945 @item @samp{s@var{cond}}
2946 Store zero or nonzero in the operand according to the condition codes.
2947 Value stored is nonzero iff the condition @var{cond} is true.
2948 @var{cond} is the name of a comparison operation expression code, such
2949 as @code{eq}, @code{lt} or @code{leu}.
2951 You specify the mode that the operand must have when you write the
2952 @code{match_operand} expression. The compiler automatically sees
2953 which mode you have used and supplies an operand of that mode.
2955 The value stored for a true condition must have 1 as its low bit, or
2956 else must be negative. Otherwise the instruction is not suitable and
2957 you should omit it from the machine description. You describe to the
2958 compiler exactly which value is stored by defining the macro
2959 @code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be
2960 found that can be used for all the @samp{s@var{cond}} patterns, you
2961 should omit those operations from the machine description.
2963 These operations may fail, but should do so only in relatively
2964 uncommon cases; if they would fail for common cases involving
2965 integer comparisons, it is best to omit these patterns.
2967 If these operations are omitted, the compiler will usually generate code
2968 that copies the constant one to the target and branches around an
2969 assignment of zero to the target. If this code is more efficient than
2970 the potential instructions used for the @samp{s@var{cond}} pattern
2971 followed by those required to convert the result into a 1 or a zero in
2972 @code{SImode}, you should omit the @samp{s@var{cond}} operations from
2973 the machine description.
2975 @cindex @code{b@var{cond}} instruction pattern
2976 @item @samp{b@var{cond}}
2977 Conditional branch instruction. Operand 0 is a @code{label_ref} that
2978 refers to the label to jump to. Jump if the condition codes meet
2979 condition @var{cond}.
2981 Some machines do not follow the model assumed here where a comparison
2982 instruction is followed by a conditional branch instruction. In that
2983 case, the @samp{cmp@var{m}} (and @samp{tst@var{m}}) patterns should
2984 simply store the operands away and generate all the required insns in a
2985 @code{define_expand} (@pxref{Expander Definitions}) for the conditional
2986 branch operations. All calls to expand @samp{b@var{cond}} patterns are
2987 immediately preceded by calls to expand either a @samp{cmp@var{m}}
2988 pattern or a @samp{tst@var{m}} pattern.
2990 Machines that use a pseudo register for the condition code value, or
2991 where the mode used for the comparison depends on the condition being
2992 tested, should also use the above mechanism. @xref{Jump Patterns}.
2994 The above discussion also applies to the @samp{mov@var{mode}cc} and
2995 @samp{s@var{cond}} patterns.
2997 @cindex @code{cbranch@var{mode}4} instruction pattern
2998 @item @samp{cbranch@var{mode}4}
2999 Conditional branch instruction combined with a compare instruction.
3000 Operand 0 is a comparison operator. Operand 1 and operand 2 are the
3001 first and second operands of the comparison, respectively. Operand 3
3002 is a @code{label_ref} that refers to the label to jump to.
3004 @cindex @code{jump} instruction pattern
3006 A jump inside a function; an unconditional branch. Operand 0 is the
3007 @code{label_ref} of the label to jump to. This pattern name is mandatory
3010 @cindex @code{call} instruction pattern
3012 Subroutine call instruction returning no value. Operand 0 is the
3013 function to call; operand 1 is the number of bytes of arguments pushed
3014 as a @code{const_int}; operand 2 is the number of registers used as
3017 On most machines, operand 2 is not actually stored into the RTL
3018 pattern. It is supplied for the sake of some RISC machines which need
3019 to put this information into the assembler code; they can put it in
3020 the RTL instead of operand 1.
3022 Operand 0 should be a @code{mem} RTX whose address is the address of the
3023 function. Note, however, that this address can be a @code{symbol_ref}
3024 expression even if it would not be a legitimate memory address on the
3025 target machine. If it is also not a valid argument for a call
3026 instruction, the pattern for this operation should be a
3027 @code{define_expand} (@pxref{Expander Definitions}) that places the
3028 address into a register and uses that register in the call instruction.
3030 @cindex @code{call_value} instruction pattern
3031 @item @samp{call_value}
3032 Subroutine call instruction returning a value. Operand 0 is the hard
3033 register in which the value is returned. There are three more
3034 operands, the same as the three operands of the @samp{call}
3035 instruction (but with numbers increased by one).
3037 Subroutines that return @code{BLKmode} objects use the @samp{call}
3040 @cindex @code{call_pop} instruction pattern
3041 @cindex @code{call_value_pop} instruction pattern
3042 @item @samp{call_pop}, @samp{call_value_pop}
3043 Similar to @samp{call} and @samp{call_value}, except used if defined and
3044 if @code{RETURN_POPS_ARGS} is nonzero. They should emit a @code{parallel}
3045 that contains both the function call and a @code{set} to indicate the
3046 adjustment made to the frame pointer.
3048 For machines where @code{RETURN_POPS_ARGS} can be nonzero, the use of these
3049 patterns increases the number of functions for which the frame pointer
3050 can be eliminated, if desired.
3052 @cindex @code{untyped_call} instruction pattern
3053 @item @samp{untyped_call}
3054 Subroutine call instruction returning a value of any type. Operand 0 is
3055 the function to call; operand 1 is a memory location where the result of
3056 calling the function is to be stored; operand 2 is a @code{parallel}
3057 expression where each element is a @code{set} expression that indicates
3058 the saving of a function return value into the result block.
3060 This instruction pattern should be defined to support
3061 @code{__builtin_apply} on machines where special instructions are needed
3062 to call a subroutine with arbitrary arguments or to save the value
3063 returned. This instruction pattern is required on machines that have
3064 multiple registers that can hold a return value
3065 (i.e.@: @code{FUNCTION_VALUE_REGNO_P} is true for more than one register).
3067 @cindex @code{return} instruction pattern
3069 Subroutine return instruction. This instruction pattern name should be
3070 defined only if a single instruction can do all the work of returning
3073 Like the @samp{mov@var{m}} patterns, this pattern is also used after the
3074 RTL generation phase. In this case it is to support machines where
3075 multiple instructions are usually needed to return from a function, but
3076 some class of functions only requires one instruction to implement a
3077 return. Normally, the applicable functions are those which do not need
3078 to save any registers or allocate stack space.
3080 @findex reload_completed
3081 @findex leaf_function_p
3082 For such machines, the condition specified in this pattern should only
3083 be true when @code{reload_completed} is nonzero and the function's
3084 epilogue would only be a single instruction. For machines with register
3085 windows, the routine @code{leaf_function_p} may be used to determine if
3086 a register window push is required.
3088 Machines that have conditional return instructions should define patterns
3094 (if_then_else (match_operator
3095 0 "comparison_operator"
3096 [(cc0) (const_int 0)])
3103 where @var{condition} would normally be the same condition specified on the
3104 named @samp{return} pattern.
3106 @cindex @code{untyped_return} instruction pattern
3107 @item @samp{untyped_return}
3108 Untyped subroutine return instruction. This instruction pattern should
3109 be defined to support @code{__builtin_return} on machines where special
3110 instructions are needed to return a value of any type.
3112 Operand 0 is a memory location where the result of calling a function
3113 with @code{__builtin_apply} is stored; operand 1 is a @code{parallel}
3114 expression where each element is a @code{set} expression that indicates
3115 the restoring of a function return value from the result block.
3117 @cindex @code{nop} instruction pattern
3119 No-op instruction. This instruction pattern name should always be defined
3120 to output a no-op in assembler code. @code{(const_int 0)} will do as an
3123 @cindex @code{indirect_jump} instruction pattern
3124 @item @samp{indirect_jump}
3125 An instruction to jump to an address which is operand zero.
3126 This pattern name is mandatory on all machines.
3128 @cindex @code{casesi} instruction pattern
3130 Instruction to jump through a dispatch table, including bounds checking.
3131 This instruction takes five operands:
3135 The index to dispatch on, which has mode @code{SImode}.
3138 The lower bound for indices in the table, an integer constant.
3141 The total range of indices in the table---the largest index
3142 minus the smallest one (both inclusive).
3145 A label that precedes the table itself.
3148 A label to jump to if the index has a value outside the bounds.
3149 (If the machine-description macro @code{CASE_DROPS_THROUGH} is defined,
3150 then an out-of-bounds index drops through to the code following
3151 the jump table instead of jumping to this label. In that case,
3152 this label is not actually used by the @samp{casesi} instruction,
3153 but it is always provided as an operand.)
3156 The table is a @code{addr_vec} or @code{addr_diff_vec} inside of a
3157 @code{jump_insn}. The number of elements in the table is one plus the
3158 difference between the upper bound and the lower bound.
3160 @cindex @code{tablejump} instruction pattern
3161 @item @samp{tablejump}
3162 Instruction to jump to a variable address. This is a low-level
3163 capability which can be used to implement a dispatch table when there
3164 is no @samp{casesi} pattern.
3166 This pattern requires two operands: the address or offset, and a label
3167 which should immediately precede the jump table. If the macro
3168 @code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first
3169 operand is an offset which counts from the address of the table; otherwise,
3170 it is an absolute address to jump to. In either case, the first operand has
3173 The @samp{tablejump} insn is always the last insn before the jump
3174 table it uses. Its assembler code normally has no need to use the
3175 second operand, but you should incorporate it in the RTL pattern so
3176 that the jump optimizer will not delete the table as unreachable code.
3179 @cindex @code{decrement_and_branch_until_zero} instruction pattern
3180 @item @samp{decrement_and_branch_until_zero}
3181 Conditional branch instruction that decrements a register and
3182 jumps if the register is nonzero. Operand 0 is the register to
3183 decrement and test; operand 1 is the label to jump to if the
3184 register is nonzero. @xref{Looping Patterns}.
3186 This optional instruction pattern is only used by the combiner,
3187 typically for loops reversed by the loop optimizer when strength
3188 reduction is enabled.
3190 @cindex @code{doloop_end} instruction pattern
3191 @item @samp{doloop_end}
3192 Conditional branch instruction that decrements a register and jumps if
3193 the register is nonzero. This instruction takes five operands: Operand
3194 0 is the register to decrement and test; operand 1 is the number of loop
3195 iterations as a @code{const_int} or @code{const0_rtx} if this cannot be
3196 determined until run-time; operand 2 is the actual or estimated maximum
3197 number of iterations as a @code{const_int}; operand 3 is the number of
3198 enclosed loops as a @code{const_int} (an innermost loop has a value of
3199 1); operand 4 is the label to jump to if the register is nonzero.
3200 @xref{Looping Patterns}.
3202 This optional instruction pattern should be defined for machines with
3203 low-overhead looping instructions as the loop optimizer will try to
3204 modify suitable loops to utilize it. If nested low-overhead looping is
3205 not supported, use a @code{define_expand} (@pxref{Expander Definitions})
3206 and make the pattern fail if operand 3 is not @code{const1_rtx}.
3207 Similarly, if the actual or estimated maximum number of iterations is
3208 too large for this instruction, make it fail.
3210 @cindex @code{doloop_begin} instruction pattern
3211 @item @samp{doloop_begin}
3212 Companion instruction to @code{doloop_end} required for machines that
3213 need to perform some initialization, such as loading special registers
3214 used by a low-overhead looping instruction. If initialization insns do
3215 not always need to be emitted, use a @code{define_expand}
3216 (@pxref{Expander Definitions}) and make it fail.
3219 @cindex @code{canonicalize_funcptr_for_compare} instruction pattern
3220 @item @samp{canonicalize_funcptr_for_compare}
3221 Canonicalize the function pointer in operand 1 and store the result
3224 Operand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1
3225 may be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc
3226 and also has mode @code{Pmode}.
3228 Canonicalization of a function pointer usually involves computing
3229 the address of the function which would be called if the function
3230 pointer were used in an indirect call.
3232 Only define this pattern if function pointers on the target machine
3233 can have different values but still call the same function when
3234 used in an indirect call.
3236 @cindex @code{save_stack_block} instruction pattern
3237 @cindex @code{save_stack_function} instruction pattern
3238 @cindex @code{save_stack_nonlocal} instruction pattern
3239 @cindex @code{restore_stack_block} instruction pattern
3240 @cindex @code{restore_stack_function} instruction pattern
3241 @cindex @code{restore_stack_nonlocal} instruction pattern
3242 @item @samp{save_stack_block}
3243 @itemx @samp{save_stack_function}
3244 @itemx @samp{save_stack_nonlocal}
3245 @itemx @samp{restore_stack_block}
3246 @itemx @samp{restore_stack_function}
3247 @itemx @samp{restore_stack_nonlocal}
3248 Most machines save and restore the stack pointer by copying it to or
3249 from an object of mode @code{Pmode}. Do not define these patterns on
3252 Some machines require special handling for stack pointer saves and
3253 restores. On those machines, define the patterns corresponding to the
3254 non-standard cases by using a @code{define_expand} (@pxref{Expander
3255 Definitions}) that produces the required insns. The three types of
3256 saves and restores are:
3260 @samp{save_stack_block} saves the stack pointer at the start of a block
3261 that allocates a variable-sized object, and @samp{restore_stack_block}
3262 restores the stack pointer when the block is exited.
3265 @samp{save_stack_function} and @samp{restore_stack_function} do a
3266 similar job for the outermost block of a function and are used when the
3267 function allocates variable-sized objects or calls @code{alloca}. Only
3268 the epilogue uses the restored stack pointer, allowing a simpler save or
3269 restore sequence on some machines.
3272 @samp{save_stack_nonlocal} is used in functions that contain labels
3273 branched to by nested functions. It saves the stack pointer in such a
3274 way that the inner function can use @samp{restore_stack_nonlocal} to
3275 restore the stack pointer. The compiler generates code to restore the
3276 frame and argument pointer registers, but some machines require saving
3277 and restoring additional data such as register window information or
3278 stack backchains. Place insns in these patterns to save and restore any
3282 When saving the stack pointer, operand 0 is the save area and operand 1
3283 is the stack pointer. The mode used to allocate the save area defaults
3284 to @code{Pmode} but you can override that choice by defining the
3285 @code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must
3286 specify an integral mode, or @code{VOIDmode} if no save area is needed
3287 for a particular type of save (either because no save is needed or
3288 because a machine-specific save area can be used). Operand 0 is the
3289 stack pointer and operand 1 is the save area for restore operations. If
3290 @samp{save_stack_block} is defined, operand 0 must not be
3291 @code{VOIDmode} since these saves can be arbitrarily nested.
3293 A save area is a @code{mem} that is at a constant offset from
3294 @code{virtual_stack_vars_rtx} when the stack pointer is saved for use by
3295 nonlocal gotos and a @code{reg} in the other two cases.
3297 @cindex @code{allocate_stack} instruction pattern
3298 @item @samp{allocate_stack}
3299 Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from
3300 the stack pointer to create space for dynamically allocated data.
3302 Store the resultant pointer to this space into operand 0. If you
3303 are allocating space from the main stack, do this by emitting a
3304 move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0.
3305 If you are allocating the space elsewhere, generate code to copy the
3306 location of the space to operand 0. In the latter case, you must
3307 ensure this space gets freed when the corresponding space on the main
3310 Do not define this pattern if all that must be done is the subtraction.
3311 Some machines require other operations such as stack probes or
3312 maintaining the back chain. Define this pattern to emit those
3313 operations in addition to updating the stack pointer.
3315 @cindex @code{check_stack} instruction pattern
3316 @item @samp{check_stack}
3317 If stack checking cannot be done on your system by probing the stack with
3318 a load or store instruction (@pxref{Stack Checking}), define this pattern
3319 to perform the needed check and signaling an error if the stack
3320 has overflowed. The single operand is the location in the stack furthest
3321 from the current stack pointer that you need to validate. Normally,
3322 on machines where this pattern is needed, you would obtain the stack
3323 limit from a global or thread-specific variable or register.
3325 @cindex @code{nonlocal_goto} instruction pattern
3326 @item @samp{nonlocal_goto}
3327 Emit code to generate a non-local goto, e.g., a jump from one function
3328 to a label in an outer function. This pattern has four arguments,
3329 each representing a value to be used in the jump. The first
3330 argument is to be loaded into the frame pointer, the second is
3331 the address to branch to (code to dispatch to the actual label),
3332 the third is the address of a location where the stack is saved,
3333 and the last is the address of the label, to be placed in the
3334 location for the incoming static chain.
3336 On most machines you need not define this pattern, since GCC will
3337 already generate the correct code, which is to load the frame pointer
3338 and static chain, restore the stack (using the
3339 @samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly
3340 to the dispatcher. You need only define this pattern if this code will
3341 not work on your machine.
3343 @cindex @code{nonlocal_goto_receiver} instruction pattern
3344 @item @samp{nonlocal_goto_receiver}
3345 This pattern, if defined, contains code needed at the target of a
3346 nonlocal goto after the code already generated by GCC@. You will not
3347 normally need to define this pattern. A typical reason why you might
3348 need this pattern is if some value, such as a pointer to a global table,
3349 must be restored when the frame pointer is restored. Note that a nonlocal
3350 goto only occurs within a unit-of-translation, so a global table pointer
3351 that is shared by all functions of a given module need not be restored.
3352 There are no arguments.
3354 @cindex @code{exception_receiver} instruction pattern
3355 @item @samp{exception_receiver}
3356 This pattern, if defined, contains code needed at the site of an
3357 exception handler that isn't needed at the site of a nonlocal goto. You
3358 will not normally need to define this pattern. A typical reason why you
3359 might need this pattern is if some value, such as a pointer to a global
3360 table, must be restored after control flow is branched to the handler of
3361 an exception. There are no arguments.
3363 @cindex @code{builtin_setjmp_setup} instruction pattern
3364 @item @samp{builtin_setjmp_setup}
3365 This pattern, if defined, contains additional code needed to initialize
3366 the @code{jmp_buf}. You will not normally need to define this pattern.
3367 A typical reason why you might need this pattern is if some value, such
3368 as a pointer to a global table, must be restored. Though it is
3369 preferred that the pointer value be recalculated if possible (given the
3370 address of a label for instance). The single argument is a pointer to
3371 the @code{jmp_buf}. Note that the buffer is five words long and that
3372 the first three are normally used by the generic mechanism.
3374 @cindex @code{builtin_setjmp_receiver} instruction pattern
3375 @item @samp{builtin_setjmp_receiver}
3376 This pattern, if defined, contains code needed at the site of an
3377 built-in setjmp that isn't needed at the site of a nonlocal goto. You
3378 will not normally need to define this pattern. A typical reason why you
3379 might need this pattern is if some value, such as a pointer to a global
3380 table, must be restored. It takes one argument, which is the label
3381 to which builtin_longjmp transfered control; this pattern may be emitted
3382 at a small offset from that label.
3384 @cindex @code{builtin_longjmp} instruction pattern
3385 @item @samp{builtin_longjmp}
3386 This pattern, if defined, performs the entire action of the longjmp.
3387 You will not normally need to define this pattern unless you also define
3388 @code{builtin_setjmp_setup}. The single argument is a pointer to the
3391 @cindex @code{eh_return} instruction pattern
3392 @item @samp{eh_return}
3393 This pattern, if defined, affects the way @code{__builtin_eh_return},
3394 and thence the call frame exception handling library routines, are
3395 built. It is intended to handle non-trivial actions needed along
3396 the abnormal return path.
3398 The address of the exception handler to which the function should return
3399 is passed as operand to this pattern. It will normally need to copied by
3400 the pattern to some special register or memory location.
3401 If the pattern needs to determine the location of the target call
3402 frame in order to do so, it may use @code{EH_RETURN_STACKADJ_RTX},
3403 if defined; it will have already been assigned.
3405 If this pattern is not defined, the default action will be to simply
3406 copy the return address to @code{EH_RETURN_HANDLER_RTX}. Either
3407 that macro or this pattern needs to be defined if call frame exception
3408 handling is to be used.
3410 @cindex @code{prologue} instruction pattern
3411 @anchor{prologue instruction pattern}
3412 @item @samp{prologue}
3413 This pattern, if defined, emits RTL for entry to a function. The function
3414 entry is responsible for setting up the stack frame, initializing the frame
3415 pointer register, saving callee saved registers, etc.
3417 Using a prologue pattern is generally preferred over defining
3418 @code{TARGET_ASM_FUNCTION_PROLOGUE} to emit assembly code for the prologue.
3420 The @code{prologue} pattern is particularly useful for targets which perform
3421 instruction scheduling.
3423 @cindex @code{epilogue} instruction pattern
3424 @anchor{epilogue instruction pattern}
3425 @item @samp{epilogue}
3426 This pattern emits RTL for exit from a function. The function
3427 exit is responsible for deallocating the stack frame, restoring callee saved
3428 registers and emitting the return instruction.
3430 Using an epilogue pattern is generally preferred over defining
3431 @code{TARGET_ASM_FUNCTION_EPILOGUE} to emit assembly code for the epilogue.
3433 The @code{epilogue} pattern is particularly useful for targets which perform
3434 instruction scheduling or which have delay slots for their return instruction.
3436 @cindex @code{sibcall_epilogue} instruction pattern
3437 @item @samp{sibcall_epilogue}
3438 This pattern, if defined, emits RTL for exit from a function without the final
3439 branch back to the calling function. This pattern will be emitted before any
3440 sibling call (aka tail call) sites.
3442 The @code{sibcall_epilogue} pattern must not clobber any arguments used for
3443 parameter passing or any stack slots for arguments passed to the current
3446 @cindex @code{trap} instruction pattern
3448 This pattern, if defined, signals an error, typically by causing some
3449 kind of signal to be raised. Among other places, it is used by the Java
3450 front end to signal `invalid array index' exceptions.
3452 @cindex @code{conditional_trap} instruction pattern
3453 @item @samp{conditional_trap}
3454 Conditional trap instruction. Operand 0 is a piece of RTL which
3455 performs a comparison. Operand 1 is the trap code, an integer.
3457 A typical @code{conditional_trap} pattern looks like
3460 (define_insn "conditional_trap"
3461 [(trap_if (match_operator 0 "trap_operator"
3462 [(cc0) (const_int 0)])
3463 (match_operand 1 "const_int_operand" "i"))]
3468 @cindex @code{prefetch} instruction pattern
3469 @item @samp{prefetch}
3471 This pattern, if defined, emits code for a non-faulting data prefetch
3472 instruction. Operand 0 is the address of the memory to prefetch. Operand 1
3473 is a constant 1 if the prefetch is preparing for a write to the memory
3474 address, or a constant 0 otherwise. Operand 2 is the expected degree of
3475 temporal locality of the data and is a value between 0 and 3, inclusive; 0
3476 means that the data has no temporal locality, so it need not be left in the
3477 cache after the access; 3 means that the data has a high degree of temporal
3478 locality and should be left in all levels of cache possible; 1 and 2 mean,
3479 respectively, a low or moderate degree of temporal locality.
3481 Targets that do not support write prefetches or locality hints can ignore
3482 the values of operands 1 and 2.
3486 @node Pattern Ordering
3487 @section When the Order of Patterns Matters
3488 @cindex Pattern Ordering
3489 @cindex Ordering of Patterns
3491 Sometimes an insn can match more than one instruction pattern. Then the
3492 pattern that appears first in the machine description is the one used.
3493 Therefore, more specific patterns (patterns that will match fewer things)
3494 and faster instructions (those that will produce better code when they
3495 do match) should usually go first in the description.
3497 In some cases the effect of ordering the patterns can be used to hide
3498 a pattern when it is not valid. For example, the 68000 has an
3499 instruction for converting a fullword to floating point and another
3500 for converting a byte to floating point. An instruction converting
3501 an integer to floating point could match either one. We put the
3502 pattern to convert the fullword first to make sure that one will
3503 be used rather than the other. (Otherwise a large integer might
3504 be generated as a single-byte immediate quantity, which would not work.)
3505 Instead of using this pattern ordering it would be possible to make the
3506 pattern for convert-a-byte smart enough to deal properly with any
3509 @node Dependent Patterns
3510 @section Interdependence of Patterns
3511 @cindex Dependent Patterns
3512 @cindex Interdependence of Patterns
3514 Every machine description must have a named pattern for each of the
3515 conditional branch names @samp{b@var{cond}}. The recognition template
3516 must always have the form
3520 (if_then_else (@var{cond} (cc0) (const_int 0))
3521 (label_ref (match_operand 0 "" ""))
3526 In addition, every machine description must have an anonymous pattern
3527 for each of the possible reverse-conditional branches. Their templates
3532 (if_then_else (@var{cond} (cc0) (const_int 0))
3534 (label_ref (match_operand 0 "" ""))))
3538 They are necessary because jump optimization can turn direct-conditional
3539 branches into reverse-conditional branches.
3541 It is often convenient to use the @code{match_operator} construct to
3542 reduce the number of patterns that must be specified for branches. For
3548 (if_then_else (match_operator 0 "comparison_operator"
3549 [(cc0) (const_int 0)])
3551 (label_ref (match_operand 1 "" ""))))]
3556 In some cases machines support instructions identical except for the
3557 machine mode of one or more operands. For example, there may be
3558 ``sign-extend halfword'' and ``sign-extend byte'' instructions whose
3562 (set (match_operand:SI 0 @dots{})
3563 (extend:SI (match_operand:HI 1 @dots{})))
3565 (set (match_operand:SI 0 @dots{})
3566 (extend:SI (match_operand:QI 1 @dots{})))
3570 Constant integers do not specify a machine mode, so an instruction to
3571 extend a constant value could match either pattern. The pattern it
3572 actually will match is the one that appears first in the file. For correct
3573 results, this must be the one for the widest possible mode (@code{HImode},
3574 here). If the pattern matches the @code{QImode} instruction, the results
3575 will be incorrect if the constant value does not actually fit that mode.
3577 Such instructions to extend constants are rarely generated because they are
3578 optimized away, but they do occasionally happen in nonoptimized
3581 If a constraint in a pattern allows a constant, the reload pass may
3582 replace a register with a constant permitted by the constraint in some
3583 cases. Similarly for memory references. Because of this substitution,
3584 you should not provide separate patterns for increment and decrement
3585 instructions. Instead, they should be generated from the same pattern
3586 that supports register-register add insns by examining the operands and
3587 generating the appropriate machine instruction.
3590 @section Defining Jump Instruction Patterns
3591 @cindex jump instruction patterns
3592 @cindex defining jump instruction patterns
3594 For most machines, GCC assumes that the machine has a condition code.
3595 A comparison insn sets the condition code, recording the results of both
3596 signed and unsigned comparison of the given operands. A separate branch
3597 insn tests the condition code and branches or not according its value.
3598 The branch insns come in distinct signed and unsigned flavors. Many
3599 common machines, such as the VAX, the 68000 and the 32000, work this
3602 Some machines have distinct signed and unsigned compare instructions, and
3603 only one set of conditional branch instructions. The easiest way to handle
3604 these machines is to treat them just like the others until the final stage
3605 where assembly code is written. At this time, when outputting code for the
3606 compare instruction, peek ahead at the following branch using
3607 @code{next_cc0_user (insn)}. (The variable @code{insn} refers to the insn
3608 being output, in the output-writing code in an instruction pattern.) If
3609 the RTL says that is an unsigned branch, output an unsigned compare;
3610 otherwise output a signed compare. When the branch itself is output, you
3611 can treat signed and unsigned branches identically.
3613 The reason you can do this is that GCC always generates a pair of
3614 consecutive RTL insns, possibly separated by @code{note} insns, one to
3615 set the condition code and one to test it, and keeps the pair inviolate
3618 To go with this technique, you must define the machine-description macro
3619 @code{NOTICE_UPDATE_CC} to do @code{CC_STATUS_INIT}; in other words, no
3620 compare instruction is superfluous.
3622 Some machines have compare-and-branch instructions and no condition code.
3623 A similar technique works for them. When it is time to ``output'' a
3624 compare instruction, record its operands in two static variables. When
3625 outputting the branch-on-condition-code instruction that follows, actually
3626 output a compare-and-branch instruction that uses the remembered operands.
3628 It also works to define patterns for compare-and-branch instructions.
3629 In optimizing compilation, the pair of compare and branch instructions
3630 will be combined according to these patterns. But this does not happen
3631 if optimization is not requested. So you must use one of the solutions
3632 above in addition to any special patterns you define.
3634 In many RISC machines, most instructions do not affect the condition
3635 code and there may not even be a separate condition code register. On
3636 these machines, the restriction that the definition and use of the
3637 condition code be adjacent insns is not necessary and can prevent
3638 important optimizations. For example, on the IBM RS/6000, there is a
3639 delay for taken branches unless the condition code register is set three
3640 instructions earlier than the conditional branch. The instruction
3641 scheduler cannot perform this optimization if it is not permitted to
3642 separate the definition and use of the condition code register.
3644 On these machines, do not use @code{(cc0)}, but instead use a register
3645 to represent the condition code. If there is a specific condition code
3646 register in the machine, use a hard register. If the condition code or
3647 comparison result can be placed in any general register, or if there are
3648 multiple condition registers, use a pseudo register.
3650 @findex prev_cc0_setter
3651 @findex next_cc0_user
3652 On some machines, the type of branch instruction generated may depend on
3653 the way the condition code was produced; for example, on the 68k and
3654 SPARC, setting the condition code directly from an add or subtract
3655 instruction does not clear the overflow bit the way that a test
3656 instruction does, so a different branch instruction must be used for
3657 some conditional branches. For machines that use @code{(cc0)}, the set
3658 and use of the condition code must be adjacent (separated only by
3659 @code{note} insns) allowing flags in @code{cc_status} to be used.
3660 (@xref{Condition Code}.) Also, the comparison and branch insns can be
3661 located from each other by using the functions @code{prev_cc0_setter}
3662 and @code{next_cc0_user}.
3664 However, this is not true on machines that do not use @code{(cc0)}. On
3665 those machines, no assumptions can be made about the adjacency of the
3666 compare and branch insns and the above methods cannot be used. Instead,
3667 we use the machine mode of the condition code register to record
3668 different formats of the condition code register.
3670 Registers used to store the condition code value should have a mode that
3671 is in class @code{MODE_CC}. Normally, it will be @code{CCmode}. If
3672 additional modes are required (as for the add example mentioned above in
3673 the SPARC), define the macro @code{EXTRA_CC_MODES} to list the
3674 additional modes required (@pxref{Condition Code}). Also define
3675 @code{SELECT_CC_MODE} to choose a mode given an operand of a compare.
3677 If it is known during RTL generation that a different mode will be
3678 required (for example, if the machine has separate compare instructions
3679 for signed and unsigned quantities, like most IBM processors), they can
3680 be specified at that time.
3682 If the cases that require different modes would be made by instruction
3683 combination, the macro @code{SELECT_CC_MODE} determines which machine
3684 mode should be used for the comparison result. The patterns should be
3685 written using that mode. To support the case of the add on the SPARC
3686 discussed above, we have the pattern
3690 [(set (reg:CC_NOOV 0)
3692 (plus:SI (match_operand:SI 0 "register_operand" "%r")
3693 (match_operand:SI 1 "arith_operand" "rI"))
3699 The @code{SELECT_CC_MODE} macro on the SPARC returns @code{CC_NOOVmode}
3700 for comparisons whose argument is a @code{plus}.
3702 @node Looping Patterns
3703 @section Defining Looping Instruction Patterns
3704 @cindex looping instruction patterns
3705 @cindex defining looping instruction patterns
3707 Some machines have special jump instructions that can be utilized to
3708 make loops more efficient. A common example is the 68000 @samp{dbra}
3709 instruction which performs a decrement of a register and a branch if the
3710 result was greater than zero. Other machines, in particular digital
3711 signal processors (DSPs), have special block repeat instructions to
3712 provide low-overhead loop support. For example, the TI TMS320C3x/C4x
3713 DSPs have a block repeat instruction that loads special registers to
3714 mark the top and end of a loop and to count the number of loop
3715 iterations. This avoids the need for fetching and executing a
3716 @samp{dbra}-like instruction and avoids pipeline stalls associated with
3719 GCC has three special named patterns to support low overhead looping.
3720 They are @samp{decrement_and_branch_until_zero}, @samp{doloop_begin},
3721 and @samp{doloop_end}. The first pattern,
3722 @samp{decrement_and_branch_until_zero}, is not emitted during RTL
3723 generation but may be emitted during the instruction combination phase.
3724 This requires the assistance of the loop optimizer, using information
3725 collected during strength reduction, to reverse a loop to count down to
3726 zero. Some targets also require the loop optimizer to add a
3727 @code{REG_NONNEG} note to indicate that the iteration count is always
3728 positive. This is needed if the target performs a signed loop
3729 termination test. For example, the 68000 uses a pattern similar to the
3730 following for its @code{dbra} instruction:
3734 (define_insn "decrement_and_branch_until_zero"
3737 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
3740 (label_ref (match_operand 1 "" ""))
3743 (plus:SI (match_dup 0)
3745 "find_reg_note (insn, REG_NONNEG, 0)"
3750 Note that since the insn is both a jump insn and has an output, it must
3751 deal with its own reloads, hence the `m' constraints. Also note that
3752 since this insn is generated by the instruction combination phase
3753 combining two sequential insns together into an implicit parallel insn,
3754 the iteration counter needs to be biased by the same amount as the
3755 decrement operation, in this case @minus{}1. Note that the following similar
3756 pattern will not be matched by the combiner.
3760 (define_insn "decrement_and_branch_until_zero"
3763 (ge (match_operand:SI 0 "general_operand" "+d*am")
3765 (label_ref (match_operand 1 "" ""))
3768 (plus:SI (match_dup 0)
3770 "find_reg_note (insn, REG_NONNEG, 0)"
3775 The other two special looping patterns, @samp{doloop_begin} and
3776 @samp{doloop_end}, are emitted by the loop optimizer for certain
3777 well-behaved loops with a finite number of loop iterations using
3778 information collected during strength reduction.
3780 The @samp{doloop_end} pattern describes the actual looping instruction
3781 (or the implicit looping operation) and the @samp{doloop_begin} pattern
3782 is an optional companion pattern that can be used for initialization
3783 needed for some low-overhead looping instructions.
3785 Note that some machines require the actual looping instruction to be
3786 emitted at the top of the loop (e.g., the TMS320C3x/C4x DSPs). Emitting
3787 the true RTL for a looping instruction at the top of the loop can cause
3788 problems with flow analysis. So instead, a dummy @code{doloop} insn is
3789 emitted at the end of the loop. The machine dependent reorg pass checks
3790 for the presence of this @code{doloop} insn and then searches back to
3791 the top of the loop, where it inserts the true looping insn (provided
3792 there are no instructions in the loop which would cause problems). Any
3793 additional labels can be emitted at this point. In addition, if the
3794 desired special iteration counter register was not allocated, this
3795 machine dependent reorg pass could emit a traditional compare and jump
3798 The essential difference between the
3799 @samp{decrement_and_branch_until_zero} and the @samp{doloop_end}
3800 patterns is that the loop optimizer allocates an additional pseudo
3801 register for the latter as an iteration counter. This pseudo register
3802 cannot be used within the loop (i.e., general induction variables cannot
3803 be derived from it), however, in many cases the loop induction variable
3804 may become redundant and removed by the flow pass.
3807 @node Insn Canonicalizations
3808 @section Canonicalization of Instructions
3809 @cindex canonicalization of instructions
3810 @cindex insn canonicalization
3812 There are often cases where multiple RTL expressions could represent an
3813 operation performed by a single machine instruction. This situation is
3814 most commonly encountered with logical, branch, and multiply-accumulate
3815 instructions. In such cases, the compiler attempts to convert these
3816 multiple RTL expressions into a single canonical form to reduce the
3817 number of insn patterns required.
3819 In addition to algebraic simplifications, following canonicalizations
3824 For commutative and comparison operators, a constant is always made the
3825 second operand. If a machine only supports a constant as the second
3826 operand, only patterns that match a constant in the second operand need
3830 For associative operators, a sequence of operators will always chain
3831 to the left; for instance, only the left operand of an integer @code{plus}
3832 can itself be a @code{plus}. @code{and}, @code{ior}, @code{xor},
3833 @code{plus}, @code{mult}, @code{smin}, @code{smax}, @code{umin}, and
3834 @code{umax} are associative when applied to integers, and sometimes to
3838 @cindex @code{neg}, canonicalization of
3839 @cindex @code{not}, canonicalization of
3840 @cindex @code{mult}, canonicalization of
3841 @cindex @code{plus}, canonicalization of
3842 @cindex @code{minus}, canonicalization of
3843 For these operators, if only one operand is a @code{neg}, @code{not},
3844 @code{mult}, @code{plus}, or @code{minus} expression, it will be the
3848 In combinations of @code{neg}, @code{mult}, @code{plus}, and
3849 @code{minus}, the @code{neg} operations (if any) will be moved inside
3850 the operations as far as possible. For instance,
3851 @code{(neg (mult A B))} is canonicalized as @code{(mult (neg A) B)}, but
3852 @code{(plus (mult (neg A) B) C)} is canonicalized as
3853 @code{(minus A (mult B C))}.
3855 @cindex @code{compare}, canonicalization of
3857 For the @code{compare} operator, a constant is always the second operand
3858 on machines where @code{cc0} is used (@pxref{Jump Patterns}). On other
3859 machines, there are rare cases where the compiler might want to construct
3860 a @code{compare} with a constant as the first operand. However, these
3861 cases are not common enough for it to be worthwhile to provide a pattern
3862 matching a constant as the first operand unless the machine actually has
3863 such an instruction.
3865 An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or
3866 @code{minus} is made the first operand under the same conditions as
3870 @code{(minus @var{x} (const_int @var{n}))} is converted to
3871 @code{(plus @var{x} (const_int @var{-n}))}.
3874 Within address computations (i.e., inside @code{mem}), a left shift is
3875 converted into the appropriate multiplication by a power of two.
3877 @cindex @code{ior}, canonicalization of
3878 @cindex @code{and}, canonicalization of
3879 @cindex De Morgan's law
3881 De`Morgan's Law is used to move bitwise negation inside a bitwise
3882 logical-and or logical-or operation. If this results in only one
3883 operand being a @code{not} expression, it will be the first one.
3885 A machine that has an instruction that performs a bitwise logical-and of one
3886 operand with the bitwise negation of the other should specify the pattern
3887 for that instruction as
3891 [(set (match_operand:@var{m} 0 @dots{})
3892 (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
3893 (match_operand:@var{m} 2 @dots{})))]
3899 Similarly, a pattern for a ``NAND'' instruction should be written
3903 [(set (match_operand:@var{m} 0 @dots{})
3904 (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
3905 (not:@var{m} (match_operand:@var{m} 2 @dots{}))))]
3910 In both cases, it is not necessary to include patterns for the many
3911 logically equivalent RTL expressions.
3913 @cindex @code{xor}, canonicalization of
3915 The only possible RTL expressions involving both bitwise exclusive-or
3916 and bitwise negation are @code{(xor:@var{m} @var{x} @var{y})}
3917 and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}.
3920 The sum of three items, one of which is a constant, will only appear in
3924 (plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant})
3928 On machines that do not use @code{cc0},
3929 @code{(compare @var{x} (const_int 0))} will be converted to
3932 @cindex @code{zero_extract}, canonicalization of
3933 @cindex @code{sign_extract}, canonicalization of
3935 Equality comparisons of a group of bits (usually a single bit) with zero
3936 will be written using @code{zero_extract} rather than the equivalent
3937 @code{and} or @code{sign_extract} operations.
3941 @node Expander Definitions
3942 @section Defining RTL Sequences for Code Generation
3943 @cindex expander definitions
3944 @cindex code generation RTL sequences
3945 @cindex defining RTL sequences for code generation
3947 On some target machines, some standard pattern names for RTL generation
3948 cannot be handled with single insn, but a sequence of RTL insns can
3949 represent them. For these target machines, you can write a
3950 @code{define_expand} to specify how to generate the sequence of RTL@.
3952 @findex define_expand
3953 A @code{define_expand} is an RTL expression that looks almost like a
3954 @code{define_insn}; but, unlike the latter, a @code{define_expand} is used
3955 only for RTL generation and it can produce more than one RTL insn.
3957 A @code{define_expand} RTX has four operands:
3961 The name. Each @code{define_expand} must have a name, since the only
3962 use for it is to refer to it by name.
3965 The RTL template. This is a vector of RTL expressions representing
3966 a sequence of separate instructions. Unlike @code{define_insn}, there
3967 is no implicit surrounding @code{PARALLEL}.
3970 The condition, a string containing a C expression. This expression is
3971 used to express how the availability of this pattern depends on
3972 subclasses of target machine, selected by command-line options when GCC
3973 is run. This is just like the condition of a @code{define_insn} that
3974 has a standard name. Therefore, the condition (if present) may not
3975 depend on the data in the insn being matched, but only the
3976 target-machine-type flags. The compiler needs to test these conditions
3977 during initialization in order to learn exactly which named instructions
3978 are available in a particular run.
3981 The preparation statements, a string containing zero or more C
3982 statements which are to be executed before RTL code is generated from
3985 Usually these statements prepare temporary registers for use as
3986 internal operands in the RTL template, but they can also generate RTL
3987 insns directly by calling routines such as @code{emit_insn}, etc.
3988 Any such insns precede the ones that come from the RTL template.
3991 Every RTL insn emitted by a @code{define_expand} must match some
3992 @code{define_insn} in the machine description. Otherwise, the compiler
3993 will crash when trying to generate code for the insn or trying to optimize
3996 The RTL template, in addition to controlling generation of RTL insns,
3997 also describes the operands that need to be specified when this pattern
3998 is used. In particular, it gives a predicate for each operand.
4000 A true operand, which needs to be specified in order to generate RTL from
4001 the pattern, should be described with a @code{match_operand} in its first
4002 occurrence in the RTL template. This enters information on the operand's
4003 predicate into the tables that record such things. GCC uses the
4004 information to preload the operand into a register if that is required for
4005 valid RTL code. If the operand is referred to more than once, subsequent
4006 references should use @code{match_dup}.
4008 The RTL template may also refer to internal ``operands'' which are
4009 temporary registers or labels used only within the sequence made by the
4010 @code{define_expand}. Internal operands are substituted into the RTL
4011 template with @code{match_dup}, never with @code{match_operand}. The
4012 values of the internal operands are not passed in as arguments by the
4013 compiler when it requests use of this pattern. Instead, they are computed
4014 within the pattern, in the preparation statements. These statements
4015 compute the values and store them into the appropriate elements of
4016 @code{operands} so that @code{match_dup} can find them.
4018 There are two special macros defined for use in the preparation statements:
4019 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
4026 Use the @code{DONE} macro to end RTL generation for the pattern. The
4027 only RTL insns resulting from the pattern on this occasion will be
4028 those already emitted by explicit calls to @code{emit_insn} within the
4029 preparation statements; the RTL template will not be generated.
4033 Make the pattern fail on this occasion. When a pattern fails, it means
4034 that the pattern was not truly available. The calling routines in the
4035 compiler will try other strategies for code generation using other patterns.
4037 Failure is currently supported only for binary (addition, multiplication,
4038 shifting, etc.) and bit-field (@code{extv}, @code{extzv}, and @code{insv})
4042 If the preparation falls through (invokes neither @code{DONE} nor
4043 @code{FAIL}), then the @code{define_expand} acts like a
4044 @code{define_insn} in that the RTL template is used to generate the
4047 The RTL template is not used for matching, only for generating the
4048 initial insn list. If the preparation statement always invokes
4049 @code{DONE} or @code{FAIL}, the RTL template may be reduced to a simple
4050 list of operands, such as this example:
4054 (define_expand "addsi3"
4055 [(match_operand:SI 0 "register_operand" "")
4056 (match_operand:SI 1 "register_operand" "")
4057 (match_operand:SI 2 "register_operand" "")]
4063 handle_add (operands[0], operands[1], operands[2]);
4069 Here is an example, the definition of left-shift for the SPUR chip:
4073 (define_expand "ashlsi3"
4074 [(set (match_operand:SI 0 "register_operand" "")
4078 (match_operand:SI 1 "register_operand" "")
4079 (match_operand:SI 2 "nonmemory_operand" "")))]
4088 if (GET_CODE (operands[2]) != CONST_INT
4089 || (unsigned) INTVAL (operands[2]) > 3)
4096 This example uses @code{define_expand} so that it can generate an RTL insn
4097 for shifting when the shift-count is in the supported range of 0 to 3 but
4098 fail in other cases where machine insns aren't available. When it fails,
4099 the compiler tries another strategy using different patterns (such as, a
4102 If the compiler were able to handle nontrivial condition-strings in
4103 patterns with names, then it would be possible to use a
4104 @code{define_insn} in that case. Here is another case (zero-extension
4105 on the 68000) which makes more use of the power of @code{define_expand}:
4108 (define_expand "zero_extendhisi2"
4109 [(set (match_operand:SI 0 "general_operand" "")
4111 (set (strict_low_part
4115 (match_operand:HI 1 "general_operand" ""))]
4117 "operands[1] = make_safe_from (operands[1], operands[0]);")
4121 @findex make_safe_from
4122 Here two RTL insns are generated, one to clear the entire output operand
4123 and the other to copy the input operand into its low half. This sequence
4124 is incorrect if the input operand refers to [the old value of] the output
4125 operand, so the preparation statement makes sure this isn't so. The
4126 function @code{make_safe_from} copies the @code{operands[1]} into a
4127 temporary register if it refers to @code{operands[0]}. It does this
4128 by emitting another RTL insn.
4130 Finally, a third example shows the use of an internal operand.
4131 Zero-extension on the SPUR chip is done by @code{and}-ing the result
4132 against a halfword mask. But this mask cannot be represented by a
4133 @code{const_int} because the constant value is too large to be legitimate
4134 on this machine. So it must be copied into a register with
4135 @code{force_reg} and then the register used in the @code{and}.
4138 (define_expand "zero_extendhisi2"
4139 [(set (match_operand:SI 0 "register_operand" "")
4141 (match_operand:HI 1 "register_operand" "")
4146 = force_reg (SImode, GEN_INT (65535)); ")
4149 @strong{Note:} If the @code{define_expand} is used to serve a
4150 standard binary or unary arithmetic operation or a bit-field operation,
4151 then the last insn it generates must not be a @code{code_label},
4152 @code{barrier} or @code{note}. It must be an @code{insn},
4153 @code{jump_insn} or @code{call_insn}. If you don't need a real insn
4154 at the end, emit an insn to copy the result of the operation into
4155 itself. Such an insn will generate no code, but it can avoid problems
4158 @node Insn Splitting
4159 @section Defining How to Split Instructions
4160 @cindex insn splitting
4161 @cindex instruction splitting
4162 @cindex splitting instructions
4164 There are two cases where you should specify how to split a pattern
4165 into multiple insns. On machines that have instructions requiring
4166 delay slots (@pxref{Delay Slots}) or that have instructions whose
4167 output is not available for multiple cycles (@pxref{Processor pipeline
4168 description}), the compiler phases that optimize these cases need to
4169 be able to move insns into one-instruction delay slots. However, some
4170 insns may generate more than one machine instruction. These insns
4171 cannot be placed into a delay slot.
4173 Often you can rewrite the single insn as a list of individual insns,
4174 each corresponding to one machine instruction. The disadvantage of
4175 doing so is that it will cause the compilation to be slower and require
4176 more space. If the resulting insns are too complex, it may also
4177 suppress some optimizations. The compiler splits the insn if there is a
4178 reason to believe that it might improve instruction or delay slot
4181 The insn combiner phase also splits putative insns. If three insns are
4182 merged into one insn with a complex expression that cannot be matched by
4183 some @code{define_insn} pattern, the combiner phase attempts to split
4184 the complex pattern into two insns that are recognized. Usually it can
4185 break the complex pattern into two patterns by splitting out some
4186 subexpression. However, in some other cases, such as performing an
4187 addition of a large constant in two insns on a RISC machine, the way to
4188 split the addition into two insns is machine-dependent.
4190 @findex define_split
4191 The @code{define_split} definition tells the compiler how to split a
4192 complex insn into several simpler insns. It looks like this:
4196 [@var{insn-pattern}]
4198 [@var{new-insn-pattern-1}
4199 @var{new-insn-pattern-2}
4201 "@var{preparation-statements}")
4204 @var{insn-pattern} is a pattern that needs to be split and
4205 @var{condition} is the final condition to be tested, as in a
4206 @code{define_insn}. When an insn matching @var{insn-pattern} and
4207 satisfying @var{condition} is found, it is replaced in the insn list
4208 with the insns given by @var{new-insn-pattern-1},
4209 @var{new-insn-pattern-2}, etc.
4211 The @var{preparation-statements} are similar to those statements that
4212 are specified for @code{define_expand} (@pxref{Expander Definitions})
4213 and are executed before the new RTL is generated to prepare for the
4214 generated code or emit some insns whose pattern is not fixed. Unlike
4215 those in @code{define_expand}, however, these statements must not
4216 generate any new pseudo-registers. Once reload has completed, they also
4217 must not allocate any space in the stack frame.
4219 Patterns are matched against @var{insn-pattern} in two different
4220 circumstances. If an insn needs to be split for delay slot scheduling
4221 or insn scheduling, the insn is already known to be valid, which means
4222 that it must have been matched by some @code{define_insn} and, if
4223 @code{reload_completed} is nonzero, is known to satisfy the constraints
4224 of that @code{define_insn}. In that case, the new insn patterns must
4225 also be insns that are matched by some @code{define_insn} and, if
4226 @code{reload_completed} is nonzero, must also satisfy the constraints
4227 of those definitions.
4229 As an example of this usage of @code{define_split}, consider the following
4230 example from @file{a29k.md}, which splits a @code{sign_extend} from
4231 @code{HImode} to @code{SImode} into a pair of shift insns:
4235 [(set (match_operand:SI 0 "gen_reg_operand" "")
4236 (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
4239 (ashift:SI (match_dup 1)
4242 (ashiftrt:SI (match_dup 0)
4245 @{ operands[1] = gen_lowpart (SImode, operands[1]); @}")
4248 When the combiner phase tries to split an insn pattern, it is always the
4249 case that the pattern is @emph{not} matched by any @code{define_insn}.
4250 The combiner pass first tries to split a single @code{set} expression
4251 and then the same @code{set} expression inside a @code{parallel}, but
4252 followed by a @code{clobber} of a pseudo-reg to use as a scratch
4253 register. In these cases, the combiner expects exactly two new insn
4254 patterns to be generated. It will verify that these patterns match some
4255 @code{define_insn} definitions, so you need not do this test in the
4256 @code{define_split} (of course, there is no point in writing a
4257 @code{define_split} that will never produce insns that match).
4259 Here is an example of this use of @code{define_split}, taken from
4264 [(set (match_operand:SI 0 "gen_reg_operand" "")
4265 (plus:SI (match_operand:SI 1 "gen_reg_operand" "")
4266 (match_operand:SI 2 "non_add_cint_operand" "")))]
4268 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
4269 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
4272 int low = INTVAL (operands[2]) & 0xffff;
4273 int high = (unsigned) INTVAL (operands[2]) >> 16;
4276 high++, low |= 0xffff0000;
4278 operands[3] = GEN_INT (high << 16);
4279 operands[4] = GEN_INT (low);
4283 Here the predicate @code{non_add_cint_operand} matches any
4284 @code{const_int} that is @emph{not} a valid operand of a single add
4285 insn. The add with the smaller displacement is written so that it
4286 can be substituted into the address of a subsequent operation.
4288 An example that uses a scratch register, from the same file, generates
4289 an equality comparison of a register and a large constant:
4293 [(set (match_operand:CC 0 "cc_reg_operand" "")
4294 (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
4295 (match_operand:SI 2 "non_short_cint_operand" "")))
4296 (clobber (match_operand:SI 3 "gen_reg_operand" ""))]
4297 "find_single_use (operands[0], insn, 0)
4298 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
4299 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
4300 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
4301 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
4304 /* Get the constant we are comparing against, C, and see what it
4305 looks like sign-extended to 16 bits. Then see what constant
4306 could be XOR'ed with C to get the sign-extended value. */
4308 int c = INTVAL (operands[2]);
4309 int sextc = (c << 16) >> 16;
4310 int xorv = c ^ sextc;
4312 operands[4] = GEN_INT (xorv);
4313 operands[5] = GEN_INT (sextc);
4317 To avoid confusion, don't write a single @code{define_split} that
4318 accepts some insns that match some @code{define_insn} as well as some
4319 insns that don't. Instead, write two separate @code{define_split}
4320 definitions, one for the insns that are valid and one for the insns that
4323 The splitter is allowed to split jump instructions into sequence of
4324 jumps or create new jumps in while splitting non-jump instructions. As
4325 the central flowgraph and branch prediction information needs to be updated,
4326 several restriction apply.
4328 Splitting of jump instruction into sequence that over by another jump
4329 instruction is always valid, as compiler expect identical behavior of new
4330 jump. When new sequence contains multiple jump instructions or new labels,
4331 more assistance is needed. Splitter is required to create only unconditional
4332 jumps, or simple conditional jump instructions. Additionally it must attach a
4333 @code{REG_BR_PROB} note to each conditional jump. A global variable
4334 @code{split_branch_probability} hold the probability of original branch in case
4335 it was an simple conditional jump, @minus{}1 otherwise. To simplify
4336 recomputing of edge frequencies, new sequence is required to have only
4337 forward jumps to the newly created labels.
4339 @findex define_insn_and_split
4340 For the common case where the pattern of a define_split exactly matches the
4341 pattern of a define_insn, use @code{define_insn_and_split}. It looks like
4345 (define_insn_and_split
4346 [@var{insn-pattern}]
4348 "@var{output-template}"
4349 "@var{split-condition}"
4350 [@var{new-insn-pattern-1}
4351 @var{new-insn-pattern-2}
4353 "@var{preparation-statements}"
4354 [@var{insn-attributes}])
4358 @var{insn-pattern}, @var{condition}, @var{output-template}, and
4359 @var{insn-attributes} are used as in @code{define_insn}. The
4360 @var{new-insn-pattern} vector and the @var{preparation-statements} are used as
4361 in a @code{define_split}. The @var{split-condition} is also used as in
4362 @code{define_split}, with the additional behavior that if the condition starts
4363 with @samp{&&}, the condition used for the split will be the constructed as a
4364 logical ``and'' of the split condition with the insn condition. For example,
4368 (define_insn_and_split "zero_extendhisi2_and"
4369 [(set (match_operand:SI 0 "register_operand" "=r")
4370 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
4371 (clobber (reg:CC 17))]
4372 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
4374 "&& reload_completed"
4375 [(parallel [(set (match_dup 0)
4376 (and:SI (match_dup 0) (const_int 65535)))
4377 (clobber (reg:CC 17))])]
4379 [(set_attr "type" "alu1")])
4383 In this case, the actual split condition will be
4384 @samp{TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed}.
4386 The @code{define_insn_and_split} construction provides exactly the same
4387 functionality as two separate @code{define_insn} and @code{define_split}
4388 patterns. It exists for compactness, and as a maintenance tool to prevent
4389 having to ensure the two patterns' templates match.
4391 @node Including Patterns
4392 @section Including Patterns in Machine Descriptions.
4393 @cindex insn includes
4396 The @code{include} pattern tells the compiler tools where to
4397 look for patterns that are in files other than in the file
4398 @file{.md}. This is used only at build time and there is no preprocessing allowed.
4412 (include "filestuff")
4416 Where @var{pathname} is a string that specifies the location of the file,
4417 specifies the include file to be in @file{gcc/config/target/filestuff}. The
4418 directory @file{gcc/config/target} is regarded as the default directory.
4421 Machine descriptions may be split up into smaller more manageable subsections
4422 and placed into subdirectories.
4428 (include "BOGUS/filestuff")
4432 the include file is specified to be in @file{gcc/config/@var{target}/BOGUS/filestuff}.
4434 Specifying an absolute path for the include file such as;
4437 (include "/u2/BOGUS/filestuff")
4440 is permitted but is not encouraged.
4442 @subsection RTL Generation Tool Options for Directory Search
4443 @cindex directory options .md
4444 @cindex options, directory search
4445 @cindex search options
4447 The @option{-I@var{dir}} option specifies directories to search for machine descriptions.
4452 genrecog -I/p1/abc/proc1 -I/p2/abcd/pro2 target.md
4457 Add the directory @var{dir} to the head of the list of directories to be
4458 searched for header files. This can be used to override a system machine definition
4459 file, substituting your own version, since these directories are
4460 searched before the default machine description file directories. If you use more than
4461 one @option{-I} option, the directories are scanned in left-to-right
4462 order; the standard default directory come after.
4465 @node Peephole Definitions
4466 @section Machine-Specific Peephole Optimizers
4467 @cindex peephole optimizer definitions
4468 @cindex defining peephole optimizers
4470 In addition to instruction patterns the @file{md} file may contain
4471 definitions of machine-specific peephole optimizations.
4473 The combiner does not notice certain peephole optimizations when the data
4474 flow in the program does not suggest that it should try them. For example,
4475 sometimes two consecutive insns related in purpose can be combined even
4476 though the second one does not appear to use a register computed in the
4477 first one. A machine-specific peephole optimizer can detect such
4480 There are two forms of peephole definitions that may be used. The
4481 original @code{define_peephole} is run at assembly output time to
4482 match insns and substitute assembly text. Use of @code{define_peephole}
4485 A newer @code{define_peephole2} matches insns and substitutes new
4486 insns. The @code{peephole2} pass is run after register allocation
4487 but before scheduling, which may result in much better code for
4488 targets that do scheduling.
4491 * define_peephole:: RTL to Text Peephole Optimizers
4492 * define_peephole2:: RTL to RTL Peephole Optimizers
4495 @node define_peephole
4496 @subsection RTL to Text Peephole Optimizers
4497 @findex define_peephole
4500 A definition looks like this:
4504 [@var{insn-pattern-1}
4505 @var{insn-pattern-2}
4509 "@var{optional-insn-attributes}")
4513 The last string operand may be omitted if you are not using any
4514 machine-specific information in this machine description. If present,
4515 it must obey the same rules as in a @code{define_insn}.
4517 In this skeleton, @var{insn-pattern-1} and so on are patterns to match
4518 consecutive insns. The optimization applies to a sequence of insns when
4519 @var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches
4520 the next, and so on.
4522 Each of the insns matched by a peephole must also match a
4523 @code{define_insn}. Peepholes are checked only at the last stage just
4524 before code generation, and only optionally. Therefore, any insn which
4525 would match a peephole but no @code{define_insn} will cause a crash in code
4526 generation in an unoptimized compilation, or at various optimization
4529 The operands of the insns are matched with @code{match_operands},
4530 @code{match_operator}, and @code{match_dup}, as usual. What is not
4531 usual is that the operand numbers apply to all the insn patterns in the
4532 definition. So, you can check for identical operands in two insns by
4533 using @code{match_operand} in one insn and @code{match_dup} in the
4536 The operand constraints used in @code{match_operand} patterns do not have
4537 any direct effect on the applicability of the peephole, but they will
4538 be validated afterward, so make sure your constraints are general enough
4539 to apply whenever the peephole matches. If the peephole matches
4540 but the constraints are not satisfied, the compiler will crash.
4542 It is safe to omit constraints in all the operands of the peephole; or
4543 you can write constraints which serve as a double-check on the criteria
4546 Once a sequence of insns matches the patterns, the @var{condition} is
4547 checked. This is a C expression which makes the final decision whether to
4548 perform the optimization (we do so if the expression is nonzero). If
4549 @var{condition} is omitted (in other words, the string is empty) then the
4550 optimization is applied to every sequence of insns that matches the
4553 The defined peephole optimizations are applied after register allocation
4554 is complete. Therefore, the peephole definition can check which
4555 operands have ended up in which kinds of registers, just by looking at
4558 @findex prev_active_insn
4559 The way to refer to the operands in @var{condition} is to write
4560 @code{operands[@var{i}]} for operand number @var{i} (as matched by
4561 @code{(match_operand @var{i} @dots{})}). Use the variable @code{insn}
4562 to refer to the last of the insns being matched; use
4563 @code{prev_active_insn} to find the preceding insns.
4565 @findex dead_or_set_p
4566 When optimizing computations with intermediate results, you can use
4567 @var{condition} to match only when the intermediate results are not used
4568 elsewhere. Use the C expression @code{dead_or_set_p (@var{insn},
4569 @var{op})}, where @var{insn} is the insn in which you expect the value
4570 to be used for the last time (from the value of @code{insn}, together
4571 with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate
4572 value (from @code{operands[@var{i}]}).
4574 Applying the optimization means replacing the sequence of insns with one
4575 new insn. The @var{template} controls ultimate output of assembler code
4576 for this combined insn. It works exactly like the template of a
4577 @code{define_insn}. Operand numbers in this template are the same ones
4578 used in matching the original sequence of insns.
4580 The result of a defined peephole optimizer does not need to match any of
4581 the insn patterns in the machine description; it does not even have an
4582 opportunity to match them. The peephole optimizer definition itself serves
4583 as the insn pattern to control how the insn is output.
4585 Defined peephole optimizers are run as assembler code is being output,
4586 so the insns they produce are never combined or rearranged in any way.
4588 Here is an example, taken from the 68000 machine description:
4592 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
4593 (set (match_operand:DF 0 "register_operand" "=f")
4594 (match_operand:DF 1 "register_operand" "ad"))]
4595 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
4598 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4600 output_asm_insn ("move.l %1,(sp)", xoperands);
4601 output_asm_insn ("move.l %1,-(sp)", operands);
4602 return "fmove.d (sp)+,%0";
4604 output_asm_insn ("movel %1,sp@@", xoperands);
4605 output_asm_insn ("movel %1,sp@@-", operands);
4606 return "fmoved sp@@+,%0";
4612 The effect of this optimization is to change
4638 If a peephole matches a sequence including one or more jump insns, you must
4639 take account of the flags such as @code{CC_REVERSED} which specify that the
4640 condition codes are represented in an unusual manner. The compiler
4641 automatically alters any ordinary conditional jumps which occur in such
4642 situations, but the compiler cannot alter jumps which have been replaced by
4643 peephole optimizations. So it is up to you to alter the assembler code
4644 that the peephole produces. Supply C code to write the assembler output,
4645 and in this C code check the condition code status flags and change the
4646 assembler code as appropriate.
4649 @var{insn-pattern-1} and so on look @emph{almost} like the second
4650 operand of @code{define_insn}. There is one important difference: the
4651 second operand of @code{define_insn} consists of one or more RTX's
4652 enclosed in square brackets. Usually, there is only one: then the same
4653 action can be written as an element of a @code{define_peephole}. But
4654 when there are multiple actions in a @code{define_insn}, they are
4655 implicitly enclosed in a @code{parallel}. Then you must explicitly
4656 write the @code{parallel}, and the square brackets within it, in the
4657 @code{define_peephole}. Thus, if an insn pattern looks like this,
4660 (define_insn "divmodsi4"
4661 [(set (match_operand:SI 0 "general_operand" "=d")
4662 (div:SI (match_operand:SI 1 "general_operand" "0")
4663 (match_operand:SI 2 "general_operand" "dmsK")))
4664 (set (match_operand:SI 3 "general_operand" "=d")
4665 (mod:SI (match_dup 1) (match_dup 2)))]
4667 "divsl%.l %2,%3:%0")
4671 then the way to mention this insn in a peephole is as follows:
4677 [(set (match_operand:SI 0 "general_operand" "=d")
4678 (div:SI (match_operand:SI 1 "general_operand" "0")
4679 (match_operand:SI 2 "general_operand" "dmsK")))
4680 (set (match_operand:SI 3 "general_operand" "=d")
4681 (mod:SI (match_dup 1) (match_dup 2)))])
4686 @node define_peephole2
4687 @subsection RTL to RTL Peephole Optimizers
4688 @findex define_peephole2
4690 The @code{define_peephole2} definition tells the compiler how to
4691 substitute one sequence of instructions for another sequence,
4692 what additional scratch registers may be needed and what their
4697 [@var{insn-pattern-1}
4698 @var{insn-pattern-2}
4701 [@var{new-insn-pattern-1}
4702 @var{new-insn-pattern-2}
4704 "@var{preparation-statements}")
4707 The definition is almost identical to @code{define_split}
4708 (@pxref{Insn Splitting}) except that the pattern to match is not a
4709 single instruction, but a sequence of instructions.
4711 It is possible to request additional scratch registers for use in the
4712 output template. If appropriate registers are not free, the pattern
4713 will simply not match.
4715 @findex match_scratch
4717 Scratch registers are requested with a @code{match_scratch} pattern at
4718 the top level of the input pattern. The allocated register (initially) will
4719 be dead at the point requested within the original sequence. If the scratch
4720 is used at more than a single point, a @code{match_dup} pattern at the
4721 top level of the input pattern marks the last position in the input sequence
4722 at which the register must be available.
4724 Here is an example from the IA-32 machine description:
4728 [(match_scratch:SI 2 "r")
4729 (parallel [(set (match_operand:SI 0 "register_operand" "")
4730 (match_operator:SI 3 "arith_or_logical_operator"
4732 (match_operand:SI 1 "memory_operand" "")]))
4733 (clobber (reg:CC 17))])]
4734 "! optimize_size && ! TARGET_READ_MODIFY"
4735 [(set (match_dup 2) (match_dup 1))
4736 (parallel [(set (match_dup 0)
4737 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
4738 (clobber (reg:CC 17))])]
4743 This pattern tries to split a load from its use in the hopes that we'll be
4744 able to schedule around the memory load latency. It allocates a single
4745 @code{SImode} register of class @code{GENERAL_REGS} (@code{"r"}) that needs
4746 to be live only at the point just before the arithmetic.
4748 A real example requiring extended scratch lifetimes is harder to come by,
4749 so here's a silly made-up example:
4753 [(match_scratch:SI 4 "r")
4754 (set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
4755 (set (match_operand:SI 2 "" "") (match_dup 1))
4757 (set (match_operand:SI 3 "" "") (match_dup 1))]
4758 "/* @r{determine 1 does not overlap 0 and 2} */"
4759 [(set (match_dup 4) (match_dup 1))
4760 (set (match_dup 0) (match_dup 4))
4761 (set (match_dup 2) (match_dup 4))]
4762 (set (match_dup 3) (match_dup 4))]
4767 If we had not added the @code{(match_dup 4)} in the middle of the input
4768 sequence, it might have been the case that the register we chose at the
4769 beginning of the sequence is killed by the first or second @code{set}.
4771 @node Insn Attributes
4772 @section Instruction Attributes
4773 @cindex insn attributes
4774 @cindex instruction attributes
4776 In addition to describing the instruction supported by the target machine,
4777 the @file{md} file also defines a group of @dfn{attributes} and a set of
4778 values for each. Every generated insn is assigned a value for each attribute.
4779 One possible attribute would be the effect that the insn has on the machine's
4780 condition code. This attribute can then be used by @code{NOTICE_UPDATE_CC}
4781 to track the condition codes.
4784 * Defining Attributes:: Specifying attributes and their values.
4785 * Expressions:: Valid expressions for attribute values.
4786 * Tagging Insns:: Assigning attribute values to insns.
4787 * Attr Example:: An example of assigning attributes.
4788 * Insn Lengths:: Computing the length of insns.
4789 * Constant Attributes:: Defining attributes that are constant.
4790 * Delay Slots:: Defining delay slots required for a machine.
4791 * Processor pipeline description:: Specifying information for insn scheduling.
4794 @node Defining Attributes
4795 @subsection Defining Attributes and their Values
4796 @cindex defining attributes and their values
4797 @cindex attributes, defining
4800 The @code{define_attr} expression is used to define each attribute required
4801 by the target machine. It looks like:
4804 (define_attr @var{name} @var{list-of-values} @var{default})
4807 @var{name} is a string specifying the name of the attribute being defined.
4809 @var{list-of-values} is either a string that specifies a comma-separated
4810 list of values that can be assigned to the attribute, or a null string to
4811 indicate that the attribute takes numeric values.
4813 @var{default} is an attribute expression that gives the value of this
4814 attribute for insns that match patterns whose definition does not include
4815 an explicit value for this attribute. @xref{Attr Example}, for more
4816 information on the handling of defaults. @xref{Constant Attributes},
4817 for information on attributes that do not depend on any particular insn.
4820 For each defined attribute, a number of definitions are written to the
4821 @file{insn-attr.h} file. For cases where an explicit set of values is
4822 specified for an attribute, the following are defined:
4826 A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}.
4829 An enumeral class is defined for @samp{attr_@var{name}} with
4830 elements of the form @samp{@var{upper-name}_@var{upper-value}} where
4831 the attribute name and value are first converted to uppercase.
4834 A function @samp{get_attr_@var{name}} is defined that is passed an insn and
4835 returns the attribute value for that insn.
4838 For example, if the following is present in the @file{md} file:
4841 (define_attr "type" "branch,fp,load,store,arith" @dots{})
4845 the following lines will be written to the file @file{insn-attr.h}.
4848 #define HAVE_ATTR_type
4849 enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD,
4850 TYPE_STORE, TYPE_ARITH@};
4851 extern enum attr_type get_attr_type ();
4854 If the attribute takes numeric values, no @code{enum} type will be
4855 defined and the function to obtain the attribute's value will return
4859 @subsection Attribute Expressions
4860 @cindex attribute expressions
4862 RTL expressions used to define attributes use the codes described above
4863 plus a few specific to attribute definitions, to be discussed below.
4864 Attribute value expressions must have one of the following forms:
4867 @cindex @code{const_int} and attributes
4868 @item (const_int @var{i})
4869 The integer @var{i} specifies the value of a numeric attribute. @var{i}
4870 must be non-negative.
4872 The value of a numeric attribute can be specified either with a
4873 @code{const_int}, or as an integer represented as a string in
4874 @code{const_string}, @code{eq_attr} (see below), @code{attr},
4875 @code{symbol_ref}, simple arithmetic expressions, and @code{set_attr}
4876 overrides on specific instructions (@pxref{Tagging Insns}).
4878 @cindex @code{const_string} and attributes
4879 @item (const_string @var{value})
4880 The string @var{value} specifies a constant attribute value.
4881 If @var{value} is specified as @samp{"*"}, it means that the default value of
4882 the attribute is to be used for the insn containing this expression.
4883 @samp{"*"} obviously cannot be used in the @var{default} expression
4884 of a @code{define_attr}.
4886 If the attribute whose value is being specified is numeric, @var{value}
4887 must be a string containing a non-negative integer (normally
4888 @code{const_int} would be used in this case). Otherwise, it must
4889 contain one of the valid values for the attribute.
4891 @cindex @code{if_then_else} and attributes
4892 @item (if_then_else @var{test} @var{true-value} @var{false-value})
4893 @var{test} specifies an attribute test, whose format is defined below.
4894 The value of this expression is @var{true-value} if @var{test} is true,
4895 otherwise it is @var{false-value}.
4897 @cindex @code{cond} and attributes
4898 @item (cond [@var{test1} @var{value1} @dots{}] @var{default})
4899 The first operand of this expression is a vector containing an even
4900 number of expressions and consisting of pairs of @var{test} and @var{value}
4901 expressions. The value of the @code{cond} expression is that of the
4902 @var{value} corresponding to the first true @var{test} expression. If
4903 none of the @var{test} expressions are true, the value of the @code{cond}
4904 expression is that of the @var{default} expression.
4907 @var{test} expressions can have one of the following forms:
4910 @cindex @code{const_int} and attribute tests
4911 @item (const_int @var{i})
4912 This test is true if @var{i} is nonzero and false otherwise.
4914 @cindex @code{not} and attributes
4915 @cindex @code{ior} and attributes
4916 @cindex @code{and} and attributes
4917 @item (not @var{test})
4918 @itemx (ior @var{test1} @var{test2})
4919 @itemx (and @var{test1} @var{test2})
4920 These tests are true if the indicated logical function is true.
4922 @cindex @code{match_operand} and attributes
4923 @item (match_operand:@var{m} @var{n} @var{pred} @var{constraints})
4924 This test is true if operand @var{n} of the insn whose attribute value
4925 is being determined has mode @var{m} (this part of the test is ignored
4926 if @var{m} is @code{VOIDmode}) and the function specified by the string
4927 @var{pred} returns a nonzero value when passed operand @var{n} and mode
4928 @var{m} (this part of the test is ignored if @var{pred} is the null
4931 The @var{constraints} operand is ignored and should be the null string.
4933 @cindex @code{le} and attributes
4934 @cindex @code{leu} and attributes
4935 @cindex @code{lt} and attributes
4936 @cindex @code{gt} and attributes
4937 @cindex @code{gtu} and attributes
4938 @cindex @code{ge} and attributes
4939 @cindex @code{geu} and attributes
4940 @cindex @code{ne} and attributes
4941 @cindex @code{eq} and attributes
4942 @cindex @code{plus} and attributes
4943 @cindex @code{minus} and attributes
4944 @cindex @code{mult} and attributes
4945 @cindex @code{div} and attributes
4946 @cindex @code{mod} and attributes
4947 @cindex @code{abs} and attributes
4948 @cindex @code{neg} and attributes
4949 @cindex @code{ashift} and attributes
4950 @cindex @code{lshiftrt} and attributes
4951 @cindex @code{ashiftrt} and attributes
4952 @item (le @var{arith1} @var{arith2})
4953 @itemx (leu @var{arith1} @var{arith2})
4954 @itemx (lt @var{arith1} @var{arith2})
4955 @itemx (ltu @var{arith1} @var{arith2})
4956 @itemx (gt @var{arith1} @var{arith2})
4957 @itemx (gtu @var{arith1} @var{arith2})
4958 @itemx (ge @var{arith1} @var{arith2})
4959 @itemx (geu @var{arith1} @var{arith2})
4960 @itemx (ne @var{arith1} @var{arith2})
4961 @itemx (eq @var{arith1} @var{arith2})
4962 These tests are true if the indicated comparison of the two arithmetic
4963 expressions is true. Arithmetic expressions are formed with
4964 @code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod},
4965 @code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not},
4966 @code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions.
4969 @code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn
4970 Lengths},for additional forms). @code{symbol_ref} is a string
4971 denoting a C expression that yields an @code{int} when evaluated by the
4972 @samp{get_attr_@dots{}} routine. It should normally be a global
4976 @item (eq_attr @var{name} @var{value})
4977 @var{name} is a string specifying the name of an attribute.
4979 @var{value} is a string that is either a valid value for attribute
4980 @var{name}, a comma-separated list of values, or @samp{!} followed by a
4981 value or list. If @var{value} does not begin with a @samp{!}, this
4982 test is true if the value of the @var{name} attribute of the current
4983 insn is in the list specified by @var{value}. If @var{value} begins
4984 with a @samp{!}, this test is true if the attribute's value is
4985 @emph{not} in the specified list.
4990 (eq_attr "type" "load,store")
4997 (ior (eq_attr "type" "load") (eq_attr "type" "store"))
5000 If @var{name} specifies an attribute of @samp{alternative}, it refers to the
5001 value of the compiler variable @code{which_alternative}
5002 (@pxref{Output Statement}) and the values must be small integers. For
5006 (eq_attr "alternative" "2,3")
5013 (ior (eq (symbol_ref "which_alternative") (const_int 2))
5014 (eq (symbol_ref "which_alternative") (const_int 3)))
5017 Note that, for most attributes, an @code{eq_attr} test is simplified in cases
5018 where the value of the attribute being tested is known for all insns matching
5019 a particular pattern. This is by far the most common case.
5022 @item (attr_flag @var{name})
5023 The value of an @code{attr_flag} expression is true if the flag
5024 specified by @var{name} is true for the @code{insn} currently being
5027 @var{name} is a string specifying one of a fixed set of flags to test.
5028 Test the flags @code{forward} and @code{backward} to determine the
5029 direction of a conditional branch. Test the flags @code{very_likely},
5030 @code{likely}, @code{very_unlikely}, and @code{unlikely} to determine
5031 if a conditional branch is expected to be taken.
5033 If the @code{very_likely} flag is true, then the @code{likely} flag is also
5034 true. Likewise for the @code{very_unlikely} and @code{unlikely} flags.
5036 This example describes a conditional branch delay slot which
5037 can be nullified for forward branches that are taken (annul-true) or
5038 for backward branches which are not taken (annul-false).
5041 (define_delay (eq_attr "type" "cbranch")
5042 [(eq_attr "in_branch_delay" "true")
5043 (and (eq_attr "in_branch_delay" "true")
5044 (attr_flag "forward"))
5045 (and (eq_attr "in_branch_delay" "true")
5046 (attr_flag "backward"))])
5049 The @code{forward} and @code{backward} flags are false if the current
5050 @code{insn} being scheduled is not a conditional branch.
5052 The @code{very_likely} and @code{likely} flags are true if the
5053 @code{insn} being scheduled is not a conditional branch.
5054 The @code{very_unlikely} and @code{unlikely} flags are false if the
5055 @code{insn} being scheduled is not a conditional branch.
5057 @code{attr_flag} is only used during delay slot scheduling and has no
5058 meaning to other passes of the compiler.
5061 @item (attr @var{name})
5062 The value of another attribute is returned. This is most useful
5063 for numeric attributes, as @code{eq_attr} and @code{attr_flag}
5064 produce more efficient code for non-numeric attributes.
5068 @subsection Assigning Attribute Values to Insns
5069 @cindex tagging insns
5070 @cindex assigning attribute values to insns
5072 The value assigned to an attribute of an insn is primarily determined by
5073 which pattern is matched by that insn (or which @code{define_peephole}
5074 generated it). Every @code{define_insn} and @code{define_peephole} can
5075 have an optional last argument to specify the values of attributes for
5076 matching insns. The value of any attribute not specified in a particular
5077 insn is set to the default value for that attribute, as specified in its
5078 @code{define_attr}. Extensive use of default values for attributes
5079 permits the specification of the values for only one or two attributes
5080 in the definition of most insn patterns, as seen in the example in the
5083 The optional last argument of @code{define_insn} and
5084 @code{define_peephole} is a vector of expressions, each of which defines
5085 the value for a single attribute. The most general way of assigning an
5086 attribute's value is to use a @code{set} expression whose first operand is an
5087 @code{attr} expression giving the name of the attribute being set. The
5088 second operand of the @code{set} is an attribute expression
5089 (@pxref{Expressions}) giving the value of the attribute.
5091 When the attribute value depends on the @samp{alternative} attribute
5092 (i.e., which is the applicable alternative in the constraint of the
5093 insn), the @code{set_attr_alternative} expression can be used. It
5094 allows the specification of a vector of attribute expressions, one for
5098 When the generality of arbitrary attribute expressions is not required,
5099 the simpler @code{set_attr} expression can be used, which allows
5100 specifying a string giving either a single attribute value or a list
5101 of attribute values, one for each alternative.
5103 The form of each of the above specifications is shown below. In each case,
5104 @var{name} is a string specifying the attribute to be set.
5107 @item (set_attr @var{name} @var{value-string})
5108 @var{value-string} is either a string giving the desired attribute value,
5109 or a string containing a comma-separated list giving the values for
5110 succeeding alternatives. The number of elements must match the number
5111 of alternatives in the constraint of the insn pattern.
5113 Note that it may be useful to specify @samp{*} for some alternative, in
5114 which case the attribute will assume its default value for insns matching
5117 @findex set_attr_alternative
5118 @item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}])
5119 Depending on the alternative of the insn, the value will be one of the
5120 specified values. This is a shorthand for using a @code{cond} with
5121 tests on the @samp{alternative} attribute.
5124 @item (set (attr @var{name}) @var{value})
5125 The first operand of this @code{set} must be the special RTL expression
5126 @code{attr}, whose sole operand is a string giving the name of the
5127 attribute being set. @var{value} is the value of the attribute.
5130 The following shows three different ways of representing the same
5131 attribute value specification:
5134 (set_attr "type" "load,store,arith")
5136 (set_attr_alternative "type"
5137 [(const_string "load") (const_string "store")
5138 (const_string "arith")])
5141 (cond [(eq_attr "alternative" "1") (const_string "load")
5142 (eq_attr "alternative" "2") (const_string "store")]
5143 (const_string "arith")))
5147 @findex define_asm_attributes
5148 The @code{define_asm_attributes} expression provides a mechanism to
5149 specify the attributes assigned to insns produced from an @code{asm}
5150 statement. It has the form:
5153 (define_asm_attributes [@var{attr-sets}])
5157 where @var{attr-sets} is specified the same as for both the
5158 @code{define_insn} and the @code{define_peephole} expressions.
5160 These values will typically be the ``worst case'' attribute values. For
5161 example, they might indicate that the condition code will be clobbered.
5163 A specification for a @code{length} attribute is handled specially. The
5164 way to compute the length of an @code{asm} insn is to multiply the
5165 length specified in the expression @code{define_asm_attributes} by the
5166 number of machine instructions specified in the @code{asm} statement,
5167 determined by counting the number of semicolons and newlines in the
5168 string. Therefore, the value of the @code{length} attribute specified
5169 in a @code{define_asm_attributes} should be the maximum possible length
5170 of a single machine instruction.
5173 @subsection Example of Attribute Specifications
5174 @cindex attribute specifications example
5175 @cindex attribute specifications
5177 The judicious use of defaulting is important in the efficient use of
5178 insn attributes. Typically, insns are divided into @dfn{types} and an
5179 attribute, customarily called @code{type}, is used to represent this
5180 value. This attribute is normally used only to define the default value
5181 for other attributes. An example will clarify this usage.
5183 Assume we have a RISC machine with a condition code and in which only
5184 full-word operations are performed in registers. Let us assume that we
5185 can divide all insns into loads, stores, (integer) arithmetic
5186 operations, floating point operations, and branches.
5188 Here we will concern ourselves with determining the effect of an insn on
5189 the condition code and will limit ourselves to the following possible
5190 effects: The condition code can be set unpredictably (clobbered), not
5191 be changed, be set to agree with the results of the operation, or only
5192 changed if the item previously set into the condition code has been
5195 Here is part of a sample @file{md} file for such a machine:
5198 (define_attr "type" "load,store,arith,fp,branch" (const_string "arith"))
5200 (define_attr "cc" "clobber,unchanged,set,change0"
5201 (cond [(eq_attr "type" "load")
5202 (const_string "change0")
5203 (eq_attr "type" "store,branch")
5204 (const_string "unchanged")
5205 (eq_attr "type" "arith")
5206 (if_then_else (match_operand:SI 0 "" "")
5207 (const_string "set")
5208 (const_string "clobber"))]
5209 (const_string "clobber")))
5212 [(set (match_operand:SI 0 "general_operand" "=r,r,m")
5213 (match_operand:SI 1 "general_operand" "r,m,r"))]
5219 [(set_attr "type" "arith,load,store")])
5222 Note that we assume in the above example that arithmetic operations
5223 performed on quantities smaller than a machine word clobber the condition
5224 code since they will set the condition code to a value corresponding to the
5228 @subsection Computing the Length of an Insn
5229 @cindex insn lengths, computing
5230 @cindex computing the length of an insn
5232 For many machines, multiple types of branch instructions are provided, each
5233 for different length branch displacements. In most cases, the assembler
5234 will choose the correct instruction to use. However, when the assembler
5235 cannot do so, GCC can when a special attribute, the @samp{length}
5236 attribute, is defined. This attribute must be defined to have numeric
5237 values by specifying a null string in its @code{define_attr}.
5239 In the case of the @samp{length} attribute, two additional forms of
5240 arithmetic terms are allowed in test expressions:
5243 @cindex @code{match_dup} and attributes
5244 @item (match_dup @var{n})
5245 This refers to the address of operand @var{n} of the current insn, which
5246 must be a @code{label_ref}.
5248 @cindex @code{pc} and attributes
5250 This refers to the address of the @emph{current} insn. It might have
5251 been more consistent with other usage to make this the address of the
5252 @emph{next} insn but this would be confusing because the length of the
5253 current insn is to be computed.
5256 @cindex @code{addr_vec}, length of
5257 @cindex @code{addr_diff_vec}, length of
5258 For normal insns, the length will be determined by value of the
5259 @samp{length} attribute. In the case of @code{addr_vec} and
5260 @code{addr_diff_vec} insn patterns, the length is computed as
5261 the number of vectors multiplied by the size of each vector.
5263 Lengths are measured in addressable storage units (bytes).
5265 The following macros can be used to refine the length computation:
5268 @findex ADJUST_INSN_LENGTH
5269 @item ADJUST_INSN_LENGTH (@var{insn}, @var{length})
5270 If defined, modifies the length assigned to instruction @var{insn} as a
5271 function of the context in which it is used. @var{length} is an lvalue
5272 that contains the initially computed length of the insn and should be
5273 updated with the correct length of the insn.
5275 This macro will normally not be required. A case in which it is
5276 required is the ROMP@. On this machine, the size of an @code{addr_vec}
5277 insn must be increased by two to compensate for the fact that alignment
5281 @findex get_attr_length
5282 The routine that returns @code{get_attr_length} (the value of the
5283 @code{length} attribute) can be used by the output routine to
5284 determine the form of the branch instruction to be written, as the
5285 example below illustrates.
5287 As an example of the specification of variable-length branches, consider
5288 the IBM 360. If we adopt the convention that a register will be set to
5289 the starting address of a function, we can jump to labels within 4k of
5290 the start using a four-byte instruction. Otherwise, we need a six-byte
5291 sequence to load the address from memory and then branch to it.
5293 On such a machine, a pattern for a branch instruction might be specified
5299 (label_ref (match_operand 0 "" "")))]
5302 return (get_attr_length (insn) == 4
5303 ? "b %l0" : "l r15,=a(%l0); br r15");
5305 [(set (attr "length")
5306 (if_then_else (lt (match_dup 0) (const_int 4096))
5311 @node Constant Attributes
5312 @subsection Constant Attributes
5313 @cindex constant attributes
5315 A special form of @code{define_attr}, where the expression for the
5316 default value is a @code{const} expression, indicates an attribute that
5317 is constant for a given run of the compiler. Constant attributes may be
5318 used to specify which variety of processor is used. For example,
5321 (define_attr "cpu" "m88100,m88110,m88000"
5323 (cond [(symbol_ref "TARGET_88100") (const_string "m88100")
5324 (symbol_ref "TARGET_88110") (const_string "m88110")]
5325 (const_string "m88000"))))
5327 (define_attr "memory" "fast,slow"
5329 (if_then_else (symbol_ref "TARGET_FAST_MEM")
5330 (const_string "fast")
5331 (const_string "slow"))))
5334 The routine generated for constant attributes has no parameters as it
5335 does not depend on any particular insn. RTL expressions used to define
5336 the value of a constant attribute may use the @code{symbol_ref} form,
5337 but may not use either the @code{match_operand} form or @code{eq_attr}
5338 forms involving insn attributes.
5341 @subsection Delay Slot Scheduling
5342 @cindex delay slots, defining
5344 The insn attribute mechanism can be used to specify the requirements for
5345 delay slots, if any, on a target machine. An instruction is said to
5346 require a @dfn{delay slot} if some instructions that are physically
5347 after the instruction are executed as if they were located before it.
5348 Classic examples are branch and call instructions, which often execute
5349 the following instruction before the branch or call is performed.
5351 On some machines, conditional branch instructions can optionally
5352 @dfn{annul} instructions in the delay slot. This means that the
5353 instruction will not be executed for certain branch outcomes. Both
5354 instructions that annul if the branch is true and instructions that
5355 annul if the branch is false are supported.
5357 Delay slot scheduling differs from instruction scheduling in that
5358 determining whether an instruction needs a delay slot is dependent only
5359 on the type of instruction being generated, not on data flow between the
5360 instructions. See the next section for a discussion of data-dependent
5361 instruction scheduling.
5363 @findex define_delay
5364 The requirement of an insn needing one or more delay slots is indicated
5365 via the @code{define_delay} expression. It has the following form:
5368 (define_delay @var{test}
5369 [@var{delay-1} @var{annul-true-1} @var{annul-false-1}
5370 @var{delay-2} @var{annul-true-2} @var{annul-false-2}
5374 @var{test} is an attribute test that indicates whether this
5375 @code{define_delay} applies to a particular insn. If so, the number of
5376 required delay slots is determined by the length of the vector specified
5377 as the second argument. An insn placed in delay slot @var{n} must
5378 satisfy attribute test @var{delay-n}. @var{annul-true-n} is an
5379 attribute test that specifies which insns may be annulled if the branch
5380 is true. Similarly, @var{annul-false-n} specifies which insns in the
5381 delay slot may be annulled if the branch is false. If annulling is not
5382 supported for that delay slot, @code{(nil)} should be coded.
5384 For example, in the common case where branch and call insns require
5385 a single delay slot, which may contain any insn other than a branch or
5386 call, the following would be placed in the @file{md} file:
5389 (define_delay (eq_attr "type" "branch,call")
5390 [(eq_attr "type" "!branch,call") (nil) (nil)])
5393 Multiple @code{define_delay} expressions may be specified. In this
5394 case, each such expression specifies different delay slot requirements
5395 and there must be no insn for which tests in two @code{define_delay}
5396 expressions are both true.
5398 For example, if we have a machine that requires one delay slot for branches
5399 but two for calls, no delay slot can contain a branch or call insn,
5400 and any valid insn in the delay slot for the branch can be annulled if the
5401 branch is true, we might represent this as follows:
5404 (define_delay (eq_attr "type" "branch")
5405 [(eq_attr "type" "!branch,call")
5406 (eq_attr "type" "!branch,call")
5409 (define_delay (eq_attr "type" "call")
5410 [(eq_attr "type" "!branch,call") (nil) (nil)
5411 (eq_attr "type" "!branch,call") (nil) (nil)])
5413 @c the above is *still* too long. --mew 4feb93
5415 @node Processor pipeline description
5416 @subsection Specifying processor pipeline description
5417 @cindex processor pipeline description
5418 @cindex processor functional units
5419 @cindex instruction latency time
5420 @cindex interlock delays
5421 @cindex data dependence delays
5422 @cindex reservation delays
5423 @cindex pipeline hazard recognizer
5424 @cindex automaton based pipeline description
5425 @cindex regular expressions
5426 @cindex deterministic finite state automaton
5427 @cindex automaton based scheduler
5431 To achieve better performance, most modern processors
5432 (super-pipelined, superscalar @acronym{RISC}, and @acronym{VLIW}
5433 processors) have many @dfn{functional units} on which several
5434 instructions can be executed simultaneously. An instruction starts
5435 execution if its issue conditions are satisfied. If not, the
5436 instruction is stalled until its conditions are satisfied. Such
5437 @dfn{interlock (pipeline) delay} causes interruption of the fetching
5438 of successor instructions (or demands nop instructions, e.g. for some
5441 There are two major kinds of interlock delays in modern processors.
5442 The first one is a data dependence delay determining @dfn{instruction
5443 latency time}. The instruction execution is not started until all
5444 source data have been evaluated by prior instructions (there are more
5445 complex cases when the instruction execution starts even when the data
5446 are not available but will be ready in given time after the
5447 instruction execution start). Taking the data dependence delays into
5448 account is simple. The data dependence (true, output, and
5449 anti-dependence) delay between two instructions is given by a
5450 constant. In most cases this approach is adequate. The second kind
5451 of interlock delays is a reservation delay. The reservation delay
5452 means that two instructions under execution will be in need of shared
5453 processors resources, i.e. buses, internal registers, and/or
5454 functional units, which are reserved for some time. Taking this kind
5455 of delay into account is complex especially for modern @acronym{RISC}
5458 The task of exploiting more processor parallelism is solved by an
5459 instruction scheduler. For a better solution to this problem, the
5460 instruction scheduler has to have an adequate description of the
5461 processor parallelism (or @dfn{pipeline description}). Currently GCC
5462 provides two alternative ways to describe processor parallelism,
5463 both described below. The first method is outlined in the next section;
5464 it was once the only method provided by GCC, and thus is used in a number
5465 of exiting ports. The second, and preferred method, specifies functional
5466 unit reservations for groups of instructions with the aid of @dfn{regular
5467 expressions}. This is called the @dfn{automaton based description}.
5469 The GCC instruction scheduler uses a @dfn{pipeline hazard recognizer} to
5470 figure out the possibility of the instruction issue by the processor
5471 on a given simulated processor cycle. The pipeline hazard recognizer is
5472 automatically generated from the processor pipeline description. The
5473 pipeline hazard recognizer generated from the automaton based
5474 description is more sophisticated and based on a deterministic finite
5475 state automaton (@acronym{DFA}) and therefore faster than one
5476 generated from the old description. Furthermore, its speed is not dependent
5477 on processor complexity. The instruction issue is possible if there is
5478 a transition from one automaton state to another one.
5480 You can use either model to describe processor pipeline
5481 characteristics or even mix them. You could use the old description
5482 for some processor submodels and the @acronym{DFA}-based one for other
5483 processor submodels.
5485 In general, using the automaton based description is preferred. Its
5486 model is richer and makes it possible to more accurately describe
5487 pipeline characteristics of processors, which results in improved
5488 code quality (although sometimes only marginally). It will also be
5489 used as an infrastructure to implement sophisticated and practical
5490 instruction scheduling which will try many instruction sequences to
5491 choose the best one.
5495 * Old pipeline description:: Specifying information for insn scheduling.
5496 * Automaton pipeline description:: Describing insn pipeline characteristics.
5497 * Comparison of the two descriptions:: Drawbacks of the old pipeline description
5500 @node Old pipeline description
5501 @subsubsection Specifying Function Units
5502 @cindex old pipeline description
5503 @cindex function units, for scheduling
5505 On most @acronym{RISC} machines, there are instructions whose results
5506 are not available for a specific number of cycles. Common cases are
5507 instructions that load data from memory. On many machines, a pipeline
5508 stall will result if the data is referenced too soon after the load
5511 In addition, many newer microprocessors have multiple function units, usually
5512 one for integer and one for floating point, and often will incur pipeline
5513 stalls when a result that is needed is not yet ready.
5515 The descriptions in this section allow the specification of how much
5516 time must elapse between the execution of an instruction and the time
5517 when its result is used. It also allows specification of when the
5518 execution of an instruction will delay execution of similar instructions
5519 due to function unit conflicts.
5521 For the purposes of the specifications in this section, a machine is
5522 divided into @dfn{function units}, each of which execute a specific
5523 class of instructions in first-in-first-out order. Function units
5524 that accept one instruction each cycle and allow a result to be used
5525 in the succeeding instruction (usually via forwarding) need not be
5526 specified. Classic @acronym{RISC} microprocessors will normally have
5527 a single function unit, which we can call @samp{memory}. The newer
5528 ``superscalar'' processors will often have function units for floating
5529 point operations, usually at least a floating point adder and
5532 @findex define_function_unit
5533 Each usage of a function units by a class of insns is specified with a
5534 @code{define_function_unit} expression, which looks like this:
5537 (define_function_unit @var{name} @var{multiplicity} @var{simultaneity}
5538 @var{test} @var{ready-delay} @var{issue-delay}
5539 [@var{conflict-list}])
5542 @var{name} is a string giving the name of the function unit.
5544 @var{multiplicity} is an integer specifying the number of identical
5545 units in the processor. If more than one unit is specified, they will
5546 be scheduled independently. Only truly independent units should be
5547 counted; a pipelined unit should be specified as a single unit. (The
5548 only common example of a machine that has multiple function units for a
5549 single instruction class that are truly independent and not pipelined
5550 are the two multiply and two increment units of the CDC 6600.)
5552 @var{simultaneity} specifies the maximum number of insns that can be
5553 executing in each instance of the function unit simultaneously or zero
5554 if the unit is pipelined and has no limit.
5556 All @code{define_function_unit} definitions referring to function unit
5557 @var{name} must have the same name and values for @var{multiplicity} and
5560 @var{test} is an attribute test that selects the insns we are describing
5561 in this definition. Note that an insn may use more than one function
5562 unit and a function unit may be specified in more than one
5563 @code{define_function_unit}.
5565 @var{ready-delay} is an integer that specifies the number of cycles
5566 after which the result of the instruction can be used without
5567 introducing any stalls.
5569 @var{issue-delay} is an integer that specifies the number of cycles
5570 after the instruction matching the @var{test} expression begins using
5571 this unit until a subsequent instruction can begin. A cost of @var{N}
5572 indicates an @var{N-1} cycle delay. A subsequent instruction may also
5573 be delayed if an earlier instruction has a longer @var{ready-delay}
5574 value. This blocking effect is computed using the @var{simultaneity},
5575 @var{ready-delay}, @var{issue-delay}, and @var{conflict-list} terms.
5576 For a normal non-pipelined function unit, @var{simultaneity} is one, the
5577 unit is taken to block for the @var{ready-delay} cycles of the executing
5578 insn, and smaller values of @var{issue-delay} are ignored.
5580 @var{conflict-list} is an optional list giving detailed conflict costs
5581 for this unit. If specified, it is a list of condition test expressions
5582 to be applied to insns chosen to execute in @var{name} following the
5583 particular insn matching @var{test} that is already executing in
5584 @var{name}. For each insn in the list, @var{issue-delay} specifies the
5585 conflict cost; for insns not in the list, the cost is zero. If not
5586 specified, @var{conflict-list} defaults to all instructions that use the
5589 Typical uses of this vector are where a floating point function unit can
5590 pipeline either single- or double-precision operations, but not both, or
5591 where a memory unit can pipeline loads, but not stores, etc.
5593 As an example, consider a classic @acronym{RISC} machine where the
5594 result of a load instruction is not available for two cycles (a single
5595 ``delay'' instruction is required) and where only one load instruction
5596 can be executed simultaneously. This would be specified as:
5599 (define_function_unit "memory" 1 1 (eq_attr "type" "load") 2 0)
5602 For the case of a floating point function unit that can pipeline either
5603 single or double precision, but not both, the following could be specified:
5606 (define_function_unit
5607 "fp" 1 0 (eq_attr "type" "sp_fp") 4 4 [(eq_attr "type" "dp_fp")])
5608 (define_function_unit
5609 "fp" 1 0 (eq_attr "type" "dp_fp") 4 4 [(eq_attr "type" "sp_fp")])
5612 @strong{Note:} The scheduler attempts to avoid function unit conflicts
5613 and uses all the specifications in the @code{define_function_unit}
5614 expression. It has recently come to our attention that these
5615 specifications may not allow modeling of some of the newer
5616 ``superscalar'' processors that have insns using multiple pipelined
5617 units. These insns will cause a potential conflict for the second unit
5618 used during their execution and there is no way of representing that
5619 conflict. We welcome any examples of how function unit conflicts work
5620 in such processors and suggestions for their representation.
5622 @node Automaton pipeline description
5623 @subsubsection Describing instruction pipeline characteristics
5624 @cindex automaton based pipeline description
5626 This section describes constructions of the automaton based processor
5627 pipeline description. The order of constructions within the machine
5628 description file is not important.
5630 @findex define_automaton
5631 @cindex pipeline hazard recognizer
5632 The following optional construction describes names of automata
5633 generated and used for the pipeline hazards recognition. Sometimes
5634 the generated finite state automaton used by the pipeline hazard
5635 recognizer is large. If we use more than one automaton and bind functional
5636 units to the automata, the total size of the automata is usually
5637 less than the size of the single automaton. If there is no one such
5638 construction, only one finite state automaton is generated.
5641 (define_automaton @var{automata-names})
5644 @var{automata-names} is a string giving names of the automata. The
5645 names are separated by commas. All the automata should have unique names.
5646 The automaton name is used in the constructions @code{define_cpu_unit} and
5647 @code{define_query_cpu_unit}.
5649 @findex define_cpu_unit
5650 @cindex processor functional units
5651 Each processor functional unit used in the description of instruction
5652 reservations should be described by the following construction.
5655 (define_cpu_unit @var{unit-names} [@var{automaton-name}])
5658 @var{unit-names} is a string giving the names of the functional units
5659 separated by commas. Don't use name @samp{nothing}, it is reserved
5662 @var{automaton-name} is a string giving the name of the automaton with
5663 which the unit is bound. The automaton should be described in
5664 construction @code{define_automaton}. You should give
5665 @dfn{automaton-name}, if there is a defined automaton.
5667 The assignment of units to automata are constrained by the uses of the
5668 units in insn reservations. The most important constraint is: if a
5669 unit reservation is present on a particular cycle of an alternative
5670 for an insn reservation, then some unit from the same automaton must
5671 be present on the same cycle for the other alternatives of the insn
5672 reservation. The rest of the constraints are mentioned in the
5673 description of the subsequent constructions.
5675 @findex define_query_cpu_unit
5676 @cindex querying function unit reservations
5677 The following construction describes CPU functional units analogously
5678 to @code{define_cpu_unit}. The reservation of such units can be
5679 queried for an automaton state. The instruction scheduler never
5680 queries reservation of functional units for given automaton state. So
5681 as a rule, you don't need this construction. This construction could
5682 be used for future code generation goals (e.g. to generate
5683 @acronym{VLIW} insn templates).
5686 (define_query_cpu_unit @var{unit-names} [@var{automaton-name}])
5689 @var{unit-names} is a string giving names of the functional units
5690 separated by commas.
5692 @var{automaton-name} is a string giving the name of the automaton with
5693 which the unit is bound.
5695 @findex define_insn_reservation
5696 @cindex instruction latency time
5697 @cindex regular expressions
5699 The following construction is the major one to describe pipeline
5700 characteristics of an instruction.
5703 (define_insn_reservation @var{insn-name} @var{default_latency}
5704 @var{condition} @var{regexp})
5707 @var{default_latency} is a number giving latency time of the
5708 instruction. There is an important difference between the old
5709 description and the automaton based pipeline description. The latency
5710 time is used for all dependencies when we use the old description. In
5711 the automaton based pipeline description, the given latency time is only
5712 used for true dependencies. The cost of anti-dependencies is always
5713 zero and the cost of output dependencies is the difference between
5714 latency times of the producing and consuming insns (if the difference
5715 is negative, the cost is considered to be zero). You can always
5716 change the default costs for any description by using the target hook
5717 @code{TARGET_SCHED_ADJUST_COST} (@pxref{Scheduling}).
5719 @var{insn-name} is a string giving the internal name of the insn. The
5720 internal names are used in constructions @code{define_bypass} and in
5721 the automaton description file generated for debugging. The internal
5722 name has nothing in common with the names in @code{define_insn}. It is a
5723 good practice to use insn classes described in the processor manual.
5725 @var{condition} defines what RTL insns are described by this
5726 construction. You should remember that you will be in trouble if
5727 @var{condition} for two or more different
5728 @code{define_insn_reservation} constructions is TRUE for an insn. In
5729 this case what reservation will be used for the insn is not defined.
5730 Such cases are not checked during generation of the pipeline hazards
5731 recognizer because in general recognizing that two conditions may have
5732 the same value is quite difficult (especially if the conditions
5733 contain @code{symbol_ref}). It is also not checked during the
5734 pipeline hazard recognizer work because it would slow down the
5735 recognizer considerably.
5737 @var{regexp} is a string describing the reservation of the cpu's functional
5738 units by the instruction. The reservations are described by a regular
5739 expression according to the following syntax:
5742 regexp = regexp "," oneof
5745 oneof = oneof "|" allof
5748 allof = allof "+" repeat
5751 repeat = element "*" number
5754 element = cpu_function_unit_name
5763 @samp{,} is used for describing the start of the next cycle in
5767 @samp{|} is used for describing a reservation described by the first
5768 regular expression @strong{or} a reservation described by the second
5769 regular expression @strong{or} etc.
5772 @samp{+} is used for describing a reservation described by the first
5773 regular expression @strong{and} a reservation described by the
5774 second regular expression @strong{and} etc.
5777 @samp{*} is used for convenience and simply means a sequence in which
5778 the regular expression are repeated @var{number} times with cycle
5779 advancing (see @samp{,}).
5782 @samp{cpu_function_unit_name} denotes reservation of the named
5786 @samp{reservation_name} --- see description of construction
5787 @samp{define_reservation}.
5790 @samp{nothing} denotes no unit reservations.
5793 @findex define_reservation
5794 Sometimes unit reservations for different insns contain common parts.
5795 In such case, you can simplify the pipeline description by describing
5796 the common part by the following construction
5799 (define_reservation @var{reservation-name} @var{regexp})
5802 @var{reservation-name} is a string giving name of @var{regexp}.
5803 Functional unit names and reservation names are in the same name
5804 space. So the reservation names should be different from the
5805 functional unit names and can not be the reserved name @samp{nothing}.
5807 @findex define_bypass
5808 @cindex instruction latency time
5810 The following construction is used to describe exceptions in the
5811 latency time for given instruction pair. This is so called bypasses.
5814 (define_bypass @var{number} @var{out_insn_names} @var{in_insn_names}
5818 @var{number} defines when the result generated by the instructions
5819 given in string @var{out_insn_names} will be ready for the
5820 instructions given in string @var{in_insn_names}. The instructions in
5821 the string are separated by commas.
5823 @var{guard} is an optional string giving the name of a C function which
5824 defines an additional guard for the bypass. The function will get the
5825 two insns as parameters. If the function returns zero the bypass will
5826 be ignored for this case. The additional guard is necessary to
5827 recognize complicated bypasses, e.g. when the consumer is only an address
5828 of insn @samp{store} (not a stored value).
5830 @findex exclusion_set
5831 @findex presence_set
5832 @findex final_presence_set
5834 @findex final_absence_set
5837 The following five constructions are usually used to describe
5838 @acronym{VLIW} processors, or more precisely, to describe a placement
5839 of small instructions into @acronym{VLIW} instruction slots. They
5840 can be used for @acronym{RISC} processors, too.
5843 (exclusion_set @var{unit-names} @var{unit-names})
5844 (presence_set @var{unit-names} @var{patterns})
5845 (final_presence_set @var{unit-names} @var{patterns})
5846 (absence_set @var{unit-names} @var{patterns})
5847 (final_absence_set @var{unit-names} @var{patterns})
5850 @var{unit-names} is a string giving names of functional units
5851 separated by commas.
5853 @var{patterns} is a string giving patterns of functional units
5854 separated by comma. Currently pattern is is one unit or units
5855 separated by white-spaces.
5857 The first construction (@samp{exclusion_set}) means that each
5858 functional unit in the first string can not be reserved simultaneously
5859 with a unit whose name is in the second string and vice versa. For
5860 example, the construction is useful for describing processors
5861 (e.g. some SPARC processors) with a fully pipelined floating point
5862 functional unit which can execute simultaneously only single floating
5863 point insns or only double floating point insns.
5865 The second construction (@samp{presence_set}) means that each
5866 functional unit in the first string can not be reserved unless at
5867 least one of pattern of units whose names are in the second string is
5868 reserved. This is an asymmetric relation. For example, it is useful
5869 for description that @acronym{VLIW} @samp{slot1} is reserved after
5870 @samp{slot0} reservation. We could describe it by the following
5874 (presence_set "slot1" "slot0")
5877 Or @samp{slot1} is reserved only after @samp{slot0} and unit @samp{b0}
5878 reservation. In this case we could write
5881 (presence_set "slot1" "slot0 b0")
5884 The third construction (@samp{final_presence_set}) is analogous to
5885 @samp{presence_set}. The difference between them is when checking is
5886 done. When an instruction is issued in given automaton state
5887 reflecting all current and planned unit reservations, the automaton
5888 state is changed. The first state is a source state, the second one
5889 is a result state. Checking for @samp{presence_set} is done on the
5890 source state reservation, checking for @samp{final_presence_set} is
5891 done on the result reservation. This construction is useful to
5892 describe a reservation which is actually two subsequent reservations.
5893 For example, if we use
5896 (presence_set "slot1" "slot0")
5899 the following insn will be never issued (because @samp{slot1} requires
5900 @samp{slot0} which is absent in the source state).
5903 (define_reservation "insn_and_nop" "slot0 + slot1")
5906 but it can be issued if we use analogous @samp{final_presence_set}.
5908 The forth construction (@samp{absence_set}) means that each functional
5909 unit in the first string can be reserved only if each pattern of units
5910 whose names are in the second string is not reserved. This is an
5911 asymmetric relation (actually @samp{exclusion_set} is analogous to
5912 this one but it is symmetric). For example, it is useful for
5913 description that @acronym{VLIW} @samp{slot0} can not be reserved after
5914 @samp{slot1} or @samp{slot2} reservation. We could describe it by the
5915 following construction
5918 (absence_set "slot2" "slot0, slot1")
5921 Or @samp{slot2} can not be reserved if @samp{slot0} and unit @samp{b0}
5922 are reserved or @samp{slot1} and unit @samp{b1} are reserved. In
5923 this case we could write
5926 (absence_set "slot2" "slot0 b0, slot1 b1")
5929 All functional units mentioned in a set should belong to the same
5932 The last construction (@samp{final_absence_set}) is analogous to
5933 @samp{absence_set} but checking is done on the result (state)
5934 reservation. See comments for @samp{final_presence_set}.
5936 @findex automata_option
5937 @cindex deterministic finite state automaton
5938 @cindex nondeterministic finite state automaton
5939 @cindex finite state automaton minimization
5940 You can control the generator of the pipeline hazard recognizer with
5941 the following construction.
5944 (automata_option @var{options})
5947 @var{options} is a string giving options which affect the generated
5948 code. Currently there are the following options:
5952 @dfn{no-minimization} makes no minimization of the automaton. This is
5953 only worth to do when we are debugging the description and need to
5954 look more accurately at reservations of states.
5957 @dfn{time} means printing additional time statistics about
5958 generation of automata.
5961 @dfn{v} means a generation of the file describing the result automata.
5962 The file has suffix @samp{.dfa} and can be used for the description
5963 verification and debugging.
5966 @dfn{w} means a generation of warning instead of error for
5967 non-critical errors.
5970 @dfn{ndfa} makes nondeterministic finite state automata. This affects
5971 the treatment of operator @samp{|} in the regular expressions. The
5972 usual treatment of the operator is to try the first alternative and,
5973 if the reservation is not possible, the second alternative. The
5974 nondeterministic treatment means trying all alternatives, some of them
5975 may be rejected by reservations in the subsequent insns. You can not
5976 query functional unit reservations in nondeterministic automaton
5980 @dfn{progress} means output of a progress bar showing how many states
5981 were generated so far for automaton being processed. This is useful
5982 during debugging a @acronym{DFA} description. If you see too many
5983 generated states, you could interrupt the generator of the pipeline
5984 hazard recognizer and try to figure out a reason for generation of the
5988 As an example, consider a superscalar @acronym{RISC} machine which can
5989 issue three insns (two integer insns and one floating point insn) on
5990 the cycle but can finish only two insns. To describe this, we define
5991 the following functional units.
5994 (define_cpu_unit "i0_pipeline, i1_pipeline, f_pipeline")
5995 (define_cpu_unit "port0, port1")
5998 All simple integer insns can be executed in any integer pipeline and
5999 their result is ready in two cycles. The simple integer insns are
6000 issued into the first pipeline unless it is reserved, otherwise they
6001 are issued into the second pipeline. Integer division and
6002 multiplication insns can be executed only in the second integer
6003 pipeline and their results are ready correspondingly in 8 and 4
6004 cycles. The integer division is not pipelined, i.e. the subsequent
6005 integer division insn can not be issued until the current division
6006 insn finished. Floating point insns are fully pipelined and their
6007 results are ready in 3 cycles. Where the result of a floating point
6008 insn is used by an integer insn, an additional delay of one cycle is
6009 incurred. To describe all of this we could specify
6012 (define_cpu_unit "div")
6014 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
6015 "(i0_pipeline | i1_pipeline), (port0 | port1)")
6017 (define_insn_reservation "mult" 4 (eq_attr "type" "mult")
6018 "i1_pipeline, nothing*2, (port0 | port1)")
6020 (define_insn_reservation "div" 8 (eq_attr "type" "div")
6021 "i1_pipeline, div*7, div + (port0 | port1)")
6023 (define_insn_reservation "float" 3 (eq_attr "type" "float")
6024 "f_pipeline, nothing, (port0 | port1))
6026 (define_bypass 4 "float" "simple,mult,div")
6029 To simplify the description we could describe the following reservation
6032 (define_reservation "finish" "port0|port1")
6035 and use it in all @code{define_insn_reservation} as in the following
6039 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
6040 "(i0_pipeline | i1_pipeline), finish")
6044 @node Comparison of the two descriptions
6045 @subsubsection Drawbacks of the old pipeline description
6046 @cindex old pipeline description
6047 @cindex automaton based pipeline description
6048 @cindex processor functional units
6049 @cindex interlock delays
6050 @cindex instruction latency time
6051 @cindex pipeline hazard recognizer
6054 The old instruction level parallelism description and the pipeline
6055 hazards recognizer based on it have the following drawbacks in
6056 comparison with the @acronym{DFA}-based ones:
6060 Each functional unit is believed to be reserved at the instruction
6061 execution start. This is a very inaccurate model for modern
6065 An inadequate description of instruction latency times. The latency
6066 time is bound with a functional unit reserved by an instruction not
6067 with the instruction itself. In other words, the description is
6068 oriented to describe at most one unit reservation by each instruction.
6069 It also does not permit to describe special bypasses between
6073 The implementation of the pipeline hazard recognizer interface has
6074 constraints on number of functional units. This is a number of bits
6075 in integer on the host machine.
6078 The interface to the pipeline hazard recognizer is more complex than
6079 one to the automaton based pipeline recognizer.
6082 An unnatural description when you write a unit and a condition which
6083 selects instructions using the unit. Writing all unit reservations
6084 for an instruction (an instruction class) is more natural.
6087 The recognition of the interlock delays has a slow implementation. The GCC
6088 scheduler supports structures which describe the unit reservations.
6089 The more functional units a processor has, the slower its pipeline hazard
6090 recognizer will be. Such an implementation would become even slower when we
6092 reserve functional units not only at the instruction execution start.
6093 In an automaton based pipeline hazard recognizer, speed is not dependent
6094 on processor complexity.
6097 @node Conditional Execution
6098 @section Conditional Execution
6099 @cindex conditional execution
6102 A number of architectures provide for some form of conditional
6103 execution, or predication. The hallmark of this feature is the
6104 ability to nullify most of the instructions in the instruction set.
6105 When the instruction set is large and not entirely symmetric, it
6106 can be quite tedious to describe these forms directly in the
6107 @file{.md} file. An alternative is the @code{define_cond_exec} template.
6109 @findex define_cond_exec
6112 [@var{predicate-pattern}]
6114 "@var{output-template}")
6117 @var{predicate-pattern} is the condition that must be true for the
6118 insn to be executed at runtime and should match a relational operator.
6119 One can use @code{match_operator} to match several relational operators
6120 at once. Any @code{match_operand} operands must have no more than one
6123 @var{condition} is a C expression that must be true for the generated
6126 @findex current_insn_predicate
6127 @var{output-template} is a string similar to the @code{define_insn}
6128 output template (@pxref{Output Template}), except that the @samp{*}
6129 and @samp{@@} special cases do not apply. This is only useful if the
6130 assembly text for the predicate is a simple prefix to the main insn.
6131 In order to handle the general case, there is a global variable
6132 @code{current_insn_predicate} that will contain the entire predicate
6133 if the current insn is predicated, and will otherwise be @code{NULL}.
6135 When @code{define_cond_exec} is used, an implicit reference to
6136 the @code{predicable} instruction attribute is made.
6137 @xref{Insn Attributes}. This attribute must be boolean (i.e.@: have
6138 exactly two elements in its @var{list-of-values}). Further, it must
6139 not be used with complex expressions. That is, the default and all
6140 uses in the insns must be a simple constant, not dependent on the
6141 alternative or anything else.
6143 For each @code{define_insn} for which the @code{predicable}
6144 attribute is true, a new @code{define_insn} pattern will be
6145 generated that matches a predicated version of the instruction.
6149 (define_insn "addsi"
6150 [(set (match_operand:SI 0 "register_operand" "r")
6151 (plus:SI (match_operand:SI 1 "register_operand" "r")
6152 (match_operand:SI 2 "register_operand" "r")))]
6157 [(ne (match_operand:CC 0 "register_operand" "c")
6164 generates a new pattern
6169 (ne (match_operand:CC 3 "register_operand" "c") (const_int 0))
6170 (set (match_operand:SI 0 "register_operand" "r")
6171 (plus:SI (match_operand:SI 1 "register_operand" "r")
6172 (match_operand:SI 2 "register_operand" "r"))))]
6173 "(@var{test2}) && (@var{test1})"
6174 "(%3) add %2,%1,%0")
6177 @node Constant Definitions
6178 @section Constant Definitions
6179 @cindex constant definitions
6180 @findex define_constants
6182 Using literal constants inside instruction patterns reduces legibility and
6183 can be a maintenance problem.
6185 To overcome this problem, you may use the @code{define_constants}
6186 expression. It contains a vector of name-value pairs. From that
6187 point on, wherever any of the names appears in the MD file, it is as
6188 if the corresponding value had been written instead. You may use
6189 @code{define_constants} multiple times; each appearance adds more
6190 constants to the table. It is an error to redefine a constant with
6193 To come back to the a29k load multiple example, instead of
6197 [(match_parallel 0 "load_multiple_operation"
6198 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
6199 (match_operand:SI 2 "memory_operand" "m"))
6201 (clobber (reg:SI 179))])]
6217 [(match_parallel 0 "load_multiple_operation"
6218 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
6219 (match_operand:SI 2 "memory_operand" "m"))
6221 (clobber (reg:SI R_CR))])]
6226 The constants that are defined with a define_constant are also output
6227 in the insn-codes.h header file as #defines.