1 @c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1996, 1998, 1999, 2000, 2001,
2 @c 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
3 @c This is part of the GCC manual.
4 @c For copying conditions, see the file gcc.texi.
8 @chapter Machine Descriptions
9 @cindex machine descriptions
11 A machine description has two parts: a file of instruction patterns
12 (@file{.md} file) and a C header file of macro definitions.
14 The @file{.md} file for a target machine contains a pattern for each
15 instruction that the target machine supports (or at least each instruction
16 that is worth telling the compiler about). It may also contain comments.
17 A semicolon causes the rest of the line to be a comment, unless the semicolon
18 is inside a quoted string.
20 See the next chapter for information on the C header file.
23 * Overview:: How the machine description is used.
24 * Patterns:: How to write instruction patterns.
25 * Example:: An explained example of a @code{define_insn} pattern.
26 * RTL Template:: The RTL template defines what insns match a pattern.
27 * Output Template:: The output template says how to make assembler code
29 * Output Statement:: For more generality, write C code to output
31 * Predicates:: Controlling what kinds of operands can be used
33 * Constraints:: Fine-tuning operand selection.
34 * Standard Names:: Names mark patterns to use for code generation.
35 * Pattern Ordering:: When the order of patterns makes a difference.
36 * Dependent Patterns:: Having one pattern may make you need another.
37 * Jump Patterns:: Special considerations for patterns for jump insns.
38 * Looping Patterns:: How to define patterns for special looping insns.
39 * Insn Canonicalizations::Canonicalization of Instructions
40 * Expander Definitions::Generating a sequence of several RTL insns
41 for a standard operation.
42 * Insn Splitting:: Splitting Instructions into Multiple Instructions.
43 * Including Patterns:: Including Patterns in Machine Descriptions.
44 * Peephole Definitions::Defining machine-specific peephole optimizations.
45 * Insn Attributes:: Specifying the value of attributes for generated insns.
46 * Conditional Execution::Generating @code{define_insn} patterns for
48 * Constant Definitions::Defining symbolic constants that can be used in the
50 * Macros:: Using macros to generate patterns from a template.
54 @section Overview of How the Machine Description is Used
56 There are three main conversions that happen in the compiler:
61 The front end reads the source code and builds a parse tree.
64 The parse tree is used to generate an RTL insn list based on named
68 The insn list is matched against the RTL templates to produce assembler
73 For the generate pass, only the names of the insns matter, from either a
74 named @code{define_insn} or a @code{define_expand}. The compiler will
75 choose the pattern with the right name and apply the operands according
76 to the documentation later in this chapter, without regard for the RTL
77 template or operand constraints. Note that the names the compiler looks
78 for are hard-coded in the compiler---it will ignore unnamed patterns and
79 patterns with names it doesn't know about, but if you don't provide a
80 named pattern it needs, it will abort.
82 If a @code{define_insn} is used, the template given is inserted into the
83 insn list. If a @code{define_expand} is used, one of three things
84 happens, based on the condition logic. The condition logic may manually
85 create new insns for the insn list, say via @code{emit_insn()}, and
86 invoke @code{DONE}. For certain named patterns, it may invoke @code{FAIL} to tell the
87 compiler to use an alternate way of performing that task. If it invokes
88 neither @code{DONE} nor @code{FAIL}, the template given in the pattern
89 is inserted, as if the @code{define_expand} were a @code{define_insn}.
91 Once the insn list is generated, various optimization passes convert,
92 replace, and rearrange the insns in the insn list. This is where the
93 @code{define_split} and @code{define_peephole} patterns get used, for
96 Finally, the insn list's RTL is matched up with the RTL templates in the
97 @code{define_insn} patterns, and those patterns are used to emit the
98 final assembly code. For this purpose, each named @code{define_insn}
99 acts like it's unnamed, since the names are ignored.
102 @section Everything about Instruction Patterns
104 @cindex instruction patterns
107 Each instruction pattern contains an incomplete RTL expression, with pieces
108 to be filled in later, operand constraints that restrict how the pieces can
109 be filled in, and an output pattern or C code to generate the assembler
110 output, all wrapped up in a @code{define_insn} expression.
112 A @code{define_insn} is an RTL expression containing four or five operands:
116 An optional name. The presence of a name indicate that this instruction
117 pattern can perform a certain standard job for the RTL-generation
118 pass of the compiler. This pass knows certain names and will use
119 the instruction patterns with those names, if the names are defined
120 in the machine description.
122 The absence of a name is indicated by writing an empty string
123 where the name should go. Nameless instruction patterns are never
124 used for generating RTL code, but they may permit several simpler insns
125 to be combined later on.
127 Names that are not thus known and used in RTL-generation have no
128 effect; they are equivalent to no name at all.
130 For the purpose of debugging the compiler, you may also specify a
131 name beginning with the @samp{*} character. Such a name is used only
132 for identifying the instruction in RTL dumps; it is entirely equivalent
133 to having a nameless pattern for all other purposes.
136 The @dfn{RTL template} (@pxref{RTL Template}) is a vector of incomplete
137 RTL expressions which show what the instruction should look like. It is
138 incomplete because it may contain @code{match_operand},
139 @code{match_operator}, and @code{match_dup} expressions that stand for
140 operands of the instruction.
142 If the vector has only one element, that element is the template for the
143 instruction pattern. If the vector has multiple elements, then the
144 instruction pattern is a @code{parallel} expression containing the
148 @cindex pattern conditions
149 @cindex conditions, in patterns
150 A condition. This is a string which contains a C expression that is
151 the final test to decide whether an insn body matches this pattern.
153 @cindex named patterns and conditions
154 For a named pattern, the condition (if present) may not depend on
155 the data in the insn being matched, but only the target-machine-type
156 flags. The compiler needs to test these conditions during
157 initialization in order to learn exactly which named instructions are
158 available in a particular run.
161 For nameless patterns, the condition is applied only when matching an
162 individual insn, and only after the insn has matched the pattern's
163 recognition template. The insn's operands may be found in the vector
164 @code{operands}. For an insn where the condition has once matched, it
165 can't be used to control register allocation, for example by excluding
166 certain hard registers or hard register combinations.
169 The @dfn{output template}: a string that says how to output matching
170 insns as assembler code. @samp{%} in this string specifies where
171 to substitute the value of an operand. @xref{Output Template}.
173 When simple substitution isn't general enough, you can specify a piece
174 of C code to compute the output. @xref{Output Statement}.
177 Optionally, a vector containing the values of attributes for insns matching
178 this pattern. @xref{Insn Attributes}.
182 @section Example of @code{define_insn}
183 @cindex @code{define_insn} example
185 Here is an actual example of an instruction pattern, for the 68000/68020.
190 (match_operand:SI 0 "general_operand" "rm"))]
194 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
196 return \"cmpl #0,%0\";
201 This can also be written using braced strings:
206 (match_operand:SI 0 "general_operand" "rm"))]
209 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
215 This is an instruction that sets the condition codes based on the value of
216 a general operand. It has no condition, so any insn whose RTL description
217 has the form shown may be handled according to this pattern. The name
218 @samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL generation
219 pass that, when it is necessary to test such a value, an insn to do so
220 can be constructed using this pattern.
222 The output control string is a piece of C code which chooses which
223 output template to return based on the kind of operand and the specific
224 type of CPU for which code is being generated.
226 @samp{"rm"} is an operand constraint. Its meaning is explained below.
229 @section RTL Template
230 @cindex RTL insn template
231 @cindex generating insns
232 @cindex insns, generating
233 @cindex recognizing insns
234 @cindex insns, recognizing
236 The RTL template is used to define which insns match the particular pattern
237 and how to find their operands. For named patterns, the RTL template also
238 says how to construct an insn from specified operands.
240 Construction involves substituting specified operands into a copy of the
241 template. Matching involves determining the values that serve as the
242 operands in the insn being matched. Both of these activities are
243 controlled by special expression types that direct matching and
244 substitution of the operands.
247 @findex match_operand
248 @item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint})
249 This expression is a placeholder for operand number @var{n} of
250 the insn. When constructing an insn, operand number @var{n}
251 will be substituted at this point. When matching an insn, whatever
252 appears at this position in the insn will be taken as operand
253 number @var{n}; but it must satisfy @var{predicate} or this instruction
254 pattern will not match at all.
256 Operand numbers must be chosen consecutively counting from zero in
257 each instruction pattern. There may be only one @code{match_operand}
258 expression in the pattern for each operand number. Usually operands
259 are numbered in the order of appearance in @code{match_operand}
260 expressions. In the case of a @code{define_expand}, any operand numbers
261 used only in @code{match_dup} expressions have higher values than all
262 other operand numbers.
264 @var{predicate} is a string that is the name of a function that
265 accepts two arguments, an expression and a machine mode.
266 @xref{Predicates}. During matching, the function will be called with
267 the putative operand as the expression and @var{m} as the mode
268 argument (if @var{m} is not specified, @code{VOIDmode} will be used,
269 which normally causes @var{predicate} to accept any mode). If it
270 returns zero, this instruction pattern fails to match.
271 @var{predicate} may be an empty string; then it means no test is to be
272 done on the operand, so anything which occurs in this position is
275 Most of the time, @var{predicate} will reject modes other than @var{m}---but
276 not always. For example, the predicate @code{address_operand} uses
277 @var{m} as the mode of memory ref that the address should be valid for.
278 Many predicates accept @code{const_int} nodes even though their mode is
281 @var{constraint} controls reloading and the choice of the best register
282 class to use for a value, as explained later (@pxref{Constraints}).
283 If the constraint would be an empty string, it can be omitted.
285 People are often unclear on the difference between the constraint and the
286 predicate. The predicate helps decide whether a given insn matches the
287 pattern. The constraint plays no role in this decision; instead, it
288 controls various decisions in the case of an insn which does match.
290 @findex match_scratch
291 @item (match_scratch:@var{m} @var{n} @var{constraint})
292 This expression is also a placeholder for operand number @var{n}
293 and indicates that operand must be a @code{scratch} or @code{reg}
296 When matching patterns, this is equivalent to
299 (match_operand:@var{m} @var{n} "scratch_operand" @var{pred})
302 but, when generating RTL, it produces a (@code{scratch}:@var{m})
305 If the last few expressions in a @code{parallel} are @code{clobber}
306 expressions whose operands are either a hard register or
307 @code{match_scratch}, the combiner can add or delete them when
308 necessary. @xref{Side Effects}.
311 @item (match_dup @var{n})
312 This expression is also a placeholder for operand number @var{n}.
313 It is used when the operand needs to appear more than once in the
316 In construction, @code{match_dup} acts just like @code{match_operand}:
317 the operand is substituted into the insn being constructed. But in
318 matching, @code{match_dup} behaves differently. It assumes that operand
319 number @var{n} has already been determined by a @code{match_operand}
320 appearing earlier in the recognition template, and it matches only an
321 identical-looking expression.
323 Note that @code{match_dup} should not be used to tell the compiler that
324 a particular register is being used for two operands (example:
325 @code{add} that adds one register to another; the second register is
326 both an input operand and the output operand). Use a matching
327 constraint (@pxref{Simple Constraints}) for those. @code{match_dup} is for the cases where one
328 operand is used in two places in the template, such as an instruction
329 that computes both a quotient and a remainder, where the opcode takes
330 two input operands but the RTL template has to refer to each of those
331 twice; once for the quotient pattern and once for the remainder pattern.
333 @findex match_operator
334 @item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}])
335 This pattern is a kind of placeholder for a variable RTL expression
338 When constructing an insn, it stands for an RTL expression whose
339 expression code is taken from that of operand @var{n}, and whose
340 operands are constructed from the patterns @var{operands}.
342 When matching an expression, it matches an expression if the function
343 @var{predicate} returns nonzero on that expression @emph{and} the
344 patterns @var{operands} match the operands of the expression.
346 Suppose that the function @code{commutative_operator} is defined as
347 follows, to match any expression whose operator is one of the
348 commutative arithmetic operators of RTL and whose mode is @var{mode}:
352 commutative_integer_operator (x, mode)
354 enum machine_mode mode;
356 enum rtx_code code = GET_CODE (x);
357 if (GET_MODE (x) != mode)
359 return (GET_RTX_CLASS (code) == RTX_COMM_ARITH
360 || code == EQ || code == NE);
364 Then the following pattern will match any RTL expression consisting
365 of a commutative operator applied to two general operands:
368 (match_operator:SI 3 "commutative_operator"
369 [(match_operand:SI 1 "general_operand" "g")
370 (match_operand:SI 2 "general_operand" "g")])
373 Here the vector @code{[@var{operands}@dots{}]} contains two patterns
374 because the expressions to be matched all contain two operands.
376 When this pattern does match, the two operands of the commutative
377 operator are recorded as operands 1 and 2 of the insn. (This is done
378 by the two instances of @code{match_operand}.) Operand 3 of the insn
379 will be the entire commutative expression: use @code{GET_CODE
380 (operands[3])} to see which commutative operator was used.
382 The machine mode @var{m} of @code{match_operator} works like that of
383 @code{match_operand}: it is passed as the second argument to the
384 predicate function, and that function is solely responsible for
385 deciding whether the expression to be matched ``has'' that mode.
387 When constructing an insn, argument 3 of the gen-function will specify
388 the operation (i.e.@: the expression code) for the expression to be
389 made. It should be an RTL expression, whose expression code is copied
390 into a new expression whose operands are arguments 1 and 2 of the
391 gen-function. The subexpressions of argument 3 are not used;
392 only its expression code matters.
394 When @code{match_operator} is used in a pattern for matching an insn,
395 it usually best if the operand number of the @code{match_operator}
396 is higher than that of the actual operands of the insn. This improves
397 register allocation because the register allocator often looks at
398 operands 1 and 2 of insns to see if it can do register tying.
400 There is no way to specify constraints in @code{match_operator}. The
401 operand of the insn which corresponds to the @code{match_operator}
402 never has any constraints because it is never reloaded as a whole.
403 However, if parts of its @var{operands} are matched by
404 @code{match_operand} patterns, those parts may have constraints of
408 @item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}])
409 Like @code{match_dup}, except that it applies to operators instead of
410 operands. When constructing an insn, operand number @var{n} will be
411 substituted at this point. But in matching, @code{match_op_dup} behaves
412 differently. It assumes that operand number @var{n} has already been
413 determined by a @code{match_operator} appearing earlier in the
414 recognition template, and it matches only an identical-looking
417 @findex match_parallel
418 @item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}])
419 This pattern is a placeholder for an insn that consists of a
420 @code{parallel} expression with a variable number of elements. This
421 expression should only appear at the top level of an insn pattern.
423 When constructing an insn, operand number @var{n} will be substituted at
424 this point. When matching an insn, it matches if the body of the insn
425 is a @code{parallel} expression with at least as many elements as the
426 vector of @var{subpat} expressions in the @code{match_parallel}, if each
427 @var{subpat} matches the corresponding element of the @code{parallel},
428 @emph{and} the function @var{predicate} returns nonzero on the
429 @code{parallel} that is the body of the insn. It is the responsibility
430 of the predicate to validate elements of the @code{parallel} beyond
431 those listed in the @code{match_parallel}.
433 A typical use of @code{match_parallel} is to match load and store
434 multiple expressions, which can contain a variable number of elements
435 in a @code{parallel}. For example,
439 [(match_parallel 0 "load_multiple_operation"
440 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
441 (match_operand:SI 2 "memory_operand" "m"))
443 (clobber (reg:SI 179))])]
448 This example comes from @file{a29k.md}. The function
449 @code{load_multiple_operation} is defined in @file{a29k.c} and checks
450 that subsequent elements in the @code{parallel} are the same as the
451 @code{set} in the pattern, except that they are referencing subsequent
452 registers and memory locations.
454 An insn that matches this pattern might look like:
458 [(set (reg:SI 20) (mem:SI (reg:SI 100)))
460 (clobber (reg:SI 179))
462 (mem:SI (plus:SI (reg:SI 100)
465 (mem:SI (plus:SI (reg:SI 100)
469 @findex match_par_dup
470 @item (match_par_dup @var{n} [@var{subpat}@dots{}])
471 Like @code{match_op_dup}, but for @code{match_parallel} instead of
472 @code{match_operator}.
476 @node Output Template
477 @section Output Templates and Operand Substitution
478 @cindex output templates
479 @cindex operand substitution
481 @cindex @samp{%} in template
483 The @dfn{output template} is a string which specifies how to output the
484 assembler code for an instruction pattern. Most of the template is a
485 fixed string which is output literally. The character @samp{%} is used
486 to specify where to substitute an operand; it can also be used to
487 identify places where different variants of the assembler require
490 In the simplest case, a @samp{%} followed by a digit @var{n} says to output
491 operand @var{n} at that point in the string.
493 @samp{%} followed by a letter and a digit says to output an operand in an
494 alternate fashion. Four letters have standard, built-in meanings described
495 below. The machine description macro @code{PRINT_OPERAND} can define
496 additional letters with nonstandard meanings.
498 @samp{%c@var{digit}} can be used to substitute an operand that is a
499 constant value without the syntax that normally indicates an immediate
502 @samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of
503 the constant is negated before printing.
505 @samp{%a@var{digit}} can be used to substitute an operand as if it were a
506 memory reference, with the actual operand treated as the address. This may
507 be useful when outputting a ``load address'' instruction, because often the
508 assembler syntax for such an instruction requires you to write the operand
509 as if it were a memory reference.
511 @samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump
514 @samp{%=} outputs a number which is unique to each instruction in the
515 entire compilation. This is useful for making local labels to be
516 referred to more than once in a single template that generates multiple
517 assembler instructions.
519 @samp{%} followed by a punctuation character specifies a substitution that
520 does not use an operand. Only one case is standard: @samp{%%} outputs a
521 @samp{%} into the assembler code. Other nonstandard cases can be
522 defined in the @code{PRINT_OPERAND} macro. You must also define
523 which punctuation characters are valid with the
524 @code{PRINT_OPERAND_PUNCT_VALID_P} macro.
528 The template may generate multiple assembler instructions. Write the text
529 for the instructions, with @samp{\;} between them.
531 @cindex matching operands
532 When the RTL contains two operands which are required by constraint to match
533 each other, the output template must refer only to the lower-numbered operand.
534 Matching operands are not always identical, and the rest of the compiler
535 arranges to put the proper RTL expression for printing into the lower-numbered
538 One use of nonstandard letters or punctuation following @samp{%} is to
539 distinguish between different assembler languages for the same machine; for
540 example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax
541 requires periods in most opcode names, while MIT syntax does not. For
542 example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola
543 syntax. The same file of patterns is used for both kinds of output syntax,
544 but the character sequence @samp{%.} is used in each place where Motorola
545 syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax
546 defines the sequence to output a period; the macro for MIT syntax defines
549 @cindex @code{#} in template
550 As a special case, a template consisting of the single character @code{#}
551 instructs the compiler to first split the insn, and then output the
552 resulting instructions separately. This helps eliminate redundancy in the
553 output templates. If you have a @code{define_insn} that needs to emit
554 multiple assembler instructions, and there is an matching @code{define_split}
555 already defined, then you can simply use @code{#} as the output template
556 instead of writing an output template that emits the multiple assembler
559 If the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct
560 of the form @samp{@{option0|option1|option2@}} in the templates. These
561 describe multiple variants of assembler language syntax.
562 @xref{Instruction Output}.
564 @node Output Statement
565 @section C Statements for Assembler Output
566 @cindex output statements
567 @cindex C statements for assembler output
568 @cindex generating assembler output
570 Often a single fixed template string cannot produce correct and efficient
571 assembler code for all the cases that are recognized by a single
572 instruction pattern. For example, the opcodes may depend on the kinds of
573 operands; or some unfortunate combinations of operands may require extra
574 machine instructions.
576 If the output control string starts with a @samp{@@}, then it is actually
577 a series of templates, each on a separate line. (Blank lines and
578 leading spaces and tabs are ignored.) The templates correspond to the
579 pattern's constraint alternatives (@pxref{Multi-Alternative}). For example,
580 if a target machine has a two-address add instruction @samp{addr} to add
581 into a register and another @samp{addm} to add a register to memory, you
582 might write this pattern:
585 (define_insn "addsi3"
586 [(set (match_operand:SI 0 "general_operand" "=r,m")
587 (plus:SI (match_operand:SI 1 "general_operand" "0,0")
588 (match_operand:SI 2 "general_operand" "g,r")))]
595 @cindex @code{*} in template
596 @cindex asterisk in template
597 If the output control string starts with a @samp{*}, then it is not an
598 output template but rather a piece of C program that should compute a
599 template. It should execute a @code{return} statement to return the
600 template-string you want. Most such templates use C string literals, which
601 require doublequote characters to delimit them. To include these
602 doublequote characters in the string, prefix each one with @samp{\}.
604 If the output control string is written as a brace block instead of a
605 double-quoted string, it is automatically assumed to be C code. In that
606 case, it is not necessary to put in a leading asterisk, or to escape the
607 doublequotes surrounding C string literals.
609 The operands may be found in the array @code{operands}, whose C data type
612 It is very common to select different ways of generating assembler code
613 based on whether an immediate operand is within a certain range. Be
614 careful when doing this, because the result of @code{INTVAL} is an
615 integer on the host machine. If the host machine has more bits in an
616 @code{int} than the target machine has in the mode in which the constant
617 will be used, then some of the bits you get from @code{INTVAL} will be
618 superfluous. For proper results, you must carefully disregard the
619 values of those bits.
621 @findex output_asm_insn
622 It is possible to output an assembler instruction and then go on to output
623 or compute more of them, using the subroutine @code{output_asm_insn}. This
624 receives two arguments: a template-string and a vector of operands. The
625 vector may be @code{operands}, or it may be another array of @code{rtx}
626 that you declare locally and initialize yourself.
628 @findex which_alternative
629 When an insn pattern has multiple alternatives in its constraints, often
630 the appearance of the assembler code is determined mostly by which alternative
631 was matched. When this is so, the C code can test the variable
632 @code{which_alternative}, which is the ordinal number of the alternative
633 that was actually satisfied (0 for the first, 1 for the second alternative,
636 For example, suppose there are two opcodes for storing zero, @samp{clrreg}
637 for registers and @samp{clrmem} for memory locations. Here is how
638 a pattern could use @code{which_alternative} to choose between them:
642 [(set (match_operand:SI 0 "general_operand" "=r,m")
646 return (which_alternative == 0
647 ? "clrreg %0" : "clrmem %0");
651 The example above, where the assembler code to generate was
652 @emph{solely} determined by the alternative, could also have been specified
653 as follows, having the output control string start with a @samp{@@}:
658 [(set (match_operand:SI 0 "general_operand" "=r,m")
670 @cindex operand predicates
671 @cindex operator predicates
673 A predicate determines whether a @code{match_operand} or
674 @code{match_operator} expression matches, and therefore whether the
675 surrounding instruction pattern will be used for that combination of
676 operands. GCC has a number of machine-independent predicates, and you
677 can define machine-specific predicates as needed. By convention,
678 predicates used with @code{match_operand} have names that end in
679 @samp{_operand}, and those used with @code{match_operator} have names
680 that end in @samp{_operator}.
682 All predicates are Boolean functions (in the mathematical sense) of
683 two arguments: the RTL expression that is being considered at that
684 position in the instruction pattern, and the machine mode that the
685 @code{match_operand} or @code{match_operator} specifies. In this
686 section, the first argument is called @var{op} and the second argument
687 @var{mode}. Predicates can be called from C as ordinary two-argument
688 functions; this can be useful in output templates or other
689 machine-specific code.
691 Operand predicates can allow operands that are not actually acceptable
692 to the hardware, as long as the constraints give reload the ability to
693 fix them up (@pxref{Constraints}). However, GCC will usually generate
694 better code if the predicates specify the requirements of the machine
695 instructions as closely as possible. Reload cannot fix up operands
696 that must be constants (``immediate operands''); you must use a
697 predicate that allows only constants, or else enforce the requirement
698 in the extra condition.
700 @cindex predicates and machine modes
701 @cindex normal predicates
702 @cindex special predicates
703 Most predicates handle their @var{mode} argument in a uniform manner.
704 If @var{mode} is @code{VOIDmode} (unspecified), then @var{op} can have
705 any mode. If @var{mode} is anything else, then @var{op} must have the
706 same mode, unless @var{op} is a @code{CONST_INT} or integer
707 @code{CONST_DOUBLE}. These RTL expressions always have
708 @code{VOIDmode}, so it would be counterproductive to check that their
709 mode matches. Instead, predicates that accept @code{CONST_INT} and/or
710 integer @code{CONST_DOUBLE} check that the value stored in the
711 constant will fit in the requested mode.
713 Predicates with this behavior are called @dfn{normal}.
714 @command{genrecog} can optimize the instruction recognizer based on
715 knowledge of how normal predicates treat modes. It can also diagnose
716 certain kinds of common errors in the use of normal predicates; for
717 instance, it is almost always an error to use a normal predicate
718 without specifying a mode.
720 Predicates that do something different with their @var{mode} argument
721 are called @dfn{special}. The generic predicates
722 @code{address_operand} and @code{pmode_register_operand} are special
723 predicates. @command{genrecog} does not do any optimizations or
724 diagnosis when special predicates are used.
727 * Machine-Independent Predicates:: Predicates available to all back ends.
728 * Defining Predicates:: How to write machine-specific predicate
732 @node Machine-Independent Predicates
733 @subsection Machine-Independent Predicates
734 @cindex machine-independent predicates
735 @cindex generic predicates
737 These are the generic predicates available to all back ends. They are
738 defined in @file{recog.c}. The first category of predicates allow
739 only constant, or @dfn{immediate}, operands.
741 @defun immediate_operand
742 This predicate allows any sort of constant that fits in @var{mode}.
743 It is an appropriate choice for instructions that take operands that
747 @defun const_int_operand
748 This predicate allows any @code{CONST_INT} expression that fits in
749 @var{mode}. It is an appropriate choice for an immediate operand that
750 does not allow a symbol or label.
753 @defun const_double_operand
754 This predicate accepts any @code{CONST_DOUBLE} expression that has
755 exactly @var{mode}. If @var{mode} is @code{VOIDmode}, it will also
756 accept @code{CONST_INT}. It is intended for immediate floating point
761 The second category of predicates allow only some kind of machine
764 @defun register_operand
765 This predicate allows any @code{REG} or @code{SUBREG} expression that
766 is valid for @var{mode}. It is often suitable for arithmetic
767 instruction operands on a RISC machine.
770 @defun pmode_register_operand
771 This is a slight variant on @code{register_operand} which works around
772 a limitation in the machine-description reader.
775 (match_operand @var{n} "pmode_register_operand" @var{constraint})
782 (match_operand:P @var{n} "register_operand" @var{constraint})
786 would mean, if the machine-description reader accepted @samp{:P}
787 mode suffixes. Unfortunately, it cannot, because @code{Pmode} is an
788 alias for some other mode, and might vary with machine-specific
789 options. @xref{Misc}.
792 @defun scratch_operand
793 This predicate allows hard registers and @code{SCRATCH} expressions,
794 but not pseudo-registers. It is used internally by @code{match_scratch};
795 it should not be used directly.
799 The third category of predicates allow only some kind of memory reference.
801 @defun memory_operand
802 This predicate allows any valid reference to a quantity of mode
803 @var{mode} in memory, as determined by the weak form of
804 @code{GO_IF_LEGITIMATE_ADDRESS} (@pxref{Addressing Modes}).
807 @defun address_operand
808 This predicate is a little unusual; it allows any operand that is a
809 valid expression for the @emph{address} of a quantity of mode
810 @var{mode}, again determined by the weak form of
811 @code{GO_IF_LEGITIMATE_ADDRESS}. To first order, if
812 @samp{@w{(mem:@var{mode} (@var{exp}))}} is acceptable to
813 @code{memory_operand}, then @var{exp} is acceptable to
814 @code{address_operand}. Note that @var{exp} does not necessarily have
818 @defun indirect_operand
819 This is a stricter form of @code{memory_operand} which allows only
820 memory references with a @code{general_operand} as the address
821 expression. New uses of this predicate are discouraged, because
822 @code{general_operand} is very permissive, so it's hard to tell what
823 an @code{indirect_operand} does or does not allow. If a target has
824 different requirements for memory operands for different instructions,
825 it is better to define target-specific predicates which enforce the
826 hardware's requirements explicitly.
830 This predicate allows a memory reference suitable for pushing a value
831 onto the stack. This will be a @code{MEM} which refers to
832 @code{stack_pointer_rtx}, with a side-effect in its address expression
833 (@pxref{Incdec}); which one is determined by the
834 @code{STACK_PUSH_CODE} macro (@pxref{Frame Layout}).
838 This predicate allows a memory reference suitable for popping a value
839 off the stack. Again, this will be a @code{MEM} referring to
840 @code{stack_pointer_rtx}, with a side-effect in its address
841 expression. However, this time @code{STACK_POP_CODE} is expected.
845 The fourth category of predicates allow some combination of the above
848 @defun nonmemory_operand
849 This predicate allows any immediate or register operand valid for @var{mode}.
852 @defun nonimmediate_operand
853 This predicate allows any register or memory operand valid for @var{mode}.
856 @defun general_operand
857 This predicate allows any immediate, register, or memory operand
858 valid for @var{mode}.
862 Finally, there is one generic operator predicate.
864 @defun comparison_operator
865 This predicate matches any expression which performs an arithmetic
866 comparison in @var{mode}; that is, @code{COMPARISON_P} is true for the
870 @node Defining Predicates
871 @subsection Defining Machine-Specific Predicates
872 @cindex defining predicates
873 @findex define_predicate
874 @findex define_special_predicate
876 Many machines have requirements for their operands that cannot be
877 expressed precisely using the generic predicates. You can define
878 additional predicates using @code{define_predicate} and
879 @code{define_special_predicate} expressions. These expressions have
884 The name of the predicate, as it will be referred to in
885 @code{match_operand} or @code{match_operator} expressions.
888 An RTL expression which evaluates to true if the predicate allows the
889 operand @var{op}, false if it does not. This expression can only use
890 the following RTL codes:
894 When written inside a predicate expression, a @code{MATCH_OPERAND}
895 expression evaluates to true if the predicate it names would allow
896 @var{op}. The operand number and constraint are ignored. Due to
897 limitations in @command{genrecog}, you can only refer to generic
898 predicates and predicates that have already been defined.
901 This expression has one operand, a string constant containing a
902 comma-separated list of RTX code names (in lower case). It evaluates
903 to true if @var{op} has any of the listed codes.
906 This expression has one operand, a string constant containing a C
907 expression. The predicate's arguments, @var{op} and @var{mode}, are
908 available with those names in the C expression. The @code{MATCH_TEST}
909 evaluates to true if the C expression evaluates to a nonzero value.
910 @code{MATCH_TEST} expressions must not have side effects.
916 The basic @samp{MATCH_} expressions can be combined using these
917 logical operators, which have the semantics of the C operators
918 @samp{&&}, @samp{||}, @samp{!}, and @samp{@w{? :}} respectively.
922 An optional block of C code, which should execute
923 @samp{@w{return true}} if the predicate is found to match and
924 @samp{@w{return false}} if it does not. It must not have any side
925 effects. The predicate arguments, @var{op} and @var{mode}, are
926 available with those names.
928 If a code block is present in a predicate definition, then the RTL
929 expression must evaluate to true @emph{and} the code block must
930 execute @samp{@w{return true}} for the predicate to allow the operand.
931 The RTL expression is evaluated first; do not re-check anything in the
932 code block that was checked in the RTL expression.
935 The program @command{genrecog} scans @code{define_predicate} and
936 @code{define_special_predicate} expressions to determine which RTX
937 codes are possibly allowed. You should always make this explicit in
938 the RTL predicate expression, using @code{MATCH_OPERAND} and
941 Here is an example of a simple predicate definition, from the IA64
946 ;; @r{True if @var{op} is a @code{SYMBOL_REF} which refers to the sdata section.}
947 (define_predicate "small_addr_symbolic_operand"
948 (and (match_code "symbol_ref")
949 (match_test "SYMBOL_REF_SMALL_ADDR_P (op)")))
954 And here is another, showing the use of the C block.
958 ;; @r{True if @var{op} is a register operand that is (or could be) a GR reg.}
959 (define_predicate "gr_register_operand"
960 (match_operand 0 "register_operand")
963 if (GET_CODE (op) == SUBREG)
964 op = SUBREG_REG (op);
967 return (regno >= FIRST_PSEUDO_REGISTER || GENERAL_REGNO_P (regno));
972 Predicates written with @code{define_predicate} automatically include
973 a test that @var{mode} is @code{VOIDmode}, or @var{op} has the same
974 mode as @var{mode}, or @var{op} is a @code{CONST_INT} or
975 @code{CONST_DOUBLE}. They do @emph{not} check specifically for
976 integer @code{CONST_DOUBLE}, nor do they test that the value of either
977 kind of constant fits in the requested mode. This is because
978 target-specific predicates that take constants usually have to do more
979 stringent value checks anyway. If you need the exact same treatment
980 of @code{CONST_INT} or @code{CONST_DOUBLE} that the generic predicates
981 provide, use a @code{MATCH_OPERAND} subexpression to call
982 @code{const_int_operand}, @code{const_double_operand}, or
983 @code{immediate_operand}.
985 Predicates written with @code{define_special_predicate} do not get any
986 automatic mode checks, and are treated as having special mode handling
987 by @command{genrecog}.
989 The program @command{genpreds} is responsible for generating code to
990 test predicates. It also writes a header file containing function
991 declarations for all machine-specific predicates. It is not necessary
992 to declare these predicates in @file{@var{cpu}-protos.h}.
995 @c Most of this node appears by itself (in a different place) even
996 @c when the INTERNALS flag is clear. Passages that require the internals
997 @c manual's context are conditionalized to appear only in the internals manual.
1000 @section Operand Constraints
1001 @cindex operand constraints
1004 Each @code{match_operand} in an instruction pattern can specify
1005 constraints for the operands allowed. The constraints allow you to
1006 fine-tune matching within the set of operands allowed by the
1012 @section Constraints for @code{asm} Operands
1013 @cindex operand constraints, @code{asm}
1014 @cindex constraints, @code{asm}
1015 @cindex @code{asm} constraints
1017 Here are specific details on what constraint letters you can use with
1018 @code{asm} operands.
1020 Constraints can say whether
1021 an operand may be in a register, and which kinds of register; whether the
1022 operand can be a memory reference, and which kinds of address; whether the
1023 operand may be an immediate constant, and which possible values it may
1024 have. Constraints can also require two operands to match.
1028 * Simple Constraints:: Basic use of constraints.
1029 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1030 * Class Preferences:: Constraints guide which hard register to put things in.
1031 * Modifiers:: More precise control over effects of constraints.
1032 * Machine Constraints:: Existing constraints for some particular machines.
1038 * Simple Constraints:: Basic use of constraints.
1039 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1040 * Modifiers:: More precise control over effects of constraints.
1041 * Machine Constraints:: Special constraints for some particular machines.
1045 @node Simple Constraints
1046 @subsection Simple Constraints
1047 @cindex simple constraints
1049 The simplest kind of constraint is a string full of letters, each of
1050 which describes one kind of operand that is permitted. Here are
1051 the letters that are allowed:
1055 Whitespace characters are ignored and can be inserted at any position
1056 except the first. This enables each alternative for different operands to
1057 be visually aligned in the machine description even if they have different
1058 number of constraints and modifiers.
1060 @cindex @samp{m} in constraint
1061 @cindex memory references in constraints
1063 A memory operand is allowed, with any kind of address that the machine
1064 supports in general.
1066 @cindex offsettable address
1067 @cindex @samp{o} in constraint
1069 A memory operand is allowed, but only if the address is
1070 @dfn{offsettable}. This means that adding a small integer (actually,
1071 the width in bytes of the operand, as determined by its machine mode)
1072 may be added to the address and the result is also a valid memory
1075 @cindex autoincrement/decrement addressing
1076 For example, an address which is constant is offsettable; so is an
1077 address that is the sum of a register and a constant (as long as a
1078 slightly larger constant is also within the range of address-offsets
1079 supported by the machine); but an autoincrement or autodecrement
1080 address is not offsettable. More complicated indirect/indexed
1081 addresses may or may not be offsettable depending on the other
1082 addressing modes that the machine supports.
1084 Note that in an output operand which can be matched by another
1085 operand, the constraint letter @samp{o} is valid only when accompanied
1086 by both @samp{<} (if the target machine has predecrement addressing)
1087 and @samp{>} (if the target machine has preincrement addressing).
1089 @cindex @samp{V} in constraint
1091 A memory operand that is not offsettable. In other words, anything that
1092 would fit the @samp{m} constraint but not the @samp{o} constraint.
1094 @cindex @samp{<} in constraint
1096 A memory operand with autodecrement addressing (either predecrement or
1097 postdecrement) is allowed.
1099 @cindex @samp{>} in constraint
1101 A memory operand with autoincrement addressing (either preincrement or
1102 postincrement) is allowed.
1104 @cindex @samp{r} in constraint
1105 @cindex registers in constraints
1107 A register operand is allowed provided that it is in a general
1110 @cindex constants in constraints
1111 @cindex @samp{i} in constraint
1113 An immediate integer operand (one with constant value) is allowed.
1114 This includes symbolic constants whose values will be known only at
1115 assembly time or later.
1117 @cindex @samp{n} in constraint
1119 An immediate integer operand with a known numeric value is allowed.
1120 Many systems cannot support assembly-time constants for operands less
1121 than a word wide. Constraints for these operands should use @samp{n}
1122 rather than @samp{i}.
1124 @cindex @samp{I} in constraint
1125 @item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P}
1126 Other letters in the range @samp{I} through @samp{P} may be defined in
1127 a machine-dependent fashion to permit immediate integer operands with
1128 explicit integer values in specified ranges. For example, on the
1129 68000, @samp{I} is defined to stand for the range of values 1 to 8.
1130 This is the range permitted as a shift count in the shift
1133 @cindex @samp{E} in constraint
1135 An immediate floating operand (expression code @code{const_double}) is
1136 allowed, but only if the target floating point format is the same as
1137 that of the host machine (on which the compiler is running).
1139 @cindex @samp{F} in constraint
1141 An immediate floating operand (expression code @code{const_double} or
1142 @code{const_vector}) is allowed.
1144 @cindex @samp{G} in constraint
1145 @cindex @samp{H} in constraint
1146 @item @samp{G}, @samp{H}
1147 @samp{G} and @samp{H} may be defined in a machine-dependent fashion to
1148 permit immediate floating operands in particular ranges of values.
1150 @cindex @samp{s} in constraint
1152 An immediate integer operand whose value is not an explicit integer is
1155 This might appear strange; if an insn allows a constant operand with a
1156 value not known at compile time, it certainly must allow any known
1157 value. So why use @samp{s} instead of @samp{i}? Sometimes it allows
1158 better code to be generated.
1160 For example, on the 68000 in a fullword instruction it is possible to
1161 use an immediate operand; but if the immediate value is between @minus{}128
1162 and 127, better code results from loading the value into a register and
1163 using the register. This is because the load into the register can be
1164 done with a @samp{moveq} instruction. We arrange for this to happen
1165 by defining the letter @samp{K} to mean ``any integer outside the
1166 range @minus{}128 to 127'', and then specifying @samp{Ks} in the operand
1169 @cindex @samp{g} in constraint
1171 Any register, memory or immediate integer operand is allowed, except for
1172 registers that are not general registers.
1174 @cindex @samp{X} in constraint
1177 Any operand whatsoever is allowed, even if it does not satisfy
1178 @code{general_operand}. This is normally used in the constraint of
1179 a @code{match_scratch} when certain alternatives will not actually
1180 require a scratch register.
1183 Any operand whatsoever is allowed.
1186 @cindex @samp{0} in constraint
1187 @cindex digits in constraint
1188 @item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9}
1189 An operand that matches the specified operand number is allowed. If a
1190 digit is used together with letters within the same alternative, the
1191 digit should come last.
1193 This number is allowed to be more than a single digit. If multiple
1194 digits are encountered consecutively, they are interpreted as a single
1195 decimal integer. There is scant chance for ambiguity, since to-date
1196 it has never been desirable that @samp{10} be interpreted as matching
1197 either operand 1 @emph{or} operand 0. Should this be desired, one
1198 can use multiple alternatives instead.
1200 @cindex matching constraint
1201 @cindex constraint, matching
1202 This is called a @dfn{matching constraint} and what it really means is
1203 that the assembler has only a single operand that fills two roles
1205 considered separate in the RTL insn. For example, an add insn has two
1206 input operands and one output operand in the RTL, but on most CISC
1209 which @code{asm} distinguishes. For example, an add instruction uses
1210 two input operands and an output operand, but on most CISC
1212 machines an add instruction really has only two operands, one of them an
1213 input-output operand:
1219 Matching constraints are used in these circumstances.
1220 More precisely, the two operands that match must include one input-only
1221 operand and one output-only operand. Moreover, the digit must be a
1222 smaller number than the number of the operand that uses it in the
1226 For operands to match in a particular case usually means that they
1227 are identical-looking RTL expressions. But in a few special cases
1228 specific kinds of dissimilarity are allowed. For example, @code{*x}
1229 as an input operand will match @code{*x++} as an output operand.
1230 For proper results in such cases, the output template should always
1231 use the output-operand's number when printing the operand.
1234 @cindex load address instruction
1235 @cindex push address instruction
1236 @cindex address constraints
1237 @cindex @samp{p} in constraint
1239 An operand that is a valid memory address is allowed. This is
1240 for ``load address'' and ``push address'' instructions.
1242 @findex address_operand
1243 @samp{p} in the constraint must be accompanied by @code{address_operand}
1244 as the predicate in the @code{match_operand}. This predicate interprets
1245 the mode specified in the @code{match_operand} as the mode of the memory
1246 reference for which the address would be valid.
1248 @cindex other register constraints
1249 @cindex extensible constraints
1250 @item @var{other-letters}
1251 Other letters can be defined in machine-dependent fashion to stand for
1252 particular classes of registers or other arbitrary operand types.
1253 @samp{d}, @samp{a} and @samp{f} are defined on the 68000/68020 to stand
1254 for data, address and floating point registers.
1257 The machine description macro @code{REG_CLASS_FROM_LETTER} has first
1258 cut at the otherwise unused letters. If it evaluates to @code{NO_REGS},
1259 then @code{EXTRA_CONSTRAINT} is evaluated.
1261 A typical use for @code{EXTRA_CONSTRAINT} would be to distinguish certain
1262 types of memory references that affect other insn operands.
1267 In order to have valid assembler code, each operand must satisfy
1268 its constraint. But a failure to do so does not prevent the pattern
1269 from applying to an insn. Instead, it directs the compiler to modify
1270 the code so that the constraint will be satisfied. Usually this is
1271 done by copying an operand into a register.
1273 Contrast, therefore, the two instruction patterns that follow:
1277 [(set (match_operand:SI 0 "general_operand" "=r")
1278 (plus:SI (match_dup 0)
1279 (match_operand:SI 1 "general_operand" "r")))]
1285 which has two operands, one of which must appear in two places, and
1289 [(set (match_operand:SI 0 "general_operand" "=r")
1290 (plus:SI (match_operand:SI 1 "general_operand" "0")
1291 (match_operand:SI 2 "general_operand" "r")))]
1297 which has three operands, two of which are required by a constraint to be
1298 identical. If we are considering an insn of the form
1301 (insn @var{n} @var{prev} @var{next}
1303 (plus:SI (reg:SI 6) (reg:SI 109)))
1308 the first pattern would not apply at all, because this insn does not
1309 contain two identical subexpressions in the right place. The pattern would
1310 say, ``That does not look like an add instruction; try other patterns''.
1311 The second pattern would say, ``Yes, that's an add instruction, but there
1312 is something wrong with it''. It would direct the reload pass of the
1313 compiler to generate additional insns to make the constraint true. The
1314 results might look like this:
1317 (insn @var{n2} @var{prev} @var{n}
1318 (set (reg:SI 3) (reg:SI 6))
1321 (insn @var{n} @var{n2} @var{next}
1323 (plus:SI (reg:SI 3) (reg:SI 109)))
1327 It is up to you to make sure that each operand, in each pattern, has
1328 constraints that can handle any RTL expression that could be present for
1329 that operand. (When multiple alternatives are in use, each pattern must,
1330 for each possible combination of operand expressions, have at least one
1331 alternative which can handle that combination of operands.) The
1332 constraints don't need to @emph{allow} any possible operand---when this is
1333 the case, they do not constrain---but they must at least point the way to
1334 reloading any possible operand so that it will fit.
1338 If the constraint accepts whatever operands the predicate permits,
1339 there is no problem: reloading is never necessary for this operand.
1341 For example, an operand whose constraints permit everything except
1342 registers is safe provided its predicate rejects registers.
1344 An operand whose predicate accepts only constant values is safe
1345 provided its constraints include the letter @samp{i}. If any possible
1346 constant value is accepted, then nothing less than @samp{i} will do;
1347 if the predicate is more selective, then the constraints may also be
1351 Any operand expression can be reloaded by copying it into a register.
1352 So if an operand's constraints allow some kind of register, it is
1353 certain to be safe. It need not permit all classes of registers; the
1354 compiler knows how to copy a register into another register of the
1355 proper class in order to make an instruction valid.
1357 @cindex nonoffsettable memory reference
1358 @cindex memory reference, nonoffsettable
1360 A nonoffsettable memory reference can be reloaded by copying the
1361 address into a register. So if the constraint uses the letter
1362 @samp{o}, all memory references are taken care of.
1365 A constant operand can be reloaded by allocating space in memory to
1366 hold it as preinitialized data. Then the memory reference can be used
1367 in place of the constant. So if the constraint uses the letters
1368 @samp{o} or @samp{m}, constant operands are not a problem.
1371 If the constraint permits a constant and a pseudo register used in an insn
1372 was not allocated to a hard register and is equivalent to a constant,
1373 the register will be replaced with the constant. If the predicate does
1374 not permit a constant and the insn is re-recognized for some reason, the
1375 compiler will crash. Thus the predicate must always recognize any
1376 objects allowed by the constraint.
1379 If the operand's predicate can recognize registers, but the constraint does
1380 not permit them, it can make the compiler crash. When this operand happens
1381 to be a register, the reload pass will be stymied, because it does not know
1382 how to copy a register temporarily into memory.
1384 If the predicate accepts a unary operator, the constraint applies to the
1385 operand. For example, the MIPS processor at ISA level 3 supports an
1386 instruction which adds two registers in @code{SImode} to produce a
1387 @code{DImode} result, but only if the registers are correctly sign
1388 extended. This predicate for the input operands accepts a
1389 @code{sign_extend} of an @code{SImode} register. Write the constraint
1390 to indicate the type of register that is required for the operand of the
1394 @node Multi-Alternative
1395 @subsection Multiple Alternative Constraints
1396 @cindex multiple alternative constraints
1398 Sometimes a single instruction has multiple alternative sets of possible
1399 operands. For example, on the 68000, a logical-or instruction can combine
1400 register or an immediate value into memory, or it can combine any kind of
1401 operand into a register; but it cannot combine one memory location into
1404 These constraints are represented as multiple alternatives. An alternative
1405 can be described by a series of letters for each operand. The overall
1406 constraint for an operand is made from the letters for this operand
1407 from the first alternative, a comma, the letters for this operand from
1408 the second alternative, a comma, and so on until the last alternative.
1410 Here is how it is done for fullword logical-or on the 68000:
1413 (define_insn "iorsi3"
1414 [(set (match_operand:SI 0 "general_operand" "=m,d")
1415 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
1416 (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
1420 The first alternative has @samp{m} (memory) for operand 0, @samp{0} for
1421 operand 1 (meaning it must match operand 0), and @samp{dKs} for operand
1422 2. The second alternative has @samp{d} (data register) for operand 0,
1423 @samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and
1424 @samp{%} in the constraints apply to all the alternatives; their
1425 meaning is explained in the next section (@pxref{Class Preferences}).
1428 @c FIXME Is this ? and ! stuff of use in asm()? If not, hide unless INTERNAL
1429 If all the operands fit any one alternative, the instruction is valid.
1430 Otherwise, for each alternative, the compiler counts how many instructions
1431 must be added to copy the operands so that that alternative applies.
1432 The alternative requiring the least copying is chosen. If two alternatives
1433 need the same amount of copying, the one that comes first is chosen.
1434 These choices can be altered with the @samp{?} and @samp{!} characters:
1437 @cindex @samp{?} in constraint
1438 @cindex question mark
1440 Disparage slightly the alternative that the @samp{?} appears in,
1441 as a choice when no alternative applies exactly. The compiler regards
1442 this alternative as one unit more costly for each @samp{?} that appears
1445 @cindex @samp{!} in constraint
1446 @cindex exclamation point
1448 Disparage severely the alternative that the @samp{!} appears in.
1449 This alternative can still be used if it fits without reloading,
1450 but if reloading is needed, some other alternative will be used.
1454 When an insn pattern has multiple alternatives in its constraints, often
1455 the appearance of the assembler code is determined mostly by which
1456 alternative was matched. When this is so, the C code for writing the
1457 assembler code can use the variable @code{which_alternative}, which is
1458 the ordinal number of the alternative that was actually satisfied (0 for
1459 the first, 1 for the second alternative, etc.). @xref{Output Statement}.
1463 @node Class Preferences
1464 @subsection Register Class Preferences
1465 @cindex class preference constraints
1466 @cindex register class preference constraints
1468 @cindex voting between constraint alternatives
1469 The operand constraints have another function: they enable the compiler
1470 to decide which kind of hardware register a pseudo register is best
1471 allocated to. The compiler examines the constraints that apply to the
1472 insns that use the pseudo register, looking for the machine-dependent
1473 letters such as @samp{d} and @samp{a} that specify classes of registers.
1474 The pseudo register is put in whichever class gets the most ``votes''.
1475 The constraint letters @samp{g} and @samp{r} also vote: they vote in
1476 favor of a general register. The machine description says which registers
1477 are considered general.
1479 Of course, on some machines all registers are equivalent, and no register
1480 classes are defined. Then none of this complexity is relevant.
1484 @subsection Constraint Modifier Characters
1485 @cindex modifiers in constraints
1486 @cindex constraint modifier characters
1488 @c prevent bad page break with this line
1489 Here are constraint modifier characters.
1492 @cindex @samp{=} in constraint
1494 Means that this operand is write-only for this instruction: the previous
1495 value is discarded and replaced by output data.
1497 @cindex @samp{+} in constraint
1499 Means that this operand is both read and written by the instruction.
1501 When the compiler fixes up the operands to satisfy the constraints,
1502 it needs to know which operands are inputs to the instruction and
1503 which are outputs from it. @samp{=} identifies an output; @samp{+}
1504 identifies an operand that is both input and output; all other operands
1505 are assumed to be input only.
1507 If you specify @samp{=} or @samp{+} in a constraint, you put it in the
1508 first character of the constraint string.
1510 @cindex @samp{&} in constraint
1511 @cindex earlyclobber operand
1513 Means (in a particular alternative) that this operand is an
1514 @dfn{earlyclobber} operand, which is modified before the instruction is
1515 finished using the input operands. Therefore, this operand may not lie
1516 in a register that is used as an input operand or as part of any memory
1519 @samp{&} applies only to the alternative in which it is written. In
1520 constraints with multiple alternatives, sometimes one alternative
1521 requires @samp{&} while others do not. See, for example, the
1522 @samp{movdf} insn of the 68000.
1524 An input operand can be tied to an earlyclobber operand if its only
1525 use as an input occurs before the early result is written. Adding
1526 alternatives of this form often allows GCC to produce better code
1527 when only some of the inputs can be affected by the earlyclobber.
1528 See, for example, the @samp{mulsi3} insn of the ARM@.
1530 @samp{&} does not obviate the need to write @samp{=}.
1532 @cindex @samp{%} in constraint
1534 Declares the instruction to be commutative for this operand and the
1535 following operand. This means that the compiler may interchange the
1536 two operands if that is the cheapest way to make all operands fit the
1539 This is often used in patterns for addition instructions
1540 that really have only two operands: the result must go in one of the
1541 arguments. Here for example, is how the 68000 halfword-add
1542 instruction is defined:
1545 (define_insn "addhi3"
1546 [(set (match_operand:HI 0 "general_operand" "=m,r")
1547 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
1548 (match_operand:HI 2 "general_operand" "di,g")))]
1552 GCC can only handle one commutative pair in an asm; if you use more,
1553 the compiler may fail. Note that you need not use the modifier if
1554 the two alternatives are strictly identical; this would only waste
1555 time in the reload pass.
1557 @cindex @samp{#} in constraint
1559 Says that all following characters, up to the next comma, are to be
1560 ignored as a constraint. They are significant only for choosing
1561 register preferences.
1563 @cindex @samp{*} in constraint
1565 Says that the following character should be ignored when choosing
1566 register preferences. @samp{*} has no effect on the meaning of the
1567 constraint as a constraint, and no effect on reloading.
1570 Here is an example: the 68000 has an instruction to sign-extend a
1571 halfword in a data register, and can also sign-extend a value by
1572 copying it into an address register. While either kind of register is
1573 acceptable, the constraints on an address-register destination are
1574 less strict, so it is best if register allocation makes an address
1575 register its goal. Therefore, @samp{*} is used so that the @samp{d}
1576 constraint letter (for data register) is ignored when computing
1577 register preferences.
1580 (define_insn "extendhisi2"
1581 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1583 (match_operand:HI 1 "general_operand" "0,g")))]
1589 @node Machine Constraints
1590 @subsection Constraints for Particular Machines
1591 @cindex machine specific constraints
1592 @cindex constraints, machine specific
1594 Whenever possible, you should use the general-purpose constraint letters
1595 in @code{asm} arguments, since they will convey meaning more readily to
1596 people reading your code. Failing that, use the constraint letters
1597 that usually have very similar meanings across architectures. The most
1598 commonly used constraints are @samp{m} and @samp{r} (for memory and
1599 general-purpose registers respectively; @pxref{Simple Constraints}), and
1600 @samp{I}, usually the letter indicating the most common
1601 immediate-constant format.
1603 For each machine architecture, the
1604 @file{config/@var{machine}/@var{machine}.h} file defines additional
1605 constraints. These constraints are used by the compiler itself for
1606 instruction generation, as well as for @code{asm} statements; therefore,
1607 some of the constraints are not particularly interesting for @code{asm}.
1608 The constraints are defined through these macros:
1611 @item REG_CLASS_FROM_LETTER
1612 Register class constraints (usually lowercase).
1614 @item CONST_OK_FOR_LETTER_P
1615 Immediate constant constraints, for non-floating point constants of
1616 word size or smaller precision (usually uppercase).
1618 @item CONST_DOUBLE_OK_FOR_LETTER_P
1619 Immediate constant constraints, for all floating point constants and for
1620 constants of greater than word size precision (usually uppercase).
1622 @item EXTRA_CONSTRAINT
1623 Special cases of registers or memory. This macro is not required, and
1624 is only defined for some machines.
1627 Inspecting these macro definitions in the compiler source for your
1628 machine is the best way to be certain you have the right constraints.
1629 However, here is a summary of the machine-dependent constraints
1630 available on some particular machines.
1633 @item ARM family---@file{arm.h}
1636 Floating-point register
1639 VFP floating-point register
1642 One of the floating-point constants 0.0, 0.5, 1.0, 2.0, 3.0, 4.0, 5.0
1646 Floating-point constant that would satisfy the constraint @samp{F} if it
1650 Integer that is valid as an immediate operand in a data processing
1651 instruction. That is, an integer in the range 0 to 255 rotated by a
1655 Integer in the range @minus{}4095 to 4095
1658 Integer that satisfies constraint @samp{I} when inverted (ones complement)
1661 Integer that satisfies constraint @samp{I} when negated (twos complement)
1664 Integer in the range 0 to 32
1667 A memory reference where the exact address is in a single register
1668 (`@samp{m}' is preferable for @code{asm} statements)
1671 An item in the constant pool
1674 A symbol in the text segment of the current file
1678 A memory reference suitable for VFP load/store insns (reg+constant offset)
1681 A memory reference suitable for iWMMXt load/store instructions.
1684 A memory reference suitable for the ARMv4 ldrsb instruction.
1686 @item AVR family---@file{avr.h}
1689 Registers from r0 to r15
1692 Registers from r16 to r23
1695 Registers from r16 to r31
1698 Registers from r24 to r31. These registers can be used in @samp{adiw} command
1701 Pointer register (r26--r31)
1704 Base pointer register (r28--r31)
1707 Stack pointer register (SPH:SPL)
1710 Temporary register r0
1713 Register pair X (r27:r26)
1716 Register pair Y (r29:r28)
1719 Register pair Z (r31:r30)
1722 Constant greater than @minus{}1, less than 64
1725 Constant greater than @minus{}64, less than 1
1734 Constant that fits in 8 bits
1737 Constant integer @minus{}1
1740 Constant integer 8, 16, or 24
1746 A floating point constant 0.0
1749 @item PowerPC and IBM RS6000---@file{rs6000.h}
1752 Address base register
1755 Floating point register
1761 @samp{MQ}, @samp{CTR}, or @samp{LINK} register
1770 @samp{LINK} register
1773 @samp{CR} register (condition register) number 0
1776 @samp{CR} register (condition register)
1779 @samp{FPMEM} stack memory for FPR-GPR transfers
1782 Signed 16-bit constant
1785 Unsigned 16-bit constant shifted left 16 bits (use @samp{L} instead for
1786 @code{SImode} constants)
1789 Unsigned 16-bit constant
1792 Signed 16-bit constant shifted left 16 bits
1795 Constant larger than 31
1804 Constant whose negation is a signed 16-bit constant
1807 Floating point constant that can be loaded into a register with one
1808 instruction per word
1811 Memory operand that is an offset from a register (@samp{m} is preferable
1812 for @code{asm} statements)
1818 Constant suitable as a 64-bit mask operand
1821 Constant suitable as a 32-bit mask operand
1824 System V Release 4 small data area reference
1827 @item Intel 386---@file{i386.h}
1830 @samp{a}, @code{b}, @code{c}, or @code{d} register for the i386.
1831 For x86-64 it is equivalent to @samp{r} class (for 8-bit instructions that
1832 do not use upper halves).
1835 @samp{a}, @code{b}, @code{c}, or @code{d} register (for 8-bit instructions,
1836 that do use upper halves).
1839 Legacy register---equivalent to @code{r} class in i386 mode.
1840 (for non-8-bit registers used together with 8-bit upper halves in a single
1844 Specifies the @samp{a} or @samp{d} registers. This is primarily useful
1845 for 64-bit integer values (when in 32-bit mode) intended to be returned
1846 with the @samp{d} register holding the most significant bits and the
1847 @samp{a} register holding the least significant bits.
1850 Floating point register
1853 First (top of stack) floating point register
1856 Second floating point register
1868 Specifies constant that can be easily constructed in SSE register without
1869 loading it from memory.
1881 @samp{xmm} SSE register
1887 Constant in range 0 to 31 (for 32-bit shifts)
1890 Constant in range 0 to 63 (for 64-bit shifts)
1899 0, 1, 2, or 3 (shifts for @code{lea} instruction)
1902 Constant in range 0 to 255 (for @code{out} instruction)
1905 Constant in range 0 to @code{0xffffffff} or symbolic reference known to fit specified range.
1906 (for using immediates in zero extending 32-bit to 64-bit x86-64 instructions)
1909 Constant in range @minus{}2147483648 to 2147483647 or symbolic reference known to fit specified range.
1910 (for using immediates in 64-bit x86-64 instructions)
1913 Standard 80387 floating point constant
1916 @item Intel IA-64---@file{ia64.h}
1919 General register @code{r0} to @code{r3} for @code{addl} instruction
1925 Predicate register (@samp{c} as in ``conditional'')
1928 Application register residing in M-unit
1931 Application register residing in I-unit
1934 Floating-point register
1938 Remember that @samp{m} allows postincrement and postdecrement which
1939 require printing with @samp{%Pn} on IA-64.
1940 Use @samp{S} to disallow postincrement and postdecrement.
1943 Floating-point constant 0.0 or 1.0
1946 14-bit signed integer constant
1949 22-bit signed integer constant
1952 8-bit signed integer constant for logical instructions
1955 8-bit adjusted signed integer constant for compare pseudo-ops
1958 6-bit unsigned integer constant for shift counts
1961 9-bit signed integer constant for load and store postincrements
1967 0 or @minus{}1 for @code{dep} instruction
1970 Non-volatile memory for floating-point loads and stores
1973 Integer constant in the range 1 to 4 for @code{shladd} instruction
1976 Memory operand except postincrement and postdecrement
1979 @item FRV---@file{frv.h}
1982 Register in the class @code{ACC_REGS} (@code{acc0} to @code{acc7}).
1985 Register in the class @code{EVEN_ACC_REGS} (@code{acc0} to @code{acc7}).
1988 Register in the class @code{CC_REGS} (@code{fcc0} to @code{fcc3} and
1989 @code{icc0} to @code{icc3}).
1992 Register in the class @code{GPR_REGS} (@code{gr0} to @code{gr63}).
1995 Register in the class @code{EVEN_REGS} (@code{gr0} to @code{gr63}).
1996 Odd registers are excluded not in the class but through the use of a machine
1997 mode larger than 4 bytes.
2000 Register in the class @code{FPR_REGS} (@code{fr0} to @code{fr63}).
2003 Register in the class @code{FEVEN_REGS} (@code{fr0} to @code{fr63}).
2004 Odd registers are excluded not in the class but through the use of a machine
2005 mode larger than 4 bytes.
2008 Register in the class @code{LR_REG} (the @code{lr} register).
2011 Register in the class @code{QUAD_REGS} (@code{gr2} to @code{gr63}).
2012 Register numbers not divisible by 4 are excluded not in the class but through
2013 the use of a machine mode larger than 8 bytes.
2016 Register in the class @code{ICC_REGS} (@code{icc0} to @code{icc3}).
2019 Register in the class @code{FCC_REGS} (@code{fcc0} to @code{fcc3}).
2022 Register in the class @code{ICR_REGS} (@code{cc4} to @code{cc7}).
2025 Register in the class @code{FCR_REGS} (@code{cc0} to @code{cc3}).
2028 Register in the class @code{QUAD_FPR_REGS} (@code{fr0} to @code{fr63}).
2029 Register numbers not divisible by 4 are excluded not in the class but through
2030 the use of a machine mode larger than 8 bytes.
2033 Register in the class @code{SPR_REGS} (@code{lcr} and @code{lr}).
2036 Register in the class @code{QUAD_ACC_REGS} (@code{acc0} to @code{acc7}).
2039 Register in the class @code{ACCG_REGS} (@code{accg0} to @code{accg7}).
2042 Register in the class @code{CR_REGS} (@code{cc0} to @code{cc7}).
2045 Floating point constant zero
2048 6-bit signed integer constant
2051 10-bit signed integer constant
2054 16-bit signed integer constant
2057 16-bit unsigned integer constant
2060 12-bit signed integer constant that is negative---i.e.@: in the
2061 range of @minus{}2048 to @minus{}1
2067 12-bit signed integer constant that is greater than zero---i.e.@: in the
2072 @item Blackfin family---@file{bfin.h}
2081 A call clobbered P register.
2084 Even-numbered D register
2087 Odd-numbered D register
2090 Accumulator register.
2093 Even-numbered accumulator register.
2096 Odd-numbered accumulator register.
2108 Registers used for circular buffering, i.e. I, B, or L registers.
2114 Any D, P, B, M, I or L register.
2117 Additional registers typically used only in prologues and epilogues: RETS,
2118 RETN, RETI, RETX, RETE, ASTAT, SEQSTAT and USP.
2121 Any register except accumulators or CC.
2124 Signed 16 bit integer (in the range -32768 to 32767)
2127 Unsigned 16 bit integer (in the range 0 to 65535)
2130 Signed 7 bit integer (in the range -64 to 63)
2133 Unsigned 7 bit integer (in the range 0 to 127)
2136 Unsigned 5 bit integer (in the range 0 to 31)
2139 Signed 4 bit integer (in the range -8 to 7)
2142 Signed 3 bit integer (in the range -3 to 4)
2145 Unsigned 3 bit integer (in the range 0 to 7)
2148 Constant @var{n}, where @var{n} is a single-digit constant in the range 0 to 4.
2157 An integer constant with exactly a single bit set.
2160 An integer constant with all bits set except exactly one.
2168 @item M32C---@file{m32c.c}
2173 @samp{$sp}, @samp{$fb}, @samp{$sb}.
2176 Any control register, when they're 16 bits wide (nothing if control
2177 registers are 24 bits wide)
2180 Any control register, when they're 24 bits wide.
2189 $r0 or $r2, or $r2r0 for 32 bit values.
2192 $r1 or $r3, or $r3r1 for 32 bit values.
2195 A register that can hold a 64 bit value.
2198 $r0 or $r1 (registers with addressable high/low bytes)
2207 Address registers when they're 16 bits wide.
2210 Address registers when they're 24 bits wide.
2213 Registers that can hold QI values.
2216 Registers that can be used with displacements ($a0, $a1, $sb).
2219 Registers that can hold 32 bit values.
2222 Registers that can hold 16 bit values.
2225 Registers chat can hold 16 bit values, including all control
2229 $r0 through R1, plus $a0 and $a1.
2235 The memory-based pseudo-registers $mem0 through $mem15.
2238 Registers that can hold pointers (16 bit registers for r8c, m16c; 24
2239 bit registers for m32cm, m32c).
2242 Matches multiple registers in a PARALLEL to form a larger register.
2243 Used to match function return values.
2252 -32768 @dots{} 32767
2258 -8 @dots{} -1 or 1 @dots{} 8
2261 -16 @dots{} -1 or 1 @dots{} 16
2264 -8 @dots{} -1 or 1 @dots{} 8
2270 An 8 bit value with exactly one bit set.
2273 A 16 bit value with exactly one bit set.
2276 The common src/dest memory addressing modes.
2279 Memory addressed using $a0 or $a1.
2282 Memory addressed with immediate addresses.
2285 Memory addressed using the stack pointer ($sp).
2288 Memory addressed using the frame base register ($fb).
2291 Memory addressed using the small base register ($sb).
2297 @item MIPS---@file{mips.h}
2300 General-purpose integer register
2303 Floating-point register (if available)
2312 @samp{Hi} or @samp{Lo} register
2315 General-purpose integer register
2318 Floating-point status register
2321 Signed 16-bit constant (for arithmetic instructions)
2327 Zero-extended 16-bit constant (for logic instructions)
2330 Constant with low 16 bits zero (can be loaded with @code{lui})
2333 32-bit constant which requires two instructions to load (a constant
2334 which is not @samp{I}, @samp{K}, or @samp{L})
2337 Negative 16-bit constant
2343 Positive 16-bit constant
2349 Memory reference that can be loaded with more than one instruction
2350 (@samp{m} is preferable for @code{asm} statements)
2353 Memory reference that can be loaded with one instruction
2354 (@samp{m} is preferable for @code{asm} statements)
2357 Memory reference in external OSF/rose PIC format
2358 (@samp{m} is preferable for @code{asm} statements)
2361 @item Motorola 680x0---@file{m68k.h}
2370 68881 floating-point register, if available
2373 Integer in the range 1 to 8
2376 16-bit signed number
2379 Signed number whose magnitude is greater than 0x80
2382 Integer in the range @minus{}8 to @minus{}1
2385 Signed number whose magnitude is greater than 0x100
2388 Floating point constant that is not a 68881 constant
2391 @item Motorola 68HC11 & 68HC12 families---@file{m68hc11.h}
2406 Temporary soft register _.tmp
2409 A soft register _.d1 to _.d31
2412 Stack pointer register
2421 Pseudo register `z' (replaced by `x' or `y' at the end)
2424 An address register: x, y or z
2427 An address register: x or y
2430 Register pair (x:d) to form a 32-bit value
2433 Constants in the range @minus{}65536 to 65535
2436 Constants whose 16-bit low part is zero
2439 Constant integer 1 or @minus{}1
2445 Constants in the range @minus{}8 to 2
2450 @item SPARC---@file{sparc.h}
2453 Floating-point register on the SPARC-V8 architecture and
2454 lower floating-point register on the SPARC-V9 architecture.
2457 Floating-point register. It is equivalent to @samp{f} on the
2458 SPARC-V8 architecture and contains both lower and upper
2459 floating-point registers on the SPARC-V9 architecture.
2462 Floating-point condition code register.
2465 Lower floating-point register. It is only valid on the SPARC-V9
2466 architecture when the Visual Instruction Set is available.
2469 Floating-point register. It is only valid on the SPARC-V9 architecture
2470 when the Visual Instruction Set is available.
2473 64-bit global or out register for the SPARC-V8+ architecture.
2476 Signed 13-bit constant
2482 32-bit constant with the low 12 bits clear (a constant that can be
2483 loaded with the @code{sethi} instruction)
2486 A constant in the range supported by @code{movcc} instructions
2489 A constant in the range supported by @code{movrcc} instructions
2492 Same as @samp{K}, except that it verifies that bits that are not in the
2493 lower 32-bit range are all zero. Must be used instead of @samp{K} for
2494 modes wider than @code{SImode}
2503 Signed 13-bit constant, sign-extended to 32 or 64 bits
2506 Floating-point constant whose integral representation can
2507 be moved into an integer register using a single sethi
2511 Floating-point constant whose integral representation can
2512 be moved into an integer register using a single mov
2516 Floating-point constant whose integral representation can
2517 be moved into an integer register using a high/lo_sum
2518 instruction sequence
2521 Memory address aligned to an 8-byte boundary
2527 Memory address for @samp{e} constraint registers
2534 @item TMS320C3x/C4x---@file{c4x.h}
2537 Auxiliary (address) register (ar0-ar7)
2540 Stack pointer register (sp)
2543 Standard (32-bit) precision integer register
2546 Extended (40-bit) precision register (r0-r11)
2549 Block count register (bk)
2552 Extended (40-bit) precision low register (r0-r7)
2555 Extended (40-bit) precision register (r0-r1)
2558 Extended (40-bit) precision register (r2-r3)
2561 Repeat count register (rc)
2564 Index register (ir0-ir1)
2567 Status (condition code) register (st)
2570 Data page register (dp)
2576 Immediate 16-bit floating-point constant
2579 Signed 16-bit constant
2582 Signed 8-bit constant
2585 Signed 5-bit constant
2588 Unsigned 16-bit constant
2591 Unsigned 8-bit constant
2594 Ones complement of unsigned 16-bit constant
2597 High 16-bit constant (32-bit constant with 16 LSBs zero)
2600 Indirect memory reference with signed 8-bit or index register displacement
2603 Indirect memory reference with unsigned 5-bit displacement
2606 Indirect memory reference with 1 bit or index register displacement
2609 Direct memory reference
2616 @item S/390 and zSeries---@file{s390.h}
2619 Address register (general purpose register except r0)
2622 Condition code register
2625 Data register (arbitrary general purpose register)
2628 Floating-point register
2631 Unsigned 8-bit constant (0--255)
2634 Unsigned 12-bit constant (0--4095)
2637 Signed 16-bit constant (@minus{}32768--32767)
2640 Value appropriate as displacement.
2643 for short displacement
2644 @item (-524288..524287)
2645 for long displacement
2649 Constant integer with a value of 0x7fffffff.
2652 Multiple letter constraint followed by 4 parameter letters.
2655 number of the part counting from most to least significant
2659 mode of the containing operand
2661 value of the other parts (F---all bits set)
2663 The constraint matches if the specified part of a constant
2664 has a value different from it's other parts.
2667 Memory reference without index register and with short displacement.
2670 Memory reference with index register and short displacement.
2673 Memory reference without index register but with long displacement.
2676 Memory reference with index register and long displacement.
2679 Pointer with short displacement.
2682 Pointer with long displacement.
2685 Shift count operand.
2689 @item Xstormy16---@file{stormy16.h}
2704 Registers r0 through r7.
2707 Registers r0 and r1.
2713 Registers r8 and r9.
2716 A constant between 0 and 3 inclusive.
2719 A constant that has exactly one bit set.
2722 A constant that has exactly one bit clear.
2725 A constant between 0 and 255 inclusive.
2728 A constant between @minus{}255 and 0 inclusive.
2731 A constant between @minus{}3 and 0 inclusive.
2734 A constant between 1 and 4 inclusive.
2737 A constant between @minus{}4 and @minus{}1 inclusive.
2740 A memory reference that is a stack push.
2743 A memory reference that is a stack pop.
2746 A memory reference that refers to a constant address of known value.
2749 The register indicated by Rx (not implemented yet).
2752 A constant that is not between 2 and 15 inclusive.
2759 @item Xtensa---@file{xtensa.h}
2762 General-purpose 32-bit register
2765 One-bit boolean register
2768 MAC16 40-bit accumulator register
2771 Signed 12-bit integer constant, for use in MOVI instructions
2774 Signed 8-bit integer constant, for use in ADDI instructions
2777 Integer constant valid for BccI instructions
2780 Unsigned constant valid for BccUI instructions
2787 @node Standard Names
2788 @section Standard Pattern Names For Generation
2789 @cindex standard pattern names
2790 @cindex pattern names
2791 @cindex names, pattern
2793 Here is a table of the instruction names that are meaningful in the RTL
2794 generation pass of the compiler. Giving one of these names to an
2795 instruction pattern tells the RTL generation pass that it can use the
2796 pattern to accomplish a certain task.
2799 @cindex @code{mov@var{m}} instruction pattern
2800 @item @samp{mov@var{m}}
2801 Here @var{m} stands for a two-letter machine mode name, in lowercase.
2802 This instruction pattern moves data with that machine mode from operand
2803 1 to operand 0. For example, @samp{movsi} moves full-word data.
2805 If operand 0 is a @code{subreg} with mode @var{m} of a register whose
2806 own mode is wider than @var{m}, the effect of this instruction is
2807 to store the specified value in the part of the register that corresponds
2808 to mode @var{m}. Bits outside of @var{m}, but which are within the
2809 same target word as the @code{subreg} are undefined. Bits which are
2810 outside the target word are left unchanged.
2812 This class of patterns is special in several ways. First of all, each
2813 of these names up to and including full word size @emph{must} be defined,
2814 because there is no other way to copy a datum from one place to another.
2815 If there are patterns accepting operands in larger modes,
2816 @samp{mov@var{m}} must be defined for integer modes of those sizes.
2818 Second, these patterns are not used solely in the RTL generation pass.
2819 Even the reload pass can generate move insns to copy values from stack
2820 slots into temporary registers. When it does so, one of the operands is
2821 a hard register and the other is an operand that can need to be reloaded
2825 Therefore, when given such a pair of operands, the pattern must generate
2826 RTL which needs no reloading and needs no temporary registers---no
2827 registers other than the operands. For example, if you support the
2828 pattern with a @code{define_expand}, then in such a case the
2829 @code{define_expand} mustn't call @code{force_reg} or any other such
2830 function which might generate new pseudo registers.
2832 This requirement exists even for subword modes on a RISC machine where
2833 fetching those modes from memory normally requires several insns and
2834 some temporary registers.
2836 @findex change_address
2837 During reload a memory reference with an invalid address may be passed
2838 as an operand. Such an address will be replaced with a valid address
2839 later in the reload pass. In this case, nothing may be done with the
2840 address except to use it as it stands. If it is copied, it will not be
2841 replaced with a valid address. No attempt should be made to make such
2842 an address into a valid address and no routine (such as
2843 @code{change_address}) that will do so may be called. Note that
2844 @code{general_operand} will fail when applied to such an address.
2846 @findex reload_in_progress
2847 The global variable @code{reload_in_progress} (which must be explicitly
2848 declared if required) can be used to determine whether such special
2849 handling is required.
2851 The variety of operands that have reloads depends on the rest of the
2852 machine description, but typically on a RISC machine these can only be
2853 pseudo registers that did not get hard registers, while on other
2854 machines explicit memory references will get optional reloads.
2856 If a scratch register is required to move an object to or from memory,
2857 it can be allocated using @code{gen_reg_rtx} prior to life analysis.
2859 If there are cases which need scratch registers during or after reload,
2860 you must define @code{SECONDARY_INPUT_RELOAD_CLASS} and/or
2861 @code{SECONDARY_OUTPUT_RELOAD_CLASS} to detect them, and provide
2862 patterns @samp{reload_in@var{m}} or @samp{reload_out@var{m}} to handle
2863 them. @xref{Register Classes}.
2865 @findex no_new_pseudos
2866 The global variable @code{no_new_pseudos} can be used to determine if it
2867 is unsafe to create new pseudo registers. If this variable is nonzero, then
2868 it is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo.
2870 The constraints on a @samp{mov@var{m}} must permit moving any hard
2871 register to any other hard register provided that
2872 @code{HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and
2873 @code{REGISTER_MOVE_COST} applied to their classes returns a value of 2.
2875 It is obligatory to support floating point @samp{mov@var{m}}
2876 instructions into and out of any registers that can hold fixed point
2877 values, because unions and structures (which have modes @code{SImode} or
2878 @code{DImode}) can be in those registers and they may have floating
2881 There may also be a need to support fixed point @samp{mov@var{m}}
2882 instructions in and out of floating point registers. Unfortunately, I
2883 have forgotten why this was so, and I don't know whether it is still
2884 true. If @code{HARD_REGNO_MODE_OK} rejects fixed point values in
2885 floating point registers, then the constraints of the fixed point
2886 @samp{mov@var{m}} instructions must be designed to avoid ever trying to
2887 reload into a floating point register.
2889 @cindex @code{reload_in} instruction pattern
2890 @cindex @code{reload_out} instruction pattern
2891 @item @samp{reload_in@var{m}}
2892 @itemx @samp{reload_out@var{m}}
2893 Like @samp{mov@var{m}}, but used when a scratch register is required to
2894 move between operand 0 and operand 1. Operand 2 describes the scratch
2895 register. See the discussion of the @code{SECONDARY_RELOAD_CLASS}
2896 macro in @pxref{Register Classes}.
2898 There are special restrictions on the form of the @code{match_operand}s
2899 used in these patterns. First, only the predicate for the reload
2900 operand is examined, i.e., @code{reload_in} examines operand 1, but not
2901 the predicates for operand 0 or 2. Second, there may be only one
2902 alternative in the constraints. Third, only a single register class
2903 letter may be used for the constraint; subsequent constraint letters
2904 are ignored. As a special exception, an empty constraint string
2905 matches the @code{ALL_REGS} register class. This may relieve ports
2906 of the burden of defining an @code{ALL_REGS} constraint letter just
2909 @cindex @code{movstrict@var{m}} instruction pattern
2910 @item @samp{movstrict@var{m}}
2911 Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg}
2912 with mode @var{m} of a register whose natural mode is wider,
2913 the @samp{movstrict@var{m}} instruction is guaranteed not to alter
2914 any of the register except the part which belongs to mode @var{m}.
2916 @cindex @code{movmisalign@var{m}} instruction pattern
2917 @item @samp{movmisalign@var{m}}
2918 This variant of a move pattern is designed to load or store a value
2919 from a memory address that is not naturally aligned for its mode.
2920 For a store, the memory will be in operand 0; for a load, the memory
2921 will be in operand 1. The other operand is guaranteed not to be a
2922 memory, so that it's easy to tell whether this is a load or store.
2924 This pattern is used by the autovectorizer, and when expanding a
2925 @code{MISALIGNED_INDIRECT_REF} expression.
2927 @cindex @code{load_multiple} instruction pattern
2928 @item @samp{load_multiple}
2929 Load several consecutive memory locations into consecutive registers.
2930 Operand 0 is the first of the consecutive registers, operand 1
2931 is the first memory location, and operand 2 is a constant: the
2932 number of consecutive registers.
2934 Define this only if the target machine really has such an instruction;
2935 do not define this if the most efficient way of loading consecutive
2936 registers from memory is to do them one at a time.
2938 On some machines, there are restrictions as to which consecutive
2939 registers can be stored into memory, such as particular starting or
2940 ending register numbers or only a range of valid counts. For those
2941 machines, use a @code{define_expand} (@pxref{Expander Definitions})
2942 and make the pattern fail if the restrictions are not met.
2944 Write the generated insn as a @code{parallel} with elements being a
2945 @code{set} of one register from the appropriate memory location (you may
2946 also need @code{use} or @code{clobber} elements). Use a
2947 @code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See
2948 @file{rs6000.md} for examples of the use of this insn pattern.
2950 @cindex @samp{store_multiple} instruction pattern
2951 @item @samp{store_multiple}
2952 Similar to @samp{load_multiple}, but store several consecutive registers
2953 into consecutive memory locations. Operand 0 is the first of the
2954 consecutive memory locations, operand 1 is the first register, and
2955 operand 2 is a constant: the number of consecutive registers.
2957 @cindex @code{vec_set@var{m}} instruction pattern
2958 @item @samp{vec_set@var{m}}
2959 Set given field in the vector value. Operand 0 is the vector to modify,
2960 operand 1 is new value of field and operand 2 specify the field index.
2962 @cindex @code{vec_extract@var{m}} instruction pattern
2963 @item @samp{vec_extract@var{m}}
2964 Extract given field from the vector value. Operand 1 is the vector, operand 2
2965 specify field index and operand 0 place to store value into.
2967 @cindex @code{vec_init@var{m}} instruction pattern
2968 @item @samp{vec_init@var{m}}
2969 Initialize the vector to given values. Operand 0 is the vector to initialize
2970 and operand 1 is parallel containing values for individual fields.
2972 @cindex @code{push@var{m}} instruction pattern
2973 @item @samp{push@var{m}}
2974 Output a push instruction. Operand 0 is value to push. Used only when
2975 @code{PUSH_ROUNDING} is defined. For historical reason, this pattern may be
2976 missing and in such case an @code{mov} expander is used instead, with a
2977 @code{MEM} expression forming the push operation. The @code{mov} expander
2978 method is deprecated.
2980 @cindex @code{add@var{m}3} instruction pattern
2981 @item @samp{add@var{m}3}
2982 Add operand 2 and operand 1, storing the result in operand 0. All operands
2983 must have mode @var{m}. This can be used even on two-address machines, by
2984 means of constraints requiring operands 1 and 0 to be the same location.
2986 @cindex @code{sub@var{m}3} instruction pattern
2987 @cindex @code{mul@var{m}3} instruction pattern
2988 @cindex @code{div@var{m}3} instruction pattern
2989 @cindex @code{udiv@var{m}3} instruction pattern
2990 @cindex @code{mod@var{m}3} instruction pattern
2991 @cindex @code{umod@var{m}3} instruction pattern
2992 @cindex @code{umin@var{m}3} instruction pattern
2993 @cindex @code{umax@var{m}3} instruction pattern
2994 @cindex @code{and@var{m}3} instruction pattern
2995 @cindex @code{ior@var{m}3} instruction pattern
2996 @cindex @code{xor@var{m}3} instruction pattern
2997 @item @samp{sub@var{m}3}, @samp{mul@var{m}3}
2998 @itemx @samp{div@var{m}3}, @samp{udiv@var{m}3}
2999 @itemx @samp{mod@var{m}3}, @samp{umod@var{m}3}
3000 @itemx @samp{umin@var{m}3}, @samp{umax@var{m}3}
3001 @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3}
3002 Similar, for other arithmetic operations.
3004 @cindex @code{min@var{m}3} instruction pattern
3005 @cindex @code{max@var{m}3} instruction pattern
3006 @item @samp{smin@var{m}3}, @samp{smax@var{m}3}
3007 Signed minimum and maximum operations. When used with floating point,
3008 if both operands are zeros, or if either operand is @code{NaN}, then
3009 it is unspecified which of the two operands is returned as the result.
3011 @cindex @code{mulhisi3} instruction pattern
3012 @item @samp{mulhisi3}
3013 Multiply operands 1 and 2, which have mode @code{HImode}, and store
3014 a @code{SImode} product in operand 0.
3016 @cindex @code{mulqihi3} instruction pattern
3017 @cindex @code{mulsidi3} instruction pattern
3018 @item @samp{mulqihi3}, @samp{mulsidi3}
3019 Similar widening-multiplication instructions of other widths.
3021 @cindex @code{umulqihi3} instruction pattern
3022 @cindex @code{umulhisi3} instruction pattern
3023 @cindex @code{umulsidi3} instruction pattern
3024 @item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3}
3025 Similar widening-multiplication instructions that do unsigned
3028 @cindex @code{smul@var{m}3_highpart} instruction pattern
3029 @item @samp{smul@var{m}3_highpart}
3030 Perform a signed multiplication of operands 1 and 2, which have mode
3031 @var{m}, and store the most significant half of the product in operand 0.
3032 The least significant half of the product is discarded.
3034 @cindex @code{umul@var{m}3_highpart} instruction pattern
3035 @item @samp{umul@var{m}3_highpart}
3036 Similar, but the multiplication is unsigned.
3038 @cindex @code{divmod@var{m}4} instruction pattern
3039 @item @samp{divmod@var{m}4}
3040 Signed division that produces both a quotient and a remainder.
3041 Operand 1 is divided by operand 2 to produce a quotient stored
3042 in operand 0 and a remainder stored in operand 3.
3044 For machines with an instruction that produces both a quotient and a
3045 remainder, provide a pattern for @samp{divmod@var{m}4} but do not
3046 provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This
3047 allows optimization in the relatively common case when both the quotient
3048 and remainder are computed.
3050 If an instruction that just produces a quotient or just a remainder
3051 exists and is more efficient than the instruction that produces both,
3052 write the output routine of @samp{divmod@var{m}4} to call
3053 @code{find_reg_note} and look for a @code{REG_UNUSED} note on the
3054 quotient or remainder and generate the appropriate instruction.
3056 @cindex @code{udivmod@var{m}4} instruction pattern
3057 @item @samp{udivmod@var{m}4}
3058 Similar, but does unsigned division.
3060 @anchor{shift patterns}
3061 @cindex @code{ashl@var{m}3} instruction pattern
3062 @item @samp{ashl@var{m}3}
3063 Arithmetic-shift operand 1 left by a number of bits specified by operand
3064 2, and store the result in operand 0. Here @var{m} is the mode of
3065 operand 0 and operand 1; operand 2's mode is specified by the
3066 instruction pattern, and the compiler will convert the operand to that
3067 mode before generating the instruction. The meaning of out-of-range shift
3068 counts can optionally be specified by @code{TARGET_SHIFT_TRUNCATION_MASK}.
3069 @xref{TARGET_SHIFT_TRUNCATION_MASK}.
3071 @cindex @code{ashr@var{m}3} instruction pattern
3072 @cindex @code{lshr@var{m}3} instruction pattern
3073 @cindex @code{rotl@var{m}3} instruction pattern
3074 @cindex @code{rotr@var{m}3} instruction pattern
3075 @item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3}
3076 Other shift and rotate instructions, analogous to the
3077 @code{ashl@var{m}3} instructions.
3079 @cindex @code{neg@var{m}2} instruction pattern
3080 @item @samp{neg@var{m}2}
3081 Negate operand 1 and store the result in operand 0.
3083 @cindex @code{abs@var{m}2} instruction pattern
3084 @item @samp{abs@var{m}2}
3085 Store the absolute value of operand 1 into operand 0.
3087 @cindex @code{sqrt@var{m}2} instruction pattern
3088 @item @samp{sqrt@var{m}2}
3089 Store the square root of operand 1 into operand 0.
3091 The @code{sqrt} built-in function of C always uses the mode which
3092 corresponds to the C data type @code{double} and the @code{sqrtf}
3093 built-in function uses the mode which corresponds to the C data
3096 @cindex @code{cos@var{m}2} instruction pattern
3097 @item @samp{cos@var{m}2}
3098 Store the cosine of operand 1 into operand 0.
3100 The @code{cos} built-in function of C always uses the mode which
3101 corresponds to the C data type @code{double} and the @code{cosf}
3102 built-in function uses the mode which corresponds to the C data
3105 @cindex @code{sin@var{m}2} instruction pattern
3106 @item @samp{sin@var{m}2}
3107 Store the sine of operand 1 into operand 0.
3109 The @code{sin} built-in function of C always uses the mode which
3110 corresponds to the C data type @code{double} and the @code{sinf}
3111 built-in function uses the mode which corresponds to the C data
3114 @cindex @code{exp@var{m}2} instruction pattern
3115 @item @samp{exp@var{m}2}
3116 Store the exponential of operand 1 into operand 0.
3118 The @code{exp} built-in function of C always uses the mode which
3119 corresponds to the C data type @code{double} and the @code{expf}
3120 built-in function uses the mode which corresponds to the C data
3123 @cindex @code{log@var{m}2} instruction pattern
3124 @item @samp{log@var{m}2}
3125 Store the natural logarithm of operand 1 into operand 0.
3127 The @code{log} built-in function of C always uses the mode which
3128 corresponds to the C data type @code{double} and the @code{logf}
3129 built-in function uses the mode which corresponds to the C data
3132 @cindex @code{pow@var{m}3} instruction pattern
3133 @item @samp{pow@var{m}3}
3134 Store the value of operand 1 raised to the exponent operand 2
3137 The @code{pow} built-in function of C always uses the mode which
3138 corresponds to the C data type @code{double} and the @code{powf}
3139 built-in function uses the mode which corresponds to the C data
3142 @cindex @code{atan2@var{m}3} instruction pattern
3143 @item @samp{atan2@var{m}3}
3144 Store the arc tangent (inverse tangent) of operand 1 divided by
3145 operand 2 into operand 0, using the signs of both arguments to
3146 determine the quadrant of the result.
3148 The @code{atan2} built-in function of C always uses the mode which
3149 corresponds to the C data type @code{double} and the @code{atan2f}
3150 built-in function uses the mode which corresponds to the C data
3153 @cindex @code{floor@var{m}2} instruction pattern
3154 @item @samp{floor@var{m}2}
3155 Store the largest integral value not greater than argument.
3157 The @code{floor} built-in function of C always uses the mode which
3158 corresponds to the C data type @code{double} and the @code{floorf}
3159 built-in function uses the mode which corresponds to the C data
3162 @cindex @code{btrunc@var{m}2} instruction pattern
3163 @item @samp{btrunc@var{m}2}
3164 Store the argument rounded to integer towards zero.
3166 The @code{trunc} built-in function of C always uses the mode which
3167 corresponds to the C data type @code{double} and the @code{truncf}
3168 built-in function uses the mode which corresponds to the C data
3171 @cindex @code{round@var{m}2} instruction pattern
3172 @item @samp{round@var{m}2}
3173 Store the argument rounded to integer away from zero.
3175 The @code{round} built-in function of C always uses the mode which
3176 corresponds to the C data type @code{double} and the @code{roundf}
3177 built-in function uses the mode which corresponds to the C data
3180 @cindex @code{ceil@var{m}2} instruction pattern
3181 @item @samp{ceil@var{m}2}
3182 Store the argument rounded to integer away from zero.
3184 The @code{ceil} built-in function of C always uses the mode which
3185 corresponds to the C data type @code{double} and the @code{ceilf}
3186 built-in function uses the mode which corresponds to the C data
3189 @cindex @code{nearbyint@var{m}2} instruction pattern
3190 @item @samp{nearbyint@var{m}2}
3191 Store the argument rounded according to the default rounding mode
3193 The @code{nearbyint} built-in function of C always uses the mode which
3194 corresponds to the C data type @code{double} and the @code{nearbyintf}
3195 built-in function uses the mode which corresponds to the C data
3198 @cindex @code{rint@var{m}2} instruction pattern
3199 @item @samp{rint@var{m}2}
3200 Store the argument rounded according to the default rounding mode and
3201 raise the inexact exception when the result differs in value from
3204 The @code{rint} built-in function of C always uses the mode which
3205 corresponds to the C data type @code{double} and the @code{rintf}
3206 built-in function uses the mode which corresponds to the C data
3209 @cindex @code{ffs@var{m}2} instruction pattern
3210 @item @samp{ffs@var{m}2}
3211 Store into operand 0 one plus the index of the least significant 1-bit
3212 of operand 1. If operand 1 is zero, store zero. @var{m} is the mode
3213 of operand 0; operand 1's mode is specified by the instruction
3214 pattern, and the compiler will convert the operand to that mode before
3215 generating the instruction.
3217 The @code{ffs} built-in function of C always uses the mode which
3218 corresponds to the C data type @code{int}.
3220 @cindex @code{clz@var{m}2} instruction pattern
3221 @item @samp{clz@var{m}2}
3222 Store into operand 0 the number of leading 0-bits in @var{x}, starting
3223 at the most significant bit position. If @var{x} is 0, the result is
3224 undefined. @var{m} is the mode of operand 0; operand 1's mode is
3225 specified by the instruction pattern, and the compiler will convert the
3226 operand to that mode before generating the instruction.
3228 @cindex @code{ctz@var{m}2} instruction pattern
3229 @item @samp{ctz@var{m}2}
3230 Store into operand 0 the number of trailing 0-bits in @var{x}, starting
3231 at the least significant bit position. If @var{x} is 0, the result is
3232 undefined. @var{m} is the mode of operand 0; operand 1's mode is
3233 specified by the instruction pattern, and the compiler will convert the
3234 operand to that mode before generating the instruction.
3236 @cindex @code{popcount@var{m}2} instruction pattern
3237 @item @samp{popcount@var{m}2}
3238 Store into operand 0 the number of 1-bits in @var{x}. @var{m} is the
3239 mode of operand 0; operand 1's mode is specified by the instruction
3240 pattern, and the compiler will convert the operand to that mode before
3241 generating the instruction.
3243 @cindex @code{parity@var{m}2} instruction pattern
3244 @item @samp{parity@var{m}2}
3245 Store into operand 0 the parity of @var{x}, i.e.@: the number of 1-bits
3246 in @var{x} modulo 2. @var{m} is the mode of operand 0; operand 1's mode
3247 is specified by the instruction pattern, and the compiler will convert
3248 the operand to that mode before generating the instruction.
3250 @cindex @code{one_cmpl@var{m}2} instruction pattern
3251 @item @samp{one_cmpl@var{m}2}
3252 Store the bitwise-complement of operand 1 into operand 0.
3254 @cindex @code{cmp@var{m}} instruction pattern
3255 @item @samp{cmp@var{m}}
3256 Compare operand 0 and operand 1, and set the condition codes.
3257 The RTL pattern should look like this:
3260 (set (cc0) (compare (match_operand:@var{m} 0 @dots{})
3261 (match_operand:@var{m} 1 @dots{})))
3264 @cindex @code{tst@var{m}} instruction pattern
3265 @item @samp{tst@var{m}}
3266 Compare operand 0 against zero, and set the condition codes.
3267 The RTL pattern should look like this:
3270 (set (cc0) (match_operand:@var{m} 0 @dots{}))
3273 @samp{tst@var{m}} patterns should not be defined for machines that do
3274 not use @code{(cc0)}. Doing so would confuse the optimizer since it
3275 would no longer be clear which @code{set} operations were comparisons.
3276 The @samp{cmp@var{m}} patterns should be used instead.
3278 @cindex @code{movmem@var{m}} instruction pattern
3279 @item @samp{movmem@var{m}}
3280 Block move instruction. The destination and source blocks of memory
3281 are the first two operands, and both are @code{mem:BLK}s with an
3282 address in mode @code{Pmode}.
3284 The number of bytes to move is the third operand, in mode @var{m}.
3285 Usually, you specify @code{word_mode} for @var{m}. However, if you can
3286 generate better code knowing the range of valid lengths is smaller than
3287 those representable in a full word, you should provide a pattern with a
3288 mode corresponding to the range of values you can handle efficiently
3289 (e.g., @code{QImode} for values in the range 0--127; note we avoid numbers
3290 that appear negative) and also a pattern with @code{word_mode}.
3292 The fourth operand is the known shared alignment of the source and
3293 destination, in the form of a @code{const_int} rtx. Thus, if the
3294 compiler knows that both source and destination are word-aligned,
3295 it may provide the value 4 for this operand.
3297 Descriptions of multiple @code{movmem@var{m}} patterns can only be
3298 beneficial if the patterns for smaller modes have fewer restrictions
3299 on their first, second and fourth operands. Note that the mode @var{m}
3300 in @code{movmem@var{m}} does not impose any restriction on the mode of
3301 individually moved data units in the block.
3303 These patterns need not give special consideration to the possibility
3304 that the source and destination strings might overlap.
3306 @cindex @code{movstr} instruction pattern
3308 String copy instruction, with @code{stpcpy} semantics. Operand 0 is
3309 an output operand in mode @code{Pmode}. The addresses of the
3310 destination and source strings are operands 1 and 2, and both are
3311 @code{mem:BLK}s with addresses in mode @code{Pmode}. The execution of
3312 the expansion of this pattern should store in operand 0 the address in
3313 which the @code{NUL} terminator was stored in the destination string.
3315 @cindex @code{setmem@var{m}} instruction pattern
3316 @item @samp{setmem@var{m}}
3317 Block set instruction. The destination string is the first operand,
3318 given as a @code{mem:BLK} whose address is in mode @code{Pmode}. The
3319 number of bytes to set is the second operand, in mode @var{m}. The value to
3320 initialize the memory with is the third operand. Targets that only support the
3321 clearing of memory should reject any value that is not the constant 0. See
3322 @samp{movmem@var{m}} for a discussion of the choice of mode.
3324 The fourth operand is the known alignment of the destination, in the form
3325 of a @code{const_int} rtx. Thus, if the compiler knows that the
3326 destination is word-aligned, it may provide the value 4 for this
3329 The use for multiple @code{setmem@var{m}} is as for @code{movmem@var{m}}.
3331 @cindex @code{cmpstrn@var{m}} instruction pattern
3332 @item @samp{cmpstrn@var{m}}
3333 String compare instruction, with five operands. Operand 0 is the output;
3334 it has mode @var{m}. The remaining four operands are like the operands
3335 of @samp{movmem@var{m}}. The two memory blocks specified are compared
3336 byte by byte in lexicographic order starting at the beginning of each
3337 string. The instruction is not allowed to prefetch more than one byte
3338 at a time since either string may end in the first byte and reading past
3339 that may access an invalid page or segment and cause a fault. The
3340 effect of the instruction is to store a value in operand 0 whose sign
3341 indicates the result of the comparison.
3343 @cindex @code{cmpstr@var{m}} instruction pattern
3344 @item @samp{cmpstr@var{m}}
3345 String compare instruction, without known maximum length. Operand 0 is the
3346 output; it has mode @var{m}. The second and third operand are the blocks of
3347 memory to be compared; both are @code{mem:BLK} with an address in mode
3350 The fourth operand is the known shared alignment of the source and
3351 destination, in the form of a @code{const_int} rtx. Thus, if the
3352 compiler knows that both source and destination are word-aligned,
3353 it may provide the value 4 for this operand.
3355 The two memory blocks specified are compared byte by byte in lexicographic
3356 order starting at the beginning of each string. The instruction is not allowed
3357 to prefetch more than one byte at a time since either string may end in the
3358 first byte and reading past that may access an invalid page or segment and
3359 cause a fault. The effect of the instruction is to store a value in operand 0
3360 whose sign indicates the result of the comparison.
3362 @cindex @code{cmpmem@var{m}} instruction pattern
3363 @item @samp{cmpmem@var{m}}
3364 Block compare instruction, with five operands like the operands
3365 of @samp{cmpstr@var{m}}. The two memory blocks specified are compared
3366 byte by byte in lexicographic order starting at the beginning of each
3367 block. Unlike @samp{cmpstr@var{m}} the instruction can prefetch
3368 any bytes in the two memory blocks. The effect of the instruction is
3369 to store a value in operand 0 whose sign indicates the result of the
3372 @cindex @code{strlen@var{m}} instruction pattern
3373 @item @samp{strlen@var{m}}
3374 Compute the length of a string, with three operands.
3375 Operand 0 is the result (of mode @var{m}), operand 1 is
3376 a @code{mem} referring to the first character of the string,
3377 operand 2 is the character to search for (normally zero),
3378 and operand 3 is a constant describing the known alignment
3379 of the beginning of the string.
3381 @cindex @code{float@var{mn}2} instruction pattern
3382 @item @samp{float@var{m}@var{n}2}
3383 Convert signed integer operand 1 (valid for fixed point mode @var{m}) to
3384 floating point mode @var{n} and store in operand 0 (which has mode
3387 @cindex @code{floatuns@var{mn}2} instruction pattern
3388 @item @samp{floatuns@var{m}@var{n}2}
3389 Convert unsigned integer operand 1 (valid for fixed point mode @var{m})
3390 to floating point mode @var{n} and store in operand 0 (which has mode
3393 @cindex @code{fix@var{mn}2} instruction pattern
3394 @item @samp{fix@var{m}@var{n}2}
3395 Convert operand 1 (valid for floating point mode @var{m}) to fixed
3396 point mode @var{n} as a signed number and store in operand 0 (which
3397 has mode @var{n}). This instruction's result is defined only when
3398 the value of operand 1 is an integer.
3400 If the machine description defines this pattern, it also needs to
3401 define the @code{ftrunc} pattern.
3403 @cindex @code{fixuns@var{mn}2} instruction pattern
3404 @item @samp{fixuns@var{m}@var{n}2}
3405 Convert operand 1 (valid for floating point mode @var{m}) to fixed
3406 point mode @var{n} as an unsigned number and store in operand 0 (which
3407 has mode @var{n}). This instruction's result is defined only when the
3408 value of operand 1 is an integer.
3410 @cindex @code{ftrunc@var{m}2} instruction pattern
3411 @item @samp{ftrunc@var{m}2}
3412 Convert operand 1 (valid for floating point mode @var{m}) to an
3413 integer value, still represented in floating point mode @var{m}, and
3414 store it in operand 0 (valid for floating point mode @var{m}).
3416 @cindex @code{fix_trunc@var{mn}2} instruction pattern
3417 @item @samp{fix_trunc@var{m}@var{n}2}
3418 Like @samp{fix@var{m}@var{n}2} but works for any floating point value
3419 of mode @var{m} by converting the value to an integer.
3421 @cindex @code{fixuns_trunc@var{mn}2} instruction pattern
3422 @item @samp{fixuns_trunc@var{m}@var{n}2}
3423 Like @samp{fixuns@var{m}@var{n}2} but works for any floating point
3424 value of mode @var{m} by converting the value to an integer.
3426 @cindex @code{trunc@var{mn}2} instruction pattern
3427 @item @samp{trunc@var{m}@var{n}2}
3428 Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and
3429 store in operand 0 (which has mode @var{n}). Both modes must be fixed
3430 point or both floating point.
3432 @cindex @code{extend@var{mn}2} instruction pattern
3433 @item @samp{extend@var{m}@var{n}2}
3434 Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
3435 store in operand 0 (which has mode @var{n}). Both modes must be fixed
3436 point or both floating point.
3438 @cindex @code{zero_extend@var{mn}2} instruction pattern
3439 @item @samp{zero_extend@var{m}@var{n}2}
3440 Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
3441 store in operand 0 (which has mode @var{n}). Both modes must be fixed
3444 @cindex @code{extv} instruction pattern
3446 Extract a bit-field from operand 1 (a register or memory operand), where
3447 operand 2 specifies the width in bits and operand 3 the starting bit,
3448 and store it in operand 0. Operand 0 must have mode @code{word_mode}.
3449 Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often
3450 @code{word_mode} is allowed only for registers. Operands 2 and 3 must
3451 be valid for @code{word_mode}.
3453 The RTL generation pass generates this instruction only with constants
3454 for operands 2 and 3.
3456 The bit-field value is sign-extended to a full word integer
3457 before it is stored in operand 0.
3459 @cindex @code{extzv} instruction pattern
3461 Like @samp{extv} except that the bit-field value is zero-extended.
3463 @cindex @code{insv} instruction pattern
3465 Store operand 3 (which must be valid for @code{word_mode}) into a
3466 bit-field in operand 0, where operand 1 specifies the width in bits and
3467 operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or
3468 @code{word_mode}; often @code{word_mode} is allowed only for registers.
3469 Operands 1 and 2 must be valid for @code{word_mode}.
3471 The RTL generation pass generates this instruction only with constants
3472 for operands 1 and 2.
3474 @cindex @code{mov@var{mode}cc} instruction pattern
3475 @item @samp{mov@var{mode}cc}
3476 Conditionally move operand 2 or operand 3 into operand 0 according to the
3477 comparison in operand 1. If the comparison is true, operand 2 is moved
3478 into operand 0, otherwise operand 3 is moved.
3480 The mode of the operands being compared need not be the same as the operands
3481 being moved. Some machines, sparc64 for example, have instructions that
3482 conditionally move an integer value based on the floating point condition
3483 codes and vice versa.
3485 If the machine does not have conditional move instructions, do not
3486 define these patterns.
3488 @cindex @code{add@var{mode}cc} instruction pattern
3489 @item @samp{add@var{mode}cc}
3490 Similar to @samp{mov@var{mode}cc} but for conditional addition. Conditionally
3491 move operand 2 or (operands 2 + operand 3) into operand 0 according to the
3492 comparison in operand 1. If the comparison is true, operand 2 is moved into
3493 operand 0, otherwise (operand 2 + operand 3) is moved.
3495 @cindex @code{s@var{cond}} instruction pattern
3496 @item @samp{s@var{cond}}
3497 Store zero or nonzero in the operand according to the condition codes.
3498 Value stored is nonzero iff the condition @var{cond} is true.
3499 @var{cond} is the name of a comparison operation expression code, such
3500 as @code{eq}, @code{lt} or @code{leu}.
3502 You specify the mode that the operand must have when you write the
3503 @code{match_operand} expression. The compiler automatically sees
3504 which mode you have used and supplies an operand of that mode.
3506 The value stored for a true condition must have 1 as its low bit, or
3507 else must be negative. Otherwise the instruction is not suitable and
3508 you should omit it from the machine description. You describe to the
3509 compiler exactly which value is stored by defining the macro
3510 @code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be
3511 found that can be used for all the @samp{s@var{cond}} patterns, you
3512 should omit those operations from the machine description.
3514 These operations may fail, but should do so only in relatively
3515 uncommon cases; if they would fail for common cases involving
3516 integer comparisons, it is best to omit these patterns.
3518 If these operations are omitted, the compiler will usually generate code
3519 that copies the constant one to the target and branches around an
3520 assignment of zero to the target. If this code is more efficient than
3521 the potential instructions used for the @samp{s@var{cond}} pattern
3522 followed by those required to convert the result into a 1 or a zero in
3523 @code{SImode}, you should omit the @samp{s@var{cond}} operations from
3524 the machine description.
3526 @cindex @code{b@var{cond}} instruction pattern
3527 @item @samp{b@var{cond}}
3528 Conditional branch instruction. Operand 0 is a @code{label_ref} that
3529 refers to the label to jump to. Jump if the condition codes meet
3530 condition @var{cond}.
3532 Some machines do not follow the model assumed here where a comparison
3533 instruction is followed by a conditional branch instruction. In that
3534 case, the @samp{cmp@var{m}} (and @samp{tst@var{m}}) patterns should
3535 simply store the operands away and generate all the required insns in a
3536 @code{define_expand} (@pxref{Expander Definitions}) for the conditional
3537 branch operations. All calls to expand @samp{b@var{cond}} patterns are
3538 immediately preceded by calls to expand either a @samp{cmp@var{m}}
3539 pattern or a @samp{tst@var{m}} pattern.
3541 Machines that use a pseudo register for the condition code value, or
3542 where the mode used for the comparison depends on the condition being
3543 tested, should also use the above mechanism. @xref{Jump Patterns}.
3545 The above discussion also applies to the @samp{mov@var{mode}cc} and
3546 @samp{s@var{cond}} patterns.
3548 @cindex @code{cbranch@var{mode}4} instruction pattern
3549 @item @samp{cbranch@var{mode}4}
3550 Conditional branch instruction combined with a compare instruction.
3551 Operand 0 is a comparison operator. Operand 1 and operand 2 are the
3552 first and second operands of the comparison, respectively. Operand 3
3553 is a @code{label_ref} that refers to the label to jump to.
3555 @cindex @code{jump} instruction pattern
3557 A jump inside a function; an unconditional branch. Operand 0 is the
3558 @code{label_ref} of the label to jump to. This pattern name is mandatory
3561 @cindex @code{call} instruction pattern
3563 Subroutine call instruction returning no value. Operand 0 is the
3564 function to call; operand 1 is the number of bytes of arguments pushed
3565 as a @code{const_int}; operand 2 is the number of registers used as
3568 On most machines, operand 2 is not actually stored into the RTL
3569 pattern. It is supplied for the sake of some RISC machines which need
3570 to put this information into the assembler code; they can put it in
3571 the RTL instead of operand 1.
3573 Operand 0 should be a @code{mem} RTX whose address is the address of the
3574 function. Note, however, that this address can be a @code{symbol_ref}
3575 expression even if it would not be a legitimate memory address on the
3576 target machine. If it is also not a valid argument for a call
3577 instruction, the pattern for this operation should be a
3578 @code{define_expand} (@pxref{Expander Definitions}) that places the
3579 address into a register and uses that register in the call instruction.
3581 @cindex @code{call_value} instruction pattern
3582 @item @samp{call_value}
3583 Subroutine call instruction returning a value. Operand 0 is the hard
3584 register in which the value is returned. There are three more
3585 operands, the same as the three operands of the @samp{call}
3586 instruction (but with numbers increased by one).
3588 Subroutines that return @code{BLKmode} objects use the @samp{call}
3591 @cindex @code{call_pop} instruction pattern
3592 @cindex @code{call_value_pop} instruction pattern
3593 @item @samp{call_pop}, @samp{call_value_pop}
3594 Similar to @samp{call} and @samp{call_value}, except used if defined and
3595 if @code{RETURN_POPS_ARGS} is nonzero. They should emit a @code{parallel}
3596 that contains both the function call and a @code{set} to indicate the
3597 adjustment made to the frame pointer.
3599 For machines where @code{RETURN_POPS_ARGS} can be nonzero, the use of these
3600 patterns increases the number of functions for which the frame pointer
3601 can be eliminated, if desired.
3603 @cindex @code{untyped_call} instruction pattern
3604 @item @samp{untyped_call}
3605 Subroutine call instruction returning a value of any type. Operand 0 is
3606 the function to call; operand 1 is a memory location where the result of
3607 calling the function is to be stored; operand 2 is a @code{parallel}
3608 expression where each element is a @code{set} expression that indicates
3609 the saving of a function return value into the result block.
3611 This instruction pattern should be defined to support
3612 @code{__builtin_apply} on machines where special instructions are needed
3613 to call a subroutine with arbitrary arguments or to save the value
3614 returned. This instruction pattern is required on machines that have
3615 multiple registers that can hold a return value
3616 (i.e.@: @code{FUNCTION_VALUE_REGNO_P} is true for more than one register).
3618 @cindex @code{return} instruction pattern
3620 Subroutine return instruction. This instruction pattern name should be
3621 defined only if a single instruction can do all the work of returning
3624 Like the @samp{mov@var{m}} patterns, this pattern is also used after the
3625 RTL generation phase. In this case it is to support machines where
3626 multiple instructions are usually needed to return from a function, but
3627 some class of functions only requires one instruction to implement a
3628 return. Normally, the applicable functions are those which do not need
3629 to save any registers or allocate stack space.
3631 @findex reload_completed
3632 @findex leaf_function_p
3633 For such machines, the condition specified in this pattern should only
3634 be true when @code{reload_completed} is nonzero and the function's
3635 epilogue would only be a single instruction. For machines with register
3636 windows, the routine @code{leaf_function_p} may be used to determine if
3637 a register window push is required.
3639 Machines that have conditional return instructions should define patterns
3645 (if_then_else (match_operator
3646 0 "comparison_operator"
3647 [(cc0) (const_int 0)])
3654 where @var{condition} would normally be the same condition specified on the
3655 named @samp{return} pattern.
3657 @cindex @code{untyped_return} instruction pattern
3658 @item @samp{untyped_return}
3659 Untyped subroutine return instruction. This instruction pattern should
3660 be defined to support @code{__builtin_return} on machines where special
3661 instructions are needed to return a value of any type.
3663 Operand 0 is a memory location where the result of calling a function
3664 with @code{__builtin_apply} is stored; operand 1 is a @code{parallel}
3665 expression where each element is a @code{set} expression that indicates
3666 the restoring of a function return value from the result block.
3668 @cindex @code{nop} instruction pattern
3670 No-op instruction. This instruction pattern name should always be defined
3671 to output a no-op in assembler code. @code{(const_int 0)} will do as an
3674 @cindex @code{indirect_jump} instruction pattern
3675 @item @samp{indirect_jump}
3676 An instruction to jump to an address which is operand zero.
3677 This pattern name is mandatory on all machines.
3679 @cindex @code{casesi} instruction pattern
3681 Instruction to jump through a dispatch table, including bounds checking.
3682 This instruction takes five operands:
3686 The index to dispatch on, which has mode @code{SImode}.
3689 The lower bound for indices in the table, an integer constant.
3692 The total range of indices in the table---the largest index
3693 minus the smallest one (both inclusive).
3696 A label that precedes the table itself.
3699 A label to jump to if the index has a value outside the bounds.
3702 The table is a @code{addr_vec} or @code{addr_diff_vec} inside of a
3703 @code{jump_insn}. The number of elements in the table is one plus the
3704 difference between the upper bound and the lower bound.
3706 @cindex @code{tablejump} instruction pattern
3707 @item @samp{tablejump}
3708 Instruction to jump to a variable address. This is a low-level
3709 capability which can be used to implement a dispatch table when there
3710 is no @samp{casesi} pattern.
3712 This pattern requires two operands: the address or offset, and a label
3713 which should immediately precede the jump table. If the macro
3714 @code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first
3715 operand is an offset which counts from the address of the table; otherwise,
3716 it is an absolute address to jump to. In either case, the first operand has
3719 The @samp{tablejump} insn is always the last insn before the jump
3720 table it uses. Its assembler code normally has no need to use the
3721 second operand, but you should incorporate it in the RTL pattern so
3722 that the jump optimizer will not delete the table as unreachable code.
3725 @cindex @code{decrement_and_branch_until_zero} instruction pattern
3726 @item @samp{decrement_and_branch_until_zero}
3727 Conditional branch instruction that decrements a register and
3728 jumps if the register is nonzero. Operand 0 is the register to
3729 decrement and test; operand 1 is the label to jump to if the
3730 register is nonzero. @xref{Looping Patterns}.
3732 This optional instruction pattern is only used by the combiner,
3733 typically for loops reversed by the loop optimizer when strength
3734 reduction is enabled.
3736 @cindex @code{doloop_end} instruction pattern
3737 @item @samp{doloop_end}
3738 Conditional branch instruction that decrements a register and jumps if
3739 the register is nonzero. This instruction takes five operands: Operand
3740 0 is the register to decrement and test; operand 1 is the number of loop
3741 iterations as a @code{const_int} or @code{const0_rtx} if this cannot be
3742 determined until run-time; operand 2 is the actual or estimated maximum
3743 number of iterations as a @code{const_int}; operand 3 is the number of
3744 enclosed loops as a @code{const_int} (an innermost loop has a value of
3745 1); operand 4 is the label to jump to if the register is nonzero.
3746 @xref{Looping Patterns}.
3748 This optional instruction pattern should be defined for machines with
3749 low-overhead looping instructions as the loop optimizer will try to
3750 modify suitable loops to utilize it. If nested low-overhead looping is
3751 not supported, use a @code{define_expand} (@pxref{Expander Definitions})
3752 and make the pattern fail if operand 3 is not @code{const1_rtx}.
3753 Similarly, if the actual or estimated maximum number of iterations is
3754 too large for this instruction, make it fail.
3756 @cindex @code{doloop_begin} instruction pattern
3757 @item @samp{doloop_begin}
3758 Companion instruction to @code{doloop_end} required for machines that
3759 need to perform some initialization, such as loading special registers
3760 used by a low-overhead looping instruction. If initialization insns do
3761 not always need to be emitted, use a @code{define_expand}
3762 (@pxref{Expander Definitions}) and make it fail.
3765 @cindex @code{canonicalize_funcptr_for_compare} instruction pattern
3766 @item @samp{canonicalize_funcptr_for_compare}
3767 Canonicalize the function pointer in operand 1 and store the result
3770 Operand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1
3771 may be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc
3772 and also has mode @code{Pmode}.
3774 Canonicalization of a function pointer usually involves computing
3775 the address of the function which would be called if the function
3776 pointer were used in an indirect call.
3778 Only define this pattern if function pointers on the target machine
3779 can have different values but still call the same function when
3780 used in an indirect call.
3782 @cindex @code{save_stack_block} instruction pattern
3783 @cindex @code{save_stack_function} instruction pattern
3784 @cindex @code{save_stack_nonlocal} instruction pattern
3785 @cindex @code{restore_stack_block} instruction pattern
3786 @cindex @code{restore_stack_function} instruction pattern
3787 @cindex @code{restore_stack_nonlocal} instruction pattern
3788 @item @samp{save_stack_block}
3789 @itemx @samp{save_stack_function}
3790 @itemx @samp{save_stack_nonlocal}
3791 @itemx @samp{restore_stack_block}
3792 @itemx @samp{restore_stack_function}
3793 @itemx @samp{restore_stack_nonlocal}
3794 Most machines save and restore the stack pointer by copying it to or
3795 from an object of mode @code{Pmode}. Do not define these patterns on
3798 Some machines require special handling for stack pointer saves and
3799 restores. On those machines, define the patterns corresponding to the
3800 non-standard cases by using a @code{define_expand} (@pxref{Expander
3801 Definitions}) that produces the required insns. The three types of
3802 saves and restores are:
3806 @samp{save_stack_block} saves the stack pointer at the start of a block
3807 that allocates a variable-sized object, and @samp{restore_stack_block}
3808 restores the stack pointer when the block is exited.
3811 @samp{save_stack_function} and @samp{restore_stack_function} do a
3812 similar job for the outermost block of a function and are used when the
3813 function allocates variable-sized objects or calls @code{alloca}. Only
3814 the epilogue uses the restored stack pointer, allowing a simpler save or
3815 restore sequence on some machines.
3818 @samp{save_stack_nonlocal} is used in functions that contain labels
3819 branched to by nested functions. It saves the stack pointer in such a
3820 way that the inner function can use @samp{restore_stack_nonlocal} to
3821 restore the stack pointer. The compiler generates code to restore the
3822 frame and argument pointer registers, but some machines require saving
3823 and restoring additional data such as register window information or
3824 stack backchains. Place insns in these patterns to save and restore any
3828 When saving the stack pointer, operand 0 is the save area and operand 1
3829 is the stack pointer. The mode used to allocate the save area defaults
3830 to @code{Pmode} but you can override that choice by defining the
3831 @code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must
3832 specify an integral mode, or @code{VOIDmode} if no save area is needed
3833 for a particular type of save (either because no save is needed or
3834 because a machine-specific save area can be used). Operand 0 is the
3835 stack pointer and operand 1 is the save area for restore operations. If
3836 @samp{save_stack_block} is defined, operand 0 must not be
3837 @code{VOIDmode} since these saves can be arbitrarily nested.
3839 A save area is a @code{mem} that is at a constant offset from
3840 @code{virtual_stack_vars_rtx} when the stack pointer is saved for use by
3841 nonlocal gotos and a @code{reg} in the other two cases.
3843 @cindex @code{allocate_stack} instruction pattern
3844 @item @samp{allocate_stack}
3845 Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from
3846 the stack pointer to create space for dynamically allocated data.
3848 Store the resultant pointer to this space into operand 0. If you
3849 are allocating space from the main stack, do this by emitting a
3850 move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0.
3851 If you are allocating the space elsewhere, generate code to copy the
3852 location of the space to operand 0. In the latter case, you must
3853 ensure this space gets freed when the corresponding space on the main
3856 Do not define this pattern if all that must be done is the subtraction.
3857 Some machines require other operations such as stack probes or
3858 maintaining the back chain. Define this pattern to emit those
3859 operations in addition to updating the stack pointer.
3861 @cindex @code{check_stack} instruction pattern
3862 @item @samp{check_stack}
3863 If stack checking cannot be done on your system by probing the stack with
3864 a load or store instruction (@pxref{Stack Checking}), define this pattern
3865 to perform the needed check and signaling an error if the stack
3866 has overflowed. The single operand is the location in the stack furthest
3867 from the current stack pointer that you need to validate. Normally,
3868 on machines where this pattern is needed, you would obtain the stack
3869 limit from a global or thread-specific variable or register.
3871 @cindex @code{nonlocal_goto} instruction pattern
3872 @item @samp{nonlocal_goto}
3873 Emit code to generate a non-local goto, e.g., a jump from one function
3874 to a label in an outer function. This pattern has four arguments,
3875 each representing a value to be used in the jump. The first
3876 argument is to be loaded into the frame pointer, the second is
3877 the address to branch to (code to dispatch to the actual label),
3878 the third is the address of a location where the stack is saved,
3879 and the last is the address of the label, to be placed in the
3880 location for the incoming static chain.
3882 On most machines you need not define this pattern, since GCC will
3883 already generate the correct code, which is to load the frame pointer
3884 and static chain, restore the stack (using the
3885 @samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly
3886 to the dispatcher. You need only define this pattern if this code will
3887 not work on your machine.
3889 @cindex @code{nonlocal_goto_receiver} instruction pattern
3890 @item @samp{nonlocal_goto_receiver}
3891 This pattern, if defined, contains code needed at the target of a
3892 nonlocal goto after the code already generated by GCC@. You will not
3893 normally need to define this pattern. A typical reason why you might
3894 need this pattern is if some value, such as a pointer to a global table,
3895 must be restored when the frame pointer is restored. Note that a nonlocal
3896 goto only occurs within a unit-of-translation, so a global table pointer
3897 that is shared by all functions of a given module need not be restored.
3898 There are no arguments.
3900 @cindex @code{exception_receiver} instruction pattern
3901 @item @samp{exception_receiver}
3902 This pattern, if defined, contains code needed at the site of an
3903 exception handler that isn't needed at the site of a nonlocal goto. You
3904 will not normally need to define this pattern. A typical reason why you
3905 might need this pattern is if some value, such as a pointer to a global
3906 table, must be restored after control flow is branched to the handler of
3907 an exception. There are no arguments.
3909 @cindex @code{builtin_setjmp_setup} instruction pattern
3910 @item @samp{builtin_setjmp_setup}
3911 This pattern, if defined, contains additional code needed to initialize
3912 the @code{jmp_buf}. You will not normally need to define this pattern.
3913 A typical reason why you might need this pattern is if some value, such
3914 as a pointer to a global table, must be restored. Though it is
3915 preferred that the pointer value be recalculated if possible (given the
3916 address of a label for instance). The single argument is a pointer to
3917 the @code{jmp_buf}. Note that the buffer is five words long and that
3918 the first three are normally used by the generic mechanism.
3920 @cindex @code{builtin_setjmp_receiver} instruction pattern
3921 @item @samp{builtin_setjmp_receiver}
3922 This pattern, if defined, contains code needed at the site of an
3923 built-in setjmp that isn't needed at the site of a nonlocal goto. You
3924 will not normally need to define this pattern. A typical reason why you
3925 might need this pattern is if some value, such as a pointer to a global
3926 table, must be restored. It takes one argument, which is the label
3927 to which builtin_longjmp transfered control; this pattern may be emitted
3928 at a small offset from that label.
3930 @cindex @code{builtin_longjmp} instruction pattern
3931 @item @samp{builtin_longjmp}
3932 This pattern, if defined, performs the entire action of the longjmp.
3933 You will not normally need to define this pattern unless you also define
3934 @code{builtin_setjmp_setup}. The single argument is a pointer to the
3937 @cindex @code{eh_return} instruction pattern
3938 @item @samp{eh_return}
3939 This pattern, if defined, affects the way @code{__builtin_eh_return},
3940 and thence the call frame exception handling library routines, are
3941 built. It is intended to handle non-trivial actions needed along
3942 the abnormal return path.
3944 The address of the exception handler to which the function should return
3945 is passed as operand to this pattern. It will normally need to copied by
3946 the pattern to some special register or memory location.
3947 If the pattern needs to determine the location of the target call
3948 frame in order to do so, it may use @code{EH_RETURN_STACKADJ_RTX},
3949 if defined; it will have already been assigned.
3951 If this pattern is not defined, the default action will be to simply
3952 copy the return address to @code{EH_RETURN_HANDLER_RTX}. Either
3953 that macro or this pattern needs to be defined if call frame exception
3954 handling is to be used.
3956 @cindex @code{prologue} instruction pattern
3957 @anchor{prologue instruction pattern}
3958 @item @samp{prologue}
3959 This pattern, if defined, emits RTL for entry to a function. The function
3960 entry is responsible for setting up the stack frame, initializing the frame
3961 pointer register, saving callee saved registers, etc.
3963 Using a prologue pattern is generally preferred over defining
3964 @code{TARGET_ASM_FUNCTION_PROLOGUE} to emit assembly code for the prologue.
3966 The @code{prologue} pattern is particularly useful for targets which perform
3967 instruction scheduling.
3969 @cindex @code{epilogue} instruction pattern
3970 @anchor{epilogue instruction pattern}
3971 @item @samp{epilogue}
3972 This pattern emits RTL for exit from a function. The function
3973 exit is responsible for deallocating the stack frame, restoring callee saved
3974 registers and emitting the return instruction.
3976 Using an epilogue pattern is generally preferred over defining
3977 @code{TARGET_ASM_FUNCTION_EPILOGUE} to emit assembly code for the epilogue.
3979 The @code{epilogue} pattern is particularly useful for targets which perform
3980 instruction scheduling or which have delay slots for their return instruction.
3982 @cindex @code{sibcall_epilogue} instruction pattern
3983 @item @samp{sibcall_epilogue}
3984 This pattern, if defined, emits RTL for exit from a function without the final
3985 branch back to the calling function. This pattern will be emitted before any
3986 sibling call (aka tail call) sites.
3988 The @code{sibcall_epilogue} pattern must not clobber any arguments used for
3989 parameter passing or any stack slots for arguments passed to the current
3992 @cindex @code{trap} instruction pattern
3994 This pattern, if defined, signals an error, typically by causing some
3995 kind of signal to be raised. Among other places, it is used by the Java
3996 front end to signal `invalid array index' exceptions.
3998 @cindex @code{conditional_trap} instruction pattern
3999 @item @samp{conditional_trap}
4000 Conditional trap instruction. Operand 0 is a piece of RTL which
4001 performs a comparison. Operand 1 is the trap code, an integer.
4003 A typical @code{conditional_trap} pattern looks like
4006 (define_insn "conditional_trap"
4007 [(trap_if (match_operator 0 "trap_operator"
4008 [(cc0) (const_int 0)])
4009 (match_operand 1 "const_int_operand" "i"))]
4014 @cindex @code{prefetch} instruction pattern
4015 @item @samp{prefetch}
4017 This pattern, if defined, emits code for a non-faulting data prefetch
4018 instruction. Operand 0 is the address of the memory to prefetch. Operand 1
4019 is a constant 1 if the prefetch is preparing for a write to the memory
4020 address, or a constant 0 otherwise. Operand 2 is the expected degree of
4021 temporal locality of the data and is a value between 0 and 3, inclusive; 0
4022 means that the data has no temporal locality, so it need not be left in the
4023 cache after the access; 3 means that the data has a high degree of temporal
4024 locality and should be left in all levels of cache possible; 1 and 2 mean,
4025 respectively, a low or moderate degree of temporal locality.
4027 Targets that do not support write prefetches or locality hints can ignore
4028 the values of operands 1 and 2.
4030 @cindex @code{memory_barrier} instruction pattern
4031 @item @samp{memory_barrier}
4033 If the target memory model is not fully synchronous, then this pattern
4034 should be defined to an instruction that orders both loads and stores
4035 before the instruction with respect to loads and stores after the instruction.
4036 This pattern has no operands.
4038 @cindex @code{sync_compare_and_swap@var{mode}} instruction pattern
4039 @item @samp{sync_compare_and_swap@var{mode}}
4041 This pattern, if defined, emits code for an atomic compare-and-swap
4042 operation. Operand 1 is the memory on which the atomic operation is
4043 performed. Operand 2 is the ``old'' value to be compared against the
4044 current contents of the memory location. Operand 3 is the ``new'' value
4045 to store in the memory if the compare succeeds. Operand 0 is the result
4046 of the operation; it should contain the contents of the memory
4047 before the operation. If the compare succeeds, this should obviously be
4048 a copy of operand 2.
4050 This pattern must show that both operand 0 and operand 1 are modified.
4052 This pattern must issue any memory barrier instructions such that all
4053 memory operations before the atomic operation occur before the atomic
4054 operation and all memory operations after the atomic operation occur
4055 after the atomic operation.
4057 @cindex @code{sync_compare_and_swap_cc@var{mode}} instruction pattern
4058 @item @samp{sync_compare_and_swap_cc@var{mode}}
4060 This pattern is just like @code{sync_compare_and_swap@var{mode}}, except
4061 it should act as if compare part of the compare-and-swap were issued via
4062 @code{cmp@var{m}}. This comparison will only be used with @code{EQ} and
4063 @code{NE} branches and @code{setcc} operations.
4065 Some targets do expose the success or failure of the compare-and-swap
4066 operation via the status flags. Ideally we wouldn't need a separate
4067 named pattern in order to take advantage of this, but the combine pass
4068 does not handle patterns with multiple sets, which is required by
4069 definition for @code{sync_compare_and_swap@var{mode}}.
4071 @cindex @code{sync_add@var{mode}} instruction pattern
4072 @cindex @code{sync_sub@var{mode}} instruction pattern
4073 @cindex @code{sync_ior@var{mode}} instruction pattern
4074 @cindex @code{sync_and@var{mode}} instruction pattern
4075 @cindex @code{sync_xor@var{mode}} instruction pattern
4076 @cindex @code{sync_nand@var{mode}} instruction pattern
4077 @item @samp{sync_add@var{mode}}, @samp{sync_sub@var{mode}}
4078 @itemx @samp{sync_ior@var{mode}}, @samp{sync_and@var{mode}}
4079 @itemx @samp{sync_xor@var{mode}}, @samp{sync_nand@var{mode}}
4081 These patterns emit code for an atomic operation on memory.
4082 Operand 0 is the memory on which the atomic operation is performed.
4083 Operand 1 is the second operand to the binary operator.
4085 The ``nand'' operation is @code{op0 & ~op1}.
4087 This pattern must issue any memory barrier instructions such that all
4088 memory operations before the atomic operation occur before the atomic
4089 operation and all memory operations after the atomic operation occur
4090 after the atomic operation.
4092 If these patterns are not defined, the operation will be constructed
4093 from a compare-and-swap operation, if defined.
4095 @cindex @code{sync_old_add@var{mode}} instruction pattern
4096 @cindex @code{sync_old_sub@var{mode}} instruction pattern
4097 @cindex @code{sync_old_ior@var{mode}} instruction pattern
4098 @cindex @code{sync_old_and@var{mode}} instruction pattern
4099 @cindex @code{sync_old_xor@var{mode}} instruction pattern
4100 @cindex @code{sync_old_nand@var{mode}} instruction pattern
4101 @item @samp{sync_old_add@var{mode}}, @samp{sync_old_sub@var{mode}}
4102 @itemx @samp{sync_old_ior@var{mode}}, @samp{sync_old_and@var{mode}}
4103 @itemx @samp{sync_old_xor@var{mode}}, @samp{sync_old_nand@var{mode}}
4105 These patterns are emit code for an atomic operation on memory,
4106 and return the value that the memory contained before the operation.
4107 Operand 0 is the result value, operand 1 is the memory on which the
4108 atomic operation is performed, and operand 2 is the second operand
4109 to the binary operator.
4111 This pattern must issue any memory barrier instructions such that all
4112 memory operations before the atomic operation occur before the atomic
4113 operation and all memory operations after the atomic operation occur
4114 after the atomic operation.
4116 If these patterns are not defined, the operation will be constructed
4117 from a compare-and-swap operation, if defined.
4119 @cindex @code{sync_new_add@var{mode}} instruction pattern
4120 @cindex @code{sync_new_sub@var{mode}} instruction pattern
4121 @cindex @code{sync_new_ior@var{mode}} instruction pattern
4122 @cindex @code{sync_new_and@var{mode}} instruction pattern
4123 @cindex @code{sync_new_xor@var{mode}} instruction pattern
4124 @cindex @code{sync_new_nand@var{mode}} instruction pattern
4125 @item @samp{sync_new_add@var{mode}}, @samp{sync_new_sub@var{mode}}
4126 @itemx @samp{sync_new_ior@var{mode}}, @samp{sync_new_and@var{mode}}
4127 @itemx @samp{sync_new_xor@var{mode}}, @samp{sync_new_nand@var{mode}}
4129 These patterns are like their @code{sync_old_@var{op}} counterparts,
4130 except that they return the value that exists in the memory location
4131 after the operation, rather than before the operation.
4133 @cindex @code{sync_lock_test_and_set@var{mode}} instruction pattern
4134 @item @samp{sync_lock_test_and_set@var{mode}}
4136 This pattern takes two forms, based on the capabilities of the target.
4137 In either case, operand 0 is the result of the operand, operand 1 is
4138 the memory on which the atomic operation is performed, and operand 2
4139 is the value to set in the lock.
4141 In the ideal case, this operation is an atomic exchange operation, in
4142 which the previous value in memory operand is copied into the result
4143 operand, and the value operand is stored in the memory operand.
4145 For less capable targets, any value operand that is not the constant 1
4146 should be rejected with @code{FAIL}. In this case the target may use
4147 an atomic test-and-set bit operation. The result operand should contain
4148 1 if the bit was previously set and 0 if the bit was previously clear.
4149 The true contents of the memory operand are implementation defined.
4151 This pattern must issue any memory barrier instructions such that the
4152 pattern as a whole acts as an acquire barrier, that is all memory
4153 operations after the pattern do not occur until the lock is acquired.
4155 If this pattern is not defined, the operation will be constructed from
4156 a compare-and-swap operation, if defined.
4158 @cindex @code{sync_lock_release@var{mode}} instruction pattern
4159 @item @samp{sync_lock_release@var{mode}}
4161 This pattern, if defined, releases a lock set by
4162 @code{sync_lock_test_and_set@var{mode}}. Operand 0 is the memory
4163 that contains the lock; operand 1 is the value to store in the lock.
4165 If the target doesn't implement full semantics for
4166 @code{sync_lock_test_and_set@var{mode}}, any value operand which is not
4167 the constant 0 should be rejected with @code{FAIL}, and the true contents
4168 of the memory operand are implementation defined.
4170 This pattern must issue any memory barrier instructions such that the
4171 pattern as a whole acts as a release barrier, that is the lock is
4172 released only after all previous memory operations have completed.
4174 If this pattern is not defined, then a @code{memory_barrier} pattern
4175 will be emitted, followed by a store of the value to the memory operand.
4177 @cindex @code{stack_protect_set} instruction pattern
4178 @item @samp{stack_protect_set}
4180 This pattern, if defined, moves a @code{Pmode} value from the memory
4181 in operand 1 to the memory in operand 0 without leaving the value in
4182 a register afterward. This is to avoid leaking the value some place
4183 that an attacker might use to rewrite the stack guard slot after
4184 having clobbered it.
4186 If this pattern is not defined, then a plain move pattern is generated.
4188 @cindex @code{stack_protect_test} instruction pattern
4189 @item @samp{stack_protect_test}
4191 This pattern, if defined, compares a @code{Pmode} value from the
4192 memory in operand 1 with the memory in operand 0 without leaving the
4193 value in a register afterward and branches to operand 2 if the values
4196 If this pattern is not defined, then a plain compare pattern and
4197 conditional branch pattern is used.
4202 @c Each of the following nodes are wrapped in separate
4203 @c "@ifset INTERNALS" to work around memory limits for the default
4204 @c configuration in older tetex distributions. Known to not work:
4205 @c tetex-1.0.7, known to work: tetex-2.0.2.
4207 @node Pattern Ordering
4208 @section When the Order of Patterns Matters
4209 @cindex Pattern Ordering
4210 @cindex Ordering of Patterns
4212 Sometimes an insn can match more than one instruction pattern. Then the
4213 pattern that appears first in the machine description is the one used.
4214 Therefore, more specific patterns (patterns that will match fewer things)
4215 and faster instructions (those that will produce better code when they
4216 do match) should usually go first in the description.
4218 In some cases the effect of ordering the patterns can be used to hide
4219 a pattern when it is not valid. For example, the 68000 has an
4220 instruction for converting a fullword to floating point and another
4221 for converting a byte to floating point. An instruction converting
4222 an integer to floating point could match either one. We put the
4223 pattern to convert the fullword first to make sure that one will
4224 be used rather than the other. (Otherwise a large integer might
4225 be generated as a single-byte immediate quantity, which would not work.)
4226 Instead of using this pattern ordering it would be possible to make the
4227 pattern for convert-a-byte smart enough to deal properly with any
4232 @node Dependent Patterns
4233 @section Interdependence of Patterns
4234 @cindex Dependent Patterns
4235 @cindex Interdependence of Patterns
4237 Every machine description must have a named pattern for each of the
4238 conditional branch names @samp{b@var{cond}}. The recognition template
4239 must always have the form
4243 (if_then_else (@var{cond} (cc0) (const_int 0))
4244 (label_ref (match_operand 0 "" ""))
4249 In addition, every machine description must have an anonymous pattern
4250 for each of the possible reverse-conditional branches. Their templates
4255 (if_then_else (@var{cond} (cc0) (const_int 0))
4257 (label_ref (match_operand 0 "" ""))))
4261 They are necessary because jump optimization can turn direct-conditional
4262 branches into reverse-conditional branches.
4264 It is often convenient to use the @code{match_operator} construct to
4265 reduce the number of patterns that must be specified for branches. For
4271 (if_then_else (match_operator 0 "comparison_operator"
4272 [(cc0) (const_int 0)])
4274 (label_ref (match_operand 1 "" ""))))]
4279 In some cases machines support instructions identical except for the
4280 machine mode of one or more operands. For example, there may be
4281 ``sign-extend halfword'' and ``sign-extend byte'' instructions whose
4285 (set (match_operand:SI 0 @dots{})
4286 (extend:SI (match_operand:HI 1 @dots{})))
4288 (set (match_operand:SI 0 @dots{})
4289 (extend:SI (match_operand:QI 1 @dots{})))
4293 Constant integers do not specify a machine mode, so an instruction to
4294 extend a constant value could match either pattern. The pattern it
4295 actually will match is the one that appears first in the file. For correct
4296 results, this must be the one for the widest possible mode (@code{HImode},
4297 here). If the pattern matches the @code{QImode} instruction, the results
4298 will be incorrect if the constant value does not actually fit that mode.
4300 Such instructions to extend constants are rarely generated because they are
4301 optimized away, but they do occasionally happen in nonoptimized
4304 If a constraint in a pattern allows a constant, the reload pass may
4305 replace a register with a constant permitted by the constraint in some
4306 cases. Similarly for memory references. Because of this substitution,
4307 you should not provide separate patterns for increment and decrement
4308 instructions. Instead, they should be generated from the same pattern
4309 that supports register-register add insns by examining the operands and
4310 generating the appropriate machine instruction.
4315 @section Defining Jump Instruction Patterns
4316 @cindex jump instruction patterns
4317 @cindex defining jump instruction patterns
4319 For most machines, GCC assumes that the machine has a condition code.
4320 A comparison insn sets the condition code, recording the results of both
4321 signed and unsigned comparison of the given operands. A separate branch
4322 insn tests the condition code and branches or not according its value.
4323 The branch insns come in distinct signed and unsigned flavors. Many
4324 common machines, such as the VAX, the 68000 and the 32000, work this
4327 Some machines have distinct signed and unsigned compare instructions, and
4328 only one set of conditional branch instructions. The easiest way to handle
4329 these machines is to treat them just like the others until the final stage
4330 where assembly code is written. At this time, when outputting code for the
4331 compare instruction, peek ahead at the following branch using
4332 @code{next_cc0_user (insn)}. (The variable @code{insn} refers to the insn
4333 being output, in the output-writing code in an instruction pattern.) If
4334 the RTL says that is an unsigned branch, output an unsigned compare;
4335 otherwise output a signed compare. When the branch itself is output, you
4336 can treat signed and unsigned branches identically.
4338 The reason you can do this is that GCC always generates a pair of
4339 consecutive RTL insns, possibly separated by @code{note} insns, one to
4340 set the condition code and one to test it, and keeps the pair inviolate
4343 To go with this technique, you must define the machine-description macro
4344 @code{NOTICE_UPDATE_CC} to do @code{CC_STATUS_INIT}; in other words, no
4345 compare instruction is superfluous.
4347 Some machines have compare-and-branch instructions and no condition code.
4348 A similar technique works for them. When it is time to ``output'' a
4349 compare instruction, record its operands in two static variables. When
4350 outputting the branch-on-condition-code instruction that follows, actually
4351 output a compare-and-branch instruction that uses the remembered operands.
4353 It also works to define patterns for compare-and-branch instructions.
4354 In optimizing compilation, the pair of compare and branch instructions
4355 will be combined according to these patterns. But this does not happen
4356 if optimization is not requested. So you must use one of the solutions
4357 above in addition to any special patterns you define.
4359 In many RISC machines, most instructions do not affect the condition
4360 code and there may not even be a separate condition code register. On
4361 these machines, the restriction that the definition and use of the
4362 condition code be adjacent insns is not necessary and can prevent
4363 important optimizations. For example, on the IBM RS/6000, there is a
4364 delay for taken branches unless the condition code register is set three
4365 instructions earlier than the conditional branch. The instruction
4366 scheduler cannot perform this optimization if it is not permitted to
4367 separate the definition and use of the condition code register.
4369 On these machines, do not use @code{(cc0)}, but instead use a register
4370 to represent the condition code. If there is a specific condition code
4371 register in the machine, use a hard register. If the condition code or
4372 comparison result can be placed in any general register, or if there are
4373 multiple condition registers, use a pseudo register.
4375 @findex prev_cc0_setter
4376 @findex next_cc0_user
4377 On some machines, the type of branch instruction generated may depend on
4378 the way the condition code was produced; for example, on the 68k and
4379 SPARC, setting the condition code directly from an add or subtract
4380 instruction does not clear the overflow bit the way that a test
4381 instruction does, so a different branch instruction must be used for
4382 some conditional branches. For machines that use @code{(cc0)}, the set
4383 and use of the condition code must be adjacent (separated only by
4384 @code{note} insns) allowing flags in @code{cc_status} to be used.
4385 (@xref{Condition Code}.) Also, the comparison and branch insns can be
4386 located from each other by using the functions @code{prev_cc0_setter}
4387 and @code{next_cc0_user}.
4389 However, this is not true on machines that do not use @code{(cc0)}. On
4390 those machines, no assumptions can be made about the adjacency of the
4391 compare and branch insns and the above methods cannot be used. Instead,
4392 we use the machine mode of the condition code register to record
4393 different formats of the condition code register.
4395 Registers used to store the condition code value should have a mode that
4396 is in class @code{MODE_CC}. Normally, it will be @code{CCmode}. If
4397 additional modes are required (as for the add example mentioned above in
4398 the SPARC), define them in @file{@var{machine}-modes.def}
4399 (@pxref{Condition Code}). Also define @code{SELECT_CC_MODE} to choose
4400 a mode given an operand of a compare.
4402 If it is known during RTL generation that a different mode will be
4403 required (for example, if the machine has separate compare instructions
4404 for signed and unsigned quantities, like most IBM processors), they can
4405 be specified at that time.
4407 If the cases that require different modes would be made by instruction
4408 combination, the macro @code{SELECT_CC_MODE} determines which machine
4409 mode should be used for the comparison result. The patterns should be
4410 written using that mode. To support the case of the add on the SPARC
4411 discussed above, we have the pattern
4415 [(set (reg:CC_NOOV 0)
4417 (plus:SI (match_operand:SI 0 "register_operand" "%r")
4418 (match_operand:SI 1 "arith_operand" "rI"))
4424 The @code{SELECT_CC_MODE} macro on the SPARC returns @code{CC_NOOVmode}
4425 for comparisons whose argument is a @code{plus}.
4429 @node Looping Patterns
4430 @section Defining Looping Instruction Patterns
4431 @cindex looping instruction patterns
4432 @cindex defining looping instruction patterns
4434 Some machines have special jump instructions that can be utilized to
4435 make loops more efficient. A common example is the 68000 @samp{dbra}
4436 instruction which performs a decrement of a register and a branch if the
4437 result was greater than zero. Other machines, in particular digital
4438 signal processors (DSPs), have special block repeat instructions to
4439 provide low-overhead loop support. For example, the TI TMS320C3x/C4x
4440 DSPs have a block repeat instruction that loads special registers to
4441 mark the top and end of a loop and to count the number of loop
4442 iterations. This avoids the need for fetching and executing a
4443 @samp{dbra}-like instruction and avoids pipeline stalls associated with
4446 GCC has three special named patterns to support low overhead looping.
4447 They are @samp{decrement_and_branch_until_zero}, @samp{doloop_begin},
4448 and @samp{doloop_end}. The first pattern,
4449 @samp{decrement_and_branch_until_zero}, is not emitted during RTL
4450 generation but may be emitted during the instruction combination phase.
4451 This requires the assistance of the loop optimizer, using information
4452 collected during strength reduction, to reverse a loop to count down to
4453 zero. Some targets also require the loop optimizer to add a
4454 @code{REG_NONNEG} note to indicate that the iteration count is always
4455 positive. This is needed if the target performs a signed loop
4456 termination test. For example, the 68000 uses a pattern similar to the
4457 following for its @code{dbra} instruction:
4461 (define_insn "decrement_and_branch_until_zero"
4464 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
4467 (label_ref (match_operand 1 "" ""))
4470 (plus:SI (match_dup 0)
4472 "find_reg_note (insn, REG_NONNEG, 0)"
4477 Note that since the insn is both a jump insn and has an output, it must
4478 deal with its own reloads, hence the `m' constraints. Also note that
4479 since this insn is generated by the instruction combination phase
4480 combining two sequential insns together into an implicit parallel insn,
4481 the iteration counter needs to be biased by the same amount as the
4482 decrement operation, in this case @minus{}1. Note that the following similar
4483 pattern will not be matched by the combiner.
4487 (define_insn "decrement_and_branch_until_zero"
4490 (ge (match_operand:SI 0 "general_operand" "+d*am")
4492 (label_ref (match_operand 1 "" ""))
4495 (plus:SI (match_dup 0)
4497 "find_reg_note (insn, REG_NONNEG, 0)"
4502 The other two special looping patterns, @samp{doloop_begin} and
4503 @samp{doloop_end}, are emitted by the loop optimizer for certain
4504 well-behaved loops with a finite number of loop iterations using
4505 information collected during strength reduction.
4507 The @samp{doloop_end} pattern describes the actual looping instruction
4508 (or the implicit looping operation) and the @samp{doloop_begin} pattern
4509 is an optional companion pattern that can be used for initialization
4510 needed for some low-overhead looping instructions.
4512 Note that some machines require the actual looping instruction to be
4513 emitted at the top of the loop (e.g., the TMS320C3x/C4x DSPs). Emitting
4514 the true RTL for a looping instruction at the top of the loop can cause
4515 problems with flow analysis. So instead, a dummy @code{doloop} insn is
4516 emitted at the end of the loop. The machine dependent reorg pass checks
4517 for the presence of this @code{doloop} insn and then searches back to
4518 the top of the loop, where it inserts the true looping insn (provided
4519 there are no instructions in the loop which would cause problems). Any
4520 additional labels can be emitted at this point. In addition, if the
4521 desired special iteration counter register was not allocated, this
4522 machine dependent reorg pass could emit a traditional compare and jump
4525 The essential difference between the
4526 @samp{decrement_and_branch_until_zero} and the @samp{doloop_end}
4527 patterns is that the loop optimizer allocates an additional pseudo
4528 register for the latter as an iteration counter. This pseudo register
4529 cannot be used within the loop (i.e., general induction variables cannot
4530 be derived from it), however, in many cases the loop induction variable
4531 may become redundant and removed by the flow pass.
4536 @node Insn Canonicalizations
4537 @section Canonicalization of Instructions
4538 @cindex canonicalization of instructions
4539 @cindex insn canonicalization
4541 There are often cases where multiple RTL expressions could represent an
4542 operation performed by a single machine instruction. This situation is
4543 most commonly encountered with logical, branch, and multiply-accumulate
4544 instructions. In such cases, the compiler attempts to convert these
4545 multiple RTL expressions into a single canonical form to reduce the
4546 number of insn patterns required.
4548 In addition to algebraic simplifications, following canonicalizations
4553 For commutative and comparison operators, a constant is always made the
4554 second operand. If a machine only supports a constant as the second
4555 operand, only patterns that match a constant in the second operand need
4559 For associative operators, a sequence of operators will always chain
4560 to the left; for instance, only the left operand of an integer @code{plus}
4561 can itself be a @code{plus}. @code{and}, @code{ior}, @code{xor},
4562 @code{plus}, @code{mult}, @code{smin}, @code{smax}, @code{umin}, and
4563 @code{umax} are associative when applied to integers, and sometimes to
4567 @cindex @code{neg}, canonicalization of
4568 @cindex @code{not}, canonicalization of
4569 @cindex @code{mult}, canonicalization of
4570 @cindex @code{plus}, canonicalization of
4571 @cindex @code{minus}, canonicalization of
4572 For these operators, if only one operand is a @code{neg}, @code{not},
4573 @code{mult}, @code{plus}, or @code{minus} expression, it will be the
4577 In combinations of @code{neg}, @code{mult}, @code{plus}, and
4578 @code{minus}, the @code{neg} operations (if any) will be moved inside
4579 the operations as far as possible. For instance,
4580 @code{(neg (mult A B))} is canonicalized as @code{(mult (neg A) B)}, but
4581 @code{(plus (mult (neg A) B) C)} is canonicalized as
4582 @code{(minus A (mult B C))}.
4584 @cindex @code{compare}, canonicalization of
4586 For the @code{compare} operator, a constant is always the second operand
4587 on machines where @code{cc0} is used (@pxref{Jump Patterns}). On other
4588 machines, there are rare cases where the compiler might want to construct
4589 a @code{compare} with a constant as the first operand. However, these
4590 cases are not common enough for it to be worthwhile to provide a pattern
4591 matching a constant as the first operand unless the machine actually has
4592 such an instruction.
4594 An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or
4595 @code{minus} is made the first operand under the same conditions as
4599 @code{(minus @var{x} (const_int @var{n}))} is converted to
4600 @code{(plus @var{x} (const_int @var{-n}))}.
4603 Within address computations (i.e., inside @code{mem}), a left shift is
4604 converted into the appropriate multiplication by a power of two.
4606 @cindex @code{ior}, canonicalization of
4607 @cindex @code{and}, canonicalization of
4608 @cindex De Morgan's law
4610 De Morgan's Law is used to move bitwise negation inside a bitwise
4611 logical-and or logical-or operation. If this results in only one
4612 operand being a @code{not} expression, it will be the first one.
4614 A machine that has an instruction that performs a bitwise logical-and of one
4615 operand with the bitwise negation of the other should specify the pattern
4616 for that instruction as
4620 [(set (match_operand:@var{m} 0 @dots{})
4621 (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
4622 (match_operand:@var{m} 2 @dots{})))]
4628 Similarly, a pattern for a ``NAND'' instruction should be written
4632 [(set (match_operand:@var{m} 0 @dots{})
4633 (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
4634 (not:@var{m} (match_operand:@var{m} 2 @dots{}))))]
4639 In both cases, it is not necessary to include patterns for the many
4640 logically equivalent RTL expressions.
4642 @cindex @code{xor}, canonicalization of
4644 The only possible RTL expressions involving both bitwise exclusive-or
4645 and bitwise negation are @code{(xor:@var{m} @var{x} @var{y})}
4646 and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}.
4649 The sum of three items, one of which is a constant, will only appear in
4653 (plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant})
4657 On machines that do not use @code{cc0},
4658 @code{(compare @var{x} (const_int 0))} will be converted to
4661 @cindex @code{zero_extract}, canonicalization of
4662 @cindex @code{sign_extract}, canonicalization of
4664 Equality comparisons of a group of bits (usually a single bit) with zero
4665 will be written using @code{zero_extract} rather than the equivalent
4666 @code{and} or @code{sign_extract} operations.
4672 @node Expander Definitions
4673 @section Defining RTL Sequences for Code Generation
4674 @cindex expander definitions
4675 @cindex code generation RTL sequences
4676 @cindex defining RTL sequences for code generation
4678 On some target machines, some standard pattern names for RTL generation
4679 cannot be handled with single insn, but a sequence of RTL insns can
4680 represent them. For these target machines, you can write a
4681 @code{define_expand} to specify how to generate the sequence of RTL@.
4683 @findex define_expand
4684 A @code{define_expand} is an RTL expression that looks almost like a
4685 @code{define_insn}; but, unlike the latter, a @code{define_expand} is used
4686 only for RTL generation and it can produce more than one RTL insn.
4688 A @code{define_expand} RTX has four operands:
4692 The name. Each @code{define_expand} must have a name, since the only
4693 use for it is to refer to it by name.
4696 The RTL template. This is a vector of RTL expressions representing
4697 a sequence of separate instructions. Unlike @code{define_insn}, there
4698 is no implicit surrounding @code{PARALLEL}.
4701 The condition, a string containing a C expression. This expression is
4702 used to express how the availability of this pattern depends on
4703 subclasses of target machine, selected by command-line options when GCC
4704 is run. This is just like the condition of a @code{define_insn} that
4705 has a standard name. Therefore, the condition (if present) may not
4706 depend on the data in the insn being matched, but only the
4707 target-machine-type flags. The compiler needs to test these conditions
4708 during initialization in order to learn exactly which named instructions
4709 are available in a particular run.
4712 The preparation statements, a string containing zero or more C
4713 statements which are to be executed before RTL code is generated from
4716 Usually these statements prepare temporary registers for use as
4717 internal operands in the RTL template, but they can also generate RTL
4718 insns directly by calling routines such as @code{emit_insn}, etc.
4719 Any such insns precede the ones that come from the RTL template.
4722 Every RTL insn emitted by a @code{define_expand} must match some
4723 @code{define_insn} in the machine description. Otherwise, the compiler
4724 will crash when trying to generate code for the insn or trying to optimize
4727 The RTL template, in addition to controlling generation of RTL insns,
4728 also describes the operands that need to be specified when this pattern
4729 is used. In particular, it gives a predicate for each operand.
4731 A true operand, which needs to be specified in order to generate RTL from
4732 the pattern, should be described with a @code{match_operand} in its first
4733 occurrence in the RTL template. This enters information on the operand's
4734 predicate into the tables that record such things. GCC uses the
4735 information to preload the operand into a register if that is required for
4736 valid RTL code. If the operand is referred to more than once, subsequent
4737 references should use @code{match_dup}.
4739 The RTL template may also refer to internal ``operands'' which are
4740 temporary registers or labels used only within the sequence made by the
4741 @code{define_expand}. Internal operands are substituted into the RTL
4742 template with @code{match_dup}, never with @code{match_operand}. The
4743 values of the internal operands are not passed in as arguments by the
4744 compiler when it requests use of this pattern. Instead, they are computed
4745 within the pattern, in the preparation statements. These statements
4746 compute the values and store them into the appropriate elements of
4747 @code{operands} so that @code{match_dup} can find them.
4749 There are two special macros defined for use in the preparation statements:
4750 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
4757 Use the @code{DONE} macro to end RTL generation for the pattern. The
4758 only RTL insns resulting from the pattern on this occasion will be
4759 those already emitted by explicit calls to @code{emit_insn} within the
4760 preparation statements; the RTL template will not be generated.
4764 Make the pattern fail on this occasion. When a pattern fails, it means
4765 that the pattern was not truly available. The calling routines in the
4766 compiler will try other strategies for code generation using other patterns.
4768 Failure is currently supported only for binary (addition, multiplication,
4769 shifting, etc.) and bit-field (@code{extv}, @code{extzv}, and @code{insv})
4773 If the preparation falls through (invokes neither @code{DONE} nor
4774 @code{FAIL}), then the @code{define_expand} acts like a
4775 @code{define_insn} in that the RTL template is used to generate the
4778 The RTL template is not used for matching, only for generating the
4779 initial insn list. If the preparation statement always invokes
4780 @code{DONE} or @code{FAIL}, the RTL template may be reduced to a simple
4781 list of operands, such as this example:
4785 (define_expand "addsi3"
4786 [(match_operand:SI 0 "register_operand" "")
4787 (match_operand:SI 1 "register_operand" "")
4788 (match_operand:SI 2 "register_operand" "")]
4794 handle_add (operands[0], operands[1], operands[2]);
4800 Here is an example, the definition of left-shift for the SPUR chip:
4804 (define_expand "ashlsi3"
4805 [(set (match_operand:SI 0 "register_operand" "")
4809 (match_operand:SI 1 "register_operand" "")
4810 (match_operand:SI 2 "nonmemory_operand" "")))]
4819 if (GET_CODE (operands[2]) != CONST_INT
4820 || (unsigned) INTVAL (operands[2]) > 3)
4827 This example uses @code{define_expand} so that it can generate an RTL insn
4828 for shifting when the shift-count is in the supported range of 0 to 3 but
4829 fail in other cases where machine insns aren't available. When it fails,
4830 the compiler tries another strategy using different patterns (such as, a
4833 If the compiler were able to handle nontrivial condition-strings in
4834 patterns with names, then it would be possible to use a
4835 @code{define_insn} in that case. Here is another case (zero-extension
4836 on the 68000) which makes more use of the power of @code{define_expand}:
4839 (define_expand "zero_extendhisi2"
4840 [(set (match_operand:SI 0 "general_operand" "")
4842 (set (strict_low_part
4846 (match_operand:HI 1 "general_operand" ""))]
4848 "operands[1] = make_safe_from (operands[1], operands[0]);")
4852 @findex make_safe_from
4853 Here two RTL insns are generated, one to clear the entire output operand
4854 and the other to copy the input operand into its low half. This sequence
4855 is incorrect if the input operand refers to [the old value of] the output
4856 operand, so the preparation statement makes sure this isn't so. The
4857 function @code{make_safe_from} copies the @code{operands[1]} into a
4858 temporary register if it refers to @code{operands[0]}. It does this
4859 by emitting another RTL insn.
4861 Finally, a third example shows the use of an internal operand.
4862 Zero-extension on the SPUR chip is done by @code{and}-ing the result
4863 against a halfword mask. But this mask cannot be represented by a
4864 @code{const_int} because the constant value is too large to be legitimate
4865 on this machine. So it must be copied into a register with
4866 @code{force_reg} and then the register used in the @code{and}.
4869 (define_expand "zero_extendhisi2"
4870 [(set (match_operand:SI 0 "register_operand" "")
4872 (match_operand:HI 1 "register_operand" "")
4877 = force_reg (SImode, GEN_INT (65535)); ")
4880 @emph{Note:} If the @code{define_expand} is used to serve a
4881 standard binary or unary arithmetic operation or a bit-field operation,
4882 then the last insn it generates must not be a @code{code_label},
4883 @code{barrier} or @code{note}. It must be an @code{insn},
4884 @code{jump_insn} or @code{call_insn}. If you don't need a real insn
4885 at the end, emit an insn to copy the result of the operation into
4886 itself. Such an insn will generate no code, but it can avoid problems
4891 @node Insn Splitting
4892 @section Defining How to Split Instructions
4893 @cindex insn splitting
4894 @cindex instruction splitting
4895 @cindex splitting instructions
4897 There are two cases where you should specify how to split a pattern
4898 into multiple insns. On machines that have instructions requiring
4899 delay slots (@pxref{Delay Slots}) or that have instructions whose
4900 output is not available for multiple cycles (@pxref{Processor pipeline
4901 description}), the compiler phases that optimize these cases need to
4902 be able to move insns into one-instruction delay slots. However, some
4903 insns may generate more than one machine instruction. These insns
4904 cannot be placed into a delay slot.
4906 Often you can rewrite the single insn as a list of individual insns,
4907 each corresponding to one machine instruction. The disadvantage of
4908 doing so is that it will cause the compilation to be slower and require
4909 more space. If the resulting insns are too complex, it may also
4910 suppress some optimizations. The compiler splits the insn if there is a
4911 reason to believe that it might improve instruction or delay slot
4914 The insn combiner phase also splits putative insns. If three insns are
4915 merged into one insn with a complex expression that cannot be matched by
4916 some @code{define_insn} pattern, the combiner phase attempts to split
4917 the complex pattern into two insns that are recognized. Usually it can
4918 break the complex pattern into two patterns by splitting out some
4919 subexpression. However, in some other cases, such as performing an
4920 addition of a large constant in two insns on a RISC machine, the way to
4921 split the addition into two insns is machine-dependent.
4923 @findex define_split
4924 The @code{define_split} definition tells the compiler how to split a
4925 complex insn into several simpler insns. It looks like this:
4929 [@var{insn-pattern}]
4931 [@var{new-insn-pattern-1}
4932 @var{new-insn-pattern-2}
4934 "@var{preparation-statements}")
4937 @var{insn-pattern} is a pattern that needs to be split and
4938 @var{condition} is the final condition to be tested, as in a
4939 @code{define_insn}. When an insn matching @var{insn-pattern} and
4940 satisfying @var{condition} is found, it is replaced in the insn list
4941 with the insns given by @var{new-insn-pattern-1},
4942 @var{new-insn-pattern-2}, etc.
4944 The @var{preparation-statements} are similar to those statements that
4945 are specified for @code{define_expand} (@pxref{Expander Definitions})
4946 and are executed before the new RTL is generated to prepare for the
4947 generated code or emit some insns whose pattern is not fixed. Unlike
4948 those in @code{define_expand}, however, these statements must not
4949 generate any new pseudo-registers. Once reload has completed, they also
4950 must not allocate any space in the stack frame.
4952 Patterns are matched against @var{insn-pattern} in two different
4953 circumstances. If an insn needs to be split for delay slot scheduling
4954 or insn scheduling, the insn is already known to be valid, which means
4955 that it must have been matched by some @code{define_insn} and, if
4956 @code{reload_completed} is nonzero, is known to satisfy the constraints
4957 of that @code{define_insn}. In that case, the new insn patterns must
4958 also be insns that are matched by some @code{define_insn} and, if
4959 @code{reload_completed} is nonzero, must also satisfy the constraints
4960 of those definitions.
4962 As an example of this usage of @code{define_split}, consider the following
4963 example from @file{a29k.md}, which splits a @code{sign_extend} from
4964 @code{HImode} to @code{SImode} into a pair of shift insns:
4968 [(set (match_operand:SI 0 "gen_reg_operand" "")
4969 (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
4972 (ashift:SI (match_dup 1)
4975 (ashiftrt:SI (match_dup 0)
4978 @{ operands[1] = gen_lowpart (SImode, operands[1]); @}")
4981 When the combiner phase tries to split an insn pattern, it is always the
4982 case that the pattern is @emph{not} matched by any @code{define_insn}.
4983 The combiner pass first tries to split a single @code{set} expression
4984 and then the same @code{set} expression inside a @code{parallel}, but
4985 followed by a @code{clobber} of a pseudo-reg to use as a scratch
4986 register. In these cases, the combiner expects exactly two new insn
4987 patterns to be generated. It will verify that these patterns match some
4988 @code{define_insn} definitions, so you need not do this test in the
4989 @code{define_split} (of course, there is no point in writing a
4990 @code{define_split} that will never produce insns that match).
4992 Here is an example of this use of @code{define_split}, taken from
4997 [(set (match_operand:SI 0 "gen_reg_operand" "")
4998 (plus:SI (match_operand:SI 1 "gen_reg_operand" "")
4999 (match_operand:SI 2 "non_add_cint_operand" "")))]
5001 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
5002 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
5005 int low = INTVAL (operands[2]) & 0xffff;
5006 int high = (unsigned) INTVAL (operands[2]) >> 16;
5009 high++, low |= 0xffff0000;
5011 operands[3] = GEN_INT (high << 16);
5012 operands[4] = GEN_INT (low);
5016 Here the predicate @code{non_add_cint_operand} matches any
5017 @code{const_int} that is @emph{not} a valid operand of a single add
5018 insn. The add with the smaller displacement is written so that it
5019 can be substituted into the address of a subsequent operation.
5021 An example that uses a scratch register, from the same file, generates
5022 an equality comparison of a register and a large constant:
5026 [(set (match_operand:CC 0 "cc_reg_operand" "")
5027 (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
5028 (match_operand:SI 2 "non_short_cint_operand" "")))
5029 (clobber (match_operand:SI 3 "gen_reg_operand" ""))]
5030 "find_single_use (operands[0], insn, 0)
5031 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
5032 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
5033 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
5034 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
5037 /* @r{Get the constant we are comparing against, C, and see what it
5038 looks like sign-extended to 16 bits. Then see what constant
5039 could be XOR'ed with C to get the sign-extended value.} */
5041 int c = INTVAL (operands[2]);
5042 int sextc = (c << 16) >> 16;
5043 int xorv = c ^ sextc;
5045 operands[4] = GEN_INT (xorv);
5046 operands[5] = GEN_INT (sextc);
5050 To avoid confusion, don't write a single @code{define_split} that
5051 accepts some insns that match some @code{define_insn} as well as some
5052 insns that don't. Instead, write two separate @code{define_split}
5053 definitions, one for the insns that are valid and one for the insns that
5056 The splitter is allowed to split jump instructions into sequence of
5057 jumps or create new jumps in while splitting non-jump instructions. As
5058 the central flowgraph and branch prediction information needs to be updated,
5059 several restriction apply.
5061 Splitting of jump instruction into sequence that over by another jump
5062 instruction is always valid, as compiler expect identical behavior of new
5063 jump. When new sequence contains multiple jump instructions or new labels,
5064 more assistance is needed. Splitter is required to create only unconditional
5065 jumps, or simple conditional jump instructions. Additionally it must attach a
5066 @code{REG_BR_PROB} note to each conditional jump. A global variable
5067 @code{split_branch_probability} holds the probability of the original branch in case
5068 it was an simple conditional jump, @minus{}1 otherwise. To simplify
5069 recomputing of edge frequencies, the new sequence is required to have only
5070 forward jumps to the newly created labels.
5072 @findex define_insn_and_split
5073 For the common case where the pattern of a define_split exactly matches the
5074 pattern of a define_insn, use @code{define_insn_and_split}. It looks like
5078 (define_insn_and_split
5079 [@var{insn-pattern}]
5081 "@var{output-template}"
5082 "@var{split-condition}"
5083 [@var{new-insn-pattern-1}
5084 @var{new-insn-pattern-2}
5086 "@var{preparation-statements}"
5087 [@var{insn-attributes}])
5091 @var{insn-pattern}, @var{condition}, @var{output-template}, and
5092 @var{insn-attributes} are used as in @code{define_insn}. The
5093 @var{new-insn-pattern} vector and the @var{preparation-statements} are used as
5094 in a @code{define_split}. The @var{split-condition} is also used as in
5095 @code{define_split}, with the additional behavior that if the condition starts
5096 with @samp{&&}, the condition used for the split will be the constructed as a
5097 logical ``and'' of the split condition with the insn condition. For example,
5101 (define_insn_and_split "zero_extendhisi2_and"
5102 [(set (match_operand:SI 0 "register_operand" "=r")
5103 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
5104 (clobber (reg:CC 17))]
5105 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
5107 "&& reload_completed"
5108 [(parallel [(set (match_dup 0)
5109 (and:SI (match_dup 0) (const_int 65535)))
5110 (clobber (reg:CC 17))])]
5112 [(set_attr "type" "alu1")])
5116 In this case, the actual split condition will be
5117 @samp{TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed}.
5119 The @code{define_insn_and_split} construction provides exactly the same
5120 functionality as two separate @code{define_insn} and @code{define_split}
5121 patterns. It exists for compactness, and as a maintenance tool to prevent
5122 having to ensure the two patterns' templates match.
5126 @node Including Patterns
5127 @section Including Patterns in Machine Descriptions.
5128 @cindex insn includes
5131 The @code{include} pattern tells the compiler tools where to
5132 look for patterns that are in files other than in the file
5133 @file{.md}. This is used only at build time and there is no preprocessing allowed.
5147 (include "filestuff")
5151 Where @var{pathname} is a string that specifies the location of the file,
5152 specifies the include file to be in @file{gcc/config/target/filestuff}. The
5153 directory @file{gcc/config/target} is regarded as the default directory.
5156 Machine descriptions may be split up into smaller more manageable subsections
5157 and placed into subdirectories.
5163 (include "BOGUS/filestuff")
5167 the include file is specified to be in @file{gcc/config/@var{target}/BOGUS/filestuff}.
5169 Specifying an absolute path for the include file such as;
5172 (include "/u2/BOGUS/filestuff")
5175 is permitted but is not encouraged.
5177 @subsection RTL Generation Tool Options for Directory Search
5178 @cindex directory options .md
5179 @cindex options, directory search
5180 @cindex search options
5182 The @option{-I@var{dir}} option specifies directories to search for machine descriptions.
5187 genrecog -I/p1/abc/proc1 -I/p2/abcd/pro2 target.md
5192 Add the directory @var{dir} to the head of the list of directories to be
5193 searched for header files. This can be used to override a system machine definition
5194 file, substituting your own version, since these directories are
5195 searched before the default machine description file directories. If you use more than
5196 one @option{-I} option, the directories are scanned in left-to-right
5197 order; the standard default directory come after.
5202 @node Peephole Definitions
5203 @section Machine-Specific Peephole Optimizers
5204 @cindex peephole optimizer definitions
5205 @cindex defining peephole optimizers
5207 In addition to instruction patterns the @file{md} file may contain
5208 definitions of machine-specific peephole optimizations.
5210 The combiner does not notice certain peephole optimizations when the data
5211 flow in the program does not suggest that it should try them. For example,
5212 sometimes two consecutive insns related in purpose can be combined even
5213 though the second one does not appear to use a register computed in the
5214 first one. A machine-specific peephole optimizer can detect such
5217 There are two forms of peephole definitions that may be used. The
5218 original @code{define_peephole} is run at assembly output time to
5219 match insns and substitute assembly text. Use of @code{define_peephole}
5222 A newer @code{define_peephole2} matches insns and substitutes new
5223 insns. The @code{peephole2} pass is run after register allocation
5224 but before scheduling, which may result in much better code for
5225 targets that do scheduling.
5228 * define_peephole:: RTL to Text Peephole Optimizers
5229 * define_peephole2:: RTL to RTL Peephole Optimizers
5234 @node define_peephole
5235 @subsection RTL to Text Peephole Optimizers
5236 @findex define_peephole
5239 A definition looks like this:
5243 [@var{insn-pattern-1}
5244 @var{insn-pattern-2}
5248 "@var{optional-insn-attributes}")
5252 The last string operand may be omitted if you are not using any
5253 machine-specific information in this machine description. If present,
5254 it must obey the same rules as in a @code{define_insn}.
5256 In this skeleton, @var{insn-pattern-1} and so on are patterns to match
5257 consecutive insns. The optimization applies to a sequence of insns when
5258 @var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches
5259 the next, and so on.
5261 Each of the insns matched by a peephole must also match a
5262 @code{define_insn}. Peepholes are checked only at the last stage just
5263 before code generation, and only optionally. Therefore, any insn which
5264 would match a peephole but no @code{define_insn} will cause a crash in code
5265 generation in an unoptimized compilation, or at various optimization
5268 The operands of the insns are matched with @code{match_operands},
5269 @code{match_operator}, and @code{match_dup}, as usual. What is not
5270 usual is that the operand numbers apply to all the insn patterns in the
5271 definition. So, you can check for identical operands in two insns by
5272 using @code{match_operand} in one insn and @code{match_dup} in the
5275 The operand constraints used in @code{match_operand} patterns do not have
5276 any direct effect on the applicability of the peephole, but they will
5277 be validated afterward, so make sure your constraints are general enough
5278 to apply whenever the peephole matches. If the peephole matches
5279 but the constraints are not satisfied, the compiler will crash.
5281 It is safe to omit constraints in all the operands of the peephole; or
5282 you can write constraints which serve as a double-check on the criteria
5285 Once a sequence of insns matches the patterns, the @var{condition} is
5286 checked. This is a C expression which makes the final decision whether to
5287 perform the optimization (we do so if the expression is nonzero). If
5288 @var{condition} is omitted (in other words, the string is empty) then the
5289 optimization is applied to every sequence of insns that matches the
5292 The defined peephole optimizations are applied after register allocation
5293 is complete. Therefore, the peephole definition can check which
5294 operands have ended up in which kinds of registers, just by looking at
5297 @findex prev_active_insn
5298 The way to refer to the operands in @var{condition} is to write
5299 @code{operands[@var{i}]} for operand number @var{i} (as matched by
5300 @code{(match_operand @var{i} @dots{})}). Use the variable @code{insn}
5301 to refer to the last of the insns being matched; use
5302 @code{prev_active_insn} to find the preceding insns.
5304 @findex dead_or_set_p
5305 When optimizing computations with intermediate results, you can use
5306 @var{condition} to match only when the intermediate results are not used
5307 elsewhere. Use the C expression @code{dead_or_set_p (@var{insn},
5308 @var{op})}, where @var{insn} is the insn in which you expect the value
5309 to be used for the last time (from the value of @code{insn}, together
5310 with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate
5311 value (from @code{operands[@var{i}]}).
5313 Applying the optimization means replacing the sequence of insns with one
5314 new insn. The @var{template} controls ultimate output of assembler code
5315 for this combined insn. It works exactly like the template of a
5316 @code{define_insn}. Operand numbers in this template are the same ones
5317 used in matching the original sequence of insns.
5319 The result of a defined peephole optimizer does not need to match any of
5320 the insn patterns in the machine description; it does not even have an
5321 opportunity to match them. The peephole optimizer definition itself serves
5322 as the insn pattern to control how the insn is output.
5324 Defined peephole optimizers are run as assembler code is being output,
5325 so the insns they produce are never combined or rearranged in any way.
5327 Here is an example, taken from the 68000 machine description:
5331 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
5332 (set (match_operand:DF 0 "register_operand" "=f")
5333 (match_operand:DF 1 "register_operand" "ad"))]
5334 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
5337 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
5339 output_asm_insn ("move.l %1,(sp)", xoperands);
5340 output_asm_insn ("move.l %1,-(sp)", operands);
5341 return "fmove.d (sp)+,%0";
5343 output_asm_insn ("movel %1,sp@@", xoperands);
5344 output_asm_insn ("movel %1,sp@@-", operands);
5345 return "fmoved sp@@+,%0";
5351 The effect of this optimization is to change
5377 If a peephole matches a sequence including one or more jump insns, you must
5378 take account of the flags such as @code{CC_REVERSED} which specify that the
5379 condition codes are represented in an unusual manner. The compiler
5380 automatically alters any ordinary conditional jumps which occur in such
5381 situations, but the compiler cannot alter jumps which have been replaced by
5382 peephole optimizations. So it is up to you to alter the assembler code
5383 that the peephole produces. Supply C code to write the assembler output,
5384 and in this C code check the condition code status flags and change the
5385 assembler code as appropriate.
5388 @var{insn-pattern-1} and so on look @emph{almost} like the second
5389 operand of @code{define_insn}. There is one important difference: the
5390 second operand of @code{define_insn} consists of one or more RTX's
5391 enclosed in square brackets. Usually, there is only one: then the same
5392 action can be written as an element of a @code{define_peephole}. But
5393 when there are multiple actions in a @code{define_insn}, they are
5394 implicitly enclosed in a @code{parallel}. Then you must explicitly
5395 write the @code{parallel}, and the square brackets within it, in the
5396 @code{define_peephole}. Thus, if an insn pattern looks like this,
5399 (define_insn "divmodsi4"
5400 [(set (match_operand:SI 0 "general_operand" "=d")
5401 (div:SI (match_operand:SI 1 "general_operand" "0")
5402 (match_operand:SI 2 "general_operand" "dmsK")))
5403 (set (match_operand:SI 3 "general_operand" "=d")
5404 (mod:SI (match_dup 1) (match_dup 2)))]
5406 "divsl%.l %2,%3:%0")
5410 then the way to mention this insn in a peephole is as follows:
5416 [(set (match_operand:SI 0 "general_operand" "=d")
5417 (div:SI (match_operand:SI 1 "general_operand" "0")
5418 (match_operand:SI 2 "general_operand" "dmsK")))
5419 (set (match_operand:SI 3 "general_operand" "=d")
5420 (mod:SI (match_dup 1) (match_dup 2)))])
5427 @node define_peephole2
5428 @subsection RTL to RTL Peephole Optimizers
5429 @findex define_peephole2
5431 The @code{define_peephole2} definition tells the compiler how to
5432 substitute one sequence of instructions for another sequence,
5433 what additional scratch registers may be needed and what their
5438 [@var{insn-pattern-1}
5439 @var{insn-pattern-2}
5442 [@var{new-insn-pattern-1}
5443 @var{new-insn-pattern-2}
5445 "@var{preparation-statements}")
5448 The definition is almost identical to @code{define_split}
5449 (@pxref{Insn Splitting}) except that the pattern to match is not a
5450 single instruction, but a sequence of instructions.
5452 It is possible to request additional scratch registers for use in the
5453 output template. If appropriate registers are not free, the pattern
5454 will simply not match.
5456 @findex match_scratch
5458 Scratch registers are requested with a @code{match_scratch} pattern at
5459 the top level of the input pattern. The allocated register (initially) will
5460 be dead at the point requested within the original sequence. If the scratch
5461 is used at more than a single point, a @code{match_dup} pattern at the
5462 top level of the input pattern marks the last position in the input sequence
5463 at which the register must be available.
5465 Here is an example from the IA-32 machine description:
5469 [(match_scratch:SI 2 "r")
5470 (parallel [(set (match_operand:SI 0 "register_operand" "")
5471 (match_operator:SI 3 "arith_or_logical_operator"
5473 (match_operand:SI 1 "memory_operand" "")]))
5474 (clobber (reg:CC 17))])]
5475 "! optimize_size && ! TARGET_READ_MODIFY"
5476 [(set (match_dup 2) (match_dup 1))
5477 (parallel [(set (match_dup 0)
5478 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
5479 (clobber (reg:CC 17))])]
5484 This pattern tries to split a load from its use in the hopes that we'll be
5485 able to schedule around the memory load latency. It allocates a single
5486 @code{SImode} register of class @code{GENERAL_REGS} (@code{"r"}) that needs
5487 to be live only at the point just before the arithmetic.
5489 A real example requiring extended scratch lifetimes is harder to come by,
5490 so here's a silly made-up example:
5494 [(match_scratch:SI 4 "r")
5495 (set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
5496 (set (match_operand:SI 2 "" "") (match_dup 1))
5498 (set (match_operand:SI 3 "" "") (match_dup 1))]
5499 "/* @r{determine 1 does not overlap 0 and 2} */"
5500 [(set (match_dup 4) (match_dup 1))
5501 (set (match_dup 0) (match_dup 4))
5502 (set (match_dup 2) (match_dup 4))]
5503 (set (match_dup 3) (match_dup 4))]
5508 If we had not added the @code{(match_dup 4)} in the middle of the input
5509 sequence, it might have been the case that the register we chose at the
5510 beginning of the sequence is killed by the first or second @code{set}.
5514 @node Insn Attributes
5515 @section Instruction Attributes
5516 @cindex insn attributes
5517 @cindex instruction attributes
5519 In addition to describing the instruction supported by the target machine,
5520 the @file{md} file also defines a group of @dfn{attributes} and a set of
5521 values for each. Every generated insn is assigned a value for each attribute.
5522 One possible attribute would be the effect that the insn has on the machine's
5523 condition code. This attribute can then be used by @code{NOTICE_UPDATE_CC}
5524 to track the condition codes.
5527 * Defining Attributes:: Specifying attributes and their values.
5528 * Expressions:: Valid expressions for attribute values.
5529 * Tagging Insns:: Assigning attribute values to insns.
5530 * Attr Example:: An example of assigning attributes.
5531 * Insn Lengths:: Computing the length of insns.
5532 * Constant Attributes:: Defining attributes that are constant.
5533 * Delay Slots:: Defining delay slots required for a machine.
5534 * Processor pipeline description:: Specifying information for insn scheduling.
5539 @node Defining Attributes
5540 @subsection Defining Attributes and their Values
5541 @cindex defining attributes and their values
5542 @cindex attributes, defining
5545 The @code{define_attr} expression is used to define each attribute required
5546 by the target machine. It looks like:
5549 (define_attr @var{name} @var{list-of-values} @var{default})
5552 @var{name} is a string specifying the name of the attribute being defined.
5554 @var{list-of-values} is either a string that specifies a comma-separated
5555 list of values that can be assigned to the attribute, or a null string to
5556 indicate that the attribute takes numeric values.
5558 @var{default} is an attribute expression that gives the value of this
5559 attribute for insns that match patterns whose definition does not include
5560 an explicit value for this attribute. @xref{Attr Example}, for more
5561 information on the handling of defaults. @xref{Constant Attributes},
5562 for information on attributes that do not depend on any particular insn.
5565 For each defined attribute, a number of definitions are written to the
5566 @file{insn-attr.h} file. For cases where an explicit set of values is
5567 specified for an attribute, the following are defined:
5571 A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}.
5574 An enumerated class is defined for @samp{attr_@var{name}} with
5575 elements of the form @samp{@var{upper-name}_@var{upper-value}} where
5576 the attribute name and value are first converted to uppercase.
5579 A function @samp{get_attr_@var{name}} is defined that is passed an insn and
5580 returns the attribute value for that insn.
5583 For example, if the following is present in the @file{md} file:
5586 (define_attr "type" "branch,fp,load,store,arith" @dots{})
5590 the following lines will be written to the file @file{insn-attr.h}.
5593 #define HAVE_ATTR_type
5594 enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD,
5595 TYPE_STORE, TYPE_ARITH@};
5596 extern enum attr_type get_attr_type ();
5599 If the attribute takes numeric values, no @code{enum} type will be
5600 defined and the function to obtain the attribute's value will return
5606 @subsection Attribute Expressions
5607 @cindex attribute expressions
5609 RTL expressions used to define attributes use the codes described above
5610 plus a few specific to attribute definitions, to be discussed below.
5611 Attribute value expressions must have one of the following forms:
5614 @cindex @code{const_int} and attributes
5615 @item (const_int @var{i})
5616 The integer @var{i} specifies the value of a numeric attribute. @var{i}
5617 must be non-negative.
5619 The value of a numeric attribute can be specified either with a
5620 @code{const_int}, or as an integer represented as a string in
5621 @code{const_string}, @code{eq_attr} (see below), @code{attr},
5622 @code{symbol_ref}, simple arithmetic expressions, and @code{set_attr}
5623 overrides on specific instructions (@pxref{Tagging Insns}).
5625 @cindex @code{const_string} and attributes
5626 @item (const_string @var{value})
5627 The string @var{value} specifies a constant attribute value.
5628 If @var{value} is specified as @samp{"*"}, it means that the default value of
5629 the attribute is to be used for the insn containing this expression.
5630 @samp{"*"} obviously cannot be used in the @var{default} expression
5631 of a @code{define_attr}.
5633 If the attribute whose value is being specified is numeric, @var{value}
5634 must be a string containing a non-negative integer (normally
5635 @code{const_int} would be used in this case). Otherwise, it must
5636 contain one of the valid values for the attribute.
5638 @cindex @code{if_then_else} and attributes
5639 @item (if_then_else @var{test} @var{true-value} @var{false-value})
5640 @var{test} specifies an attribute test, whose format is defined below.
5641 The value of this expression is @var{true-value} if @var{test} is true,
5642 otherwise it is @var{false-value}.
5644 @cindex @code{cond} and attributes
5645 @item (cond [@var{test1} @var{value1} @dots{}] @var{default})
5646 The first operand of this expression is a vector containing an even
5647 number of expressions and consisting of pairs of @var{test} and @var{value}
5648 expressions. The value of the @code{cond} expression is that of the
5649 @var{value} corresponding to the first true @var{test} expression. If
5650 none of the @var{test} expressions are true, the value of the @code{cond}
5651 expression is that of the @var{default} expression.
5654 @var{test} expressions can have one of the following forms:
5657 @cindex @code{const_int} and attribute tests
5658 @item (const_int @var{i})
5659 This test is true if @var{i} is nonzero and false otherwise.
5661 @cindex @code{not} and attributes
5662 @cindex @code{ior} and attributes
5663 @cindex @code{and} and attributes
5664 @item (not @var{test})
5665 @itemx (ior @var{test1} @var{test2})
5666 @itemx (and @var{test1} @var{test2})
5667 These tests are true if the indicated logical function is true.
5669 @cindex @code{match_operand} and attributes
5670 @item (match_operand:@var{m} @var{n} @var{pred} @var{constraints})
5671 This test is true if operand @var{n} of the insn whose attribute value
5672 is being determined has mode @var{m} (this part of the test is ignored
5673 if @var{m} is @code{VOIDmode}) and the function specified by the string
5674 @var{pred} returns a nonzero value when passed operand @var{n} and mode
5675 @var{m} (this part of the test is ignored if @var{pred} is the null
5678 The @var{constraints} operand is ignored and should be the null string.
5680 @cindex @code{le} and attributes
5681 @cindex @code{leu} and attributes
5682 @cindex @code{lt} and attributes
5683 @cindex @code{gt} and attributes
5684 @cindex @code{gtu} and attributes
5685 @cindex @code{ge} and attributes
5686 @cindex @code{geu} and attributes
5687 @cindex @code{ne} and attributes
5688 @cindex @code{eq} and attributes
5689 @cindex @code{plus} and attributes
5690 @cindex @code{minus} and attributes
5691 @cindex @code{mult} and attributes
5692 @cindex @code{div} and attributes
5693 @cindex @code{mod} and attributes
5694 @cindex @code{abs} and attributes
5695 @cindex @code{neg} and attributes
5696 @cindex @code{ashift} and attributes
5697 @cindex @code{lshiftrt} and attributes
5698 @cindex @code{ashiftrt} and attributes
5699 @item (le @var{arith1} @var{arith2})
5700 @itemx (leu @var{arith1} @var{arith2})
5701 @itemx (lt @var{arith1} @var{arith2})
5702 @itemx (ltu @var{arith1} @var{arith2})
5703 @itemx (gt @var{arith1} @var{arith2})
5704 @itemx (gtu @var{arith1} @var{arith2})
5705 @itemx (ge @var{arith1} @var{arith2})
5706 @itemx (geu @var{arith1} @var{arith2})
5707 @itemx (ne @var{arith1} @var{arith2})
5708 @itemx (eq @var{arith1} @var{arith2})
5709 These tests are true if the indicated comparison of the two arithmetic
5710 expressions is true. Arithmetic expressions are formed with
5711 @code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod},
5712 @code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not},
5713 @code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions.
5716 @code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn
5717 Lengths},for additional forms). @code{symbol_ref} is a string
5718 denoting a C expression that yields an @code{int} when evaluated by the
5719 @samp{get_attr_@dots{}} routine. It should normally be a global
5723 @item (eq_attr @var{name} @var{value})
5724 @var{name} is a string specifying the name of an attribute.
5726 @var{value} is a string that is either a valid value for attribute
5727 @var{name}, a comma-separated list of values, or @samp{!} followed by a
5728 value or list. If @var{value} does not begin with a @samp{!}, this
5729 test is true if the value of the @var{name} attribute of the current
5730 insn is in the list specified by @var{value}. If @var{value} begins
5731 with a @samp{!}, this test is true if the attribute's value is
5732 @emph{not} in the specified list.
5737 (eq_attr "type" "load,store")
5744 (ior (eq_attr "type" "load") (eq_attr "type" "store"))
5747 If @var{name} specifies an attribute of @samp{alternative}, it refers to the
5748 value of the compiler variable @code{which_alternative}
5749 (@pxref{Output Statement}) and the values must be small integers. For
5753 (eq_attr "alternative" "2,3")
5760 (ior (eq (symbol_ref "which_alternative") (const_int 2))
5761 (eq (symbol_ref "which_alternative") (const_int 3)))
5764 Note that, for most attributes, an @code{eq_attr} test is simplified in cases
5765 where the value of the attribute being tested is known for all insns matching
5766 a particular pattern. This is by far the most common case.
5769 @item (attr_flag @var{name})
5770 The value of an @code{attr_flag} expression is true if the flag
5771 specified by @var{name} is true for the @code{insn} currently being
5774 @var{name} is a string specifying one of a fixed set of flags to test.
5775 Test the flags @code{forward} and @code{backward} to determine the
5776 direction of a conditional branch. Test the flags @code{very_likely},
5777 @code{likely}, @code{very_unlikely}, and @code{unlikely} to determine
5778 if a conditional branch is expected to be taken.
5780 If the @code{very_likely} flag is true, then the @code{likely} flag is also
5781 true. Likewise for the @code{very_unlikely} and @code{unlikely} flags.
5783 This example describes a conditional branch delay slot which
5784 can be nullified for forward branches that are taken (annul-true) or
5785 for backward branches which are not taken (annul-false).
5788 (define_delay (eq_attr "type" "cbranch")
5789 [(eq_attr "in_branch_delay" "true")
5790 (and (eq_attr "in_branch_delay" "true")
5791 (attr_flag "forward"))
5792 (and (eq_attr "in_branch_delay" "true")
5793 (attr_flag "backward"))])
5796 The @code{forward} and @code{backward} flags are false if the current
5797 @code{insn} being scheduled is not a conditional branch.
5799 The @code{very_likely} and @code{likely} flags are true if the
5800 @code{insn} being scheduled is not a conditional branch.
5801 The @code{very_unlikely} and @code{unlikely} flags are false if the
5802 @code{insn} being scheduled is not a conditional branch.
5804 @code{attr_flag} is only used during delay slot scheduling and has no
5805 meaning to other passes of the compiler.
5808 @item (attr @var{name})
5809 The value of another attribute is returned. This is most useful
5810 for numeric attributes, as @code{eq_attr} and @code{attr_flag}
5811 produce more efficient code for non-numeric attributes.
5817 @subsection Assigning Attribute Values to Insns
5818 @cindex tagging insns
5819 @cindex assigning attribute values to insns
5821 The value assigned to an attribute of an insn is primarily determined by
5822 which pattern is matched by that insn (or which @code{define_peephole}
5823 generated it). Every @code{define_insn} and @code{define_peephole} can
5824 have an optional last argument to specify the values of attributes for
5825 matching insns. The value of any attribute not specified in a particular
5826 insn is set to the default value for that attribute, as specified in its
5827 @code{define_attr}. Extensive use of default values for attributes
5828 permits the specification of the values for only one or two attributes
5829 in the definition of most insn patterns, as seen in the example in the
5832 The optional last argument of @code{define_insn} and
5833 @code{define_peephole} is a vector of expressions, each of which defines
5834 the value for a single attribute. The most general way of assigning an
5835 attribute's value is to use a @code{set} expression whose first operand is an
5836 @code{attr} expression giving the name of the attribute being set. The
5837 second operand of the @code{set} is an attribute expression
5838 (@pxref{Expressions}) giving the value of the attribute.
5840 When the attribute value depends on the @samp{alternative} attribute
5841 (i.e., which is the applicable alternative in the constraint of the
5842 insn), the @code{set_attr_alternative} expression can be used. It
5843 allows the specification of a vector of attribute expressions, one for
5847 When the generality of arbitrary attribute expressions is not required,
5848 the simpler @code{set_attr} expression can be used, which allows
5849 specifying a string giving either a single attribute value or a list
5850 of attribute values, one for each alternative.
5852 The form of each of the above specifications is shown below. In each case,
5853 @var{name} is a string specifying the attribute to be set.
5856 @item (set_attr @var{name} @var{value-string})
5857 @var{value-string} is either a string giving the desired attribute value,
5858 or a string containing a comma-separated list giving the values for
5859 succeeding alternatives. The number of elements must match the number
5860 of alternatives in the constraint of the insn pattern.
5862 Note that it may be useful to specify @samp{*} for some alternative, in
5863 which case the attribute will assume its default value for insns matching
5866 @findex set_attr_alternative
5867 @item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}])
5868 Depending on the alternative of the insn, the value will be one of the
5869 specified values. This is a shorthand for using a @code{cond} with
5870 tests on the @samp{alternative} attribute.
5873 @item (set (attr @var{name}) @var{value})
5874 The first operand of this @code{set} must be the special RTL expression
5875 @code{attr}, whose sole operand is a string giving the name of the
5876 attribute being set. @var{value} is the value of the attribute.
5879 The following shows three different ways of representing the same
5880 attribute value specification:
5883 (set_attr "type" "load,store,arith")
5885 (set_attr_alternative "type"
5886 [(const_string "load") (const_string "store")
5887 (const_string "arith")])
5890 (cond [(eq_attr "alternative" "1") (const_string "load")
5891 (eq_attr "alternative" "2") (const_string "store")]
5892 (const_string "arith")))
5896 @findex define_asm_attributes
5897 The @code{define_asm_attributes} expression provides a mechanism to
5898 specify the attributes assigned to insns produced from an @code{asm}
5899 statement. It has the form:
5902 (define_asm_attributes [@var{attr-sets}])
5906 where @var{attr-sets} is specified the same as for both the
5907 @code{define_insn} and the @code{define_peephole} expressions.
5909 These values will typically be the ``worst case'' attribute values. For
5910 example, they might indicate that the condition code will be clobbered.
5912 A specification for a @code{length} attribute is handled specially. The
5913 way to compute the length of an @code{asm} insn is to multiply the
5914 length specified in the expression @code{define_asm_attributes} by the
5915 number of machine instructions specified in the @code{asm} statement,
5916 determined by counting the number of semicolons and newlines in the
5917 string. Therefore, the value of the @code{length} attribute specified
5918 in a @code{define_asm_attributes} should be the maximum possible length
5919 of a single machine instruction.
5924 @subsection Example of Attribute Specifications
5925 @cindex attribute specifications example
5926 @cindex attribute specifications
5928 The judicious use of defaulting is important in the efficient use of
5929 insn attributes. Typically, insns are divided into @dfn{types} and an
5930 attribute, customarily called @code{type}, is used to represent this
5931 value. This attribute is normally used only to define the default value
5932 for other attributes. An example will clarify this usage.
5934 Assume we have a RISC machine with a condition code and in which only
5935 full-word operations are performed in registers. Let us assume that we
5936 can divide all insns into loads, stores, (integer) arithmetic
5937 operations, floating point operations, and branches.
5939 Here we will concern ourselves with determining the effect of an insn on
5940 the condition code and will limit ourselves to the following possible
5941 effects: The condition code can be set unpredictably (clobbered), not
5942 be changed, be set to agree with the results of the operation, or only
5943 changed if the item previously set into the condition code has been
5946 Here is part of a sample @file{md} file for such a machine:
5949 (define_attr "type" "load,store,arith,fp,branch" (const_string "arith"))
5951 (define_attr "cc" "clobber,unchanged,set,change0"
5952 (cond [(eq_attr "type" "load")
5953 (const_string "change0")
5954 (eq_attr "type" "store,branch")
5955 (const_string "unchanged")
5956 (eq_attr "type" "arith")
5957 (if_then_else (match_operand:SI 0 "" "")
5958 (const_string "set")
5959 (const_string "clobber"))]
5960 (const_string "clobber")))
5963 [(set (match_operand:SI 0 "general_operand" "=r,r,m")
5964 (match_operand:SI 1 "general_operand" "r,m,r"))]
5970 [(set_attr "type" "arith,load,store")])
5973 Note that we assume in the above example that arithmetic operations
5974 performed on quantities smaller than a machine word clobber the condition
5975 code since they will set the condition code to a value corresponding to the
5981 @subsection Computing the Length of an Insn
5982 @cindex insn lengths, computing
5983 @cindex computing the length of an insn
5985 For many machines, multiple types of branch instructions are provided, each
5986 for different length branch displacements. In most cases, the assembler
5987 will choose the correct instruction to use. However, when the assembler
5988 cannot do so, GCC can when a special attribute, the @code{length}
5989 attribute, is defined. This attribute must be defined to have numeric
5990 values by specifying a null string in its @code{define_attr}.
5992 In the case of the @code{length} attribute, two additional forms of
5993 arithmetic terms are allowed in test expressions:
5996 @cindex @code{match_dup} and attributes
5997 @item (match_dup @var{n})
5998 This refers to the address of operand @var{n} of the current insn, which
5999 must be a @code{label_ref}.
6001 @cindex @code{pc} and attributes
6003 This refers to the address of the @emph{current} insn. It might have
6004 been more consistent with other usage to make this the address of the
6005 @emph{next} insn but this would be confusing because the length of the
6006 current insn is to be computed.
6009 @cindex @code{addr_vec}, length of
6010 @cindex @code{addr_diff_vec}, length of
6011 For normal insns, the length will be determined by value of the
6012 @code{length} attribute. In the case of @code{addr_vec} and
6013 @code{addr_diff_vec} insn patterns, the length is computed as
6014 the number of vectors multiplied by the size of each vector.
6016 Lengths are measured in addressable storage units (bytes).
6018 The following macros can be used to refine the length computation:
6021 @findex ADJUST_INSN_LENGTH
6022 @item ADJUST_INSN_LENGTH (@var{insn}, @var{length})
6023 If defined, modifies the length assigned to instruction @var{insn} as a
6024 function of the context in which it is used. @var{length} is an lvalue
6025 that contains the initially computed length of the insn and should be
6026 updated with the correct length of the insn.
6028 This macro will normally not be required. A case in which it is
6029 required is the ROMP@. On this machine, the size of an @code{addr_vec}
6030 insn must be increased by two to compensate for the fact that alignment
6034 @findex get_attr_length
6035 The routine that returns @code{get_attr_length} (the value of the
6036 @code{length} attribute) can be used by the output routine to
6037 determine the form of the branch instruction to be written, as the
6038 example below illustrates.
6040 As an example of the specification of variable-length branches, consider
6041 the IBM 360. If we adopt the convention that a register will be set to
6042 the starting address of a function, we can jump to labels within 4k of
6043 the start using a four-byte instruction. Otherwise, we need a six-byte
6044 sequence to load the address from memory and then branch to it.
6046 On such a machine, a pattern for a branch instruction might be specified
6052 (label_ref (match_operand 0 "" "")))]
6055 return (get_attr_length (insn) == 4
6056 ? "b %l0" : "l r15,=a(%l0); br r15");
6058 [(set (attr "length")
6059 (if_then_else (lt (match_dup 0) (const_int 4096))
6066 @node Constant Attributes
6067 @subsection Constant Attributes
6068 @cindex constant attributes
6070 A special form of @code{define_attr}, where the expression for the
6071 default value is a @code{const} expression, indicates an attribute that
6072 is constant for a given run of the compiler. Constant attributes may be
6073 used to specify which variety of processor is used. For example,
6076 (define_attr "cpu" "m88100,m88110,m88000"
6078 (cond [(symbol_ref "TARGET_88100") (const_string "m88100")
6079 (symbol_ref "TARGET_88110") (const_string "m88110")]
6080 (const_string "m88000"))))
6082 (define_attr "memory" "fast,slow"
6084 (if_then_else (symbol_ref "TARGET_FAST_MEM")
6085 (const_string "fast")
6086 (const_string "slow"))))
6089 The routine generated for constant attributes has no parameters as it
6090 does not depend on any particular insn. RTL expressions used to define
6091 the value of a constant attribute may use the @code{symbol_ref} form,
6092 but may not use either the @code{match_operand} form or @code{eq_attr}
6093 forms involving insn attributes.
6098 @subsection Delay Slot Scheduling
6099 @cindex delay slots, defining
6101 The insn attribute mechanism can be used to specify the requirements for
6102 delay slots, if any, on a target machine. An instruction is said to
6103 require a @dfn{delay slot} if some instructions that are physically
6104 after the instruction are executed as if they were located before it.
6105 Classic examples are branch and call instructions, which often execute
6106 the following instruction before the branch or call is performed.
6108 On some machines, conditional branch instructions can optionally
6109 @dfn{annul} instructions in the delay slot. This means that the
6110 instruction will not be executed for certain branch outcomes. Both
6111 instructions that annul if the branch is true and instructions that
6112 annul if the branch is false are supported.
6114 Delay slot scheduling differs from instruction scheduling in that
6115 determining whether an instruction needs a delay slot is dependent only
6116 on the type of instruction being generated, not on data flow between the
6117 instructions. See the next section for a discussion of data-dependent
6118 instruction scheduling.
6120 @findex define_delay
6121 The requirement of an insn needing one or more delay slots is indicated
6122 via the @code{define_delay} expression. It has the following form:
6125 (define_delay @var{test}
6126 [@var{delay-1} @var{annul-true-1} @var{annul-false-1}
6127 @var{delay-2} @var{annul-true-2} @var{annul-false-2}
6131 @var{test} is an attribute test that indicates whether this
6132 @code{define_delay} applies to a particular insn. If so, the number of
6133 required delay slots is determined by the length of the vector specified
6134 as the second argument. An insn placed in delay slot @var{n} must
6135 satisfy attribute test @var{delay-n}. @var{annul-true-n} is an
6136 attribute test that specifies which insns may be annulled if the branch
6137 is true. Similarly, @var{annul-false-n} specifies which insns in the
6138 delay slot may be annulled if the branch is false. If annulling is not
6139 supported for that delay slot, @code{(nil)} should be coded.
6141 For example, in the common case where branch and call insns require
6142 a single delay slot, which may contain any insn other than a branch or
6143 call, the following would be placed in the @file{md} file:
6146 (define_delay (eq_attr "type" "branch,call")
6147 [(eq_attr "type" "!branch,call") (nil) (nil)])
6150 Multiple @code{define_delay} expressions may be specified. In this
6151 case, each such expression specifies different delay slot requirements
6152 and there must be no insn for which tests in two @code{define_delay}
6153 expressions are both true.
6155 For example, if we have a machine that requires one delay slot for branches
6156 but two for calls, no delay slot can contain a branch or call insn,
6157 and any valid insn in the delay slot for the branch can be annulled if the
6158 branch is true, we might represent this as follows:
6161 (define_delay (eq_attr "type" "branch")
6162 [(eq_attr "type" "!branch,call")
6163 (eq_attr "type" "!branch,call")
6166 (define_delay (eq_attr "type" "call")
6167 [(eq_attr "type" "!branch,call") (nil) (nil)
6168 (eq_attr "type" "!branch,call") (nil) (nil)])
6170 @c the above is *still* too long. --mew 4feb93
6174 @node Processor pipeline description
6175 @subsection Specifying processor pipeline description
6176 @cindex processor pipeline description
6177 @cindex processor functional units
6178 @cindex instruction latency time
6179 @cindex interlock delays
6180 @cindex data dependence delays
6181 @cindex reservation delays
6182 @cindex pipeline hazard recognizer
6183 @cindex automaton based pipeline description
6184 @cindex regular expressions
6185 @cindex deterministic finite state automaton
6186 @cindex automaton based scheduler
6190 To achieve better performance, most modern processors
6191 (super-pipelined, superscalar @acronym{RISC}, and @acronym{VLIW}
6192 processors) have many @dfn{functional units} on which several
6193 instructions can be executed simultaneously. An instruction starts
6194 execution if its issue conditions are satisfied. If not, the
6195 instruction is stalled until its conditions are satisfied. Such
6196 @dfn{interlock (pipeline) delay} causes interruption of the fetching
6197 of successor instructions (or demands nop instructions, e.g.@: for some
6200 There are two major kinds of interlock delays in modern processors.
6201 The first one is a data dependence delay determining @dfn{instruction
6202 latency time}. The instruction execution is not started until all
6203 source data have been evaluated by prior instructions (there are more
6204 complex cases when the instruction execution starts even when the data
6205 are not available but will be ready in given time after the
6206 instruction execution start). Taking the data dependence delays into
6207 account is simple. The data dependence (true, output, and
6208 anti-dependence) delay between two instructions is given by a
6209 constant. In most cases this approach is adequate. The second kind
6210 of interlock delays is a reservation delay. The reservation delay
6211 means that two instructions under execution will be in need of shared
6212 processors resources, i.e.@: buses, internal registers, and/or
6213 functional units, which are reserved for some time. Taking this kind
6214 of delay into account is complex especially for modern @acronym{RISC}
6217 The task of exploiting more processor parallelism is solved by an
6218 instruction scheduler. For a better solution to this problem, the
6219 instruction scheduler has to have an adequate description of the
6220 processor parallelism (or @dfn{pipeline description}). GCC
6221 machine descriptions describe processor parallelism and functional
6222 unit reservations for groups of instructions with the aid of
6223 @dfn{regular expressions}.
6225 The GCC instruction scheduler uses a @dfn{pipeline hazard recognizer} to
6226 figure out the possibility of the instruction issue by the processor
6227 on a given simulated processor cycle. The pipeline hazard recognizer is
6228 automatically generated from the processor pipeline description. The
6229 pipeline hazard recognizer generated from the machine description
6230 is based on a deterministic finite state automaton (@acronym{DFA}):
6231 the instruction issue is possible if there is a transition from one
6232 automaton state to another one. This algorithm is very fast, and
6233 furthermore, its speed is not dependent on processor
6234 complexity@footnote{However, the size of the automaton depends on
6235 processor complexity. To limit this effect, machine descriptions
6236 can split orthogonal parts of the machine description among several
6237 automata: but then, since each of these must be stepped independently,
6238 this does cause a small decrease in the algorithm's performance.}.
6240 @cindex automaton based pipeline description
6241 The rest of this section describes the directives that constitute
6242 an automaton-based processor pipeline description. The order of
6243 these constructions within the machine description file is not
6246 @findex define_automaton
6247 @cindex pipeline hazard recognizer
6248 The following optional construction describes names of automata
6249 generated and used for the pipeline hazards recognition. Sometimes
6250 the generated finite state automaton used by the pipeline hazard
6251 recognizer is large. If we use more than one automaton and bind functional
6252 units to the automata, the total size of the automata is usually
6253 less than the size of the single automaton. If there is no one such
6254 construction, only one finite state automaton is generated.
6257 (define_automaton @var{automata-names})
6260 @var{automata-names} is a string giving names of the automata. The
6261 names are separated by commas. All the automata should have unique names.
6262 The automaton name is used in the constructions @code{define_cpu_unit} and
6263 @code{define_query_cpu_unit}.
6265 @findex define_cpu_unit
6266 @cindex processor functional units
6267 Each processor functional unit used in the description of instruction
6268 reservations should be described by the following construction.
6271 (define_cpu_unit @var{unit-names} [@var{automaton-name}])
6274 @var{unit-names} is a string giving the names of the functional units
6275 separated by commas. Don't use name @samp{nothing}, it is reserved
6278 @var{automaton-name} is a string giving the name of the automaton with
6279 which the unit is bound. The automaton should be described in
6280 construction @code{define_automaton}. You should give
6281 @dfn{automaton-name}, if there is a defined automaton.
6283 The assignment of units to automata are constrained by the uses of the
6284 units in insn reservations. The most important constraint is: if a
6285 unit reservation is present on a particular cycle of an alternative
6286 for an insn reservation, then some unit from the same automaton must
6287 be present on the same cycle for the other alternatives of the insn
6288 reservation. The rest of the constraints are mentioned in the
6289 description of the subsequent constructions.
6291 @findex define_query_cpu_unit
6292 @cindex querying function unit reservations
6293 The following construction describes CPU functional units analogously
6294 to @code{define_cpu_unit}. The reservation of such units can be
6295 queried for an automaton state. The instruction scheduler never
6296 queries reservation of functional units for given automaton state. So
6297 as a rule, you don't need this construction. This construction could
6298 be used for future code generation goals (e.g.@: to generate
6299 @acronym{VLIW} insn templates).
6302 (define_query_cpu_unit @var{unit-names} [@var{automaton-name}])
6305 @var{unit-names} is a string giving names of the functional units
6306 separated by commas.
6308 @var{automaton-name} is a string giving the name of the automaton with
6309 which the unit is bound.
6311 @findex define_insn_reservation
6312 @cindex instruction latency time
6313 @cindex regular expressions
6315 The following construction is the major one to describe pipeline
6316 characteristics of an instruction.
6319 (define_insn_reservation @var{insn-name} @var{default_latency}
6320 @var{condition} @var{regexp})
6323 @var{default_latency} is a number giving latency time of the
6324 instruction. There is an important difference between the old
6325 description and the automaton based pipeline description. The latency
6326 time is used for all dependencies when we use the old description. In
6327 the automaton based pipeline description, the given latency time is only
6328 used for true dependencies. The cost of anti-dependencies is always
6329 zero and the cost of output dependencies is the difference between
6330 latency times of the producing and consuming insns (if the difference
6331 is negative, the cost is considered to be zero). You can always
6332 change the default costs for any description by using the target hook
6333 @code{TARGET_SCHED_ADJUST_COST} (@pxref{Scheduling}).
6335 @var{insn-name} is a string giving the internal name of the insn. The
6336 internal names are used in constructions @code{define_bypass} and in
6337 the automaton description file generated for debugging. The internal
6338 name has nothing in common with the names in @code{define_insn}. It is a
6339 good practice to use insn classes described in the processor manual.
6341 @var{condition} defines what RTL insns are described by this
6342 construction. You should remember that you will be in trouble if
6343 @var{condition} for two or more different
6344 @code{define_insn_reservation} constructions is TRUE for an insn. In
6345 this case what reservation will be used for the insn is not defined.
6346 Such cases are not checked during generation of the pipeline hazards
6347 recognizer because in general recognizing that two conditions may have
6348 the same value is quite difficult (especially if the conditions
6349 contain @code{symbol_ref}). It is also not checked during the
6350 pipeline hazard recognizer work because it would slow down the
6351 recognizer considerably.
6353 @var{regexp} is a string describing the reservation of the cpu's functional
6354 units by the instruction. The reservations are described by a regular
6355 expression according to the following syntax:
6358 regexp = regexp "," oneof
6361 oneof = oneof "|" allof
6364 allof = allof "+" repeat
6367 repeat = element "*" number
6370 element = cpu_function_unit_name
6379 @samp{,} is used for describing the start of the next cycle in
6383 @samp{|} is used for describing a reservation described by the first
6384 regular expression @strong{or} a reservation described by the second
6385 regular expression @strong{or} etc.
6388 @samp{+} is used for describing a reservation described by the first
6389 regular expression @strong{and} a reservation described by the
6390 second regular expression @strong{and} etc.
6393 @samp{*} is used for convenience and simply means a sequence in which
6394 the regular expression are repeated @var{number} times with cycle
6395 advancing (see @samp{,}).
6398 @samp{cpu_function_unit_name} denotes reservation of the named
6402 @samp{reservation_name} --- see description of construction
6403 @samp{define_reservation}.
6406 @samp{nothing} denotes no unit reservations.
6409 @findex define_reservation
6410 Sometimes unit reservations for different insns contain common parts.
6411 In such case, you can simplify the pipeline description by describing
6412 the common part by the following construction
6415 (define_reservation @var{reservation-name} @var{regexp})
6418 @var{reservation-name} is a string giving name of @var{regexp}.
6419 Functional unit names and reservation names are in the same name
6420 space. So the reservation names should be different from the
6421 functional unit names and can not be the reserved name @samp{nothing}.
6423 @findex define_bypass
6424 @cindex instruction latency time
6426 The following construction is used to describe exceptions in the
6427 latency time for given instruction pair. This is so called bypasses.
6430 (define_bypass @var{number} @var{out_insn_names} @var{in_insn_names}
6434 @var{number} defines when the result generated by the instructions
6435 given in string @var{out_insn_names} will be ready for the
6436 instructions given in string @var{in_insn_names}. The instructions in
6437 the string are separated by commas.
6439 @var{guard} is an optional string giving the name of a C function which
6440 defines an additional guard for the bypass. The function will get the
6441 two insns as parameters. If the function returns zero the bypass will
6442 be ignored for this case. The additional guard is necessary to
6443 recognize complicated bypasses, e.g.@: when the consumer is only an address
6444 of insn @samp{store} (not a stored value).
6446 @findex exclusion_set
6447 @findex presence_set
6448 @findex final_presence_set
6450 @findex final_absence_set
6453 The following five constructions are usually used to describe
6454 @acronym{VLIW} processors, or more precisely, to describe a placement
6455 of small instructions into @acronym{VLIW} instruction slots. They
6456 can be used for @acronym{RISC} processors, too.
6459 (exclusion_set @var{unit-names} @var{unit-names})
6460 (presence_set @var{unit-names} @var{patterns})
6461 (final_presence_set @var{unit-names} @var{patterns})
6462 (absence_set @var{unit-names} @var{patterns})
6463 (final_absence_set @var{unit-names} @var{patterns})
6466 @var{unit-names} is a string giving names of functional units
6467 separated by commas.
6469 @var{patterns} is a string giving patterns of functional units
6470 separated by comma. Currently pattern is one unit or units
6471 separated by white-spaces.
6473 The first construction (@samp{exclusion_set}) means that each
6474 functional unit in the first string can not be reserved simultaneously
6475 with a unit whose name is in the second string and vice versa. For
6476 example, the construction is useful for describing processors
6477 (e.g.@: some SPARC processors) with a fully pipelined floating point
6478 functional unit which can execute simultaneously only single floating
6479 point insns or only double floating point insns.
6481 The second construction (@samp{presence_set}) means that each
6482 functional unit in the first string can not be reserved unless at
6483 least one of pattern of units whose names are in the second string is
6484 reserved. This is an asymmetric relation. For example, it is useful
6485 for description that @acronym{VLIW} @samp{slot1} is reserved after
6486 @samp{slot0} reservation. We could describe it by the following
6490 (presence_set "slot1" "slot0")
6493 Or @samp{slot1} is reserved only after @samp{slot0} and unit @samp{b0}
6494 reservation. In this case we could write
6497 (presence_set "slot1" "slot0 b0")
6500 The third construction (@samp{final_presence_set}) is analogous to
6501 @samp{presence_set}. The difference between them is when checking is
6502 done. When an instruction is issued in given automaton state
6503 reflecting all current and planned unit reservations, the automaton
6504 state is changed. The first state is a source state, the second one
6505 is a result state. Checking for @samp{presence_set} is done on the
6506 source state reservation, checking for @samp{final_presence_set} is
6507 done on the result reservation. This construction is useful to
6508 describe a reservation which is actually two subsequent reservations.
6509 For example, if we use
6512 (presence_set "slot1" "slot0")
6515 the following insn will be never issued (because @samp{slot1} requires
6516 @samp{slot0} which is absent in the source state).
6519 (define_reservation "insn_and_nop" "slot0 + slot1")
6522 but it can be issued if we use analogous @samp{final_presence_set}.
6524 The forth construction (@samp{absence_set}) means that each functional
6525 unit in the first string can be reserved only if each pattern of units
6526 whose names are in the second string is not reserved. This is an
6527 asymmetric relation (actually @samp{exclusion_set} is analogous to
6528 this one but it is symmetric). For example, it is useful for
6529 description that @acronym{VLIW} @samp{slot0} can not be reserved after
6530 @samp{slot1} or @samp{slot2} reservation. We could describe it by the
6531 following construction
6534 (absence_set "slot2" "slot0, slot1")
6537 Or @samp{slot2} can not be reserved if @samp{slot0} and unit @samp{b0}
6538 are reserved or @samp{slot1} and unit @samp{b1} are reserved. In
6539 this case we could write
6542 (absence_set "slot2" "slot0 b0, slot1 b1")
6545 All functional units mentioned in a set should belong to the same
6548 The last construction (@samp{final_absence_set}) is analogous to
6549 @samp{absence_set} but checking is done on the result (state)
6550 reservation. See comments for @samp{final_presence_set}.
6552 @findex automata_option
6553 @cindex deterministic finite state automaton
6554 @cindex nondeterministic finite state automaton
6555 @cindex finite state automaton minimization
6556 You can control the generator of the pipeline hazard recognizer with
6557 the following construction.
6560 (automata_option @var{options})
6563 @var{options} is a string giving options which affect the generated
6564 code. Currently there are the following options:
6568 @dfn{no-minimization} makes no minimization of the automaton. This is
6569 only worth to do when we are debugging the description and need to
6570 look more accurately at reservations of states.
6573 @dfn{time} means printing additional time statistics about
6574 generation of automata.
6577 @dfn{v} means a generation of the file describing the result automata.
6578 The file has suffix @samp{.dfa} and can be used for the description
6579 verification and debugging.
6582 @dfn{w} means a generation of warning instead of error for
6583 non-critical errors.
6586 @dfn{ndfa} makes nondeterministic finite state automata. This affects
6587 the treatment of operator @samp{|} in the regular expressions. The
6588 usual treatment of the operator is to try the first alternative and,
6589 if the reservation is not possible, the second alternative. The
6590 nondeterministic treatment means trying all alternatives, some of them
6591 may be rejected by reservations in the subsequent insns.
6594 @dfn{progress} means output of a progress bar showing how many states
6595 were generated so far for automaton being processed. This is useful
6596 during debugging a @acronym{DFA} description. If you see too many
6597 generated states, you could interrupt the generator of the pipeline
6598 hazard recognizer and try to figure out a reason for generation of the
6602 As an example, consider a superscalar @acronym{RISC} machine which can
6603 issue three insns (two integer insns and one floating point insn) on
6604 the cycle but can finish only two insns. To describe this, we define
6605 the following functional units.
6608 (define_cpu_unit "i0_pipeline, i1_pipeline, f_pipeline")
6609 (define_cpu_unit "port0, port1")
6612 All simple integer insns can be executed in any integer pipeline and
6613 their result is ready in two cycles. The simple integer insns are
6614 issued into the first pipeline unless it is reserved, otherwise they
6615 are issued into the second pipeline. Integer division and
6616 multiplication insns can be executed only in the second integer
6617 pipeline and their results are ready correspondingly in 8 and 4
6618 cycles. The integer division is not pipelined, i.e.@: the subsequent
6619 integer division insn can not be issued until the current division
6620 insn finished. Floating point insns are fully pipelined and their
6621 results are ready in 3 cycles. Where the result of a floating point
6622 insn is used by an integer insn, an additional delay of one cycle is
6623 incurred. To describe all of this we could specify
6626 (define_cpu_unit "div")
6628 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
6629 "(i0_pipeline | i1_pipeline), (port0 | port1)")
6631 (define_insn_reservation "mult" 4 (eq_attr "type" "mult")
6632 "i1_pipeline, nothing*2, (port0 | port1)")
6634 (define_insn_reservation "div" 8 (eq_attr "type" "div")
6635 "i1_pipeline, div*7, div + (port0 | port1)")
6637 (define_insn_reservation "float" 3 (eq_attr "type" "float")
6638 "f_pipeline, nothing, (port0 | port1))
6640 (define_bypass 4 "float" "simple,mult,div")
6643 To simplify the description we could describe the following reservation
6646 (define_reservation "finish" "port0|port1")
6649 and use it in all @code{define_insn_reservation} as in the following
6653 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
6654 "(i0_pipeline | i1_pipeline), finish")
6660 @node Conditional Execution
6661 @section Conditional Execution
6662 @cindex conditional execution
6665 A number of architectures provide for some form of conditional
6666 execution, or predication. The hallmark of this feature is the
6667 ability to nullify most of the instructions in the instruction set.
6668 When the instruction set is large and not entirely symmetric, it
6669 can be quite tedious to describe these forms directly in the
6670 @file{.md} file. An alternative is the @code{define_cond_exec} template.
6672 @findex define_cond_exec
6675 [@var{predicate-pattern}]
6677 "@var{output-template}")
6680 @var{predicate-pattern} is the condition that must be true for the
6681 insn to be executed at runtime and should match a relational operator.
6682 One can use @code{match_operator} to match several relational operators
6683 at once. Any @code{match_operand} operands must have no more than one
6686 @var{condition} is a C expression that must be true for the generated
6689 @findex current_insn_predicate
6690 @var{output-template} is a string similar to the @code{define_insn}
6691 output template (@pxref{Output Template}), except that the @samp{*}
6692 and @samp{@@} special cases do not apply. This is only useful if the
6693 assembly text for the predicate is a simple prefix to the main insn.
6694 In order to handle the general case, there is a global variable
6695 @code{current_insn_predicate} that will contain the entire predicate
6696 if the current insn is predicated, and will otherwise be @code{NULL}.
6698 When @code{define_cond_exec} is used, an implicit reference to
6699 the @code{predicable} instruction attribute is made.
6700 @xref{Insn Attributes}. This attribute must be boolean (i.e.@: have
6701 exactly two elements in its @var{list-of-values}). Further, it must
6702 not be used with complex expressions. That is, the default and all
6703 uses in the insns must be a simple constant, not dependent on the
6704 alternative or anything else.
6706 For each @code{define_insn} for which the @code{predicable}
6707 attribute is true, a new @code{define_insn} pattern will be
6708 generated that matches a predicated version of the instruction.
6712 (define_insn "addsi"
6713 [(set (match_operand:SI 0 "register_operand" "r")
6714 (plus:SI (match_operand:SI 1 "register_operand" "r")
6715 (match_operand:SI 2 "register_operand" "r")))]
6720 [(ne (match_operand:CC 0 "register_operand" "c")
6727 generates a new pattern
6732 (ne (match_operand:CC 3 "register_operand" "c") (const_int 0))
6733 (set (match_operand:SI 0 "register_operand" "r")
6734 (plus:SI (match_operand:SI 1 "register_operand" "r")
6735 (match_operand:SI 2 "register_operand" "r"))))]
6736 "(@var{test2}) && (@var{test1})"
6737 "(%3) add %2,%1,%0")
6742 @node Constant Definitions
6743 @section Constant Definitions
6744 @cindex constant definitions
6745 @findex define_constants
6747 Using literal constants inside instruction patterns reduces legibility and
6748 can be a maintenance problem.
6750 To overcome this problem, you may use the @code{define_constants}
6751 expression. It contains a vector of name-value pairs. From that
6752 point on, wherever any of the names appears in the MD file, it is as
6753 if the corresponding value had been written instead. You may use
6754 @code{define_constants} multiple times; each appearance adds more
6755 constants to the table. It is an error to redefine a constant with
6758 To come back to the a29k load multiple example, instead of
6762 [(match_parallel 0 "load_multiple_operation"
6763 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
6764 (match_operand:SI 2 "memory_operand" "m"))
6766 (clobber (reg:SI 179))])]
6782 [(match_parallel 0 "load_multiple_operation"
6783 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
6784 (match_operand:SI 2 "memory_operand" "m"))
6786 (clobber (reg:SI R_CR))])]
6791 The constants that are defined with a define_constant are also output
6792 in the insn-codes.h header file as #defines.
6797 @cindex macros in @file{.md} files
6799 Ports often need to define similar patterns for more than one machine
6800 mode or for more than one rtx code. GCC provides some simple macro
6801 facilities to make this process easier.
6804 * Mode Macros:: Generating variations of patterns for different modes.
6805 * Code Macros:: Doing the same for codes.
6809 @subsection Mode Macros
6810 @cindex mode macros in @file{.md} files
6812 Ports often need to define similar patterns for two or more different modes.
6817 If a processor has hardware support for both single and double
6818 floating-point arithmetic, the @code{SFmode} patterns tend to be
6819 very similar to the @code{DFmode} ones.
6822 If a port uses @code{SImode} pointers in one configuration and
6823 @code{DImode} pointers in another, it will usually have very similar
6824 @code{SImode} and @code{DImode} patterns for manipulating pointers.
6827 Mode macros allow several patterns to be instantiated from one
6828 @file{.md} file template. They can be used with any type of
6829 rtx-based construct, such as a @code{define_insn},
6830 @code{define_split}, or @code{define_peephole2}.
6833 * Defining Mode Macros:: Defining a new mode macro.
6834 * Substitutions:: Combining mode macros with substitutions
6835 * Examples:: Examples
6838 @node Defining Mode Macros
6839 @subsubsection Defining Mode Macros
6840 @findex define_mode_macro
6842 The syntax for defining a mode macro is:
6845 (define_mode_macro @var{name} [(@var{mode1} "@var{cond1}") ... (@var{moden} "@var{condn}")])
6848 This allows subsequent @file{.md} file constructs to use the mode suffix
6849 @code{:@var{name}}. Every construct that does so will be expanded
6850 @var{n} times, once with every use of @code{:@var{name}} replaced by
6851 @code{:@var{mode1}}, once with every use replaced by @code{:@var{mode2}},
6852 and so on. In the expansion for a particular @var{modei}, every
6853 C condition will also require that @var{condi} be true.
6858 (define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
6861 defines a new mode suffix @code{:P}. Every construct that uses
6862 @code{:P} will be expanded twice, once with every @code{:P} replaced
6863 by @code{:SI} and once with every @code{:P} replaced by @code{:DI}.
6864 The @code{:SI} version will only apply if @code{Pmode == SImode} and
6865 the @code{:DI} version will only apply if @code{Pmode == DImode}.
6867 As with other @file{.md} conditions, an empty string is treated
6868 as ``always true''. @code{(@var{mode} "")} can also be abbreviated
6869 to @code{@var{mode}}. For example:
6872 (define_mode_macro GPR [SI (DI "TARGET_64BIT")])
6875 means that the @code{:DI} expansion only applies if @code{TARGET_64BIT}
6876 but that the @code{:SI} expansion has no such constraint.
6878 Macros are applied in the order they are defined. This can be
6879 significant if two macros are used in a construct that requires
6880 substitutions. @xref{Substitutions}.
6883 @subsubsection Substitution in Mode Macros
6884 @findex define_mode_attr
6886 If an @file{.md} file construct uses mode macros, each version of the
6887 construct will often need slightly different strings or modes. For
6892 When a @code{define_expand} defines several @code{add@var{m}3} patterns
6893 (@pxref{Standard Names}), each expander will need to use the
6894 appropriate mode name for @var{m}.
6897 When a @code{define_insn} defines several instruction patterns,
6898 each instruction will often use a different assembler mnemonic.
6901 When a @code{define_insn} requires operands with different modes,
6902 using a macro for one of the operand modes usually requires a specific
6903 mode for the other operand(s).
6906 GCC supports such variations through a system of ``mode attributes''.
6907 There are two standard attributes: @code{mode}, which is the name of
6908 the mode in lower case, and @code{MODE}, which is the same thing in
6909 upper case. You can define other attributes using:
6912 (define_mode_attr @var{name} [(@var{mode1} "@var{value1}") ... (@var{moden} "@var{valuen}")])
6915 where @var{name} is the name of the attribute and @var{valuei}
6916 is the value associated with @var{modei}.
6918 When GCC replaces some @var{:macro} with @var{:mode}, it will scan
6919 each string and mode in the pattern for sequences of the form
6920 @code{<@var{macro}:@var{attr}>}, where @var{attr} is the name of a
6921 mode attribute. If the attribute is defined for @var{mode}, the whole
6922 @code{<...>} sequence will be replaced by the appropriate attribute
6925 For example, suppose an @file{.md} file has:
6928 (define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
6929 (define_mode_attr load [(SI "lw") (DI "ld")])
6932 If one of the patterns that uses @code{:P} contains the string
6933 @code{"<P:load>\t%0,%1"}, the @code{SI} version of that pattern
6934 will use @code{"lw\t%0,%1"} and the @code{DI} version will use
6937 Here is an example of using an attribute for a mode:
6940 (define_mode_macro LONG [SI DI])
6941 (define_mode_attr SHORT [(SI "HI") (DI "SI")])
6943 (sign_extend:LONG (match_operand:<LONG:SHORT> ...)) ...)
6946 The @code{@var{macro}:} prefix may be omitted, in which case the
6947 substitution will be attempted for every macro expansion.
6950 @subsubsection Mode Macro Examples
6952 Here is an example from the MIPS port. It defines the following
6953 modes and attributes (among others):
6956 (define_mode_macro GPR [SI (DI "TARGET_64BIT")])
6957 (define_mode_attr d [(SI "") (DI "d")])
6960 and uses the following template to define both @code{subsi3}
6964 (define_insn "sub<mode>3"
6965 [(set (match_operand:GPR 0 "register_operand" "=d")
6966 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
6967 (match_operand:GPR 2 "register_operand" "d")))]
6970 [(set_attr "type" "arith")
6971 (set_attr "mode" "<MODE>")])
6974 This is exactly equivalent to:
6977 (define_insn "subsi3"
6978 [(set (match_operand:SI 0 "register_operand" "=d")
6979 (minus:SI (match_operand:SI 1 "register_operand" "d")
6980 (match_operand:SI 2 "register_operand" "d")))]
6983 [(set_attr "type" "arith")
6984 (set_attr "mode" "SI")])
6986 (define_insn "subdi3"
6987 [(set (match_operand:DI 0 "register_operand" "=d")
6988 (minus:DI (match_operand:DI 1 "register_operand" "d")
6989 (match_operand:DI 2 "register_operand" "d")))]
6992 [(set_attr "type" "arith")
6993 (set_attr "mode" "DI")])
6997 @subsection Code Macros
6998 @cindex code macros in @file{.md} files
6999 @findex define_code_macro
7000 @findex define_code_attr
7002 Code macros operate in a similar way to mode macros. @xref{Mode Macros}.
7007 (define_code_macro @var{name} [(@var{code1} "@var{cond1}") ... (@var{coden} "@var{condn}")])
7010 defines a pseudo rtx code @var{name} that can be instantiated as
7011 @var{codei} if condition @var{condi} is true. Each @var{codei}
7012 must have the same rtx format. @xref{RTL Classes}.
7014 As with mode macros, each pattern that uses @var{name} will be
7015 expanded @var{n} times, once with all uses of @var{name} replaced by
7016 @var{code1}, once with all uses replaced by @var{code2}, and so on.
7017 @xref{Defining Mode Macros}.
7019 It is possible to define attributes for codes as well as for modes.
7020 There are two standard code attributes: @code{code}, the name of the
7021 code in lower case, and @code{CODE}, the name of the code in upper case.
7022 Other attributes are defined using:
7025 (define_code_attr @var{name} [(@var{code1} "@var{value1}") ... (@var{coden} "@var{valuen}")])
7028 Here's an example of code macros in action, taken from the MIPS port:
7031 (define_code_macro any_cond [unordered ordered unlt unge uneq ltgt unle ungt
7032 eq ne gt ge lt le gtu geu ltu leu])
7034 (define_expand "b<code>"
7036 (if_then_else (any_cond:CC (cc0)
7038 (label_ref (match_operand 0 ""))
7042 gen_conditional_branch (operands, <CODE>);
7047 This is equivalent to:
7050 (define_expand "bunordered"
7052 (if_then_else (unordered:CC (cc0)
7054 (label_ref (match_operand 0 ""))
7058 gen_conditional_branch (operands, UNORDERED);
7062 (define_expand "bordered"
7064 (if_then_else (ordered:CC (cc0)
7066 (label_ref (match_operand 0 ""))
7070 gen_conditional_branch (operands, ORDERED);