1 @c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1996, 1998, 1999, 2000, 2001,
2 @c 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
3 @c This is part of the GCC manual.
4 @c For copying conditions, see the file gcc.texi.
8 @chapter Machine Descriptions
9 @cindex machine descriptions
11 A machine description has two parts: a file of instruction patterns
12 (@file{.md} file) and a C header file of macro definitions.
14 The @file{.md} file for a target machine contains a pattern for each
15 instruction that the target machine supports (or at least each instruction
16 that is worth telling the compiler about). It may also contain comments.
17 A semicolon causes the rest of the line to be a comment, unless the semicolon
18 is inside a quoted string.
20 See the next chapter for information on the C header file.
23 * Overview:: How the machine description is used.
24 * Patterns:: How to write instruction patterns.
25 * Example:: An explained example of a @code{define_insn} pattern.
26 * RTL Template:: The RTL template defines what insns match a pattern.
27 * Output Template:: The output template says how to make assembler code
29 * Output Statement:: For more generality, write C code to output
31 * Predicates:: Controlling what kinds of operands can be used
33 * Constraints:: Fine-tuning operand selection.
34 * Standard Names:: Names mark patterns to use for code generation.
35 * Pattern Ordering:: When the order of patterns makes a difference.
36 * Dependent Patterns:: Having one pattern may make you need another.
37 * Jump Patterns:: Special considerations for patterns for jump insns.
38 * Looping Patterns:: How to define patterns for special looping insns.
39 * Insn Canonicalizations::Canonicalization of Instructions
40 * Expander Definitions::Generating a sequence of several RTL insns
41 for a standard operation.
42 * Insn Splitting:: Splitting Instructions into Multiple Instructions.
43 * Including Patterns:: Including Patterns in Machine Descriptions.
44 * Peephole Definitions::Defining machine-specific peephole optimizations.
45 * Insn Attributes:: Specifying the value of attributes for generated insns.
46 * Conditional Execution::Generating @code{define_insn} patterns for
48 * Constant Definitions::Defining symbolic constants that can be used in the
50 * Macros:: Using macros to generate patterns from a template.
54 @section Overview of How the Machine Description is Used
56 There are three main conversions that happen in the compiler:
61 The front end reads the source code and builds a parse tree.
64 The parse tree is used to generate an RTL insn list based on named
68 The insn list is matched against the RTL templates to produce assembler
73 For the generate pass, only the names of the insns matter, from either a
74 named @code{define_insn} or a @code{define_expand}. The compiler will
75 choose the pattern with the right name and apply the operands according
76 to the documentation later in this chapter, without regard for the RTL
77 template or operand constraints. Note that the names the compiler looks
78 for are hard-coded in the compiler---it will ignore unnamed patterns and
79 patterns with names it doesn't know about, but if you don't provide a
80 named pattern it needs, it will abort.
82 If a @code{define_insn} is used, the template given is inserted into the
83 insn list. If a @code{define_expand} is used, one of three things
84 happens, based on the condition logic. The condition logic may manually
85 create new insns for the insn list, say via @code{emit_insn()}, and
86 invoke @code{DONE}. For certain named patterns, it may invoke @code{FAIL} to tell the
87 compiler to use an alternate way of performing that task. If it invokes
88 neither @code{DONE} nor @code{FAIL}, the template given in the pattern
89 is inserted, as if the @code{define_expand} were a @code{define_insn}.
91 Once the insn list is generated, various optimization passes convert,
92 replace, and rearrange the insns in the insn list. This is where the
93 @code{define_split} and @code{define_peephole} patterns get used, for
96 Finally, the insn list's RTL is matched up with the RTL templates in the
97 @code{define_insn} patterns, and those patterns are used to emit the
98 final assembly code. For this purpose, each named @code{define_insn}
99 acts like it's unnamed, since the names are ignored.
102 @section Everything about Instruction Patterns
104 @cindex instruction patterns
107 Each instruction pattern contains an incomplete RTL expression, with pieces
108 to be filled in later, operand constraints that restrict how the pieces can
109 be filled in, and an output pattern or C code to generate the assembler
110 output, all wrapped up in a @code{define_insn} expression.
112 A @code{define_insn} is an RTL expression containing four or five operands:
116 An optional name. The presence of a name indicate that this instruction
117 pattern can perform a certain standard job for the RTL-generation
118 pass of the compiler. This pass knows certain names and will use
119 the instruction patterns with those names, if the names are defined
120 in the machine description.
122 The absence of a name is indicated by writing an empty string
123 where the name should go. Nameless instruction patterns are never
124 used for generating RTL code, but they may permit several simpler insns
125 to be combined later on.
127 Names that are not thus known and used in RTL-generation have no
128 effect; they are equivalent to no name at all.
130 For the purpose of debugging the compiler, you may also specify a
131 name beginning with the @samp{*} character. Such a name is used only
132 for identifying the instruction in RTL dumps; it is entirely equivalent
133 to having a nameless pattern for all other purposes.
136 The @dfn{RTL template} (@pxref{RTL Template}) is a vector of incomplete
137 RTL expressions which show what the instruction should look like. It is
138 incomplete because it may contain @code{match_operand},
139 @code{match_operator}, and @code{match_dup} expressions that stand for
140 operands of the instruction.
142 If the vector has only one element, that element is the template for the
143 instruction pattern. If the vector has multiple elements, then the
144 instruction pattern is a @code{parallel} expression containing the
148 @cindex pattern conditions
149 @cindex conditions, in patterns
150 A condition. This is a string which contains a C expression that is
151 the final test to decide whether an insn body matches this pattern.
153 @cindex named patterns and conditions
154 For a named pattern, the condition (if present) may not depend on
155 the data in the insn being matched, but only the target-machine-type
156 flags. The compiler needs to test these conditions during
157 initialization in order to learn exactly which named instructions are
158 available in a particular run.
161 For nameless patterns, the condition is applied only when matching an
162 individual insn, and only after the insn has matched the pattern's
163 recognition template. The insn's operands may be found in the vector
164 @code{operands}. For an insn where the condition has once matched, it
165 can't be used to control register allocation, for example by excluding
166 certain hard registers or hard register combinations.
169 The @dfn{output template}: a string that says how to output matching
170 insns as assembler code. @samp{%} in this string specifies where
171 to substitute the value of an operand. @xref{Output Template}.
173 When simple substitution isn't general enough, you can specify a piece
174 of C code to compute the output. @xref{Output Statement}.
177 Optionally, a vector containing the values of attributes for insns matching
178 this pattern. @xref{Insn Attributes}.
182 @section Example of @code{define_insn}
183 @cindex @code{define_insn} example
185 Here is an actual example of an instruction pattern, for the 68000/68020.
190 (match_operand:SI 0 "general_operand" "rm"))]
194 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
196 return \"cmpl #0,%0\";
201 This can also be written using braced strings:
206 (match_operand:SI 0 "general_operand" "rm"))]
209 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
215 This is an instruction that sets the condition codes based on the value of
216 a general operand. It has no condition, so any insn whose RTL description
217 has the form shown may be handled according to this pattern. The name
218 @samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL generation
219 pass that, when it is necessary to test such a value, an insn to do so
220 can be constructed using this pattern.
222 The output control string is a piece of C code which chooses which
223 output template to return based on the kind of operand and the specific
224 type of CPU for which code is being generated.
226 @samp{"rm"} is an operand constraint. Its meaning is explained below.
229 @section RTL Template
230 @cindex RTL insn template
231 @cindex generating insns
232 @cindex insns, generating
233 @cindex recognizing insns
234 @cindex insns, recognizing
236 The RTL template is used to define which insns match the particular pattern
237 and how to find their operands. For named patterns, the RTL template also
238 says how to construct an insn from specified operands.
240 Construction involves substituting specified operands into a copy of the
241 template. Matching involves determining the values that serve as the
242 operands in the insn being matched. Both of these activities are
243 controlled by special expression types that direct matching and
244 substitution of the operands.
247 @findex match_operand
248 @item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint})
249 This expression is a placeholder for operand number @var{n} of
250 the insn. When constructing an insn, operand number @var{n}
251 will be substituted at this point. When matching an insn, whatever
252 appears at this position in the insn will be taken as operand
253 number @var{n}; but it must satisfy @var{predicate} or this instruction
254 pattern will not match at all.
256 Operand numbers must be chosen consecutively counting from zero in
257 each instruction pattern. There may be only one @code{match_operand}
258 expression in the pattern for each operand number. Usually operands
259 are numbered in the order of appearance in @code{match_operand}
260 expressions. In the case of a @code{define_expand}, any operand numbers
261 used only in @code{match_dup} expressions have higher values than all
262 other operand numbers.
264 @var{predicate} is a string that is the name of a function that
265 accepts two arguments, an expression and a machine mode.
266 @xref{Predicates}. During matching, the function will be called with
267 the putative operand as the expression and @var{m} as the mode
268 argument (if @var{m} is not specified, @code{VOIDmode} will be used,
269 which normally causes @var{predicate} to accept any mode). If it
270 returns zero, this instruction pattern fails to match.
271 @var{predicate} may be an empty string; then it means no test is to be
272 done on the operand, so anything which occurs in this position is
275 Most of the time, @var{predicate} will reject modes other than @var{m}---but
276 not always. For example, the predicate @code{address_operand} uses
277 @var{m} as the mode of memory ref that the address should be valid for.
278 Many predicates accept @code{const_int} nodes even though their mode is
281 @var{constraint} controls reloading and the choice of the best register
282 class to use for a value, as explained later (@pxref{Constraints}).
283 If the constraint would be an empty string, it can be omitted.
285 People are often unclear on the difference between the constraint and the
286 predicate. The predicate helps decide whether a given insn matches the
287 pattern. The constraint plays no role in this decision; instead, it
288 controls various decisions in the case of an insn which does match.
290 @findex match_scratch
291 @item (match_scratch:@var{m} @var{n} @var{constraint})
292 This expression is also a placeholder for operand number @var{n}
293 and indicates that operand must be a @code{scratch} or @code{reg}
296 When matching patterns, this is equivalent to
299 (match_operand:@var{m} @var{n} "scratch_operand" @var{pred})
302 but, when generating RTL, it produces a (@code{scratch}:@var{m})
305 If the last few expressions in a @code{parallel} are @code{clobber}
306 expressions whose operands are either a hard register or
307 @code{match_scratch}, the combiner can add or delete them when
308 necessary. @xref{Side Effects}.
311 @item (match_dup @var{n})
312 This expression is also a placeholder for operand number @var{n}.
313 It is used when the operand needs to appear more than once in the
316 In construction, @code{match_dup} acts just like @code{match_operand}:
317 the operand is substituted into the insn being constructed. But in
318 matching, @code{match_dup} behaves differently. It assumes that operand
319 number @var{n} has already been determined by a @code{match_operand}
320 appearing earlier in the recognition template, and it matches only an
321 identical-looking expression.
323 Note that @code{match_dup} should not be used to tell the compiler that
324 a particular register is being used for two operands (example:
325 @code{add} that adds one register to another; the second register is
326 both an input operand and the output operand). Use a matching
327 constraint (@pxref{Simple Constraints}) for those. @code{match_dup} is for the cases where one
328 operand is used in two places in the template, such as an instruction
329 that computes both a quotient and a remainder, where the opcode takes
330 two input operands but the RTL template has to refer to each of those
331 twice; once for the quotient pattern and once for the remainder pattern.
333 @findex match_operator
334 @item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}])
335 This pattern is a kind of placeholder for a variable RTL expression
338 When constructing an insn, it stands for an RTL expression whose
339 expression code is taken from that of operand @var{n}, and whose
340 operands are constructed from the patterns @var{operands}.
342 When matching an expression, it matches an expression if the function
343 @var{predicate} returns nonzero on that expression @emph{and} the
344 patterns @var{operands} match the operands of the expression.
346 Suppose that the function @code{commutative_operator} is defined as
347 follows, to match any expression whose operator is one of the
348 commutative arithmetic operators of RTL and whose mode is @var{mode}:
352 commutative_integer_operator (x, mode)
354 enum machine_mode mode;
356 enum rtx_code code = GET_CODE (x);
357 if (GET_MODE (x) != mode)
359 return (GET_RTX_CLASS (code) == RTX_COMM_ARITH
360 || code == EQ || code == NE);
364 Then the following pattern will match any RTL expression consisting
365 of a commutative operator applied to two general operands:
368 (match_operator:SI 3 "commutative_operator"
369 [(match_operand:SI 1 "general_operand" "g")
370 (match_operand:SI 2 "general_operand" "g")])
373 Here the vector @code{[@var{operands}@dots{}]} contains two patterns
374 because the expressions to be matched all contain two operands.
376 When this pattern does match, the two operands of the commutative
377 operator are recorded as operands 1 and 2 of the insn. (This is done
378 by the two instances of @code{match_operand}.) Operand 3 of the insn
379 will be the entire commutative expression: use @code{GET_CODE
380 (operands[3])} to see which commutative operator was used.
382 The machine mode @var{m} of @code{match_operator} works like that of
383 @code{match_operand}: it is passed as the second argument to the
384 predicate function, and that function is solely responsible for
385 deciding whether the expression to be matched ``has'' that mode.
387 When constructing an insn, argument 3 of the gen-function will specify
388 the operation (i.e.@: the expression code) for the expression to be
389 made. It should be an RTL expression, whose expression code is copied
390 into a new expression whose operands are arguments 1 and 2 of the
391 gen-function. The subexpressions of argument 3 are not used;
392 only its expression code matters.
394 When @code{match_operator} is used in a pattern for matching an insn,
395 it usually best if the operand number of the @code{match_operator}
396 is higher than that of the actual operands of the insn. This improves
397 register allocation because the register allocator often looks at
398 operands 1 and 2 of insns to see if it can do register tying.
400 There is no way to specify constraints in @code{match_operator}. The
401 operand of the insn which corresponds to the @code{match_operator}
402 never has any constraints because it is never reloaded as a whole.
403 However, if parts of its @var{operands} are matched by
404 @code{match_operand} patterns, those parts may have constraints of
408 @item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}])
409 Like @code{match_dup}, except that it applies to operators instead of
410 operands. When constructing an insn, operand number @var{n} will be
411 substituted at this point. But in matching, @code{match_op_dup} behaves
412 differently. It assumes that operand number @var{n} has already been
413 determined by a @code{match_operator} appearing earlier in the
414 recognition template, and it matches only an identical-looking
417 @findex match_parallel
418 @item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}])
419 This pattern is a placeholder for an insn that consists of a
420 @code{parallel} expression with a variable number of elements. This
421 expression should only appear at the top level of an insn pattern.
423 When constructing an insn, operand number @var{n} will be substituted at
424 this point. When matching an insn, it matches if the body of the insn
425 is a @code{parallel} expression with at least as many elements as the
426 vector of @var{subpat} expressions in the @code{match_parallel}, if each
427 @var{subpat} matches the corresponding element of the @code{parallel},
428 @emph{and} the function @var{predicate} returns nonzero on the
429 @code{parallel} that is the body of the insn. It is the responsibility
430 of the predicate to validate elements of the @code{parallel} beyond
431 those listed in the @code{match_parallel}.
433 A typical use of @code{match_parallel} is to match load and store
434 multiple expressions, which can contain a variable number of elements
435 in a @code{parallel}. For example,
439 [(match_parallel 0 "load_multiple_operation"
440 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
441 (match_operand:SI 2 "memory_operand" "m"))
443 (clobber (reg:SI 179))])]
448 This example comes from @file{a29k.md}. The function
449 @code{load_multiple_operation} is defined in @file{a29k.c} and checks
450 that subsequent elements in the @code{parallel} are the same as the
451 @code{set} in the pattern, except that they are referencing subsequent
452 registers and memory locations.
454 An insn that matches this pattern might look like:
458 [(set (reg:SI 20) (mem:SI (reg:SI 100)))
460 (clobber (reg:SI 179))
462 (mem:SI (plus:SI (reg:SI 100)
465 (mem:SI (plus:SI (reg:SI 100)
469 @findex match_par_dup
470 @item (match_par_dup @var{n} [@var{subpat}@dots{}])
471 Like @code{match_op_dup}, but for @code{match_parallel} instead of
472 @code{match_operator}.
476 @node Output Template
477 @section Output Templates and Operand Substitution
478 @cindex output templates
479 @cindex operand substitution
481 @cindex @samp{%} in template
483 The @dfn{output template} is a string which specifies how to output the
484 assembler code for an instruction pattern. Most of the template is a
485 fixed string which is output literally. The character @samp{%} is used
486 to specify where to substitute an operand; it can also be used to
487 identify places where different variants of the assembler require
490 In the simplest case, a @samp{%} followed by a digit @var{n} says to output
491 operand @var{n} at that point in the string.
493 @samp{%} followed by a letter and a digit says to output an operand in an
494 alternate fashion. Four letters have standard, built-in meanings described
495 below. The machine description macro @code{PRINT_OPERAND} can define
496 additional letters with nonstandard meanings.
498 @samp{%c@var{digit}} can be used to substitute an operand that is a
499 constant value without the syntax that normally indicates an immediate
502 @samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of
503 the constant is negated before printing.
505 @samp{%a@var{digit}} can be used to substitute an operand as if it were a
506 memory reference, with the actual operand treated as the address. This may
507 be useful when outputting a ``load address'' instruction, because often the
508 assembler syntax for such an instruction requires you to write the operand
509 as if it were a memory reference.
511 @samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump
514 @samp{%=} outputs a number which is unique to each instruction in the
515 entire compilation. This is useful for making local labels to be
516 referred to more than once in a single template that generates multiple
517 assembler instructions.
519 @samp{%} followed by a punctuation character specifies a substitution that
520 does not use an operand. Only one case is standard: @samp{%%} outputs a
521 @samp{%} into the assembler code. Other nonstandard cases can be
522 defined in the @code{PRINT_OPERAND} macro. You must also define
523 which punctuation characters are valid with the
524 @code{PRINT_OPERAND_PUNCT_VALID_P} macro.
528 The template may generate multiple assembler instructions. Write the text
529 for the instructions, with @samp{\;} between them.
531 @cindex matching operands
532 When the RTL contains two operands which are required by constraint to match
533 each other, the output template must refer only to the lower-numbered operand.
534 Matching operands are not always identical, and the rest of the compiler
535 arranges to put the proper RTL expression for printing into the lower-numbered
538 One use of nonstandard letters or punctuation following @samp{%} is to
539 distinguish between different assembler languages for the same machine; for
540 example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax
541 requires periods in most opcode names, while MIT syntax does not. For
542 example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola
543 syntax. The same file of patterns is used for both kinds of output syntax,
544 but the character sequence @samp{%.} is used in each place where Motorola
545 syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax
546 defines the sequence to output a period; the macro for MIT syntax defines
549 @cindex @code{#} in template
550 As a special case, a template consisting of the single character @code{#}
551 instructs the compiler to first split the insn, and then output the
552 resulting instructions separately. This helps eliminate redundancy in the
553 output templates. If you have a @code{define_insn} that needs to emit
554 multiple assembler instructions, and there is an matching @code{define_split}
555 already defined, then you can simply use @code{#} as the output template
556 instead of writing an output template that emits the multiple assembler
559 If the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct
560 of the form @samp{@{option0|option1|option2@}} in the templates. These
561 describe multiple variants of assembler language syntax.
562 @xref{Instruction Output}.
564 @node Output Statement
565 @section C Statements for Assembler Output
566 @cindex output statements
567 @cindex C statements for assembler output
568 @cindex generating assembler output
570 Often a single fixed template string cannot produce correct and efficient
571 assembler code for all the cases that are recognized by a single
572 instruction pattern. For example, the opcodes may depend on the kinds of
573 operands; or some unfortunate combinations of operands may require extra
574 machine instructions.
576 If the output control string starts with a @samp{@@}, then it is actually
577 a series of templates, each on a separate line. (Blank lines and
578 leading spaces and tabs are ignored.) The templates correspond to the
579 pattern's constraint alternatives (@pxref{Multi-Alternative}). For example,
580 if a target machine has a two-address add instruction @samp{addr} to add
581 into a register and another @samp{addm} to add a register to memory, you
582 might write this pattern:
585 (define_insn "addsi3"
586 [(set (match_operand:SI 0 "general_operand" "=r,m")
587 (plus:SI (match_operand:SI 1 "general_operand" "0,0")
588 (match_operand:SI 2 "general_operand" "g,r")))]
595 @cindex @code{*} in template
596 @cindex asterisk in template
597 If the output control string starts with a @samp{*}, then it is not an
598 output template but rather a piece of C program that should compute a
599 template. It should execute a @code{return} statement to return the
600 template-string you want. Most such templates use C string literals, which
601 require doublequote characters to delimit them. To include these
602 doublequote characters in the string, prefix each one with @samp{\}.
604 If the output control string is written as a brace block instead of a
605 double-quoted string, it is automatically assumed to be C code. In that
606 case, it is not necessary to put in a leading asterisk, or to escape the
607 doublequotes surrounding C string literals.
609 The operands may be found in the array @code{operands}, whose C data type
612 It is very common to select different ways of generating assembler code
613 based on whether an immediate operand is within a certain range. Be
614 careful when doing this, because the result of @code{INTVAL} is an
615 integer on the host machine. If the host machine has more bits in an
616 @code{int} than the target machine has in the mode in which the constant
617 will be used, then some of the bits you get from @code{INTVAL} will be
618 superfluous. For proper results, you must carefully disregard the
619 values of those bits.
621 @findex output_asm_insn
622 It is possible to output an assembler instruction and then go on to output
623 or compute more of them, using the subroutine @code{output_asm_insn}. This
624 receives two arguments: a template-string and a vector of operands. The
625 vector may be @code{operands}, or it may be another array of @code{rtx}
626 that you declare locally and initialize yourself.
628 @findex which_alternative
629 When an insn pattern has multiple alternatives in its constraints, often
630 the appearance of the assembler code is determined mostly by which alternative
631 was matched. When this is so, the C code can test the variable
632 @code{which_alternative}, which is the ordinal number of the alternative
633 that was actually satisfied (0 for the first, 1 for the second alternative,
636 For example, suppose there are two opcodes for storing zero, @samp{clrreg}
637 for registers and @samp{clrmem} for memory locations. Here is how
638 a pattern could use @code{which_alternative} to choose between them:
642 [(set (match_operand:SI 0 "general_operand" "=r,m")
646 return (which_alternative == 0
647 ? "clrreg %0" : "clrmem %0");
651 The example above, where the assembler code to generate was
652 @emph{solely} determined by the alternative, could also have been specified
653 as follows, having the output control string start with a @samp{@@}:
658 [(set (match_operand:SI 0 "general_operand" "=r,m")
670 @cindex operand predicates
671 @cindex operator predicates
673 A predicate determines whether a @code{match_operand} or
674 @code{match_operator} expression matches, and therefore whether the
675 surrounding instruction pattern will be used for that combination of
676 operands. GCC has a number of machine-independent predicates, and you
677 can define machine-specific predicates as needed. By convention,
678 predicates used with @code{match_operand} have names that end in
679 @samp{_operand}, and those used with @code{match_operator} have names
680 that end in @samp{_operator}.
682 All predicates are Boolean functions (in the mathematical sense) of
683 two arguments: the RTL expression that is being considered at that
684 position in the instruction pattern, and the machine mode that the
685 @code{match_operand} or @code{match_operator} specifies. In this
686 section, the first argument is called @var{op} and the second argument
687 @var{mode}. Predicates can be called from C as ordinary two-argument
688 functions; this can be useful in output templates or other
689 machine-specific code.
691 Operand predicates can allow operands that are not actually acceptable
692 to the hardware, as long as the constraints give reload the ability to
693 fix them up (@pxref{Constraints}). However, GCC will usually generate
694 better code if the predicates specify the requirements of the machine
695 instructions as closely as possible. Reload cannot fix up operands
696 that must be constants (``immediate operands''); you must use a
697 predicate that allows only constants, or else enforce the requirement
698 in the extra condition.
700 @cindex predicates and machine modes
701 @cindex normal predicates
702 @cindex special predicates
703 Most predicates handle their @var{mode} argument in a uniform manner.
704 If @var{mode} is @code{VOIDmode} (unspecified), then @var{op} can have
705 any mode. If @var{mode} is anything else, then @var{op} must have the
706 same mode, unless @var{op} is a @code{CONST_INT} or integer
707 @code{CONST_DOUBLE}. These RTL expressions always have
708 @code{VOIDmode}, so it would be counterproductive to check that their
709 mode matches. Instead, predicates that accept @code{CONST_INT} and/or
710 integer @code{CONST_DOUBLE} check that the value stored in the
711 constant will fit in the requested mode.
713 Predicates with this behavior are called @dfn{normal}.
714 @command{genrecog} can optimize the instruction recognizer based on
715 knowledge of how normal predicates treat modes. It can also diagnose
716 certain kinds of common errors in the use of normal predicates; for
717 instance, it is almost always an error to use a normal predicate
718 without specifying a mode.
720 Predicates that do something different with their @var{mode} argument
721 are called @dfn{special}. The generic predicates
722 @code{address_operand} and @code{pmode_register_operand} are special
723 predicates. @command{genrecog} does not do any optimizations or
724 diagnosis when special predicates are used.
727 * Machine-Independent Predicates:: Predicates available to all back ends.
728 * Defining Predicates:: How to write machine-specific predicate
732 @node Machine-Independent Predicates
733 @subsection Machine-Independent Predicates
734 @cindex machine-independent predicates
735 @cindex generic predicates
737 These are the generic predicates available to all back ends. They are
738 defined in @file{recog.c}. The first category of predicates allow
739 only constant, or @dfn{immediate}, operands.
741 @defun immediate_operand
742 This predicate allows any sort of constant that fits in @var{mode}.
743 It is an appropriate choice for instructions that take operands that
747 @defun const_int_operand
748 This predicate allows any @code{CONST_INT} expression that fits in
749 @var{mode}. It is an appropriate choice for an immediate operand that
750 does not allow a symbol or label.
753 @defun const_double_operand
754 This predicate accepts any @code{CONST_DOUBLE} expression that has
755 exactly @var{mode}. If @var{mode} is @code{VOIDmode}, it will also
756 accept @code{CONST_INT}. It is intended for immediate floating point
761 The second category of predicates allow only some kind of machine
764 @defun register_operand
765 This predicate allows any @code{REG} or @code{SUBREG} expression that
766 is valid for @var{mode}. It is often suitable for arithmetic
767 instruction operands on a RISC machine.
770 @defun pmode_register_operand
771 This is a slight variant on @code{register_operand} which works around
772 a limitation in the machine-description reader.
775 (match_operand @var{n} "pmode_register_operand" @var{constraint})
782 (match_operand:P @var{n} "register_operand" @var{constraint})
786 would mean, if the machine-description reader accepted @samp{:P}
787 mode suffixes. Unfortunately, it cannot, because @code{Pmode} is an
788 alias for some other mode, and might vary with machine-specific
789 options. @xref{Misc}.
792 @defun scratch_operand
793 This predicate allows hard registers and @code{SCRATCH} expressions,
794 but not pseudo-registers. It is used internally by @code{match_scratch};
795 it should not be used directly.
799 The third category of predicates allow only some kind of memory reference.
801 @defun memory_operand
802 This predicate allows any valid reference to a quantity of mode
803 @var{mode} in memory, as determined by the weak form of
804 @code{GO_IF_LEGITIMATE_ADDRESS} (@pxref{Addressing Modes}).
807 @defun address_operand
808 This predicate is a little unusual; it allows any operand that is a
809 valid expression for the @emph{address} of a quantity of mode
810 @var{mode}, again determined by the weak form of
811 @code{GO_IF_LEGITIMATE_ADDRESS}. To first order, if
812 @samp{@w{(mem:@var{mode} (@var{exp}))}} is acceptable to
813 @code{memory_operand}, then @var{exp} is acceptable to
814 @code{address_operand}. Note that @var{exp} does not necessarily have
818 @defun indirect_operand
819 This is a stricter form of @code{memory_operand} which allows only
820 memory references with a @code{general_operand} as the address
821 expression. New uses of this predicate are discouraged, because
822 @code{general_operand} is very permissive, so it's hard to tell what
823 an @code{indirect_operand} does or does not allow. If a target has
824 different requirements for memory operands for different instructions,
825 it is better to define target-specific predicates which enforce the
826 hardware's requirements explicitly.
830 This predicate allows a memory reference suitable for pushing a value
831 onto the stack. This will be a @code{MEM} which refers to
832 @code{stack_pointer_rtx}, with a side-effect in its address expression
833 (@pxref{Incdec}); which one is determined by the
834 @code{STACK_PUSH_CODE} macro (@pxref{Frame Layout}).
838 This predicate allows a memory reference suitable for popping a value
839 off the stack. Again, this will be a @code{MEM} referring to
840 @code{stack_pointer_rtx}, with a side-effect in its address
841 expression. However, this time @code{STACK_POP_CODE} is expected.
845 The fourth category of predicates allow some combination of the above
848 @defun nonmemory_operand
849 This predicate allows any immediate or register operand valid for @var{mode}.
852 @defun nonimmediate_operand
853 This predicate allows any register or memory operand valid for @var{mode}.
856 @defun general_operand
857 This predicate allows any immediate, register, or memory operand
858 valid for @var{mode}.
862 Finally, there is one generic operator predicate.
864 @defun comparison_operator
865 This predicate matches any expression which performs an arithmetic
866 comparison in @var{mode}; that is, @code{COMPARISON_P} is true for the
870 @node Defining Predicates
871 @subsection Defining Machine-Specific Predicates
872 @cindex defining predicates
873 @findex define_predicate
874 @findex define_special_predicate
876 Many machines have requirements for their operands that cannot be
877 expressed precisely using the generic predicates. You can define
878 additional predicates using @code{define_predicate} and
879 @code{define_special_predicate} expressions. These expressions have
884 The name of the predicate, as it will be referred to in
885 @code{match_operand} or @code{match_operator} expressions.
888 An RTL expression which evaluates to true if the predicate allows the
889 operand @var{op}, false if it does not. This expression can only use
890 the following RTL codes:
894 When written inside a predicate expression, a @code{MATCH_OPERAND}
895 expression evaluates to true if the predicate it names would allow
896 @var{op}. The operand number and constraint are ignored. Due to
897 limitations in @command{genrecog}, you can only refer to generic
898 predicates and predicates that have already been defined.
901 This expression evaluates to true if @var{op} or a specified
902 subexpression of @var{op} has one of a given list of RTX codes.
904 The first operand of this expression is a string constant containing a
905 comma-separated list of RTX code names (in lower case). These are the
906 codes for which the @code{MATCH_CODE} will be true.
908 The second operand is a string constant which indicates what
909 subexpression of @var{op} to examine. If it is absent or the empty
910 string, @var{op} itself is examined. Otherwise, the string constant
911 must be a sequence of digits and/or lowercase letters. Each character
912 indicates a subexpression to extract from the current expression; for
913 the first character this is @var{op}, for the second and subsequent
914 characters it is the result of the previous character. A digit
915 @var{n} extracts @samp{@w{XEXP (@var{e}, @var{n})}}; a letter @var{l}
916 extracts @samp{@w{XVECEXP (@var{e}, 0, @var{n})}} where @var{n} is the
917 alphabetic ordinal of @var{l} (0 for `a', 1 for 'b', and so on). The
918 @code{MATCH_CODE} then examines the RTX code of the subexpression
919 extracted by the complete string. It is not possible to extract
920 components of an @code{rtvec} that is not at position 0 within its RTX
924 This expression has one operand, a string constant containing a C
925 expression. The predicate's arguments, @var{op} and @var{mode}, are
926 available with those names in the C expression. The @code{MATCH_TEST}
927 evaluates to true if the C expression evaluates to a nonzero value.
928 @code{MATCH_TEST} expressions must not have side effects.
934 The basic @samp{MATCH_} expressions can be combined using these
935 logical operators, which have the semantics of the C operators
936 @samp{&&}, @samp{||}, @samp{!}, and @samp{@w{? :}} respectively. As
937 in Common Lisp, you may give an @code{AND} or @code{IOR} expression an
938 arbitrary number of arguments; this has exactly the same effect as
939 writing a chain of two-argument @code{AND} or @code{IOR} expressions.
943 An optional block of C code, which should execute
944 @samp{@w{return true}} if the predicate is found to match and
945 @samp{@w{return false}} if it does not. It must not have any side
946 effects. The predicate arguments, @var{op} and @var{mode}, are
947 available with those names.
949 If a code block is present in a predicate definition, then the RTL
950 expression must evaluate to true @emph{and} the code block must
951 execute @samp{@w{return true}} for the predicate to allow the operand.
952 The RTL expression is evaluated first; do not re-check anything in the
953 code block that was checked in the RTL expression.
956 The program @command{genrecog} scans @code{define_predicate} and
957 @code{define_special_predicate} expressions to determine which RTX
958 codes are possibly allowed. You should always make this explicit in
959 the RTL predicate expression, using @code{MATCH_OPERAND} and
962 Here is an example of a simple predicate definition, from the IA64
967 ;; @r{True if @var{op} is a @code{SYMBOL_REF} which refers to the sdata section.}
968 (define_predicate "small_addr_symbolic_operand"
969 (and (match_code "symbol_ref")
970 (match_test "SYMBOL_REF_SMALL_ADDR_P (op)")))
975 And here is another, showing the use of the C block.
979 ;; @r{True if @var{op} is a register operand that is (or could be) a GR reg.}
980 (define_predicate "gr_register_operand"
981 (match_operand 0 "register_operand")
984 if (GET_CODE (op) == SUBREG)
985 op = SUBREG_REG (op);
988 return (regno >= FIRST_PSEUDO_REGISTER || GENERAL_REGNO_P (regno));
993 Predicates written with @code{define_predicate} automatically include
994 a test that @var{mode} is @code{VOIDmode}, or @var{op} has the same
995 mode as @var{mode}, or @var{op} is a @code{CONST_INT} or
996 @code{CONST_DOUBLE}. They do @emph{not} check specifically for
997 integer @code{CONST_DOUBLE}, nor do they test that the value of either
998 kind of constant fits in the requested mode. This is because
999 target-specific predicates that take constants usually have to do more
1000 stringent value checks anyway. If you need the exact same treatment
1001 of @code{CONST_INT} or @code{CONST_DOUBLE} that the generic predicates
1002 provide, use a @code{MATCH_OPERAND} subexpression to call
1003 @code{const_int_operand}, @code{const_double_operand}, or
1004 @code{immediate_operand}.
1006 Predicates written with @code{define_special_predicate} do not get any
1007 automatic mode checks, and are treated as having special mode handling
1008 by @command{genrecog}.
1010 The program @command{genpreds} is responsible for generating code to
1011 test predicates. It also writes a header file containing function
1012 declarations for all machine-specific predicates. It is not necessary
1013 to declare these predicates in @file{@var{cpu}-protos.h}.
1016 @c Most of this node appears by itself (in a different place) even
1017 @c when the INTERNALS flag is clear. Passages that require the internals
1018 @c manual's context are conditionalized to appear only in the internals manual.
1021 @section Operand Constraints
1022 @cindex operand constraints
1025 Each @code{match_operand} in an instruction pattern can specify
1026 constraints for the operands allowed. The constraints allow you to
1027 fine-tune matching within the set of operands allowed by the
1033 @section Constraints for @code{asm} Operands
1034 @cindex operand constraints, @code{asm}
1035 @cindex constraints, @code{asm}
1036 @cindex @code{asm} constraints
1038 Here are specific details on what constraint letters you can use with
1039 @code{asm} operands.
1041 Constraints can say whether
1042 an operand may be in a register, and which kinds of register; whether the
1043 operand can be a memory reference, and which kinds of address; whether the
1044 operand may be an immediate constant, and which possible values it may
1045 have. Constraints can also require two operands to match.
1049 * Simple Constraints:: Basic use of constraints.
1050 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1051 * Class Preferences:: Constraints guide which hard register to put things in.
1052 * Modifiers:: More precise control over effects of constraints.
1053 * Machine Constraints:: Existing constraints for some particular machines.
1054 * Define Constraints:: How to define machine-specific constraints.
1055 * C Constraint Interface:: How to test constraints from C code.
1061 * Simple Constraints:: Basic use of constraints.
1062 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1063 * Modifiers:: More precise control over effects of constraints.
1064 * Machine Constraints:: Special constraints for some particular machines.
1068 @node Simple Constraints
1069 @subsection Simple Constraints
1070 @cindex simple constraints
1072 The simplest kind of constraint is a string full of letters, each of
1073 which describes one kind of operand that is permitted. Here are
1074 the letters that are allowed:
1078 Whitespace characters are ignored and can be inserted at any position
1079 except the first. This enables each alternative for different operands to
1080 be visually aligned in the machine description even if they have different
1081 number of constraints and modifiers.
1083 @cindex @samp{m} in constraint
1084 @cindex memory references in constraints
1086 A memory operand is allowed, with any kind of address that the machine
1087 supports in general.
1089 @cindex offsettable address
1090 @cindex @samp{o} in constraint
1092 A memory operand is allowed, but only if the address is
1093 @dfn{offsettable}. This means that adding a small integer (actually,
1094 the width in bytes of the operand, as determined by its machine mode)
1095 may be added to the address and the result is also a valid memory
1098 @cindex autoincrement/decrement addressing
1099 For example, an address which is constant is offsettable; so is an
1100 address that is the sum of a register and a constant (as long as a
1101 slightly larger constant is also within the range of address-offsets
1102 supported by the machine); but an autoincrement or autodecrement
1103 address is not offsettable. More complicated indirect/indexed
1104 addresses may or may not be offsettable depending on the other
1105 addressing modes that the machine supports.
1107 Note that in an output operand which can be matched by another
1108 operand, the constraint letter @samp{o} is valid only when accompanied
1109 by both @samp{<} (if the target machine has predecrement addressing)
1110 and @samp{>} (if the target machine has preincrement addressing).
1112 @cindex @samp{V} in constraint
1114 A memory operand that is not offsettable. In other words, anything that
1115 would fit the @samp{m} constraint but not the @samp{o} constraint.
1117 @cindex @samp{<} in constraint
1119 A memory operand with autodecrement addressing (either predecrement or
1120 postdecrement) is allowed.
1122 @cindex @samp{>} in constraint
1124 A memory operand with autoincrement addressing (either preincrement or
1125 postincrement) is allowed.
1127 @cindex @samp{r} in constraint
1128 @cindex registers in constraints
1130 A register operand is allowed provided that it is in a general
1133 @cindex constants in constraints
1134 @cindex @samp{i} in constraint
1136 An immediate integer operand (one with constant value) is allowed.
1137 This includes symbolic constants whose values will be known only at
1138 assembly time or later.
1140 @cindex @samp{n} in constraint
1142 An immediate integer operand with a known numeric value is allowed.
1143 Many systems cannot support assembly-time constants for operands less
1144 than a word wide. Constraints for these operands should use @samp{n}
1145 rather than @samp{i}.
1147 @cindex @samp{I} in constraint
1148 @item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P}
1149 Other letters in the range @samp{I} through @samp{P} may be defined in
1150 a machine-dependent fashion to permit immediate integer operands with
1151 explicit integer values in specified ranges. For example, on the
1152 68000, @samp{I} is defined to stand for the range of values 1 to 8.
1153 This is the range permitted as a shift count in the shift
1156 @cindex @samp{E} in constraint
1158 An immediate floating operand (expression code @code{const_double}) is
1159 allowed, but only if the target floating point format is the same as
1160 that of the host machine (on which the compiler is running).
1162 @cindex @samp{F} in constraint
1164 An immediate floating operand (expression code @code{const_double} or
1165 @code{const_vector}) is allowed.
1167 @cindex @samp{G} in constraint
1168 @cindex @samp{H} in constraint
1169 @item @samp{G}, @samp{H}
1170 @samp{G} and @samp{H} may be defined in a machine-dependent fashion to
1171 permit immediate floating operands in particular ranges of values.
1173 @cindex @samp{s} in constraint
1175 An immediate integer operand whose value is not an explicit integer is
1178 This might appear strange; if an insn allows a constant operand with a
1179 value not known at compile time, it certainly must allow any known
1180 value. So why use @samp{s} instead of @samp{i}? Sometimes it allows
1181 better code to be generated.
1183 For example, on the 68000 in a fullword instruction it is possible to
1184 use an immediate operand; but if the immediate value is between @minus{}128
1185 and 127, better code results from loading the value into a register and
1186 using the register. This is because the load into the register can be
1187 done with a @samp{moveq} instruction. We arrange for this to happen
1188 by defining the letter @samp{K} to mean ``any integer outside the
1189 range @minus{}128 to 127'', and then specifying @samp{Ks} in the operand
1192 @cindex @samp{g} in constraint
1194 Any register, memory or immediate integer operand is allowed, except for
1195 registers that are not general registers.
1197 @cindex @samp{X} in constraint
1200 Any operand whatsoever is allowed, even if it does not satisfy
1201 @code{general_operand}. This is normally used in the constraint of
1202 a @code{match_scratch} when certain alternatives will not actually
1203 require a scratch register.
1206 Any operand whatsoever is allowed.
1209 @cindex @samp{0} in constraint
1210 @cindex digits in constraint
1211 @item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9}
1212 An operand that matches the specified operand number is allowed. If a
1213 digit is used together with letters within the same alternative, the
1214 digit should come last.
1216 This number is allowed to be more than a single digit. If multiple
1217 digits are encountered consecutively, they are interpreted as a single
1218 decimal integer. There is scant chance for ambiguity, since to-date
1219 it has never been desirable that @samp{10} be interpreted as matching
1220 either operand 1 @emph{or} operand 0. Should this be desired, one
1221 can use multiple alternatives instead.
1223 @cindex matching constraint
1224 @cindex constraint, matching
1225 This is called a @dfn{matching constraint} and what it really means is
1226 that the assembler has only a single operand that fills two roles
1228 considered separate in the RTL insn. For example, an add insn has two
1229 input operands and one output operand in the RTL, but on most CISC
1232 which @code{asm} distinguishes. For example, an add instruction uses
1233 two input operands and an output operand, but on most CISC
1235 machines an add instruction really has only two operands, one of them an
1236 input-output operand:
1242 Matching constraints are used in these circumstances.
1243 More precisely, the two operands that match must include one input-only
1244 operand and one output-only operand. Moreover, the digit must be a
1245 smaller number than the number of the operand that uses it in the
1249 For operands to match in a particular case usually means that they
1250 are identical-looking RTL expressions. But in a few special cases
1251 specific kinds of dissimilarity are allowed. For example, @code{*x}
1252 as an input operand will match @code{*x++} as an output operand.
1253 For proper results in such cases, the output template should always
1254 use the output-operand's number when printing the operand.
1257 @cindex load address instruction
1258 @cindex push address instruction
1259 @cindex address constraints
1260 @cindex @samp{p} in constraint
1262 An operand that is a valid memory address is allowed. This is
1263 for ``load address'' and ``push address'' instructions.
1265 @findex address_operand
1266 @samp{p} in the constraint must be accompanied by @code{address_operand}
1267 as the predicate in the @code{match_operand}. This predicate interprets
1268 the mode specified in the @code{match_operand} as the mode of the memory
1269 reference for which the address would be valid.
1271 @cindex other register constraints
1272 @cindex extensible constraints
1273 @item @var{other-letters}
1274 Other letters can be defined in machine-dependent fashion to stand for
1275 particular classes of registers or other arbitrary operand types.
1276 @samp{d}, @samp{a} and @samp{f} are defined on the 68000/68020 to stand
1277 for data, address and floating point registers.
1281 In order to have valid assembler code, each operand must satisfy
1282 its constraint. But a failure to do so does not prevent the pattern
1283 from applying to an insn. Instead, it directs the compiler to modify
1284 the code so that the constraint will be satisfied. Usually this is
1285 done by copying an operand into a register.
1287 Contrast, therefore, the two instruction patterns that follow:
1291 [(set (match_operand:SI 0 "general_operand" "=r")
1292 (plus:SI (match_dup 0)
1293 (match_operand:SI 1 "general_operand" "r")))]
1299 which has two operands, one of which must appear in two places, and
1303 [(set (match_operand:SI 0 "general_operand" "=r")
1304 (plus:SI (match_operand:SI 1 "general_operand" "0")
1305 (match_operand:SI 2 "general_operand" "r")))]
1311 which has three operands, two of which are required by a constraint to be
1312 identical. If we are considering an insn of the form
1315 (insn @var{n} @var{prev} @var{next}
1317 (plus:SI (reg:SI 6) (reg:SI 109)))
1322 the first pattern would not apply at all, because this insn does not
1323 contain two identical subexpressions in the right place. The pattern would
1324 say, ``That does not look like an add instruction; try other patterns''.
1325 The second pattern would say, ``Yes, that's an add instruction, but there
1326 is something wrong with it''. It would direct the reload pass of the
1327 compiler to generate additional insns to make the constraint true. The
1328 results might look like this:
1331 (insn @var{n2} @var{prev} @var{n}
1332 (set (reg:SI 3) (reg:SI 6))
1335 (insn @var{n} @var{n2} @var{next}
1337 (plus:SI (reg:SI 3) (reg:SI 109)))
1341 It is up to you to make sure that each operand, in each pattern, has
1342 constraints that can handle any RTL expression that could be present for
1343 that operand. (When multiple alternatives are in use, each pattern must,
1344 for each possible combination of operand expressions, have at least one
1345 alternative which can handle that combination of operands.) The
1346 constraints don't need to @emph{allow} any possible operand---when this is
1347 the case, they do not constrain---but they must at least point the way to
1348 reloading any possible operand so that it will fit.
1352 If the constraint accepts whatever operands the predicate permits,
1353 there is no problem: reloading is never necessary for this operand.
1355 For example, an operand whose constraints permit everything except
1356 registers is safe provided its predicate rejects registers.
1358 An operand whose predicate accepts only constant values is safe
1359 provided its constraints include the letter @samp{i}. If any possible
1360 constant value is accepted, then nothing less than @samp{i} will do;
1361 if the predicate is more selective, then the constraints may also be
1365 Any operand expression can be reloaded by copying it into a register.
1366 So if an operand's constraints allow some kind of register, it is
1367 certain to be safe. It need not permit all classes of registers; the
1368 compiler knows how to copy a register into another register of the
1369 proper class in order to make an instruction valid.
1371 @cindex nonoffsettable memory reference
1372 @cindex memory reference, nonoffsettable
1374 A nonoffsettable memory reference can be reloaded by copying the
1375 address into a register. So if the constraint uses the letter
1376 @samp{o}, all memory references are taken care of.
1379 A constant operand can be reloaded by allocating space in memory to
1380 hold it as preinitialized data. Then the memory reference can be used
1381 in place of the constant. So if the constraint uses the letters
1382 @samp{o} or @samp{m}, constant operands are not a problem.
1385 If the constraint permits a constant and a pseudo register used in an insn
1386 was not allocated to a hard register and is equivalent to a constant,
1387 the register will be replaced with the constant. If the predicate does
1388 not permit a constant and the insn is re-recognized for some reason, the
1389 compiler will crash. Thus the predicate must always recognize any
1390 objects allowed by the constraint.
1393 If the operand's predicate can recognize registers, but the constraint does
1394 not permit them, it can make the compiler crash. When this operand happens
1395 to be a register, the reload pass will be stymied, because it does not know
1396 how to copy a register temporarily into memory.
1398 If the predicate accepts a unary operator, the constraint applies to the
1399 operand. For example, the MIPS processor at ISA level 3 supports an
1400 instruction which adds two registers in @code{SImode} to produce a
1401 @code{DImode} result, but only if the registers are correctly sign
1402 extended. This predicate for the input operands accepts a
1403 @code{sign_extend} of an @code{SImode} register. Write the constraint
1404 to indicate the type of register that is required for the operand of the
1408 @node Multi-Alternative
1409 @subsection Multiple Alternative Constraints
1410 @cindex multiple alternative constraints
1412 Sometimes a single instruction has multiple alternative sets of possible
1413 operands. For example, on the 68000, a logical-or instruction can combine
1414 register or an immediate value into memory, or it can combine any kind of
1415 operand into a register; but it cannot combine one memory location into
1418 These constraints are represented as multiple alternatives. An alternative
1419 can be described by a series of letters for each operand. The overall
1420 constraint for an operand is made from the letters for this operand
1421 from the first alternative, a comma, the letters for this operand from
1422 the second alternative, a comma, and so on until the last alternative.
1424 Here is how it is done for fullword logical-or on the 68000:
1427 (define_insn "iorsi3"
1428 [(set (match_operand:SI 0 "general_operand" "=m,d")
1429 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
1430 (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
1434 The first alternative has @samp{m} (memory) for operand 0, @samp{0} for
1435 operand 1 (meaning it must match operand 0), and @samp{dKs} for operand
1436 2. The second alternative has @samp{d} (data register) for operand 0,
1437 @samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and
1438 @samp{%} in the constraints apply to all the alternatives; their
1439 meaning is explained in the next section (@pxref{Class Preferences}).
1442 @c FIXME Is this ? and ! stuff of use in asm()? If not, hide unless INTERNAL
1443 If all the operands fit any one alternative, the instruction is valid.
1444 Otherwise, for each alternative, the compiler counts how many instructions
1445 must be added to copy the operands so that that alternative applies.
1446 The alternative requiring the least copying is chosen. If two alternatives
1447 need the same amount of copying, the one that comes first is chosen.
1448 These choices can be altered with the @samp{?} and @samp{!} characters:
1451 @cindex @samp{?} in constraint
1452 @cindex question mark
1454 Disparage slightly the alternative that the @samp{?} appears in,
1455 as a choice when no alternative applies exactly. The compiler regards
1456 this alternative as one unit more costly for each @samp{?} that appears
1459 @cindex @samp{!} in constraint
1460 @cindex exclamation point
1462 Disparage severely the alternative that the @samp{!} appears in.
1463 This alternative can still be used if it fits without reloading,
1464 but if reloading is needed, some other alternative will be used.
1468 When an insn pattern has multiple alternatives in its constraints, often
1469 the appearance of the assembler code is determined mostly by which
1470 alternative was matched. When this is so, the C code for writing the
1471 assembler code can use the variable @code{which_alternative}, which is
1472 the ordinal number of the alternative that was actually satisfied (0 for
1473 the first, 1 for the second alternative, etc.). @xref{Output Statement}.
1477 @node Class Preferences
1478 @subsection Register Class Preferences
1479 @cindex class preference constraints
1480 @cindex register class preference constraints
1482 @cindex voting between constraint alternatives
1483 The operand constraints have another function: they enable the compiler
1484 to decide which kind of hardware register a pseudo register is best
1485 allocated to. The compiler examines the constraints that apply to the
1486 insns that use the pseudo register, looking for the machine-dependent
1487 letters such as @samp{d} and @samp{a} that specify classes of registers.
1488 The pseudo register is put in whichever class gets the most ``votes''.
1489 The constraint letters @samp{g} and @samp{r} also vote: they vote in
1490 favor of a general register. The machine description says which registers
1491 are considered general.
1493 Of course, on some machines all registers are equivalent, and no register
1494 classes are defined. Then none of this complexity is relevant.
1498 @subsection Constraint Modifier Characters
1499 @cindex modifiers in constraints
1500 @cindex constraint modifier characters
1502 @c prevent bad page break with this line
1503 Here are constraint modifier characters.
1506 @cindex @samp{=} in constraint
1508 Means that this operand is write-only for this instruction: the previous
1509 value is discarded and replaced by output data.
1511 @cindex @samp{+} in constraint
1513 Means that this operand is both read and written by the instruction.
1515 When the compiler fixes up the operands to satisfy the constraints,
1516 it needs to know which operands are inputs to the instruction and
1517 which are outputs from it. @samp{=} identifies an output; @samp{+}
1518 identifies an operand that is both input and output; all other operands
1519 are assumed to be input only.
1521 If you specify @samp{=} or @samp{+} in a constraint, you put it in the
1522 first character of the constraint string.
1524 @cindex @samp{&} in constraint
1525 @cindex earlyclobber operand
1527 Means (in a particular alternative) that this operand is an
1528 @dfn{earlyclobber} operand, which is modified before the instruction is
1529 finished using the input operands. Therefore, this operand may not lie
1530 in a register that is used as an input operand or as part of any memory
1533 @samp{&} applies only to the alternative in which it is written. In
1534 constraints with multiple alternatives, sometimes one alternative
1535 requires @samp{&} while others do not. See, for example, the
1536 @samp{movdf} insn of the 68000.
1538 An input operand can be tied to an earlyclobber operand if its only
1539 use as an input occurs before the early result is written. Adding
1540 alternatives of this form often allows GCC to produce better code
1541 when only some of the inputs can be affected by the earlyclobber.
1542 See, for example, the @samp{mulsi3} insn of the ARM@.
1544 @samp{&} does not obviate the need to write @samp{=}.
1546 @cindex @samp{%} in constraint
1548 Declares the instruction to be commutative for this operand and the
1549 following operand. This means that the compiler may interchange the
1550 two operands if that is the cheapest way to make all operands fit the
1553 This is often used in patterns for addition instructions
1554 that really have only two operands: the result must go in one of the
1555 arguments. Here for example, is how the 68000 halfword-add
1556 instruction is defined:
1559 (define_insn "addhi3"
1560 [(set (match_operand:HI 0 "general_operand" "=m,r")
1561 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
1562 (match_operand:HI 2 "general_operand" "di,g")))]
1566 GCC can only handle one commutative pair in an asm; if you use more,
1567 the compiler may fail. Note that you need not use the modifier if
1568 the two alternatives are strictly identical; this would only waste
1569 time in the reload pass. The modifier is not operational after
1570 register allocation, so the result of @code{define_peephole2}
1571 and @code{define_split}s performed after reload cannot rely on
1572 @samp{%} to make the intended insn match.
1574 @cindex @samp{#} in constraint
1576 Says that all following characters, up to the next comma, are to be
1577 ignored as a constraint. They are significant only for choosing
1578 register preferences.
1580 @cindex @samp{*} in constraint
1582 Says that the following character should be ignored when choosing
1583 register preferences. @samp{*} has no effect on the meaning of the
1584 constraint as a constraint, and no effect on reloading.
1587 Here is an example: the 68000 has an instruction to sign-extend a
1588 halfword in a data register, and can also sign-extend a value by
1589 copying it into an address register. While either kind of register is
1590 acceptable, the constraints on an address-register destination are
1591 less strict, so it is best if register allocation makes an address
1592 register its goal. Therefore, @samp{*} is used so that the @samp{d}
1593 constraint letter (for data register) is ignored when computing
1594 register preferences.
1597 (define_insn "extendhisi2"
1598 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1600 (match_operand:HI 1 "general_operand" "0,g")))]
1606 @node Machine Constraints
1607 @subsection Constraints for Particular Machines
1608 @cindex machine specific constraints
1609 @cindex constraints, machine specific
1611 Whenever possible, you should use the general-purpose constraint letters
1612 in @code{asm} arguments, since they will convey meaning more readily to
1613 people reading your code. Failing that, use the constraint letters
1614 that usually have very similar meanings across architectures. The most
1615 commonly used constraints are @samp{m} and @samp{r} (for memory and
1616 general-purpose registers respectively; @pxref{Simple Constraints}), and
1617 @samp{I}, usually the letter indicating the most common
1618 immediate-constant format.
1620 Each architecture defines additional constraints. These constraints
1621 are used by the compiler itself for instruction generation, as well as
1622 for @code{asm} statements; therefore, some of the constraints are not
1623 particularly useful for @code{asm}. Here is a summary of some of the
1624 machine-dependent constraints available on some particular machines;
1625 it includes both constraints that are useful for @code{asm} and
1626 constraints that aren't. The compiler source file mentioned in the
1627 table heading for each architecture is the definitive reference for
1628 the meanings of that architecture's constraints.
1631 @item ARM family---@file{config/arm/arm.h}
1634 Floating-point register
1637 VFP floating-point register
1640 One of the floating-point constants 0.0, 0.5, 1.0, 2.0, 3.0, 4.0, 5.0
1644 Floating-point constant that would satisfy the constraint @samp{F} if it
1648 Integer that is valid as an immediate operand in a data processing
1649 instruction. That is, an integer in the range 0 to 255 rotated by a
1653 Integer in the range @minus{}4095 to 4095
1656 Integer that satisfies constraint @samp{I} when inverted (ones complement)
1659 Integer that satisfies constraint @samp{I} when negated (twos complement)
1662 Integer in the range 0 to 32
1665 A memory reference where the exact address is in a single register
1666 (`@samp{m}' is preferable for @code{asm} statements)
1669 An item in the constant pool
1672 A symbol in the text segment of the current file
1675 A memory reference suitable for VFP load/store insns (reg+constant offset)
1678 A memory reference suitable for iWMMXt load/store instructions.
1681 A memory reference suitable for the ARMv4 ldrsb instruction.
1684 @item AVR family---@file{config/avr/constraints.md}
1687 Registers from r0 to r15
1690 Registers from r16 to r23
1693 Registers from r16 to r31
1696 Registers from r24 to r31. These registers can be used in @samp{adiw} command
1699 Pointer register (r26--r31)
1702 Base pointer register (r28--r31)
1705 Stack pointer register (SPH:SPL)
1708 Temporary register r0
1711 Register pair X (r27:r26)
1714 Register pair Y (r29:r28)
1717 Register pair Z (r31:r30)
1720 Constant greater than @minus{}1, less than 64
1723 Constant greater than @minus{}64, less than 1
1732 Constant that fits in 8 bits
1735 Constant integer @minus{}1
1738 Constant integer 8, 16, or 24
1744 A floating point constant 0.0
1747 @item CRX Architecture---@file{config/crx/crx.h}
1751 Registers from r0 to r14 (registers without stack pointer)
1754 Register r16 (64-bit accumulator lo register)
1757 Register r17 (64-bit accumulator hi register)
1760 Register pair r16-r17. (64-bit accumulator lo-hi pair)
1763 Constant that fits in 3 bits
1766 Constant that fits in 4 bits
1769 Constant that fits in 5 bits
1772 Constant that is one of -1, 4, -4, 7, 8, 12, 16, 20, 32, 48
1775 Floating point constant that is legal for store immediate
1778 @item PowerPC and IBM RS6000---@file{config/rs6000/rs6000.h}
1781 Address base register
1784 Floating point register
1790 @samp{MQ}, @samp{CTR}, or @samp{LINK} register
1799 @samp{LINK} register
1802 @samp{CR} register (condition register) number 0
1805 @samp{CR} register (condition register)
1808 @samp{FPMEM} stack memory for FPR-GPR transfers
1811 Signed 16-bit constant
1814 Unsigned 16-bit constant shifted left 16 bits (use @samp{L} instead for
1815 @code{SImode} constants)
1818 Unsigned 16-bit constant
1821 Signed 16-bit constant shifted left 16 bits
1824 Constant larger than 31
1833 Constant whose negation is a signed 16-bit constant
1836 Floating point constant that can be loaded into a register with one
1837 instruction per word
1840 Integer/Floating point constant that can be loaded into a register using
1844 Memory operand that is an offset from a register (@samp{m} is preferable
1845 for @code{asm} statements)
1848 Memory operand that is an indexed or indirect from a register (@samp{m} is
1849 preferable for @code{asm} statements)
1855 Address operand that is an indexed or indirect from a register (@samp{p} is
1856 preferable for @code{asm} statements)
1859 Constant suitable as a 64-bit mask operand
1862 Constant suitable as a 32-bit mask operand
1865 System V Release 4 small data area reference
1868 AND masks that can be performed by two rldic@{l, r@} instructions
1871 Vector constant that does not require memory
1875 @item MorphoTech family---@file{config/mt/mt.h}
1878 Constant for an arithmetic insn (16-bit signed integer).
1884 Constant for a logical insn (16-bit zero-extended integer).
1887 A constant that can be loaded with @code{lui} (i.e.@: the bottom 16
1891 A constant that takes two words to load (i.e.@: not matched by
1892 @code{I}, @code{K}, or @code{L}).
1895 Negative 16-bit constants other than -65536.
1898 A 15-bit signed integer constant.
1901 A positive 16-bit constant.
1904 @item Intel 386---@file{config/i386/constraints.md}
1907 Legacy register---the eight integer registers available on all
1908 i386 processors (@code{a}, @code{b}, @code{c}, @code{d},
1909 @code{si}, @code{di}, @code{bp}, @code{sp}).
1912 Any register accessible as @code{@var{r}l}. In 32-bit mode, @code{a},
1913 @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.
1916 Any register accessible as @code{@var{r}h}: @code{a}, @code{b},
1917 @code{c}, and @code{d}.
1921 Any register that can be used as the index in a base+index memory
1922 access: that is, any general register except the stack pointer.
1926 The @code{a} register.
1929 The @code{b} register.
1932 The @code{c} register.
1935 The @code{d} register.
1938 The @code{si} register.
1941 The @code{di} register.
1944 The @code{a} and @code{d} registers, as a pair (for instructions that
1945 return half the result in one and half in the other).
1948 Any 80387 floating-point (stack) register.
1951 Top of 80387 floating-point stack (@code{%st(0)}).
1954 Second from top of 80387 floating-point stack (@code{%st(1)}).
1968 Integer constant in the range 0 @dots{} 31, for 32-bit shifts.
1971 Integer constant in the range 0 @dots{} 63, for 64-bit shifts.
1974 Signed 8-bit integer constant.
1977 @code{0xFF} or @code{0xFFFF}, for andsi as a zero-extending move.
1980 0, 1, 2, or 3 (shifts for the @code{lea} instruction).
1983 Unsigned 8-bit integer constant (for @code{in} and @code{out}
1988 Integer constant in the range 0 @dots{} 127, for 128-bit shifts.
1992 Standard 80387 floating point constant.
1995 Standard SSE floating point constant.
1998 32-bit signed integer constant, or a symbolic reference known
1999 to fit that range (for immediate operands in sign-extending x86-64
2003 32-bit unsigned integer constant, or a symbolic reference known
2004 to fit that range (for immediate operands in zero-extending x86-64
2009 @item Intel IA-64---@file{config/ia64/ia64.h}
2012 General register @code{r0} to @code{r3} for @code{addl} instruction
2018 Predicate register (@samp{c} as in ``conditional'')
2021 Application register residing in M-unit
2024 Application register residing in I-unit
2027 Floating-point register
2031 Remember that @samp{m} allows postincrement and postdecrement which
2032 require printing with @samp{%Pn} on IA-64.
2033 Use @samp{S} to disallow postincrement and postdecrement.
2036 Floating-point constant 0.0 or 1.0
2039 14-bit signed integer constant
2042 22-bit signed integer constant
2045 8-bit signed integer constant for logical instructions
2048 8-bit adjusted signed integer constant for compare pseudo-ops
2051 6-bit unsigned integer constant for shift counts
2054 9-bit signed integer constant for load and store postincrements
2060 0 or @minus{}1 for @code{dep} instruction
2063 Non-volatile memory for floating-point loads and stores
2066 Integer constant in the range 1 to 4 for @code{shladd} instruction
2069 Memory operand except postincrement and postdecrement
2072 @item FRV---@file{config/frv/frv.h}
2075 Register in the class @code{ACC_REGS} (@code{acc0} to @code{acc7}).
2078 Register in the class @code{EVEN_ACC_REGS} (@code{acc0} to @code{acc7}).
2081 Register in the class @code{CC_REGS} (@code{fcc0} to @code{fcc3} and
2082 @code{icc0} to @code{icc3}).
2085 Register in the class @code{GPR_REGS} (@code{gr0} to @code{gr63}).
2088 Register in the class @code{EVEN_REGS} (@code{gr0} to @code{gr63}).
2089 Odd registers are excluded not in the class but through the use of a machine
2090 mode larger than 4 bytes.
2093 Register in the class @code{FPR_REGS} (@code{fr0} to @code{fr63}).
2096 Register in the class @code{FEVEN_REGS} (@code{fr0} to @code{fr63}).
2097 Odd registers are excluded not in the class but through the use of a machine
2098 mode larger than 4 bytes.
2101 Register in the class @code{LR_REG} (the @code{lr} register).
2104 Register in the class @code{QUAD_REGS} (@code{gr2} to @code{gr63}).
2105 Register numbers not divisible by 4 are excluded not in the class but through
2106 the use of a machine mode larger than 8 bytes.
2109 Register in the class @code{ICC_REGS} (@code{icc0} to @code{icc3}).
2112 Register in the class @code{FCC_REGS} (@code{fcc0} to @code{fcc3}).
2115 Register in the class @code{ICR_REGS} (@code{cc4} to @code{cc7}).
2118 Register in the class @code{FCR_REGS} (@code{cc0} to @code{cc3}).
2121 Register in the class @code{QUAD_FPR_REGS} (@code{fr0} to @code{fr63}).
2122 Register numbers not divisible by 4 are excluded not in the class but through
2123 the use of a machine mode larger than 8 bytes.
2126 Register in the class @code{SPR_REGS} (@code{lcr} and @code{lr}).
2129 Register in the class @code{QUAD_ACC_REGS} (@code{acc0} to @code{acc7}).
2132 Register in the class @code{ACCG_REGS} (@code{accg0} to @code{accg7}).
2135 Register in the class @code{CR_REGS} (@code{cc0} to @code{cc7}).
2138 Floating point constant zero
2141 6-bit signed integer constant
2144 10-bit signed integer constant
2147 16-bit signed integer constant
2150 16-bit unsigned integer constant
2153 12-bit signed integer constant that is negative---i.e.@: in the
2154 range of @minus{}2048 to @minus{}1
2160 12-bit signed integer constant that is greater than zero---i.e.@: in the
2165 @item Blackfin family---@file{config/bfin/bfin.h}
2174 A call clobbered P register.
2177 Even-numbered D register
2180 Odd-numbered D register
2183 Accumulator register.
2186 Even-numbered accumulator register.
2189 Odd-numbered accumulator register.
2201 Registers used for circular buffering, i.e. I, B, or L registers.
2216 Any D, P, B, M, I or L register.
2219 Additional registers typically used only in prologues and epilogues: RETS,
2220 RETN, RETI, RETX, RETE, ASTAT, SEQSTAT and USP.
2223 Any register except accumulators or CC.
2226 Signed 16 bit integer (in the range -32768 to 32767)
2229 Unsigned 16 bit integer (in the range 0 to 65535)
2232 Signed 7 bit integer (in the range -64 to 63)
2235 Unsigned 7 bit integer (in the range 0 to 127)
2238 Unsigned 5 bit integer (in the range 0 to 31)
2241 Signed 4 bit integer (in the range -8 to 7)
2244 Signed 3 bit integer (in the range -3 to 4)
2247 Unsigned 3 bit integer (in the range 0 to 7)
2250 Constant @var{n}, where @var{n} is a single-digit constant in the range 0 to 4.
2253 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2254 use with either accumulator.
2257 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2258 use only with accumulator A1.
2267 An integer constant with exactly a single bit set.
2270 An integer constant with all bits set except exactly one.
2278 @item M32C---@file{config/m32c/m32c.c}
2283 @samp{$sp}, @samp{$fb}, @samp{$sb}.
2286 Any control register, when they're 16 bits wide (nothing if control
2287 registers are 24 bits wide)
2290 Any control register, when they're 24 bits wide.
2299 $r0 or $r2, or $r2r0 for 32 bit values.
2302 $r1 or $r3, or $r3r1 for 32 bit values.
2305 A register that can hold a 64 bit value.
2308 $r0 or $r1 (registers with addressable high/low bytes)
2317 Address registers when they're 16 bits wide.
2320 Address registers when they're 24 bits wide.
2323 Registers that can hold QI values.
2326 Registers that can be used with displacements ($a0, $a1, $sb).
2329 Registers that can hold 32 bit values.
2332 Registers that can hold 16 bit values.
2335 Registers chat can hold 16 bit values, including all control
2339 $r0 through R1, plus $a0 and $a1.
2345 The memory-based pseudo-registers $mem0 through $mem15.
2348 Registers that can hold pointers (16 bit registers for r8c, m16c; 24
2349 bit registers for m32cm, m32c).
2352 Matches multiple registers in a PARALLEL to form a larger register.
2353 Used to match function return values.
2362 -32768 @dots{} 32767
2368 -8 @dots{} -1 or 1 @dots{} 8
2371 -16 @dots{} -1 or 1 @dots{} 16
2374 -32 @dots{} -1 or 1 @dots{} 32
2380 An 8 bit value with exactly one bit set.
2383 A 16 bit value with exactly one bit set.
2386 The common src/dest memory addressing modes.
2389 Memory addressed using $a0 or $a1.
2392 Memory addressed with immediate addresses.
2395 Memory addressed using the stack pointer ($sp).
2398 Memory addressed using the frame base register ($fb).
2401 Memory addressed using the small base register ($sb).
2407 @item MIPS---@file{config/mips/constraints.md}
2410 An address register. This is equivalent to @code{r} unless
2411 generating MIPS16 code.
2414 A floating-point register (if available).
2417 The @code{hi} register.
2420 The @code{lo} register.
2423 The @code{hi} and @code{lo} registers.
2426 A register suitable for use in an indirect jump. This will always be
2427 @code{$25} for @option{-mabicalls}.
2430 Equivalent to @code{r}; retained for backwards compatibility.
2433 A floating-point condition code register.
2436 A signed 16-bit constant (for arithmetic instructions).
2442 An unsigned 16-bit constant (for logic instructions).
2445 A signed 32-bit constant in which the lower 16 bits are zero.
2446 Such constants can be loaded using @code{lui}.
2449 A constant that cannot be loaded using @code{lui}, @code{addiu}
2453 A constant in the range -65535 to -1 (inclusive).
2456 A signed 15-bit constant.
2459 A constant in the range 1 to 65535 (inclusive).
2462 Floating-point zero.
2465 An address that can be used in a non-macro load or store.
2468 @item Motorola 680x0---@file{config/m68k/m68k.h}
2477 68881 floating-point register, if available
2480 Integer in the range 1 to 8
2483 16-bit signed number
2486 Signed number whose magnitude is greater than 0x80
2489 Integer in the range @minus{}8 to @minus{}1
2492 Signed number whose magnitude is greater than 0x100
2495 Floating point constant that is not a 68881 constant
2498 @item Motorola 68HC11 & 68HC12 families---@file{config/m68hc11/m68hc11.h}
2513 Temporary soft register _.tmp
2516 A soft register _.d1 to _.d31
2519 Stack pointer register
2528 Pseudo register `z' (replaced by `x' or `y' at the end)
2531 An address register: x, y or z
2534 An address register: x or y
2537 Register pair (x:d) to form a 32-bit value
2540 Constants in the range @minus{}65536 to 65535
2543 Constants whose 16-bit low part is zero
2546 Constant integer 1 or @minus{}1
2552 Constants in the range @minus{}8 to 2
2557 @item SPARC---@file{config/sparc/sparc.h}
2560 Floating-point register on the SPARC-V8 architecture and
2561 lower floating-point register on the SPARC-V9 architecture.
2564 Floating-point register. It is equivalent to @samp{f} on the
2565 SPARC-V8 architecture and contains both lower and upper
2566 floating-point registers on the SPARC-V9 architecture.
2569 Floating-point condition code register.
2572 Lower floating-point register. It is only valid on the SPARC-V9
2573 architecture when the Visual Instruction Set is available.
2576 Floating-point register. It is only valid on the SPARC-V9 architecture
2577 when the Visual Instruction Set is available.
2580 64-bit global or out register for the SPARC-V8+ architecture.
2583 Signed 13-bit constant
2589 32-bit constant with the low 12 bits clear (a constant that can be
2590 loaded with the @code{sethi} instruction)
2593 A constant in the range supported by @code{movcc} instructions
2596 A constant in the range supported by @code{movrcc} instructions
2599 Same as @samp{K}, except that it verifies that bits that are not in the
2600 lower 32-bit range are all zero. Must be used instead of @samp{K} for
2601 modes wider than @code{SImode}
2610 Signed 13-bit constant, sign-extended to 32 or 64 bits
2613 Floating-point constant whose integral representation can
2614 be moved into an integer register using a single sethi
2618 Floating-point constant whose integral representation can
2619 be moved into an integer register using a single mov
2623 Floating-point constant whose integral representation can
2624 be moved into an integer register using a high/lo_sum
2625 instruction sequence
2628 Memory address aligned to an 8-byte boundary
2634 Memory address for @samp{e} constraint registers
2641 @item SPU---@file{config/spu/spu.h}
2644 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 64 bit value.
2647 An immediate for and/xor/or instructions. const_int is treated as a 64 bit value.
2650 An immediate for the @code{iohl} instruction. const_int is treated as a 64 bit value.
2653 An immediate which can be loaded with @code{fsmbi}.
2656 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 32 bit value.
2659 An immediate for most arithmetic instructions. const_int is treated as a 32 bit value.
2662 An immediate for and/xor/or instructions. const_int is treated as a 32 bit value.
2665 An immediate for the @code{iohl} instruction. const_int is treated as a 32 bit value.
2668 A constant in the range [-64, 63] for shift/rotate instructions.
2671 An unsigned 7-bit constant for conversion/nop/channel instructions.
2674 A signed 10-bit constant for most arithmetic instructions.
2677 A signed 16 bit immediate for @code{stop}.
2680 An unsigned 16-bit constant for @code{iohl} and @code{fsmbi}.
2683 An unsigned 7-bit constant whose 3 least significant bits are 0.
2686 An unsigned 3-bit constant for 16-byte rotates and shifts
2689 Call operand, reg, for indirect calls
2692 Call operand, symbol, for relative calls.
2695 Call operand, const_int, for absolute calls.
2698 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is sign extended to 128 bit.
2701 An immediate for shift and rotate instructions. const_int is treated as a 32 bit value.
2704 An immediate for and/xor/or instructions. const_int is sign extended as a 128 bit.
2707 An immediate for the @code{iohl} instruction. const_int is sign extended to 128 bit.
2711 @item TMS320C3x/C4x---@file{config/c4x/c4x.h}
2714 Auxiliary (address) register (ar0-ar7)
2717 Stack pointer register (sp)
2720 Standard (32-bit) precision integer register
2723 Extended (40-bit) precision register (r0-r11)
2726 Block count register (bk)
2729 Extended (40-bit) precision low register (r0-r7)
2732 Extended (40-bit) precision register (r0-r1)
2735 Extended (40-bit) precision register (r2-r3)
2738 Repeat count register (rc)
2741 Index register (ir0-ir1)
2744 Status (condition code) register (st)
2747 Data page register (dp)
2753 Immediate 16-bit floating-point constant
2756 Signed 16-bit constant
2759 Signed 8-bit constant
2762 Signed 5-bit constant
2765 Unsigned 16-bit constant
2768 Unsigned 8-bit constant
2771 Ones complement of unsigned 16-bit constant
2774 High 16-bit constant (32-bit constant with 16 LSBs zero)
2777 Indirect memory reference with signed 8-bit or index register displacement
2780 Indirect memory reference with unsigned 5-bit displacement
2783 Indirect memory reference with 1 bit or index register displacement
2786 Direct memory reference
2793 @item S/390 and zSeries---@file{config/s390/s390.h}
2796 Address register (general purpose register except r0)
2799 Condition code register
2802 Data register (arbitrary general purpose register)
2805 Floating-point register
2808 Unsigned 8-bit constant (0--255)
2811 Unsigned 12-bit constant (0--4095)
2814 Signed 16-bit constant (@minus{}32768--32767)
2817 Value appropriate as displacement.
2820 for short displacement
2821 @item (-524288..524287)
2822 for long displacement
2826 Constant integer with a value of 0x7fffffff.
2829 Multiple letter constraint followed by 4 parameter letters.
2832 number of the part counting from most to least significant
2836 mode of the containing operand
2838 value of the other parts (F---all bits set)
2840 The constraint matches if the specified part of a constant
2841 has a value different from it's other parts.
2844 Memory reference without index register and with short displacement.
2847 Memory reference with index register and short displacement.
2850 Memory reference without index register but with long displacement.
2853 Memory reference with index register and long displacement.
2856 Pointer with short displacement.
2859 Pointer with long displacement.
2862 Shift count operand.
2866 @item Score family---@file{config/score/score.h}
2869 Registers from r0 to r32.
2872 Registers from r0 to r16.
2875 r8---r11 or r22---r27 registers.
2896 cnt + lcb + scb register.
2899 cr0---cr15 register.
2911 cp1 + cp2 + cp3 registers.
2914 High 16-bit constant (32-bit constant with 16 LSBs zero).
2917 Unsigned 5 bit integer (in the range 0 to 31).
2920 Unsigned 16 bit integer (in the range 0 to 65535).
2923 Signed 16 bit integer (in the range @minus{}32768 to 32767).
2926 Unsigned 14 bit integer (in the range 0 to 16383).
2929 Signed 14 bit integer (in the range @minus{}8192 to 8191).
2935 @item Xstormy16---@file{config/stormy16/stormy16.h}
2950 Registers r0 through r7.
2953 Registers r0 and r1.
2959 Registers r8 and r9.
2962 A constant between 0 and 3 inclusive.
2965 A constant that has exactly one bit set.
2968 A constant that has exactly one bit clear.
2971 A constant between 0 and 255 inclusive.
2974 A constant between @minus{}255 and 0 inclusive.
2977 A constant between @minus{}3 and 0 inclusive.
2980 A constant between 1 and 4 inclusive.
2983 A constant between @minus{}4 and @minus{}1 inclusive.
2986 A memory reference that is a stack push.
2989 A memory reference that is a stack pop.
2992 A memory reference that refers to a constant address of known value.
2995 The register indicated by Rx (not implemented yet).
2998 A constant that is not between 2 and 15 inclusive.
3005 @item Xtensa---@file{config/xtensa/constraints.md}
3008 General-purpose 32-bit register
3011 One-bit boolean register
3014 MAC16 40-bit accumulator register
3017 Signed 12-bit integer constant, for use in MOVI instructions
3020 Signed 8-bit integer constant, for use in ADDI instructions
3023 Integer constant valid for BccI instructions
3026 Unsigned constant valid for BccUI instructions
3033 @node Define Constraints
3034 @subsection Defining Machine-Specific Constraints
3035 @cindex defining constraints
3036 @cindex constraints, defining
3038 Machine-specific constraints fall into two categories: register and
3039 non-register constraints. Within the latter category, constraints
3040 which allow subsets of all possible memory or address operands should
3041 be specially marked, to give @code{reload} more information.
3043 Machine-specific constraints can be given names of arbitrary length,
3044 but they must be entirely composed of letters, digits, underscores
3045 (@samp{_}), and angle brackets (@samp{< >}). Like C identifiers, they
3046 must begin with a letter or underscore.
3048 In order to avoid ambiguity in operand constraint strings, no
3049 constraint can have a name that begins with any other constraint's
3050 name. For example, if @code{x} is defined as a constraint name,
3051 @code{xy} may not be, and vice versa. As a consequence of this rule,
3052 no constraint may begin with one of the generic constraint letters:
3053 @samp{E F V X g i m n o p r s}.
3055 Register constraints correspond directly to register classes.
3056 @xref{Register Classes}. There is thus not much flexibility in their
3059 @deffn {MD Expression} define_register_constraint name regclass docstring
3060 All three arguments are string constants.
3061 @var{name} is the name of the constraint, as it will appear in
3062 @code{match_operand} expressions. If @var{name} is a multi-letter
3063 constraint its length shall be the same for all constraints starting
3064 with the same letter. @var{regclass} can be either the
3065 name of the corresponding register class (@pxref{Register Classes}),
3066 or a C expression which evaluates to the appropriate register class.
3067 If it is an expression, it must have no side effects, and it cannot
3068 look at the operand. The usual use of expressions is to map some
3069 register constraints to @code{NO_REGS} when the register class
3070 is not available on a given subarchitecture.
3072 @var{docstring} is a sentence documenting the meaning of the
3073 constraint. Docstrings are explained further below.
3076 Non-register constraints are more like predicates: the constraint
3077 definition gives a Boolean expression which indicates whether the
3080 @deffn {MD Expression} define_constraint name docstring exp
3081 The @var{name} and @var{docstring} arguments are the same as for
3082 @code{define_register_constraint}, but note that the docstring comes
3083 immediately after the name for these expressions. @var{exp} is an RTL
3084 expression, obeying the same rules as the RTL expressions in predicate
3085 definitions. @xref{Defining Predicates}, for details. If it
3086 evaluates true, the constraint matches; if it evaluates false, it
3087 doesn't. Constraint expressions should indicate which RTL codes they
3088 might match, just like predicate expressions.
3090 @code{match_test} C expressions have access to the
3091 following variables:
3095 The RTL object defining the operand.
3097 The machine mode of @var{op}.
3099 @samp{INTVAL (@var{op})}, if @var{op} is a @code{const_int}.
3101 @samp{CONST_DOUBLE_HIGH (@var{op})}, if @var{op} is an integer
3102 @code{const_double}.
3104 @samp{CONST_DOUBLE_LOW (@var{op})}, if @var{op} is an integer
3105 @code{const_double}.
3107 @samp{CONST_DOUBLE_REAL_VALUE (@var{op})}, if @var{op} is a floating-point
3108 @code{const_double}.
3111 The @var{*val} variables should only be used once another piece of the
3112 expression has verified that @var{op} is the appropriate kind of RTL
3116 Most non-register constraints should be defined with
3117 @code{define_constraint}. The remaining two definition expressions
3118 are only appropriate for constraints that should be handled specially
3119 by @code{reload} if they fail to match.
3121 @deffn {MD Expression} define_memory_constraint name docstring exp
3122 Use this expression for constraints that match a subset of all memory
3123 operands: that is, @code{reload} can make them match by converting the
3124 operand to the form @samp{@w{(mem (reg @var{X}))}}, where @var{X} is a
3125 base register (from the register class specified by
3126 @code{BASE_REG_CLASS}, @pxref{Register Classes}).
3128 For example, on the S/390, some instructions do not accept arbitrary
3129 memory references, but only those that do not make use of an index
3130 register. The constraint letter @samp{Q} is defined to represent a
3131 memory address of this type. If @samp{Q} is defined with
3132 @code{define_memory_constraint}, a @samp{Q} constraint can handle any
3133 memory operand, because @code{reload} knows it can simply copy the
3134 memory address into a base register if required. This is analogous to
3135 the way a @samp{o} constraint can handle any memory operand.
3137 The syntax and semantics are otherwise identical to
3138 @code{define_constraint}.
3141 @deffn {MD Expression} define_address_constraint name docstring exp
3142 Use this expression for constraints that match a subset of all address
3143 operands: that is, @code{reload} can make the constraint match by
3144 converting the operand to the form @samp{@w{(reg @var{X})}}, again
3145 with @var{X} a base register.
3147 Constraints defined with @code{define_address_constraint} can only be
3148 used with the @code{address_operand} predicate, or machine-specific
3149 predicates that work the same way. They are treated analogously to
3150 the generic @samp{p} constraint.
3152 The syntax and semantics are otherwise identical to
3153 @code{define_constraint}.
3156 For historical reasons, names beginning with the letters @samp{G H}
3157 are reserved for constraints that match only @code{const_double}s, and
3158 names beginning with the letters @samp{I J K L M N O P} are reserved
3159 for constraints that match only @code{const_int}s. This may change in
3160 the future. For the time being, constraints with these names must be
3161 written in a stylized form, so that @code{genpreds} can tell you did
3166 (define_constraint "[@var{GHIJKLMNOP}]@dots{}"
3168 (and (match_code "const_int") ; @r{@code{const_double} for G/H}
3169 @var{condition}@dots{})) ; @r{usually a @code{match_test}}
3172 @c the semicolons line up in the formatted manual
3174 It is fine to use names beginning with other letters for constraints
3175 that match @code{const_double}s or @code{const_int}s.
3177 Each docstring in a constraint definition should be one or more complete
3178 sentences, marked up in Texinfo format. @emph{They are currently unused.}
3179 In the future they will be copied into the GCC manual, in @ref{Machine
3180 Constraints}, replacing the hand-maintained tables currently found in
3181 that section. Also, in the future the compiler may use this to give
3182 more helpful diagnostics when poor choice of @code{asm} constraints
3183 causes a reload failure.
3185 If you put the pseudo-Texinfo directive @samp{@@internal} at the
3186 beginning of a docstring, then (in the future) it will appear only in
3187 the internals manual's version of the machine-specific constraint tables.
3188 Use this for constraints that should not appear in @code{asm} statements.
3190 @node C Constraint Interface
3191 @subsection Testing constraints from C
3192 @cindex testing constraints
3193 @cindex constraints, testing
3195 It is occasionally useful to test a constraint from C code rather than
3196 implicitly via the constraint string in a @code{match_operand}. The
3197 generated file @file{tm_p.h} declares a few interfaces for working
3198 with machine-specific constraints. None of these interfaces work with
3199 the generic constraints described in @ref{Simple Constraints}. This
3200 may change in the future.
3202 @strong{Warning:} @file{tm_p.h} may declare other functions that
3203 operate on constraints, besides the ones documented here. Do not use
3204 those functions from machine-dependent code. They exist to implement
3205 the old constraint interface that machine-independent components of
3206 the compiler still expect. They will change or disappear in the
3209 Some valid constraint names are not valid C identifiers, so there is a
3210 mangling scheme for referring to them from C@. Constraint names that
3211 do not contain angle brackets or underscores are left unchanged.
3212 Underscores are doubled, each @samp{<} is replaced with @samp{_l}, and
3213 each @samp{>} with @samp{_g}. Here are some examples:
3215 @c the @c's prevent double blank lines in the printed manual.
3217 @multitable {Original} {Mangled}
3218 @item @strong{Original} @tab @strong{Mangled} @c
3219 @item @code{x} @tab @code{x} @c
3220 @item @code{P42x} @tab @code{P42x} @c
3221 @item @code{P4_x} @tab @code{P4__x} @c
3222 @item @code{P4>x} @tab @code{P4_gx} @c
3223 @item @code{P4>>} @tab @code{P4_g_g} @c
3224 @item @code{P4_g>} @tab @code{P4__g_g} @c
3228 Throughout this section, the variable @var{c} is either a constraint
3229 in the abstract sense, or a constant from @code{enum constraint_num};
3230 the variable @var{m} is a mangled constraint name (usually as part of
3231 a larger identifier).
3233 @deftp Enum constraint_num
3234 For each machine-specific constraint, there is a corresponding
3235 enumeration constant: @samp{CONSTRAINT_} plus the mangled name of the
3236 constraint. Functions that take an @code{enum constraint_num} as an
3237 argument expect one of these constants.
3239 Machine-independent constraints do not have associated constants.
3240 This may change in the future.
3243 @deftypefun {inline bool} satisfies_constraint_@var{m} (rtx @var{exp})
3244 For each machine-specific, non-register constraint @var{m}, there is
3245 one of these functions; it returns @code{true} if @var{exp} satisfies the
3246 constraint. These functions are only visible if @file{rtl.h} was included
3247 before @file{tm_p.h}.
3250 @deftypefun bool constraint_satisfied_p (rtx @var{exp}, enum constraint_num @var{c})
3251 Like the @code{satisfies_constraint_@var{m}} functions, but the
3252 constraint to test is given as an argument, @var{c}. If @var{c}
3253 specifies a register constraint, this function will always return
3257 @deftypefun {enum reg_class} regclass_for_constraint (enum constraint_num @var{c})
3258 Returns the register class associated with @var{c}. If @var{c} is not
3259 a register constraint, or those registers are not available for the
3260 currently selected subtarget, returns @code{NO_REGS}.
3263 Here is an example use of @code{satisfies_constraint_@var{m}}. In
3264 peephole optimizations (@pxref{Peephole Definitions}), operand
3265 constraint strings are ignored, so if there are relevant constraints,
3266 they must be tested in the C condition. In the example, the
3267 optimization is applied if operand 2 does @emph{not} satisfy the
3268 @samp{K} constraint. (This is a simplified version of a peephole
3269 definition from the i386 machine description.)
3273 [(match_scratch:SI 3 "r")
3274 (set (match_operand:SI 0 "register_operand" "")
3275 (mult:SI (match_operand:SI 1 "memory_operand" "")
3276 (match_operand:SI 2 "immediate_operand" "")))]
3278 "!satisfies_constraint_K (operands[2])"
3280 [(set (match_dup 3) (match_dup 1))
3281 (set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))]
3286 @node Standard Names
3287 @section Standard Pattern Names For Generation
3288 @cindex standard pattern names
3289 @cindex pattern names
3290 @cindex names, pattern
3292 Here is a table of the instruction names that are meaningful in the RTL
3293 generation pass of the compiler. Giving one of these names to an
3294 instruction pattern tells the RTL generation pass that it can use the
3295 pattern to accomplish a certain task.
3298 @cindex @code{mov@var{m}} instruction pattern
3299 @item @samp{mov@var{m}}
3300 Here @var{m} stands for a two-letter machine mode name, in lowercase.
3301 This instruction pattern moves data with that machine mode from operand
3302 1 to operand 0. For example, @samp{movsi} moves full-word data.
3304 If operand 0 is a @code{subreg} with mode @var{m} of a register whose
3305 own mode is wider than @var{m}, the effect of this instruction is
3306 to store the specified value in the part of the register that corresponds
3307 to mode @var{m}. Bits outside of @var{m}, but which are within the
3308 same target word as the @code{subreg} are undefined. Bits which are
3309 outside the target word are left unchanged.
3311 This class of patterns is special in several ways. First of all, each
3312 of these names up to and including full word size @emph{must} be defined,
3313 because there is no other way to copy a datum from one place to another.
3314 If there are patterns accepting operands in larger modes,
3315 @samp{mov@var{m}} must be defined for integer modes of those sizes.
3317 Second, these patterns are not used solely in the RTL generation pass.
3318 Even the reload pass can generate move insns to copy values from stack
3319 slots into temporary registers. When it does so, one of the operands is
3320 a hard register and the other is an operand that can need to be reloaded
3324 Therefore, when given such a pair of operands, the pattern must generate
3325 RTL which needs no reloading and needs no temporary registers---no
3326 registers other than the operands. For example, if you support the
3327 pattern with a @code{define_expand}, then in such a case the
3328 @code{define_expand} mustn't call @code{force_reg} or any other such
3329 function which might generate new pseudo registers.
3331 This requirement exists even for subword modes on a RISC machine where
3332 fetching those modes from memory normally requires several insns and
3333 some temporary registers.
3335 @findex change_address
3336 During reload a memory reference with an invalid address may be passed
3337 as an operand. Such an address will be replaced with a valid address
3338 later in the reload pass. In this case, nothing may be done with the
3339 address except to use it as it stands. If it is copied, it will not be
3340 replaced with a valid address. No attempt should be made to make such
3341 an address into a valid address and no routine (such as
3342 @code{change_address}) that will do so may be called. Note that
3343 @code{general_operand} will fail when applied to such an address.
3345 @findex reload_in_progress
3346 The global variable @code{reload_in_progress} (which must be explicitly
3347 declared if required) can be used to determine whether such special
3348 handling is required.
3350 The variety of operands that have reloads depends on the rest of the
3351 machine description, but typically on a RISC machine these can only be
3352 pseudo registers that did not get hard registers, while on other
3353 machines explicit memory references will get optional reloads.
3355 If a scratch register is required to move an object to or from memory,
3356 it can be allocated using @code{gen_reg_rtx} prior to life analysis.
3358 If there are cases which need scratch registers during or after reload,
3359 you must provide an appropriate secondary_reload target hook.
3361 @findex no_new_pseudos
3362 The global variable @code{no_new_pseudos} can be used to determine if it
3363 is unsafe to create new pseudo registers. If this variable is nonzero, then
3364 it is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo.
3366 The constraints on a @samp{mov@var{m}} must permit moving any hard
3367 register to any other hard register provided that
3368 @code{HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and
3369 @code{REGISTER_MOVE_COST} applied to their classes returns a value of 2.
3371 It is obligatory to support floating point @samp{mov@var{m}}
3372 instructions into and out of any registers that can hold fixed point
3373 values, because unions and structures (which have modes @code{SImode} or
3374 @code{DImode}) can be in those registers and they may have floating
3377 There may also be a need to support fixed point @samp{mov@var{m}}
3378 instructions in and out of floating point registers. Unfortunately, I
3379 have forgotten why this was so, and I don't know whether it is still
3380 true. If @code{HARD_REGNO_MODE_OK} rejects fixed point values in
3381 floating point registers, then the constraints of the fixed point
3382 @samp{mov@var{m}} instructions must be designed to avoid ever trying to
3383 reload into a floating point register.
3385 @cindex @code{reload_in} instruction pattern
3386 @cindex @code{reload_out} instruction pattern
3387 @item @samp{reload_in@var{m}}
3388 @itemx @samp{reload_out@var{m}}
3389 These named patterns have been obsoleted by the target hook
3390 @code{secondary_reload}.
3392 Like @samp{mov@var{m}}, but used when a scratch register is required to
3393 move between operand 0 and operand 1. Operand 2 describes the scratch
3394 register. See the discussion of the @code{SECONDARY_RELOAD_CLASS}
3395 macro in @pxref{Register Classes}.
3397 There are special restrictions on the form of the @code{match_operand}s
3398 used in these patterns. First, only the predicate for the reload
3399 operand is examined, i.e., @code{reload_in} examines operand 1, but not
3400 the predicates for operand 0 or 2. Second, there may be only one
3401 alternative in the constraints. Third, only a single register class
3402 letter may be used for the constraint; subsequent constraint letters
3403 are ignored. As a special exception, an empty constraint string
3404 matches the @code{ALL_REGS} register class. This may relieve ports
3405 of the burden of defining an @code{ALL_REGS} constraint letter just
3408 @cindex @code{movstrict@var{m}} instruction pattern
3409 @item @samp{movstrict@var{m}}
3410 Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg}
3411 with mode @var{m} of a register whose natural mode is wider,
3412 the @samp{movstrict@var{m}} instruction is guaranteed not to alter
3413 any of the register except the part which belongs to mode @var{m}.
3415 @cindex @code{movmisalign@var{m}} instruction pattern
3416 @item @samp{movmisalign@var{m}}
3417 This variant of a move pattern is designed to load or store a value
3418 from a memory address that is not naturally aligned for its mode.
3419 For a store, the memory will be in operand 0; for a load, the memory
3420 will be in operand 1. The other operand is guaranteed not to be a
3421 memory, so that it's easy to tell whether this is a load or store.
3423 This pattern is used by the autovectorizer, and when expanding a
3424 @code{MISALIGNED_INDIRECT_REF} expression.
3426 @cindex @code{load_multiple} instruction pattern
3427 @item @samp{load_multiple}
3428 Load several consecutive memory locations into consecutive registers.
3429 Operand 0 is the first of the consecutive registers, operand 1
3430 is the first memory location, and operand 2 is a constant: the
3431 number of consecutive registers.
3433 Define this only if the target machine really has such an instruction;
3434 do not define this if the most efficient way of loading consecutive
3435 registers from memory is to do them one at a time.
3437 On some machines, there are restrictions as to which consecutive
3438 registers can be stored into memory, such as particular starting or
3439 ending register numbers or only a range of valid counts. For those
3440 machines, use a @code{define_expand} (@pxref{Expander Definitions})
3441 and make the pattern fail if the restrictions are not met.
3443 Write the generated insn as a @code{parallel} with elements being a
3444 @code{set} of one register from the appropriate memory location (you may
3445 also need @code{use} or @code{clobber} elements). Use a
3446 @code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See
3447 @file{rs6000.md} for examples of the use of this insn pattern.
3449 @cindex @samp{store_multiple} instruction pattern
3450 @item @samp{store_multiple}
3451 Similar to @samp{load_multiple}, but store several consecutive registers
3452 into consecutive memory locations. Operand 0 is the first of the
3453 consecutive memory locations, operand 1 is the first register, and
3454 operand 2 is a constant: the number of consecutive registers.
3456 @cindex @code{vec_set@var{m}} instruction pattern
3457 @item @samp{vec_set@var{m}}
3458 Set given field in the vector value. Operand 0 is the vector to modify,
3459 operand 1 is new value of field and operand 2 specify the field index.
3461 @cindex @code{vec_extract@var{m}} instruction pattern
3462 @item @samp{vec_extract@var{m}}
3463 Extract given field from the vector value. Operand 1 is the vector, operand 2
3464 specify field index and operand 0 place to store value into.
3466 @cindex @code{vec_extract_even@var{m}} instruction pattern
3467 @item @samp{vec_extract_even@var{m}}
3468 Extract even elements from the input vectors (operand 1 and operand 2).
3469 The even elements of operand 2 are concatenated to the even elements of operand
3470 1 in their original order. The result is stored in operand 0.
3471 The output and input vectors should have the same modes.
3473 @cindex @code{vec_extract_odd@var{m}} instruction pattern
3474 @item @samp{vec_extract_odd@var{m}}
3475 Extract odd elements from the input vectors (operand 1 and operand 2).
3476 The odd elements of operand 2 are concatenated to the odd elements of operand
3477 1 in their original order. The result is stored in operand 0.
3478 The output and input vectors should have the same modes.
3480 @cindex @code{vec_interleave_high@var{m}} instruction pattern
3481 @item @samp{vec_interleave_high@var{m}}
3482 Merge high elements of the two input vectors into the output vector. The output
3483 and input vectors should have the same modes (@code{N} elements). The high
3484 @code{N/2} elements of the first input vector are interleaved with the high
3485 @code{N/2} elements of the second input vector.
3487 @cindex @code{vec_interleave_low@var{m}} instruction pattern
3488 @item @samp{vec_interleave_low@var{m}}
3489 Merge low elements of the two input vectors into the output vector. The output
3490 and input vectors should have the same modes (@code{N} elements). The low
3491 @code{N/2} elements of the first input vector are interleaved with the low
3492 @code{N/2} elements of the second input vector.
3494 @cindex @code{vec_init@var{m}} instruction pattern
3495 @item @samp{vec_init@var{m}}
3496 Initialize the vector to given values. Operand 0 is the vector to initialize
3497 and operand 1 is parallel containing values for individual fields.
3499 @cindex @code{push@var{m}1} instruction pattern
3500 @item @samp{push@var{m}1}
3501 Output a push instruction. Operand 0 is value to push. Used only when
3502 @code{PUSH_ROUNDING} is defined. For historical reason, this pattern may be
3503 missing and in such case an @code{mov} expander is used instead, with a
3504 @code{MEM} expression forming the push operation. The @code{mov} expander
3505 method is deprecated.
3507 @cindex @code{add@var{m}3} instruction pattern
3508 @item @samp{add@var{m}3}
3509 Add operand 2 and operand 1, storing the result in operand 0. All operands
3510 must have mode @var{m}. This can be used even on two-address machines, by
3511 means of constraints requiring operands 1 and 0 to be the same location.
3513 @cindex @code{sub@var{m}3} instruction pattern
3514 @cindex @code{mul@var{m}3} instruction pattern
3515 @cindex @code{div@var{m}3} instruction pattern
3516 @cindex @code{udiv@var{m}3} instruction pattern
3517 @cindex @code{mod@var{m}3} instruction pattern
3518 @cindex @code{umod@var{m}3} instruction pattern
3519 @cindex @code{umin@var{m}3} instruction pattern
3520 @cindex @code{umax@var{m}3} instruction pattern
3521 @cindex @code{and@var{m}3} instruction pattern
3522 @cindex @code{ior@var{m}3} instruction pattern
3523 @cindex @code{xor@var{m}3} instruction pattern
3524 @item @samp{sub@var{m}3}, @samp{mul@var{m}3}
3525 @itemx @samp{div@var{m}3}, @samp{udiv@var{m}3}
3526 @itemx @samp{mod@var{m}3}, @samp{umod@var{m}3}
3527 @itemx @samp{umin@var{m}3}, @samp{umax@var{m}3}
3528 @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3}
3529 Similar, for other arithmetic operations.
3531 @cindex @code{min@var{m}3} instruction pattern
3532 @cindex @code{max@var{m}3} instruction pattern
3533 @item @samp{smin@var{m}3}, @samp{smax@var{m}3}
3534 Signed minimum and maximum operations. When used with floating point,
3535 if both operands are zeros, or if either operand is @code{NaN}, then
3536 it is unspecified which of the two operands is returned as the result.
3538 @cindex @code{reduc_smin_@var{m}} instruction pattern
3539 @cindex @code{reduc_smax_@var{m}} instruction pattern
3540 @item @samp{reduc_smin_@var{m}}, @samp{reduc_smax_@var{m}}
3541 Find the signed minimum/maximum of the elements of a vector. The vector is
3542 operand 1, and the scalar result is stored in the least significant bits of
3543 operand 0 (also a vector). The output and input vector should have the same
3546 @cindex @code{reduc_umin_@var{m}} instruction pattern
3547 @cindex @code{reduc_umax_@var{m}} instruction pattern
3548 @item @samp{reduc_umin_@var{m}}, @samp{reduc_umax_@var{m}}
3549 Find the unsigned minimum/maximum of the elements of a vector. The vector is
3550 operand 1, and the scalar result is stored in the least significant bits of
3551 operand 0 (also a vector). The output and input vector should have the same
3554 @cindex @code{reduc_splus_@var{m}} instruction pattern
3555 @item @samp{reduc_splus_@var{m}}
3556 Compute the sum of the signed elements of a vector. The vector is operand 1,
3557 and the scalar result is stored in the least significant bits of operand 0
3558 (also a vector). The output and input vector should have the same modes.
3560 @cindex @code{reduc_uplus_@var{m}} instruction pattern
3561 @item @samp{reduc_uplus_@var{m}}
3562 Compute the sum of the unsigned elements of a vector. The vector is operand 1,
3563 and the scalar result is stored in the least significant bits of operand 0
3564 (also a vector). The output and input vector should have the same modes.
3566 @cindex @code{sdot_prod@var{m}} instruction pattern
3567 @item @samp{sdot_prod@var{m}}
3568 @cindex @code{udot_prod@var{m}} instruction pattern
3569 @item @samp{udot_prod@var{m}}
3570 Compute the sum of the products of two signed/unsigned elements.
3571 Operand 1 and operand 2 are of the same mode. Their product, which is of a
3572 wider mode, is computed and added to operand 3. Operand 3 is of a mode equal or
3573 wider than the mode of the product. The result is placed in operand 0, which
3574 is of the same mode as operand 3.
3576 @cindex @code{ssum_widen@var{m3}} instruction pattern
3577 @item @samp{ssum_widen@var{m3}}
3578 @cindex @code{usum_widen@var{m3}} instruction pattern
3579 @item @samp{usum_widen@var{m3}}
3580 Operands 0 and 2 are of the same mode, which is wider than the mode of
3581 operand 1. Add operand 1 to operand 2 and place the widened result in
3582 operand 0. (This is used express accumulation of elements into an accumulator
3585 @cindex @code{vec_shl_@var{m}} instruction pattern
3586 @cindex @code{vec_shr_@var{m}} instruction pattern
3587 @item @samp{vec_shl_@var{m}}, @samp{vec_shr_@var{m}}
3588 Whole vector left/right shift in bits.
3589 Operand 1 is a vector to be shifted.
3590 Operand 2 is an integer shift amount in bits.
3591 Operand 0 is where the resulting shifted vector is stored.
3592 The output and input vectors should have the same modes.
3594 @cindex @code{vec_pack_trunc_@var{m}} instruction pattern
3595 @item @samp{vec_pack_trunc_@var{m}}
3596 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
3597 are vectors of the same mode having N integral or floating point elements
3598 of size S. Operand 0 is the resulting vector in which 2*N elements of
3599 size N/2 are concatenated after narrowing them down using truncation.
3601 @cindex @code{vec_pack_ssat_@var{m}} instruction pattern
3602 @cindex @code{vec_pack_usat_@var{m}} instruction pattern
3603 @item @samp{vec_pack_ssat_@var{m}}, @samp{vec_pack_usat_@var{m}}
3604 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
3605 are vectors of the same mode having N integral elements of size S.
3606 Operand 0 is the resulting vector in which the elements of the two input
3607 vectors are concatenated after narrowing them down using signed/unsigned
3608 saturating arithmetic.
3610 @cindex @code{vec_unpacks_hi_@var{m}} instruction pattern
3611 @cindex @code{vec_unpacks_lo_@var{m}} instruction pattern
3612 @item @samp{vec_unpacks_hi_@var{m}}, @samp{vec_unpacks_lo_@var{m}}
3613 Extract and widen (promote) the high/low part of a vector of signed
3614 integral or floating point elements. The input vector (operand 1) has N
3615 elements of size S. Widen (promote) the high/low elements of the vector
3616 using signed or floating point extension and place the resulting N/2
3617 values of size 2*S in the output vector (operand 0).
3619 @cindex @code{vec_unpacku_hi_@var{m}} instruction pattern
3620 @cindex @code{vec_unpacku_lo_@var{m}} instruction pattern
3621 @item @samp{vec_unpacku_hi_@var{m}}, @samp{vec_unpacku_lo_@var{m}}
3622 Extract and widen (promote) the high/low part of a vector of unsigned
3623 integral elements. The input vector (operand 1) has N elements of size S.
3624 Widen (promote) the high/low elements of the vector using zero extension and
3625 place the resulting N/2 values of size 2*S in the output vector (operand 0).
3627 @cindex @code{vec_widen_umult_hi_@var{m}} instruction pattern
3628 @cindex @code{vec_widen_umult_lo__@var{m}} instruction pattern
3629 @cindex @code{vec_widen_smult_hi_@var{m}} instruction pattern
3630 @cindex @code{vec_widen_smult_lo_@var{m}} instruction pattern
3631 @item @samp{vec_widen_umult_hi_@var{m}}, @samp{vec_widen_umult_lo_@var{m}}, @samp{vec_widen_smult_hi_@var{m}}, @samp{vec_widen_smult_lo_@var{m}}
3632 Signed/Unsigned widening multiplication. The two inputs (operands 1 and 2)
3633 are vectors with N signed/unsigned elements of size S. Multiply the high/low
3634 elements of the two vectors, and put the N/2 products of size 2*S in the
3635 output vector (operand 0).
3637 @cindex @code{mulhisi3} instruction pattern
3638 @item @samp{mulhisi3}
3639 Multiply operands 1 and 2, which have mode @code{HImode}, and store
3640 a @code{SImode} product in operand 0.
3642 @cindex @code{mulqihi3} instruction pattern
3643 @cindex @code{mulsidi3} instruction pattern
3644 @item @samp{mulqihi3}, @samp{mulsidi3}
3645 Similar widening-multiplication instructions of other widths.
3647 @cindex @code{umulqihi3} instruction pattern
3648 @cindex @code{umulhisi3} instruction pattern
3649 @cindex @code{umulsidi3} instruction pattern
3650 @item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3}
3651 Similar widening-multiplication instructions that do unsigned
3654 @cindex @code{usmulqihi3} instruction pattern
3655 @cindex @code{usmulhisi3} instruction pattern
3656 @cindex @code{usmulsidi3} instruction pattern
3657 @item @samp{usmulqihi3}, @samp{usmulhisi3}, @samp{usmulsidi3}
3658 Similar widening-multiplication instructions that interpret the first
3659 operand as unsigned and the second operand as signed, then do a signed
3662 @cindex @code{smul@var{m}3_highpart} instruction pattern
3663 @item @samp{smul@var{m}3_highpart}
3664 Perform a signed multiplication of operands 1 and 2, which have mode
3665 @var{m}, and store the most significant half of the product in operand 0.
3666 The least significant half of the product is discarded.
3668 @cindex @code{umul@var{m}3_highpart} instruction pattern
3669 @item @samp{umul@var{m}3_highpart}
3670 Similar, but the multiplication is unsigned.
3672 @cindex @code{madd@var{m}@var{n}4} instruction pattern
3673 @item @samp{madd@var{m}@var{n}4}
3674 Multiply operands 1 and 2, sign-extend them to mode @var{n}, add
3675 operand 3, and store the result in operand 0. Operands 1 and 2
3676 have mode @var{m} and operands 0 and 3 have mode @var{n}.
3677 Both modes must be integer modes and @var{n} must be twice
3678 the size of @var{m}.
3680 In other words, @code{madd@var{m}@var{n}4} is like
3681 @code{mul@var{m}@var{n}3} except that it also adds operand 3.
3683 These instructions are not allowed to @code{FAIL}.
3685 @cindex @code{umadd@var{m}@var{n}4} instruction pattern
3686 @item @samp{umadd@var{m}@var{n}4}
3687 Like @code{madd@var{m}@var{n}4}, but zero-extend the multiplication
3688 operands instead of sign-extending them.
3690 @cindex @code{msub@var{m}@var{n}4} instruction pattern
3691 @item @samp{msub@var{m}@var{n}4}
3692 Multiply operands 1 and 2, sign-extend them to mode @var{n}, subtract the
3693 result from operand 3, and store the result in operand 0. Operands 1 and 2
3694 have mode @var{m} and operands 0 and 3 have mode @var{n}.
3695 Both modes must be integer modes and @var{n} must be twice
3696 the size of @var{m}.
3698 In other words, @code{msub@var{m}@var{n}4} is like
3699 @code{mul@var{m}@var{n}3} except that it also subtracts the result
3702 These instructions are not allowed to @code{FAIL}.
3704 @cindex @code{umsub@var{m}@var{n}4} instruction pattern
3705 @item @samp{umsub@var{m}@var{n}4}
3706 Like @code{msub@var{m}@var{n}4}, but zero-extend the multiplication
3707 operands instead of sign-extending them.
3709 @cindex @code{divmod@var{m}4} instruction pattern
3710 @item @samp{divmod@var{m}4}
3711 Signed division that produces both a quotient and a remainder.
3712 Operand 1 is divided by operand 2 to produce a quotient stored
3713 in operand 0 and a remainder stored in operand 3.
3715 For machines with an instruction that produces both a quotient and a
3716 remainder, provide a pattern for @samp{divmod@var{m}4} but do not
3717 provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This
3718 allows optimization in the relatively common case when both the quotient
3719 and remainder are computed.
3721 If an instruction that just produces a quotient or just a remainder
3722 exists and is more efficient than the instruction that produces both,
3723 write the output routine of @samp{divmod@var{m}4} to call
3724 @code{find_reg_note} and look for a @code{REG_UNUSED} note on the
3725 quotient or remainder and generate the appropriate instruction.
3727 @cindex @code{udivmod@var{m}4} instruction pattern
3728 @item @samp{udivmod@var{m}4}
3729 Similar, but does unsigned division.
3731 @anchor{shift patterns}
3732 @cindex @code{ashl@var{m}3} instruction pattern
3733 @item @samp{ashl@var{m}3}
3734 Arithmetic-shift operand 1 left by a number of bits specified by operand
3735 2, and store the result in operand 0. Here @var{m} is the mode of
3736 operand 0 and operand 1; operand 2's mode is specified by the
3737 instruction pattern, and the compiler will convert the operand to that
3738 mode before generating the instruction. The meaning of out-of-range shift
3739 counts can optionally be specified by @code{TARGET_SHIFT_TRUNCATION_MASK}.
3740 @xref{TARGET_SHIFT_TRUNCATION_MASK}.
3742 @cindex @code{ashr@var{m}3} instruction pattern
3743 @cindex @code{lshr@var{m}3} instruction pattern
3744 @cindex @code{rotl@var{m}3} instruction pattern
3745 @cindex @code{rotr@var{m}3} instruction pattern
3746 @item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3}
3747 Other shift and rotate instructions, analogous to the
3748 @code{ashl@var{m}3} instructions.
3750 @cindex @code{neg@var{m}2} instruction pattern
3751 @item @samp{neg@var{m}2}
3752 Negate operand 1 and store the result in operand 0.
3754 @cindex @code{abs@var{m}2} instruction pattern
3755 @item @samp{abs@var{m}2}
3756 Store the absolute value of operand 1 into operand 0.
3758 @cindex @code{sqrt@var{m}2} instruction pattern
3759 @item @samp{sqrt@var{m}2}
3760 Store the square root of operand 1 into operand 0.
3762 The @code{sqrt} built-in function of C always uses the mode which
3763 corresponds to the C data type @code{double} and the @code{sqrtf}
3764 built-in function uses the mode which corresponds to the C data
3767 @cindex @code{fmod@var{m}3} instruction pattern
3768 @item @samp{fmod@var{m}3}
3769 Store the remainder of dividing operand 1 by operand 2 into
3770 operand 0, rounded towards zero to an integer.
3772 The @code{fmod} built-in function of C always uses the mode which
3773 corresponds to the C data type @code{double} and the @code{fmodf}
3774 built-in function uses the mode which corresponds to the C data
3777 @cindex @code{remainder@var{m}3} instruction pattern
3778 @item @samp{remainder@var{m}3}
3779 Store the remainder of dividing operand 1 by operand 2 into
3780 operand 0, rounded to the nearest integer.
3782 The @code{remainder} built-in function of C always uses the mode
3783 which corresponds to the C data type @code{double} and the
3784 @code{remainderf} built-in function uses the mode which corresponds
3785 to the C data type @code{float}.
3787 @cindex @code{cos@var{m}2} instruction pattern
3788 @item @samp{cos@var{m}2}
3789 Store the cosine of operand 1 into operand 0.
3791 The @code{cos} built-in function of C always uses the mode which
3792 corresponds to the C data type @code{double} and the @code{cosf}
3793 built-in function uses the mode which corresponds to the C data
3796 @cindex @code{sin@var{m}2} instruction pattern
3797 @item @samp{sin@var{m}2}
3798 Store the sine of operand 1 into operand 0.
3800 The @code{sin} built-in function of C always uses the mode which
3801 corresponds to the C data type @code{double} and the @code{sinf}
3802 built-in function uses the mode which corresponds to the C data
3805 @cindex @code{exp@var{m}2} instruction pattern
3806 @item @samp{exp@var{m}2}
3807 Store the exponential of operand 1 into operand 0.
3809 The @code{exp} built-in function of C always uses the mode which
3810 corresponds to the C data type @code{double} and the @code{expf}
3811 built-in function uses the mode which corresponds to the C data
3814 @cindex @code{log@var{m}2} instruction pattern
3815 @item @samp{log@var{m}2}
3816 Store the natural logarithm of operand 1 into operand 0.
3818 The @code{log} built-in function of C always uses the mode which
3819 corresponds to the C data type @code{double} and the @code{logf}
3820 built-in function uses the mode which corresponds to the C data
3823 @cindex @code{pow@var{m}3} instruction pattern
3824 @item @samp{pow@var{m}3}
3825 Store the value of operand 1 raised to the exponent operand 2
3828 The @code{pow} built-in function of C always uses the mode which
3829 corresponds to the C data type @code{double} and the @code{powf}
3830 built-in function uses the mode which corresponds to the C data
3833 @cindex @code{atan2@var{m}3} instruction pattern
3834 @item @samp{atan2@var{m}3}
3835 Store the arc tangent (inverse tangent) of operand 1 divided by
3836 operand 2 into operand 0, using the signs of both arguments to
3837 determine the quadrant of the result.
3839 The @code{atan2} built-in function of C always uses the mode which
3840 corresponds to the C data type @code{double} and the @code{atan2f}
3841 built-in function uses the mode which corresponds to the C data
3844 @cindex @code{floor@var{m}2} instruction pattern
3845 @item @samp{floor@var{m}2}
3846 Store the largest integral value not greater than argument.
3848 The @code{floor} built-in function of C always uses the mode which
3849 corresponds to the C data type @code{double} and the @code{floorf}
3850 built-in function uses the mode which corresponds to the C data
3853 @cindex @code{btrunc@var{m}2} instruction pattern
3854 @item @samp{btrunc@var{m}2}
3855 Store the argument rounded to integer towards zero.
3857 The @code{trunc} built-in function of C always uses the mode which
3858 corresponds to the C data type @code{double} and the @code{truncf}
3859 built-in function uses the mode which corresponds to the C data
3862 @cindex @code{round@var{m}2} instruction pattern
3863 @item @samp{round@var{m}2}
3864 Store the argument rounded to integer away from zero.
3866 The @code{round} built-in function of C always uses the mode which
3867 corresponds to the C data type @code{double} and the @code{roundf}
3868 built-in function uses the mode which corresponds to the C data
3871 @cindex @code{ceil@var{m}2} instruction pattern
3872 @item @samp{ceil@var{m}2}
3873 Store the argument rounded to integer away from zero.
3875 The @code{ceil} built-in function of C always uses the mode which
3876 corresponds to the C data type @code{double} and the @code{ceilf}
3877 built-in function uses the mode which corresponds to the C data
3880 @cindex @code{nearbyint@var{m}2} instruction pattern
3881 @item @samp{nearbyint@var{m}2}
3882 Store the argument rounded according to the default rounding mode
3884 The @code{nearbyint} built-in function of C always uses the mode which
3885 corresponds to the C data type @code{double} and the @code{nearbyintf}
3886 built-in function uses the mode which corresponds to the C data
3889 @cindex @code{rint@var{m}2} instruction pattern
3890 @item @samp{rint@var{m}2}
3891 Store the argument rounded according to the default rounding mode and
3892 raise the inexact exception when the result differs in value from
3895 The @code{rint} built-in function of C always uses the mode which
3896 corresponds to the C data type @code{double} and the @code{rintf}
3897 built-in function uses the mode which corresponds to the C data
3900 @cindex @code{lrint@var{m}@var{n}2}
3901 @item @samp{lrint@var{m}@var{n}2}
3902 Convert operand 1 (valid for floating point mode @var{m}) to fixed
3903 point mode @var{n} as a signed number according to the current
3904 rounding mode and store in operand 0 (which has mode @var{n}).
3906 @cindex @code{lround@var{m}@var{n}2}
3907 @item @samp{lround@var{m}2}
3908 Convert operand 1 (valid for floating point mode @var{m}) to fixed
3909 point mode @var{n} as a signed number rounding to nearest and away
3910 from zero and store in operand 0 (which has mode @var{n}).
3912 @cindex @code{lfloor@var{m}@var{n}2}
3913 @item @samp{lfloor@var{m}2}
3914 Convert operand 1 (valid for floating point mode @var{m}) to fixed
3915 point mode @var{n} as a signed number rounding down and store in
3916 operand 0 (which has mode @var{n}).
3918 @cindex @code{lceil@var{m}@var{n}2}
3919 @item @samp{lceil@var{m}2}
3920 Convert operand 1 (valid for floating point mode @var{m}) to fixed
3921 point mode @var{n} as a signed number rounding up and store in
3922 operand 0 (which has mode @var{n}).
3924 @cindex @code{copysign@var{m}3} instruction pattern
3925 @item @samp{copysign@var{m}3}
3926 Store a value with the magnitude of operand 1 and the sign of operand
3929 The @code{copysign} built-in function of C always uses the mode which
3930 corresponds to the C data type @code{double} and the @code{copysignf}
3931 built-in function uses the mode which corresponds to the C data
3934 @cindex @code{ffs@var{m}2} instruction pattern
3935 @item @samp{ffs@var{m}2}
3936 Store into operand 0 one plus the index of the least significant 1-bit
3937 of operand 1. If operand 1 is zero, store zero. @var{m} is the mode
3938 of operand 0; operand 1's mode is specified by the instruction
3939 pattern, and the compiler will convert the operand to that mode before
3940 generating the instruction.
3942 The @code{ffs} built-in function of C always uses the mode which
3943 corresponds to the C data type @code{int}.
3945 @cindex @code{clz@var{m}2} instruction pattern
3946 @item @samp{clz@var{m}2}
3947 Store into operand 0 the number of leading 0-bits in @var{x}, starting
3948 at the most significant bit position. If @var{x} is 0, the result is
3949 undefined. @var{m} is the mode of operand 0; operand 1's mode is
3950 specified by the instruction pattern, and the compiler will convert the
3951 operand to that mode before generating the instruction.
3953 @cindex @code{ctz@var{m}2} instruction pattern
3954 @item @samp{ctz@var{m}2}
3955 Store into operand 0 the number of trailing 0-bits in @var{x}, starting
3956 at the least significant bit position. If @var{x} is 0, the result is
3957 undefined. @var{m} is the mode of operand 0; operand 1's mode is
3958 specified by the instruction pattern, and the compiler will convert the
3959 operand to that mode before generating the instruction.
3961 @cindex @code{popcount@var{m}2} instruction pattern
3962 @item @samp{popcount@var{m}2}
3963 Store into operand 0 the number of 1-bits in @var{x}. @var{m} is the
3964 mode of operand 0; operand 1's mode is specified by the instruction
3965 pattern, and the compiler will convert the operand to that mode before
3966 generating the instruction.
3968 @cindex @code{parity@var{m}2} instruction pattern
3969 @item @samp{parity@var{m}2}
3970 Store into operand 0 the parity of @var{x}, i.e.@: the number of 1-bits
3971 in @var{x} modulo 2. @var{m} is the mode of operand 0; operand 1's mode
3972 is specified by the instruction pattern, and the compiler will convert
3973 the operand to that mode before generating the instruction.
3975 @cindex @code{one_cmpl@var{m}2} instruction pattern
3976 @item @samp{one_cmpl@var{m}2}
3977 Store the bitwise-complement of operand 1 into operand 0.
3979 @cindex @code{cmp@var{m}} instruction pattern
3980 @item @samp{cmp@var{m}}
3981 Compare operand 0 and operand 1, and set the condition codes.
3982 The RTL pattern should look like this:
3985 (set (cc0) (compare (match_operand:@var{m} 0 @dots{})
3986 (match_operand:@var{m} 1 @dots{})))
3989 @cindex @code{tst@var{m}} instruction pattern
3990 @item @samp{tst@var{m}}
3991 Compare operand 0 against zero, and set the condition codes.
3992 The RTL pattern should look like this:
3995 (set (cc0) (match_operand:@var{m} 0 @dots{}))
3998 @samp{tst@var{m}} patterns should not be defined for machines that do
3999 not use @code{(cc0)}. Doing so would confuse the optimizer since it
4000 would no longer be clear which @code{set} operations were comparisons.
4001 The @samp{cmp@var{m}} patterns should be used instead.
4003 @cindex @code{movmem@var{m}} instruction pattern
4004 @item @samp{movmem@var{m}}
4005 Block move instruction. The destination and source blocks of memory
4006 are the first two operands, and both are @code{mem:BLK}s with an
4007 address in mode @code{Pmode}.
4009 The number of bytes to move is the third operand, in mode @var{m}.
4010 Usually, you specify @code{word_mode} for @var{m}. However, if you can
4011 generate better code knowing the range of valid lengths is smaller than
4012 those representable in a full word, you should provide a pattern with a
4013 mode corresponding to the range of values you can handle efficiently
4014 (e.g., @code{QImode} for values in the range 0--127; note we avoid numbers
4015 that appear negative) and also a pattern with @code{word_mode}.
4017 The fourth operand is the known shared alignment of the source and
4018 destination, in the form of a @code{const_int} rtx. Thus, if the
4019 compiler knows that both source and destination are word-aligned,
4020 it may provide the value 4 for this operand.
4022 Optional operands 5 and 6 specify expected alignment and size of block
4023 respectively. The expected alignment differs from alignment in operand 4
4024 in a way that the blocks are not required to be aligned according to it in
4025 all cases. Expected size, when unknown, is set to @code{(const_int -1)}.
4027 Descriptions of multiple @code{movmem@var{m}} patterns can only be
4028 beneficial if the patterns for smaller modes have fewer restrictions
4029 on their first, second and fourth operands. Note that the mode @var{m}
4030 in @code{movmem@var{m}} does not impose any restriction on the mode of
4031 individually moved data units in the block.
4033 These patterns need not give special consideration to the possibility
4034 that the source and destination strings might overlap.
4036 @cindex @code{movstr} instruction pattern
4038 String copy instruction, with @code{stpcpy} semantics. Operand 0 is
4039 an output operand in mode @code{Pmode}. The addresses of the
4040 destination and source strings are operands 1 and 2, and both are
4041 @code{mem:BLK}s with addresses in mode @code{Pmode}. The execution of
4042 the expansion of this pattern should store in operand 0 the address in
4043 which the @code{NUL} terminator was stored in the destination string.
4045 @cindex @code{setmem@var{m}} instruction pattern
4046 @item @samp{setmem@var{m}}
4047 Block set instruction. The destination string is the first operand,
4048 given as a @code{mem:BLK} whose address is in mode @code{Pmode}. The
4049 number of bytes to set is the second operand, in mode @var{m}. The value to
4050 initialize the memory with is the third operand. Targets that only support the
4051 clearing of memory should reject any value that is not the constant 0. See
4052 @samp{movmem@var{m}} for a discussion of the choice of mode.
4054 The fourth operand is the known alignment of the destination, in the form
4055 of a @code{const_int} rtx. Thus, if the compiler knows that the
4056 destination is word-aligned, it may provide the value 4 for this
4059 Optional operands 5 and 6 specify expected alignment and size of block
4060 respectively. The expected alignment differs from alignment in operand 4
4061 in a way that the blocks are not required to be aligned according to it in
4062 all cases. Expected size, when unknown, is set to @code{(const_int -1)}.
4064 The use for multiple @code{setmem@var{m}} is as for @code{movmem@var{m}}.
4066 @cindex @code{cmpstrn@var{m}} instruction pattern
4067 @item @samp{cmpstrn@var{m}}
4068 String compare instruction, with five operands. Operand 0 is the output;
4069 it has mode @var{m}. The remaining four operands are like the operands
4070 of @samp{movmem@var{m}}. The two memory blocks specified are compared
4071 byte by byte in lexicographic order starting at the beginning of each
4072 string. The instruction is not allowed to prefetch more than one byte
4073 at a time since either string may end in the first byte and reading past
4074 that may access an invalid page or segment and cause a fault. The
4075 effect of the instruction is to store a value in operand 0 whose sign
4076 indicates the result of the comparison.
4078 @cindex @code{cmpstr@var{m}} instruction pattern
4079 @item @samp{cmpstr@var{m}}
4080 String compare instruction, without known maximum length. Operand 0 is the
4081 output; it has mode @var{m}. The second and third operand are the blocks of
4082 memory to be compared; both are @code{mem:BLK} with an address in mode
4085 The fourth operand is the known shared alignment of the source and
4086 destination, in the form of a @code{const_int} rtx. Thus, if the
4087 compiler knows that both source and destination are word-aligned,
4088 it may provide the value 4 for this operand.
4090 The two memory blocks specified are compared byte by byte in lexicographic
4091 order starting at the beginning of each string. The instruction is not allowed
4092 to prefetch more than one byte at a time since either string may end in the
4093 first byte and reading past that may access an invalid page or segment and
4094 cause a fault. The effect of the instruction is to store a value in operand 0
4095 whose sign indicates the result of the comparison.
4097 @cindex @code{cmpmem@var{m}} instruction pattern
4098 @item @samp{cmpmem@var{m}}
4099 Block compare instruction, with five operands like the operands
4100 of @samp{cmpstr@var{m}}. The two memory blocks specified are compared
4101 byte by byte in lexicographic order starting at the beginning of each
4102 block. Unlike @samp{cmpstr@var{m}} the instruction can prefetch
4103 any bytes in the two memory blocks. The effect of the instruction is
4104 to store a value in operand 0 whose sign indicates the result of the
4107 @cindex @code{strlen@var{m}} instruction pattern
4108 @item @samp{strlen@var{m}}
4109 Compute the length of a string, with three operands.
4110 Operand 0 is the result (of mode @var{m}), operand 1 is
4111 a @code{mem} referring to the first character of the string,
4112 operand 2 is the character to search for (normally zero),
4113 and operand 3 is a constant describing the known alignment
4114 of the beginning of the string.
4116 @cindex @code{float@var{mn}2} instruction pattern
4117 @item @samp{float@var{m}@var{n}2}
4118 Convert signed integer operand 1 (valid for fixed point mode @var{m}) to
4119 floating point mode @var{n} and store in operand 0 (which has mode
4122 @cindex @code{floatuns@var{mn}2} instruction pattern
4123 @item @samp{floatuns@var{m}@var{n}2}
4124 Convert unsigned integer operand 1 (valid for fixed point mode @var{m})
4125 to floating point mode @var{n} and store in operand 0 (which has mode
4128 @cindex @code{fix@var{mn}2} instruction pattern
4129 @item @samp{fix@var{m}@var{n}2}
4130 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4131 point mode @var{n} as a signed number and store in operand 0 (which
4132 has mode @var{n}). This instruction's result is defined only when
4133 the value of operand 1 is an integer.
4135 If the machine description defines this pattern, it also needs to
4136 define the @code{ftrunc} pattern.
4138 @cindex @code{fixuns@var{mn}2} instruction pattern
4139 @item @samp{fixuns@var{m}@var{n}2}
4140 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4141 point mode @var{n} as an unsigned number and store in operand 0 (which
4142 has mode @var{n}). This instruction's result is defined only when the
4143 value of operand 1 is an integer.
4145 @cindex @code{ftrunc@var{m}2} instruction pattern
4146 @item @samp{ftrunc@var{m}2}
4147 Convert operand 1 (valid for floating point mode @var{m}) to an
4148 integer value, still represented in floating point mode @var{m}, and
4149 store it in operand 0 (valid for floating point mode @var{m}).
4151 @cindex @code{fix_trunc@var{mn}2} instruction pattern
4152 @item @samp{fix_trunc@var{m}@var{n}2}
4153 Like @samp{fix@var{m}@var{n}2} but works for any floating point value
4154 of mode @var{m} by converting the value to an integer.
4156 @cindex @code{fixuns_trunc@var{mn}2} instruction pattern
4157 @item @samp{fixuns_trunc@var{m}@var{n}2}
4158 Like @samp{fixuns@var{m}@var{n}2} but works for any floating point
4159 value of mode @var{m} by converting the value to an integer.
4161 @cindex @code{trunc@var{mn}2} instruction pattern
4162 @item @samp{trunc@var{m}@var{n}2}
4163 Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and
4164 store in operand 0 (which has mode @var{n}). Both modes must be fixed
4165 point or both floating point.
4167 @cindex @code{extend@var{mn}2} instruction pattern
4168 @item @samp{extend@var{m}@var{n}2}
4169 Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
4170 store in operand 0 (which has mode @var{n}). Both modes must be fixed
4171 point or both floating point.
4173 @cindex @code{zero_extend@var{mn}2} instruction pattern
4174 @item @samp{zero_extend@var{m}@var{n}2}
4175 Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
4176 store in operand 0 (which has mode @var{n}). Both modes must be fixed
4179 @cindex @code{extv} instruction pattern
4181 Extract a bit-field from operand 1 (a register or memory operand), where
4182 operand 2 specifies the width in bits and operand 3 the starting bit,
4183 and store it in operand 0. Operand 0 must have mode @code{word_mode}.
4184 Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often
4185 @code{word_mode} is allowed only for registers. Operands 2 and 3 must
4186 be valid for @code{word_mode}.
4188 The RTL generation pass generates this instruction only with constants
4189 for operands 2 and 3 and the constant is never zero for operand 2.
4191 The bit-field value is sign-extended to a full word integer
4192 before it is stored in operand 0.
4194 @cindex @code{extzv} instruction pattern
4196 Like @samp{extv} except that the bit-field value is zero-extended.
4198 @cindex @code{insv} instruction pattern
4200 Store operand 3 (which must be valid for @code{word_mode}) into a
4201 bit-field in operand 0, where operand 1 specifies the width in bits and
4202 operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or
4203 @code{word_mode}; often @code{word_mode} is allowed only for registers.
4204 Operands 1 and 2 must be valid for @code{word_mode}.
4206 The RTL generation pass generates this instruction only with constants
4207 for operands 1 and 2 and the constant is never zero for operand 1.
4209 @cindex @code{mov@var{mode}cc} instruction pattern
4210 @item @samp{mov@var{mode}cc}
4211 Conditionally move operand 2 or operand 3 into operand 0 according to the
4212 comparison in operand 1. If the comparison is true, operand 2 is moved
4213 into operand 0, otherwise operand 3 is moved.
4215 The mode of the operands being compared need not be the same as the operands
4216 being moved. Some machines, sparc64 for example, have instructions that
4217 conditionally move an integer value based on the floating point condition
4218 codes and vice versa.
4220 If the machine does not have conditional move instructions, do not
4221 define these patterns.
4223 @cindex @code{add@var{mode}cc} instruction pattern
4224 @item @samp{add@var{mode}cc}
4225 Similar to @samp{mov@var{mode}cc} but for conditional addition. Conditionally
4226 move operand 2 or (operands 2 + operand 3) into operand 0 according to the
4227 comparison in operand 1. If the comparison is true, operand 2 is moved into
4228 operand 0, otherwise (operand 2 + operand 3) is moved.
4230 @cindex @code{s@var{cond}} instruction pattern
4231 @item @samp{s@var{cond}}
4232 Store zero or nonzero in the operand according to the condition codes.
4233 Value stored is nonzero iff the condition @var{cond} is true.
4234 @var{cond} is the name of a comparison operation expression code, such
4235 as @code{eq}, @code{lt} or @code{leu}.
4237 You specify the mode that the operand must have when you write the
4238 @code{match_operand} expression. The compiler automatically sees
4239 which mode you have used and supplies an operand of that mode.
4241 The value stored for a true condition must have 1 as its low bit, or
4242 else must be negative. Otherwise the instruction is not suitable and
4243 you should omit it from the machine description. You describe to the
4244 compiler exactly which value is stored by defining the macro
4245 @code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be
4246 found that can be used for all the @samp{s@var{cond}} patterns, you
4247 should omit those operations from the machine description.
4249 These operations may fail, but should do so only in relatively
4250 uncommon cases; if they would fail for common cases involving
4251 integer comparisons, it is best to omit these patterns.
4253 If these operations are omitted, the compiler will usually generate code
4254 that copies the constant one to the target and branches around an
4255 assignment of zero to the target. If this code is more efficient than
4256 the potential instructions used for the @samp{s@var{cond}} pattern
4257 followed by those required to convert the result into a 1 or a zero in
4258 @code{SImode}, you should omit the @samp{s@var{cond}} operations from
4259 the machine description.
4261 @cindex @code{b@var{cond}} instruction pattern
4262 @item @samp{b@var{cond}}
4263 Conditional branch instruction. Operand 0 is a @code{label_ref} that
4264 refers to the label to jump to. Jump if the condition codes meet
4265 condition @var{cond}.
4267 Some machines do not follow the model assumed here where a comparison
4268 instruction is followed by a conditional branch instruction. In that
4269 case, the @samp{cmp@var{m}} (and @samp{tst@var{m}}) patterns should
4270 simply store the operands away and generate all the required insns in a
4271 @code{define_expand} (@pxref{Expander Definitions}) for the conditional
4272 branch operations. All calls to expand @samp{b@var{cond}} patterns are
4273 immediately preceded by calls to expand either a @samp{cmp@var{m}}
4274 pattern or a @samp{tst@var{m}} pattern.
4276 Machines that use a pseudo register for the condition code value, or
4277 where the mode used for the comparison depends on the condition being
4278 tested, should also use the above mechanism. @xref{Jump Patterns}.
4280 The above discussion also applies to the @samp{mov@var{mode}cc} and
4281 @samp{s@var{cond}} patterns.
4283 @cindex @code{cbranch@var{mode}4} instruction pattern
4284 @item @samp{cbranch@var{mode}4}
4285 Conditional branch instruction combined with a compare instruction.
4286 Operand 0 is a comparison operator. Operand 1 and operand 2 are the
4287 first and second operands of the comparison, respectively. Operand 3
4288 is a @code{label_ref} that refers to the label to jump to.
4290 @cindex @code{jump} instruction pattern
4292 A jump inside a function; an unconditional branch. Operand 0 is the
4293 @code{label_ref} of the label to jump to. This pattern name is mandatory
4296 @cindex @code{call} instruction pattern
4298 Subroutine call instruction returning no value. Operand 0 is the
4299 function to call; operand 1 is the number of bytes of arguments pushed
4300 as a @code{const_int}; operand 2 is the number of registers used as
4303 On most machines, operand 2 is not actually stored into the RTL
4304 pattern. It is supplied for the sake of some RISC machines which need
4305 to put this information into the assembler code; they can put it in
4306 the RTL instead of operand 1.
4308 Operand 0 should be a @code{mem} RTX whose address is the address of the
4309 function. Note, however, that this address can be a @code{symbol_ref}
4310 expression even if it would not be a legitimate memory address on the
4311 target machine. If it is also not a valid argument for a call
4312 instruction, the pattern for this operation should be a
4313 @code{define_expand} (@pxref{Expander Definitions}) that places the
4314 address into a register and uses that register in the call instruction.
4316 @cindex @code{call_value} instruction pattern
4317 @item @samp{call_value}
4318 Subroutine call instruction returning a value. Operand 0 is the hard
4319 register in which the value is returned. There are three more
4320 operands, the same as the three operands of the @samp{call}
4321 instruction (but with numbers increased by one).
4323 Subroutines that return @code{BLKmode} objects use the @samp{call}
4326 @cindex @code{call_pop} instruction pattern
4327 @cindex @code{call_value_pop} instruction pattern
4328 @item @samp{call_pop}, @samp{call_value_pop}
4329 Similar to @samp{call} and @samp{call_value}, except used if defined and
4330 if @code{RETURN_POPS_ARGS} is nonzero. They should emit a @code{parallel}
4331 that contains both the function call and a @code{set} to indicate the
4332 adjustment made to the frame pointer.
4334 For machines where @code{RETURN_POPS_ARGS} can be nonzero, the use of these
4335 patterns increases the number of functions for which the frame pointer
4336 can be eliminated, if desired.
4338 @cindex @code{untyped_call} instruction pattern
4339 @item @samp{untyped_call}
4340 Subroutine call instruction returning a value of any type. Operand 0 is
4341 the function to call; operand 1 is a memory location where the result of
4342 calling the function is to be stored; operand 2 is a @code{parallel}
4343 expression where each element is a @code{set} expression that indicates
4344 the saving of a function return value into the result block.
4346 This instruction pattern should be defined to support
4347 @code{__builtin_apply} on machines where special instructions are needed
4348 to call a subroutine with arbitrary arguments or to save the value
4349 returned. This instruction pattern is required on machines that have
4350 multiple registers that can hold a return value
4351 (i.e.@: @code{FUNCTION_VALUE_REGNO_P} is true for more than one register).
4353 @cindex @code{return} instruction pattern
4355 Subroutine return instruction. This instruction pattern name should be
4356 defined only if a single instruction can do all the work of returning
4359 Like the @samp{mov@var{m}} patterns, this pattern is also used after the
4360 RTL generation phase. In this case it is to support machines where
4361 multiple instructions are usually needed to return from a function, but
4362 some class of functions only requires one instruction to implement a
4363 return. Normally, the applicable functions are those which do not need
4364 to save any registers or allocate stack space.
4366 @findex reload_completed
4367 @findex leaf_function_p
4368 For such machines, the condition specified in this pattern should only
4369 be true when @code{reload_completed} is nonzero and the function's
4370 epilogue would only be a single instruction. For machines with register
4371 windows, the routine @code{leaf_function_p} may be used to determine if
4372 a register window push is required.
4374 Machines that have conditional return instructions should define patterns
4380 (if_then_else (match_operator
4381 0 "comparison_operator"
4382 [(cc0) (const_int 0)])
4389 where @var{condition} would normally be the same condition specified on the
4390 named @samp{return} pattern.
4392 @cindex @code{untyped_return} instruction pattern
4393 @item @samp{untyped_return}
4394 Untyped subroutine return instruction. This instruction pattern should
4395 be defined to support @code{__builtin_return} on machines where special
4396 instructions are needed to return a value of any type.
4398 Operand 0 is a memory location where the result of calling a function
4399 with @code{__builtin_apply} is stored; operand 1 is a @code{parallel}
4400 expression where each element is a @code{set} expression that indicates
4401 the restoring of a function return value from the result block.
4403 @cindex @code{nop} instruction pattern
4405 No-op instruction. This instruction pattern name should always be defined
4406 to output a no-op in assembler code. @code{(const_int 0)} will do as an
4409 @cindex @code{indirect_jump} instruction pattern
4410 @item @samp{indirect_jump}
4411 An instruction to jump to an address which is operand zero.
4412 This pattern name is mandatory on all machines.
4414 @cindex @code{casesi} instruction pattern
4416 Instruction to jump through a dispatch table, including bounds checking.
4417 This instruction takes five operands:
4421 The index to dispatch on, which has mode @code{SImode}.
4424 The lower bound for indices in the table, an integer constant.
4427 The total range of indices in the table---the largest index
4428 minus the smallest one (both inclusive).
4431 A label that precedes the table itself.
4434 A label to jump to if the index has a value outside the bounds.
4437 The table is a @code{addr_vec} or @code{addr_diff_vec} inside of a
4438 @code{jump_insn}. The number of elements in the table is one plus the
4439 difference between the upper bound and the lower bound.
4441 @cindex @code{tablejump} instruction pattern
4442 @item @samp{tablejump}
4443 Instruction to jump to a variable address. This is a low-level
4444 capability which can be used to implement a dispatch table when there
4445 is no @samp{casesi} pattern.
4447 This pattern requires two operands: the address or offset, and a label
4448 which should immediately precede the jump table. If the macro
4449 @code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first
4450 operand is an offset which counts from the address of the table; otherwise,
4451 it is an absolute address to jump to. In either case, the first operand has
4454 The @samp{tablejump} insn is always the last insn before the jump
4455 table it uses. Its assembler code normally has no need to use the
4456 second operand, but you should incorporate it in the RTL pattern so
4457 that the jump optimizer will not delete the table as unreachable code.
4460 @cindex @code{decrement_and_branch_until_zero} instruction pattern
4461 @item @samp{decrement_and_branch_until_zero}
4462 Conditional branch instruction that decrements a register and
4463 jumps if the register is nonzero. Operand 0 is the register to
4464 decrement and test; operand 1 is the label to jump to if the
4465 register is nonzero. @xref{Looping Patterns}.
4467 This optional instruction pattern is only used by the combiner,
4468 typically for loops reversed by the loop optimizer when strength
4469 reduction is enabled.
4471 @cindex @code{doloop_end} instruction pattern
4472 @item @samp{doloop_end}
4473 Conditional branch instruction that decrements a register and jumps if
4474 the register is nonzero. This instruction takes five operands: Operand
4475 0 is the register to decrement and test; operand 1 is the number of loop
4476 iterations as a @code{const_int} or @code{const0_rtx} if this cannot be
4477 determined until run-time; operand 2 is the actual or estimated maximum
4478 number of iterations as a @code{const_int}; operand 3 is the number of
4479 enclosed loops as a @code{const_int} (an innermost loop has a value of
4480 1); operand 4 is the label to jump to if the register is nonzero.
4481 @xref{Looping Patterns}.
4483 This optional instruction pattern should be defined for machines with
4484 low-overhead looping instructions as the loop optimizer will try to
4485 modify suitable loops to utilize it. If nested low-overhead looping is
4486 not supported, use a @code{define_expand} (@pxref{Expander Definitions})
4487 and make the pattern fail if operand 3 is not @code{const1_rtx}.
4488 Similarly, if the actual or estimated maximum number of iterations is
4489 too large for this instruction, make it fail.
4491 @cindex @code{doloop_begin} instruction pattern
4492 @item @samp{doloop_begin}
4493 Companion instruction to @code{doloop_end} required for machines that
4494 need to perform some initialization, such as loading special registers
4495 used by a low-overhead looping instruction. If initialization insns do
4496 not always need to be emitted, use a @code{define_expand}
4497 (@pxref{Expander Definitions}) and make it fail.
4500 @cindex @code{canonicalize_funcptr_for_compare} instruction pattern
4501 @item @samp{canonicalize_funcptr_for_compare}
4502 Canonicalize the function pointer in operand 1 and store the result
4505 Operand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1
4506 may be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc
4507 and also has mode @code{Pmode}.
4509 Canonicalization of a function pointer usually involves computing
4510 the address of the function which would be called if the function
4511 pointer were used in an indirect call.
4513 Only define this pattern if function pointers on the target machine
4514 can have different values but still call the same function when
4515 used in an indirect call.
4517 @cindex @code{save_stack_block} instruction pattern
4518 @cindex @code{save_stack_function} instruction pattern
4519 @cindex @code{save_stack_nonlocal} instruction pattern
4520 @cindex @code{restore_stack_block} instruction pattern
4521 @cindex @code{restore_stack_function} instruction pattern
4522 @cindex @code{restore_stack_nonlocal} instruction pattern
4523 @item @samp{save_stack_block}
4524 @itemx @samp{save_stack_function}
4525 @itemx @samp{save_stack_nonlocal}
4526 @itemx @samp{restore_stack_block}
4527 @itemx @samp{restore_stack_function}
4528 @itemx @samp{restore_stack_nonlocal}
4529 Most machines save and restore the stack pointer by copying it to or
4530 from an object of mode @code{Pmode}. Do not define these patterns on
4533 Some machines require special handling for stack pointer saves and
4534 restores. On those machines, define the patterns corresponding to the
4535 non-standard cases by using a @code{define_expand} (@pxref{Expander
4536 Definitions}) that produces the required insns. The three types of
4537 saves and restores are:
4541 @samp{save_stack_block} saves the stack pointer at the start of a block
4542 that allocates a variable-sized object, and @samp{restore_stack_block}
4543 restores the stack pointer when the block is exited.
4546 @samp{save_stack_function} and @samp{restore_stack_function} do a
4547 similar job for the outermost block of a function and are used when the
4548 function allocates variable-sized objects or calls @code{alloca}. Only
4549 the epilogue uses the restored stack pointer, allowing a simpler save or
4550 restore sequence on some machines.
4553 @samp{save_stack_nonlocal} is used in functions that contain labels
4554 branched to by nested functions. It saves the stack pointer in such a
4555 way that the inner function can use @samp{restore_stack_nonlocal} to
4556 restore the stack pointer. The compiler generates code to restore the
4557 frame and argument pointer registers, but some machines require saving
4558 and restoring additional data such as register window information or
4559 stack backchains. Place insns in these patterns to save and restore any
4563 When saving the stack pointer, operand 0 is the save area and operand 1
4564 is the stack pointer. The mode used to allocate the save area defaults
4565 to @code{Pmode} but you can override that choice by defining the
4566 @code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must
4567 specify an integral mode, or @code{VOIDmode} if no save area is needed
4568 for a particular type of save (either because no save is needed or
4569 because a machine-specific save area can be used). Operand 0 is the
4570 stack pointer and operand 1 is the save area for restore operations. If
4571 @samp{save_stack_block} is defined, operand 0 must not be
4572 @code{VOIDmode} since these saves can be arbitrarily nested.
4574 A save area is a @code{mem} that is at a constant offset from
4575 @code{virtual_stack_vars_rtx} when the stack pointer is saved for use by
4576 nonlocal gotos and a @code{reg} in the other two cases.
4578 @cindex @code{allocate_stack} instruction pattern
4579 @item @samp{allocate_stack}
4580 Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from
4581 the stack pointer to create space for dynamically allocated data.
4583 Store the resultant pointer to this space into operand 0. If you
4584 are allocating space from the main stack, do this by emitting a
4585 move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0.
4586 If you are allocating the space elsewhere, generate code to copy the
4587 location of the space to operand 0. In the latter case, you must
4588 ensure this space gets freed when the corresponding space on the main
4591 Do not define this pattern if all that must be done is the subtraction.
4592 Some machines require other operations such as stack probes or
4593 maintaining the back chain. Define this pattern to emit those
4594 operations in addition to updating the stack pointer.
4596 @cindex @code{check_stack} instruction pattern
4597 @item @samp{check_stack}
4598 If stack checking cannot be done on your system by probing the stack with
4599 a load or store instruction (@pxref{Stack Checking}), define this pattern
4600 to perform the needed check and signaling an error if the stack
4601 has overflowed. The single operand is the location in the stack furthest
4602 from the current stack pointer that you need to validate. Normally,
4603 on machines where this pattern is needed, you would obtain the stack
4604 limit from a global or thread-specific variable or register.
4606 @cindex @code{nonlocal_goto} instruction pattern
4607 @item @samp{nonlocal_goto}
4608 Emit code to generate a non-local goto, e.g., a jump from one function
4609 to a label in an outer function. This pattern has four arguments,
4610 each representing a value to be used in the jump. The first
4611 argument is to be loaded into the frame pointer, the second is
4612 the address to branch to (code to dispatch to the actual label),
4613 the third is the address of a location where the stack is saved,
4614 and the last is the address of the label, to be placed in the
4615 location for the incoming static chain.
4617 On most machines you need not define this pattern, since GCC will
4618 already generate the correct code, which is to load the frame pointer
4619 and static chain, restore the stack (using the
4620 @samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly
4621 to the dispatcher. You need only define this pattern if this code will
4622 not work on your machine.
4624 @cindex @code{nonlocal_goto_receiver} instruction pattern
4625 @item @samp{nonlocal_goto_receiver}
4626 This pattern, if defined, contains code needed at the target of a
4627 nonlocal goto after the code already generated by GCC@. You will not
4628 normally need to define this pattern. A typical reason why you might
4629 need this pattern is if some value, such as a pointer to a global table,
4630 must be restored when the frame pointer is restored. Note that a nonlocal
4631 goto only occurs within a unit-of-translation, so a global table pointer
4632 that is shared by all functions of a given module need not be restored.
4633 There are no arguments.
4635 @cindex @code{exception_receiver} instruction pattern
4636 @item @samp{exception_receiver}
4637 This pattern, if defined, contains code needed at the site of an
4638 exception handler that isn't needed at the site of a nonlocal goto. You
4639 will not normally need to define this pattern. A typical reason why you
4640 might need this pattern is if some value, such as a pointer to a global
4641 table, must be restored after control flow is branched to the handler of
4642 an exception. There are no arguments.
4644 @cindex @code{builtin_setjmp_setup} instruction pattern
4645 @item @samp{builtin_setjmp_setup}
4646 This pattern, if defined, contains additional code needed to initialize
4647 the @code{jmp_buf}. You will not normally need to define this pattern.
4648 A typical reason why you might need this pattern is if some value, such
4649 as a pointer to a global table, must be restored. Though it is
4650 preferred that the pointer value be recalculated if possible (given the
4651 address of a label for instance). The single argument is a pointer to
4652 the @code{jmp_buf}. Note that the buffer is five words long and that
4653 the first three are normally used by the generic mechanism.
4655 @cindex @code{builtin_setjmp_receiver} instruction pattern
4656 @item @samp{builtin_setjmp_receiver}
4657 This pattern, if defined, contains code needed at the site of an
4658 built-in setjmp that isn't needed at the site of a nonlocal goto. You
4659 will not normally need to define this pattern. A typical reason why you
4660 might need this pattern is if some value, such as a pointer to a global
4661 table, must be restored. It takes one argument, which is the label
4662 to which builtin_longjmp transfered control; this pattern may be emitted
4663 at a small offset from that label.
4665 @cindex @code{builtin_longjmp} instruction pattern
4666 @item @samp{builtin_longjmp}
4667 This pattern, if defined, performs the entire action of the longjmp.
4668 You will not normally need to define this pattern unless you also define
4669 @code{builtin_setjmp_setup}. The single argument is a pointer to the
4672 @cindex @code{eh_return} instruction pattern
4673 @item @samp{eh_return}
4674 This pattern, if defined, affects the way @code{__builtin_eh_return},
4675 and thence the call frame exception handling library routines, are
4676 built. It is intended to handle non-trivial actions needed along
4677 the abnormal return path.
4679 The address of the exception handler to which the function should return
4680 is passed as operand to this pattern. It will normally need to copied by
4681 the pattern to some special register or memory location.
4682 If the pattern needs to determine the location of the target call
4683 frame in order to do so, it may use @code{EH_RETURN_STACKADJ_RTX},
4684 if defined; it will have already been assigned.
4686 If this pattern is not defined, the default action will be to simply
4687 copy the return address to @code{EH_RETURN_HANDLER_RTX}. Either
4688 that macro or this pattern needs to be defined if call frame exception
4689 handling is to be used.
4691 @cindex @code{prologue} instruction pattern
4692 @anchor{prologue instruction pattern}
4693 @item @samp{prologue}
4694 This pattern, if defined, emits RTL for entry to a function. The function
4695 entry is responsible for setting up the stack frame, initializing the frame
4696 pointer register, saving callee saved registers, etc.
4698 Using a prologue pattern is generally preferred over defining
4699 @code{TARGET_ASM_FUNCTION_PROLOGUE} to emit assembly code for the prologue.
4701 The @code{prologue} pattern is particularly useful for targets which perform
4702 instruction scheduling.
4704 @cindex @code{epilogue} instruction pattern
4705 @anchor{epilogue instruction pattern}
4706 @item @samp{epilogue}
4707 This pattern emits RTL for exit from a function. The function
4708 exit is responsible for deallocating the stack frame, restoring callee saved
4709 registers and emitting the return instruction.
4711 Using an epilogue pattern is generally preferred over defining
4712 @code{TARGET_ASM_FUNCTION_EPILOGUE} to emit assembly code for the epilogue.
4714 The @code{epilogue} pattern is particularly useful for targets which perform
4715 instruction scheduling or which have delay slots for their return instruction.
4717 @cindex @code{sibcall_epilogue} instruction pattern
4718 @item @samp{sibcall_epilogue}
4719 This pattern, if defined, emits RTL for exit from a function without the final
4720 branch back to the calling function. This pattern will be emitted before any
4721 sibling call (aka tail call) sites.
4723 The @code{sibcall_epilogue} pattern must not clobber any arguments used for
4724 parameter passing or any stack slots for arguments passed to the current
4727 @cindex @code{trap} instruction pattern
4729 This pattern, if defined, signals an error, typically by causing some
4730 kind of signal to be raised. Among other places, it is used by the Java
4731 front end to signal `invalid array index' exceptions.
4733 @cindex @code{conditional_trap} instruction pattern
4734 @item @samp{conditional_trap}
4735 Conditional trap instruction. Operand 0 is a piece of RTL which
4736 performs a comparison. Operand 1 is the trap code, an integer.
4738 A typical @code{conditional_trap} pattern looks like
4741 (define_insn "conditional_trap"
4742 [(trap_if (match_operator 0 "trap_operator"
4743 [(cc0) (const_int 0)])
4744 (match_operand 1 "const_int_operand" "i"))]
4749 @cindex @code{prefetch} instruction pattern
4750 @item @samp{prefetch}
4752 This pattern, if defined, emits code for a non-faulting data prefetch
4753 instruction. Operand 0 is the address of the memory to prefetch. Operand 1
4754 is a constant 1 if the prefetch is preparing for a write to the memory
4755 address, or a constant 0 otherwise. Operand 2 is the expected degree of
4756 temporal locality of the data and is a value between 0 and 3, inclusive; 0
4757 means that the data has no temporal locality, so it need not be left in the
4758 cache after the access; 3 means that the data has a high degree of temporal
4759 locality and should be left in all levels of cache possible; 1 and 2 mean,
4760 respectively, a low or moderate degree of temporal locality.
4762 Targets that do not support write prefetches or locality hints can ignore
4763 the values of operands 1 and 2.
4765 @cindex @code{blockage} instruction pattern
4766 @item @samp{blockage}
4768 This pattern defines a pseudo insn that prevents the instruction
4769 scheduler from moving instructions across the boundary defined by the
4770 blockage insn. Normally an UNSPEC_VOLATILE pattern.
4772 @cindex @code{memory_barrier} instruction pattern
4773 @item @samp{memory_barrier}
4775 If the target memory model is not fully synchronous, then this pattern
4776 should be defined to an instruction that orders both loads and stores
4777 before the instruction with respect to loads and stores after the instruction.
4778 This pattern has no operands.
4780 @cindex @code{sync_compare_and_swap@var{mode}} instruction pattern
4781 @item @samp{sync_compare_and_swap@var{mode}}
4783 This pattern, if defined, emits code for an atomic compare-and-swap
4784 operation. Operand 1 is the memory on which the atomic operation is
4785 performed. Operand 2 is the ``old'' value to be compared against the
4786 current contents of the memory location. Operand 3 is the ``new'' value
4787 to store in the memory if the compare succeeds. Operand 0 is the result
4788 of the operation; it should contain the contents of the memory
4789 before the operation. If the compare succeeds, this should obviously be
4790 a copy of operand 2.
4792 This pattern must show that both operand 0 and operand 1 are modified.
4794 This pattern must issue any memory barrier instructions such that all
4795 memory operations before the atomic operation occur before the atomic
4796 operation and all memory operations after the atomic operation occur
4797 after the atomic operation.
4799 @cindex @code{sync_compare_and_swap_cc@var{mode}} instruction pattern
4800 @item @samp{sync_compare_and_swap_cc@var{mode}}
4802 This pattern is just like @code{sync_compare_and_swap@var{mode}}, except
4803 it should act as if compare part of the compare-and-swap were issued via
4804 @code{cmp@var{m}}. This comparison will only be used with @code{EQ} and
4805 @code{NE} branches and @code{setcc} operations.
4807 Some targets do expose the success or failure of the compare-and-swap
4808 operation via the status flags. Ideally we wouldn't need a separate
4809 named pattern in order to take advantage of this, but the combine pass
4810 does not handle patterns with multiple sets, which is required by
4811 definition for @code{sync_compare_and_swap@var{mode}}.
4813 @cindex @code{sync_add@var{mode}} instruction pattern
4814 @cindex @code{sync_sub@var{mode}} instruction pattern
4815 @cindex @code{sync_ior@var{mode}} instruction pattern
4816 @cindex @code{sync_and@var{mode}} instruction pattern
4817 @cindex @code{sync_xor@var{mode}} instruction pattern
4818 @cindex @code{sync_nand@var{mode}} instruction pattern
4819 @item @samp{sync_add@var{mode}}, @samp{sync_sub@var{mode}}
4820 @itemx @samp{sync_ior@var{mode}}, @samp{sync_and@var{mode}}
4821 @itemx @samp{sync_xor@var{mode}}, @samp{sync_nand@var{mode}}
4823 These patterns emit code for an atomic operation on memory.
4824 Operand 0 is the memory on which the atomic operation is performed.
4825 Operand 1 is the second operand to the binary operator.
4827 The ``nand'' operation is @code{~op0 & op1}.
4829 This pattern must issue any memory barrier instructions such that all
4830 memory operations before the atomic operation occur before the atomic
4831 operation and all memory operations after the atomic operation occur
4832 after the atomic operation.
4834 If these patterns are not defined, the operation will be constructed
4835 from a compare-and-swap operation, if defined.
4837 @cindex @code{sync_old_add@var{mode}} instruction pattern
4838 @cindex @code{sync_old_sub@var{mode}} instruction pattern
4839 @cindex @code{sync_old_ior@var{mode}} instruction pattern
4840 @cindex @code{sync_old_and@var{mode}} instruction pattern
4841 @cindex @code{sync_old_xor@var{mode}} instruction pattern
4842 @cindex @code{sync_old_nand@var{mode}} instruction pattern
4843 @item @samp{sync_old_add@var{mode}}, @samp{sync_old_sub@var{mode}}
4844 @itemx @samp{sync_old_ior@var{mode}}, @samp{sync_old_and@var{mode}}
4845 @itemx @samp{sync_old_xor@var{mode}}, @samp{sync_old_nand@var{mode}}
4847 These patterns are emit code for an atomic operation on memory,
4848 and return the value that the memory contained before the operation.
4849 Operand 0 is the result value, operand 1 is the memory on which the
4850 atomic operation is performed, and operand 2 is the second operand
4851 to the binary operator.
4853 This pattern must issue any memory barrier instructions such that all
4854 memory operations before the atomic operation occur before the atomic
4855 operation and all memory operations after the atomic operation occur
4856 after the atomic operation.
4858 If these patterns are not defined, the operation will be constructed
4859 from a compare-and-swap operation, if defined.
4861 @cindex @code{sync_new_add@var{mode}} instruction pattern
4862 @cindex @code{sync_new_sub@var{mode}} instruction pattern
4863 @cindex @code{sync_new_ior@var{mode}} instruction pattern
4864 @cindex @code{sync_new_and@var{mode}} instruction pattern
4865 @cindex @code{sync_new_xor@var{mode}} instruction pattern
4866 @cindex @code{sync_new_nand@var{mode}} instruction pattern
4867 @item @samp{sync_new_add@var{mode}}, @samp{sync_new_sub@var{mode}}
4868 @itemx @samp{sync_new_ior@var{mode}}, @samp{sync_new_and@var{mode}}
4869 @itemx @samp{sync_new_xor@var{mode}}, @samp{sync_new_nand@var{mode}}
4871 These patterns are like their @code{sync_old_@var{op}} counterparts,
4872 except that they return the value that exists in the memory location
4873 after the operation, rather than before the operation.
4875 @cindex @code{sync_lock_test_and_set@var{mode}} instruction pattern
4876 @item @samp{sync_lock_test_and_set@var{mode}}
4878 This pattern takes two forms, based on the capabilities of the target.
4879 In either case, operand 0 is the result of the operand, operand 1 is
4880 the memory on which the atomic operation is performed, and operand 2
4881 is the value to set in the lock.
4883 In the ideal case, this operation is an atomic exchange operation, in
4884 which the previous value in memory operand is copied into the result
4885 operand, and the value operand is stored in the memory operand.
4887 For less capable targets, any value operand that is not the constant 1
4888 should be rejected with @code{FAIL}. In this case the target may use
4889 an atomic test-and-set bit operation. The result operand should contain
4890 1 if the bit was previously set and 0 if the bit was previously clear.
4891 The true contents of the memory operand are implementation defined.
4893 This pattern must issue any memory barrier instructions such that the
4894 pattern as a whole acts as an acquire barrier, that is all memory
4895 operations after the pattern do not occur until the lock is acquired.
4897 If this pattern is not defined, the operation will be constructed from
4898 a compare-and-swap operation, if defined.
4900 @cindex @code{sync_lock_release@var{mode}} instruction pattern
4901 @item @samp{sync_lock_release@var{mode}}
4903 This pattern, if defined, releases a lock set by
4904 @code{sync_lock_test_and_set@var{mode}}. Operand 0 is the memory
4905 that contains the lock; operand 1 is the value to store in the lock.
4907 If the target doesn't implement full semantics for
4908 @code{sync_lock_test_and_set@var{mode}}, any value operand which is not
4909 the constant 0 should be rejected with @code{FAIL}, and the true contents
4910 of the memory operand are implementation defined.
4912 This pattern must issue any memory barrier instructions such that the
4913 pattern as a whole acts as a release barrier, that is the lock is
4914 released only after all previous memory operations have completed.
4916 If this pattern is not defined, then a @code{memory_barrier} pattern
4917 will be emitted, followed by a store of the value to the memory operand.
4919 @cindex @code{stack_protect_set} instruction pattern
4920 @item @samp{stack_protect_set}
4922 This pattern, if defined, moves a @code{Pmode} value from the memory
4923 in operand 1 to the memory in operand 0 without leaving the value in
4924 a register afterward. This is to avoid leaking the value some place
4925 that an attacker might use to rewrite the stack guard slot after
4926 having clobbered it.
4928 If this pattern is not defined, then a plain move pattern is generated.
4930 @cindex @code{stack_protect_test} instruction pattern
4931 @item @samp{stack_protect_test}
4933 This pattern, if defined, compares a @code{Pmode} value from the
4934 memory in operand 1 with the memory in operand 0 without leaving the
4935 value in a register afterward and branches to operand 2 if the values
4938 If this pattern is not defined, then a plain compare pattern and
4939 conditional branch pattern is used.
4944 @c Each of the following nodes are wrapped in separate
4945 @c "@ifset INTERNALS" to work around memory limits for the default
4946 @c configuration in older tetex distributions. Known to not work:
4947 @c tetex-1.0.7, known to work: tetex-2.0.2.
4949 @node Pattern Ordering
4950 @section When the Order of Patterns Matters
4951 @cindex Pattern Ordering
4952 @cindex Ordering of Patterns
4954 Sometimes an insn can match more than one instruction pattern. Then the
4955 pattern that appears first in the machine description is the one used.
4956 Therefore, more specific patterns (patterns that will match fewer things)
4957 and faster instructions (those that will produce better code when they
4958 do match) should usually go first in the description.
4960 In some cases the effect of ordering the patterns can be used to hide
4961 a pattern when it is not valid. For example, the 68000 has an
4962 instruction for converting a fullword to floating point and another
4963 for converting a byte to floating point. An instruction converting
4964 an integer to floating point could match either one. We put the
4965 pattern to convert the fullword first to make sure that one will
4966 be used rather than the other. (Otherwise a large integer might
4967 be generated as a single-byte immediate quantity, which would not work.)
4968 Instead of using this pattern ordering it would be possible to make the
4969 pattern for convert-a-byte smart enough to deal properly with any
4974 @node Dependent Patterns
4975 @section Interdependence of Patterns
4976 @cindex Dependent Patterns
4977 @cindex Interdependence of Patterns
4979 Every machine description must have a named pattern for each of the
4980 conditional branch names @samp{b@var{cond}}. The recognition template
4981 must always have the form
4985 (if_then_else (@var{cond} (cc0) (const_int 0))
4986 (label_ref (match_operand 0 "" ""))
4991 In addition, every machine description must have an anonymous pattern
4992 for each of the possible reverse-conditional branches. Their templates
4997 (if_then_else (@var{cond} (cc0) (const_int 0))
4999 (label_ref (match_operand 0 "" ""))))
5003 They are necessary because jump optimization can turn direct-conditional
5004 branches into reverse-conditional branches.
5006 It is often convenient to use the @code{match_operator} construct to
5007 reduce the number of patterns that must be specified for branches. For
5013 (if_then_else (match_operator 0 "comparison_operator"
5014 [(cc0) (const_int 0)])
5016 (label_ref (match_operand 1 "" ""))))]
5021 In some cases machines support instructions identical except for the
5022 machine mode of one or more operands. For example, there may be
5023 ``sign-extend halfword'' and ``sign-extend byte'' instructions whose
5027 (set (match_operand:SI 0 @dots{})
5028 (extend:SI (match_operand:HI 1 @dots{})))
5030 (set (match_operand:SI 0 @dots{})
5031 (extend:SI (match_operand:QI 1 @dots{})))
5035 Constant integers do not specify a machine mode, so an instruction to
5036 extend a constant value could match either pattern. The pattern it
5037 actually will match is the one that appears first in the file. For correct
5038 results, this must be the one for the widest possible mode (@code{HImode},
5039 here). If the pattern matches the @code{QImode} instruction, the results
5040 will be incorrect if the constant value does not actually fit that mode.
5042 Such instructions to extend constants are rarely generated because they are
5043 optimized away, but they do occasionally happen in nonoptimized
5046 If a constraint in a pattern allows a constant, the reload pass may
5047 replace a register with a constant permitted by the constraint in some
5048 cases. Similarly for memory references. Because of this substitution,
5049 you should not provide separate patterns for increment and decrement
5050 instructions. Instead, they should be generated from the same pattern
5051 that supports register-register add insns by examining the operands and
5052 generating the appropriate machine instruction.
5057 @section Defining Jump Instruction Patterns
5058 @cindex jump instruction patterns
5059 @cindex defining jump instruction patterns
5061 For most machines, GCC assumes that the machine has a condition code.
5062 A comparison insn sets the condition code, recording the results of both
5063 signed and unsigned comparison of the given operands. A separate branch
5064 insn tests the condition code and branches or not according its value.
5065 The branch insns come in distinct signed and unsigned flavors. Many
5066 common machines, such as the VAX, the 68000 and the 32000, work this
5069 Some machines have distinct signed and unsigned compare instructions, and
5070 only one set of conditional branch instructions. The easiest way to handle
5071 these machines is to treat them just like the others until the final stage
5072 where assembly code is written. At this time, when outputting code for the
5073 compare instruction, peek ahead at the following branch using
5074 @code{next_cc0_user (insn)}. (The variable @code{insn} refers to the insn
5075 being output, in the output-writing code in an instruction pattern.) If
5076 the RTL says that is an unsigned branch, output an unsigned compare;
5077 otherwise output a signed compare. When the branch itself is output, you
5078 can treat signed and unsigned branches identically.
5080 The reason you can do this is that GCC always generates a pair of
5081 consecutive RTL insns, possibly separated by @code{note} insns, one to
5082 set the condition code and one to test it, and keeps the pair inviolate
5085 To go with this technique, you must define the machine-description macro
5086 @code{NOTICE_UPDATE_CC} to do @code{CC_STATUS_INIT}; in other words, no
5087 compare instruction is superfluous.
5089 Some machines have compare-and-branch instructions and no condition code.
5090 A similar technique works for them. When it is time to ``output'' a
5091 compare instruction, record its operands in two static variables. When
5092 outputting the branch-on-condition-code instruction that follows, actually
5093 output a compare-and-branch instruction that uses the remembered operands.
5095 It also works to define patterns for compare-and-branch instructions.
5096 In optimizing compilation, the pair of compare and branch instructions
5097 will be combined according to these patterns. But this does not happen
5098 if optimization is not requested. So you must use one of the solutions
5099 above in addition to any special patterns you define.
5101 In many RISC machines, most instructions do not affect the condition
5102 code and there may not even be a separate condition code register. On
5103 these machines, the restriction that the definition and use of the
5104 condition code be adjacent insns is not necessary and can prevent
5105 important optimizations. For example, on the IBM RS/6000, there is a
5106 delay for taken branches unless the condition code register is set three
5107 instructions earlier than the conditional branch. The instruction
5108 scheduler cannot perform this optimization if it is not permitted to
5109 separate the definition and use of the condition code register.
5111 On these machines, do not use @code{(cc0)}, but instead use a register
5112 to represent the condition code. If there is a specific condition code
5113 register in the machine, use a hard register. If the condition code or
5114 comparison result can be placed in any general register, or if there are
5115 multiple condition registers, use a pseudo register.
5117 @findex prev_cc0_setter
5118 @findex next_cc0_user
5119 On some machines, the type of branch instruction generated may depend on
5120 the way the condition code was produced; for example, on the 68k and
5121 SPARC, setting the condition code directly from an add or subtract
5122 instruction does not clear the overflow bit the way that a test
5123 instruction does, so a different branch instruction must be used for
5124 some conditional branches. For machines that use @code{(cc0)}, the set
5125 and use of the condition code must be adjacent (separated only by
5126 @code{note} insns) allowing flags in @code{cc_status} to be used.
5127 (@xref{Condition Code}.) Also, the comparison and branch insns can be
5128 located from each other by using the functions @code{prev_cc0_setter}
5129 and @code{next_cc0_user}.
5131 However, this is not true on machines that do not use @code{(cc0)}. On
5132 those machines, no assumptions can be made about the adjacency of the
5133 compare and branch insns and the above methods cannot be used. Instead,
5134 we use the machine mode of the condition code register to record
5135 different formats of the condition code register.
5137 Registers used to store the condition code value should have a mode that
5138 is in class @code{MODE_CC}. Normally, it will be @code{CCmode}. If
5139 additional modes are required (as for the add example mentioned above in
5140 the SPARC), define them in @file{@var{machine}-modes.def}
5141 (@pxref{Condition Code}). Also define @code{SELECT_CC_MODE} to choose
5142 a mode given an operand of a compare.
5144 If it is known during RTL generation that a different mode will be
5145 required (for example, if the machine has separate compare instructions
5146 for signed and unsigned quantities, like most IBM processors), they can
5147 be specified at that time.
5149 If the cases that require different modes would be made by instruction
5150 combination, the macro @code{SELECT_CC_MODE} determines which machine
5151 mode should be used for the comparison result. The patterns should be
5152 written using that mode. To support the case of the add on the SPARC
5153 discussed above, we have the pattern
5157 [(set (reg:CC_NOOV 0)
5159 (plus:SI (match_operand:SI 0 "register_operand" "%r")
5160 (match_operand:SI 1 "arith_operand" "rI"))
5166 The @code{SELECT_CC_MODE} macro on the SPARC returns @code{CC_NOOVmode}
5167 for comparisons whose argument is a @code{plus}.
5171 @node Looping Patterns
5172 @section Defining Looping Instruction Patterns
5173 @cindex looping instruction patterns
5174 @cindex defining looping instruction patterns
5176 Some machines have special jump instructions that can be utilized to
5177 make loops more efficient. A common example is the 68000 @samp{dbra}
5178 instruction which performs a decrement of a register and a branch if the
5179 result was greater than zero. Other machines, in particular digital
5180 signal processors (DSPs), have special block repeat instructions to
5181 provide low-overhead loop support. For example, the TI TMS320C3x/C4x
5182 DSPs have a block repeat instruction that loads special registers to
5183 mark the top and end of a loop and to count the number of loop
5184 iterations. This avoids the need for fetching and executing a
5185 @samp{dbra}-like instruction and avoids pipeline stalls associated with
5188 GCC has three special named patterns to support low overhead looping.
5189 They are @samp{decrement_and_branch_until_zero}, @samp{doloop_begin},
5190 and @samp{doloop_end}. The first pattern,
5191 @samp{decrement_and_branch_until_zero}, is not emitted during RTL
5192 generation but may be emitted during the instruction combination phase.
5193 This requires the assistance of the loop optimizer, using information
5194 collected during strength reduction, to reverse a loop to count down to
5195 zero. Some targets also require the loop optimizer to add a
5196 @code{REG_NONNEG} note to indicate that the iteration count is always
5197 positive. This is needed if the target performs a signed loop
5198 termination test. For example, the 68000 uses a pattern similar to the
5199 following for its @code{dbra} instruction:
5203 (define_insn "decrement_and_branch_until_zero"
5206 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
5209 (label_ref (match_operand 1 "" ""))
5212 (plus:SI (match_dup 0)
5214 "find_reg_note (insn, REG_NONNEG, 0)"
5219 Note that since the insn is both a jump insn and has an output, it must
5220 deal with its own reloads, hence the `m' constraints. Also note that
5221 since this insn is generated by the instruction combination phase
5222 combining two sequential insns together into an implicit parallel insn,
5223 the iteration counter needs to be biased by the same amount as the
5224 decrement operation, in this case @minus{}1. Note that the following similar
5225 pattern will not be matched by the combiner.
5229 (define_insn "decrement_and_branch_until_zero"
5232 (ge (match_operand:SI 0 "general_operand" "+d*am")
5234 (label_ref (match_operand 1 "" ""))
5237 (plus:SI (match_dup 0)
5239 "find_reg_note (insn, REG_NONNEG, 0)"
5244 The other two special looping patterns, @samp{doloop_begin} and
5245 @samp{doloop_end}, are emitted by the loop optimizer for certain
5246 well-behaved loops with a finite number of loop iterations using
5247 information collected during strength reduction.
5249 The @samp{doloop_end} pattern describes the actual looping instruction
5250 (or the implicit looping operation) and the @samp{doloop_begin} pattern
5251 is an optional companion pattern that can be used for initialization
5252 needed for some low-overhead looping instructions.
5254 Note that some machines require the actual looping instruction to be
5255 emitted at the top of the loop (e.g., the TMS320C3x/C4x DSPs). Emitting
5256 the true RTL for a looping instruction at the top of the loop can cause
5257 problems with flow analysis. So instead, a dummy @code{doloop} insn is
5258 emitted at the end of the loop. The machine dependent reorg pass checks
5259 for the presence of this @code{doloop} insn and then searches back to
5260 the top of the loop, where it inserts the true looping insn (provided
5261 there are no instructions in the loop which would cause problems). Any
5262 additional labels can be emitted at this point. In addition, if the
5263 desired special iteration counter register was not allocated, this
5264 machine dependent reorg pass could emit a traditional compare and jump
5267 The essential difference between the
5268 @samp{decrement_and_branch_until_zero} and the @samp{doloop_end}
5269 patterns is that the loop optimizer allocates an additional pseudo
5270 register for the latter as an iteration counter. This pseudo register
5271 cannot be used within the loop (i.e., general induction variables cannot
5272 be derived from it), however, in many cases the loop induction variable
5273 may become redundant and removed by the flow pass.
5278 @node Insn Canonicalizations
5279 @section Canonicalization of Instructions
5280 @cindex canonicalization of instructions
5281 @cindex insn canonicalization
5283 There are often cases where multiple RTL expressions could represent an
5284 operation performed by a single machine instruction. This situation is
5285 most commonly encountered with logical, branch, and multiply-accumulate
5286 instructions. In such cases, the compiler attempts to convert these
5287 multiple RTL expressions into a single canonical form to reduce the
5288 number of insn patterns required.
5290 In addition to algebraic simplifications, following canonicalizations
5295 For commutative and comparison operators, a constant is always made the
5296 second operand. If a machine only supports a constant as the second
5297 operand, only patterns that match a constant in the second operand need
5301 For associative operators, a sequence of operators will always chain
5302 to the left; for instance, only the left operand of an integer @code{plus}
5303 can itself be a @code{plus}. @code{and}, @code{ior}, @code{xor},
5304 @code{plus}, @code{mult}, @code{smin}, @code{smax}, @code{umin}, and
5305 @code{umax} are associative when applied to integers, and sometimes to
5309 @cindex @code{neg}, canonicalization of
5310 @cindex @code{not}, canonicalization of
5311 @cindex @code{mult}, canonicalization of
5312 @cindex @code{plus}, canonicalization of
5313 @cindex @code{minus}, canonicalization of
5314 For these operators, if only one operand is a @code{neg}, @code{not},
5315 @code{mult}, @code{plus}, or @code{minus} expression, it will be the
5319 In combinations of @code{neg}, @code{mult}, @code{plus}, and
5320 @code{minus}, the @code{neg} operations (if any) will be moved inside
5321 the operations as far as possible. For instance,
5322 @code{(neg (mult A B))} is canonicalized as @code{(mult (neg A) B)}, but
5323 @code{(plus (mult (neg A) B) C)} is canonicalized as
5324 @code{(minus A (mult B C))}.
5326 @cindex @code{compare}, canonicalization of
5328 For the @code{compare} operator, a constant is always the second operand
5329 on machines where @code{cc0} is used (@pxref{Jump Patterns}). On other
5330 machines, there are rare cases where the compiler might want to construct
5331 a @code{compare} with a constant as the first operand. However, these
5332 cases are not common enough for it to be worthwhile to provide a pattern
5333 matching a constant as the first operand unless the machine actually has
5334 such an instruction.
5336 An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or
5337 @code{minus} is made the first operand under the same conditions as
5341 @code{(minus @var{x} (const_int @var{n}))} is converted to
5342 @code{(plus @var{x} (const_int @var{-n}))}.
5345 Within address computations (i.e., inside @code{mem}), a left shift is
5346 converted into the appropriate multiplication by a power of two.
5348 @cindex @code{ior}, canonicalization of
5349 @cindex @code{and}, canonicalization of
5350 @cindex De Morgan's law
5352 De Morgan's Law is used to move bitwise negation inside a bitwise
5353 logical-and or logical-or operation. If this results in only one
5354 operand being a @code{not} expression, it will be the first one.
5356 A machine that has an instruction that performs a bitwise logical-and of one
5357 operand with the bitwise negation of the other should specify the pattern
5358 for that instruction as
5362 [(set (match_operand:@var{m} 0 @dots{})
5363 (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
5364 (match_operand:@var{m} 2 @dots{})))]
5370 Similarly, a pattern for a ``NAND'' instruction should be written
5374 [(set (match_operand:@var{m} 0 @dots{})
5375 (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
5376 (not:@var{m} (match_operand:@var{m} 2 @dots{}))))]
5381 In both cases, it is not necessary to include patterns for the many
5382 logically equivalent RTL expressions.
5384 @cindex @code{xor}, canonicalization of
5386 The only possible RTL expressions involving both bitwise exclusive-or
5387 and bitwise negation are @code{(xor:@var{m} @var{x} @var{y})}
5388 and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}.
5391 The sum of three items, one of which is a constant, will only appear in
5395 (plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant})
5399 On machines that do not use @code{cc0},
5400 @code{(compare @var{x} (const_int 0))} will be converted to
5403 @cindex @code{zero_extract}, canonicalization of
5404 @cindex @code{sign_extract}, canonicalization of
5406 Equality comparisons of a group of bits (usually a single bit) with zero
5407 will be written using @code{zero_extract} rather than the equivalent
5408 @code{and} or @code{sign_extract} operations.
5412 Further canonicalization rules are defined in the function
5413 @code{commutative_operand_precedence} in @file{gcc/rtlanal.c}.
5417 @node Expander Definitions
5418 @section Defining RTL Sequences for Code Generation
5419 @cindex expander definitions
5420 @cindex code generation RTL sequences
5421 @cindex defining RTL sequences for code generation
5423 On some target machines, some standard pattern names for RTL generation
5424 cannot be handled with single insn, but a sequence of RTL insns can
5425 represent them. For these target machines, you can write a
5426 @code{define_expand} to specify how to generate the sequence of RTL@.
5428 @findex define_expand
5429 A @code{define_expand} is an RTL expression that looks almost like a
5430 @code{define_insn}; but, unlike the latter, a @code{define_expand} is used
5431 only for RTL generation and it can produce more than one RTL insn.
5433 A @code{define_expand} RTX has four operands:
5437 The name. Each @code{define_expand} must have a name, since the only
5438 use for it is to refer to it by name.
5441 The RTL template. This is a vector of RTL expressions representing
5442 a sequence of separate instructions. Unlike @code{define_insn}, there
5443 is no implicit surrounding @code{PARALLEL}.
5446 The condition, a string containing a C expression. This expression is
5447 used to express how the availability of this pattern depends on
5448 subclasses of target machine, selected by command-line options when GCC
5449 is run. This is just like the condition of a @code{define_insn} that
5450 has a standard name. Therefore, the condition (if present) may not
5451 depend on the data in the insn being matched, but only the
5452 target-machine-type flags. The compiler needs to test these conditions
5453 during initialization in order to learn exactly which named instructions
5454 are available in a particular run.
5457 The preparation statements, a string containing zero or more C
5458 statements which are to be executed before RTL code is generated from
5461 Usually these statements prepare temporary registers for use as
5462 internal operands in the RTL template, but they can also generate RTL
5463 insns directly by calling routines such as @code{emit_insn}, etc.
5464 Any such insns precede the ones that come from the RTL template.
5467 Every RTL insn emitted by a @code{define_expand} must match some
5468 @code{define_insn} in the machine description. Otherwise, the compiler
5469 will crash when trying to generate code for the insn or trying to optimize
5472 The RTL template, in addition to controlling generation of RTL insns,
5473 also describes the operands that need to be specified when this pattern
5474 is used. In particular, it gives a predicate for each operand.
5476 A true operand, which needs to be specified in order to generate RTL from
5477 the pattern, should be described with a @code{match_operand} in its first
5478 occurrence in the RTL template. This enters information on the operand's
5479 predicate into the tables that record such things. GCC uses the
5480 information to preload the operand into a register if that is required for
5481 valid RTL code. If the operand is referred to more than once, subsequent
5482 references should use @code{match_dup}.
5484 The RTL template may also refer to internal ``operands'' which are
5485 temporary registers or labels used only within the sequence made by the
5486 @code{define_expand}. Internal operands are substituted into the RTL
5487 template with @code{match_dup}, never with @code{match_operand}. The
5488 values of the internal operands are not passed in as arguments by the
5489 compiler when it requests use of this pattern. Instead, they are computed
5490 within the pattern, in the preparation statements. These statements
5491 compute the values and store them into the appropriate elements of
5492 @code{operands} so that @code{match_dup} can find them.
5494 There are two special macros defined for use in the preparation statements:
5495 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
5502 Use the @code{DONE} macro to end RTL generation for the pattern. The
5503 only RTL insns resulting from the pattern on this occasion will be
5504 those already emitted by explicit calls to @code{emit_insn} within the
5505 preparation statements; the RTL template will not be generated.
5509 Make the pattern fail on this occasion. When a pattern fails, it means
5510 that the pattern was not truly available. The calling routines in the
5511 compiler will try other strategies for code generation using other patterns.
5513 Failure is currently supported only for binary (addition, multiplication,
5514 shifting, etc.) and bit-field (@code{extv}, @code{extzv}, and @code{insv})
5518 If the preparation falls through (invokes neither @code{DONE} nor
5519 @code{FAIL}), then the @code{define_expand} acts like a
5520 @code{define_insn} in that the RTL template is used to generate the
5523 The RTL template is not used for matching, only for generating the
5524 initial insn list. If the preparation statement always invokes
5525 @code{DONE} or @code{FAIL}, the RTL template may be reduced to a simple
5526 list of operands, such as this example:
5530 (define_expand "addsi3"
5531 [(match_operand:SI 0 "register_operand" "")
5532 (match_operand:SI 1 "register_operand" "")
5533 (match_operand:SI 2 "register_operand" "")]
5539 handle_add (operands[0], operands[1], operands[2]);
5545 Here is an example, the definition of left-shift for the SPUR chip:
5549 (define_expand "ashlsi3"
5550 [(set (match_operand:SI 0 "register_operand" "")
5554 (match_operand:SI 1 "register_operand" "")
5555 (match_operand:SI 2 "nonmemory_operand" "")))]
5564 if (GET_CODE (operands[2]) != CONST_INT
5565 || (unsigned) INTVAL (operands[2]) > 3)
5572 This example uses @code{define_expand} so that it can generate an RTL insn
5573 for shifting when the shift-count is in the supported range of 0 to 3 but
5574 fail in other cases where machine insns aren't available. When it fails,
5575 the compiler tries another strategy using different patterns (such as, a
5578 If the compiler were able to handle nontrivial condition-strings in
5579 patterns with names, then it would be possible to use a
5580 @code{define_insn} in that case. Here is another case (zero-extension
5581 on the 68000) which makes more use of the power of @code{define_expand}:
5584 (define_expand "zero_extendhisi2"
5585 [(set (match_operand:SI 0 "general_operand" "")
5587 (set (strict_low_part
5591 (match_operand:HI 1 "general_operand" ""))]
5593 "operands[1] = make_safe_from (operands[1], operands[0]);")
5597 @findex make_safe_from
5598 Here two RTL insns are generated, one to clear the entire output operand
5599 and the other to copy the input operand into its low half. This sequence
5600 is incorrect if the input operand refers to [the old value of] the output
5601 operand, so the preparation statement makes sure this isn't so. The
5602 function @code{make_safe_from} copies the @code{operands[1]} into a
5603 temporary register if it refers to @code{operands[0]}. It does this
5604 by emitting another RTL insn.
5606 Finally, a third example shows the use of an internal operand.
5607 Zero-extension on the SPUR chip is done by @code{and}-ing the result
5608 against a halfword mask. But this mask cannot be represented by a
5609 @code{const_int} because the constant value is too large to be legitimate
5610 on this machine. So it must be copied into a register with
5611 @code{force_reg} and then the register used in the @code{and}.
5614 (define_expand "zero_extendhisi2"
5615 [(set (match_operand:SI 0 "register_operand" "")
5617 (match_operand:HI 1 "register_operand" "")
5622 = force_reg (SImode, GEN_INT (65535)); ")
5625 @emph{Note:} If the @code{define_expand} is used to serve a
5626 standard binary or unary arithmetic operation or a bit-field operation,
5627 then the last insn it generates must not be a @code{code_label},
5628 @code{barrier} or @code{note}. It must be an @code{insn},
5629 @code{jump_insn} or @code{call_insn}. If you don't need a real insn
5630 at the end, emit an insn to copy the result of the operation into
5631 itself. Such an insn will generate no code, but it can avoid problems
5636 @node Insn Splitting
5637 @section Defining How to Split Instructions
5638 @cindex insn splitting
5639 @cindex instruction splitting
5640 @cindex splitting instructions
5642 There are two cases where you should specify how to split a pattern
5643 into multiple insns. On machines that have instructions requiring
5644 delay slots (@pxref{Delay Slots}) or that have instructions whose
5645 output is not available for multiple cycles (@pxref{Processor pipeline
5646 description}), the compiler phases that optimize these cases need to
5647 be able to move insns into one-instruction delay slots. However, some
5648 insns may generate more than one machine instruction. These insns
5649 cannot be placed into a delay slot.
5651 Often you can rewrite the single insn as a list of individual insns,
5652 each corresponding to one machine instruction. The disadvantage of
5653 doing so is that it will cause the compilation to be slower and require
5654 more space. If the resulting insns are too complex, it may also
5655 suppress some optimizations. The compiler splits the insn if there is a
5656 reason to believe that it might improve instruction or delay slot
5659 The insn combiner phase also splits putative insns. If three insns are
5660 merged into one insn with a complex expression that cannot be matched by
5661 some @code{define_insn} pattern, the combiner phase attempts to split
5662 the complex pattern into two insns that are recognized. Usually it can
5663 break the complex pattern into two patterns by splitting out some
5664 subexpression. However, in some other cases, such as performing an
5665 addition of a large constant in two insns on a RISC machine, the way to
5666 split the addition into two insns is machine-dependent.
5668 @findex define_split
5669 The @code{define_split} definition tells the compiler how to split a
5670 complex insn into several simpler insns. It looks like this:
5674 [@var{insn-pattern}]
5676 [@var{new-insn-pattern-1}
5677 @var{new-insn-pattern-2}
5679 "@var{preparation-statements}")
5682 @var{insn-pattern} is a pattern that needs to be split and
5683 @var{condition} is the final condition to be tested, as in a
5684 @code{define_insn}. When an insn matching @var{insn-pattern} and
5685 satisfying @var{condition} is found, it is replaced in the insn list
5686 with the insns given by @var{new-insn-pattern-1},
5687 @var{new-insn-pattern-2}, etc.
5689 The @var{preparation-statements} are similar to those statements that
5690 are specified for @code{define_expand} (@pxref{Expander Definitions})
5691 and are executed before the new RTL is generated to prepare for the
5692 generated code or emit some insns whose pattern is not fixed. Unlike
5693 those in @code{define_expand}, however, these statements must not
5694 generate any new pseudo-registers. Once reload has completed, they also
5695 must not allocate any space in the stack frame.
5697 Patterns are matched against @var{insn-pattern} in two different
5698 circumstances. If an insn needs to be split for delay slot scheduling
5699 or insn scheduling, the insn is already known to be valid, which means
5700 that it must have been matched by some @code{define_insn} and, if
5701 @code{reload_completed} is nonzero, is known to satisfy the constraints
5702 of that @code{define_insn}. In that case, the new insn patterns must
5703 also be insns that are matched by some @code{define_insn} and, if
5704 @code{reload_completed} is nonzero, must also satisfy the constraints
5705 of those definitions.
5707 As an example of this usage of @code{define_split}, consider the following
5708 example from @file{a29k.md}, which splits a @code{sign_extend} from
5709 @code{HImode} to @code{SImode} into a pair of shift insns:
5713 [(set (match_operand:SI 0 "gen_reg_operand" "")
5714 (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
5717 (ashift:SI (match_dup 1)
5720 (ashiftrt:SI (match_dup 0)
5723 @{ operands[1] = gen_lowpart (SImode, operands[1]); @}")
5726 When the combiner phase tries to split an insn pattern, it is always the
5727 case that the pattern is @emph{not} matched by any @code{define_insn}.
5728 The combiner pass first tries to split a single @code{set} expression
5729 and then the same @code{set} expression inside a @code{parallel}, but
5730 followed by a @code{clobber} of a pseudo-reg to use as a scratch
5731 register. In these cases, the combiner expects exactly two new insn
5732 patterns to be generated. It will verify that these patterns match some
5733 @code{define_insn} definitions, so you need not do this test in the
5734 @code{define_split} (of course, there is no point in writing a
5735 @code{define_split} that will never produce insns that match).
5737 Here is an example of this use of @code{define_split}, taken from
5742 [(set (match_operand:SI 0 "gen_reg_operand" "")
5743 (plus:SI (match_operand:SI 1 "gen_reg_operand" "")
5744 (match_operand:SI 2 "non_add_cint_operand" "")))]
5746 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
5747 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
5750 int low = INTVAL (operands[2]) & 0xffff;
5751 int high = (unsigned) INTVAL (operands[2]) >> 16;
5754 high++, low |= 0xffff0000;
5756 operands[3] = GEN_INT (high << 16);
5757 operands[4] = GEN_INT (low);
5761 Here the predicate @code{non_add_cint_operand} matches any
5762 @code{const_int} that is @emph{not} a valid operand of a single add
5763 insn. The add with the smaller displacement is written so that it
5764 can be substituted into the address of a subsequent operation.
5766 An example that uses a scratch register, from the same file, generates
5767 an equality comparison of a register and a large constant:
5771 [(set (match_operand:CC 0 "cc_reg_operand" "")
5772 (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
5773 (match_operand:SI 2 "non_short_cint_operand" "")))
5774 (clobber (match_operand:SI 3 "gen_reg_operand" ""))]
5775 "find_single_use (operands[0], insn, 0)
5776 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
5777 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
5778 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
5779 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
5782 /* @r{Get the constant we are comparing against, C, and see what it
5783 looks like sign-extended to 16 bits. Then see what constant
5784 could be XOR'ed with C to get the sign-extended value.} */
5786 int c = INTVAL (operands[2]);
5787 int sextc = (c << 16) >> 16;
5788 int xorv = c ^ sextc;
5790 operands[4] = GEN_INT (xorv);
5791 operands[5] = GEN_INT (sextc);
5795 To avoid confusion, don't write a single @code{define_split} that
5796 accepts some insns that match some @code{define_insn} as well as some
5797 insns that don't. Instead, write two separate @code{define_split}
5798 definitions, one for the insns that are valid and one for the insns that
5801 The splitter is allowed to split jump instructions into sequence of
5802 jumps or create new jumps in while splitting non-jump instructions. As
5803 the central flowgraph and branch prediction information needs to be updated,
5804 several restriction apply.
5806 Splitting of jump instruction into sequence that over by another jump
5807 instruction is always valid, as compiler expect identical behavior of new
5808 jump. When new sequence contains multiple jump instructions or new labels,
5809 more assistance is needed. Splitter is required to create only unconditional
5810 jumps, or simple conditional jump instructions. Additionally it must attach a
5811 @code{REG_BR_PROB} note to each conditional jump. A global variable
5812 @code{split_branch_probability} holds the probability of the original branch in case
5813 it was an simple conditional jump, @minus{}1 otherwise. To simplify
5814 recomputing of edge frequencies, the new sequence is required to have only
5815 forward jumps to the newly created labels.
5817 @findex define_insn_and_split
5818 For the common case where the pattern of a define_split exactly matches the
5819 pattern of a define_insn, use @code{define_insn_and_split}. It looks like
5823 (define_insn_and_split
5824 [@var{insn-pattern}]
5826 "@var{output-template}"
5827 "@var{split-condition}"
5828 [@var{new-insn-pattern-1}
5829 @var{new-insn-pattern-2}
5831 "@var{preparation-statements}"
5832 [@var{insn-attributes}])
5836 @var{insn-pattern}, @var{condition}, @var{output-template}, and
5837 @var{insn-attributes} are used as in @code{define_insn}. The
5838 @var{new-insn-pattern} vector and the @var{preparation-statements} are used as
5839 in a @code{define_split}. The @var{split-condition} is also used as in
5840 @code{define_split}, with the additional behavior that if the condition starts
5841 with @samp{&&}, the condition used for the split will be the constructed as a
5842 logical ``and'' of the split condition with the insn condition. For example,
5846 (define_insn_and_split "zero_extendhisi2_and"
5847 [(set (match_operand:SI 0 "register_operand" "=r")
5848 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
5849 (clobber (reg:CC 17))]
5850 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
5852 "&& reload_completed"
5853 [(parallel [(set (match_dup 0)
5854 (and:SI (match_dup 0) (const_int 65535)))
5855 (clobber (reg:CC 17))])]
5857 [(set_attr "type" "alu1")])
5861 In this case, the actual split condition will be
5862 @samp{TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed}.
5864 The @code{define_insn_and_split} construction provides exactly the same
5865 functionality as two separate @code{define_insn} and @code{define_split}
5866 patterns. It exists for compactness, and as a maintenance tool to prevent
5867 having to ensure the two patterns' templates match.
5871 @node Including Patterns
5872 @section Including Patterns in Machine Descriptions.
5873 @cindex insn includes
5876 The @code{include} pattern tells the compiler tools where to
5877 look for patterns that are in files other than in the file
5878 @file{.md}. This is used only at build time and there is no preprocessing allowed.
5892 (include "filestuff")
5896 Where @var{pathname} is a string that specifies the location of the file,
5897 specifies the include file to be in @file{gcc/config/target/filestuff}. The
5898 directory @file{gcc/config/target} is regarded as the default directory.
5901 Machine descriptions may be split up into smaller more manageable subsections
5902 and placed into subdirectories.
5908 (include "BOGUS/filestuff")
5912 the include file is specified to be in @file{gcc/config/@var{target}/BOGUS/filestuff}.
5914 Specifying an absolute path for the include file such as;
5917 (include "/u2/BOGUS/filestuff")
5920 is permitted but is not encouraged.
5922 @subsection RTL Generation Tool Options for Directory Search
5923 @cindex directory options .md
5924 @cindex options, directory search
5925 @cindex search options
5927 The @option{-I@var{dir}} option specifies directories to search for machine descriptions.
5932 genrecog -I/p1/abc/proc1 -I/p2/abcd/pro2 target.md
5937 Add the directory @var{dir} to the head of the list of directories to be
5938 searched for header files. This can be used to override a system machine definition
5939 file, substituting your own version, since these directories are
5940 searched before the default machine description file directories. If you use more than
5941 one @option{-I} option, the directories are scanned in left-to-right
5942 order; the standard default directory come after.
5947 @node Peephole Definitions
5948 @section Machine-Specific Peephole Optimizers
5949 @cindex peephole optimizer definitions
5950 @cindex defining peephole optimizers
5952 In addition to instruction patterns the @file{md} file may contain
5953 definitions of machine-specific peephole optimizations.
5955 The combiner does not notice certain peephole optimizations when the data
5956 flow in the program does not suggest that it should try them. For example,
5957 sometimes two consecutive insns related in purpose can be combined even
5958 though the second one does not appear to use a register computed in the
5959 first one. A machine-specific peephole optimizer can detect such
5962 There are two forms of peephole definitions that may be used. The
5963 original @code{define_peephole} is run at assembly output time to
5964 match insns and substitute assembly text. Use of @code{define_peephole}
5967 A newer @code{define_peephole2} matches insns and substitutes new
5968 insns. The @code{peephole2} pass is run after register allocation
5969 but before scheduling, which may result in much better code for
5970 targets that do scheduling.
5973 * define_peephole:: RTL to Text Peephole Optimizers
5974 * define_peephole2:: RTL to RTL Peephole Optimizers
5979 @node define_peephole
5980 @subsection RTL to Text Peephole Optimizers
5981 @findex define_peephole
5984 A definition looks like this:
5988 [@var{insn-pattern-1}
5989 @var{insn-pattern-2}
5993 "@var{optional-insn-attributes}")
5997 The last string operand may be omitted if you are not using any
5998 machine-specific information in this machine description. If present,
5999 it must obey the same rules as in a @code{define_insn}.
6001 In this skeleton, @var{insn-pattern-1} and so on are patterns to match
6002 consecutive insns. The optimization applies to a sequence of insns when
6003 @var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches
6004 the next, and so on.
6006 Each of the insns matched by a peephole must also match a
6007 @code{define_insn}. Peepholes are checked only at the last stage just
6008 before code generation, and only optionally. Therefore, any insn which
6009 would match a peephole but no @code{define_insn} will cause a crash in code
6010 generation in an unoptimized compilation, or at various optimization
6013 The operands of the insns are matched with @code{match_operands},
6014 @code{match_operator}, and @code{match_dup}, as usual. What is not
6015 usual is that the operand numbers apply to all the insn patterns in the
6016 definition. So, you can check for identical operands in two insns by
6017 using @code{match_operand} in one insn and @code{match_dup} in the
6020 The operand constraints used in @code{match_operand} patterns do not have
6021 any direct effect on the applicability of the peephole, but they will
6022 be validated afterward, so make sure your constraints are general enough
6023 to apply whenever the peephole matches. If the peephole matches
6024 but the constraints are not satisfied, the compiler will crash.
6026 It is safe to omit constraints in all the operands of the peephole; or
6027 you can write constraints which serve as a double-check on the criteria
6030 Once a sequence of insns matches the patterns, the @var{condition} is
6031 checked. This is a C expression which makes the final decision whether to
6032 perform the optimization (we do so if the expression is nonzero). If
6033 @var{condition} is omitted (in other words, the string is empty) then the
6034 optimization is applied to every sequence of insns that matches the
6037 The defined peephole optimizations are applied after register allocation
6038 is complete. Therefore, the peephole definition can check which
6039 operands have ended up in which kinds of registers, just by looking at
6042 @findex prev_active_insn
6043 The way to refer to the operands in @var{condition} is to write
6044 @code{operands[@var{i}]} for operand number @var{i} (as matched by
6045 @code{(match_operand @var{i} @dots{})}). Use the variable @code{insn}
6046 to refer to the last of the insns being matched; use
6047 @code{prev_active_insn} to find the preceding insns.
6049 @findex dead_or_set_p
6050 When optimizing computations with intermediate results, you can use
6051 @var{condition} to match only when the intermediate results are not used
6052 elsewhere. Use the C expression @code{dead_or_set_p (@var{insn},
6053 @var{op})}, where @var{insn} is the insn in which you expect the value
6054 to be used for the last time (from the value of @code{insn}, together
6055 with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate
6056 value (from @code{operands[@var{i}]}).
6058 Applying the optimization means replacing the sequence of insns with one
6059 new insn. The @var{template} controls ultimate output of assembler code
6060 for this combined insn. It works exactly like the template of a
6061 @code{define_insn}. Operand numbers in this template are the same ones
6062 used in matching the original sequence of insns.
6064 The result of a defined peephole optimizer does not need to match any of
6065 the insn patterns in the machine description; it does not even have an
6066 opportunity to match them. The peephole optimizer definition itself serves
6067 as the insn pattern to control how the insn is output.
6069 Defined peephole optimizers are run as assembler code is being output,
6070 so the insns they produce are never combined or rearranged in any way.
6072 Here is an example, taken from the 68000 machine description:
6076 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
6077 (set (match_operand:DF 0 "register_operand" "=f")
6078 (match_operand:DF 1 "register_operand" "ad"))]
6079 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
6082 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
6084 output_asm_insn ("move.l %1,(sp)", xoperands);
6085 output_asm_insn ("move.l %1,-(sp)", operands);
6086 return "fmove.d (sp)+,%0";
6088 output_asm_insn ("movel %1,sp@@", xoperands);
6089 output_asm_insn ("movel %1,sp@@-", operands);
6090 return "fmoved sp@@+,%0";
6096 The effect of this optimization is to change
6122 If a peephole matches a sequence including one or more jump insns, you must
6123 take account of the flags such as @code{CC_REVERSED} which specify that the
6124 condition codes are represented in an unusual manner. The compiler
6125 automatically alters any ordinary conditional jumps which occur in such
6126 situations, but the compiler cannot alter jumps which have been replaced by
6127 peephole optimizations. So it is up to you to alter the assembler code
6128 that the peephole produces. Supply C code to write the assembler output,
6129 and in this C code check the condition code status flags and change the
6130 assembler code as appropriate.
6133 @var{insn-pattern-1} and so on look @emph{almost} like the second
6134 operand of @code{define_insn}. There is one important difference: the
6135 second operand of @code{define_insn} consists of one or more RTX's
6136 enclosed in square brackets. Usually, there is only one: then the same
6137 action can be written as an element of a @code{define_peephole}. But
6138 when there are multiple actions in a @code{define_insn}, they are
6139 implicitly enclosed in a @code{parallel}. Then you must explicitly
6140 write the @code{parallel}, and the square brackets within it, in the
6141 @code{define_peephole}. Thus, if an insn pattern looks like this,
6144 (define_insn "divmodsi4"
6145 [(set (match_operand:SI 0 "general_operand" "=d")
6146 (div:SI (match_operand:SI 1 "general_operand" "0")
6147 (match_operand:SI 2 "general_operand" "dmsK")))
6148 (set (match_operand:SI 3 "general_operand" "=d")
6149 (mod:SI (match_dup 1) (match_dup 2)))]
6151 "divsl%.l %2,%3:%0")
6155 then the way to mention this insn in a peephole is as follows:
6161 [(set (match_operand:SI 0 "general_operand" "=d")
6162 (div:SI (match_operand:SI 1 "general_operand" "0")
6163 (match_operand:SI 2 "general_operand" "dmsK")))
6164 (set (match_operand:SI 3 "general_operand" "=d")
6165 (mod:SI (match_dup 1) (match_dup 2)))])
6172 @node define_peephole2
6173 @subsection RTL to RTL Peephole Optimizers
6174 @findex define_peephole2
6176 The @code{define_peephole2} definition tells the compiler how to
6177 substitute one sequence of instructions for another sequence,
6178 what additional scratch registers may be needed and what their
6183 [@var{insn-pattern-1}
6184 @var{insn-pattern-2}
6187 [@var{new-insn-pattern-1}
6188 @var{new-insn-pattern-2}
6190 "@var{preparation-statements}")
6193 The definition is almost identical to @code{define_split}
6194 (@pxref{Insn Splitting}) except that the pattern to match is not a
6195 single instruction, but a sequence of instructions.
6197 It is possible to request additional scratch registers for use in the
6198 output template. If appropriate registers are not free, the pattern
6199 will simply not match.
6201 @findex match_scratch
6203 Scratch registers are requested with a @code{match_scratch} pattern at
6204 the top level of the input pattern. The allocated register (initially) will
6205 be dead at the point requested within the original sequence. If the scratch
6206 is used at more than a single point, a @code{match_dup} pattern at the
6207 top level of the input pattern marks the last position in the input sequence
6208 at which the register must be available.
6210 Here is an example from the IA-32 machine description:
6214 [(match_scratch:SI 2 "r")
6215 (parallel [(set (match_operand:SI 0 "register_operand" "")
6216 (match_operator:SI 3 "arith_or_logical_operator"
6218 (match_operand:SI 1 "memory_operand" "")]))
6219 (clobber (reg:CC 17))])]
6220 "! optimize_size && ! TARGET_READ_MODIFY"
6221 [(set (match_dup 2) (match_dup 1))
6222 (parallel [(set (match_dup 0)
6223 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
6224 (clobber (reg:CC 17))])]
6229 This pattern tries to split a load from its use in the hopes that we'll be
6230 able to schedule around the memory load latency. It allocates a single
6231 @code{SImode} register of class @code{GENERAL_REGS} (@code{"r"}) that needs
6232 to be live only at the point just before the arithmetic.
6234 A real example requiring extended scratch lifetimes is harder to come by,
6235 so here's a silly made-up example:
6239 [(match_scratch:SI 4 "r")
6240 (set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
6241 (set (match_operand:SI 2 "" "") (match_dup 1))
6243 (set (match_operand:SI 3 "" "") (match_dup 1))]
6244 "/* @r{determine 1 does not overlap 0 and 2} */"
6245 [(set (match_dup 4) (match_dup 1))
6246 (set (match_dup 0) (match_dup 4))
6247 (set (match_dup 2) (match_dup 4))]
6248 (set (match_dup 3) (match_dup 4))]
6253 If we had not added the @code{(match_dup 4)} in the middle of the input
6254 sequence, it might have been the case that the register we chose at the
6255 beginning of the sequence is killed by the first or second @code{set}.
6259 @node Insn Attributes
6260 @section Instruction Attributes
6261 @cindex insn attributes
6262 @cindex instruction attributes
6264 In addition to describing the instruction supported by the target machine,
6265 the @file{md} file also defines a group of @dfn{attributes} and a set of
6266 values for each. Every generated insn is assigned a value for each attribute.
6267 One possible attribute would be the effect that the insn has on the machine's
6268 condition code. This attribute can then be used by @code{NOTICE_UPDATE_CC}
6269 to track the condition codes.
6272 * Defining Attributes:: Specifying attributes and their values.
6273 * Expressions:: Valid expressions for attribute values.
6274 * Tagging Insns:: Assigning attribute values to insns.
6275 * Attr Example:: An example of assigning attributes.
6276 * Insn Lengths:: Computing the length of insns.
6277 * Constant Attributes:: Defining attributes that are constant.
6278 * Delay Slots:: Defining delay slots required for a machine.
6279 * Processor pipeline description:: Specifying information for insn scheduling.
6284 @node Defining Attributes
6285 @subsection Defining Attributes and their Values
6286 @cindex defining attributes and their values
6287 @cindex attributes, defining
6290 The @code{define_attr} expression is used to define each attribute required
6291 by the target machine. It looks like:
6294 (define_attr @var{name} @var{list-of-values} @var{default})
6297 @var{name} is a string specifying the name of the attribute being defined.
6299 @var{list-of-values} is either a string that specifies a comma-separated
6300 list of values that can be assigned to the attribute, or a null string to
6301 indicate that the attribute takes numeric values.
6303 @var{default} is an attribute expression that gives the value of this
6304 attribute for insns that match patterns whose definition does not include
6305 an explicit value for this attribute. @xref{Attr Example}, for more
6306 information on the handling of defaults. @xref{Constant Attributes},
6307 for information on attributes that do not depend on any particular insn.
6310 For each defined attribute, a number of definitions are written to the
6311 @file{insn-attr.h} file. For cases where an explicit set of values is
6312 specified for an attribute, the following are defined:
6316 A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}.
6319 An enumerated class is defined for @samp{attr_@var{name}} with
6320 elements of the form @samp{@var{upper-name}_@var{upper-value}} where
6321 the attribute name and value are first converted to uppercase.
6324 A function @samp{get_attr_@var{name}} is defined that is passed an insn and
6325 returns the attribute value for that insn.
6328 For example, if the following is present in the @file{md} file:
6331 (define_attr "type" "branch,fp,load,store,arith" @dots{})
6335 the following lines will be written to the file @file{insn-attr.h}.
6338 #define HAVE_ATTR_type
6339 enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD,
6340 TYPE_STORE, TYPE_ARITH@};
6341 extern enum attr_type get_attr_type ();
6344 If the attribute takes numeric values, no @code{enum} type will be
6345 defined and the function to obtain the attribute's value will return
6351 @subsection Attribute Expressions
6352 @cindex attribute expressions
6354 RTL expressions used to define attributes use the codes described above
6355 plus a few specific to attribute definitions, to be discussed below.
6356 Attribute value expressions must have one of the following forms:
6359 @cindex @code{const_int} and attributes
6360 @item (const_int @var{i})
6361 The integer @var{i} specifies the value of a numeric attribute. @var{i}
6362 must be non-negative.
6364 The value of a numeric attribute can be specified either with a
6365 @code{const_int}, or as an integer represented as a string in
6366 @code{const_string}, @code{eq_attr} (see below), @code{attr},
6367 @code{symbol_ref}, simple arithmetic expressions, and @code{set_attr}
6368 overrides on specific instructions (@pxref{Tagging Insns}).
6370 @cindex @code{const_string} and attributes
6371 @item (const_string @var{value})
6372 The string @var{value} specifies a constant attribute value.
6373 If @var{value} is specified as @samp{"*"}, it means that the default value of
6374 the attribute is to be used for the insn containing this expression.
6375 @samp{"*"} obviously cannot be used in the @var{default} expression
6376 of a @code{define_attr}.
6378 If the attribute whose value is being specified is numeric, @var{value}
6379 must be a string containing a non-negative integer (normally
6380 @code{const_int} would be used in this case). Otherwise, it must
6381 contain one of the valid values for the attribute.
6383 @cindex @code{if_then_else} and attributes
6384 @item (if_then_else @var{test} @var{true-value} @var{false-value})
6385 @var{test} specifies an attribute test, whose format is defined below.
6386 The value of this expression is @var{true-value} if @var{test} is true,
6387 otherwise it is @var{false-value}.
6389 @cindex @code{cond} and attributes
6390 @item (cond [@var{test1} @var{value1} @dots{}] @var{default})
6391 The first operand of this expression is a vector containing an even
6392 number of expressions and consisting of pairs of @var{test} and @var{value}
6393 expressions. The value of the @code{cond} expression is that of the
6394 @var{value} corresponding to the first true @var{test} expression. If
6395 none of the @var{test} expressions are true, the value of the @code{cond}
6396 expression is that of the @var{default} expression.
6399 @var{test} expressions can have one of the following forms:
6402 @cindex @code{const_int} and attribute tests
6403 @item (const_int @var{i})
6404 This test is true if @var{i} is nonzero and false otherwise.
6406 @cindex @code{not} and attributes
6407 @cindex @code{ior} and attributes
6408 @cindex @code{and} and attributes
6409 @item (not @var{test})
6410 @itemx (ior @var{test1} @var{test2})
6411 @itemx (and @var{test1} @var{test2})
6412 These tests are true if the indicated logical function is true.
6414 @cindex @code{match_operand} and attributes
6415 @item (match_operand:@var{m} @var{n} @var{pred} @var{constraints})
6416 This test is true if operand @var{n} of the insn whose attribute value
6417 is being determined has mode @var{m} (this part of the test is ignored
6418 if @var{m} is @code{VOIDmode}) and the function specified by the string
6419 @var{pred} returns a nonzero value when passed operand @var{n} and mode
6420 @var{m} (this part of the test is ignored if @var{pred} is the null
6423 The @var{constraints} operand is ignored and should be the null string.
6425 @cindex @code{le} and attributes
6426 @cindex @code{leu} and attributes
6427 @cindex @code{lt} and attributes
6428 @cindex @code{gt} and attributes
6429 @cindex @code{gtu} and attributes
6430 @cindex @code{ge} and attributes
6431 @cindex @code{geu} and attributes
6432 @cindex @code{ne} and attributes
6433 @cindex @code{eq} and attributes
6434 @cindex @code{plus} and attributes
6435 @cindex @code{minus} and attributes
6436 @cindex @code{mult} and attributes
6437 @cindex @code{div} and attributes
6438 @cindex @code{mod} and attributes
6439 @cindex @code{abs} and attributes
6440 @cindex @code{neg} and attributes
6441 @cindex @code{ashift} and attributes
6442 @cindex @code{lshiftrt} and attributes
6443 @cindex @code{ashiftrt} and attributes
6444 @item (le @var{arith1} @var{arith2})
6445 @itemx (leu @var{arith1} @var{arith2})
6446 @itemx (lt @var{arith1} @var{arith2})
6447 @itemx (ltu @var{arith1} @var{arith2})
6448 @itemx (gt @var{arith1} @var{arith2})
6449 @itemx (gtu @var{arith1} @var{arith2})
6450 @itemx (ge @var{arith1} @var{arith2})
6451 @itemx (geu @var{arith1} @var{arith2})
6452 @itemx (ne @var{arith1} @var{arith2})
6453 @itemx (eq @var{arith1} @var{arith2})
6454 These tests are true if the indicated comparison of the two arithmetic
6455 expressions is true. Arithmetic expressions are formed with
6456 @code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod},
6457 @code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not},
6458 @code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions.
6461 @code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn
6462 Lengths},for additional forms). @code{symbol_ref} is a string
6463 denoting a C expression that yields an @code{int} when evaluated by the
6464 @samp{get_attr_@dots{}} routine. It should normally be a global
6468 @item (eq_attr @var{name} @var{value})
6469 @var{name} is a string specifying the name of an attribute.
6471 @var{value} is a string that is either a valid value for attribute
6472 @var{name}, a comma-separated list of values, or @samp{!} followed by a
6473 value or list. If @var{value} does not begin with a @samp{!}, this
6474 test is true if the value of the @var{name} attribute of the current
6475 insn is in the list specified by @var{value}. If @var{value} begins
6476 with a @samp{!}, this test is true if the attribute's value is
6477 @emph{not} in the specified list.
6482 (eq_attr "type" "load,store")
6489 (ior (eq_attr "type" "load") (eq_attr "type" "store"))
6492 If @var{name} specifies an attribute of @samp{alternative}, it refers to the
6493 value of the compiler variable @code{which_alternative}
6494 (@pxref{Output Statement}) and the values must be small integers. For
6498 (eq_attr "alternative" "2,3")
6505 (ior (eq (symbol_ref "which_alternative") (const_int 2))
6506 (eq (symbol_ref "which_alternative") (const_int 3)))
6509 Note that, for most attributes, an @code{eq_attr} test is simplified in cases
6510 where the value of the attribute being tested is known for all insns matching
6511 a particular pattern. This is by far the most common case.
6514 @item (attr_flag @var{name})
6515 The value of an @code{attr_flag} expression is true if the flag
6516 specified by @var{name} is true for the @code{insn} currently being
6519 @var{name} is a string specifying one of a fixed set of flags to test.
6520 Test the flags @code{forward} and @code{backward} to determine the
6521 direction of a conditional branch. Test the flags @code{very_likely},
6522 @code{likely}, @code{very_unlikely}, and @code{unlikely} to determine
6523 if a conditional branch is expected to be taken.
6525 If the @code{very_likely} flag is true, then the @code{likely} flag is also
6526 true. Likewise for the @code{very_unlikely} and @code{unlikely} flags.
6528 This example describes a conditional branch delay slot which
6529 can be nullified for forward branches that are taken (annul-true) or
6530 for backward branches which are not taken (annul-false).
6533 (define_delay (eq_attr "type" "cbranch")
6534 [(eq_attr "in_branch_delay" "true")
6535 (and (eq_attr "in_branch_delay" "true")
6536 (attr_flag "forward"))
6537 (and (eq_attr "in_branch_delay" "true")
6538 (attr_flag "backward"))])
6541 The @code{forward} and @code{backward} flags are false if the current
6542 @code{insn} being scheduled is not a conditional branch.
6544 The @code{very_likely} and @code{likely} flags are true if the
6545 @code{insn} being scheduled is not a conditional branch.
6546 The @code{very_unlikely} and @code{unlikely} flags are false if the
6547 @code{insn} being scheduled is not a conditional branch.
6549 @code{attr_flag} is only used during delay slot scheduling and has no
6550 meaning to other passes of the compiler.
6553 @item (attr @var{name})
6554 The value of another attribute is returned. This is most useful
6555 for numeric attributes, as @code{eq_attr} and @code{attr_flag}
6556 produce more efficient code for non-numeric attributes.
6562 @subsection Assigning Attribute Values to Insns
6563 @cindex tagging insns
6564 @cindex assigning attribute values to insns
6566 The value assigned to an attribute of an insn is primarily determined by
6567 which pattern is matched by that insn (or which @code{define_peephole}
6568 generated it). Every @code{define_insn} and @code{define_peephole} can
6569 have an optional last argument to specify the values of attributes for
6570 matching insns. The value of any attribute not specified in a particular
6571 insn is set to the default value for that attribute, as specified in its
6572 @code{define_attr}. Extensive use of default values for attributes
6573 permits the specification of the values for only one or two attributes
6574 in the definition of most insn patterns, as seen in the example in the
6577 The optional last argument of @code{define_insn} and
6578 @code{define_peephole} is a vector of expressions, each of which defines
6579 the value for a single attribute. The most general way of assigning an
6580 attribute's value is to use a @code{set} expression whose first operand is an
6581 @code{attr} expression giving the name of the attribute being set. The
6582 second operand of the @code{set} is an attribute expression
6583 (@pxref{Expressions}) giving the value of the attribute.
6585 When the attribute value depends on the @samp{alternative} attribute
6586 (i.e., which is the applicable alternative in the constraint of the
6587 insn), the @code{set_attr_alternative} expression can be used. It
6588 allows the specification of a vector of attribute expressions, one for
6592 When the generality of arbitrary attribute expressions is not required,
6593 the simpler @code{set_attr} expression can be used, which allows
6594 specifying a string giving either a single attribute value or a list
6595 of attribute values, one for each alternative.
6597 The form of each of the above specifications is shown below. In each case,
6598 @var{name} is a string specifying the attribute to be set.
6601 @item (set_attr @var{name} @var{value-string})
6602 @var{value-string} is either a string giving the desired attribute value,
6603 or a string containing a comma-separated list giving the values for
6604 succeeding alternatives. The number of elements must match the number
6605 of alternatives in the constraint of the insn pattern.
6607 Note that it may be useful to specify @samp{*} for some alternative, in
6608 which case the attribute will assume its default value for insns matching
6611 @findex set_attr_alternative
6612 @item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}])
6613 Depending on the alternative of the insn, the value will be one of the
6614 specified values. This is a shorthand for using a @code{cond} with
6615 tests on the @samp{alternative} attribute.
6618 @item (set (attr @var{name}) @var{value})
6619 The first operand of this @code{set} must be the special RTL expression
6620 @code{attr}, whose sole operand is a string giving the name of the
6621 attribute being set. @var{value} is the value of the attribute.
6624 The following shows three different ways of representing the same
6625 attribute value specification:
6628 (set_attr "type" "load,store,arith")
6630 (set_attr_alternative "type"
6631 [(const_string "load") (const_string "store")
6632 (const_string "arith")])
6635 (cond [(eq_attr "alternative" "1") (const_string "load")
6636 (eq_attr "alternative" "2") (const_string "store")]
6637 (const_string "arith")))
6641 @findex define_asm_attributes
6642 The @code{define_asm_attributes} expression provides a mechanism to
6643 specify the attributes assigned to insns produced from an @code{asm}
6644 statement. It has the form:
6647 (define_asm_attributes [@var{attr-sets}])
6651 where @var{attr-sets} is specified the same as for both the
6652 @code{define_insn} and the @code{define_peephole} expressions.
6654 These values will typically be the ``worst case'' attribute values. For
6655 example, they might indicate that the condition code will be clobbered.
6657 A specification for a @code{length} attribute is handled specially. The
6658 way to compute the length of an @code{asm} insn is to multiply the
6659 length specified in the expression @code{define_asm_attributes} by the
6660 number of machine instructions specified in the @code{asm} statement,
6661 determined by counting the number of semicolons and newlines in the
6662 string. Therefore, the value of the @code{length} attribute specified
6663 in a @code{define_asm_attributes} should be the maximum possible length
6664 of a single machine instruction.
6669 @subsection Example of Attribute Specifications
6670 @cindex attribute specifications example
6671 @cindex attribute specifications
6673 The judicious use of defaulting is important in the efficient use of
6674 insn attributes. Typically, insns are divided into @dfn{types} and an
6675 attribute, customarily called @code{type}, is used to represent this
6676 value. This attribute is normally used only to define the default value
6677 for other attributes. An example will clarify this usage.
6679 Assume we have a RISC machine with a condition code and in which only
6680 full-word operations are performed in registers. Let us assume that we
6681 can divide all insns into loads, stores, (integer) arithmetic
6682 operations, floating point operations, and branches.
6684 Here we will concern ourselves with determining the effect of an insn on
6685 the condition code and will limit ourselves to the following possible
6686 effects: The condition code can be set unpredictably (clobbered), not
6687 be changed, be set to agree with the results of the operation, or only
6688 changed if the item previously set into the condition code has been
6691 Here is part of a sample @file{md} file for such a machine:
6694 (define_attr "type" "load,store,arith,fp,branch" (const_string "arith"))
6696 (define_attr "cc" "clobber,unchanged,set,change0"
6697 (cond [(eq_attr "type" "load")
6698 (const_string "change0")
6699 (eq_attr "type" "store,branch")
6700 (const_string "unchanged")
6701 (eq_attr "type" "arith")
6702 (if_then_else (match_operand:SI 0 "" "")
6703 (const_string "set")
6704 (const_string "clobber"))]
6705 (const_string "clobber")))
6708 [(set (match_operand:SI 0 "general_operand" "=r,r,m")
6709 (match_operand:SI 1 "general_operand" "r,m,r"))]
6715 [(set_attr "type" "arith,load,store")])
6718 Note that we assume in the above example that arithmetic operations
6719 performed on quantities smaller than a machine word clobber the condition
6720 code since they will set the condition code to a value corresponding to the
6726 @subsection Computing the Length of an Insn
6727 @cindex insn lengths, computing
6728 @cindex computing the length of an insn
6730 For many machines, multiple types of branch instructions are provided, each
6731 for different length branch displacements. In most cases, the assembler
6732 will choose the correct instruction to use. However, when the assembler
6733 cannot do so, GCC can when a special attribute, the @code{length}
6734 attribute, is defined. This attribute must be defined to have numeric
6735 values by specifying a null string in its @code{define_attr}.
6737 In the case of the @code{length} attribute, two additional forms of
6738 arithmetic terms are allowed in test expressions:
6741 @cindex @code{match_dup} and attributes
6742 @item (match_dup @var{n})
6743 This refers to the address of operand @var{n} of the current insn, which
6744 must be a @code{label_ref}.
6746 @cindex @code{pc} and attributes
6748 This refers to the address of the @emph{current} insn. It might have
6749 been more consistent with other usage to make this the address of the
6750 @emph{next} insn but this would be confusing because the length of the
6751 current insn is to be computed.
6754 @cindex @code{addr_vec}, length of
6755 @cindex @code{addr_diff_vec}, length of
6756 For normal insns, the length will be determined by value of the
6757 @code{length} attribute. In the case of @code{addr_vec} and
6758 @code{addr_diff_vec} insn patterns, the length is computed as
6759 the number of vectors multiplied by the size of each vector.
6761 Lengths are measured in addressable storage units (bytes).
6763 The following macros can be used to refine the length computation:
6766 @findex ADJUST_INSN_LENGTH
6767 @item ADJUST_INSN_LENGTH (@var{insn}, @var{length})
6768 If defined, modifies the length assigned to instruction @var{insn} as a
6769 function of the context in which it is used. @var{length} is an lvalue
6770 that contains the initially computed length of the insn and should be
6771 updated with the correct length of the insn.
6773 This macro will normally not be required. A case in which it is
6774 required is the ROMP@. On this machine, the size of an @code{addr_vec}
6775 insn must be increased by two to compensate for the fact that alignment
6779 @findex get_attr_length
6780 The routine that returns @code{get_attr_length} (the value of the
6781 @code{length} attribute) can be used by the output routine to
6782 determine the form of the branch instruction to be written, as the
6783 example below illustrates.
6785 As an example of the specification of variable-length branches, consider
6786 the IBM 360. If we adopt the convention that a register will be set to
6787 the starting address of a function, we can jump to labels within 4k of
6788 the start using a four-byte instruction. Otherwise, we need a six-byte
6789 sequence to load the address from memory and then branch to it.
6791 On such a machine, a pattern for a branch instruction might be specified
6797 (label_ref (match_operand 0 "" "")))]
6800 return (get_attr_length (insn) == 4
6801 ? "b %l0" : "l r15,=a(%l0); br r15");
6803 [(set (attr "length")
6804 (if_then_else (lt (match_dup 0) (const_int 4096))
6811 @node Constant Attributes
6812 @subsection Constant Attributes
6813 @cindex constant attributes
6815 A special form of @code{define_attr}, where the expression for the
6816 default value is a @code{const} expression, indicates an attribute that
6817 is constant for a given run of the compiler. Constant attributes may be
6818 used to specify which variety of processor is used. For example,
6821 (define_attr "cpu" "m88100,m88110,m88000"
6823 (cond [(symbol_ref "TARGET_88100") (const_string "m88100")
6824 (symbol_ref "TARGET_88110") (const_string "m88110")]
6825 (const_string "m88000"))))
6827 (define_attr "memory" "fast,slow"
6829 (if_then_else (symbol_ref "TARGET_FAST_MEM")
6830 (const_string "fast")
6831 (const_string "slow"))))
6834 The routine generated for constant attributes has no parameters as it
6835 does not depend on any particular insn. RTL expressions used to define
6836 the value of a constant attribute may use the @code{symbol_ref} form,
6837 but may not use either the @code{match_operand} form or @code{eq_attr}
6838 forms involving insn attributes.
6843 @subsection Delay Slot Scheduling
6844 @cindex delay slots, defining
6846 The insn attribute mechanism can be used to specify the requirements for
6847 delay slots, if any, on a target machine. An instruction is said to
6848 require a @dfn{delay slot} if some instructions that are physically
6849 after the instruction are executed as if they were located before it.
6850 Classic examples are branch and call instructions, which often execute
6851 the following instruction before the branch or call is performed.
6853 On some machines, conditional branch instructions can optionally
6854 @dfn{annul} instructions in the delay slot. This means that the
6855 instruction will not be executed for certain branch outcomes. Both
6856 instructions that annul if the branch is true and instructions that
6857 annul if the branch is false are supported.
6859 Delay slot scheduling differs from instruction scheduling in that
6860 determining whether an instruction needs a delay slot is dependent only
6861 on the type of instruction being generated, not on data flow between the
6862 instructions. See the next section for a discussion of data-dependent
6863 instruction scheduling.
6865 @findex define_delay
6866 The requirement of an insn needing one or more delay slots is indicated
6867 via the @code{define_delay} expression. It has the following form:
6870 (define_delay @var{test}
6871 [@var{delay-1} @var{annul-true-1} @var{annul-false-1}
6872 @var{delay-2} @var{annul-true-2} @var{annul-false-2}
6876 @var{test} is an attribute test that indicates whether this
6877 @code{define_delay} applies to a particular insn. If so, the number of
6878 required delay slots is determined by the length of the vector specified
6879 as the second argument. An insn placed in delay slot @var{n} must
6880 satisfy attribute test @var{delay-n}. @var{annul-true-n} is an
6881 attribute test that specifies which insns may be annulled if the branch
6882 is true. Similarly, @var{annul-false-n} specifies which insns in the
6883 delay slot may be annulled if the branch is false. If annulling is not
6884 supported for that delay slot, @code{(nil)} should be coded.
6886 For example, in the common case where branch and call insns require
6887 a single delay slot, which may contain any insn other than a branch or
6888 call, the following would be placed in the @file{md} file:
6891 (define_delay (eq_attr "type" "branch,call")
6892 [(eq_attr "type" "!branch,call") (nil) (nil)])
6895 Multiple @code{define_delay} expressions may be specified. In this
6896 case, each such expression specifies different delay slot requirements
6897 and there must be no insn for which tests in two @code{define_delay}
6898 expressions are both true.
6900 For example, if we have a machine that requires one delay slot for branches
6901 but two for calls, no delay slot can contain a branch or call insn,
6902 and any valid insn in the delay slot for the branch can be annulled if the
6903 branch is true, we might represent this as follows:
6906 (define_delay (eq_attr "type" "branch")
6907 [(eq_attr "type" "!branch,call")
6908 (eq_attr "type" "!branch,call")
6911 (define_delay (eq_attr "type" "call")
6912 [(eq_attr "type" "!branch,call") (nil) (nil)
6913 (eq_attr "type" "!branch,call") (nil) (nil)])
6915 @c the above is *still* too long. --mew 4feb93
6919 @node Processor pipeline description
6920 @subsection Specifying processor pipeline description
6921 @cindex processor pipeline description
6922 @cindex processor functional units
6923 @cindex instruction latency time
6924 @cindex interlock delays
6925 @cindex data dependence delays
6926 @cindex reservation delays
6927 @cindex pipeline hazard recognizer
6928 @cindex automaton based pipeline description
6929 @cindex regular expressions
6930 @cindex deterministic finite state automaton
6931 @cindex automaton based scheduler
6935 To achieve better performance, most modern processors
6936 (super-pipelined, superscalar @acronym{RISC}, and @acronym{VLIW}
6937 processors) have many @dfn{functional units} on which several
6938 instructions can be executed simultaneously. An instruction starts
6939 execution if its issue conditions are satisfied. If not, the
6940 instruction is stalled until its conditions are satisfied. Such
6941 @dfn{interlock (pipeline) delay} causes interruption of the fetching
6942 of successor instructions (or demands nop instructions, e.g.@: for some
6945 There are two major kinds of interlock delays in modern processors.
6946 The first one is a data dependence delay determining @dfn{instruction
6947 latency time}. The instruction execution is not started until all
6948 source data have been evaluated by prior instructions (there are more
6949 complex cases when the instruction execution starts even when the data
6950 are not available but will be ready in given time after the
6951 instruction execution start). Taking the data dependence delays into
6952 account is simple. The data dependence (true, output, and
6953 anti-dependence) delay between two instructions is given by a
6954 constant. In most cases this approach is adequate. The second kind
6955 of interlock delays is a reservation delay. The reservation delay
6956 means that two instructions under execution will be in need of shared
6957 processors resources, i.e.@: buses, internal registers, and/or
6958 functional units, which are reserved for some time. Taking this kind
6959 of delay into account is complex especially for modern @acronym{RISC}
6962 The task of exploiting more processor parallelism is solved by an
6963 instruction scheduler. For a better solution to this problem, the
6964 instruction scheduler has to have an adequate description of the
6965 processor parallelism (or @dfn{pipeline description}). GCC
6966 machine descriptions describe processor parallelism and functional
6967 unit reservations for groups of instructions with the aid of
6968 @dfn{regular expressions}.
6970 The GCC instruction scheduler uses a @dfn{pipeline hazard recognizer} to
6971 figure out the possibility of the instruction issue by the processor
6972 on a given simulated processor cycle. The pipeline hazard recognizer is
6973 automatically generated from the processor pipeline description. The
6974 pipeline hazard recognizer generated from the machine description
6975 is based on a deterministic finite state automaton (@acronym{DFA}):
6976 the instruction issue is possible if there is a transition from one
6977 automaton state to another one. This algorithm is very fast, and
6978 furthermore, its speed is not dependent on processor
6979 complexity@footnote{However, the size of the automaton depends on
6980 processor complexity. To limit this effect, machine descriptions
6981 can split orthogonal parts of the machine description among several
6982 automata: but then, since each of these must be stepped independently,
6983 this does cause a small decrease in the algorithm's performance.}.
6985 @cindex automaton based pipeline description
6986 The rest of this section describes the directives that constitute
6987 an automaton-based processor pipeline description. The order of
6988 these constructions within the machine description file is not
6991 @findex define_automaton
6992 @cindex pipeline hazard recognizer
6993 The following optional construction describes names of automata
6994 generated and used for the pipeline hazards recognition. Sometimes
6995 the generated finite state automaton used by the pipeline hazard
6996 recognizer is large. If we use more than one automaton and bind functional
6997 units to the automata, the total size of the automata is usually
6998 less than the size of the single automaton. If there is no one such
6999 construction, only one finite state automaton is generated.
7002 (define_automaton @var{automata-names})
7005 @var{automata-names} is a string giving names of the automata. The
7006 names are separated by commas. All the automata should have unique names.
7007 The automaton name is used in the constructions @code{define_cpu_unit} and
7008 @code{define_query_cpu_unit}.
7010 @findex define_cpu_unit
7011 @cindex processor functional units
7012 Each processor functional unit used in the description of instruction
7013 reservations should be described by the following construction.
7016 (define_cpu_unit @var{unit-names} [@var{automaton-name}])
7019 @var{unit-names} is a string giving the names of the functional units
7020 separated by commas. Don't use name @samp{nothing}, it is reserved
7023 @var{automaton-name} is a string giving the name of the automaton with
7024 which the unit is bound. The automaton should be described in
7025 construction @code{define_automaton}. You should give
7026 @dfn{automaton-name}, if there is a defined automaton.
7028 The assignment of units to automata are constrained by the uses of the
7029 units in insn reservations. The most important constraint is: if a
7030 unit reservation is present on a particular cycle of an alternative
7031 for an insn reservation, then some unit from the same automaton must
7032 be present on the same cycle for the other alternatives of the insn
7033 reservation. The rest of the constraints are mentioned in the
7034 description of the subsequent constructions.
7036 @findex define_query_cpu_unit
7037 @cindex querying function unit reservations
7038 The following construction describes CPU functional units analogously
7039 to @code{define_cpu_unit}. The reservation of such units can be
7040 queried for an automaton state. The instruction scheduler never
7041 queries reservation of functional units for given automaton state. So
7042 as a rule, you don't need this construction. This construction could
7043 be used for future code generation goals (e.g.@: to generate
7044 @acronym{VLIW} insn templates).
7047 (define_query_cpu_unit @var{unit-names} [@var{automaton-name}])
7050 @var{unit-names} is a string giving names of the functional units
7051 separated by commas.
7053 @var{automaton-name} is a string giving the name of the automaton with
7054 which the unit is bound.
7056 @findex define_insn_reservation
7057 @cindex instruction latency time
7058 @cindex regular expressions
7060 The following construction is the major one to describe pipeline
7061 characteristics of an instruction.
7064 (define_insn_reservation @var{insn-name} @var{default_latency}
7065 @var{condition} @var{regexp})
7068 @var{default_latency} is a number giving latency time of the
7069 instruction. There is an important difference between the old
7070 description and the automaton based pipeline description. The latency
7071 time is used for all dependencies when we use the old description. In
7072 the automaton based pipeline description, the given latency time is only
7073 used for true dependencies. The cost of anti-dependencies is always
7074 zero and the cost of output dependencies is the difference between
7075 latency times of the producing and consuming insns (if the difference
7076 is negative, the cost is considered to be zero). You can always
7077 change the default costs for any description by using the target hook
7078 @code{TARGET_SCHED_ADJUST_COST} (@pxref{Scheduling}).
7080 @var{insn-name} is a string giving the internal name of the insn. The
7081 internal names are used in constructions @code{define_bypass} and in
7082 the automaton description file generated for debugging. The internal
7083 name has nothing in common with the names in @code{define_insn}. It is a
7084 good practice to use insn classes described in the processor manual.
7086 @var{condition} defines what RTL insns are described by this
7087 construction. You should remember that you will be in trouble if
7088 @var{condition} for two or more different
7089 @code{define_insn_reservation} constructions is TRUE for an insn. In
7090 this case what reservation will be used for the insn is not defined.
7091 Such cases are not checked during generation of the pipeline hazards
7092 recognizer because in general recognizing that two conditions may have
7093 the same value is quite difficult (especially if the conditions
7094 contain @code{symbol_ref}). It is also not checked during the
7095 pipeline hazard recognizer work because it would slow down the
7096 recognizer considerably.
7098 @var{regexp} is a string describing the reservation of the cpu's functional
7099 units by the instruction. The reservations are described by a regular
7100 expression according to the following syntax:
7103 regexp = regexp "," oneof
7106 oneof = oneof "|" allof
7109 allof = allof "+" repeat
7112 repeat = element "*" number
7115 element = cpu_function_unit_name
7124 @samp{,} is used for describing the start of the next cycle in
7128 @samp{|} is used for describing a reservation described by the first
7129 regular expression @strong{or} a reservation described by the second
7130 regular expression @strong{or} etc.
7133 @samp{+} is used for describing a reservation described by the first
7134 regular expression @strong{and} a reservation described by the
7135 second regular expression @strong{and} etc.
7138 @samp{*} is used for convenience and simply means a sequence in which
7139 the regular expression are repeated @var{number} times with cycle
7140 advancing (see @samp{,}).
7143 @samp{cpu_function_unit_name} denotes reservation of the named
7147 @samp{reservation_name} --- see description of construction
7148 @samp{define_reservation}.
7151 @samp{nothing} denotes no unit reservations.
7154 @findex define_reservation
7155 Sometimes unit reservations for different insns contain common parts.
7156 In such case, you can simplify the pipeline description by describing
7157 the common part by the following construction
7160 (define_reservation @var{reservation-name} @var{regexp})
7163 @var{reservation-name} is a string giving name of @var{regexp}.
7164 Functional unit names and reservation names are in the same name
7165 space. So the reservation names should be different from the
7166 functional unit names and can not be the reserved name @samp{nothing}.
7168 @findex define_bypass
7169 @cindex instruction latency time
7171 The following construction is used to describe exceptions in the
7172 latency time for given instruction pair. This is so called bypasses.
7175 (define_bypass @var{number} @var{out_insn_names} @var{in_insn_names}
7179 @var{number} defines when the result generated by the instructions
7180 given in string @var{out_insn_names} will be ready for the
7181 instructions given in string @var{in_insn_names}. The instructions in
7182 the string are separated by commas.
7184 @var{guard} is an optional string giving the name of a C function which
7185 defines an additional guard for the bypass. The function will get the
7186 two insns as parameters. If the function returns zero the bypass will
7187 be ignored for this case. The additional guard is necessary to
7188 recognize complicated bypasses, e.g.@: when the consumer is only an address
7189 of insn @samp{store} (not a stored value).
7191 @findex exclusion_set
7192 @findex presence_set
7193 @findex final_presence_set
7195 @findex final_absence_set
7198 The following five constructions are usually used to describe
7199 @acronym{VLIW} processors, or more precisely, to describe a placement
7200 of small instructions into @acronym{VLIW} instruction slots. They
7201 can be used for @acronym{RISC} processors, too.
7204 (exclusion_set @var{unit-names} @var{unit-names})
7205 (presence_set @var{unit-names} @var{patterns})
7206 (final_presence_set @var{unit-names} @var{patterns})
7207 (absence_set @var{unit-names} @var{patterns})
7208 (final_absence_set @var{unit-names} @var{patterns})
7211 @var{unit-names} is a string giving names of functional units
7212 separated by commas.
7214 @var{patterns} is a string giving patterns of functional units
7215 separated by comma. Currently pattern is one unit or units
7216 separated by white-spaces.
7218 The first construction (@samp{exclusion_set}) means that each
7219 functional unit in the first string can not be reserved simultaneously
7220 with a unit whose name is in the second string and vice versa. For
7221 example, the construction is useful for describing processors
7222 (e.g.@: some SPARC processors) with a fully pipelined floating point
7223 functional unit which can execute simultaneously only single floating
7224 point insns or only double floating point insns.
7226 The second construction (@samp{presence_set}) means that each
7227 functional unit in the first string can not be reserved unless at
7228 least one of pattern of units whose names are in the second string is
7229 reserved. This is an asymmetric relation. For example, it is useful
7230 for description that @acronym{VLIW} @samp{slot1} is reserved after
7231 @samp{slot0} reservation. We could describe it by the following
7235 (presence_set "slot1" "slot0")
7238 Or @samp{slot1} is reserved only after @samp{slot0} and unit @samp{b0}
7239 reservation. In this case we could write
7242 (presence_set "slot1" "slot0 b0")
7245 The third construction (@samp{final_presence_set}) is analogous to
7246 @samp{presence_set}. The difference between them is when checking is
7247 done. When an instruction is issued in given automaton state
7248 reflecting all current and planned unit reservations, the automaton
7249 state is changed. The first state is a source state, the second one
7250 is a result state. Checking for @samp{presence_set} is done on the
7251 source state reservation, checking for @samp{final_presence_set} is
7252 done on the result reservation. This construction is useful to
7253 describe a reservation which is actually two subsequent reservations.
7254 For example, if we use
7257 (presence_set "slot1" "slot0")
7260 the following insn will be never issued (because @samp{slot1} requires
7261 @samp{slot0} which is absent in the source state).
7264 (define_reservation "insn_and_nop" "slot0 + slot1")
7267 but it can be issued if we use analogous @samp{final_presence_set}.
7269 The forth construction (@samp{absence_set}) means that each functional
7270 unit in the first string can be reserved only if each pattern of units
7271 whose names are in the second string is not reserved. This is an
7272 asymmetric relation (actually @samp{exclusion_set} is analogous to
7273 this one but it is symmetric). For example it might be useful in a
7274 @acronym{VLIW} description to say that @samp{slot0} cannot be reserved
7275 after either @samp{slot1} or @samp{slot2} have been reserved. This
7276 can be described as:
7279 (absence_set "slot0" "slot1, slot2")
7282 Or @samp{slot2} can not be reserved if @samp{slot0} and unit @samp{b0}
7283 are reserved or @samp{slot1} and unit @samp{b1} are reserved. In
7284 this case we could write
7287 (absence_set "slot2" "slot0 b0, slot1 b1")
7290 All functional units mentioned in a set should belong to the same
7293 The last construction (@samp{final_absence_set}) is analogous to
7294 @samp{absence_set} but checking is done on the result (state)
7295 reservation. See comments for @samp{final_presence_set}.
7297 @findex automata_option
7298 @cindex deterministic finite state automaton
7299 @cindex nondeterministic finite state automaton
7300 @cindex finite state automaton minimization
7301 You can control the generator of the pipeline hazard recognizer with
7302 the following construction.
7305 (automata_option @var{options})
7308 @var{options} is a string giving options which affect the generated
7309 code. Currently there are the following options:
7313 @dfn{no-minimization} makes no minimization of the automaton. This is
7314 only worth to do when we are debugging the description and need to
7315 look more accurately at reservations of states.
7318 @dfn{time} means printing time statistics about the generation of
7322 @dfn{stats} means printing statistics about the generated automata
7323 such as the number of DFA states, NDFA states and arcs.
7326 @dfn{v} means a generation of the file describing the result automata.
7327 The file has suffix @samp{.dfa} and can be used for the description
7328 verification and debugging.
7331 @dfn{w} means a generation of warning instead of error for
7332 non-critical errors.
7335 @dfn{ndfa} makes nondeterministic finite state automata. This affects
7336 the treatment of operator @samp{|} in the regular expressions. The
7337 usual treatment of the operator is to try the first alternative and,
7338 if the reservation is not possible, the second alternative. The
7339 nondeterministic treatment means trying all alternatives, some of them
7340 may be rejected by reservations in the subsequent insns.
7343 @dfn{progress} means output of a progress bar showing how many states
7344 were generated so far for automaton being processed. This is useful
7345 during debugging a @acronym{DFA} description. If you see too many
7346 generated states, you could interrupt the generator of the pipeline
7347 hazard recognizer and try to figure out a reason for generation of the
7351 As an example, consider a superscalar @acronym{RISC} machine which can
7352 issue three insns (two integer insns and one floating point insn) on
7353 the cycle but can finish only two insns. To describe this, we define
7354 the following functional units.
7357 (define_cpu_unit "i0_pipeline, i1_pipeline, f_pipeline")
7358 (define_cpu_unit "port0, port1")
7361 All simple integer insns can be executed in any integer pipeline and
7362 their result is ready in two cycles. The simple integer insns are
7363 issued into the first pipeline unless it is reserved, otherwise they
7364 are issued into the second pipeline. Integer division and
7365 multiplication insns can be executed only in the second integer
7366 pipeline and their results are ready correspondingly in 8 and 4
7367 cycles. The integer division is not pipelined, i.e.@: the subsequent
7368 integer division insn can not be issued until the current division
7369 insn finished. Floating point insns are fully pipelined and their
7370 results are ready in 3 cycles. Where the result of a floating point
7371 insn is used by an integer insn, an additional delay of one cycle is
7372 incurred. To describe all of this we could specify
7375 (define_cpu_unit "div")
7377 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
7378 "(i0_pipeline | i1_pipeline), (port0 | port1)")
7380 (define_insn_reservation "mult" 4 (eq_attr "type" "mult")
7381 "i1_pipeline, nothing*2, (port0 | port1)")
7383 (define_insn_reservation "div" 8 (eq_attr "type" "div")
7384 "i1_pipeline, div*7, div + (port0 | port1)")
7386 (define_insn_reservation "float" 3 (eq_attr "type" "float")
7387 "f_pipeline, nothing, (port0 | port1))
7389 (define_bypass 4 "float" "simple,mult,div")
7392 To simplify the description we could describe the following reservation
7395 (define_reservation "finish" "port0|port1")
7398 and use it in all @code{define_insn_reservation} as in the following
7402 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
7403 "(i0_pipeline | i1_pipeline), finish")
7409 @node Conditional Execution
7410 @section Conditional Execution
7411 @cindex conditional execution
7414 A number of architectures provide for some form of conditional
7415 execution, or predication. The hallmark of this feature is the
7416 ability to nullify most of the instructions in the instruction set.
7417 When the instruction set is large and not entirely symmetric, it
7418 can be quite tedious to describe these forms directly in the
7419 @file{.md} file. An alternative is the @code{define_cond_exec} template.
7421 @findex define_cond_exec
7424 [@var{predicate-pattern}]
7426 "@var{output-template}")
7429 @var{predicate-pattern} is the condition that must be true for the
7430 insn to be executed at runtime and should match a relational operator.
7431 One can use @code{match_operator} to match several relational operators
7432 at once. Any @code{match_operand} operands must have no more than one
7435 @var{condition} is a C expression that must be true for the generated
7438 @findex current_insn_predicate
7439 @var{output-template} is a string similar to the @code{define_insn}
7440 output template (@pxref{Output Template}), except that the @samp{*}
7441 and @samp{@@} special cases do not apply. This is only useful if the
7442 assembly text for the predicate is a simple prefix to the main insn.
7443 In order to handle the general case, there is a global variable
7444 @code{current_insn_predicate} that will contain the entire predicate
7445 if the current insn is predicated, and will otherwise be @code{NULL}.
7447 When @code{define_cond_exec} is used, an implicit reference to
7448 the @code{predicable} instruction attribute is made.
7449 @xref{Insn Attributes}. This attribute must be boolean (i.e.@: have
7450 exactly two elements in its @var{list-of-values}). Further, it must
7451 not be used with complex expressions. That is, the default and all
7452 uses in the insns must be a simple constant, not dependent on the
7453 alternative or anything else.
7455 For each @code{define_insn} for which the @code{predicable}
7456 attribute is true, a new @code{define_insn} pattern will be
7457 generated that matches a predicated version of the instruction.
7461 (define_insn "addsi"
7462 [(set (match_operand:SI 0 "register_operand" "r")
7463 (plus:SI (match_operand:SI 1 "register_operand" "r")
7464 (match_operand:SI 2 "register_operand" "r")))]
7469 [(ne (match_operand:CC 0 "register_operand" "c")
7476 generates a new pattern
7481 (ne (match_operand:CC 3 "register_operand" "c") (const_int 0))
7482 (set (match_operand:SI 0 "register_operand" "r")
7483 (plus:SI (match_operand:SI 1 "register_operand" "r")
7484 (match_operand:SI 2 "register_operand" "r"))))]
7485 "(@var{test2}) && (@var{test1})"
7486 "(%3) add %2,%1,%0")
7491 @node Constant Definitions
7492 @section Constant Definitions
7493 @cindex constant definitions
7494 @findex define_constants
7496 Using literal constants inside instruction patterns reduces legibility and
7497 can be a maintenance problem.
7499 To overcome this problem, you may use the @code{define_constants}
7500 expression. It contains a vector of name-value pairs. From that
7501 point on, wherever any of the names appears in the MD file, it is as
7502 if the corresponding value had been written instead. You may use
7503 @code{define_constants} multiple times; each appearance adds more
7504 constants to the table. It is an error to redefine a constant with
7507 To come back to the a29k load multiple example, instead of
7511 [(match_parallel 0 "load_multiple_operation"
7512 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
7513 (match_operand:SI 2 "memory_operand" "m"))
7515 (clobber (reg:SI 179))])]
7531 [(match_parallel 0 "load_multiple_operation"
7532 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
7533 (match_operand:SI 2 "memory_operand" "m"))
7535 (clobber (reg:SI R_CR))])]
7540 The constants that are defined with a define_constant are also output
7541 in the insn-codes.h header file as #defines.
7546 @cindex macros in @file{.md} files
7548 Ports often need to define similar patterns for more than one machine
7549 mode or for more than one rtx code. GCC provides some simple macro
7550 facilities to make this process easier.
7553 * Mode Macros:: Generating variations of patterns for different modes.
7554 * Code Macros:: Doing the same for codes.
7558 @subsection Mode Macros
7559 @cindex mode macros in @file{.md} files
7561 Ports often need to define similar patterns for two or more different modes.
7566 If a processor has hardware support for both single and double
7567 floating-point arithmetic, the @code{SFmode} patterns tend to be
7568 very similar to the @code{DFmode} ones.
7571 If a port uses @code{SImode} pointers in one configuration and
7572 @code{DImode} pointers in another, it will usually have very similar
7573 @code{SImode} and @code{DImode} patterns for manipulating pointers.
7576 Mode macros allow several patterns to be instantiated from one
7577 @file{.md} file template. They can be used with any type of
7578 rtx-based construct, such as a @code{define_insn},
7579 @code{define_split}, or @code{define_peephole2}.
7582 * Defining Mode Macros:: Defining a new mode macro.
7583 * Substitutions:: Combining mode macros with substitutions
7584 * Examples:: Examples
7587 @node Defining Mode Macros
7588 @subsubsection Defining Mode Macros
7589 @findex define_mode_macro
7591 The syntax for defining a mode macro is:
7594 (define_mode_macro @var{name} [(@var{mode1} "@var{cond1}") ... (@var{moden} "@var{condn}")])
7597 This allows subsequent @file{.md} file constructs to use the mode suffix
7598 @code{:@var{name}}. Every construct that does so will be expanded
7599 @var{n} times, once with every use of @code{:@var{name}} replaced by
7600 @code{:@var{mode1}}, once with every use replaced by @code{:@var{mode2}},
7601 and so on. In the expansion for a particular @var{modei}, every
7602 C condition will also require that @var{condi} be true.
7607 (define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
7610 defines a new mode suffix @code{:P}. Every construct that uses
7611 @code{:P} will be expanded twice, once with every @code{:P} replaced
7612 by @code{:SI} and once with every @code{:P} replaced by @code{:DI}.
7613 The @code{:SI} version will only apply if @code{Pmode == SImode} and
7614 the @code{:DI} version will only apply if @code{Pmode == DImode}.
7616 As with other @file{.md} conditions, an empty string is treated
7617 as ``always true''. @code{(@var{mode} "")} can also be abbreviated
7618 to @code{@var{mode}}. For example:
7621 (define_mode_macro GPR [SI (DI "TARGET_64BIT")])
7624 means that the @code{:DI} expansion only applies if @code{TARGET_64BIT}
7625 but that the @code{:SI} expansion has no such constraint.
7627 Macros are applied in the order they are defined. This can be
7628 significant if two macros are used in a construct that requires
7629 substitutions. @xref{Substitutions}.
7632 @subsubsection Substitution in Mode Macros
7633 @findex define_mode_attr
7635 If an @file{.md} file construct uses mode macros, each version of the
7636 construct will often need slightly different strings or modes. For
7641 When a @code{define_expand} defines several @code{add@var{m}3} patterns
7642 (@pxref{Standard Names}), each expander will need to use the
7643 appropriate mode name for @var{m}.
7646 When a @code{define_insn} defines several instruction patterns,
7647 each instruction will often use a different assembler mnemonic.
7650 When a @code{define_insn} requires operands with different modes,
7651 using a macro for one of the operand modes usually requires a specific
7652 mode for the other operand(s).
7655 GCC supports such variations through a system of ``mode attributes''.
7656 There are two standard attributes: @code{mode}, which is the name of
7657 the mode in lower case, and @code{MODE}, which is the same thing in
7658 upper case. You can define other attributes using:
7661 (define_mode_attr @var{name} [(@var{mode1} "@var{value1}") ... (@var{moden} "@var{valuen}")])
7664 where @var{name} is the name of the attribute and @var{valuei}
7665 is the value associated with @var{modei}.
7667 When GCC replaces some @var{:macro} with @var{:mode}, it will scan
7668 each string and mode in the pattern for sequences of the form
7669 @code{<@var{macro}:@var{attr}>}, where @var{attr} is the name of a
7670 mode attribute. If the attribute is defined for @var{mode}, the whole
7671 @code{<...>} sequence will be replaced by the appropriate attribute
7674 For example, suppose an @file{.md} file has:
7677 (define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
7678 (define_mode_attr load [(SI "lw") (DI "ld")])
7681 If one of the patterns that uses @code{:P} contains the string
7682 @code{"<P:load>\t%0,%1"}, the @code{SI} version of that pattern
7683 will use @code{"lw\t%0,%1"} and the @code{DI} version will use
7686 Here is an example of using an attribute for a mode:
7689 (define_mode_macro LONG [SI DI])
7690 (define_mode_attr SHORT [(SI "HI") (DI "SI")])
7692 (sign_extend:LONG (match_operand:<LONG:SHORT> ...)) ...)
7695 The @code{@var{macro}:} prefix may be omitted, in which case the
7696 substitution will be attempted for every macro expansion.
7699 @subsubsection Mode Macro Examples
7701 Here is an example from the MIPS port. It defines the following
7702 modes and attributes (among others):
7705 (define_mode_macro GPR [SI (DI "TARGET_64BIT")])
7706 (define_mode_attr d [(SI "") (DI "d")])
7709 and uses the following template to define both @code{subsi3}
7713 (define_insn "sub<mode>3"
7714 [(set (match_operand:GPR 0 "register_operand" "=d")
7715 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
7716 (match_operand:GPR 2 "register_operand" "d")))]
7719 [(set_attr "type" "arith")
7720 (set_attr "mode" "<MODE>")])
7723 This is exactly equivalent to:
7726 (define_insn "subsi3"
7727 [(set (match_operand:SI 0 "register_operand" "=d")
7728 (minus:SI (match_operand:SI 1 "register_operand" "d")
7729 (match_operand:SI 2 "register_operand" "d")))]
7732 [(set_attr "type" "arith")
7733 (set_attr "mode" "SI")])
7735 (define_insn "subdi3"
7736 [(set (match_operand:DI 0 "register_operand" "=d")
7737 (minus:DI (match_operand:DI 1 "register_operand" "d")
7738 (match_operand:DI 2 "register_operand" "d")))]
7741 [(set_attr "type" "arith")
7742 (set_attr "mode" "DI")])
7746 @subsection Code Macros
7747 @cindex code macros in @file{.md} files
7748 @findex define_code_macro
7749 @findex define_code_attr
7751 Code macros operate in a similar way to mode macros. @xref{Mode Macros}.
7756 (define_code_macro @var{name} [(@var{code1} "@var{cond1}") ... (@var{coden} "@var{condn}")])
7759 defines a pseudo rtx code @var{name} that can be instantiated as
7760 @var{codei} if condition @var{condi} is true. Each @var{codei}
7761 must have the same rtx format. @xref{RTL Classes}.
7763 As with mode macros, each pattern that uses @var{name} will be
7764 expanded @var{n} times, once with all uses of @var{name} replaced by
7765 @var{code1}, once with all uses replaced by @var{code2}, and so on.
7766 @xref{Defining Mode Macros}.
7768 It is possible to define attributes for codes as well as for modes.
7769 There are two standard code attributes: @code{code}, the name of the
7770 code in lower case, and @code{CODE}, the name of the code in upper case.
7771 Other attributes are defined using:
7774 (define_code_attr @var{name} [(@var{code1} "@var{value1}") ... (@var{coden} "@var{valuen}")])
7777 Here's an example of code macros in action, taken from the MIPS port:
7780 (define_code_macro any_cond [unordered ordered unlt unge uneq ltgt unle ungt
7781 eq ne gt ge lt le gtu geu ltu leu])
7783 (define_expand "b<code>"
7785 (if_then_else (any_cond:CC (cc0)
7787 (label_ref (match_operand 0 ""))
7791 gen_conditional_branch (operands, <CODE>);
7796 This is equivalent to:
7799 (define_expand "bunordered"
7801 (if_then_else (unordered:CC (cc0)
7803 (label_ref (match_operand 0 ""))
7807 gen_conditional_branch (operands, UNORDERED);
7811 (define_expand "bordered"
7813 (if_then_else (ordered:CC (cc0)
7815 (label_ref (match_operand 0 ""))
7819 gen_conditional_branch (operands, ORDERED);