1 @c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1996, 1998, 1999, 2000, 2001,
2 @c 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
3 @c Free Software Foundation, Inc.
4 @c This is part of the GCC manual.
5 @c For copying conditions, see the file gcc.texi.
9 @chapter Machine Descriptions
10 @cindex machine descriptions
12 A machine description has two parts: a file of instruction patterns
13 (@file{.md} file) and a C header file of macro definitions.
15 The @file{.md} file for a target machine contains a pattern for each
16 instruction that the target machine supports (or at least each instruction
17 that is worth telling the compiler about). It may also contain comments.
18 A semicolon causes the rest of the line to be a comment, unless the semicolon
19 is inside a quoted string.
21 See the next chapter for information on the C header file.
24 * Overview:: How the machine description is used.
25 * Patterns:: How to write instruction patterns.
26 * Example:: An explained example of a @code{define_insn} pattern.
27 * RTL Template:: The RTL template defines what insns match a pattern.
28 * Output Template:: The output template says how to make assembler code
30 * Output Statement:: For more generality, write C code to output
32 * Predicates:: Controlling what kinds of operands can be used
34 * Constraints:: Fine-tuning operand selection.
35 * Standard Names:: Names mark patterns to use for code generation.
36 * Pattern Ordering:: When the order of patterns makes a difference.
37 * Dependent Patterns:: Having one pattern may make you need another.
38 * Jump Patterns:: Special considerations for patterns for jump insns.
39 * Looping Patterns:: How to define patterns for special looping insns.
40 * Insn Canonicalizations::Canonicalization of Instructions
41 * Expander Definitions::Generating a sequence of several RTL insns
42 for a standard operation.
43 * Insn Splitting:: Splitting Instructions into Multiple Instructions.
44 * Including Patterns:: Including Patterns in Machine Descriptions.
45 * Peephole Definitions::Defining machine-specific peephole optimizations.
46 * Insn Attributes:: Specifying the value of attributes for generated insns.
47 * Conditional Execution::Generating @code{define_insn} patterns for
49 * Constant Definitions::Defining symbolic constants that can be used in the
51 * Iterators:: Using iterators to generate patterns from a template.
55 @section Overview of How the Machine Description is Used
57 There are three main conversions that happen in the compiler:
62 The front end reads the source code and builds a parse tree.
65 The parse tree is used to generate an RTL insn list based on named
69 The insn list is matched against the RTL templates to produce assembler
74 For the generate pass, only the names of the insns matter, from either a
75 named @code{define_insn} or a @code{define_expand}. The compiler will
76 choose the pattern with the right name and apply the operands according
77 to the documentation later in this chapter, without regard for the RTL
78 template or operand constraints. Note that the names the compiler looks
79 for are hard-coded in the compiler---it will ignore unnamed patterns and
80 patterns with names it doesn't know about, but if you don't provide a
81 named pattern it needs, it will abort.
83 If a @code{define_insn} is used, the template given is inserted into the
84 insn list. If a @code{define_expand} is used, one of three things
85 happens, based on the condition logic. The condition logic may manually
86 create new insns for the insn list, say via @code{emit_insn()}, and
87 invoke @code{DONE}. For certain named patterns, it may invoke @code{FAIL} to tell the
88 compiler to use an alternate way of performing that task. If it invokes
89 neither @code{DONE} nor @code{FAIL}, the template given in the pattern
90 is inserted, as if the @code{define_expand} were a @code{define_insn}.
92 Once the insn list is generated, various optimization passes convert,
93 replace, and rearrange the insns in the insn list. This is where the
94 @code{define_split} and @code{define_peephole} patterns get used, for
97 Finally, the insn list's RTL is matched up with the RTL templates in the
98 @code{define_insn} patterns, and those patterns are used to emit the
99 final assembly code. For this purpose, each named @code{define_insn}
100 acts like it's unnamed, since the names are ignored.
103 @section Everything about Instruction Patterns
105 @cindex instruction patterns
108 Each instruction pattern contains an incomplete RTL expression, with pieces
109 to be filled in later, operand constraints that restrict how the pieces can
110 be filled in, and an output pattern or C code to generate the assembler
111 output, all wrapped up in a @code{define_insn} expression.
113 A @code{define_insn} is an RTL expression containing four or five operands:
117 An optional name. The presence of a name indicate that this instruction
118 pattern can perform a certain standard job for the RTL-generation
119 pass of the compiler. This pass knows certain names and will use
120 the instruction patterns with those names, if the names are defined
121 in the machine description.
123 The absence of a name is indicated by writing an empty string
124 where the name should go. Nameless instruction patterns are never
125 used for generating RTL code, but they may permit several simpler insns
126 to be combined later on.
128 Names that are not thus known and used in RTL-generation have no
129 effect; they are equivalent to no name at all.
131 For the purpose of debugging the compiler, you may also specify a
132 name beginning with the @samp{*} character. Such a name is used only
133 for identifying the instruction in RTL dumps; it is entirely equivalent
134 to having a nameless pattern for all other purposes.
137 The @dfn{RTL template} (@pxref{RTL Template}) is a vector of incomplete
138 RTL expressions which show what the instruction should look like. It is
139 incomplete because it may contain @code{match_operand},
140 @code{match_operator}, and @code{match_dup} expressions that stand for
141 operands of the instruction.
143 If the vector has only one element, that element is the template for the
144 instruction pattern. If the vector has multiple elements, then the
145 instruction pattern is a @code{parallel} expression containing the
149 @cindex pattern conditions
150 @cindex conditions, in patterns
151 A condition. This is a string which contains a C expression that is
152 the final test to decide whether an insn body matches this pattern.
154 @cindex named patterns and conditions
155 For a named pattern, the condition (if present) may not depend on
156 the data in the insn being matched, but only the target-machine-type
157 flags. The compiler needs to test these conditions during
158 initialization in order to learn exactly which named instructions are
159 available in a particular run.
162 For nameless patterns, the condition is applied only when matching an
163 individual insn, and only after the insn has matched the pattern's
164 recognition template. The insn's operands may be found in the vector
165 @code{operands}. For an insn where the condition has once matched, it
166 can't be used to control register allocation, for example by excluding
167 certain hard registers or hard register combinations.
170 The @dfn{output template}: a string that says how to output matching
171 insns as assembler code. @samp{%} in this string specifies where
172 to substitute the value of an operand. @xref{Output Template}.
174 When simple substitution isn't general enough, you can specify a piece
175 of C code to compute the output. @xref{Output Statement}.
178 Optionally, a vector containing the values of attributes for insns matching
179 this pattern. @xref{Insn Attributes}.
183 @section Example of @code{define_insn}
184 @cindex @code{define_insn} example
186 Here is an actual example of an instruction pattern, for the 68000/68020.
191 (match_operand:SI 0 "general_operand" "rm"))]
195 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
197 return \"cmpl #0,%0\";
202 This can also be written using braced strings:
207 (match_operand:SI 0 "general_operand" "rm"))]
210 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
216 This is an instruction that sets the condition codes based on the value of
217 a general operand. It has no condition, so any insn whose RTL description
218 has the form shown may be handled according to this pattern. The name
219 @samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL generation
220 pass that, when it is necessary to test such a value, an insn to do so
221 can be constructed using this pattern.
223 The output control string is a piece of C code which chooses which
224 output template to return based on the kind of operand and the specific
225 type of CPU for which code is being generated.
227 @samp{"rm"} is an operand constraint. Its meaning is explained below.
230 @section RTL Template
231 @cindex RTL insn template
232 @cindex generating insns
233 @cindex insns, generating
234 @cindex recognizing insns
235 @cindex insns, recognizing
237 The RTL template is used to define which insns match the particular pattern
238 and how to find their operands. For named patterns, the RTL template also
239 says how to construct an insn from specified operands.
241 Construction involves substituting specified operands into a copy of the
242 template. Matching involves determining the values that serve as the
243 operands in the insn being matched. Both of these activities are
244 controlled by special expression types that direct matching and
245 substitution of the operands.
248 @findex match_operand
249 @item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint})
250 This expression is a placeholder for operand number @var{n} of
251 the insn. When constructing an insn, operand number @var{n}
252 will be substituted at this point. When matching an insn, whatever
253 appears at this position in the insn will be taken as operand
254 number @var{n}; but it must satisfy @var{predicate} or this instruction
255 pattern will not match at all.
257 Operand numbers must be chosen consecutively counting from zero in
258 each instruction pattern. There may be only one @code{match_operand}
259 expression in the pattern for each operand number. Usually operands
260 are numbered in the order of appearance in @code{match_operand}
261 expressions. In the case of a @code{define_expand}, any operand numbers
262 used only in @code{match_dup} expressions have higher values than all
263 other operand numbers.
265 @var{predicate} is a string that is the name of a function that
266 accepts two arguments, an expression and a machine mode.
267 @xref{Predicates}. During matching, the function will be called with
268 the putative operand as the expression and @var{m} as the mode
269 argument (if @var{m} is not specified, @code{VOIDmode} will be used,
270 which normally causes @var{predicate} to accept any mode). If it
271 returns zero, this instruction pattern fails to match.
272 @var{predicate} may be an empty string; then it means no test is to be
273 done on the operand, so anything which occurs in this position is
276 Most of the time, @var{predicate} will reject modes other than @var{m}---but
277 not always. For example, the predicate @code{address_operand} uses
278 @var{m} as the mode of memory ref that the address should be valid for.
279 Many predicates accept @code{const_int} nodes even though their mode is
282 @var{constraint} controls reloading and the choice of the best register
283 class to use for a value, as explained later (@pxref{Constraints}).
284 If the constraint would be an empty string, it can be omitted.
286 People are often unclear on the difference between the constraint and the
287 predicate. The predicate helps decide whether a given insn matches the
288 pattern. The constraint plays no role in this decision; instead, it
289 controls various decisions in the case of an insn which does match.
291 @findex match_scratch
292 @item (match_scratch:@var{m} @var{n} @var{constraint})
293 This expression is also a placeholder for operand number @var{n}
294 and indicates that operand must be a @code{scratch} or @code{reg}
297 When matching patterns, this is equivalent to
300 (match_operand:@var{m} @var{n} "scratch_operand" @var{pred})
303 but, when generating RTL, it produces a (@code{scratch}:@var{m})
306 If the last few expressions in a @code{parallel} are @code{clobber}
307 expressions whose operands are either a hard register or
308 @code{match_scratch}, the combiner can add or delete them when
309 necessary. @xref{Side Effects}.
312 @item (match_dup @var{n})
313 This expression is also a placeholder for operand number @var{n}.
314 It is used when the operand needs to appear more than once in the
317 In construction, @code{match_dup} acts just like @code{match_operand}:
318 the operand is substituted into the insn being constructed. But in
319 matching, @code{match_dup} behaves differently. It assumes that operand
320 number @var{n} has already been determined by a @code{match_operand}
321 appearing earlier in the recognition template, and it matches only an
322 identical-looking expression.
324 Note that @code{match_dup} should not be used to tell the compiler that
325 a particular register is being used for two operands (example:
326 @code{add} that adds one register to another; the second register is
327 both an input operand and the output operand). Use a matching
328 constraint (@pxref{Simple Constraints}) for those. @code{match_dup} is for the cases where one
329 operand is used in two places in the template, such as an instruction
330 that computes both a quotient and a remainder, where the opcode takes
331 two input operands but the RTL template has to refer to each of those
332 twice; once for the quotient pattern and once for the remainder pattern.
334 @findex match_operator
335 @item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}])
336 This pattern is a kind of placeholder for a variable RTL expression
339 When constructing an insn, it stands for an RTL expression whose
340 expression code is taken from that of operand @var{n}, and whose
341 operands are constructed from the patterns @var{operands}.
343 When matching an expression, it matches an expression if the function
344 @var{predicate} returns nonzero on that expression @emph{and} the
345 patterns @var{operands} match the operands of the expression.
347 Suppose that the function @code{commutative_operator} is defined as
348 follows, to match any expression whose operator is one of the
349 commutative arithmetic operators of RTL and whose mode is @var{mode}:
353 commutative_integer_operator (x, mode)
355 enum machine_mode mode;
357 enum rtx_code code = GET_CODE (x);
358 if (GET_MODE (x) != mode)
360 return (GET_RTX_CLASS (code) == RTX_COMM_ARITH
361 || code == EQ || code == NE);
365 Then the following pattern will match any RTL expression consisting
366 of a commutative operator applied to two general operands:
369 (match_operator:SI 3 "commutative_operator"
370 [(match_operand:SI 1 "general_operand" "g")
371 (match_operand:SI 2 "general_operand" "g")])
374 Here the vector @code{[@var{operands}@dots{}]} contains two patterns
375 because the expressions to be matched all contain two operands.
377 When this pattern does match, the two operands of the commutative
378 operator are recorded as operands 1 and 2 of the insn. (This is done
379 by the two instances of @code{match_operand}.) Operand 3 of the insn
380 will be the entire commutative expression: use @code{GET_CODE
381 (operands[3])} to see which commutative operator was used.
383 The machine mode @var{m} of @code{match_operator} works like that of
384 @code{match_operand}: it is passed as the second argument to the
385 predicate function, and that function is solely responsible for
386 deciding whether the expression to be matched ``has'' that mode.
388 When constructing an insn, argument 3 of the gen-function will specify
389 the operation (i.e.@: the expression code) for the expression to be
390 made. It should be an RTL expression, whose expression code is copied
391 into a new expression whose operands are arguments 1 and 2 of the
392 gen-function. The subexpressions of argument 3 are not used;
393 only its expression code matters.
395 When @code{match_operator} is used in a pattern for matching an insn,
396 it usually best if the operand number of the @code{match_operator}
397 is higher than that of the actual operands of the insn. This improves
398 register allocation because the register allocator often looks at
399 operands 1 and 2 of insns to see if it can do register tying.
401 There is no way to specify constraints in @code{match_operator}. The
402 operand of the insn which corresponds to the @code{match_operator}
403 never has any constraints because it is never reloaded as a whole.
404 However, if parts of its @var{operands} are matched by
405 @code{match_operand} patterns, those parts may have constraints of
409 @item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}])
410 Like @code{match_dup}, except that it applies to operators instead of
411 operands. When constructing an insn, operand number @var{n} will be
412 substituted at this point. But in matching, @code{match_op_dup} behaves
413 differently. It assumes that operand number @var{n} has already been
414 determined by a @code{match_operator} appearing earlier in the
415 recognition template, and it matches only an identical-looking
418 @findex match_parallel
419 @item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}])
420 This pattern is a placeholder for an insn that consists of a
421 @code{parallel} expression with a variable number of elements. This
422 expression should only appear at the top level of an insn pattern.
424 When constructing an insn, operand number @var{n} will be substituted at
425 this point. When matching an insn, it matches if the body of the insn
426 is a @code{parallel} expression with at least as many elements as the
427 vector of @var{subpat} expressions in the @code{match_parallel}, if each
428 @var{subpat} matches the corresponding element of the @code{parallel},
429 @emph{and} the function @var{predicate} returns nonzero on the
430 @code{parallel} that is the body of the insn. It is the responsibility
431 of the predicate to validate elements of the @code{parallel} beyond
432 those listed in the @code{match_parallel}.
434 A typical use of @code{match_parallel} is to match load and store
435 multiple expressions, which can contain a variable number of elements
436 in a @code{parallel}. For example,
440 [(match_parallel 0 "load_multiple_operation"
441 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
442 (match_operand:SI 2 "memory_operand" "m"))
444 (clobber (reg:SI 179))])]
449 This example comes from @file{a29k.md}. The function
450 @code{load_multiple_operation} is defined in @file{a29k.c} and checks
451 that subsequent elements in the @code{parallel} are the same as the
452 @code{set} in the pattern, except that they are referencing subsequent
453 registers and memory locations.
455 An insn that matches this pattern might look like:
459 [(set (reg:SI 20) (mem:SI (reg:SI 100)))
461 (clobber (reg:SI 179))
463 (mem:SI (plus:SI (reg:SI 100)
466 (mem:SI (plus:SI (reg:SI 100)
470 @findex match_par_dup
471 @item (match_par_dup @var{n} [@var{subpat}@dots{}])
472 Like @code{match_op_dup}, but for @code{match_parallel} instead of
473 @code{match_operator}.
477 @node Output Template
478 @section Output Templates and Operand Substitution
479 @cindex output templates
480 @cindex operand substitution
482 @cindex @samp{%} in template
484 The @dfn{output template} is a string which specifies how to output the
485 assembler code for an instruction pattern. Most of the template is a
486 fixed string which is output literally. The character @samp{%} is used
487 to specify where to substitute an operand; it can also be used to
488 identify places where different variants of the assembler require
491 In the simplest case, a @samp{%} followed by a digit @var{n} says to output
492 operand @var{n} at that point in the string.
494 @samp{%} followed by a letter and a digit says to output an operand in an
495 alternate fashion. Four letters have standard, built-in meanings described
496 below. The machine description macro @code{PRINT_OPERAND} can define
497 additional letters with nonstandard meanings.
499 @samp{%c@var{digit}} can be used to substitute an operand that is a
500 constant value without the syntax that normally indicates an immediate
503 @samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of
504 the constant is negated before printing.
506 @samp{%a@var{digit}} can be used to substitute an operand as if it were a
507 memory reference, with the actual operand treated as the address. This may
508 be useful when outputting a ``load address'' instruction, because often the
509 assembler syntax for such an instruction requires you to write the operand
510 as if it were a memory reference.
512 @samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump
515 @samp{%=} outputs a number which is unique to each instruction in the
516 entire compilation. This is useful for making local labels to be
517 referred to more than once in a single template that generates multiple
518 assembler instructions.
520 @samp{%} followed by a punctuation character specifies a substitution that
521 does not use an operand. Only one case is standard: @samp{%%} outputs a
522 @samp{%} into the assembler code. Other nonstandard cases can be
523 defined in the @code{PRINT_OPERAND} macro. You must also define
524 which punctuation characters are valid with the
525 @code{PRINT_OPERAND_PUNCT_VALID_P} macro.
529 The template may generate multiple assembler instructions. Write the text
530 for the instructions, with @samp{\;} between them.
532 @cindex matching operands
533 When the RTL contains two operands which are required by constraint to match
534 each other, the output template must refer only to the lower-numbered operand.
535 Matching operands are not always identical, and the rest of the compiler
536 arranges to put the proper RTL expression for printing into the lower-numbered
539 One use of nonstandard letters or punctuation following @samp{%} is to
540 distinguish between different assembler languages for the same machine; for
541 example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax
542 requires periods in most opcode names, while MIT syntax does not. For
543 example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola
544 syntax. The same file of patterns is used for both kinds of output syntax,
545 but the character sequence @samp{%.} is used in each place where Motorola
546 syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax
547 defines the sequence to output a period; the macro for MIT syntax defines
550 @cindex @code{#} in template
551 As a special case, a template consisting of the single character @code{#}
552 instructs the compiler to first split the insn, and then output the
553 resulting instructions separately. This helps eliminate redundancy in the
554 output templates. If you have a @code{define_insn} that needs to emit
555 multiple assembler instructions, and there is a matching @code{define_split}
556 already defined, then you can simply use @code{#} as the output template
557 instead of writing an output template that emits the multiple assembler
560 If the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct
561 of the form @samp{@{option0|option1|option2@}} in the templates. These
562 describe multiple variants of assembler language syntax.
563 @xref{Instruction Output}.
565 @node Output Statement
566 @section C Statements for Assembler Output
567 @cindex output statements
568 @cindex C statements for assembler output
569 @cindex generating assembler output
571 Often a single fixed template string cannot produce correct and efficient
572 assembler code for all the cases that are recognized by a single
573 instruction pattern. For example, the opcodes may depend on the kinds of
574 operands; or some unfortunate combinations of operands may require extra
575 machine instructions.
577 If the output control string starts with a @samp{@@}, then it is actually
578 a series of templates, each on a separate line. (Blank lines and
579 leading spaces and tabs are ignored.) The templates correspond to the
580 pattern's constraint alternatives (@pxref{Multi-Alternative}). For example,
581 if a target machine has a two-address add instruction @samp{addr} to add
582 into a register and another @samp{addm} to add a register to memory, you
583 might write this pattern:
586 (define_insn "addsi3"
587 [(set (match_operand:SI 0 "general_operand" "=r,m")
588 (plus:SI (match_operand:SI 1 "general_operand" "0,0")
589 (match_operand:SI 2 "general_operand" "g,r")))]
596 @cindex @code{*} in template
597 @cindex asterisk in template
598 If the output control string starts with a @samp{*}, then it is not an
599 output template but rather a piece of C program that should compute a
600 template. It should execute a @code{return} statement to return the
601 template-string you want. Most such templates use C string literals, which
602 require doublequote characters to delimit them. To include these
603 doublequote characters in the string, prefix each one with @samp{\}.
605 If the output control string is written as a brace block instead of a
606 double-quoted string, it is automatically assumed to be C code. In that
607 case, it is not necessary to put in a leading asterisk, or to escape the
608 doublequotes surrounding C string literals.
610 The operands may be found in the array @code{operands}, whose C data type
613 It is very common to select different ways of generating assembler code
614 based on whether an immediate operand is within a certain range. Be
615 careful when doing this, because the result of @code{INTVAL} is an
616 integer on the host machine. If the host machine has more bits in an
617 @code{int} than the target machine has in the mode in which the constant
618 will be used, then some of the bits you get from @code{INTVAL} will be
619 superfluous. For proper results, you must carefully disregard the
620 values of those bits.
622 @findex output_asm_insn
623 It is possible to output an assembler instruction and then go on to output
624 or compute more of them, using the subroutine @code{output_asm_insn}. This
625 receives two arguments: a template-string and a vector of operands. The
626 vector may be @code{operands}, or it may be another array of @code{rtx}
627 that you declare locally and initialize yourself.
629 @findex which_alternative
630 When an insn pattern has multiple alternatives in its constraints, often
631 the appearance of the assembler code is determined mostly by which alternative
632 was matched. When this is so, the C code can test the variable
633 @code{which_alternative}, which is the ordinal number of the alternative
634 that was actually satisfied (0 for the first, 1 for the second alternative,
637 For example, suppose there are two opcodes for storing zero, @samp{clrreg}
638 for registers and @samp{clrmem} for memory locations. Here is how
639 a pattern could use @code{which_alternative} to choose between them:
643 [(set (match_operand:SI 0 "general_operand" "=r,m")
647 return (which_alternative == 0
648 ? "clrreg %0" : "clrmem %0");
652 The example above, where the assembler code to generate was
653 @emph{solely} determined by the alternative, could also have been specified
654 as follows, having the output control string start with a @samp{@@}:
659 [(set (match_operand:SI 0 "general_operand" "=r,m")
671 @cindex operand predicates
672 @cindex operator predicates
674 A predicate determines whether a @code{match_operand} or
675 @code{match_operator} expression matches, and therefore whether the
676 surrounding instruction pattern will be used for that combination of
677 operands. GCC has a number of machine-independent predicates, and you
678 can define machine-specific predicates as needed. By convention,
679 predicates used with @code{match_operand} have names that end in
680 @samp{_operand}, and those used with @code{match_operator} have names
681 that end in @samp{_operator}.
683 All predicates are Boolean functions (in the mathematical sense) of
684 two arguments: the RTL expression that is being considered at that
685 position in the instruction pattern, and the machine mode that the
686 @code{match_operand} or @code{match_operator} specifies. In this
687 section, the first argument is called @var{op} and the second argument
688 @var{mode}. Predicates can be called from C as ordinary two-argument
689 functions; this can be useful in output templates or other
690 machine-specific code.
692 Operand predicates can allow operands that are not actually acceptable
693 to the hardware, as long as the constraints give reload the ability to
694 fix them up (@pxref{Constraints}). However, GCC will usually generate
695 better code if the predicates specify the requirements of the machine
696 instructions as closely as possible. Reload cannot fix up operands
697 that must be constants (``immediate operands''); you must use a
698 predicate that allows only constants, or else enforce the requirement
699 in the extra condition.
701 @cindex predicates and machine modes
702 @cindex normal predicates
703 @cindex special predicates
704 Most predicates handle their @var{mode} argument in a uniform manner.
705 If @var{mode} is @code{VOIDmode} (unspecified), then @var{op} can have
706 any mode. If @var{mode} is anything else, then @var{op} must have the
707 same mode, unless @var{op} is a @code{CONST_INT} or integer
708 @code{CONST_DOUBLE}. These RTL expressions always have
709 @code{VOIDmode}, so it would be counterproductive to check that their
710 mode matches. Instead, predicates that accept @code{CONST_INT} and/or
711 integer @code{CONST_DOUBLE} check that the value stored in the
712 constant will fit in the requested mode.
714 Predicates with this behavior are called @dfn{normal}.
715 @command{genrecog} can optimize the instruction recognizer based on
716 knowledge of how normal predicates treat modes. It can also diagnose
717 certain kinds of common errors in the use of normal predicates; for
718 instance, it is almost always an error to use a normal predicate
719 without specifying a mode.
721 Predicates that do something different with their @var{mode} argument
722 are called @dfn{special}. The generic predicates
723 @code{address_operand} and @code{pmode_register_operand} are special
724 predicates. @command{genrecog} does not do any optimizations or
725 diagnosis when special predicates are used.
728 * Machine-Independent Predicates:: Predicates available to all back ends.
729 * Defining Predicates:: How to write machine-specific predicate
733 @node Machine-Independent Predicates
734 @subsection Machine-Independent Predicates
735 @cindex machine-independent predicates
736 @cindex generic predicates
738 These are the generic predicates available to all back ends. They are
739 defined in @file{recog.c}. The first category of predicates allow
740 only constant, or @dfn{immediate}, operands.
742 @defun immediate_operand
743 This predicate allows any sort of constant that fits in @var{mode}.
744 It is an appropriate choice for instructions that take operands that
748 @defun const_int_operand
749 This predicate allows any @code{CONST_INT} expression that fits in
750 @var{mode}. It is an appropriate choice for an immediate operand that
751 does not allow a symbol or label.
754 @defun const_double_operand
755 This predicate accepts any @code{CONST_DOUBLE} expression that has
756 exactly @var{mode}. If @var{mode} is @code{VOIDmode}, it will also
757 accept @code{CONST_INT}. It is intended for immediate floating point
762 The second category of predicates allow only some kind of machine
765 @defun register_operand
766 This predicate allows any @code{REG} or @code{SUBREG} expression that
767 is valid for @var{mode}. It is often suitable for arithmetic
768 instruction operands on a RISC machine.
771 @defun pmode_register_operand
772 This is a slight variant on @code{register_operand} which works around
773 a limitation in the machine-description reader.
776 (match_operand @var{n} "pmode_register_operand" @var{constraint})
783 (match_operand:P @var{n} "register_operand" @var{constraint})
787 would mean, if the machine-description reader accepted @samp{:P}
788 mode suffixes. Unfortunately, it cannot, because @code{Pmode} is an
789 alias for some other mode, and might vary with machine-specific
790 options. @xref{Misc}.
793 @defun scratch_operand
794 This predicate allows hard registers and @code{SCRATCH} expressions,
795 but not pseudo-registers. It is used internally by @code{match_scratch};
796 it should not be used directly.
800 The third category of predicates allow only some kind of memory reference.
802 @defun memory_operand
803 This predicate allows any valid reference to a quantity of mode
804 @var{mode} in memory, as determined by the weak form of
805 @code{GO_IF_LEGITIMATE_ADDRESS} (@pxref{Addressing Modes}).
808 @defun address_operand
809 This predicate is a little unusual; it allows any operand that is a
810 valid expression for the @emph{address} of a quantity of mode
811 @var{mode}, again determined by the weak form of
812 @code{GO_IF_LEGITIMATE_ADDRESS}. To first order, if
813 @samp{@w{(mem:@var{mode} (@var{exp}))}} is acceptable to
814 @code{memory_operand}, then @var{exp} is acceptable to
815 @code{address_operand}. Note that @var{exp} does not necessarily have
819 @defun indirect_operand
820 This is a stricter form of @code{memory_operand} which allows only
821 memory references with a @code{general_operand} as the address
822 expression. New uses of this predicate are discouraged, because
823 @code{general_operand} is very permissive, so it's hard to tell what
824 an @code{indirect_operand} does or does not allow. If a target has
825 different requirements for memory operands for different instructions,
826 it is better to define target-specific predicates which enforce the
827 hardware's requirements explicitly.
831 This predicate allows a memory reference suitable for pushing a value
832 onto the stack. This will be a @code{MEM} which refers to
833 @code{stack_pointer_rtx}, with a side-effect in its address expression
834 (@pxref{Incdec}); which one is determined by the
835 @code{STACK_PUSH_CODE} macro (@pxref{Frame Layout}).
839 This predicate allows a memory reference suitable for popping a value
840 off the stack. Again, this will be a @code{MEM} referring to
841 @code{stack_pointer_rtx}, with a side-effect in its address
842 expression. However, this time @code{STACK_POP_CODE} is expected.
846 The fourth category of predicates allow some combination of the above
849 @defun nonmemory_operand
850 This predicate allows any immediate or register operand valid for @var{mode}.
853 @defun nonimmediate_operand
854 This predicate allows any register or memory operand valid for @var{mode}.
857 @defun general_operand
858 This predicate allows any immediate, register, or memory operand
859 valid for @var{mode}.
863 Finally, there are two generic operator predicates.
865 @defun comparison_operator
866 This predicate matches any expression which performs an arithmetic
867 comparison in @var{mode}; that is, @code{COMPARISON_P} is true for the
871 @defun ordered_comparison_operator
872 This predicate matches any expression which performs an arithmetic
873 comparison in @var{mode} and whose expression code is valid for integer
874 modes; that is, the expression code will be one of @code{eq}, @code{ne},
875 @code{lt}, @code{ltu}, @code{le}, @code{leu}, @code{gt}, @code{gtu},
876 @code{ge}, @code{geu}.
879 @node Defining Predicates
880 @subsection Defining Machine-Specific Predicates
881 @cindex defining predicates
882 @findex define_predicate
883 @findex define_special_predicate
885 Many machines have requirements for their operands that cannot be
886 expressed precisely using the generic predicates. You can define
887 additional predicates using @code{define_predicate} and
888 @code{define_special_predicate} expressions. These expressions have
893 The name of the predicate, as it will be referred to in
894 @code{match_operand} or @code{match_operator} expressions.
897 An RTL expression which evaluates to true if the predicate allows the
898 operand @var{op}, false if it does not. This expression can only use
899 the following RTL codes:
903 When written inside a predicate expression, a @code{MATCH_OPERAND}
904 expression evaluates to true if the predicate it names would allow
905 @var{op}. The operand number and constraint are ignored. Due to
906 limitations in @command{genrecog}, you can only refer to generic
907 predicates and predicates that have already been defined.
910 This expression evaluates to true if @var{op} or a specified
911 subexpression of @var{op} has one of a given list of RTX codes.
913 The first operand of this expression is a string constant containing a
914 comma-separated list of RTX code names (in lower case). These are the
915 codes for which the @code{MATCH_CODE} will be true.
917 The second operand is a string constant which indicates what
918 subexpression of @var{op} to examine. If it is absent or the empty
919 string, @var{op} itself is examined. Otherwise, the string constant
920 must be a sequence of digits and/or lowercase letters. Each character
921 indicates a subexpression to extract from the current expression; for
922 the first character this is @var{op}, for the second and subsequent
923 characters it is the result of the previous character. A digit
924 @var{n} extracts @samp{@w{XEXP (@var{e}, @var{n})}}; a letter @var{l}
925 extracts @samp{@w{XVECEXP (@var{e}, 0, @var{n})}} where @var{n} is the
926 alphabetic ordinal of @var{l} (0 for `a', 1 for 'b', and so on). The
927 @code{MATCH_CODE} then examines the RTX code of the subexpression
928 extracted by the complete string. It is not possible to extract
929 components of an @code{rtvec} that is not at position 0 within its RTX
933 This expression has one operand, a string constant containing a C
934 expression. The predicate's arguments, @var{op} and @var{mode}, are
935 available with those names in the C expression. The @code{MATCH_TEST}
936 evaluates to true if the C expression evaluates to a nonzero value.
937 @code{MATCH_TEST} expressions must not have side effects.
943 The basic @samp{MATCH_} expressions can be combined using these
944 logical operators, which have the semantics of the C operators
945 @samp{&&}, @samp{||}, @samp{!}, and @samp{@w{? :}} respectively. As
946 in Common Lisp, you may give an @code{AND} or @code{IOR} expression an
947 arbitrary number of arguments; this has exactly the same effect as
948 writing a chain of two-argument @code{AND} or @code{IOR} expressions.
952 An optional block of C code, which should execute
953 @samp{@w{return true}} if the predicate is found to match and
954 @samp{@w{return false}} if it does not. It must not have any side
955 effects. The predicate arguments, @var{op} and @var{mode}, are
956 available with those names.
958 If a code block is present in a predicate definition, then the RTL
959 expression must evaluate to true @emph{and} the code block must
960 execute @samp{@w{return true}} for the predicate to allow the operand.
961 The RTL expression is evaluated first; do not re-check anything in the
962 code block that was checked in the RTL expression.
965 The program @command{genrecog} scans @code{define_predicate} and
966 @code{define_special_predicate} expressions to determine which RTX
967 codes are possibly allowed. You should always make this explicit in
968 the RTL predicate expression, using @code{MATCH_OPERAND} and
971 Here is an example of a simple predicate definition, from the IA64
976 ;; @r{True if @var{op} is a @code{SYMBOL_REF} which refers to the sdata section.}
977 (define_predicate "small_addr_symbolic_operand"
978 (and (match_code "symbol_ref")
979 (match_test "SYMBOL_REF_SMALL_ADDR_P (op)")))
984 And here is another, showing the use of the C block.
988 ;; @r{True if @var{op} is a register operand that is (or could be) a GR reg.}
989 (define_predicate "gr_register_operand"
990 (match_operand 0 "register_operand")
993 if (GET_CODE (op) == SUBREG)
994 op = SUBREG_REG (op);
997 return (regno >= FIRST_PSEUDO_REGISTER || GENERAL_REGNO_P (regno));
1002 Predicates written with @code{define_predicate} automatically include
1003 a test that @var{mode} is @code{VOIDmode}, or @var{op} has the same
1004 mode as @var{mode}, or @var{op} is a @code{CONST_INT} or
1005 @code{CONST_DOUBLE}. They do @emph{not} check specifically for
1006 integer @code{CONST_DOUBLE}, nor do they test that the value of either
1007 kind of constant fits in the requested mode. This is because
1008 target-specific predicates that take constants usually have to do more
1009 stringent value checks anyway. If you need the exact same treatment
1010 of @code{CONST_INT} or @code{CONST_DOUBLE} that the generic predicates
1011 provide, use a @code{MATCH_OPERAND} subexpression to call
1012 @code{const_int_operand}, @code{const_double_operand}, or
1013 @code{immediate_operand}.
1015 Predicates written with @code{define_special_predicate} do not get any
1016 automatic mode checks, and are treated as having special mode handling
1017 by @command{genrecog}.
1019 The program @command{genpreds} is responsible for generating code to
1020 test predicates. It also writes a header file containing function
1021 declarations for all machine-specific predicates. It is not necessary
1022 to declare these predicates in @file{@var{cpu}-protos.h}.
1025 @c Most of this node appears by itself (in a different place) even
1026 @c when the INTERNALS flag is clear. Passages that require the internals
1027 @c manual's context are conditionalized to appear only in the internals manual.
1030 @section Operand Constraints
1031 @cindex operand constraints
1034 Each @code{match_operand} in an instruction pattern can specify
1035 constraints for the operands allowed. The constraints allow you to
1036 fine-tune matching within the set of operands allowed by the
1042 @section Constraints for @code{asm} Operands
1043 @cindex operand constraints, @code{asm}
1044 @cindex constraints, @code{asm}
1045 @cindex @code{asm} constraints
1047 Here are specific details on what constraint letters you can use with
1048 @code{asm} operands.
1050 Constraints can say whether
1051 an operand may be in a register, and which kinds of register; whether the
1052 operand can be a memory reference, and which kinds of address; whether the
1053 operand may be an immediate constant, and which possible values it may
1054 have. Constraints can also require two operands to match.
1055 Side-effects aren't allowed in operands of inline @code{asm}, unless
1056 @samp{<} or @samp{>} constraints are used, because there is no guarantee
1057 that the side-effects will happen exactly once in an instruction that can update
1058 the addressing register.
1062 * Simple Constraints:: Basic use of constraints.
1063 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1064 * Class Preferences:: Constraints guide which hard register to put things in.
1065 * Modifiers:: More precise control over effects of constraints.
1066 * Disable Insn Alternatives:: Disable insn alternatives using the @code{enabled} attribute.
1067 * Machine Constraints:: Existing constraints for some particular machines.
1068 * Define Constraints:: How to define machine-specific constraints.
1069 * C Constraint Interface:: How to test constraints from C code.
1075 * Simple Constraints:: Basic use of constraints.
1076 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1077 * Modifiers:: More precise control over effects of constraints.
1078 * Machine Constraints:: Special constraints for some particular machines.
1082 @node Simple Constraints
1083 @subsection Simple Constraints
1084 @cindex simple constraints
1086 The simplest kind of constraint is a string full of letters, each of
1087 which describes one kind of operand that is permitted. Here are
1088 the letters that are allowed:
1092 Whitespace characters are ignored and can be inserted at any position
1093 except the first. This enables each alternative for different operands to
1094 be visually aligned in the machine description even if they have different
1095 number of constraints and modifiers.
1097 @cindex @samp{m} in constraint
1098 @cindex memory references in constraints
1100 A memory operand is allowed, with any kind of address that the machine
1101 supports in general.
1102 Note that the letter used for the general memory constraint can be
1103 re-defined by a back end using the @code{TARGET_MEM_CONSTRAINT} macro.
1105 @cindex offsettable address
1106 @cindex @samp{o} in constraint
1108 A memory operand is allowed, but only if the address is
1109 @dfn{offsettable}. This means that adding a small integer (actually,
1110 the width in bytes of the operand, as determined by its machine mode)
1111 may be added to the address and the result is also a valid memory
1114 @cindex autoincrement/decrement addressing
1115 For example, an address which is constant is offsettable; so is an
1116 address that is the sum of a register and a constant (as long as a
1117 slightly larger constant is also within the range of address-offsets
1118 supported by the machine); but an autoincrement or autodecrement
1119 address is not offsettable. More complicated indirect/indexed
1120 addresses may or may not be offsettable depending on the other
1121 addressing modes that the machine supports.
1123 Note that in an output operand which can be matched by another
1124 operand, the constraint letter @samp{o} is valid only when accompanied
1125 by both @samp{<} (if the target machine has predecrement addressing)
1126 and @samp{>} (if the target machine has preincrement addressing).
1128 @cindex @samp{V} in constraint
1130 A memory operand that is not offsettable. In other words, anything that
1131 would fit the @samp{m} constraint but not the @samp{o} constraint.
1133 @cindex @samp{<} in constraint
1135 A memory operand with autodecrement addressing (either predecrement or
1136 postdecrement) is allowed. In inline @code{asm} this constraint is only
1137 allowed if the operand is used exactly once in an instruction that can
1138 handle the side-effects. Not using an operand with @samp{<} in constraint
1139 string in the inline @code{asm} pattern at all or using it in multiple
1140 instructions isn't valid, because the side-effects wouldn't be performed
1141 or would be performed more than once. Furthermore, on some targets
1142 the operand with @samp{<} in constraint string must be accompanied by
1143 special instruction suffixes like @code{%U0} instruction suffix on PowerPC
1144 or @code{%P0} on IA-64.
1146 @cindex @samp{>} in constraint
1148 A memory operand with autoincrement addressing (either preincrement or
1149 postincrement) is allowed. In inline @code{asm} the same restrictions
1150 as for @samp{<} apply.
1152 @cindex @samp{r} in constraint
1153 @cindex registers in constraints
1155 A register operand is allowed provided that it is in a general
1158 @cindex constants in constraints
1159 @cindex @samp{i} in constraint
1161 An immediate integer operand (one with constant value) is allowed.
1162 This includes symbolic constants whose values will be known only at
1163 assembly time or later.
1165 @cindex @samp{n} in constraint
1167 An immediate integer operand with a known numeric value is allowed.
1168 Many systems cannot support assembly-time constants for operands less
1169 than a word wide. Constraints for these operands should use @samp{n}
1170 rather than @samp{i}.
1172 @cindex @samp{I} in constraint
1173 @item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P}
1174 Other letters in the range @samp{I} through @samp{P} may be defined in
1175 a machine-dependent fashion to permit immediate integer operands with
1176 explicit integer values in specified ranges. For example, on the
1177 68000, @samp{I} is defined to stand for the range of values 1 to 8.
1178 This is the range permitted as a shift count in the shift
1181 @cindex @samp{E} in constraint
1183 An immediate floating operand (expression code @code{const_double}) is
1184 allowed, but only if the target floating point format is the same as
1185 that of the host machine (on which the compiler is running).
1187 @cindex @samp{F} in constraint
1189 An immediate floating operand (expression code @code{const_double} or
1190 @code{const_vector}) is allowed.
1192 @cindex @samp{G} in constraint
1193 @cindex @samp{H} in constraint
1194 @item @samp{G}, @samp{H}
1195 @samp{G} and @samp{H} may be defined in a machine-dependent fashion to
1196 permit immediate floating operands in particular ranges of values.
1198 @cindex @samp{s} in constraint
1200 An immediate integer operand whose value is not an explicit integer is
1203 This might appear strange; if an insn allows a constant operand with a
1204 value not known at compile time, it certainly must allow any known
1205 value. So why use @samp{s} instead of @samp{i}? Sometimes it allows
1206 better code to be generated.
1208 For example, on the 68000 in a fullword instruction it is possible to
1209 use an immediate operand; but if the immediate value is between @minus{}128
1210 and 127, better code results from loading the value into a register and
1211 using the register. This is because the load into the register can be
1212 done with a @samp{moveq} instruction. We arrange for this to happen
1213 by defining the letter @samp{K} to mean ``any integer outside the
1214 range @minus{}128 to 127'', and then specifying @samp{Ks} in the operand
1217 @cindex @samp{g} in constraint
1219 Any register, memory or immediate integer operand is allowed, except for
1220 registers that are not general registers.
1222 @cindex @samp{X} in constraint
1225 Any operand whatsoever is allowed, even if it does not satisfy
1226 @code{general_operand}. This is normally used in the constraint of
1227 a @code{match_scratch} when certain alternatives will not actually
1228 require a scratch register.
1231 Any operand whatsoever is allowed.
1234 @cindex @samp{0} in constraint
1235 @cindex digits in constraint
1236 @item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9}
1237 An operand that matches the specified operand number is allowed. If a
1238 digit is used together with letters within the same alternative, the
1239 digit should come last.
1241 This number is allowed to be more than a single digit. If multiple
1242 digits are encountered consecutively, they are interpreted as a single
1243 decimal integer. There is scant chance for ambiguity, since to-date
1244 it has never been desirable that @samp{10} be interpreted as matching
1245 either operand 1 @emph{or} operand 0. Should this be desired, one
1246 can use multiple alternatives instead.
1248 @cindex matching constraint
1249 @cindex constraint, matching
1250 This is called a @dfn{matching constraint} and what it really means is
1251 that the assembler has only a single operand that fills two roles
1253 considered separate in the RTL insn. For example, an add insn has two
1254 input operands and one output operand in the RTL, but on most CISC
1257 which @code{asm} distinguishes. For example, an add instruction uses
1258 two input operands and an output operand, but on most CISC
1260 machines an add instruction really has only two operands, one of them an
1261 input-output operand:
1267 Matching constraints are used in these circumstances.
1268 More precisely, the two operands that match must include one input-only
1269 operand and one output-only operand. Moreover, the digit must be a
1270 smaller number than the number of the operand that uses it in the
1274 For operands to match in a particular case usually means that they
1275 are identical-looking RTL expressions. But in a few special cases
1276 specific kinds of dissimilarity are allowed. For example, @code{*x}
1277 as an input operand will match @code{*x++} as an output operand.
1278 For proper results in such cases, the output template should always
1279 use the output-operand's number when printing the operand.
1282 @cindex load address instruction
1283 @cindex push address instruction
1284 @cindex address constraints
1285 @cindex @samp{p} in constraint
1287 An operand that is a valid memory address is allowed. This is
1288 for ``load address'' and ``push address'' instructions.
1290 @findex address_operand
1291 @samp{p} in the constraint must be accompanied by @code{address_operand}
1292 as the predicate in the @code{match_operand}. This predicate interprets
1293 the mode specified in the @code{match_operand} as the mode of the memory
1294 reference for which the address would be valid.
1296 @cindex other register constraints
1297 @cindex extensible constraints
1298 @item @var{other-letters}
1299 Other letters can be defined in machine-dependent fashion to stand for
1300 particular classes of registers or other arbitrary operand types.
1301 @samp{d}, @samp{a} and @samp{f} are defined on the 68000/68020 to stand
1302 for data, address and floating point registers.
1306 In order to have valid assembler code, each operand must satisfy
1307 its constraint. But a failure to do so does not prevent the pattern
1308 from applying to an insn. Instead, it directs the compiler to modify
1309 the code so that the constraint will be satisfied. Usually this is
1310 done by copying an operand into a register.
1312 Contrast, therefore, the two instruction patterns that follow:
1316 [(set (match_operand:SI 0 "general_operand" "=r")
1317 (plus:SI (match_dup 0)
1318 (match_operand:SI 1 "general_operand" "r")))]
1324 which has two operands, one of which must appear in two places, and
1328 [(set (match_operand:SI 0 "general_operand" "=r")
1329 (plus:SI (match_operand:SI 1 "general_operand" "0")
1330 (match_operand:SI 2 "general_operand" "r")))]
1336 which has three operands, two of which are required by a constraint to be
1337 identical. If we are considering an insn of the form
1340 (insn @var{n} @var{prev} @var{next}
1342 (plus:SI (reg:SI 6) (reg:SI 109)))
1347 the first pattern would not apply at all, because this insn does not
1348 contain two identical subexpressions in the right place. The pattern would
1349 say, ``That does not look like an add instruction; try other patterns''.
1350 The second pattern would say, ``Yes, that's an add instruction, but there
1351 is something wrong with it''. It would direct the reload pass of the
1352 compiler to generate additional insns to make the constraint true. The
1353 results might look like this:
1356 (insn @var{n2} @var{prev} @var{n}
1357 (set (reg:SI 3) (reg:SI 6))
1360 (insn @var{n} @var{n2} @var{next}
1362 (plus:SI (reg:SI 3) (reg:SI 109)))
1366 It is up to you to make sure that each operand, in each pattern, has
1367 constraints that can handle any RTL expression that could be present for
1368 that operand. (When multiple alternatives are in use, each pattern must,
1369 for each possible combination of operand expressions, have at least one
1370 alternative which can handle that combination of operands.) The
1371 constraints don't need to @emph{allow} any possible operand---when this is
1372 the case, they do not constrain---but they must at least point the way to
1373 reloading any possible operand so that it will fit.
1377 If the constraint accepts whatever operands the predicate permits,
1378 there is no problem: reloading is never necessary for this operand.
1380 For example, an operand whose constraints permit everything except
1381 registers is safe provided its predicate rejects registers.
1383 An operand whose predicate accepts only constant values is safe
1384 provided its constraints include the letter @samp{i}. If any possible
1385 constant value is accepted, then nothing less than @samp{i} will do;
1386 if the predicate is more selective, then the constraints may also be
1390 Any operand expression can be reloaded by copying it into a register.
1391 So if an operand's constraints allow some kind of register, it is
1392 certain to be safe. It need not permit all classes of registers; the
1393 compiler knows how to copy a register into another register of the
1394 proper class in order to make an instruction valid.
1396 @cindex nonoffsettable memory reference
1397 @cindex memory reference, nonoffsettable
1399 A nonoffsettable memory reference can be reloaded by copying the
1400 address into a register. So if the constraint uses the letter
1401 @samp{o}, all memory references are taken care of.
1404 A constant operand can be reloaded by allocating space in memory to
1405 hold it as preinitialized data. Then the memory reference can be used
1406 in place of the constant. So if the constraint uses the letters
1407 @samp{o} or @samp{m}, constant operands are not a problem.
1410 If the constraint permits a constant and a pseudo register used in an insn
1411 was not allocated to a hard register and is equivalent to a constant,
1412 the register will be replaced with the constant. If the predicate does
1413 not permit a constant and the insn is re-recognized for some reason, the
1414 compiler will crash. Thus the predicate must always recognize any
1415 objects allowed by the constraint.
1418 If the operand's predicate can recognize registers, but the constraint does
1419 not permit them, it can make the compiler crash. When this operand happens
1420 to be a register, the reload pass will be stymied, because it does not know
1421 how to copy a register temporarily into memory.
1423 If the predicate accepts a unary operator, the constraint applies to the
1424 operand. For example, the MIPS processor at ISA level 3 supports an
1425 instruction which adds two registers in @code{SImode} to produce a
1426 @code{DImode} result, but only if the registers are correctly sign
1427 extended. This predicate for the input operands accepts a
1428 @code{sign_extend} of an @code{SImode} register. Write the constraint
1429 to indicate the type of register that is required for the operand of the
1433 @node Multi-Alternative
1434 @subsection Multiple Alternative Constraints
1435 @cindex multiple alternative constraints
1437 Sometimes a single instruction has multiple alternative sets of possible
1438 operands. For example, on the 68000, a logical-or instruction can combine
1439 register or an immediate value into memory, or it can combine any kind of
1440 operand into a register; but it cannot combine one memory location into
1443 These constraints are represented as multiple alternatives. An alternative
1444 can be described by a series of letters for each operand. The overall
1445 constraint for an operand is made from the letters for this operand
1446 from the first alternative, a comma, the letters for this operand from
1447 the second alternative, a comma, and so on until the last alternative.
1449 Here is how it is done for fullword logical-or on the 68000:
1452 (define_insn "iorsi3"
1453 [(set (match_operand:SI 0 "general_operand" "=m,d")
1454 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
1455 (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
1459 The first alternative has @samp{m} (memory) for operand 0, @samp{0} for
1460 operand 1 (meaning it must match operand 0), and @samp{dKs} for operand
1461 2. The second alternative has @samp{d} (data register) for operand 0,
1462 @samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and
1463 @samp{%} in the constraints apply to all the alternatives; their
1464 meaning is explained in the next section (@pxref{Class Preferences}).
1467 @c FIXME Is this ? and ! stuff of use in asm()? If not, hide unless INTERNAL
1468 If all the operands fit any one alternative, the instruction is valid.
1469 Otherwise, for each alternative, the compiler counts how many instructions
1470 must be added to copy the operands so that that alternative applies.
1471 The alternative requiring the least copying is chosen. If two alternatives
1472 need the same amount of copying, the one that comes first is chosen.
1473 These choices can be altered with the @samp{?} and @samp{!} characters:
1476 @cindex @samp{?} in constraint
1477 @cindex question mark
1479 Disparage slightly the alternative that the @samp{?} appears in,
1480 as a choice when no alternative applies exactly. The compiler regards
1481 this alternative as one unit more costly for each @samp{?} that appears
1484 @cindex @samp{!} in constraint
1485 @cindex exclamation point
1487 Disparage severely the alternative that the @samp{!} appears in.
1488 This alternative can still be used if it fits without reloading,
1489 but if reloading is needed, some other alternative will be used.
1493 When an insn pattern has multiple alternatives in its constraints, often
1494 the appearance of the assembler code is determined mostly by which
1495 alternative was matched. When this is so, the C code for writing the
1496 assembler code can use the variable @code{which_alternative}, which is
1497 the ordinal number of the alternative that was actually satisfied (0 for
1498 the first, 1 for the second alternative, etc.). @xref{Output Statement}.
1502 @node Class Preferences
1503 @subsection Register Class Preferences
1504 @cindex class preference constraints
1505 @cindex register class preference constraints
1507 @cindex voting between constraint alternatives
1508 The operand constraints have another function: they enable the compiler
1509 to decide which kind of hardware register a pseudo register is best
1510 allocated to. The compiler examines the constraints that apply to the
1511 insns that use the pseudo register, looking for the machine-dependent
1512 letters such as @samp{d} and @samp{a} that specify classes of registers.
1513 The pseudo register is put in whichever class gets the most ``votes''.
1514 The constraint letters @samp{g} and @samp{r} also vote: they vote in
1515 favor of a general register. The machine description says which registers
1516 are considered general.
1518 Of course, on some machines all registers are equivalent, and no register
1519 classes are defined. Then none of this complexity is relevant.
1523 @subsection Constraint Modifier Characters
1524 @cindex modifiers in constraints
1525 @cindex constraint modifier characters
1527 @c prevent bad page break with this line
1528 Here are constraint modifier characters.
1531 @cindex @samp{=} in constraint
1533 Means that this operand is write-only for this instruction: the previous
1534 value is discarded and replaced by output data.
1536 @cindex @samp{+} in constraint
1538 Means that this operand is both read and written by the instruction.
1540 When the compiler fixes up the operands to satisfy the constraints,
1541 it needs to know which operands are inputs to the instruction and
1542 which are outputs from it. @samp{=} identifies an output; @samp{+}
1543 identifies an operand that is both input and output; all other operands
1544 are assumed to be input only.
1546 If you specify @samp{=} or @samp{+} in a constraint, you put it in the
1547 first character of the constraint string.
1549 @cindex @samp{&} in constraint
1550 @cindex earlyclobber operand
1552 Means (in a particular alternative) that this operand is an
1553 @dfn{earlyclobber} operand, which is modified before the instruction is
1554 finished using the input operands. Therefore, this operand may not lie
1555 in a register that is used as an input operand or as part of any memory
1558 @samp{&} applies only to the alternative in which it is written. In
1559 constraints with multiple alternatives, sometimes one alternative
1560 requires @samp{&} while others do not. See, for example, the
1561 @samp{movdf} insn of the 68000.
1563 An input operand can be tied to an earlyclobber operand if its only
1564 use as an input occurs before the early result is written. Adding
1565 alternatives of this form often allows GCC to produce better code
1566 when only some of the inputs can be affected by the earlyclobber.
1567 See, for example, the @samp{mulsi3} insn of the ARM@.
1569 @samp{&} does not obviate the need to write @samp{=}.
1571 @cindex @samp{%} in constraint
1573 Declares the instruction to be commutative for this operand and the
1574 following operand. This means that the compiler may interchange the
1575 two operands if that is the cheapest way to make all operands fit the
1578 This is often used in patterns for addition instructions
1579 that really have only two operands: the result must go in one of the
1580 arguments. Here for example, is how the 68000 halfword-add
1581 instruction is defined:
1584 (define_insn "addhi3"
1585 [(set (match_operand:HI 0 "general_operand" "=m,r")
1586 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
1587 (match_operand:HI 2 "general_operand" "di,g")))]
1591 GCC can only handle one commutative pair in an asm; if you use more,
1592 the compiler may fail. Note that you need not use the modifier if
1593 the two alternatives are strictly identical; this would only waste
1594 time in the reload pass. The modifier is not operational after
1595 register allocation, so the result of @code{define_peephole2}
1596 and @code{define_split}s performed after reload cannot rely on
1597 @samp{%} to make the intended insn match.
1599 @cindex @samp{#} in constraint
1601 Says that all following characters, up to the next comma, are to be
1602 ignored as a constraint. They are significant only for choosing
1603 register preferences.
1605 @cindex @samp{*} in constraint
1607 Says that the following character should be ignored when choosing
1608 register preferences. @samp{*} has no effect on the meaning of the
1609 constraint as a constraint, and no effect on reloading.
1612 Here is an example: the 68000 has an instruction to sign-extend a
1613 halfword in a data register, and can also sign-extend a value by
1614 copying it into an address register. While either kind of register is
1615 acceptable, the constraints on an address-register destination are
1616 less strict, so it is best if register allocation makes an address
1617 register its goal. Therefore, @samp{*} is used so that the @samp{d}
1618 constraint letter (for data register) is ignored when computing
1619 register preferences.
1622 (define_insn "extendhisi2"
1623 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1625 (match_operand:HI 1 "general_operand" "0,g")))]
1631 @node Machine Constraints
1632 @subsection Constraints for Particular Machines
1633 @cindex machine specific constraints
1634 @cindex constraints, machine specific
1636 Whenever possible, you should use the general-purpose constraint letters
1637 in @code{asm} arguments, since they will convey meaning more readily to
1638 people reading your code. Failing that, use the constraint letters
1639 that usually have very similar meanings across architectures. The most
1640 commonly used constraints are @samp{m} and @samp{r} (for memory and
1641 general-purpose registers respectively; @pxref{Simple Constraints}), and
1642 @samp{I}, usually the letter indicating the most common
1643 immediate-constant format.
1645 Each architecture defines additional constraints. These constraints
1646 are used by the compiler itself for instruction generation, as well as
1647 for @code{asm} statements; therefore, some of the constraints are not
1648 particularly useful for @code{asm}. Here is a summary of some of the
1649 machine-dependent constraints available on some particular machines;
1650 it includes both constraints that are useful for @code{asm} and
1651 constraints that aren't. The compiler source file mentioned in the
1652 table heading for each architecture is the definitive reference for
1653 the meanings of that architecture's constraints.
1656 @item ARM family---@file{config/arm/arm.h}
1659 Floating-point register
1662 VFP floating-point register
1665 One of the floating-point constants 0.0, 0.5, 1.0, 2.0, 3.0, 4.0, 5.0
1669 Floating-point constant that would satisfy the constraint @samp{F} if it
1673 Integer that is valid as an immediate operand in a data processing
1674 instruction. That is, an integer in the range 0 to 255 rotated by a
1678 Integer in the range @minus{}4095 to 4095
1681 Integer that satisfies constraint @samp{I} when inverted (ones complement)
1684 Integer that satisfies constraint @samp{I} when negated (twos complement)
1687 Integer in the range 0 to 32
1690 A memory reference where the exact address is in a single register
1691 (`@samp{m}' is preferable for @code{asm} statements)
1694 An item in the constant pool
1697 A symbol in the text segment of the current file
1700 A memory reference suitable for VFP load/store insns (reg+constant offset)
1703 A memory reference suitable for iWMMXt load/store instructions.
1706 A memory reference suitable for the ARMv4 ldrsb instruction.
1709 @item AVR family---@file{config/avr/constraints.md}
1712 Registers from r0 to r15
1715 Registers from r16 to r23
1718 Registers from r16 to r31
1721 Registers from r24 to r31. These registers can be used in @samp{adiw} command
1724 Pointer register (r26--r31)
1727 Base pointer register (r28--r31)
1730 Stack pointer register (SPH:SPL)
1733 Temporary register r0
1736 Register pair X (r27:r26)
1739 Register pair Y (r29:r28)
1742 Register pair Z (r31:r30)
1745 Constant greater than @minus{}1, less than 64
1748 Constant greater than @minus{}64, less than 1
1757 Constant that fits in 8 bits
1760 Constant integer @minus{}1
1763 Constant integer 8, 16, or 24
1769 A floating point constant 0.0
1772 Integer constant in the range @minus{}6 @dots{} 5.
1775 A memory address based on Y or Z pointer with displacement.
1781 @item Epiphany---@file{config/epiphany/constraints.md}
1784 An unsigned 16-bit constant.
1787 An unsigned 5-bit constant.
1790 A signed 11-bit constant.
1793 A signed 11-bit constant added to @minus{}1.
1794 Can only match when the @option{-m1reg-@var{reg}} option is active.
1797 Left-shift of @minus{}1, i.e., a bit mask with a block of leading ones, the rest
1798 being a block of trailing zeroes.
1799 Can only match when the @option{-m1reg-@var{reg}} option is active.
1802 Right-shift of @minus{}1, i.e., a bit mask with a trailing block of ones, the
1803 rest being zeroes. Or to put it another way, one less than a power of two.
1804 Can only match when the @option{-m1reg-@var{reg}} option is active.
1807 Constant for arithmetic/logical operations.
1808 This is like @code{i}, except that for position independent code,
1809 no symbols / expressions needing relocations are allowed.
1812 Symbolic constant for call/jump instruction.
1815 The register class usable in short insns. This is a register class
1816 constraint, and can thus drive register allocation.
1817 This constraint won't match unless @option{-mprefer-short-insn-regs} is
1821 The the register class of registers that can be used to hold a
1822 sibcall call address. I.e., a caller-saved register.
1825 Core control register class.
1828 The register group usable in short insns.
1829 This constraint does not use a register class, so that it only
1830 passively matches suitable registers, and doesn't drive register allocation.
1834 Constant suitable for the addsi3_r pattern. This is a valid offset
1835 For byte, halfword, or word addressing.
1839 Matches the return address if it can be replaced with the link register.
1842 Matches the integer condition code register.
1845 Matches the return address if it is in a stack slot.
1848 Matches control register values to switch fp mode, which are encapsulated in
1849 @code{UNSPEC_FP_MODE}.
1852 @item Hewlett-Packard PA-RISC---@file{config/pa/pa.h}
1858 Floating point register
1861 Shift amount register
1864 Floating point register (deprecated)
1867 Upper floating point register (32-bit), floating point register (64-bit)
1873 Signed 11-bit integer constant
1876 Signed 14-bit integer constant
1879 Integer constant that can be deposited with a @code{zdepi} instruction
1882 Signed 5-bit integer constant
1888 Integer constant that can be loaded with a @code{ldil} instruction
1891 Integer constant whose value plus one is a power of 2
1894 Integer constant that can be used for @code{and} operations in @code{depi}
1895 and @code{extru} instructions
1904 Floating-point constant 0.0
1907 A @code{lo_sum} data-linkage-table memory operand
1910 A memory operand that can be used as the destination operand of an
1911 integer store instruction
1914 A scaled or unscaled indexed memory operand
1917 A memory operand for floating-point loads and stores
1920 A register indirect memory operand
1923 @item picoChip family---@file{picochip.h}
1929 Pointer register. A register which can be used to access memory without
1930 supplying an offset. Any other register can be used to access memory,
1931 but will need a constant offset. In the case of the offset being zero,
1932 it is more efficient to use a pointer register, since this reduces code
1936 A twin register. A register which may be paired with an adjacent
1937 register to create a 32-bit register.
1940 Any absolute memory address (e.g., symbolic constant, symbolic
1944 4-bit signed integer.
1947 4-bit unsigned integer.
1950 8-bit signed integer.
1953 Any constant whose absolute value is no greater than 4-bits.
1956 10-bit signed integer
1959 16-bit signed integer.
1963 @item PowerPC and IBM RS6000---@file{config/rs6000/rs6000.h}
1966 Address base register
1969 Floating point register (containing 64-bit value)
1972 Floating point register (containing 32-bit value)
1975 Altivec vector register
1978 VSX vector register to hold vector double data
1981 VSX vector register to hold vector float data
1984 VSX vector register to hold scalar float data
1990 @samp{MQ}, @samp{CTR}, or @samp{LINK} register
1999 @samp{LINK} register
2002 @samp{CR} register (condition register) number 0
2005 @samp{CR} register (condition register)
2008 @samp{XER[CA]} carry bit (part of the XER register)
2011 Signed 16-bit constant
2014 Unsigned 16-bit constant shifted left 16 bits (use @samp{L} instead for
2015 @code{SImode} constants)
2018 Unsigned 16-bit constant
2021 Signed 16-bit constant shifted left 16 bits
2024 Constant larger than 31
2033 Constant whose negation is a signed 16-bit constant
2036 Floating point constant that can be loaded into a register with one
2037 instruction per word
2040 Integer/Floating point constant that can be loaded into a register using
2045 Normally, @code{m} does not allow addresses that update the base register.
2046 If @samp{<} or @samp{>} constraint is also used, they are allowed and
2047 therefore on PowerPC targets in that case it is only safe
2048 to use @samp{m<>} in an @code{asm} statement if that @code{asm} statement
2049 accesses the operand exactly once. The @code{asm} statement must also
2050 use @samp{%U@var{<opno>}} as a placeholder for the ``update'' flag in the
2051 corresponding load or store instruction. For example:
2054 asm ("st%U0 %1,%0" : "=m<>" (mem) : "r" (val));
2060 asm ("st %1,%0" : "=m<>" (mem) : "r" (val));
2066 A ``stable'' memory operand; that is, one which does not include any
2067 automodification of the base register. This used to be useful when
2068 @samp{m} allowed automodification of the base register, but as those are now only
2069 allowed when @samp{<} or @samp{>} is used, @samp{es} is basically the same
2070 as @samp{m} without @samp{<} and @samp{>}.
2073 Memory operand that is an offset from a register (it is usually better
2074 to use @samp{m} or @samp{es} in @code{asm} statements)
2077 Memory operand that is an indexed or indirect from a register (it is
2078 usually better to use @samp{m} or @samp{es} in @code{asm} statements)
2084 Address operand that is an indexed or indirect from a register (@samp{p} is
2085 preferable for @code{asm} statements)
2088 Constant suitable as a 64-bit mask operand
2091 Constant suitable as a 32-bit mask operand
2094 System V Release 4 small data area reference
2097 AND masks that can be performed by two rldic@{l, r@} instructions
2100 Vector constant that does not require memory
2103 Vector constant that is all zeros.
2107 @item Intel 386---@file{config/i386/constraints.md}
2110 Legacy register---the eight integer registers available on all
2111 i386 processors (@code{a}, @code{b}, @code{c}, @code{d},
2112 @code{si}, @code{di}, @code{bp}, @code{sp}).
2115 Any register accessible as @code{@var{r}l}. In 32-bit mode, @code{a},
2116 @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.
2119 Any register accessible as @code{@var{r}h}: @code{a}, @code{b},
2120 @code{c}, and @code{d}.
2124 Any register that can be used as the index in a base+index memory
2125 access: that is, any general register except the stack pointer.
2129 The @code{a} register.
2132 The @code{b} register.
2135 The @code{c} register.
2138 The @code{d} register.
2141 The @code{si} register.
2144 The @code{di} register.
2147 The @code{a} and @code{d} registers. This class is used for instructions
2148 that return double word results in the @code{ax:dx} register pair. Single
2149 word values will be allocated either in @code{ax} or @code{dx}.
2150 For example on i386 the following implements @code{rdtsc}:
2153 unsigned long long rdtsc (void)
2155 unsigned long long tick;
2156 __asm__ __volatile__("rdtsc":"=A"(tick));
2161 This is not correct on x86_64 as it would allocate tick in either @code{ax}
2162 or @code{dx}. You have to use the following variant instead:
2165 unsigned long long rdtsc (void)
2167 unsigned int tickl, tickh;
2168 __asm__ __volatile__("rdtsc":"=a"(tickl),"=d"(tickh));
2169 return ((unsigned long long)tickh << 32)|tickl;
2175 Any 80387 floating-point (stack) register.
2178 Top of 80387 floating-point stack (@code{%st(0)}).
2181 Second from top of 80387 floating-point stack (@code{%st(1)}).
2190 First SSE register (@code{%xmm0}).
2194 Any SSE register, when SSE2 is enabled.
2197 Any SSE register, when SSE2 and inter-unit moves are enabled.
2200 Any MMX register, when inter-unit moves are enabled.
2204 Integer constant in the range 0 @dots{} 31, for 32-bit shifts.
2207 Integer constant in the range 0 @dots{} 63, for 64-bit shifts.
2210 Signed 8-bit integer constant.
2213 @code{0xFF} or @code{0xFFFF}, for andsi as a zero-extending move.
2216 0, 1, 2, or 3 (shifts for the @code{lea} instruction).
2219 Unsigned 8-bit integer constant (for @code{in} and @code{out}
2224 Integer constant in the range 0 @dots{} 127, for 128-bit shifts.
2228 Standard 80387 floating point constant.
2231 Standard SSE floating point constant.
2234 32-bit signed integer constant, or a symbolic reference known
2235 to fit that range (for immediate operands in sign-extending x86-64
2239 32-bit unsigned integer constant, or a symbolic reference known
2240 to fit that range (for immediate operands in zero-extending x86-64
2245 @item Intel IA-64---@file{config/ia64/ia64.h}
2248 General register @code{r0} to @code{r3} for @code{addl} instruction
2254 Predicate register (@samp{c} as in ``conditional'')
2257 Application register residing in M-unit
2260 Application register residing in I-unit
2263 Floating-point register
2266 Memory operand. If used together with @samp{<} or @samp{>},
2267 the operand can have postincrement and postdecrement which
2268 require printing with @samp{%Pn} on IA-64.
2271 Floating-point constant 0.0 or 1.0
2274 14-bit signed integer constant
2277 22-bit signed integer constant
2280 8-bit signed integer constant for logical instructions
2283 8-bit adjusted signed integer constant for compare pseudo-ops
2286 6-bit unsigned integer constant for shift counts
2289 9-bit signed integer constant for load and store postincrements
2295 0 or @minus{}1 for @code{dep} instruction
2298 Non-volatile memory for floating-point loads and stores
2301 Integer constant in the range 1 to 4 for @code{shladd} instruction
2304 Memory operand except postincrement and postdecrement. This is
2305 now roughly the same as @samp{m} when not used together with @samp{<}
2309 @item FRV---@file{config/frv/frv.h}
2312 Register in the class @code{ACC_REGS} (@code{acc0} to @code{acc7}).
2315 Register in the class @code{EVEN_ACC_REGS} (@code{acc0} to @code{acc7}).
2318 Register in the class @code{CC_REGS} (@code{fcc0} to @code{fcc3} and
2319 @code{icc0} to @code{icc3}).
2322 Register in the class @code{GPR_REGS} (@code{gr0} to @code{gr63}).
2325 Register in the class @code{EVEN_REGS} (@code{gr0} to @code{gr63}).
2326 Odd registers are excluded not in the class but through the use of a machine
2327 mode larger than 4 bytes.
2330 Register in the class @code{FPR_REGS} (@code{fr0} to @code{fr63}).
2333 Register in the class @code{FEVEN_REGS} (@code{fr0} to @code{fr63}).
2334 Odd registers are excluded not in the class but through the use of a machine
2335 mode larger than 4 bytes.
2338 Register in the class @code{LR_REG} (the @code{lr} register).
2341 Register in the class @code{QUAD_REGS} (@code{gr2} to @code{gr63}).
2342 Register numbers not divisible by 4 are excluded not in the class but through
2343 the use of a machine mode larger than 8 bytes.
2346 Register in the class @code{ICC_REGS} (@code{icc0} to @code{icc3}).
2349 Register in the class @code{FCC_REGS} (@code{fcc0} to @code{fcc3}).
2352 Register in the class @code{ICR_REGS} (@code{cc4} to @code{cc7}).
2355 Register in the class @code{FCR_REGS} (@code{cc0} to @code{cc3}).
2358 Register in the class @code{QUAD_FPR_REGS} (@code{fr0} to @code{fr63}).
2359 Register numbers not divisible by 4 are excluded not in the class but through
2360 the use of a machine mode larger than 8 bytes.
2363 Register in the class @code{SPR_REGS} (@code{lcr} and @code{lr}).
2366 Register in the class @code{QUAD_ACC_REGS} (@code{acc0} to @code{acc7}).
2369 Register in the class @code{ACCG_REGS} (@code{accg0} to @code{accg7}).
2372 Register in the class @code{CR_REGS} (@code{cc0} to @code{cc7}).
2375 Floating point constant zero
2378 6-bit signed integer constant
2381 10-bit signed integer constant
2384 16-bit signed integer constant
2387 16-bit unsigned integer constant
2390 12-bit signed integer constant that is negative---i.e.@: in the
2391 range of @minus{}2048 to @minus{}1
2397 12-bit signed integer constant that is greater than zero---i.e.@: in the
2402 @item Blackfin family---@file{config/bfin/constraints.md}
2411 A call clobbered P register.
2414 A single register. If @var{n} is in the range 0 to 7, the corresponding D
2415 register. If it is @code{A}, then the register P0.
2418 Even-numbered D register
2421 Odd-numbered D register
2424 Accumulator register.
2427 Even-numbered accumulator register.
2430 Odd-numbered accumulator register.
2442 Registers used for circular buffering, i.e. I, B, or L registers.
2457 Any D, P, B, M, I or L register.
2460 Additional registers typically used only in prologues and epilogues: RETS,
2461 RETN, RETI, RETX, RETE, ASTAT, SEQSTAT and USP.
2464 Any register except accumulators or CC.
2467 Signed 16 bit integer (in the range @minus{}32768 to 32767)
2470 Unsigned 16 bit integer (in the range 0 to 65535)
2473 Signed 7 bit integer (in the range @minus{}64 to 63)
2476 Unsigned 7 bit integer (in the range 0 to 127)
2479 Unsigned 5 bit integer (in the range 0 to 31)
2482 Signed 4 bit integer (in the range @minus{}8 to 7)
2485 Signed 3 bit integer (in the range @minus{}3 to 4)
2488 Unsigned 3 bit integer (in the range 0 to 7)
2491 Constant @var{n}, where @var{n} is a single-digit constant in the range 0 to 4.
2494 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2495 use with either accumulator.
2498 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2499 use only with accumulator A1.
2508 An integer constant with exactly a single bit set.
2511 An integer constant with all bits set except exactly one.
2519 @item M32C---@file{config/m32c/m32c.c}
2524 @samp{$sp}, @samp{$fb}, @samp{$sb}.
2527 Any control register, when they're 16 bits wide (nothing if control
2528 registers are 24 bits wide)
2531 Any control register, when they're 24 bits wide.
2540 $r0 or $r2, or $r2r0 for 32 bit values.
2543 $r1 or $r3, or $r3r1 for 32 bit values.
2546 A register that can hold a 64 bit value.
2549 $r0 or $r1 (registers with addressable high/low bytes)
2558 Address registers when they're 16 bits wide.
2561 Address registers when they're 24 bits wide.
2564 Registers that can hold QI values.
2567 Registers that can be used with displacements ($a0, $a1, $sb).
2570 Registers that can hold 32 bit values.
2573 Registers that can hold 16 bit values.
2576 Registers chat can hold 16 bit values, including all control
2580 $r0 through R1, plus $a0 and $a1.
2586 The memory-based pseudo-registers $mem0 through $mem15.
2589 Registers that can hold pointers (16 bit registers for r8c, m16c; 24
2590 bit registers for m32cm, m32c).
2593 Matches multiple registers in a PARALLEL to form a larger register.
2594 Used to match function return values.
2600 @minus{}128 @dots{} 127
2603 @minus{}32768 @dots{} 32767
2609 @minus{}8 @dots{} @minus{}1 or 1 @dots{} 8
2612 @minus{}16 @dots{} @minus{}1 or 1 @dots{} 16
2615 @minus{}32 @dots{} @minus{}1 or 1 @dots{} 32
2618 @minus{}65536 @dots{} @minus{}1
2621 An 8 bit value with exactly one bit set.
2624 A 16 bit value with exactly one bit set.
2627 The common src/dest memory addressing modes.
2630 Memory addressed using $a0 or $a1.
2633 Memory addressed with immediate addresses.
2636 Memory addressed using the stack pointer ($sp).
2639 Memory addressed using the frame base register ($fb).
2642 Memory addressed using the small base register ($sb).
2648 @item MeP---@file{config/mep/constraints.md}
2658 Any control register.
2661 Either the $hi or the $lo register.
2664 Coprocessor registers that can be directly loaded ($c0-$c15).
2667 Coprocessor registers that can be moved to each other.
2670 Coprocessor registers that can be moved to core registers.
2682 Registers which can be used in $tp-relative addressing.
2688 The coprocessor registers.
2691 The coprocessor control registers.
2697 User-defined register set A.
2700 User-defined register set B.
2703 User-defined register set C.
2706 User-defined register set D.
2709 Offsets for $gp-rel addressing.
2712 Constants that can be used directly with boolean insns.
2715 Constants that can be moved directly to registers.
2718 Small constants that can be added to registers.
2724 Small constants that can be compared to registers.
2727 Constants that can be loaded into the top half of registers.
2730 Signed 8-bit immediates.
2733 Symbols encoded for $tp-rel or $gp-rel addressing.
2736 Non-constant addresses for loading/saving coprocessor registers.
2739 The top half of a symbol's value.
2742 A register indirect address without offset.
2745 Symbolic references to the control bus.
2749 @item MicroBlaze---@file{config/microblaze/constraints.md}
2752 A general register (@code{r0} to @code{r31}).
2755 A status register (@code{rmsr}, @code{$fcc1} to @code{$fcc7}).
2759 @item MIPS---@file{config/mips/constraints.md}
2762 An address register. This is equivalent to @code{r} unless
2763 generating MIPS16 code.
2766 A floating-point register (if available).
2769 Formerly the @code{hi} register. This constraint is no longer supported.
2772 The @code{lo} register. Use this register to store values that are
2773 no bigger than a word.
2776 The concatenated @code{hi} and @code{lo} registers. Use this register
2777 to store doubleword values.
2780 A register suitable for use in an indirect jump. This will always be
2781 @code{$25} for @option{-mabicalls}.
2784 Register @code{$3}. Do not use this constraint in new code;
2785 it is retained only for compatibility with glibc.
2788 Equivalent to @code{r}; retained for backwards compatibility.
2791 A floating-point condition code register.
2794 A signed 16-bit constant (for arithmetic instructions).
2800 An unsigned 16-bit constant (for logic instructions).
2803 A signed 32-bit constant in which the lower 16 bits are zero.
2804 Such constants can be loaded using @code{lui}.
2807 A constant that cannot be loaded using @code{lui}, @code{addiu}
2811 A constant in the range @minus{}65535 to @minus{}1 (inclusive).
2814 A signed 15-bit constant.
2817 A constant in the range 1 to 65535 (inclusive).
2820 Floating-point zero.
2823 An address that can be used in a non-macro load or store.
2826 @item Motorola 680x0---@file{config/m68k/constraints.md}
2835 68881 floating-point register, if available
2838 Integer in the range 1 to 8
2841 16-bit signed number
2844 Signed number whose magnitude is greater than 0x80
2847 Integer in the range @minus{}8 to @minus{}1
2850 Signed number whose magnitude is greater than 0x100
2853 Range 24 to 31, rotatert:SI 8 to 1 expressed as rotate
2856 16 (for rotate using swap)
2859 Range 8 to 15, rotatert:HI 8 to 1 expressed as rotate
2862 Numbers that mov3q can handle
2865 Floating point constant that is not a 68881 constant
2868 Operands that satisfy 'm' when -mpcrel is in effect
2871 Operands that satisfy 's' when -mpcrel is not in effect
2874 Address register indirect addressing mode
2877 Register offset addressing
2892 Range of signed numbers that don't fit in 16 bits
2895 Integers valid for mvq
2898 Integers valid for a moveq followed by a swap
2901 Integers valid for mvz
2904 Integers valid for mvs
2910 Non-register operands allowed in clr
2914 @item Moxie---@file{config/moxie/constraints.md}
2923 A register indirect memory operand
2926 A constant in the range of 0 to 255.
2929 A constant in the range of 0 to @minus{}255.
2933 @item PDP-11---@file{config/pdp11/constraints.md}
2936 Floating point registers AC0 through AC3. These can be loaded from/to
2937 memory with a single instruction.
2940 Odd numbered general registers (R1, R3, R5). These are used for
2941 16-bit multiply operations.
2944 Any of the floating point registers (AC0 through AC5).
2947 Floating point constant 0.
2950 An integer constant that fits in 16 bits.
2953 An integer constant whose low order 16 bits are zero.
2956 An integer constant that does not meet the constraints for codes
2957 @samp{I} or @samp{J}.
2960 The integer constant 1.
2963 The integer constant @minus{}1.
2966 The integer constant 0.
2969 Integer constants @minus{}4 through @minus{}1 and 1 through 4; shifts by these
2970 amounts are handled as multiple single-bit shifts rather than a single
2971 variable-length shift.
2974 A memory reference which requires an additional word (address or
2975 offset) after the opcode.
2978 A memory reference that is encoded within the opcode.
2982 @item RX---@file{config/rx/constraints.md}
2985 An address which does not involve register indirect addressing or
2986 pre/post increment/decrement addressing.
2992 A constant in the range @minus{}256 to 255, inclusive.
2995 A constant in the range @minus{}128 to 127, inclusive.
2998 A constant in the range @minus{}32768 to 32767, inclusive.
3001 A constant in the range @minus{}8388608 to 8388607, inclusive.
3004 A constant in the range 0 to 15, inclusive.
3009 @item SPARC---@file{config/sparc/sparc.h}
3012 Floating-point register on the SPARC-V8 architecture and
3013 lower floating-point register on the SPARC-V9 architecture.
3016 Floating-point register. It is equivalent to @samp{f} on the
3017 SPARC-V8 architecture and contains both lower and upper
3018 floating-point registers on the SPARC-V9 architecture.
3021 Floating-point condition code register.
3024 Lower floating-point register. It is only valid on the SPARC-V9
3025 architecture when the Visual Instruction Set is available.
3028 Floating-point register. It is only valid on the SPARC-V9 architecture
3029 when the Visual Instruction Set is available.
3032 64-bit global or out register for the SPARC-V8+ architecture.
3038 Signed 13-bit constant
3044 32-bit constant with the low 12 bits clear (a constant that can be
3045 loaded with the @code{sethi} instruction)
3048 A constant in the range supported by @code{movcc} instructions
3051 A constant in the range supported by @code{movrcc} instructions
3054 Same as @samp{K}, except that it verifies that bits that are not in the
3055 lower 32-bit range are all zero. Must be used instead of @samp{K} for
3056 modes wider than @code{SImode}
3065 Signed 13-bit constant, sign-extended to 32 or 64 bits
3068 Floating-point constant whose integral representation can
3069 be moved into an integer register using a single sethi
3073 Floating-point constant whose integral representation can
3074 be moved into an integer register using a single mov
3078 Floating-point constant whose integral representation can
3079 be moved into an integer register using a high/lo_sum
3080 instruction sequence
3083 Memory address aligned to an 8-byte boundary
3089 Memory address for @samp{e} constraint registers
3096 @item SPU---@file{config/spu/spu.h}
3099 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 64 bit value.
3102 An immediate for and/xor/or instructions. const_int is treated as a 64 bit value.
3105 An immediate for the @code{iohl} instruction. const_int is treated as a 64 bit value.
3108 An immediate which can be loaded with @code{fsmbi}.
3111 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 32 bit value.
3114 An immediate for most arithmetic instructions. const_int is treated as a 32 bit value.
3117 An immediate for and/xor/or instructions. const_int is treated as a 32 bit value.
3120 An immediate for the @code{iohl} instruction. const_int is treated as a 32 bit value.
3123 A constant in the range [@minus{}64, 63] for shift/rotate instructions.
3126 An unsigned 7-bit constant for conversion/nop/channel instructions.
3129 A signed 10-bit constant for most arithmetic instructions.
3132 A signed 16 bit immediate for @code{stop}.
3135 An unsigned 16-bit constant for @code{iohl} and @code{fsmbi}.
3138 An unsigned 7-bit constant whose 3 least significant bits are 0.
3141 An unsigned 3-bit constant for 16-byte rotates and shifts
3144 Call operand, reg, for indirect calls
3147 Call operand, symbol, for relative calls.
3150 Call operand, const_int, for absolute calls.
3153 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is sign extended to 128 bit.
3156 An immediate for shift and rotate instructions. const_int is treated as a 32 bit value.
3159 An immediate for and/xor/or instructions. const_int is sign extended as a 128 bit.
3162 An immediate for the @code{iohl} instruction. const_int is sign extended to 128 bit.
3166 @item S/390 and zSeries---@file{config/s390/s390.h}
3169 Address register (general purpose register except r0)
3172 Condition code register
3175 Data register (arbitrary general purpose register)
3178 Floating-point register
3181 Unsigned 8-bit constant (0--255)
3184 Unsigned 12-bit constant (0--4095)
3187 Signed 16-bit constant (@minus{}32768--32767)
3190 Value appropriate as displacement.
3193 for short displacement
3194 @item (@minus{}524288..524287)
3195 for long displacement
3199 Constant integer with a value of 0x7fffffff.
3202 Multiple letter constraint followed by 4 parameter letters.
3205 number of the part counting from most to least significant
3209 mode of the containing operand
3211 value of the other parts (F---all bits set)
3213 The constraint matches if the specified part of a constant
3214 has a value different from its other parts.
3217 Memory reference without index register and with short displacement.
3220 Memory reference with index register and short displacement.
3223 Memory reference without index register but with long displacement.
3226 Memory reference with index register and long displacement.
3229 Pointer with short displacement.
3232 Pointer with long displacement.
3235 Shift count operand.
3239 @item Score family---@file{config/score/score.h}
3242 Registers from r0 to r32.
3245 Registers from r0 to r16.
3248 r8---r11 or r22---r27 registers.
3269 cnt + lcb + scb register.
3272 cr0---cr15 register.
3284 cp1 + cp2 + cp3 registers.
3287 High 16-bit constant (32-bit constant with 16 LSBs zero).
3290 Unsigned 5 bit integer (in the range 0 to 31).
3293 Unsigned 16 bit integer (in the range 0 to 65535).
3296 Signed 16 bit integer (in the range @minus{}32768 to 32767).
3299 Unsigned 14 bit integer (in the range 0 to 16383).
3302 Signed 14 bit integer (in the range @minus{}8192 to 8191).
3308 @item Xstormy16---@file{config/stormy16/stormy16.h}
3323 Registers r0 through r7.
3326 Registers r0 and r1.
3332 Registers r8 and r9.
3335 A constant between 0 and 3 inclusive.
3338 A constant that has exactly one bit set.
3341 A constant that has exactly one bit clear.
3344 A constant between 0 and 255 inclusive.
3347 A constant between @minus{}255 and 0 inclusive.
3350 A constant between @minus{}3 and 0 inclusive.
3353 A constant between 1 and 4 inclusive.
3356 A constant between @minus{}4 and @minus{}1 inclusive.
3359 A memory reference that is a stack push.
3362 A memory reference that is a stack pop.
3365 A memory reference that refers to a constant address of known value.
3368 The register indicated by Rx (not implemented yet).
3371 A constant that is not between 2 and 15 inclusive.
3378 @item TI C6X family---@file{config/c6x/constraints.md}
3381 Register file A (A0--A31).
3384 Register file B (B0--B31).
3387 Predicate registers in register file A (A0--A2 on C64X and
3388 higher, A1 and A2 otherwise).
3391 Predicate registers in register file B (B0--B2).
3394 A call-used register in register file B (B0--B9, B16--B31).
3397 Register file A, excluding predicate registers (A3--A31,
3398 plus A0 if not C64X or higher).
3401 Register file B, excluding predicate registers (B3--B31).
3404 Integer constant in the range 0 @dots{} 15.
3407 Integer constant in the range 0 @dots{} 31.
3410 Integer constant in the range @minus{}31 @dots{} 0.
3413 Integer constant in the range @minus{}16 @dots{} 15.
3416 Integer constant that can be the operand of an ADDA or a SUBA insn.
3419 Integer constant in the range 0 @dots{} 65535.
3422 Integer constant in the range @minus{}32768 @dots{} 32767.
3425 Integer constant in the range @math{-2^{20}} @dots{} @math{2^{20} - 1}.
3428 Integer constant that is a valid mask for the clr instruction.
3431 Integer constant that is a valid mask for the set instruction.
3434 Memory location with A base register.
3437 Memory location with B base register.
3441 On C64x+ targets, a GP-relative small data reference.
3444 Any kind of @code{SYMBOL_REF}, for use in a call address.
3447 Any kind of immediate operand, unless it matches the S0 constraint.
3450 Memory location with B base register, but not using a long offset.
3453 A memory operand with an address that can't be used in an unaligned access.
3457 Register B14 (aka DP).
3461 @item Xtensa---@file{config/xtensa/constraints.md}
3464 General-purpose 32-bit register
3467 One-bit boolean register
3470 MAC16 40-bit accumulator register
3473 Signed 12-bit integer constant, for use in MOVI instructions
3476 Signed 8-bit integer constant, for use in ADDI instructions
3479 Integer constant valid for BccI instructions
3482 Unsigned constant valid for BccUI instructions
3489 @node Disable Insn Alternatives
3490 @subsection Disable insn alternatives using the @code{enabled} attribute
3493 The @code{enabled} insn attribute may be used to disable certain insn
3494 alternatives for machine-specific reasons. This is useful when adding
3495 new instructions to an existing pattern which are only available for
3496 certain cpu architecture levels as specified with the @code{-march=}
3499 If an insn alternative is disabled, then it will never be used. The
3500 compiler treats the constraints for the disabled alternative as
3503 In order to make use of the @code{enabled} attribute a back end has to add
3504 in the machine description files:
3508 A definition of the @code{enabled} insn attribute. The attribute is
3509 defined as usual using the @code{define_attr} command. This
3510 definition should be based on other insn attributes and/or target flags.
3511 The @code{enabled} attribute is a numeric attribute and should evaluate to
3512 @code{(const_int 1)} for an enabled alternative and to
3513 @code{(const_int 0)} otherwise.
3515 A definition of another insn attribute used to describe for what
3516 reason an insn alternative might be available or
3517 not. E.g. @code{cpu_facility} as in the example below.
3519 An assignment for the second attribute to each insn definition
3520 combining instructions which are not all available under the same
3521 circumstances. (Note: It obviously only makes sense for definitions
3522 with more than one alternative. Otherwise the insn pattern should be
3523 disabled or enabled using the insn condition.)
3526 E.g. the following two patterns could easily be merged using the @code{enabled}
3531 (define_insn "*movdi_old"
3532 [(set (match_operand:DI 0 "register_operand" "=d")
3533 (match_operand:DI 1 "register_operand" " d"))]
3537 (define_insn "*movdi_new"
3538 [(set (match_operand:DI 0 "register_operand" "=d,f,d")
3539 (match_operand:DI 1 "register_operand" " d,d,f"))]
3552 (define_insn "*movdi_combined"
3553 [(set (match_operand:DI 0 "register_operand" "=d,f,d")
3554 (match_operand:DI 1 "register_operand" " d,d,f"))]
3560 [(set_attr "cpu_facility" "*,new,new")])
3564 with the @code{enabled} attribute defined like this:
3568 (define_attr "cpu_facility" "standard,new" (const_string "standard"))
3570 (define_attr "enabled" ""
3571 (cond [(eq_attr "cpu_facility" "standard") (const_int 1)
3572 (and (eq_attr "cpu_facility" "new")
3573 (ne (symbol_ref "TARGET_NEW") (const_int 0)))
3582 @node Define Constraints
3583 @subsection Defining Machine-Specific Constraints
3584 @cindex defining constraints
3585 @cindex constraints, defining
3587 Machine-specific constraints fall into two categories: register and
3588 non-register constraints. Within the latter category, constraints
3589 which allow subsets of all possible memory or address operands should
3590 be specially marked, to give @code{reload} more information.
3592 Machine-specific constraints can be given names of arbitrary length,
3593 but they must be entirely composed of letters, digits, underscores
3594 (@samp{_}), and angle brackets (@samp{< >}). Like C identifiers, they
3595 must begin with a letter or underscore.
3597 In order to avoid ambiguity in operand constraint strings, no
3598 constraint can have a name that begins with any other constraint's
3599 name. For example, if @code{x} is defined as a constraint name,
3600 @code{xy} may not be, and vice versa. As a consequence of this rule,
3601 no constraint may begin with one of the generic constraint letters:
3602 @samp{E F V X g i m n o p r s}.
3604 Register constraints correspond directly to register classes.
3605 @xref{Register Classes}. There is thus not much flexibility in their
3608 @deffn {MD Expression} define_register_constraint name regclass docstring
3609 All three arguments are string constants.
3610 @var{name} is the name of the constraint, as it will appear in
3611 @code{match_operand} expressions. If @var{name} is a multi-letter
3612 constraint its length shall be the same for all constraints starting
3613 with the same letter. @var{regclass} can be either the
3614 name of the corresponding register class (@pxref{Register Classes}),
3615 or a C expression which evaluates to the appropriate register class.
3616 If it is an expression, it must have no side effects, and it cannot
3617 look at the operand. The usual use of expressions is to map some
3618 register constraints to @code{NO_REGS} when the register class
3619 is not available on a given subarchitecture.
3621 @var{docstring} is a sentence documenting the meaning of the
3622 constraint. Docstrings are explained further below.
3625 Non-register constraints are more like predicates: the constraint
3626 definition gives a Boolean expression which indicates whether the
3629 @deffn {MD Expression} define_constraint name docstring exp
3630 The @var{name} and @var{docstring} arguments are the same as for
3631 @code{define_register_constraint}, but note that the docstring comes
3632 immediately after the name for these expressions. @var{exp} is an RTL
3633 expression, obeying the same rules as the RTL expressions in predicate
3634 definitions. @xref{Defining Predicates}, for details. If it
3635 evaluates true, the constraint matches; if it evaluates false, it
3636 doesn't. Constraint expressions should indicate which RTL codes they
3637 might match, just like predicate expressions.
3639 @code{match_test} C expressions have access to the
3640 following variables:
3644 The RTL object defining the operand.
3646 The machine mode of @var{op}.
3648 @samp{INTVAL (@var{op})}, if @var{op} is a @code{const_int}.
3650 @samp{CONST_DOUBLE_HIGH (@var{op})}, if @var{op} is an integer
3651 @code{const_double}.
3653 @samp{CONST_DOUBLE_LOW (@var{op})}, if @var{op} is an integer
3654 @code{const_double}.
3656 @samp{CONST_DOUBLE_REAL_VALUE (@var{op})}, if @var{op} is a floating-point
3657 @code{const_double}.
3660 The @var{*val} variables should only be used once another piece of the
3661 expression has verified that @var{op} is the appropriate kind of RTL
3665 Most non-register constraints should be defined with
3666 @code{define_constraint}. The remaining two definition expressions
3667 are only appropriate for constraints that should be handled specially
3668 by @code{reload} if they fail to match.
3670 @deffn {MD Expression} define_memory_constraint name docstring exp
3671 Use this expression for constraints that match a subset of all memory
3672 operands: that is, @code{reload} can make them match by converting the
3673 operand to the form @samp{@w{(mem (reg @var{X}))}}, where @var{X} is a
3674 base register (from the register class specified by
3675 @code{BASE_REG_CLASS}, @pxref{Register Classes}).
3677 For example, on the S/390, some instructions do not accept arbitrary
3678 memory references, but only those that do not make use of an index
3679 register. The constraint letter @samp{Q} is defined to represent a
3680 memory address of this type. If @samp{Q} is defined with
3681 @code{define_memory_constraint}, a @samp{Q} constraint can handle any
3682 memory operand, because @code{reload} knows it can simply copy the
3683 memory address into a base register if required. This is analogous to
3684 the way an @samp{o} constraint can handle any memory operand.
3686 The syntax and semantics are otherwise identical to
3687 @code{define_constraint}.
3690 @deffn {MD Expression} define_address_constraint name docstring exp
3691 Use this expression for constraints that match a subset of all address
3692 operands: that is, @code{reload} can make the constraint match by
3693 converting the operand to the form @samp{@w{(reg @var{X})}}, again
3694 with @var{X} a base register.
3696 Constraints defined with @code{define_address_constraint} can only be
3697 used with the @code{address_operand} predicate, or machine-specific
3698 predicates that work the same way. They are treated analogously to
3699 the generic @samp{p} constraint.
3701 The syntax and semantics are otherwise identical to
3702 @code{define_constraint}.
3705 For historical reasons, names beginning with the letters @samp{G H}
3706 are reserved for constraints that match only @code{const_double}s, and
3707 names beginning with the letters @samp{I J K L M N O P} are reserved
3708 for constraints that match only @code{const_int}s. This may change in
3709 the future. For the time being, constraints with these names must be
3710 written in a stylized form, so that @code{genpreds} can tell you did
3715 (define_constraint "[@var{GHIJKLMNOP}]@dots{}"
3717 (and (match_code "const_int") ; @r{@code{const_double} for G/H}
3718 @var{condition}@dots{})) ; @r{usually a @code{match_test}}
3721 @c the semicolons line up in the formatted manual
3723 It is fine to use names beginning with other letters for constraints
3724 that match @code{const_double}s or @code{const_int}s.
3726 Each docstring in a constraint definition should be one or more complete
3727 sentences, marked up in Texinfo format. @emph{They are currently unused.}
3728 In the future they will be copied into the GCC manual, in @ref{Machine
3729 Constraints}, replacing the hand-maintained tables currently found in
3730 that section. Also, in the future the compiler may use this to give
3731 more helpful diagnostics when poor choice of @code{asm} constraints
3732 causes a reload failure.
3734 If you put the pseudo-Texinfo directive @samp{@@internal} at the
3735 beginning of a docstring, then (in the future) it will appear only in
3736 the internals manual's version of the machine-specific constraint tables.
3737 Use this for constraints that should not appear in @code{asm} statements.
3739 @node C Constraint Interface
3740 @subsection Testing constraints from C
3741 @cindex testing constraints
3742 @cindex constraints, testing
3744 It is occasionally useful to test a constraint from C code rather than
3745 implicitly via the constraint string in a @code{match_operand}. The
3746 generated file @file{tm_p.h} declares a few interfaces for working
3747 with machine-specific constraints. None of these interfaces work with
3748 the generic constraints described in @ref{Simple Constraints}. This
3749 may change in the future.
3751 @strong{Warning:} @file{tm_p.h} may declare other functions that
3752 operate on constraints, besides the ones documented here. Do not use
3753 those functions from machine-dependent code. They exist to implement
3754 the old constraint interface that machine-independent components of
3755 the compiler still expect. They will change or disappear in the
3758 Some valid constraint names are not valid C identifiers, so there is a
3759 mangling scheme for referring to them from C@. Constraint names that
3760 do not contain angle brackets or underscores are left unchanged.
3761 Underscores are doubled, each @samp{<} is replaced with @samp{_l}, and
3762 each @samp{>} with @samp{_g}. Here are some examples:
3764 @c the @c's prevent double blank lines in the printed manual.
3766 @multitable {Original} {Mangled}
3767 @item @strong{Original} @tab @strong{Mangled} @c
3768 @item @code{x} @tab @code{x} @c
3769 @item @code{P42x} @tab @code{P42x} @c
3770 @item @code{P4_x} @tab @code{P4__x} @c
3771 @item @code{P4>x} @tab @code{P4_gx} @c
3772 @item @code{P4>>} @tab @code{P4_g_g} @c
3773 @item @code{P4_g>} @tab @code{P4__g_g} @c
3777 Throughout this section, the variable @var{c} is either a constraint
3778 in the abstract sense, or a constant from @code{enum constraint_num};
3779 the variable @var{m} is a mangled constraint name (usually as part of
3780 a larger identifier).
3782 @deftp Enum constraint_num
3783 For each machine-specific constraint, there is a corresponding
3784 enumeration constant: @samp{CONSTRAINT_} plus the mangled name of the
3785 constraint. Functions that take an @code{enum constraint_num} as an
3786 argument expect one of these constants.
3788 Machine-independent constraints do not have associated constants.
3789 This may change in the future.
3792 @deftypefun {inline bool} satisfies_constraint_@var{m} (rtx @var{exp})
3793 For each machine-specific, non-register constraint @var{m}, there is
3794 one of these functions; it returns @code{true} if @var{exp} satisfies the
3795 constraint. These functions are only visible if @file{rtl.h} was included
3796 before @file{tm_p.h}.
3799 @deftypefun bool constraint_satisfied_p (rtx @var{exp}, enum constraint_num @var{c})
3800 Like the @code{satisfies_constraint_@var{m}} functions, but the
3801 constraint to test is given as an argument, @var{c}. If @var{c}
3802 specifies a register constraint, this function will always return
3806 @deftypefun {enum reg_class} regclass_for_constraint (enum constraint_num @var{c})
3807 Returns the register class associated with @var{c}. If @var{c} is not
3808 a register constraint, or those registers are not available for the
3809 currently selected subtarget, returns @code{NO_REGS}.
3812 Here is an example use of @code{satisfies_constraint_@var{m}}. In
3813 peephole optimizations (@pxref{Peephole Definitions}), operand
3814 constraint strings are ignored, so if there are relevant constraints,
3815 they must be tested in the C condition. In the example, the
3816 optimization is applied if operand 2 does @emph{not} satisfy the
3817 @samp{K} constraint. (This is a simplified version of a peephole
3818 definition from the i386 machine description.)
3822 [(match_scratch:SI 3 "r")
3823 (set (match_operand:SI 0 "register_operand" "")
3824 (mult:SI (match_operand:SI 1 "memory_operand" "")
3825 (match_operand:SI 2 "immediate_operand" "")))]
3827 "!satisfies_constraint_K (operands[2])"
3829 [(set (match_dup 3) (match_dup 1))
3830 (set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))]
3835 @node Standard Names
3836 @section Standard Pattern Names For Generation
3837 @cindex standard pattern names
3838 @cindex pattern names
3839 @cindex names, pattern
3841 Here is a table of the instruction names that are meaningful in the RTL
3842 generation pass of the compiler. Giving one of these names to an
3843 instruction pattern tells the RTL generation pass that it can use the
3844 pattern to accomplish a certain task.
3847 @cindex @code{mov@var{m}} instruction pattern
3848 @item @samp{mov@var{m}}
3849 Here @var{m} stands for a two-letter machine mode name, in lowercase.
3850 This instruction pattern moves data with that machine mode from operand
3851 1 to operand 0. For example, @samp{movsi} moves full-word data.
3853 If operand 0 is a @code{subreg} with mode @var{m} of a register whose
3854 own mode is wider than @var{m}, the effect of this instruction is
3855 to store the specified value in the part of the register that corresponds
3856 to mode @var{m}. Bits outside of @var{m}, but which are within the
3857 same target word as the @code{subreg} are undefined. Bits which are
3858 outside the target word are left unchanged.
3860 This class of patterns is special in several ways. First of all, each
3861 of these names up to and including full word size @emph{must} be defined,
3862 because there is no other way to copy a datum from one place to another.
3863 If there are patterns accepting operands in larger modes,
3864 @samp{mov@var{m}} must be defined for integer modes of those sizes.
3866 Second, these patterns are not used solely in the RTL generation pass.
3867 Even the reload pass can generate move insns to copy values from stack
3868 slots into temporary registers. When it does so, one of the operands is
3869 a hard register and the other is an operand that can need to be reloaded
3873 Therefore, when given such a pair of operands, the pattern must generate
3874 RTL which needs no reloading and needs no temporary registers---no
3875 registers other than the operands. For example, if you support the
3876 pattern with a @code{define_expand}, then in such a case the
3877 @code{define_expand} mustn't call @code{force_reg} or any other such
3878 function which might generate new pseudo registers.
3880 This requirement exists even for subword modes on a RISC machine where
3881 fetching those modes from memory normally requires several insns and
3882 some temporary registers.
3884 @findex change_address
3885 During reload a memory reference with an invalid address may be passed
3886 as an operand. Such an address will be replaced with a valid address
3887 later in the reload pass. In this case, nothing may be done with the
3888 address except to use it as it stands. If it is copied, it will not be
3889 replaced with a valid address. No attempt should be made to make such
3890 an address into a valid address and no routine (such as
3891 @code{change_address}) that will do so may be called. Note that
3892 @code{general_operand} will fail when applied to such an address.
3894 @findex reload_in_progress
3895 The global variable @code{reload_in_progress} (which must be explicitly
3896 declared if required) can be used to determine whether such special
3897 handling is required.
3899 The variety of operands that have reloads depends on the rest of the
3900 machine description, but typically on a RISC machine these can only be
3901 pseudo registers that did not get hard registers, while on other
3902 machines explicit memory references will get optional reloads.
3904 If a scratch register is required to move an object to or from memory,
3905 it can be allocated using @code{gen_reg_rtx} prior to life analysis.
3907 If there are cases which need scratch registers during or after reload,
3908 you must provide an appropriate secondary_reload target hook.
3910 @findex can_create_pseudo_p
3911 The macro @code{can_create_pseudo_p} can be used to determine if it
3912 is unsafe to create new pseudo registers. If this variable is nonzero, then
3913 it is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo.
3915 The constraints on a @samp{mov@var{m}} must permit moving any hard
3916 register to any other hard register provided that
3917 @code{HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and
3918 @code{TARGET_REGISTER_MOVE_COST} applied to their classes returns a value
3921 It is obligatory to support floating point @samp{mov@var{m}}
3922 instructions into and out of any registers that can hold fixed point
3923 values, because unions and structures (which have modes @code{SImode} or
3924 @code{DImode}) can be in those registers and they may have floating
3927 There may also be a need to support fixed point @samp{mov@var{m}}
3928 instructions in and out of floating point registers. Unfortunately, I
3929 have forgotten why this was so, and I don't know whether it is still
3930 true. If @code{HARD_REGNO_MODE_OK} rejects fixed point values in
3931 floating point registers, then the constraints of the fixed point
3932 @samp{mov@var{m}} instructions must be designed to avoid ever trying to
3933 reload into a floating point register.
3935 @cindex @code{reload_in} instruction pattern
3936 @cindex @code{reload_out} instruction pattern
3937 @item @samp{reload_in@var{m}}
3938 @itemx @samp{reload_out@var{m}}
3939 These named patterns have been obsoleted by the target hook
3940 @code{secondary_reload}.
3942 Like @samp{mov@var{m}}, but used when a scratch register is required to
3943 move between operand 0 and operand 1. Operand 2 describes the scratch
3944 register. See the discussion of the @code{SECONDARY_RELOAD_CLASS}
3945 macro in @pxref{Register Classes}.
3947 There are special restrictions on the form of the @code{match_operand}s
3948 used in these patterns. First, only the predicate for the reload
3949 operand is examined, i.e., @code{reload_in} examines operand 1, but not
3950 the predicates for operand 0 or 2. Second, there may be only one
3951 alternative in the constraints. Third, only a single register class
3952 letter may be used for the constraint; subsequent constraint letters
3953 are ignored. As a special exception, an empty constraint string
3954 matches the @code{ALL_REGS} register class. This may relieve ports
3955 of the burden of defining an @code{ALL_REGS} constraint letter just
3958 @cindex @code{movstrict@var{m}} instruction pattern
3959 @item @samp{movstrict@var{m}}
3960 Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg}
3961 with mode @var{m} of a register whose natural mode is wider,
3962 the @samp{movstrict@var{m}} instruction is guaranteed not to alter
3963 any of the register except the part which belongs to mode @var{m}.
3965 @cindex @code{movmisalign@var{m}} instruction pattern
3966 @item @samp{movmisalign@var{m}}
3967 This variant of a move pattern is designed to load or store a value
3968 from a memory address that is not naturally aligned for its mode.
3969 For a store, the memory will be in operand 0; for a load, the memory
3970 will be in operand 1. The other operand is guaranteed not to be a
3971 memory, so that it's easy to tell whether this is a load or store.
3973 This pattern is used by the autovectorizer, and when expanding a
3974 @code{MISALIGNED_INDIRECT_REF} expression.
3976 @cindex @code{load_multiple} instruction pattern
3977 @item @samp{load_multiple}
3978 Load several consecutive memory locations into consecutive registers.
3979 Operand 0 is the first of the consecutive registers, operand 1
3980 is the first memory location, and operand 2 is a constant: the
3981 number of consecutive registers.
3983 Define this only if the target machine really has such an instruction;
3984 do not define this if the most efficient way of loading consecutive
3985 registers from memory is to do them one at a time.
3987 On some machines, there are restrictions as to which consecutive
3988 registers can be stored into memory, such as particular starting or
3989 ending register numbers or only a range of valid counts. For those
3990 machines, use a @code{define_expand} (@pxref{Expander Definitions})
3991 and make the pattern fail if the restrictions are not met.
3993 Write the generated insn as a @code{parallel} with elements being a
3994 @code{set} of one register from the appropriate memory location (you may
3995 also need @code{use} or @code{clobber} elements). Use a
3996 @code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See
3997 @file{rs6000.md} for examples of the use of this insn pattern.
3999 @cindex @samp{store_multiple} instruction pattern
4000 @item @samp{store_multiple}
4001 Similar to @samp{load_multiple}, but store several consecutive registers
4002 into consecutive memory locations. Operand 0 is the first of the
4003 consecutive memory locations, operand 1 is the first register, and
4004 operand 2 is a constant: the number of consecutive registers.
4006 @cindex @code{vec_load_lanes@var{m}@var{n}} instruction pattern
4007 @item @samp{vec_load_lanes@var{m}@var{n}}
4008 Perform an interleaved load of several vectors from memory operand 1
4009 into register operand 0. Both operands have mode @var{m}. The register
4010 operand is viewed as holding consecutive vectors of mode @var{n},
4011 while the memory operand is a flat array that contains the same number
4012 of elements. The operation is equivalent to:
4015 int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
4016 for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
4017 for (i = 0; i < c; i++)
4018 operand0[i][j] = operand1[j * c + i];
4021 For example, @samp{vec_load_lanestiv4hi} loads 8 16-bit values
4022 from memory into a register of mode @samp{TI}@. The register
4023 contains two consecutive vectors of mode @samp{V4HI}@.
4025 This pattern can only be used if:
4027 TARGET_ARRAY_MODE_SUPPORTED_P (@var{n}, @var{c})
4029 is true. GCC assumes that, if a target supports this kind of
4030 instruction for some mode @var{n}, it also supports unaligned
4031 loads for vectors of mode @var{n}.
4033 @cindex @code{vec_store_lanes@var{m}@var{n}} instruction pattern
4034 @item @samp{vec_store_lanes@var{m}@var{n}}
4035 Equivalent to @samp{vec_load_lanes@var{m}@var{n}}, with the memory
4036 and register operands reversed. That is, the instruction is
4040 int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
4041 for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
4042 for (i = 0; i < c; i++)
4043 operand0[j * c + i] = operand1[i][j];
4046 for a memory operand 0 and register operand 1.
4048 @cindex @code{vec_set@var{m}} instruction pattern
4049 @item @samp{vec_set@var{m}}
4050 Set given field in the vector value. Operand 0 is the vector to modify,
4051 operand 1 is new value of field and operand 2 specify the field index.
4053 @cindex @code{vec_extract@var{m}} instruction pattern
4054 @item @samp{vec_extract@var{m}}
4055 Extract given field from the vector value. Operand 1 is the vector, operand 2
4056 specify field index and operand 0 place to store value into.
4058 @cindex @code{vec_extract_even@var{m}} instruction pattern
4059 @item @samp{vec_extract_even@var{m}}
4060 Extract even elements from the input vectors (operand 1 and operand 2).
4061 The even elements of operand 2 are concatenated to the even elements of operand
4062 1 in their original order. The result is stored in operand 0.
4063 The output and input vectors should have the same modes.
4065 @cindex @code{vec_extract_odd@var{m}} instruction pattern
4066 @item @samp{vec_extract_odd@var{m}}
4067 Extract odd elements from the input vectors (operand 1 and operand 2).
4068 The odd elements of operand 2 are concatenated to the odd elements of operand
4069 1 in their original order. The result is stored in operand 0.
4070 The output and input vectors should have the same modes.
4072 @cindex @code{vec_interleave_high@var{m}} instruction pattern
4073 @item @samp{vec_interleave_high@var{m}}
4074 Merge high elements of the two input vectors into the output vector. The output
4075 and input vectors should have the same modes (@code{N} elements). The high
4076 @code{N/2} elements of the first input vector are interleaved with the high
4077 @code{N/2} elements of the second input vector.
4079 @cindex @code{vec_interleave_low@var{m}} instruction pattern
4080 @item @samp{vec_interleave_low@var{m}}
4081 Merge low elements of the two input vectors into the output vector. The output
4082 and input vectors should have the same modes (@code{N} elements). The low
4083 @code{N/2} elements of the first input vector are interleaved with the low
4084 @code{N/2} elements of the second input vector.
4086 @cindex @code{vec_init@var{m}} instruction pattern
4087 @item @samp{vec_init@var{m}}
4088 Initialize the vector to given values. Operand 0 is the vector to initialize
4089 and operand 1 is parallel containing values for individual fields.
4091 @cindex @code{vcond@var{m}@var{n}} instruction pattern
4092 @item @samp{vcond@var{m}@var{n}}
4093 Output a conditional vector move. Operand 0 is the destination to
4094 receive a combination of operand 1 and operand 2, which are of mode @var{m},
4095 dependent on the outcome of the predicate in operand 3 which is a
4096 vector comparison with operands of mode @var{n} in operands 4 and 5. The
4097 modes @var{m} and @var{n} should have the same size. Operand 0
4098 will be set to the value @var{op1} & @var{msk} | @var{op2} & ~@var{msk}
4099 where @var{msk} is computed by element-wise evaluation of the vector
4100 comparison with a truth value of all-ones and a false value of all-zeros.
4102 @cindex @code{vec_perm@var{m}} instruction pattern
4103 @item @samp{vec_perm@var{m}}
4104 Output a (variable) vector permutation. Operand 0 is the destination
4105 to receive elements from operand 1 and operand 2, which are of mode
4106 @var{m}. Operand 3 is the @dfn{selector}. It is an integral mode
4107 vector of the same width and number of elements as mode @var{m}.
4109 The input elements are numbered from 0 in operand 1 through
4110 @math{2*@var{N}-1} in operand 2. The elements of the selector must
4111 be computed modulo @math{2*@var{N}}. Note that if
4112 @code{rtx_equal_p(operand1, operand2)}, this can be implemented
4113 with just operand 1 and selector elements modulo @var{N}.
4115 In order to make things easy for a number of targets, if there is no
4116 @samp{vec_perm} pattern for mode @var{m}, but there is for mode @var{q}
4117 where @var{q} is a vector of @code{QImode} of the same width as @var{m},
4118 the middle-end will lower the mode @var{m} @code{VEC_PERM_EXPR} to
4121 @cindex @code{vec_perm_const@var{m}} instruction pattern
4122 @item @samp{vec_perm_const@var{m}}
4123 Like @samp{vec_perm} except that the permutation is a compile-time
4124 constant. That is, operand 3, the @dfn{selector}, is a @code{CONST_VECTOR}.
4126 Some targets cannot perform a permutation with a variable selector,
4127 but can efficiently perform a constant permutation. Further, the
4128 target hook @code{vec_perm_ok} is queried to determine if the
4129 specific constant permutation is available efficiently; the named
4130 pattern is never expanded without @code{vec_perm_ok} returning true.
4132 There is no need for a target to supply both @samp{vec_perm@var{m}}
4133 and @samp{vec_perm_const@var{m}} if the former can trivially implement
4134 the operation with, say, the vector constant loaded into a register.
4136 @cindex @code{push@var{m}1} instruction pattern
4137 @item @samp{push@var{m}1}
4138 Output a push instruction. Operand 0 is value to push. Used only when
4139 @code{PUSH_ROUNDING} is defined. For historical reason, this pattern may be
4140 missing and in such case an @code{mov} expander is used instead, with a
4141 @code{MEM} expression forming the push operation. The @code{mov} expander
4142 method is deprecated.
4144 @cindex @code{add@var{m}3} instruction pattern
4145 @item @samp{add@var{m}3}
4146 Add operand 2 and operand 1, storing the result in operand 0. All operands
4147 must have mode @var{m}. This can be used even on two-address machines, by
4148 means of constraints requiring operands 1 and 0 to be the same location.
4150 @cindex @code{ssadd@var{m}3} instruction pattern
4151 @cindex @code{usadd@var{m}3} instruction pattern
4152 @cindex @code{sub@var{m}3} instruction pattern
4153 @cindex @code{sssub@var{m}3} instruction pattern
4154 @cindex @code{ussub@var{m}3} instruction pattern
4155 @cindex @code{mul@var{m}3} instruction pattern
4156 @cindex @code{ssmul@var{m}3} instruction pattern
4157 @cindex @code{usmul@var{m}3} instruction pattern
4158 @cindex @code{div@var{m}3} instruction pattern
4159 @cindex @code{ssdiv@var{m}3} instruction pattern
4160 @cindex @code{udiv@var{m}3} instruction pattern
4161 @cindex @code{usdiv@var{m}3} instruction pattern
4162 @cindex @code{mod@var{m}3} instruction pattern
4163 @cindex @code{umod@var{m}3} instruction pattern
4164 @cindex @code{umin@var{m}3} instruction pattern
4165 @cindex @code{umax@var{m}3} instruction pattern
4166 @cindex @code{and@var{m}3} instruction pattern
4167 @cindex @code{ior@var{m}3} instruction pattern
4168 @cindex @code{xor@var{m}3} instruction pattern
4169 @item @samp{ssadd@var{m}3}, @samp{usadd@var{m}3}
4170 @item @samp{sub@var{m}3}, @samp{sssub@var{m}3}, @samp{ussub@var{m}3}
4171 @item @samp{mul@var{m}3}, @samp{ssmul@var{m}3}, @samp{usmul@var{m}3}
4172 @itemx @samp{div@var{m}3}, @samp{ssdiv@var{m}3}
4173 @itemx @samp{udiv@var{m}3}, @samp{usdiv@var{m}3}
4174 @itemx @samp{mod@var{m}3}, @samp{umod@var{m}3}
4175 @itemx @samp{umin@var{m}3}, @samp{umax@var{m}3}
4176 @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3}
4177 Similar, for other arithmetic operations.
4179 @cindex @code{fma@var{m}4} instruction pattern
4180 @item @samp{fma@var{m}4}
4181 Multiply operand 2 and operand 1, then add operand 3, storing the
4182 result in operand 0. All operands must have mode @var{m}. This
4183 pattern is used to implement the @code{fma}, @code{fmaf}, and
4184 @code{fmal} builtin functions from the ISO C99 standard. The
4185 @code{fma} operation may produce different results than doing the
4186 multiply followed by the add if the machine does not perform a
4187 rounding step between the operations.
4189 @cindex @code{fms@var{m}4} instruction pattern
4190 @item @samp{fms@var{m}4}
4191 Like @code{fma@var{m}4}, except operand 3 subtracted from the
4192 product instead of added to the product. This is represented
4196 (fma:@var{m} @var{op1} @var{op2} (neg:@var{m} @var{op3}))
4199 @cindex @code{fnma@var{m}4} instruction pattern
4200 @item @samp{fnma@var{m}4}
4201 Like @code{fma@var{m}4} except that the intermediate product
4202 is negated before being added to operand 3. This is represented
4206 (fma:@var{m} (neg:@var{m} @var{op1}) @var{op2} @var{op3})
4209 @cindex @code{fnms@var{m}4} instruction pattern
4210 @item @samp{fnms@var{m}4}
4211 Like @code{fms@var{m}4} except that the intermediate product
4212 is negated before subtracting operand 3. This is represented
4216 (fma:@var{m} (neg:@var{m} @var{op1}) @var{op2} (neg:@var{m} @var{op3}))
4219 @cindex @code{min@var{m}3} instruction pattern
4220 @cindex @code{max@var{m}3} instruction pattern
4221 @item @samp{smin@var{m}3}, @samp{smax@var{m}3}
4222 Signed minimum and maximum operations. When used with floating point,
4223 if both operands are zeros, or if either operand is @code{NaN}, then
4224 it is unspecified which of the two operands is returned as the result.
4226 @cindex @code{reduc_smin_@var{m}} instruction pattern
4227 @cindex @code{reduc_smax_@var{m}} instruction pattern
4228 @item @samp{reduc_smin_@var{m}}, @samp{reduc_smax_@var{m}}
4229 Find the signed minimum/maximum of the elements of a vector. The vector is
4230 operand 1, and the scalar result is stored in the least significant bits of
4231 operand 0 (also a vector). The output and input vector should have the same
4234 @cindex @code{reduc_umin_@var{m}} instruction pattern
4235 @cindex @code{reduc_umax_@var{m}} instruction pattern
4236 @item @samp{reduc_umin_@var{m}}, @samp{reduc_umax_@var{m}}
4237 Find the unsigned minimum/maximum of the elements of a vector. The vector is
4238 operand 1, and the scalar result is stored in the least significant bits of
4239 operand 0 (also a vector). The output and input vector should have the same
4242 @cindex @code{reduc_splus_@var{m}} instruction pattern
4243 @item @samp{reduc_splus_@var{m}}
4244 Compute the sum of the signed elements of a vector. The vector is operand 1,
4245 and the scalar result is stored in the least significant bits of operand 0
4246 (also a vector). The output and input vector should have the same modes.
4248 @cindex @code{reduc_uplus_@var{m}} instruction pattern
4249 @item @samp{reduc_uplus_@var{m}}
4250 Compute the sum of the unsigned elements of a vector. The vector is operand 1,
4251 and the scalar result is stored in the least significant bits of operand 0
4252 (also a vector). The output and input vector should have the same modes.
4254 @cindex @code{sdot_prod@var{m}} instruction pattern
4255 @item @samp{sdot_prod@var{m}}
4256 @cindex @code{udot_prod@var{m}} instruction pattern
4257 @item @samp{udot_prod@var{m}}
4258 Compute the sum of the products of two signed/unsigned elements.
4259 Operand 1 and operand 2 are of the same mode. Their product, which is of a
4260 wider mode, is computed and added to operand 3. Operand 3 is of a mode equal or
4261 wider than the mode of the product. The result is placed in operand 0, which
4262 is of the same mode as operand 3.
4264 @cindex @code{ssum_widen@var{m3}} instruction pattern
4265 @item @samp{ssum_widen@var{m3}}
4266 @cindex @code{usum_widen@var{m3}} instruction pattern
4267 @item @samp{usum_widen@var{m3}}
4268 Operands 0 and 2 are of the same mode, which is wider than the mode of
4269 operand 1. Add operand 1 to operand 2 and place the widened result in
4270 operand 0. (This is used express accumulation of elements into an accumulator
4273 @cindex @code{vec_shl_@var{m}} instruction pattern
4274 @cindex @code{vec_shr_@var{m}} instruction pattern
4275 @item @samp{vec_shl_@var{m}}, @samp{vec_shr_@var{m}}
4276 Whole vector left/right shift in bits.
4277 Operand 1 is a vector to be shifted.
4278 Operand 2 is an integer shift amount in bits.
4279 Operand 0 is where the resulting shifted vector is stored.
4280 The output and input vectors should have the same modes.
4282 @cindex @code{vec_pack_trunc_@var{m}} instruction pattern
4283 @item @samp{vec_pack_trunc_@var{m}}
4284 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
4285 are vectors of the same mode having N integral or floating point elements
4286 of size S@. Operand 0 is the resulting vector in which 2*N elements of
4287 size N/2 are concatenated after narrowing them down using truncation.
4289 @cindex @code{vec_pack_ssat_@var{m}} instruction pattern
4290 @cindex @code{vec_pack_usat_@var{m}} instruction pattern
4291 @item @samp{vec_pack_ssat_@var{m}}, @samp{vec_pack_usat_@var{m}}
4292 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
4293 are vectors of the same mode having N integral elements of size S.
4294 Operand 0 is the resulting vector in which the elements of the two input
4295 vectors are concatenated after narrowing them down using signed/unsigned
4296 saturating arithmetic.
4298 @cindex @code{vec_pack_sfix_trunc_@var{m}} instruction pattern
4299 @cindex @code{vec_pack_ufix_trunc_@var{m}} instruction pattern
4300 @item @samp{vec_pack_sfix_trunc_@var{m}}, @samp{vec_pack_ufix_trunc_@var{m}}
4301 Narrow, convert to signed/unsigned integral type and merge the elements
4302 of two vectors. Operands 1 and 2 are vectors of the same mode having N
4303 floating point elements of size S@. Operand 0 is the resulting vector
4304 in which 2*N elements of size N/2 are concatenated.
4306 @cindex @code{vec_unpacks_hi_@var{m}} instruction pattern
4307 @cindex @code{vec_unpacks_lo_@var{m}} instruction pattern
4308 @item @samp{vec_unpacks_hi_@var{m}}, @samp{vec_unpacks_lo_@var{m}}
4309 Extract and widen (promote) the high/low part of a vector of signed
4310 integral or floating point elements. The input vector (operand 1) has N
4311 elements of size S@. Widen (promote) the high/low elements of the vector
4312 using signed or floating point extension and place the resulting N/2
4313 values of size 2*S in the output vector (operand 0).
4315 @cindex @code{vec_unpacku_hi_@var{m}} instruction pattern
4316 @cindex @code{vec_unpacku_lo_@var{m}} instruction pattern
4317 @item @samp{vec_unpacku_hi_@var{m}}, @samp{vec_unpacku_lo_@var{m}}
4318 Extract and widen (promote) the high/low part of a vector of unsigned
4319 integral elements. The input vector (operand 1) has N elements of size S.
4320 Widen (promote) the high/low elements of the vector using zero extension and
4321 place the resulting N/2 values of size 2*S in the output vector (operand 0).
4323 @cindex @code{vec_unpacks_float_hi_@var{m}} instruction pattern
4324 @cindex @code{vec_unpacks_float_lo_@var{m}} instruction pattern
4325 @cindex @code{vec_unpacku_float_hi_@var{m}} instruction pattern
4326 @cindex @code{vec_unpacku_float_lo_@var{m}} instruction pattern
4327 @item @samp{vec_unpacks_float_hi_@var{m}}, @samp{vec_unpacks_float_lo_@var{m}}
4328 @itemx @samp{vec_unpacku_float_hi_@var{m}}, @samp{vec_unpacku_float_lo_@var{m}}
4329 Extract, convert to floating point type and widen the high/low part of a
4330 vector of signed/unsigned integral elements. The input vector (operand 1)
4331 has N elements of size S@. Convert the high/low elements of the vector using
4332 floating point conversion and place the resulting N/2 values of size 2*S in
4333 the output vector (operand 0).
4335 @cindex @code{vec_widen_umult_hi_@var{m}} instruction pattern
4336 @cindex @code{vec_widen_umult_lo__@var{m}} instruction pattern
4337 @cindex @code{vec_widen_smult_hi_@var{m}} instruction pattern
4338 @cindex @code{vec_widen_smult_lo_@var{m}} instruction pattern
4339 @item @samp{vec_widen_umult_hi_@var{m}}, @samp{vec_widen_umult_lo_@var{m}}
4340 @itemx @samp{vec_widen_smult_hi_@var{m}}, @samp{vec_widen_smult_lo_@var{m}}
4341 Signed/Unsigned widening multiplication. The two inputs (operands 1 and 2)
4342 are vectors with N signed/unsigned elements of size S@. Multiply the high/low
4343 elements of the two vectors, and put the N/2 products of size 2*S in the
4344 output vector (operand 0).
4346 @cindex @code{vec_widen_ushiftl_hi_@var{m}} instruction pattern
4347 @cindex @code{vec_widen_ushiftl_lo_@var{m}} instruction pattern
4348 @cindex @code{vec_widen_sshiftl_hi_@var{m}} instruction pattern
4349 @cindex @code{vec_widen_sshiftl_lo_@var{m}} instruction pattern
4350 @item @samp{vec_widen_ushiftl_hi_@var{m}}, @samp{vec_widen_ushiftl_lo_@var{m}}
4351 @itemx @samp{vec_widen_sshiftl_hi_@var{m}}, @samp{vec_widen_sshiftl_lo_@var{m}}
4352 Signed/Unsigned widening shift left. The first input (operand 1) is a vector
4353 with N signed/unsigned elements of size S@. Operand 2 is a constant. Shift
4354 the high/low elements of operand 1, and put the N/2 results of size 2*S in the
4355 output vector (operand 0).
4357 @cindex @code{mulhisi3} instruction pattern
4358 @item @samp{mulhisi3}
4359 Multiply operands 1 and 2, which have mode @code{HImode}, and store
4360 a @code{SImode} product in operand 0.
4362 @cindex @code{mulqihi3} instruction pattern
4363 @cindex @code{mulsidi3} instruction pattern
4364 @item @samp{mulqihi3}, @samp{mulsidi3}
4365 Similar widening-multiplication instructions of other widths.
4367 @cindex @code{umulqihi3} instruction pattern
4368 @cindex @code{umulhisi3} instruction pattern
4369 @cindex @code{umulsidi3} instruction pattern
4370 @item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3}
4371 Similar widening-multiplication instructions that do unsigned
4374 @cindex @code{usmulqihi3} instruction pattern
4375 @cindex @code{usmulhisi3} instruction pattern
4376 @cindex @code{usmulsidi3} instruction pattern
4377 @item @samp{usmulqihi3}, @samp{usmulhisi3}, @samp{usmulsidi3}
4378 Similar widening-multiplication instructions that interpret the first
4379 operand as unsigned and the second operand as signed, then do a signed
4382 @cindex @code{smul@var{m}3_highpart} instruction pattern
4383 @item @samp{smul@var{m}3_highpart}
4384 Perform a signed multiplication of operands 1 and 2, which have mode
4385 @var{m}, and store the most significant half of the product in operand 0.
4386 The least significant half of the product is discarded.
4388 @cindex @code{umul@var{m}3_highpart} instruction pattern
4389 @item @samp{umul@var{m}3_highpart}
4390 Similar, but the multiplication is unsigned.
4392 @cindex @code{madd@var{m}@var{n}4} instruction pattern
4393 @item @samp{madd@var{m}@var{n}4}
4394 Multiply operands 1 and 2, sign-extend them to mode @var{n}, add
4395 operand 3, and store the result in operand 0. Operands 1 and 2
4396 have mode @var{m} and operands 0 and 3 have mode @var{n}.
4397 Both modes must be integer or fixed-point modes and @var{n} must be twice
4398 the size of @var{m}.
4400 In other words, @code{madd@var{m}@var{n}4} is like
4401 @code{mul@var{m}@var{n}3} except that it also adds operand 3.
4403 These instructions are not allowed to @code{FAIL}.
4405 @cindex @code{umadd@var{m}@var{n}4} instruction pattern
4406 @item @samp{umadd@var{m}@var{n}4}
4407 Like @code{madd@var{m}@var{n}4}, but zero-extend the multiplication
4408 operands instead of sign-extending them.
4410 @cindex @code{ssmadd@var{m}@var{n}4} instruction pattern
4411 @item @samp{ssmadd@var{m}@var{n}4}
4412 Like @code{madd@var{m}@var{n}4}, but all involved operations must be
4415 @cindex @code{usmadd@var{m}@var{n}4} instruction pattern
4416 @item @samp{usmadd@var{m}@var{n}4}
4417 Like @code{umadd@var{m}@var{n}4}, but all involved operations must be
4418 unsigned-saturating.
4420 @cindex @code{msub@var{m}@var{n}4} instruction pattern
4421 @item @samp{msub@var{m}@var{n}4}
4422 Multiply operands 1 and 2, sign-extend them to mode @var{n}, subtract the
4423 result from operand 3, and store the result in operand 0. Operands 1 and 2
4424 have mode @var{m} and operands 0 and 3 have mode @var{n}.
4425 Both modes must be integer or fixed-point modes and @var{n} must be twice
4426 the size of @var{m}.
4428 In other words, @code{msub@var{m}@var{n}4} is like
4429 @code{mul@var{m}@var{n}3} except that it also subtracts the result
4432 These instructions are not allowed to @code{FAIL}.
4434 @cindex @code{umsub@var{m}@var{n}4} instruction pattern
4435 @item @samp{umsub@var{m}@var{n}4}
4436 Like @code{msub@var{m}@var{n}4}, but zero-extend the multiplication
4437 operands instead of sign-extending them.
4439 @cindex @code{ssmsub@var{m}@var{n}4} instruction pattern
4440 @item @samp{ssmsub@var{m}@var{n}4}
4441 Like @code{msub@var{m}@var{n}4}, but all involved operations must be
4444 @cindex @code{usmsub@var{m}@var{n}4} instruction pattern
4445 @item @samp{usmsub@var{m}@var{n}4}
4446 Like @code{umsub@var{m}@var{n}4}, but all involved operations must be
4447 unsigned-saturating.
4449 @cindex @code{divmod@var{m}4} instruction pattern
4450 @item @samp{divmod@var{m}4}
4451 Signed division that produces both a quotient and a remainder.
4452 Operand 1 is divided by operand 2 to produce a quotient stored
4453 in operand 0 and a remainder stored in operand 3.
4455 For machines with an instruction that produces both a quotient and a
4456 remainder, provide a pattern for @samp{divmod@var{m}4} but do not
4457 provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This
4458 allows optimization in the relatively common case when both the quotient
4459 and remainder are computed.
4461 If an instruction that just produces a quotient or just a remainder
4462 exists and is more efficient than the instruction that produces both,
4463 write the output routine of @samp{divmod@var{m}4} to call
4464 @code{find_reg_note} and look for a @code{REG_UNUSED} note on the
4465 quotient or remainder and generate the appropriate instruction.
4467 @cindex @code{udivmod@var{m}4} instruction pattern
4468 @item @samp{udivmod@var{m}4}
4469 Similar, but does unsigned division.
4471 @anchor{shift patterns}
4472 @cindex @code{ashl@var{m}3} instruction pattern
4473 @cindex @code{ssashl@var{m}3} instruction pattern
4474 @cindex @code{usashl@var{m}3} instruction pattern
4475 @item @samp{ashl@var{m}3}, @samp{ssashl@var{m}3}, @samp{usashl@var{m}3}
4476 Arithmetic-shift operand 1 left by a number of bits specified by operand
4477 2, and store the result in operand 0. Here @var{m} is the mode of
4478 operand 0 and operand 1; operand 2's mode is specified by the
4479 instruction pattern, and the compiler will convert the operand to that
4480 mode before generating the instruction. The meaning of out-of-range shift
4481 counts can optionally be specified by @code{TARGET_SHIFT_TRUNCATION_MASK}.
4482 @xref{TARGET_SHIFT_TRUNCATION_MASK}. Operand 2 is always a scalar type.
4484 @cindex @code{ashr@var{m}3} instruction pattern
4485 @cindex @code{lshr@var{m}3} instruction pattern
4486 @cindex @code{rotl@var{m}3} instruction pattern
4487 @cindex @code{rotr@var{m}3} instruction pattern
4488 @item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3}
4489 Other shift and rotate instructions, analogous to the
4490 @code{ashl@var{m}3} instructions. Operand 2 is always a scalar type.
4492 @cindex @code{vashl@var{m}3} instruction pattern
4493 @cindex @code{vashr@var{m}3} instruction pattern
4494 @cindex @code{vlshr@var{m}3} instruction pattern
4495 @cindex @code{vrotl@var{m}3} instruction pattern
4496 @cindex @code{vrotr@var{m}3} instruction pattern
4497 @item @samp{vashl@var{m}3}, @samp{vashr@var{m}3}, @samp{vlshr@var{m}3}, @samp{vrotl@var{m}3}, @samp{vrotr@var{m}3}
4498 Vector shift and rotate instructions that take vectors as operand 2
4499 instead of a scalar type.
4501 @cindex @code{neg@var{m}2} instruction pattern
4502 @cindex @code{ssneg@var{m}2} instruction pattern
4503 @cindex @code{usneg@var{m}2} instruction pattern
4504 @item @samp{neg@var{m}2}, @samp{ssneg@var{m}2}, @samp{usneg@var{m}2}
4505 Negate operand 1 and store the result in operand 0.
4507 @cindex @code{abs@var{m}2} instruction pattern
4508 @item @samp{abs@var{m}2}
4509 Store the absolute value of operand 1 into operand 0.
4511 @cindex @code{sqrt@var{m}2} instruction pattern
4512 @item @samp{sqrt@var{m}2}
4513 Store the square root of operand 1 into operand 0.
4515 The @code{sqrt} built-in function of C always uses the mode which
4516 corresponds to the C data type @code{double} and the @code{sqrtf}
4517 built-in function uses the mode which corresponds to the C data
4520 @cindex @code{fmod@var{m}3} instruction pattern
4521 @item @samp{fmod@var{m}3}
4522 Store the remainder of dividing operand 1 by operand 2 into
4523 operand 0, rounded towards zero to an integer.
4525 The @code{fmod} built-in function of C always uses the mode which
4526 corresponds to the C data type @code{double} and the @code{fmodf}
4527 built-in function uses the mode which corresponds to the C data
4530 @cindex @code{remainder@var{m}3} instruction pattern
4531 @item @samp{remainder@var{m}3}
4532 Store the remainder of dividing operand 1 by operand 2 into
4533 operand 0, rounded to the nearest integer.
4535 The @code{remainder} built-in function of C always uses the mode
4536 which corresponds to the C data type @code{double} and the
4537 @code{remainderf} built-in function uses the mode which corresponds
4538 to the C data type @code{float}.
4540 @cindex @code{cos@var{m}2} instruction pattern
4541 @item @samp{cos@var{m}2}
4542 Store the cosine of operand 1 into operand 0.
4544 The @code{cos} built-in function of C always uses the mode which
4545 corresponds to the C data type @code{double} and the @code{cosf}
4546 built-in function uses the mode which corresponds to the C data
4549 @cindex @code{sin@var{m}2} instruction pattern
4550 @item @samp{sin@var{m}2}
4551 Store the sine of operand 1 into operand 0.
4553 The @code{sin} built-in function of C always uses the mode which
4554 corresponds to the C data type @code{double} and the @code{sinf}
4555 built-in function uses the mode which corresponds to the C data
4558 @cindex @code{exp@var{m}2} instruction pattern
4559 @item @samp{exp@var{m}2}
4560 Store the exponential of operand 1 into operand 0.
4562 The @code{exp} built-in function of C always uses the mode which
4563 corresponds to the C data type @code{double} and the @code{expf}
4564 built-in function uses the mode which corresponds to the C data
4567 @cindex @code{log@var{m}2} instruction pattern
4568 @item @samp{log@var{m}2}
4569 Store the natural logarithm of operand 1 into operand 0.
4571 The @code{log} built-in function of C always uses the mode which
4572 corresponds to the C data type @code{double} and the @code{logf}
4573 built-in function uses the mode which corresponds to the C data
4576 @cindex @code{pow@var{m}3} instruction pattern
4577 @item @samp{pow@var{m}3}
4578 Store the value of operand 1 raised to the exponent operand 2
4581 The @code{pow} built-in function of C always uses the mode which
4582 corresponds to the C data type @code{double} and the @code{powf}
4583 built-in function uses the mode which corresponds to the C data
4586 @cindex @code{atan2@var{m}3} instruction pattern
4587 @item @samp{atan2@var{m}3}
4588 Store the arc tangent (inverse tangent) of operand 1 divided by
4589 operand 2 into operand 0, using the signs of both arguments to
4590 determine the quadrant of the result.
4592 The @code{atan2} built-in function of C always uses the mode which
4593 corresponds to the C data type @code{double} and the @code{atan2f}
4594 built-in function uses the mode which corresponds to the C data
4597 @cindex @code{floor@var{m}2} instruction pattern
4598 @item @samp{floor@var{m}2}
4599 Store the largest integral value not greater than argument.
4601 The @code{floor} built-in function of C always uses the mode which
4602 corresponds to the C data type @code{double} and the @code{floorf}
4603 built-in function uses the mode which corresponds to the C data
4606 @cindex @code{btrunc@var{m}2} instruction pattern
4607 @item @samp{btrunc@var{m}2}
4608 Store the argument rounded to integer towards zero.
4610 The @code{trunc} built-in function of C always uses the mode which
4611 corresponds to the C data type @code{double} and the @code{truncf}
4612 built-in function uses the mode which corresponds to the C data
4615 @cindex @code{round@var{m}2} instruction pattern
4616 @item @samp{round@var{m}2}
4617 Store the argument rounded to integer away from zero.
4619 The @code{round} built-in function of C always uses the mode which
4620 corresponds to the C data type @code{double} and the @code{roundf}
4621 built-in function uses the mode which corresponds to the C data
4624 @cindex @code{ceil@var{m}2} instruction pattern
4625 @item @samp{ceil@var{m}2}
4626 Store the argument rounded to integer away from zero.
4628 The @code{ceil} built-in function of C always uses the mode which
4629 corresponds to the C data type @code{double} and the @code{ceilf}
4630 built-in function uses the mode which corresponds to the C data
4633 @cindex @code{nearbyint@var{m}2} instruction pattern
4634 @item @samp{nearbyint@var{m}2}
4635 Store the argument rounded according to the default rounding mode
4637 The @code{nearbyint} built-in function of C always uses the mode which
4638 corresponds to the C data type @code{double} and the @code{nearbyintf}
4639 built-in function uses the mode which corresponds to the C data
4642 @cindex @code{rint@var{m}2} instruction pattern
4643 @item @samp{rint@var{m}2}
4644 Store the argument rounded according to the default rounding mode and
4645 raise the inexact exception when the result differs in value from
4648 The @code{rint} built-in function of C always uses the mode which
4649 corresponds to the C data type @code{double} and the @code{rintf}
4650 built-in function uses the mode which corresponds to the C data
4653 @cindex @code{lrint@var{m}@var{n}2}
4654 @item @samp{lrint@var{m}@var{n}2}
4655 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4656 point mode @var{n} as a signed number according to the current
4657 rounding mode and store in operand 0 (which has mode @var{n}).
4659 @cindex @code{lround@var{m}@var{n}2}
4660 @item @samp{lround@var{m}@var{n}2}
4661 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4662 point mode @var{n} as a signed number rounding to nearest and away
4663 from zero and store in operand 0 (which has mode @var{n}).
4665 @cindex @code{lfloor@var{m}@var{n}2}
4666 @item @samp{lfloor@var{m}@var{n}2}
4667 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4668 point mode @var{n} as a signed number rounding down and store in
4669 operand 0 (which has mode @var{n}).
4671 @cindex @code{lceil@var{m}@var{n}2}
4672 @item @samp{lceil@var{m}@var{n}2}
4673 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4674 point mode @var{n} as a signed number rounding up and store in
4675 operand 0 (which has mode @var{n}).
4677 @cindex @code{copysign@var{m}3} instruction pattern
4678 @item @samp{copysign@var{m}3}
4679 Store a value with the magnitude of operand 1 and the sign of operand
4682 The @code{copysign} built-in function of C always uses the mode which
4683 corresponds to the C data type @code{double} and the @code{copysignf}
4684 built-in function uses the mode which corresponds to the C data
4687 @cindex @code{ffs@var{m}2} instruction pattern
4688 @item @samp{ffs@var{m}2}
4689 Store into operand 0 one plus the index of the least significant 1-bit
4690 of operand 1. If operand 1 is zero, store zero. @var{m} is the mode
4691 of operand 0; operand 1's mode is specified by the instruction
4692 pattern, and the compiler will convert the operand to that mode before
4693 generating the instruction.
4695 The @code{ffs} built-in function of C always uses the mode which
4696 corresponds to the C data type @code{int}.
4698 @cindex @code{clz@var{m}2} instruction pattern
4699 @item @samp{clz@var{m}2}
4700 Store into operand 0 the number of leading 0-bits in @var{x}, starting
4701 at the most significant bit position. If @var{x} is 0, the
4702 @code{CLZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
4703 the result is undefined or has a useful value.
4704 @var{m} is the mode of operand 0; operand 1's mode is
4705 specified by the instruction pattern, and the compiler will convert the
4706 operand to that mode before generating the instruction.
4708 @cindex @code{ctz@var{m}2} instruction pattern
4709 @item @samp{ctz@var{m}2}
4710 Store into operand 0 the number of trailing 0-bits in @var{x}, starting
4711 at the least significant bit position. If @var{x} is 0, the
4712 @code{CTZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
4713 the result is undefined or has a useful value.
4714 @var{m} is the mode of operand 0; operand 1's mode is
4715 specified by the instruction pattern, and the compiler will convert the
4716 operand to that mode before generating the instruction.
4718 @cindex @code{popcount@var{m}2} instruction pattern
4719 @item @samp{popcount@var{m}2}
4720 Store into operand 0 the number of 1-bits in @var{x}. @var{m} is the
4721 mode of operand 0; operand 1's mode is specified by the instruction
4722 pattern, and the compiler will convert the operand to that mode before
4723 generating the instruction.
4725 @cindex @code{parity@var{m}2} instruction pattern
4726 @item @samp{parity@var{m}2}
4727 Store into operand 0 the parity of @var{x}, i.e.@: the number of 1-bits
4728 in @var{x} modulo 2. @var{m} is the mode of operand 0; operand 1's mode
4729 is specified by the instruction pattern, and the compiler will convert
4730 the operand to that mode before generating the instruction.
4732 @cindex @code{one_cmpl@var{m}2} instruction pattern
4733 @item @samp{one_cmpl@var{m}2}
4734 Store the bitwise-complement of operand 1 into operand 0.
4736 @cindex @code{movmem@var{m}} instruction pattern
4737 @item @samp{movmem@var{m}}
4738 Block move instruction. The destination and source blocks of memory
4739 are the first two operands, and both are @code{mem:BLK}s with an
4740 address in mode @code{Pmode}.
4742 The number of bytes to move is the third operand, in mode @var{m}.
4743 Usually, you specify @code{word_mode} for @var{m}. However, if you can
4744 generate better code knowing the range of valid lengths is smaller than
4745 those representable in a full word, you should provide a pattern with a
4746 mode corresponding to the range of values you can handle efficiently
4747 (e.g., @code{QImode} for values in the range 0--127; note we avoid numbers
4748 that appear negative) and also a pattern with @code{word_mode}.
4750 The fourth operand is the known shared alignment of the source and
4751 destination, in the form of a @code{const_int} rtx. Thus, if the
4752 compiler knows that both source and destination are word-aligned,
4753 it may provide the value 4 for this operand.
4755 Optional operands 5 and 6 specify expected alignment and size of block
4756 respectively. The expected alignment differs from alignment in operand 4
4757 in a way that the blocks are not required to be aligned according to it in
4758 all cases. This expected alignment is also in bytes, just like operand 4.
4759 Expected size, when unknown, is set to @code{(const_int -1)}.
4761 Descriptions of multiple @code{movmem@var{m}} patterns can only be
4762 beneficial if the patterns for smaller modes have fewer restrictions
4763 on their first, second and fourth operands. Note that the mode @var{m}
4764 in @code{movmem@var{m}} does not impose any restriction on the mode of
4765 individually moved data units in the block.
4767 These patterns need not give special consideration to the possibility
4768 that the source and destination strings might overlap.
4770 @cindex @code{movstr} instruction pattern
4772 String copy instruction, with @code{stpcpy} semantics. Operand 0 is
4773 an output operand in mode @code{Pmode}. The addresses of the
4774 destination and source strings are operands 1 and 2, and both are
4775 @code{mem:BLK}s with addresses in mode @code{Pmode}. The execution of
4776 the expansion of this pattern should store in operand 0 the address in
4777 which the @code{NUL} terminator was stored in the destination string.
4779 @cindex @code{setmem@var{m}} instruction pattern
4780 @item @samp{setmem@var{m}}
4781 Block set instruction. The destination string is the first operand,
4782 given as a @code{mem:BLK} whose address is in mode @code{Pmode}. The
4783 number of bytes to set is the second operand, in mode @var{m}. The value to
4784 initialize the memory with is the third operand. Targets that only support the
4785 clearing of memory should reject any value that is not the constant 0. See
4786 @samp{movmem@var{m}} for a discussion of the choice of mode.
4788 The fourth operand is the known alignment of the destination, in the form
4789 of a @code{const_int} rtx. Thus, if the compiler knows that the
4790 destination is word-aligned, it may provide the value 4 for this
4793 Optional operands 5 and 6 specify expected alignment and size of block
4794 respectively. The expected alignment differs from alignment in operand 4
4795 in a way that the blocks are not required to be aligned according to it in
4796 all cases. This expected alignment is also in bytes, just like operand 4.
4797 Expected size, when unknown, is set to @code{(const_int -1)}.
4799 The use for multiple @code{setmem@var{m}} is as for @code{movmem@var{m}}.
4801 @cindex @code{cmpstrn@var{m}} instruction pattern
4802 @item @samp{cmpstrn@var{m}}
4803 String compare instruction, with five operands. Operand 0 is the output;
4804 it has mode @var{m}. The remaining four operands are like the operands
4805 of @samp{movmem@var{m}}. The two memory blocks specified are compared
4806 byte by byte in lexicographic order starting at the beginning of each
4807 string. The instruction is not allowed to prefetch more than one byte
4808 at a time since either string may end in the first byte and reading past
4809 that may access an invalid page or segment and cause a fault. The
4810 comparison terminates early if the fetched bytes are different or if
4811 they are equal to zero. The effect of the instruction is to store a
4812 value in operand 0 whose sign indicates the result of the comparison.
4814 @cindex @code{cmpstr@var{m}} instruction pattern
4815 @item @samp{cmpstr@var{m}}
4816 String compare instruction, without known maximum length. Operand 0 is the
4817 output; it has mode @var{m}. The second and third operand are the blocks of
4818 memory to be compared; both are @code{mem:BLK} with an address in mode
4821 The fourth operand is the known shared alignment of the source and
4822 destination, in the form of a @code{const_int} rtx. Thus, if the
4823 compiler knows that both source and destination are word-aligned,
4824 it may provide the value 4 for this operand.
4826 The two memory blocks specified are compared byte by byte in lexicographic
4827 order starting at the beginning of each string. The instruction is not allowed
4828 to prefetch more than one byte at a time since either string may end in the
4829 first byte and reading past that may access an invalid page or segment and
4830 cause a fault. The comparison will terminate when the fetched bytes
4831 are different or if they are equal to zero. The effect of the
4832 instruction is to store a value in operand 0 whose sign indicates the
4833 result of the comparison.
4835 @cindex @code{cmpmem@var{m}} instruction pattern
4836 @item @samp{cmpmem@var{m}}
4837 Block compare instruction, with five operands like the operands
4838 of @samp{cmpstr@var{m}}. The two memory blocks specified are compared
4839 byte by byte in lexicographic order starting at the beginning of each
4840 block. Unlike @samp{cmpstr@var{m}} the instruction can prefetch
4841 any bytes in the two memory blocks. Also unlike @samp{cmpstr@var{m}}
4842 the comparison will not stop if both bytes are zero. The effect of
4843 the instruction is to store a value in operand 0 whose sign indicates
4844 the result of the comparison.
4846 @cindex @code{strlen@var{m}} instruction pattern
4847 @item @samp{strlen@var{m}}
4848 Compute the length of a string, with three operands.
4849 Operand 0 is the result (of mode @var{m}), operand 1 is
4850 a @code{mem} referring to the first character of the string,
4851 operand 2 is the character to search for (normally zero),
4852 and operand 3 is a constant describing the known alignment
4853 of the beginning of the string.
4855 @cindex @code{float@var{m}@var{n}2} instruction pattern
4856 @item @samp{float@var{m}@var{n}2}
4857 Convert signed integer operand 1 (valid for fixed point mode @var{m}) to
4858 floating point mode @var{n} and store in operand 0 (which has mode
4861 @cindex @code{floatuns@var{m}@var{n}2} instruction pattern
4862 @item @samp{floatuns@var{m}@var{n}2}
4863 Convert unsigned integer operand 1 (valid for fixed point mode @var{m})
4864 to floating point mode @var{n} and store in operand 0 (which has mode
4867 @cindex @code{fix@var{m}@var{n}2} instruction pattern
4868 @item @samp{fix@var{m}@var{n}2}
4869 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4870 point mode @var{n} as a signed number and store in operand 0 (which
4871 has mode @var{n}). This instruction's result is defined only when
4872 the value of operand 1 is an integer.
4874 If the machine description defines this pattern, it also needs to
4875 define the @code{ftrunc} pattern.
4877 @cindex @code{fixuns@var{m}@var{n}2} instruction pattern
4878 @item @samp{fixuns@var{m}@var{n}2}
4879 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4880 point mode @var{n} as an unsigned number and store in operand 0 (which
4881 has mode @var{n}). This instruction's result is defined only when the
4882 value of operand 1 is an integer.
4884 @cindex @code{ftrunc@var{m}2} instruction pattern
4885 @item @samp{ftrunc@var{m}2}
4886 Convert operand 1 (valid for floating point mode @var{m}) to an
4887 integer value, still represented in floating point mode @var{m}, and
4888 store it in operand 0 (valid for floating point mode @var{m}).
4890 @cindex @code{fix_trunc@var{m}@var{n}2} instruction pattern
4891 @item @samp{fix_trunc@var{m}@var{n}2}
4892 Like @samp{fix@var{m}@var{n}2} but works for any floating point value
4893 of mode @var{m} by converting the value to an integer.
4895 @cindex @code{fixuns_trunc@var{m}@var{n}2} instruction pattern
4896 @item @samp{fixuns_trunc@var{m}@var{n}2}
4897 Like @samp{fixuns@var{m}@var{n}2} but works for any floating point
4898 value of mode @var{m} by converting the value to an integer.
4900 @cindex @code{trunc@var{m}@var{n}2} instruction pattern
4901 @item @samp{trunc@var{m}@var{n}2}
4902 Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and
4903 store in operand 0 (which has mode @var{n}). Both modes must be fixed
4904 point or both floating point.
4906 @cindex @code{extend@var{m}@var{n}2} instruction pattern
4907 @item @samp{extend@var{m}@var{n}2}
4908 Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
4909 store in operand 0 (which has mode @var{n}). Both modes must be fixed
4910 point or both floating point.
4912 @cindex @code{zero_extend@var{m}@var{n}2} instruction pattern
4913 @item @samp{zero_extend@var{m}@var{n}2}
4914 Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
4915 store in operand 0 (which has mode @var{n}). Both modes must be fixed
4918 @cindex @code{fract@var{m}@var{n}2} instruction pattern
4919 @item @samp{fract@var{m}@var{n}2}
4920 Convert operand 1 of mode @var{m} to mode @var{n} and store in
4921 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
4922 could be fixed-point to fixed-point, signed integer to fixed-point,
4923 fixed-point to signed integer, floating-point to fixed-point,
4924 or fixed-point to floating-point.
4925 When overflows or underflows happen, the results are undefined.
4927 @cindex @code{satfract@var{m}@var{n}2} instruction pattern
4928 @item @samp{satfract@var{m}@var{n}2}
4929 Convert operand 1 of mode @var{m} to mode @var{n} and store in
4930 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
4931 could be fixed-point to fixed-point, signed integer to fixed-point,
4932 or floating-point to fixed-point.
4933 When overflows or underflows happen, the instruction saturates the
4934 results to the maximum or the minimum.
4936 @cindex @code{fractuns@var{m}@var{n}2} instruction pattern
4937 @item @samp{fractuns@var{m}@var{n}2}
4938 Convert operand 1 of mode @var{m} to mode @var{n} and store in
4939 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
4940 could be unsigned integer to fixed-point, or
4941 fixed-point to unsigned integer.
4942 When overflows or underflows happen, the results are undefined.
4944 @cindex @code{satfractuns@var{m}@var{n}2} instruction pattern
4945 @item @samp{satfractuns@var{m}@var{n}2}
4946 Convert unsigned integer operand 1 of mode @var{m} to fixed-point mode
4947 @var{n} and store in operand 0 (which has mode @var{n}).
4948 When overflows or underflows happen, the instruction saturates the
4949 results to the maximum or the minimum.
4951 @cindex @code{extv} instruction pattern
4953 Extract a bit-field from operand 1 (a register or memory operand), where
4954 operand 2 specifies the width in bits and operand 3 the starting bit,
4955 and store it in operand 0. Operand 0 must have mode @code{word_mode}.
4956 Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often
4957 @code{word_mode} is allowed only for registers. Operands 2 and 3 must
4958 be valid for @code{word_mode}.
4960 The RTL generation pass generates this instruction only with constants
4961 for operands 2 and 3 and the constant is never zero for operand 2.
4963 The bit-field value is sign-extended to a full word integer
4964 before it is stored in operand 0.
4966 @cindex @code{extzv} instruction pattern
4968 Like @samp{extv} except that the bit-field value is zero-extended.
4970 @cindex @code{insv} instruction pattern
4972 Store operand 3 (which must be valid for @code{word_mode}) into a
4973 bit-field in operand 0, where operand 1 specifies the width in bits and
4974 operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or
4975 @code{word_mode}; often @code{word_mode} is allowed only for registers.
4976 Operands 1 and 2 must be valid for @code{word_mode}.
4978 The RTL generation pass generates this instruction only with constants
4979 for operands 1 and 2 and the constant is never zero for operand 1.
4981 @cindex @code{mov@var{mode}cc} instruction pattern
4982 @item @samp{mov@var{mode}cc}
4983 Conditionally move operand 2 or operand 3 into operand 0 according to the
4984 comparison in operand 1. If the comparison is true, operand 2 is moved
4985 into operand 0, otherwise operand 3 is moved.
4987 The mode of the operands being compared need not be the same as the operands
4988 being moved. Some machines, sparc64 for example, have instructions that
4989 conditionally move an integer value based on the floating point condition
4990 codes and vice versa.
4992 If the machine does not have conditional move instructions, do not
4993 define these patterns.
4995 @cindex @code{add@var{mode}cc} instruction pattern
4996 @item @samp{add@var{mode}cc}
4997 Similar to @samp{mov@var{mode}cc} but for conditional addition. Conditionally
4998 move operand 2 or (operands 2 + operand 3) into operand 0 according to the
4999 comparison in operand 1. If the comparison is true, operand 2 is moved into
5000 operand 0, otherwise (operand 2 + operand 3) is moved.
5002 @cindex @code{cstore@var{mode}4} instruction pattern
5003 @item @samp{cstore@var{mode}4}
5004 Store zero or nonzero in operand 0 according to whether a comparison
5005 is true. Operand 1 is a comparison operator. Operand 2 and operand 3
5006 are the first and second operand of the comparison, respectively.
5007 You specify the mode that operand 0 must have when you write the
5008 @code{match_operand} expression. The compiler automatically sees which
5009 mode you have used and supplies an operand of that mode.
5011 The value stored for a true condition must have 1 as its low bit, or
5012 else must be negative. Otherwise the instruction is not suitable and
5013 you should omit it from the machine description. You describe to the
5014 compiler exactly which value is stored by defining the macro
5015 @code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be
5016 found that can be used for all the possible comparison operators, you
5017 should pick one and use a @code{define_expand} to map all results
5018 onto the one you chose.
5020 These operations may @code{FAIL}, but should do so only in relatively
5021 uncommon cases; if they would @code{FAIL} for common cases involving
5022 integer comparisons, it is best to restrict the predicates to not
5023 allow these operands. Likewise if a given comparison operator will
5024 always fail, independent of the operands (for floating-point modes, the
5025 @code{ordered_comparison_operator} predicate is often useful in this case).
5027 If this pattern is omitted, the compiler will generate a conditional
5028 branch---for example, it may copy a constant one to the target and branching
5029 around an assignment of zero to the target---or a libcall. If the predicate
5030 for operand 1 only rejects some operators, it will also try reordering the
5031 operands and/or inverting the result value (e.g.@: by an exclusive OR).
5032 These possibilities could be cheaper or equivalent to the instructions
5033 used for the @samp{cstore@var{mode}4} pattern followed by those required
5034 to convert a positive result from @code{STORE_FLAG_VALUE} to 1; in this
5035 case, you can and should make operand 1's predicate reject some operators
5036 in the @samp{cstore@var{mode}4} pattern, or remove the pattern altogether
5037 from the machine description.
5039 @cindex @code{cbranch@var{mode}4} instruction pattern
5040 @item @samp{cbranch@var{mode}4}
5041 Conditional branch instruction combined with a compare instruction.
5042 Operand 0 is a comparison operator. Operand 1 and operand 2 are the
5043 first and second operands of the comparison, respectively. Operand 3
5044 is a @code{label_ref} that refers to the label to jump to.
5046 @cindex @code{jump} instruction pattern
5048 A jump inside a function; an unconditional branch. Operand 0 is the
5049 @code{label_ref} of the label to jump to. This pattern name is mandatory
5052 @cindex @code{call} instruction pattern
5054 Subroutine call instruction returning no value. Operand 0 is the
5055 function to call; operand 1 is the number of bytes of arguments pushed
5056 as a @code{const_int}; operand 2 is the number of registers used as
5059 On most machines, operand 2 is not actually stored into the RTL
5060 pattern. It is supplied for the sake of some RISC machines which need
5061 to put this information into the assembler code; they can put it in
5062 the RTL instead of operand 1.
5064 Operand 0 should be a @code{mem} RTX whose address is the address of the
5065 function. Note, however, that this address can be a @code{symbol_ref}
5066 expression even if it would not be a legitimate memory address on the
5067 target machine. If it is also not a valid argument for a call
5068 instruction, the pattern for this operation should be a
5069 @code{define_expand} (@pxref{Expander Definitions}) that places the
5070 address into a register and uses that register in the call instruction.
5072 @cindex @code{call_value} instruction pattern
5073 @item @samp{call_value}
5074 Subroutine call instruction returning a value. Operand 0 is the hard
5075 register in which the value is returned. There are three more
5076 operands, the same as the three operands of the @samp{call}
5077 instruction (but with numbers increased by one).
5079 Subroutines that return @code{BLKmode} objects use the @samp{call}
5082 @cindex @code{call_pop} instruction pattern
5083 @cindex @code{call_value_pop} instruction pattern
5084 @item @samp{call_pop}, @samp{call_value_pop}
5085 Similar to @samp{call} and @samp{call_value}, except used if defined and
5086 if @code{RETURN_POPS_ARGS} is nonzero. They should emit a @code{parallel}
5087 that contains both the function call and a @code{set} to indicate the
5088 adjustment made to the frame pointer.
5090 For machines where @code{RETURN_POPS_ARGS} can be nonzero, the use of these
5091 patterns increases the number of functions for which the frame pointer
5092 can be eliminated, if desired.
5094 @cindex @code{untyped_call} instruction pattern
5095 @item @samp{untyped_call}
5096 Subroutine call instruction returning a value of any type. Operand 0 is
5097 the function to call; operand 1 is a memory location where the result of
5098 calling the function is to be stored; operand 2 is a @code{parallel}
5099 expression where each element is a @code{set} expression that indicates
5100 the saving of a function return value into the result block.
5102 This instruction pattern should be defined to support
5103 @code{__builtin_apply} on machines where special instructions are needed
5104 to call a subroutine with arbitrary arguments or to save the value
5105 returned. This instruction pattern is required on machines that have
5106 multiple registers that can hold a return value
5107 (i.e.@: @code{FUNCTION_VALUE_REGNO_P} is true for more than one register).
5109 @cindex @code{return} instruction pattern
5111 Subroutine return instruction. This instruction pattern name should be
5112 defined only if a single instruction can do all the work of returning
5115 Like the @samp{mov@var{m}} patterns, this pattern is also used after the
5116 RTL generation phase. In this case it is to support machines where
5117 multiple instructions are usually needed to return from a function, but
5118 some class of functions only requires one instruction to implement a
5119 return. Normally, the applicable functions are those which do not need
5120 to save any registers or allocate stack space.
5122 It is valid for this pattern to expand to an instruction using
5123 @code{simple_return} if no epilogue is required.
5125 @cindex @code{simple_return} instruction pattern
5126 @item @samp{simple_return}
5127 Subroutine return instruction. This instruction pattern name should be
5128 defined only if a single instruction can do all the work of returning
5129 from a function on a path where no epilogue is required. This pattern
5130 is very similar to the @code{return} instruction pattern, but it is emitted
5131 only by the shrink-wrapping optimization on paths where the function
5132 prologue has not been executed, and a function return should occur without
5133 any of the effects of the epilogue. Additional uses may be introduced on
5134 paths where both the prologue and the epilogue have executed.
5136 @findex reload_completed
5137 @findex leaf_function_p
5138 For such machines, the condition specified in this pattern should only
5139 be true when @code{reload_completed} is nonzero and the function's
5140 epilogue would only be a single instruction. For machines with register
5141 windows, the routine @code{leaf_function_p} may be used to determine if
5142 a register window push is required.
5144 Machines that have conditional return instructions should define patterns
5150 (if_then_else (match_operator
5151 0 "comparison_operator"
5152 [(cc0) (const_int 0)])
5159 where @var{condition} would normally be the same condition specified on the
5160 named @samp{return} pattern.
5162 @cindex @code{untyped_return} instruction pattern
5163 @item @samp{untyped_return}
5164 Untyped subroutine return instruction. This instruction pattern should
5165 be defined to support @code{__builtin_return} on machines where special
5166 instructions are needed to return a value of any type.
5168 Operand 0 is a memory location where the result of calling a function
5169 with @code{__builtin_apply} is stored; operand 1 is a @code{parallel}
5170 expression where each element is a @code{set} expression that indicates
5171 the restoring of a function return value from the result block.
5173 @cindex @code{nop} instruction pattern
5175 No-op instruction. This instruction pattern name should always be defined
5176 to output a no-op in assembler code. @code{(const_int 0)} will do as an
5179 @cindex @code{indirect_jump} instruction pattern
5180 @item @samp{indirect_jump}
5181 An instruction to jump to an address which is operand zero.
5182 This pattern name is mandatory on all machines.
5184 @cindex @code{casesi} instruction pattern
5186 Instruction to jump through a dispatch table, including bounds checking.
5187 This instruction takes five operands:
5191 The index to dispatch on, which has mode @code{SImode}.
5194 The lower bound for indices in the table, an integer constant.
5197 The total range of indices in the table---the largest index
5198 minus the smallest one (both inclusive).
5201 A label that precedes the table itself.
5204 A label to jump to if the index has a value outside the bounds.
5207 The table is an @code{addr_vec} or @code{addr_diff_vec} inside of a
5208 @code{jump_insn}. The number of elements in the table is one plus the
5209 difference between the upper bound and the lower bound.
5211 @cindex @code{tablejump} instruction pattern
5212 @item @samp{tablejump}
5213 Instruction to jump to a variable address. This is a low-level
5214 capability which can be used to implement a dispatch table when there
5215 is no @samp{casesi} pattern.
5217 This pattern requires two operands: the address or offset, and a label
5218 which should immediately precede the jump table. If the macro
5219 @code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first
5220 operand is an offset which counts from the address of the table; otherwise,
5221 it is an absolute address to jump to. In either case, the first operand has
5224 The @samp{tablejump} insn is always the last insn before the jump
5225 table it uses. Its assembler code normally has no need to use the
5226 second operand, but you should incorporate it in the RTL pattern so
5227 that the jump optimizer will not delete the table as unreachable code.
5230 @cindex @code{decrement_and_branch_until_zero} instruction pattern
5231 @item @samp{decrement_and_branch_until_zero}
5232 Conditional branch instruction that decrements a register and
5233 jumps if the register is nonzero. Operand 0 is the register to
5234 decrement and test; operand 1 is the label to jump to if the
5235 register is nonzero. @xref{Looping Patterns}.
5237 This optional instruction pattern is only used by the combiner,
5238 typically for loops reversed by the loop optimizer when strength
5239 reduction is enabled.
5241 @cindex @code{doloop_end} instruction pattern
5242 @item @samp{doloop_end}
5243 Conditional branch instruction that decrements a register and jumps if
5244 the register is nonzero. This instruction takes five operands: Operand
5245 0 is the register to decrement and test; operand 1 is the number of loop
5246 iterations as a @code{const_int} or @code{const0_rtx} if this cannot be
5247 determined until run-time; operand 2 is the actual or estimated maximum
5248 number of iterations as a @code{const_int}; operand 3 is the number of
5249 enclosed loops as a @code{const_int} (an innermost loop has a value of
5250 1); operand 4 is the label to jump to if the register is nonzero.
5251 @xref{Looping Patterns}.
5253 This optional instruction pattern should be defined for machines with
5254 low-overhead looping instructions as the loop optimizer will try to
5255 modify suitable loops to utilize it. If nested low-overhead looping is
5256 not supported, use a @code{define_expand} (@pxref{Expander Definitions})
5257 and make the pattern fail if operand 3 is not @code{const1_rtx}.
5258 Similarly, if the actual or estimated maximum number of iterations is
5259 too large for this instruction, make it fail.
5261 @cindex @code{doloop_begin} instruction pattern
5262 @item @samp{doloop_begin}
5263 Companion instruction to @code{doloop_end} required for machines that
5264 need to perform some initialization, such as loading special registers
5265 used by a low-overhead looping instruction. If initialization insns do
5266 not always need to be emitted, use a @code{define_expand}
5267 (@pxref{Expander Definitions}) and make it fail.
5270 @cindex @code{canonicalize_funcptr_for_compare} instruction pattern
5271 @item @samp{canonicalize_funcptr_for_compare}
5272 Canonicalize the function pointer in operand 1 and store the result
5275 Operand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1
5276 may be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc
5277 and also has mode @code{Pmode}.
5279 Canonicalization of a function pointer usually involves computing
5280 the address of the function which would be called if the function
5281 pointer were used in an indirect call.
5283 Only define this pattern if function pointers on the target machine
5284 can have different values but still call the same function when
5285 used in an indirect call.
5287 @cindex @code{save_stack_block} instruction pattern
5288 @cindex @code{save_stack_function} instruction pattern
5289 @cindex @code{save_stack_nonlocal} instruction pattern
5290 @cindex @code{restore_stack_block} instruction pattern
5291 @cindex @code{restore_stack_function} instruction pattern
5292 @cindex @code{restore_stack_nonlocal} instruction pattern
5293 @item @samp{save_stack_block}
5294 @itemx @samp{save_stack_function}
5295 @itemx @samp{save_stack_nonlocal}
5296 @itemx @samp{restore_stack_block}
5297 @itemx @samp{restore_stack_function}
5298 @itemx @samp{restore_stack_nonlocal}
5299 Most machines save and restore the stack pointer by copying it to or
5300 from an object of mode @code{Pmode}. Do not define these patterns on
5303 Some machines require special handling for stack pointer saves and
5304 restores. On those machines, define the patterns corresponding to the
5305 non-standard cases by using a @code{define_expand} (@pxref{Expander
5306 Definitions}) that produces the required insns. The three types of
5307 saves and restores are:
5311 @samp{save_stack_block} saves the stack pointer at the start of a block
5312 that allocates a variable-sized object, and @samp{restore_stack_block}
5313 restores the stack pointer when the block is exited.
5316 @samp{save_stack_function} and @samp{restore_stack_function} do a
5317 similar job for the outermost block of a function and are used when the
5318 function allocates variable-sized objects or calls @code{alloca}. Only
5319 the epilogue uses the restored stack pointer, allowing a simpler save or
5320 restore sequence on some machines.
5323 @samp{save_stack_nonlocal} is used in functions that contain labels
5324 branched to by nested functions. It saves the stack pointer in such a
5325 way that the inner function can use @samp{restore_stack_nonlocal} to
5326 restore the stack pointer. The compiler generates code to restore the
5327 frame and argument pointer registers, but some machines require saving
5328 and restoring additional data such as register window information or
5329 stack backchains. Place insns in these patterns to save and restore any
5333 When saving the stack pointer, operand 0 is the save area and operand 1
5334 is the stack pointer. The mode used to allocate the save area defaults
5335 to @code{Pmode} but you can override that choice by defining the
5336 @code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must
5337 specify an integral mode, or @code{VOIDmode} if no save area is needed
5338 for a particular type of save (either because no save is needed or
5339 because a machine-specific save area can be used). Operand 0 is the
5340 stack pointer and operand 1 is the save area for restore operations. If
5341 @samp{save_stack_block} is defined, operand 0 must not be
5342 @code{VOIDmode} since these saves can be arbitrarily nested.
5344 A save area is a @code{mem} that is at a constant offset from
5345 @code{virtual_stack_vars_rtx} when the stack pointer is saved for use by
5346 nonlocal gotos and a @code{reg} in the other two cases.
5348 @cindex @code{allocate_stack} instruction pattern
5349 @item @samp{allocate_stack}
5350 Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from
5351 the stack pointer to create space for dynamically allocated data.
5353 Store the resultant pointer to this space into operand 0. If you
5354 are allocating space from the main stack, do this by emitting a
5355 move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0.
5356 If you are allocating the space elsewhere, generate code to copy the
5357 location of the space to operand 0. In the latter case, you must
5358 ensure this space gets freed when the corresponding space on the main
5361 Do not define this pattern if all that must be done is the subtraction.
5362 Some machines require other operations such as stack probes or
5363 maintaining the back chain. Define this pattern to emit those
5364 operations in addition to updating the stack pointer.
5366 @cindex @code{check_stack} instruction pattern
5367 @item @samp{check_stack}
5368 If stack checking (@pxref{Stack Checking}) cannot be done on your system by
5369 probing the stack, define this pattern to perform the needed check and signal
5370 an error if the stack has overflowed. The single operand is the address in
5371 the stack farthest from the current stack pointer that you need to validate.
5372 Normally, on platforms where this pattern is needed, you would obtain the
5373 stack limit from a global or thread-specific variable or register.
5375 @cindex @code{probe_stack} instruction pattern
5376 @item @samp{probe_stack}
5377 If stack checking (@pxref{Stack Checking}) can be done on your system by
5378 probing the stack but doing it with a ``store zero'' instruction is not valid
5379 or optimal, define this pattern to do the probing differently and signal an
5380 error if the stack has overflowed. The single operand is the memory reference
5381 in the stack that needs to be probed.
5383 @cindex @code{nonlocal_goto} instruction pattern
5384 @item @samp{nonlocal_goto}
5385 Emit code to generate a non-local goto, e.g., a jump from one function
5386 to a label in an outer function. This pattern has four arguments,
5387 each representing a value to be used in the jump. The first
5388 argument is to be loaded into the frame pointer, the second is
5389 the address to branch to (code to dispatch to the actual label),
5390 the third is the address of a location where the stack is saved,
5391 and the last is the address of the label, to be placed in the
5392 location for the incoming static chain.
5394 On most machines you need not define this pattern, since GCC will
5395 already generate the correct code, which is to load the frame pointer
5396 and static chain, restore the stack (using the
5397 @samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly
5398 to the dispatcher. You need only define this pattern if this code will
5399 not work on your machine.
5401 @cindex @code{nonlocal_goto_receiver} instruction pattern
5402 @item @samp{nonlocal_goto_receiver}
5403 This pattern, if defined, contains code needed at the target of a
5404 nonlocal goto after the code already generated by GCC@. You will not
5405 normally need to define this pattern. A typical reason why you might
5406 need this pattern is if some value, such as a pointer to a global table,
5407 must be restored when the frame pointer is restored. Note that a nonlocal
5408 goto only occurs within a unit-of-translation, so a global table pointer
5409 that is shared by all functions of a given module need not be restored.
5410 There are no arguments.
5412 @cindex @code{exception_receiver} instruction pattern
5413 @item @samp{exception_receiver}
5414 This pattern, if defined, contains code needed at the site of an
5415 exception handler that isn't needed at the site of a nonlocal goto. You
5416 will not normally need to define this pattern. A typical reason why you
5417 might need this pattern is if some value, such as a pointer to a global
5418 table, must be restored after control flow is branched to the handler of
5419 an exception. There are no arguments.
5421 @cindex @code{builtin_setjmp_setup} instruction pattern
5422 @item @samp{builtin_setjmp_setup}
5423 This pattern, if defined, contains additional code needed to initialize
5424 the @code{jmp_buf}. You will not normally need to define this pattern.
5425 A typical reason why you might need this pattern is if some value, such
5426 as a pointer to a global table, must be restored. Though it is
5427 preferred that the pointer value be recalculated if possible (given the
5428 address of a label for instance). The single argument is a pointer to
5429 the @code{jmp_buf}. Note that the buffer is five words long and that
5430 the first three are normally used by the generic mechanism.
5432 @cindex @code{builtin_setjmp_receiver} instruction pattern
5433 @item @samp{builtin_setjmp_receiver}
5434 This pattern, if defined, contains code needed at the site of a
5435 built-in setjmp that isn't needed at the site of a nonlocal goto. You
5436 will not normally need to define this pattern. A typical reason why you
5437 might need this pattern is if some value, such as a pointer to a global
5438 table, must be restored. It takes one argument, which is the label
5439 to which builtin_longjmp transfered control; this pattern may be emitted
5440 at a small offset from that label.
5442 @cindex @code{builtin_longjmp} instruction pattern
5443 @item @samp{builtin_longjmp}
5444 This pattern, if defined, performs the entire action of the longjmp.
5445 You will not normally need to define this pattern unless you also define
5446 @code{builtin_setjmp_setup}. The single argument is a pointer to the
5449 @cindex @code{eh_return} instruction pattern
5450 @item @samp{eh_return}
5451 This pattern, if defined, affects the way @code{__builtin_eh_return},
5452 and thence the call frame exception handling library routines, are
5453 built. It is intended to handle non-trivial actions needed along
5454 the abnormal return path.
5456 The address of the exception handler to which the function should return
5457 is passed as operand to this pattern. It will normally need to copied by
5458 the pattern to some special register or memory location.
5459 If the pattern needs to determine the location of the target call
5460 frame in order to do so, it may use @code{EH_RETURN_STACKADJ_RTX},
5461 if defined; it will have already been assigned.
5463 If this pattern is not defined, the default action will be to simply
5464 copy the return address to @code{EH_RETURN_HANDLER_RTX}. Either
5465 that macro or this pattern needs to be defined if call frame exception
5466 handling is to be used.
5468 @cindex @code{prologue} instruction pattern
5469 @anchor{prologue instruction pattern}
5470 @item @samp{prologue}
5471 This pattern, if defined, emits RTL for entry to a function. The function
5472 entry is responsible for setting up the stack frame, initializing the frame
5473 pointer register, saving callee saved registers, etc.
5475 Using a prologue pattern is generally preferred over defining
5476 @code{TARGET_ASM_FUNCTION_PROLOGUE} to emit assembly code for the prologue.
5478 The @code{prologue} pattern is particularly useful for targets which perform
5479 instruction scheduling.
5481 @cindex @code{window_save} instruction pattern
5482 @anchor{window_save instruction pattern}
5483 @item @samp{window_save}
5484 This pattern, if defined, emits RTL for a register window save. It should
5485 be defined if the target machine has register windows but the window events
5486 are decoupled from calls to subroutines. The canonical example is the SPARC
5489 @cindex @code{epilogue} instruction pattern
5490 @anchor{epilogue instruction pattern}
5491 @item @samp{epilogue}
5492 This pattern emits RTL for exit from a function. The function
5493 exit is responsible for deallocating the stack frame, restoring callee saved
5494 registers and emitting the return instruction.
5496 Using an epilogue pattern is generally preferred over defining
5497 @code{TARGET_ASM_FUNCTION_EPILOGUE} to emit assembly code for the epilogue.
5499 The @code{epilogue} pattern is particularly useful for targets which perform
5500 instruction scheduling or which have delay slots for their return instruction.
5502 @cindex @code{sibcall_epilogue} instruction pattern
5503 @item @samp{sibcall_epilogue}
5504 This pattern, if defined, emits RTL for exit from a function without the final
5505 branch back to the calling function. This pattern will be emitted before any
5506 sibling call (aka tail call) sites.
5508 The @code{sibcall_epilogue} pattern must not clobber any arguments used for
5509 parameter passing or any stack slots for arguments passed to the current
5512 @cindex @code{trap} instruction pattern
5514 This pattern, if defined, signals an error, typically by causing some
5515 kind of signal to be raised. Among other places, it is used by the Java
5516 front end to signal `invalid array index' exceptions.
5518 @cindex @code{ctrap@var{MM}4} instruction pattern
5519 @item @samp{ctrap@var{MM}4}
5520 Conditional trap instruction. Operand 0 is a piece of RTL which
5521 performs a comparison, and operands 1 and 2 are the arms of the
5522 comparison. Operand 3 is the trap code, an integer.
5524 A typical @code{ctrap} pattern looks like
5527 (define_insn "ctrapsi4"
5528 [(trap_if (match_operator 0 "trap_operator"
5529 [(match_operand 1 "register_operand")
5530 (match_operand 2 "immediate_operand")])
5531 (match_operand 3 "const_int_operand" "i"))]
5536 @cindex @code{prefetch} instruction pattern
5537 @item @samp{prefetch}
5539 This pattern, if defined, emits code for a non-faulting data prefetch
5540 instruction. Operand 0 is the address of the memory to prefetch. Operand 1
5541 is a constant 1 if the prefetch is preparing for a write to the memory
5542 address, or a constant 0 otherwise. Operand 2 is the expected degree of
5543 temporal locality of the data and is a value between 0 and 3, inclusive; 0
5544 means that the data has no temporal locality, so it need not be left in the
5545 cache after the access; 3 means that the data has a high degree of temporal
5546 locality and should be left in all levels of cache possible; 1 and 2 mean,
5547 respectively, a low or moderate degree of temporal locality.
5549 Targets that do not support write prefetches or locality hints can ignore
5550 the values of operands 1 and 2.
5552 @cindex @code{blockage} instruction pattern
5553 @item @samp{blockage}
5555 This pattern defines a pseudo insn that prevents the instruction
5556 scheduler from moving instructions across the boundary defined by the
5557 blockage insn. Normally an UNSPEC_VOLATILE pattern.
5559 @cindex @code{memory_barrier} instruction pattern
5560 @item @samp{memory_barrier}
5562 If the target memory model is not fully synchronous, then this pattern
5563 should be defined to an instruction that orders both loads and stores
5564 before the instruction with respect to loads and stores after the instruction.
5565 This pattern has no operands.
5567 @cindex @code{sync_compare_and_swap@var{mode}} instruction pattern
5568 @item @samp{sync_compare_and_swap@var{mode}}
5570 This pattern, if defined, emits code for an atomic compare-and-swap
5571 operation. Operand 1 is the memory on which the atomic operation is
5572 performed. Operand 2 is the ``old'' value to be compared against the
5573 current contents of the memory location. Operand 3 is the ``new'' value
5574 to store in the memory if the compare succeeds. Operand 0 is the result
5575 of the operation; it should contain the contents of the memory
5576 before the operation. If the compare succeeds, this should obviously be
5577 a copy of operand 2.
5579 This pattern must show that both operand 0 and operand 1 are modified.
5581 This pattern must issue any memory barrier instructions such that all
5582 memory operations before the atomic operation occur before the atomic
5583 operation and all memory operations after the atomic operation occur
5584 after the atomic operation.
5586 For targets where the success or failure of the compare-and-swap
5587 operation is available via the status flags, it is possible to
5588 avoid a separate compare operation and issue the subsequent
5589 branch or store-flag operation immediately after the compare-and-swap.
5590 To this end, GCC will look for a @code{MODE_CC} set in the
5591 output of @code{sync_compare_and_swap@var{mode}}; if the machine
5592 description includes such a set, the target should also define special
5593 @code{cbranchcc4} and/or @code{cstorecc4} instructions. GCC will then
5594 be able to take the destination of the @code{MODE_CC} set and pass it
5595 to the @code{cbranchcc4} or @code{cstorecc4} pattern as the first
5596 operand of the comparison (the second will be @code{(const_int 0)}).
5598 @cindex @code{sync_add@var{mode}} instruction pattern
5599 @cindex @code{sync_sub@var{mode}} instruction pattern
5600 @cindex @code{sync_ior@var{mode}} instruction pattern
5601 @cindex @code{sync_and@var{mode}} instruction pattern
5602 @cindex @code{sync_xor@var{mode}} instruction pattern
5603 @cindex @code{sync_nand@var{mode}} instruction pattern
5604 @item @samp{sync_add@var{mode}}, @samp{sync_sub@var{mode}}
5605 @itemx @samp{sync_ior@var{mode}}, @samp{sync_and@var{mode}}
5606 @itemx @samp{sync_xor@var{mode}}, @samp{sync_nand@var{mode}}
5608 These patterns emit code for an atomic operation on memory.
5609 Operand 0 is the memory on which the atomic operation is performed.
5610 Operand 1 is the second operand to the binary operator.
5612 This pattern must issue any memory barrier instructions such that all
5613 memory operations before the atomic operation occur before the atomic
5614 operation and all memory operations after the atomic operation occur
5615 after the atomic operation.
5617 If these patterns are not defined, the operation will be constructed
5618 from a compare-and-swap operation, if defined.
5620 @cindex @code{sync_old_add@var{mode}} instruction pattern
5621 @cindex @code{sync_old_sub@var{mode}} instruction pattern
5622 @cindex @code{sync_old_ior@var{mode}} instruction pattern
5623 @cindex @code{sync_old_and@var{mode}} instruction pattern
5624 @cindex @code{sync_old_xor@var{mode}} instruction pattern
5625 @cindex @code{sync_old_nand@var{mode}} instruction pattern
5626 @item @samp{sync_old_add@var{mode}}, @samp{sync_old_sub@var{mode}}
5627 @itemx @samp{sync_old_ior@var{mode}}, @samp{sync_old_and@var{mode}}
5628 @itemx @samp{sync_old_xor@var{mode}}, @samp{sync_old_nand@var{mode}}
5630 These patterns are emit code for an atomic operation on memory,
5631 and return the value that the memory contained before the operation.
5632 Operand 0 is the result value, operand 1 is the memory on which the
5633 atomic operation is performed, and operand 2 is the second operand
5634 to the binary operator.
5636 This pattern must issue any memory barrier instructions such that all
5637 memory operations before the atomic operation occur before the atomic
5638 operation and all memory operations after the atomic operation occur
5639 after the atomic operation.
5641 If these patterns are not defined, the operation will be constructed
5642 from a compare-and-swap operation, if defined.
5644 @cindex @code{sync_new_add@var{mode}} instruction pattern
5645 @cindex @code{sync_new_sub@var{mode}} instruction pattern
5646 @cindex @code{sync_new_ior@var{mode}} instruction pattern
5647 @cindex @code{sync_new_and@var{mode}} instruction pattern
5648 @cindex @code{sync_new_xor@var{mode}} instruction pattern
5649 @cindex @code{sync_new_nand@var{mode}} instruction pattern
5650 @item @samp{sync_new_add@var{mode}}, @samp{sync_new_sub@var{mode}}
5651 @itemx @samp{sync_new_ior@var{mode}}, @samp{sync_new_and@var{mode}}
5652 @itemx @samp{sync_new_xor@var{mode}}, @samp{sync_new_nand@var{mode}}
5654 These patterns are like their @code{sync_old_@var{op}} counterparts,
5655 except that they return the value that exists in the memory location
5656 after the operation, rather than before the operation.
5658 @cindex @code{sync_lock_test_and_set@var{mode}} instruction pattern
5659 @item @samp{sync_lock_test_and_set@var{mode}}
5661 This pattern takes two forms, based on the capabilities of the target.
5662 In either case, operand 0 is the result of the operand, operand 1 is
5663 the memory on which the atomic operation is performed, and operand 2
5664 is the value to set in the lock.
5666 In the ideal case, this operation is an atomic exchange operation, in
5667 which the previous value in memory operand is copied into the result
5668 operand, and the value operand is stored in the memory operand.
5670 For less capable targets, any value operand that is not the constant 1
5671 should be rejected with @code{FAIL}. In this case the target may use
5672 an atomic test-and-set bit operation. The result operand should contain
5673 1 if the bit was previously set and 0 if the bit was previously clear.
5674 The true contents of the memory operand are implementation defined.
5676 This pattern must issue any memory barrier instructions such that the
5677 pattern as a whole acts as an acquire barrier, that is all memory
5678 operations after the pattern do not occur until the lock is acquired.
5680 If this pattern is not defined, the operation will be constructed from
5681 a compare-and-swap operation, if defined.
5683 @cindex @code{sync_lock_release@var{mode}} instruction pattern
5684 @item @samp{sync_lock_release@var{mode}}
5686 This pattern, if defined, releases a lock set by
5687 @code{sync_lock_test_and_set@var{mode}}. Operand 0 is the memory
5688 that contains the lock; operand 1 is the value to store in the lock.
5690 If the target doesn't implement full semantics for
5691 @code{sync_lock_test_and_set@var{mode}}, any value operand which is not
5692 the constant 0 should be rejected with @code{FAIL}, and the true contents
5693 of the memory operand are implementation defined.
5695 This pattern must issue any memory barrier instructions such that the
5696 pattern as a whole acts as a release barrier, that is the lock is
5697 released only after all previous memory operations have completed.
5699 If this pattern is not defined, then a @code{memory_barrier} pattern
5700 will be emitted, followed by a store of the value to the memory operand.
5702 @cindex @code{atomic_compare_and_swap@var{mode}} instruction pattern
5703 @item @samp{atomic_compare_and_swap@var{mode}}
5704 This pattern, if defined, emits code for an atomic compare-and-swap
5705 operation with memory model semantics. Operand 2 is the memory on which
5706 the atomic operation is performed. Operand 0 is an output operand which
5707 is set to true or false based on whether the operation succeeded. Operand
5708 1 is an output operand which is set to the contents of the memory before
5709 the operation was attempted. Operand 3 is the value that is expected to
5710 be in memory. Operand 4 is the value to put in memory if the expected
5711 value is found there. Operand 5 is set to 1 if this compare and swap is to
5712 be treated as a weak operation. Operand 6 is the memory model to be used
5713 if the operation is a success. Operand 7 is the memory model to be used
5714 if the operation fails.
5716 If memory referred to in operand 2 contains the value in operand 3, then
5717 operand 4 is stored in memory pointed to by operand 2 and fencing based on
5718 the memory model in operand 6 is issued.
5720 If memory referred to in operand 2 does not contain the value in operand 3,
5721 then fencing based on the memory model in operand 7 is issued.
5723 If a target does not support weak compare-and-swap operations, or the port
5724 elects not to implement weak operations, the argument in operand 5 can be
5725 ignored. Note a strong implementation must be provided.
5727 If this pattern is not provided, the @code{__atomic_compare_exchange}
5728 built-in functions will utilize the legacy @code{sync_compare_and_swap}
5729 pattern with an @code{__ATOMIC_SEQ_CST} memory model.
5731 @cindex @code{atomic_load@var{mode}} instruction pattern
5732 @item @samp{atomic_load@var{mode}}
5733 This pattern implements an atomic load operation with memory model
5734 semantics. Operand 1 is the memory address being loaded from. Operand 0
5735 is the result of the load. Operand 2 is the memory model to be used for
5738 If not present, the @code{__atomic_load} built-in function will either
5739 resort to a normal load with memory barriers, or a compare-and-swap
5740 operation if a normal load would not be atomic.
5742 @cindex @code{atomic_store@var{mode}} instruction pattern
5743 @item @samp{atomic_store@var{mode}}
5744 This pattern implements an atomic store operation with memory model
5745 semantics. Operand 0 is the memory address being stored to. Operand 1
5746 is the value to be written. Operand 2 is the memory model to be used for
5749 If not present, the @code{__atomic_store} built-in function will attempt to
5750 perform a normal store and surround it with any required memory fences. If
5751 the store would not be atomic, then an @code{__atomic_exchange} is
5752 attempted with the result being ignored.
5754 @cindex @code{atomic_exchange@var{mode}} instruction pattern
5755 @item @samp{atomic_exchange@var{mode}}
5756 This pattern implements an atomic exchange operation with memory model
5757 semantics. Operand 1 is the memory location the operation is performed on.
5758 Operand 0 is an output operand which is set to the original value contained
5759 in the memory pointed to by operand 1. Operand 2 is the value to be
5760 stored. Operand 3 is the memory model to be used.
5762 If this pattern is not present, the built-in function
5763 @code{__atomic_exchange} will attempt to preform the operation with a
5764 compare and swap loop.
5766 @cindex @code{atomic_add@var{mode}} instruction pattern
5767 @cindex @code{atomic_sub@var{mode}} instruction pattern
5768 @cindex @code{atomic_or@var{mode}} instruction pattern
5769 @cindex @code{atomic_and@var{mode}} instruction pattern
5770 @cindex @code{atomic_xor@var{mode}} instruction pattern
5771 @cindex @code{atomic_nand@var{mode}} instruction pattern
5772 @item @samp{atomic_add@var{mode}}, @samp{atomic_sub@var{mode}}
5773 @itemx @samp{atomic_or@var{mode}}, @samp{atomic_and@var{mode}}
5774 @itemx @samp{atomic_xor@var{mode}}, @samp{atomic_nand@var{mode}}
5776 These patterns emit code for an atomic operation on memory with memory
5777 model semantics. Operand 0 is the memory on which the atomic operation is
5778 performed. Operand 1 is the second operand to the binary operator.
5779 Operand 2 is the memory model to be used by the operation.
5781 If these patterns are not defined, attempts will be made to use legacy
5782 @code{sync} patterns, or equivilent patterns which return a result. If
5783 none of these are available a compare-and-swap loop will be used.
5785 @cindex @code{atomic_fetch_add@var{mode}} instruction pattern
5786 @cindex @code{atomic_fetch_sub@var{mode}} instruction pattern
5787 @cindex @code{atomic_fetch_or@var{mode}} instruction pattern
5788 @cindex @code{atomic_fetch_and@var{mode}} instruction pattern
5789 @cindex @code{atomic_fetch_xor@var{mode}} instruction pattern
5790 @cindex @code{atomic_fetch_nand@var{mode}} instruction pattern
5791 @item @samp{atomic_fetch_add@var{mode}}, @samp{atomic_fetch_sub@var{mode}}
5792 @itemx @samp{atomic_fetch_or@var{mode}}, @samp{atomic_fetch_and@var{mode}}
5793 @itemx @samp{atomic_fetch_xor@var{mode}}, @samp{atomic_fetch_nand@var{mode}}
5795 These patterns emit code for an atomic operation on memory with memory
5796 model semantics, and return the original value. Operand 0 is an output
5797 operand which contains the value of the memory location before the
5798 operation was performed. Operand 1 is the memory on which the atomic
5799 operation is performed. Operand 2 is the second operand to the binary
5800 operator. Operand 3 is the memory model to be used by the operation.
5802 If these patterns are not defined, attempts will be made to use legacy
5803 @code{sync} patterns. If none of these are available a compare-and-swap
5806 @cindex @code{atomic_add_fetch@var{mode}} instruction pattern
5807 @cindex @code{atomic_sub_fetch@var{mode}} instruction pattern
5808 @cindex @code{atomic_or_fetch@var{mode}} instruction pattern
5809 @cindex @code{atomic_and_fetch@var{mode}} instruction pattern
5810 @cindex @code{atomic_xor_fetch@var{mode}} instruction pattern
5811 @cindex @code{atomic_nand_fetch@var{mode}} instruction pattern
5812 @item @samp{atomic_add_fetch@var{mode}}, @samp{atomic_sub_fetch@var{mode}}
5813 @itemx @samp{atomic_or_fetch@var{mode}}, @samp{atomic_and_fetch@var{mode}}
5814 @itemx @samp{atomic_xor_fetch@var{mode}}, @samp{atomic_nand_fetch@var{mode}}
5816 These patterns emit code for an atomic operation on memory with memory
5817 model semantics and return the result after the operation is performed.
5818 Operand 0 is an output operand which contains the value after the
5819 operation. Operand 1 is the memory on which the atomic operation is
5820 performed. Operand 2 is the second operand to the binary operator.
5821 Operand 3 is the memory model to be used by the operation.
5823 If these patterns are not defined, attempts will be made to use legacy
5824 @code{sync} patterns, or equivilent patterns which return the result before
5825 the operation followed by the arithmetic operation required to produce the
5826 result. If none of these are available a compare-and-swap loop will be
5829 @cindex @code{mem_thread_fence@var{mode}} instruction pattern
5830 @item @samp{mem_thread_fence@var{mode}}
5831 This pattern emits code required to implement a thread fence with
5832 memory model semantics. Operand 0 is the memory model to be used.
5834 If this pattern is not specified, all memory models except
5835 @code{__ATOMIC_RELAXED} will result in issuing a @code{sync_synchronize}
5838 @cindex @code{mem_signal_fence@var{mode}} instruction pattern
5839 @item @samp{mem_signal_fence@var{mode}}
5840 This pattern emits code required to implement a signal fence with
5841 memory model semantics. Operand 0 is the memory model to be used.
5843 This pattern should impact the compiler optimizers the same way that
5844 mem_signal_fence does, but it does not need to issue any barrier
5847 If this pattern is not specified, all memory models except
5848 @code{__ATOMIC_RELAXED} will result in issuing a @code{sync_synchronize}
5851 @cindex @code{stack_protect_set} instruction pattern
5852 @item @samp{stack_protect_set}
5854 This pattern, if defined, moves a @code{ptr_mode} value from the memory
5855 in operand 1 to the memory in operand 0 without leaving the value in
5856 a register afterward. This is to avoid leaking the value some place
5857 that an attacker might use to rewrite the stack guard slot after
5858 having clobbered it.
5860 If this pattern is not defined, then a plain move pattern is generated.
5862 @cindex @code{stack_protect_test} instruction pattern
5863 @item @samp{stack_protect_test}
5865 This pattern, if defined, compares a @code{ptr_mode} value from the
5866 memory in operand 1 with the memory in operand 0 without leaving the
5867 value in a register afterward and branches to operand 2 if the values
5870 If this pattern is not defined, then a plain compare pattern and
5871 conditional branch pattern is used.
5873 @cindex @code{clear_cache} instruction pattern
5874 @item @samp{clear_cache}
5876 This pattern, if defined, flushes the instruction cache for a region of
5877 memory. The region is bounded to by the Pmode pointers in operand 0
5878 inclusive and operand 1 exclusive.
5880 If this pattern is not defined, a call to the library function
5881 @code{__clear_cache} is used.
5886 @c Each of the following nodes are wrapped in separate
5887 @c "@ifset INTERNALS" to work around memory limits for the default
5888 @c configuration in older tetex distributions. Known to not work:
5889 @c tetex-1.0.7, known to work: tetex-2.0.2.
5891 @node Pattern Ordering
5892 @section When the Order of Patterns Matters
5893 @cindex Pattern Ordering
5894 @cindex Ordering of Patterns
5896 Sometimes an insn can match more than one instruction pattern. Then the
5897 pattern that appears first in the machine description is the one used.
5898 Therefore, more specific patterns (patterns that will match fewer things)
5899 and faster instructions (those that will produce better code when they
5900 do match) should usually go first in the description.
5902 In some cases the effect of ordering the patterns can be used to hide
5903 a pattern when it is not valid. For example, the 68000 has an
5904 instruction for converting a fullword to floating point and another
5905 for converting a byte to floating point. An instruction converting
5906 an integer to floating point could match either one. We put the
5907 pattern to convert the fullword first to make sure that one will
5908 be used rather than the other. (Otherwise a large integer might
5909 be generated as a single-byte immediate quantity, which would not work.)
5910 Instead of using this pattern ordering it would be possible to make the
5911 pattern for convert-a-byte smart enough to deal properly with any
5916 @node Dependent Patterns
5917 @section Interdependence of Patterns
5918 @cindex Dependent Patterns
5919 @cindex Interdependence of Patterns
5921 In some cases machines support instructions identical except for the
5922 machine mode of one or more operands. For example, there may be
5923 ``sign-extend halfword'' and ``sign-extend byte'' instructions whose
5927 (set (match_operand:SI 0 @dots{})
5928 (extend:SI (match_operand:HI 1 @dots{})))
5930 (set (match_operand:SI 0 @dots{})
5931 (extend:SI (match_operand:QI 1 @dots{})))
5935 Constant integers do not specify a machine mode, so an instruction to
5936 extend a constant value could match either pattern. The pattern it
5937 actually will match is the one that appears first in the file. For correct
5938 results, this must be the one for the widest possible mode (@code{HImode},
5939 here). If the pattern matches the @code{QImode} instruction, the results
5940 will be incorrect if the constant value does not actually fit that mode.
5942 Such instructions to extend constants are rarely generated because they are
5943 optimized away, but they do occasionally happen in nonoptimized
5946 If a constraint in a pattern allows a constant, the reload pass may
5947 replace a register with a constant permitted by the constraint in some
5948 cases. Similarly for memory references. Because of this substitution,
5949 you should not provide separate patterns for increment and decrement
5950 instructions. Instead, they should be generated from the same pattern
5951 that supports register-register add insns by examining the operands and
5952 generating the appropriate machine instruction.
5957 @section Defining Jump Instruction Patterns
5958 @cindex jump instruction patterns
5959 @cindex defining jump instruction patterns
5961 GCC does not assume anything about how the machine realizes jumps.
5962 The machine description should define a single pattern, usually
5963 a @code{define_expand}, which expands to all the required insns.
5965 Usually, this would be a comparison insn to set the condition code
5966 and a separate branch insn testing the condition code and branching
5967 or not according to its value. For many machines, however,
5968 separating compares and branches is limiting, which is why the
5969 more flexible approach with one @code{define_expand} is used in GCC.
5970 The machine description becomes clearer for architectures that
5971 have compare-and-branch instructions but no condition code. It also
5972 works better when different sets of comparison operators are supported
5973 by different kinds of conditional branches (e.g. integer vs. floating-point),
5974 or by conditional branches with respect to conditional stores.
5976 Two separate insns are always used if the machine description represents
5977 a condition code register using the legacy RTL expression @code{(cc0)},
5978 and on most machines that use a separate condition code register
5979 (@pxref{Condition Code}). For machines that use @code{(cc0)}, in
5980 fact, the set and use of the condition code must be separate and
5981 adjacent@footnote{@code{note} insns can separate them, though.}, thus
5982 allowing flags in @code{cc_status} to be used (@pxref{Condition Code}) and
5983 so that the comparison and branch insns could be located from each other
5984 by using the functions @code{prev_cc0_setter} and @code{next_cc0_user}.
5986 Even in this case having a single entry point for conditional branches
5987 is advantageous, because it handles equally well the case where a single
5988 comparison instruction records the results of both signed and unsigned
5989 comparison of the given operands (with the branch insns coming in distinct
5990 signed and unsigned flavors) as in the x86 or SPARC, and the case where
5991 there are distinct signed and unsigned compare instructions and only
5992 one set of conditional branch instructions as in the PowerPC.
5996 @node Looping Patterns
5997 @section Defining Looping Instruction Patterns
5998 @cindex looping instruction patterns
5999 @cindex defining looping instruction patterns
6001 Some machines have special jump instructions that can be utilized to
6002 make loops more efficient. A common example is the 68000 @samp{dbra}
6003 instruction which performs a decrement of a register and a branch if the
6004 result was greater than zero. Other machines, in particular digital
6005 signal processors (DSPs), have special block repeat instructions to
6006 provide low-overhead loop support. For example, the TI TMS320C3x/C4x
6007 DSPs have a block repeat instruction that loads special registers to
6008 mark the top and end of a loop and to count the number of loop
6009 iterations. This avoids the need for fetching and executing a
6010 @samp{dbra}-like instruction and avoids pipeline stalls associated with
6013 GCC has three special named patterns to support low overhead looping.
6014 They are @samp{decrement_and_branch_until_zero}, @samp{doloop_begin},
6015 and @samp{doloop_end}. The first pattern,
6016 @samp{decrement_and_branch_until_zero}, is not emitted during RTL
6017 generation but may be emitted during the instruction combination phase.
6018 This requires the assistance of the loop optimizer, using information
6019 collected during strength reduction, to reverse a loop to count down to
6020 zero. Some targets also require the loop optimizer to add a
6021 @code{REG_NONNEG} note to indicate that the iteration count is always
6022 positive. This is needed if the target performs a signed loop
6023 termination test. For example, the 68000 uses a pattern similar to the
6024 following for its @code{dbra} instruction:
6028 (define_insn "decrement_and_branch_until_zero"
6031 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
6034 (label_ref (match_operand 1 "" ""))
6037 (plus:SI (match_dup 0)
6039 "find_reg_note (insn, REG_NONNEG, 0)"
6044 Note that since the insn is both a jump insn and has an output, it must
6045 deal with its own reloads, hence the `m' constraints. Also note that
6046 since this insn is generated by the instruction combination phase
6047 combining two sequential insns together into an implicit parallel insn,
6048 the iteration counter needs to be biased by the same amount as the
6049 decrement operation, in this case @minus{}1. Note that the following similar
6050 pattern will not be matched by the combiner.
6054 (define_insn "decrement_and_branch_until_zero"
6057 (ge (match_operand:SI 0 "general_operand" "+d*am")
6059 (label_ref (match_operand 1 "" ""))
6062 (plus:SI (match_dup 0)
6064 "find_reg_note (insn, REG_NONNEG, 0)"
6069 The other two special looping patterns, @samp{doloop_begin} and
6070 @samp{doloop_end}, are emitted by the loop optimizer for certain
6071 well-behaved loops with a finite number of loop iterations using
6072 information collected during strength reduction.
6074 The @samp{doloop_end} pattern describes the actual looping instruction
6075 (or the implicit looping operation) and the @samp{doloop_begin} pattern
6076 is an optional companion pattern that can be used for initialization
6077 needed for some low-overhead looping instructions.
6079 Note that some machines require the actual looping instruction to be
6080 emitted at the top of the loop (e.g., the TMS320C3x/C4x DSPs). Emitting
6081 the true RTL for a looping instruction at the top of the loop can cause
6082 problems with flow analysis. So instead, a dummy @code{doloop} insn is
6083 emitted at the end of the loop. The machine dependent reorg pass checks
6084 for the presence of this @code{doloop} insn and then searches back to
6085 the top of the loop, where it inserts the true looping insn (provided
6086 there are no instructions in the loop which would cause problems). Any
6087 additional labels can be emitted at this point. In addition, if the
6088 desired special iteration counter register was not allocated, this
6089 machine dependent reorg pass could emit a traditional compare and jump
6092 The essential difference between the
6093 @samp{decrement_and_branch_until_zero} and the @samp{doloop_end}
6094 patterns is that the loop optimizer allocates an additional pseudo
6095 register for the latter as an iteration counter. This pseudo register
6096 cannot be used within the loop (i.e., general induction variables cannot
6097 be derived from it), however, in many cases the loop induction variable
6098 may become redundant and removed by the flow pass.
6103 @node Insn Canonicalizations
6104 @section Canonicalization of Instructions
6105 @cindex canonicalization of instructions
6106 @cindex insn canonicalization
6108 There are often cases where multiple RTL expressions could represent an
6109 operation performed by a single machine instruction. This situation is
6110 most commonly encountered with logical, branch, and multiply-accumulate
6111 instructions. In such cases, the compiler attempts to convert these
6112 multiple RTL expressions into a single canonical form to reduce the
6113 number of insn patterns required.
6115 In addition to algebraic simplifications, following canonicalizations
6120 For commutative and comparison operators, a constant is always made the
6121 second operand. If a machine only supports a constant as the second
6122 operand, only patterns that match a constant in the second operand need
6126 For associative operators, a sequence of operators will always chain
6127 to the left; for instance, only the left operand of an integer @code{plus}
6128 can itself be a @code{plus}. @code{and}, @code{ior}, @code{xor},
6129 @code{plus}, @code{mult}, @code{smin}, @code{smax}, @code{umin}, and
6130 @code{umax} are associative when applied to integers, and sometimes to
6134 @cindex @code{neg}, canonicalization of
6135 @cindex @code{not}, canonicalization of
6136 @cindex @code{mult}, canonicalization of
6137 @cindex @code{plus}, canonicalization of
6138 @cindex @code{minus}, canonicalization of
6139 For these operators, if only one operand is a @code{neg}, @code{not},
6140 @code{mult}, @code{plus}, or @code{minus} expression, it will be the
6144 In combinations of @code{neg}, @code{mult}, @code{plus}, and
6145 @code{minus}, the @code{neg} operations (if any) will be moved inside
6146 the operations as far as possible. For instance,
6147 @code{(neg (mult A B))} is canonicalized as @code{(mult (neg A) B)}, but
6148 @code{(plus (mult (neg B) C) A)} is canonicalized as
6149 @code{(minus A (mult B C))}.
6151 @cindex @code{compare}, canonicalization of
6153 For the @code{compare} operator, a constant is always the second operand
6154 if the first argument is a condition code register or @code{(cc0)}.
6157 An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or
6158 @code{minus} is made the first operand under the same conditions as
6162 @code{(ltu (plus @var{a} @var{b}) @var{b})} is converted to
6163 @code{(ltu (plus @var{a} @var{b}) @var{a})}. Likewise with @code{geu} instead
6167 @code{(minus @var{x} (const_int @var{n}))} is converted to
6168 @code{(plus @var{x} (const_int @var{-n}))}.
6171 Within address computations (i.e., inside @code{mem}), a left shift is
6172 converted into the appropriate multiplication by a power of two.
6174 @cindex @code{ior}, canonicalization of
6175 @cindex @code{and}, canonicalization of
6176 @cindex De Morgan's law
6178 De Morgan's Law is used to move bitwise negation inside a bitwise
6179 logical-and or logical-or operation. If this results in only one
6180 operand being a @code{not} expression, it will be the first one.
6182 A machine that has an instruction that performs a bitwise logical-and of one
6183 operand with the bitwise negation of the other should specify the pattern
6184 for that instruction as
6188 [(set (match_operand:@var{m} 0 @dots{})
6189 (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
6190 (match_operand:@var{m} 2 @dots{})))]
6196 Similarly, a pattern for a ``NAND'' instruction should be written
6200 [(set (match_operand:@var{m} 0 @dots{})
6201 (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
6202 (not:@var{m} (match_operand:@var{m} 2 @dots{}))))]
6207 In both cases, it is not necessary to include patterns for the many
6208 logically equivalent RTL expressions.
6210 @cindex @code{xor}, canonicalization of
6212 The only possible RTL expressions involving both bitwise exclusive-or
6213 and bitwise negation are @code{(xor:@var{m} @var{x} @var{y})}
6214 and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}.
6217 The sum of three items, one of which is a constant, will only appear in
6221 (plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant})
6224 @cindex @code{zero_extract}, canonicalization of
6225 @cindex @code{sign_extract}, canonicalization of
6227 Equality comparisons of a group of bits (usually a single bit) with zero
6228 will be written using @code{zero_extract} rather than the equivalent
6229 @code{and} or @code{sign_extract} operations.
6231 @cindex @code{mult}, canonicalization of
6233 @code{(sign_extend:@var{m1} (mult:@var{m2} (sign_extend:@var{m2} @var{x})
6234 (sign_extend:@var{m2} @var{y})))} is converted to @code{(mult:@var{m1}
6235 (sign_extend:@var{m1} @var{x}) (sign_extend:@var{m1} @var{y}))}, and likewise
6236 for @code{zero_extend}.
6239 @code{(sign_extend:@var{m1} (mult:@var{m2} (ashiftrt:@var{m2}
6240 @var{x} @var{s}) (sign_extend:@var{m2} @var{y})))} is converted
6241 to @code{(mult:@var{m1} (sign_extend:@var{m1} (ashiftrt:@var{m2}
6242 @var{x} @var{s})) (sign_extend:@var{m1} @var{y}))}, and likewise for
6243 patterns using @code{zero_extend} and @code{lshiftrt}. If the second
6244 operand of @code{mult} is also a shift, then that is extended also.
6245 This transformation is only applied when it can be proven that the
6246 original operation had sufficient precision to prevent overflow.
6250 Further canonicalization rules are defined in the function
6251 @code{commutative_operand_precedence} in @file{gcc/rtlanal.c}.
6255 @node Expander Definitions
6256 @section Defining RTL Sequences for Code Generation
6257 @cindex expander definitions
6258 @cindex code generation RTL sequences
6259 @cindex defining RTL sequences for code generation
6261 On some target machines, some standard pattern names for RTL generation
6262 cannot be handled with single insn, but a sequence of RTL insns can
6263 represent them. For these target machines, you can write a
6264 @code{define_expand} to specify how to generate the sequence of RTL@.
6266 @findex define_expand
6267 A @code{define_expand} is an RTL expression that looks almost like a
6268 @code{define_insn}; but, unlike the latter, a @code{define_expand} is used
6269 only for RTL generation and it can produce more than one RTL insn.
6271 A @code{define_expand} RTX has four operands:
6275 The name. Each @code{define_expand} must have a name, since the only
6276 use for it is to refer to it by name.
6279 The RTL template. This is a vector of RTL expressions representing
6280 a sequence of separate instructions. Unlike @code{define_insn}, there
6281 is no implicit surrounding @code{PARALLEL}.
6284 The condition, a string containing a C expression. This expression is
6285 used to express how the availability of this pattern depends on
6286 subclasses of target machine, selected by command-line options when GCC
6287 is run. This is just like the condition of a @code{define_insn} that
6288 has a standard name. Therefore, the condition (if present) may not
6289 depend on the data in the insn being matched, but only the
6290 target-machine-type flags. The compiler needs to test these conditions
6291 during initialization in order to learn exactly which named instructions
6292 are available in a particular run.
6295 The preparation statements, a string containing zero or more C
6296 statements which are to be executed before RTL code is generated from
6299 Usually these statements prepare temporary registers for use as
6300 internal operands in the RTL template, but they can also generate RTL
6301 insns directly by calling routines such as @code{emit_insn}, etc.
6302 Any such insns precede the ones that come from the RTL template.
6305 Every RTL insn emitted by a @code{define_expand} must match some
6306 @code{define_insn} in the machine description. Otherwise, the compiler
6307 will crash when trying to generate code for the insn or trying to optimize
6310 The RTL template, in addition to controlling generation of RTL insns,
6311 also describes the operands that need to be specified when this pattern
6312 is used. In particular, it gives a predicate for each operand.
6314 A true operand, which needs to be specified in order to generate RTL from
6315 the pattern, should be described with a @code{match_operand} in its first
6316 occurrence in the RTL template. This enters information on the operand's
6317 predicate into the tables that record such things. GCC uses the
6318 information to preload the operand into a register if that is required for
6319 valid RTL code. If the operand is referred to more than once, subsequent
6320 references should use @code{match_dup}.
6322 The RTL template may also refer to internal ``operands'' which are
6323 temporary registers or labels used only within the sequence made by the
6324 @code{define_expand}. Internal operands are substituted into the RTL
6325 template with @code{match_dup}, never with @code{match_operand}. The
6326 values of the internal operands are not passed in as arguments by the
6327 compiler when it requests use of this pattern. Instead, they are computed
6328 within the pattern, in the preparation statements. These statements
6329 compute the values and store them into the appropriate elements of
6330 @code{operands} so that @code{match_dup} can find them.
6332 There are two special macros defined for use in the preparation statements:
6333 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
6340 Use the @code{DONE} macro to end RTL generation for the pattern. The
6341 only RTL insns resulting from the pattern on this occasion will be
6342 those already emitted by explicit calls to @code{emit_insn} within the
6343 preparation statements; the RTL template will not be generated.
6347 Make the pattern fail on this occasion. When a pattern fails, it means
6348 that the pattern was not truly available. The calling routines in the
6349 compiler will try other strategies for code generation using other patterns.
6351 Failure is currently supported only for binary (addition, multiplication,
6352 shifting, etc.) and bit-field (@code{extv}, @code{extzv}, and @code{insv})
6356 If the preparation falls through (invokes neither @code{DONE} nor
6357 @code{FAIL}), then the @code{define_expand} acts like a
6358 @code{define_insn} in that the RTL template is used to generate the
6361 The RTL template is not used for matching, only for generating the
6362 initial insn list. If the preparation statement always invokes
6363 @code{DONE} or @code{FAIL}, the RTL template may be reduced to a simple
6364 list of operands, such as this example:
6368 (define_expand "addsi3"
6369 [(match_operand:SI 0 "register_operand" "")
6370 (match_operand:SI 1 "register_operand" "")
6371 (match_operand:SI 2 "register_operand" "")]
6377 handle_add (operands[0], operands[1], operands[2]);
6383 Here is an example, the definition of left-shift for the SPUR chip:
6387 (define_expand "ashlsi3"
6388 [(set (match_operand:SI 0 "register_operand" "")
6392 (match_operand:SI 1 "register_operand" "")
6393 (match_operand:SI 2 "nonmemory_operand" "")))]
6402 if (GET_CODE (operands[2]) != CONST_INT
6403 || (unsigned) INTVAL (operands[2]) > 3)
6410 This example uses @code{define_expand} so that it can generate an RTL insn
6411 for shifting when the shift-count is in the supported range of 0 to 3 but
6412 fail in other cases where machine insns aren't available. When it fails,
6413 the compiler tries another strategy using different patterns (such as, a
6416 If the compiler were able to handle nontrivial condition-strings in
6417 patterns with names, then it would be possible to use a
6418 @code{define_insn} in that case. Here is another case (zero-extension
6419 on the 68000) which makes more use of the power of @code{define_expand}:
6422 (define_expand "zero_extendhisi2"
6423 [(set (match_operand:SI 0 "general_operand" "")
6425 (set (strict_low_part
6429 (match_operand:HI 1 "general_operand" ""))]
6431 "operands[1] = make_safe_from (operands[1], operands[0]);")
6435 @findex make_safe_from
6436 Here two RTL insns are generated, one to clear the entire output operand
6437 and the other to copy the input operand into its low half. This sequence
6438 is incorrect if the input operand refers to [the old value of] the output
6439 operand, so the preparation statement makes sure this isn't so. The
6440 function @code{make_safe_from} copies the @code{operands[1]} into a
6441 temporary register if it refers to @code{operands[0]}. It does this
6442 by emitting another RTL insn.
6444 Finally, a third example shows the use of an internal operand.
6445 Zero-extension on the SPUR chip is done by @code{and}-ing the result
6446 against a halfword mask. But this mask cannot be represented by a
6447 @code{const_int} because the constant value is too large to be legitimate
6448 on this machine. So it must be copied into a register with
6449 @code{force_reg} and then the register used in the @code{and}.
6452 (define_expand "zero_extendhisi2"
6453 [(set (match_operand:SI 0 "register_operand" "")
6455 (match_operand:HI 1 "register_operand" "")
6460 = force_reg (SImode, GEN_INT (65535)); ")
6463 @emph{Note:} If the @code{define_expand} is used to serve a
6464 standard binary or unary arithmetic operation or a bit-field operation,
6465 then the last insn it generates must not be a @code{code_label},
6466 @code{barrier} or @code{note}. It must be an @code{insn},
6467 @code{jump_insn} or @code{call_insn}. If you don't need a real insn
6468 at the end, emit an insn to copy the result of the operation into
6469 itself. Such an insn will generate no code, but it can avoid problems
6474 @node Insn Splitting
6475 @section Defining How to Split Instructions
6476 @cindex insn splitting
6477 @cindex instruction splitting
6478 @cindex splitting instructions
6480 There are two cases where you should specify how to split a pattern
6481 into multiple insns. On machines that have instructions requiring
6482 delay slots (@pxref{Delay Slots}) or that have instructions whose
6483 output is not available for multiple cycles (@pxref{Processor pipeline
6484 description}), the compiler phases that optimize these cases need to
6485 be able to move insns into one-instruction delay slots. However, some
6486 insns may generate more than one machine instruction. These insns
6487 cannot be placed into a delay slot.
6489 Often you can rewrite the single insn as a list of individual insns,
6490 each corresponding to one machine instruction. The disadvantage of
6491 doing so is that it will cause the compilation to be slower and require
6492 more space. If the resulting insns are too complex, it may also
6493 suppress some optimizations. The compiler splits the insn if there is a
6494 reason to believe that it might improve instruction or delay slot
6497 The insn combiner phase also splits putative insns. If three insns are
6498 merged into one insn with a complex expression that cannot be matched by
6499 some @code{define_insn} pattern, the combiner phase attempts to split
6500 the complex pattern into two insns that are recognized. Usually it can
6501 break the complex pattern into two patterns by splitting out some
6502 subexpression. However, in some other cases, such as performing an
6503 addition of a large constant in two insns on a RISC machine, the way to
6504 split the addition into two insns is machine-dependent.
6506 @findex define_split
6507 The @code{define_split} definition tells the compiler how to split a
6508 complex insn into several simpler insns. It looks like this:
6512 [@var{insn-pattern}]
6514 [@var{new-insn-pattern-1}
6515 @var{new-insn-pattern-2}
6517 "@var{preparation-statements}")
6520 @var{insn-pattern} is a pattern that needs to be split and
6521 @var{condition} is the final condition to be tested, as in a
6522 @code{define_insn}. When an insn matching @var{insn-pattern} and
6523 satisfying @var{condition} is found, it is replaced in the insn list
6524 with the insns given by @var{new-insn-pattern-1},
6525 @var{new-insn-pattern-2}, etc.
6527 The @var{preparation-statements} are similar to those statements that
6528 are specified for @code{define_expand} (@pxref{Expander Definitions})
6529 and are executed before the new RTL is generated to prepare for the
6530 generated code or emit some insns whose pattern is not fixed. Unlike
6531 those in @code{define_expand}, however, these statements must not
6532 generate any new pseudo-registers. Once reload has completed, they also
6533 must not allocate any space in the stack frame.
6535 Patterns are matched against @var{insn-pattern} in two different
6536 circumstances. If an insn needs to be split for delay slot scheduling
6537 or insn scheduling, the insn is already known to be valid, which means
6538 that it must have been matched by some @code{define_insn} and, if
6539 @code{reload_completed} is nonzero, is known to satisfy the constraints
6540 of that @code{define_insn}. In that case, the new insn patterns must
6541 also be insns that are matched by some @code{define_insn} and, if
6542 @code{reload_completed} is nonzero, must also satisfy the constraints
6543 of those definitions.
6545 As an example of this usage of @code{define_split}, consider the following
6546 example from @file{a29k.md}, which splits a @code{sign_extend} from
6547 @code{HImode} to @code{SImode} into a pair of shift insns:
6551 [(set (match_operand:SI 0 "gen_reg_operand" "")
6552 (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
6555 (ashift:SI (match_dup 1)
6558 (ashiftrt:SI (match_dup 0)
6561 @{ operands[1] = gen_lowpart (SImode, operands[1]); @}")
6564 When the combiner phase tries to split an insn pattern, it is always the
6565 case that the pattern is @emph{not} matched by any @code{define_insn}.
6566 The combiner pass first tries to split a single @code{set} expression
6567 and then the same @code{set} expression inside a @code{parallel}, but
6568 followed by a @code{clobber} of a pseudo-reg to use as a scratch
6569 register. In these cases, the combiner expects exactly two new insn
6570 patterns to be generated. It will verify that these patterns match some
6571 @code{define_insn} definitions, so you need not do this test in the
6572 @code{define_split} (of course, there is no point in writing a
6573 @code{define_split} that will never produce insns that match).
6575 Here is an example of this use of @code{define_split}, taken from
6580 [(set (match_operand:SI 0 "gen_reg_operand" "")
6581 (plus:SI (match_operand:SI 1 "gen_reg_operand" "")
6582 (match_operand:SI 2 "non_add_cint_operand" "")))]
6584 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
6585 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
6588 int low = INTVAL (operands[2]) & 0xffff;
6589 int high = (unsigned) INTVAL (operands[2]) >> 16;
6592 high++, low |= 0xffff0000;
6594 operands[3] = GEN_INT (high << 16);
6595 operands[4] = GEN_INT (low);
6599 Here the predicate @code{non_add_cint_operand} matches any
6600 @code{const_int} that is @emph{not} a valid operand of a single add
6601 insn. The add with the smaller displacement is written so that it
6602 can be substituted into the address of a subsequent operation.
6604 An example that uses a scratch register, from the same file, generates
6605 an equality comparison of a register and a large constant:
6609 [(set (match_operand:CC 0 "cc_reg_operand" "")
6610 (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
6611 (match_operand:SI 2 "non_short_cint_operand" "")))
6612 (clobber (match_operand:SI 3 "gen_reg_operand" ""))]
6613 "find_single_use (operands[0], insn, 0)
6614 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
6615 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
6616 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
6617 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
6620 /* @r{Get the constant we are comparing against, C, and see what it
6621 looks like sign-extended to 16 bits. Then see what constant
6622 could be XOR'ed with C to get the sign-extended value.} */
6624 int c = INTVAL (operands[2]);
6625 int sextc = (c << 16) >> 16;
6626 int xorv = c ^ sextc;
6628 operands[4] = GEN_INT (xorv);
6629 operands[5] = GEN_INT (sextc);
6633 To avoid confusion, don't write a single @code{define_split} that
6634 accepts some insns that match some @code{define_insn} as well as some
6635 insns that don't. Instead, write two separate @code{define_split}
6636 definitions, one for the insns that are valid and one for the insns that
6639 The splitter is allowed to split jump instructions into sequence of
6640 jumps or create new jumps in while splitting non-jump instructions. As
6641 the central flowgraph and branch prediction information needs to be updated,
6642 several restriction apply.
6644 Splitting of jump instruction into sequence that over by another jump
6645 instruction is always valid, as compiler expect identical behavior of new
6646 jump. When new sequence contains multiple jump instructions or new labels,
6647 more assistance is needed. Splitter is required to create only unconditional
6648 jumps, or simple conditional jump instructions. Additionally it must attach a
6649 @code{REG_BR_PROB} note to each conditional jump. A global variable
6650 @code{split_branch_probability} holds the probability of the original branch in case
6651 it was a simple conditional jump, @minus{}1 otherwise. To simplify
6652 recomputing of edge frequencies, the new sequence is required to have only
6653 forward jumps to the newly created labels.
6655 @findex define_insn_and_split
6656 For the common case where the pattern of a define_split exactly matches the
6657 pattern of a define_insn, use @code{define_insn_and_split}. It looks like
6661 (define_insn_and_split
6662 [@var{insn-pattern}]
6664 "@var{output-template}"
6665 "@var{split-condition}"
6666 [@var{new-insn-pattern-1}
6667 @var{new-insn-pattern-2}
6669 "@var{preparation-statements}"
6670 [@var{insn-attributes}])
6674 @var{insn-pattern}, @var{condition}, @var{output-template}, and
6675 @var{insn-attributes} are used as in @code{define_insn}. The
6676 @var{new-insn-pattern} vector and the @var{preparation-statements} are used as
6677 in a @code{define_split}. The @var{split-condition} is also used as in
6678 @code{define_split}, with the additional behavior that if the condition starts
6679 with @samp{&&}, the condition used for the split will be the constructed as a
6680 logical ``and'' of the split condition with the insn condition. For example,
6684 (define_insn_and_split "zero_extendhisi2_and"
6685 [(set (match_operand:SI 0 "register_operand" "=r")
6686 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
6687 (clobber (reg:CC 17))]
6688 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
6690 "&& reload_completed"
6691 [(parallel [(set (match_dup 0)
6692 (and:SI (match_dup 0) (const_int 65535)))
6693 (clobber (reg:CC 17))])]
6695 [(set_attr "type" "alu1")])
6699 In this case, the actual split condition will be
6700 @samp{TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed}.
6702 The @code{define_insn_and_split} construction provides exactly the same
6703 functionality as two separate @code{define_insn} and @code{define_split}
6704 patterns. It exists for compactness, and as a maintenance tool to prevent
6705 having to ensure the two patterns' templates match.
6709 @node Including Patterns
6710 @section Including Patterns in Machine Descriptions.
6711 @cindex insn includes
6714 The @code{include} pattern tells the compiler tools where to
6715 look for patterns that are in files other than in the file
6716 @file{.md}. This is used only at build time and there is no preprocessing allowed.
6730 (include "filestuff")
6734 Where @var{pathname} is a string that specifies the location of the file,
6735 specifies the include file to be in @file{gcc/config/target/filestuff}. The
6736 directory @file{gcc/config/target} is regarded as the default directory.
6739 Machine descriptions may be split up into smaller more manageable subsections
6740 and placed into subdirectories.
6746 (include "BOGUS/filestuff")
6750 the include file is specified to be in @file{gcc/config/@var{target}/BOGUS/filestuff}.
6752 Specifying an absolute path for the include file such as;
6755 (include "/u2/BOGUS/filestuff")
6758 is permitted but is not encouraged.
6760 @subsection RTL Generation Tool Options for Directory Search
6761 @cindex directory options .md
6762 @cindex options, directory search
6763 @cindex search options
6765 The @option{-I@var{dir}} option specifies directories to search for machine descriptions.
6770 genrecog -I/p1/abc/proc1 -I/p2/abcd/pro2 target.md
6775 Add the directory @var{dir} to the head of the list of directories to be
6776 searched for header files. This can be used to override a system machine definition
6777 file, substituting your own version, since these directories are
6778 searched before the default machine description file directories. If you use more than
6779 one @option{-I} option, the directories are scanned in left-to-right
6780 order; the standard default directory come after.
6785 @node Peephole Definitions
6786 @section Machine-Specific Peephole Optimizers
6787 @cindex peephole optimizer definitions
6788 @cindex defining peephole optimizers
6790 In addition to instruction patterns the @file{md} file may contain
6791 definitions of machine-specific peephole optimizations.
6793 The combiner does not notice certain peephole optimizations when the data
6794 flow in the program does not suggest that it should try them. For example,
6795 sometimes two consecutive insns related in purpose can be combined even
6796 though the second one does not appear to use a register computed in the
6797 first one. A machine-specific peephole optimizer can detect such
6800 There are two forms of peephole definitions that may be used. The
6801 original @code{define_peephole} is run at assembly output time to
6802 match insns and substitute assembly text. Use of @code{define_peephole}
6805 A newer @code{define_peephole2} matches insns and substitutes new
6806 insns. The @code{peephole2} pass is run after register allocation
6807 but before scheduling, which may result in much better code for
6808 targets that do scheduling.
6811 * define_peephole:: RTL to Text Peephole Optimizers
6812 * define_peephole2:: RTL to RTL Peephole Optimizers
6817 @node define_peephole
6818 @subsection RTL to Text Peephole Optimizers
6819 @findex define_peephole
6822 A definition looks like this:
6826 [@var{insn-pattern-1}
6827 @var{insn-pattern-2}
6831 "@var{optional-insn-attributes}")
6835 The last string operand may be omitted if you are not using any
6836 machine-specific information in this machine description. If present,
6837 it must obey the same rules as in a @code{define_insn}.
6839 In this skeleton, @var{insn-pattern-1} and so on are patterns to match
6840 consecutive insns. The optimization applies to a sequence of insns when
6841 @var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches
6842 the next, and so on.
6844 Each of the insns matched by a peephole must also match a
6845 @code{define_insn}. Peepholes are checked only at the last stage just
6846 before code generation, and only optionally. Therefore, any insn which
6847 would match a peephole but no @code{define_insn} will cause a crash in code
6848 generation in an unoptimized compilation, or at various optimization
6851 The operands of the insns are matched with @code{match_operands},
6852 @code{match_operator}, and @code{match_dup}, as usual. What is not
6853 usual is that the operand numbers apply to all the insn patterns in the
6854 definition. So, you can check for identical operands in two insns by
6855 using @code{match_operand} in one insn and @code{match_dup} in the
6858 The operand constraints used in @code{match_operand} patterns do not have
6859 any direct effect on the applicability of the peephole, but they will
6860 be validated afterward, so make sure your constraints are general enough
6861 to apply whenever the peephole matches. If the peephole matches
6862 but the constraints are not satisfied, the compiler will crash.
6864 It is safe to omit constraints in all the operands of the peephole; or
6865 you can write constraints which serve as a double-check on the criteria
6868 Once a sequence of insns matches the patterns, the @var{condition} is
6869 checked. This is a C expression which makes the final decision whether to
6870 perform the optimization (we do so if the expression is nonzero). If
6871 @var{condition} is omitted (in other words, the string is empty) then the
6872 optimization is applied to every sequence of insns that matches the
6875 The defined peephole optimizations are applied after register allocation
6876 is complete. Therefore, the peephole definition can check which
6877 operands have ended up in which kinds of registers, just by looking at
6880 @findex prev_active_insn
6881 The way to refer to the operands in @var{condition} is to write
6882 @code{operands[@var{i}]} for operand number @var{i} (as matched by
6883 @code{(match_operand @var{i} @dots{})}). Use the variable @code{insn}
6884 to refer to the last of the insns being matched; use
6885 @code{prev_active_insn} to find the preceding insns.
6887 @findex dead_or_set_p
6888 When optimizing computations with intermediate results, you can use
6889 @var{condition} to match only when the intermediate results are not used
6890 elsewhere. Use the C expression @code{dead_or_set_p (@var{insn},
6891 @var{op})}, where @var{insn} is the insn in which you expect the value
6892 to be used for the last time (from the value of @code{insn}, together
6893 with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate
6894 value (from @code{operands[@var{i}]}).
6896 Applying the optimization means replacing the sequence of insns with one
6897 new insn. The @var{template} controls ultimate output of assembler code
6898 for this combined insn. It works exactly like the template of a
6899 @code{define_insn}. Operand numbers in this template are the same ones
6900 used in matching the original sequence of insns.
6902 The result of a defined peephole optimizer does not need to match any of
6903 the insn patterns in the machine description; it does not even have an
6904 opportunity to match them. The peephole optimizer definition itself serves
6905 as the insn pattern to control how the insn is output.
6907 Defined peephole optimizers are run as assembler code is being output,
6908 so the insns they produce are never combined or rearranged in any way.
6910 Here is an example, taken from the 68000 machine description:
6914 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
6915 (set (match_operand:DF 0 "register_operand" "=f")
6916 (match_operand:DF 1 "register_operand" "ad"))]
6917 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
6920 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
6922 output_asm_insn ("move.l %1,(sp)", xoperands);
6923 output_asm_insn ("move.l %1,-(sp)", operands);
6924 return "fmove.d (sp)+,%0";
6926 output_asm_insn ("movel %1,sp@@", xoperands);
6927 output_asm_insn ("movel %1,sp@@-", operands);
6928 return "fmoved sp@@+,%0";
6934 The effect of this optimization is to change
6960 If a peephole matches a sequence including one or more jump insns, you must
6961 take account of the flags such as @code{CC_REVERSED} which specify that the
6962 condition codes are represented in an unusual manner. The compiler
6963 automatically alters any ordinary conditional jumps which occur in such
6964 situations, but the compiler cannot alter jumps which have been replaced by
6965 peephole optimizations. So it is up to you to alter the assembler code
6966 that the peephole produces. Supply C code to write the assembler output,
6967 and in this C code check the condition code status flags and change the
6968 assembler code as appropriate.
6971 @var{insn-pattern-1} and so on look @emph{almost} like the second
6972 operand of @code{define_insn}. There is one important difference: the
6973 second operand of @code{define_insn} consists of one or more RTX's
6974 enclosed in square brackets. Usually, there is only one: then the same
6975 action can be written as an element of a @code{define_peephole}. But
6976 when there are multiple actions in a @code{define_insn}, they are
6977 implicitly enclosed in a @code{parallel}. Then you must explicitly
6978 write the @code{parallel}, and the square brackets within it, in the
6979 @code{define_peephole}. Thus, if an insn pattern looks like this,
6982 (define_insn "divmodsi4"
6983 [(set (match_operand:SI 0 "general_operand" "=d")
6984 (div:SI (match_operand:SI 1 "general_operand" "0")
6985 (match_operand:SI 2 "general_operand" "dmsK")))
6986 (set (match_operand:SI 3 "general_operand" "=d")
6987 (mod:SI (match_dup 1) (match_dup 2)))]
6989 "divsl%.l %2,%3:%0")
6993 then the way to mention this insn in a peephole is as follows:
6999 [(set (match_operand:SI 0 "general_operand" "=d")
7000 (div:SI (match_operand:SI 1 "general_operand" "0")
7001 (match_operand:SI 2 "general_operand" "dmsK")))
7002 (set (match_operand:SI 3 "general_operand" "=d")
7003 (mod:SI (match_dup 1) (match_dup 2)))])
7010 @node define_peephole2
7011 @subsection RTL to RTL Peephole Optimizers
7012 @findex define_peephole2
7014 The @code{define_peephole2} definition tells the compiler how to
7015 substitute one sequence of instructions for another sequence,
7016 what additional scratch registers may be needed and what their
7021 [@var{insn-pattern-1}
7022 @var{insn-pattern-2}
7025 [@var{new-insn-pattern-1}
7026 @var{new-insn-pattern-2}
7028 "@var{preparation-statements}")
7031 The definition is almost identical to @code{define_split}
7032 (@pxref{Insn Splitting}) except that the pattern to match is not a
7033 single instruction, but a sequence of instructions.
7035 It is possible to request additional scratch registers for use in the
7036 output template. If appropriate registers are not free, the pattern
7037 will simply not match.
7039 @findex match_scratch
7041 Scratch registers are requested with a @code{match_scratch} pattern at
7042 the top level of the input pattern. The allocated register (initially) will
7043 be dead at the point requested within the original sequence. If the scratch
7044 is used at more than a single point, a @code{match_dup} pattern at the
7045 top level of the input pattern marks the last position in the input sequence
7046 at which the register must be available.
7048 Here is an example from the IA-32 machine description:
7052 [(match_scratch:SI 2 "r")
7053 (parallel [(set (match_operand:SI 0 "register_operand" "")
7054 (match_operator:SI 3 "arith_or_logical_operator"
7056 (match_operand:SI 1 "memory_operand" "")]))
7057 (clobber (reg:CC 17))])]
7058 "! optimize_size && ! TARGET_READ_MODIFY"
7059 [(set (match_dup 2) (match_dup 1))
7060 (parallel [(set (match_dup 0)
7061 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
7062 (clobber (reg:CC 17))])]
7067 This pattern tries to split a load from its use in the hopes that we'll be
7068 able to schedule around the memory load latency. It allocates a single
7069 @code{SImode} register of class @code{GENERAL_REGS} (@code{"r"}) that needs
7070 to be live only at the point just before the arithmetic.
7072 A real example requiring extended scratch lifetimes is harder to come by,
7073 so here's a silly made-up example:
7077 [(match_scratch:SI 4 "r")
7078 (set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
7079 (set (match_operand:SI 2 "" "") (match_dup 1))
7081 (set (match_operand:SI 3 "" "") (match_dup 1))]
7082 "/* @r{determine 1 does not overlap 0 and 2} */"
7083 [(set (match_dup 4) (match_dup 1))
7084 (set (match_dup 0) (match_dup 4))
7085 (set (match_dup 2) (match_dup 4))]
7086 (set (match_dup 3) (match_dup 4))]
7091 If we had not added the @code{(match_dup 4)} in the middle of the input
7092 sequence, it might have been the case that the register we chose at the
7093 beginning of the sequence is killed by the first or second @code{set}.
7097 @node Insn Attributes
7098 @section Instruction Attributes
7099 @cindex insn attributes
7100 @cindex instruction attributes
7102 In addition to describing the instruction supported by the target machine,
7103 the @file{md} file also defines a group of @dfn{attributes} and a set of
7104 values for each. Every generated insn is assigned a value for each attribute.
7105 One possible attribute would be the effect that the insn has on the machine's
7106 condition code. This attribute can then be used by @code{NOTICE_UPDATE_CC}
7107 to track the condition codes.
7110 * Defining Attributes:: Specifying attributes and their values.
7111 * Expressions:: Valid expressions for attribute values.
7112 * Tagging Insns:: Assigning attribute values to insns.
7113 * Attr Example:: An example of assigning attributes.
7114 * Insn Lengths:: Computing the length of insns.
7115 * Constant Attributes:: Defining attributes that are constant.
7116 * Delay Slots:: Defining delay slots required for a machine.
7117 * Processor pipeline description:: Specifying information for insn scheduling.
7122 @node Defining Attributes
7123 @subsection Defining Attributes and their Values
7124 @cindex defining attributes and their values
7125 @cindex attributes, defining
7128 The @code{define_attr} expression is used to define each attribute required
7129 by the target machine. It looks like:
7132 (define_attr @var{name} @var{list-of-values} @var{default})
7135 @var{name} is a string specifying the name of the attribute being defined.
7136 Some attributes are used in a special way by the rest of the compiler. The
7137 @code{enabled} attribute can be used to conditionally enable or disable
7138 insn alternatives (@pxref{Disable Insn Alternatives}). The @code{predicable}
7139 attribute, together with a suitable @code{define_cond_exec}
7140 (@pxref{Conditional Execution}), can be used to automatically generate
7141 conditional variants of instruction patterns. The compiler internally uses
7142 the names @code{ce_enabled} and @code{nonce_enabled}, so they should not be
7143 used elsewhere as alternative names.
7145 @var{list-of-values} is either a string that specifies a comma-separated
7146 list of values that can be assigned to the attribute, or a null string to
7147 indicate that the attribute takes numeric values.
7149 @var{default} is an attribute expression that gives the value of this
7150 attribute for insns that match patterns whose definition does not include
7151 an explicit value for this attribute. @xref{Attr Example}, for more
7152 information on the handling of defaults. @xref{Constant Attributes},
7153 for information on attributes that do not depend on any particular insn.
7156 For each defined attribute, a number of definitions are written to the
7157 @file{insn-attr.h} file. For cases where an explicit set of values is
7158 specified for an attribute, the following are defined:
7162 A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}.
7165 An enumerated class is defined for @samp{attr_@var{name}} with
7166 elements of the form @samp{@var{upper-name}_@var{upper-value}} where
7167 the attribute name and value are first converted to uppercase.
7170 A function @samp{get_attr_@var{name}} is defined that is passed an insn and
7171 returns the attribute value for that insn.
7174 For example, if the following is present in the @file{md} file:
7177 (define_attr "type" "branch,fp,load,store,arith" @dots{})
7181 the following lines will be written to the file @file{insn-attr.h}.
7184 #define HAVE_ATTR_type
7185 enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD,
7186 TYPE_STORE, TYPE_ARITH@};
7187 extern enum attr_type get_attr_type ();
7190 If the attribute takes numeric values, no @code{enum} type will be
7191 defined and the function to obtain the attribute's value will return
7194 There are attributes which are tied to a specific meaning. These
7195 attributes are not free to use for other purposes:
7199 The @code{length} attribute is used to calculate the length of emitted
7200 code chunks. This is especially important when verifying branch
7201 distances. @xref{Insn Lengths}.
7204 The @code{enabled} attribute can be defined to prevent certain
7205 alternatives of an insn definition from being used during code
7206 generation. @xref{Disable Insn Alternatives}.
7209 @findex define_enum_attr
7210 @anchor{define_enum_attr}
7211 Another way of defining an attribute is to use:
7214 (define_enum_attr "@var{attr}" "@var{enum}" @var{default})
7217 This works in just the same way as @code{define_attr}, except that
7218 the list of values is taken from a separate enumeration called
7219 @var{enum} (@pxref{define_enum}). This form allows you to use
7220 the same list of values for several attributes without having to
7221 repeat the list each time. For example:
7224 (define_enum "processor" [
7229 (define_enum_attr "arch" "processor"
7230 (const (symbol_ref "target_arch")))
7231 (define_enum_attr "tune" "processor"
7232 (const (symbol_ref "target_tune")))
7235 defines the same attributes as:
7238 (define_attr "arch" "model_a,model_b,@dots{}"
7239 (const (symbol_ref "target_arch")))
7240 (define_attr "tune" "model_a,model_b,@dots{}"
7241 (const (symbol_ref "target_tune")))
7244 but without duplicating the processor list. The second example defines two
7245 separate C enums (@code{attr_arch} and @code{attr_tune}) whereas the first
7246 defines a single C enum (@code{processor}).
7250 @subsection Attribute Expressions
7251 @cindex attribute expressions
7253 RTL expressions used to define attributes use the codes described above
7254 plus a few specific to attribute definitions, to be discussed below.
7255 Attribute value expressions must have one of the following forms:
7258 @cindex @code{const_int} and attributes
7259 @item (const_int @var{i})
7260 The integer @var{i} specifies the value of a numeric attribute. @var{i}
7261 must be non-negative.
7263 The value of a numeric attribute can be specified either with a
7264 @code{const_int}, or as an integer represented as a string in
7265 @code{const_string}, @code{eq_attr} (see below), @code{attr},
7266 @code{symbol_ref}, simple arithmetic expressions, and @code{set_attr}
7267 overrides on specific instructions (@pxref{Tagging Insns}).
7269 @cindex @code{const_string} and attributes
7270 @item (const_string @var{value})
7271 The string @var{value} specifies a constant attribute value.
7272 If @var{value} is specified as @samp{"*"}, it means that the default value of
7273 the attribute is to be used for the insn containing this expression.
7274 @samp{"*"} obviously cannot be used in the @var{default} expression
7275 of a @code{define_attr}.
7277 If the attribute whose value is being specified is numeric, @var{value}
7278 must be a string containing a non-negative integer (normally
7279 @code{const_int} would be used in this case). Otherwise, it must
7280 contain one of the valid values for the attribute.
7282 @cindex @code{if_then_else} and attributes
7283 @item (if_then_else @var{test} @var{true-value} @var{false-value})
7284 @var{test} specifies an attribute test, whose format is defined below.
7285 The value of this expression is @var{true-value} if @var{test} is true,
7286 otherwise it is @var{false-value}.
7288 @cindex @code{cond} and attributes
7289 @item (cond [@var{test1} @var{value1} @dots{}] @var{default})
7290 The first operand of this expression is a vector containing an even
7291 number of expressions and consisting of pairs of @var{test} and @var{value}
7292 expressions. The value of the @code{cond} expression is that of the
7293 @var{value} corresponding to the first true @var{test} expression. If
7294 none of the @var{test} expressions are true, the value of the @code{cond}
7295 expression is that of the @var{default} expression.
7298 @var{test} expressions can have one of the following forms:
7301 @cindex @code{const_int} and attribute tests
7302 @item (const_int @var{i})
7303 This test is true if @var{i} is nonzero and false otherwise.
7305 @cindex @code{not} and attributes
7306 @cindex @code{ior} and attributes
7307 @cindex @code{and} and attributes
7308 @item (not @var{test})
7309 @itemx (ior @var{test1} @var{test2})
7310 @itemx (and @var{test1} @var{test2})
7311 These tests are true if the indicated logical function is true.
7313 @cindex @code{match_operand} and attributes
7314 @item (match_operand:@var{m} @var{n} @var{pred} @var{constraints})
7315 This test is true if operand @var{n} of the insn whose attribute value
7316 is being determined has mode @var{m} (this part of the test is ignored
7317 if @var{m} is @code{VOIDmode}) and the function specified by the string
7318 @var{pred} returns a nonzero value when passed operand @var{n} and mode
7319 @var{m} (this part of the test is ignored if @var{pred} is the null
7322 The @var{constraints} operand is ignored and should be the null string.
7324 @cindex @code{match_test} and attributes
7325 @item (match_test @var{c-expr})
7326 The test is true if C expression @var{c-expr} is true. In non-constant
7327 attributes, @var{c-expr} has access to the following variables:
7331 The rtl instruction under test.
7332 @item which_alternative
7333 The @code{define_insn} alternative that @var{insn} matches.
7334 @xref{Output Statement}.
7336 An array of @var{insn}'s rtl operands.
7339 @var{c-expr} behaves like the condition in a C @code{if} statement,
7340 so there is no need to explicitly convert the expression into a boolean
7341 0 or 1 value. For example, the following two tests are equivalent:
7344 (match_test "x & 2")
7345 (match_test "(x & 2) != 0")
7348 @cindex @code{le} and attributes
7349 @cindex @code{leu} and attributes
7350 @cindex @code{lt} and attributes
7351 @cindex @code{gt} and attributes
7352 @cindex @code{gtu} and attributes
7353 @cindex @code{ge} and attributes
7354 @cindex @code{geu} and attributes
7355 @cindex @code{ne} and attributes
7356 @cindex @code{eq} and attributes
7357 @cindex @code{plus} and attributes
7358 @cindex @code{minus} and attributes
7359 @cindex @code{mult} and attributes
7360 @cindex @code{div} and attributes
7361 @cindex @code{mod} and attributes
7362 @cindex @code{abs} and attributes
7363 @cindex @code{neg} and attributes
7364 @cindex @code{ashift} and attributes
7365 @cindex @code{lshiftrt} and attributes
7366 @cindex @code{ashiftrt} and attributes
7367 @item (le @var{arith1} @var{arith2})
7368 @itemx (leu @var{arith1} @var{arith2})
7369 @itemx (lt @var{arith1} @var{arith2})
7370 @itemx (ltu @var{arith1} @var{arith2})
7371 @itemx (gt @var{arith1} @var{arith2})
7372 @itemx (gtu @var{arith1} @var{arith2})
7373 @itemx (ge @var{arith1} @var{arith2})
7374 @itemx (geu @var{arith1} @var{arith2})
7375 @itemx (ne @var{arith1} @var{arith2})
7376 @itemx (eq @var{arith1} @var{arith2})
7377 These tests are true if the indicated comparison of the two arithmetic
7378 expressions is true. Arithmetic expressions are formed with
7379 @code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod},
7380 @code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not},
7381 @code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions.
7384 @code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn
7385 Lengths},for additional forms). @code{symbol_ref} is a string
7386 denoting a C expression that yields an @code{int} when evaluated by the
7387 @samp{get_attr_@dots{}} routine. It should normally be a global
7391 @item (eq_attr @var{name} @var{value})
7392 @var{name} is a string specifying the name of an attribute.
7394 @var{value} is a string that is either a valid value for attribute
7395 @var{name}, a comma-separated list of values, or @samp{!} followed by a
7396 value or list. If @var{value} does not begin with a @samp{!}, this
7397 test is true if the value of the @var{name} attribute of the current
7398 insn is in the list specified by @var{value}. If @var{value} begins
7399 with a @samp{!}, this test is true if the attribute's value is
7400 @emph{not} in the specified list.
7405 (eq_attr "type" "load,store")
7412 (ior (eq_attr "type" "load") (eq_attr "type" "store"))
7415 If @var{name} specifies an attribute of @samp{alternative}, it refers to the
7416 value of the compiler variable @code{which_alternative}
7417 (@pxref{Output Statement}) and the values must be small integers. For
7421 (eq_attr "alternative" "2,3")
7428 (ior (eq (symbol_ref "which_alternative") (const_int 2))
7429 (eq (symbol_ref "which_alternative") (const_int 3)))
7432 Note that, for most attributes, an @code{eq_attr} test is simplified in cases
7433 where the value of the attribute being tested is known for all insns matching
7434 a particular pattern. This is by far the most common case.
7437 @item (attr_flag @var{name})
7438 The value of an @code{attr_flag} expression is true if the flag
7439 specified by @var{name} is true for the @code{insn} currently being
7442 @var{name} is a string specifying one of a fixed set of flags to test.
7443 Test the flags @code{forward} and @code{backward} to determine the
7444 direction of a conditional branch. Test the flags @code{very_likely},
7445 @code{likely}, @code{very_unlikely}, and @code{unlikely} to determine
7446 if a conditional branch is expected to be taken.
7448 If the @code{very_likely} flag is true, then the @code{likely} flag is also
7449 true. Likewise for the @code{very_unlikely} and @code{unlikely} flags.
7451 This example describes a conditional branch delay slot which
7452 can be nullified for forward branches that are taken (annul-true) or
7453 for backward branches which are not taken (annul-false).
7456 (define_delay (eq_attr "type" "cbranch")
7457 [(eq_attr "in_branch_delay" "true")
7458 (and (eq_attr "in_branch_delay" "true")
7459 (attr_flag "forward"))
7460 (and (eq_attr "in_branch_delay" "true")
7461 (attr_flag "backward"))])
7464 The @code{forward} and @code{backward} flags are false if the current
7465 @code{insn} being scheduled is not a conditional branch.
7467 The @code{very_likely} and @code{likely} flags are true if the
7468 @code{insn} being scheduled is not a conditional branch.
7469 The @code{very_unlikely} and @code{unlikely} flags are false if the
7470 @code{insn} being scheduled is not a conditional branch.
7472 @code{attr_flag} is only used during delay slot scheduling and has no
7473 meaning to other passes of the compiler.
7476 @item (attr @var{name})
7477 The value of another attribute is returned. This is most useful
7478 for numeric attributes, as @code{eq_attr} and @code{attr_flag}
7479 produce more efficient code for non-numeric attributes.
7485 @subsection Assigning Attribute Values to Insns
7486 @cindex tagging insns
7487 @cindex assigning attribute values to insns
7489 The value assigned to an attribute of an insn is primarily determined by
7490 which pattern is matched by that insn (or which @code{define_peephole}
7491 generated it). Every @code{define_insn} and @code{define_peephole} can
7492 have an optional last argument to specify the values of attributes for
7493 matching insns. The value of any attribute not specified in a particular
7494 insn is set to the default value for that attribute, as specified in its
7495 @code{define_attr}. Extensive use of default values for attributes
7496 permits the specification of the values for only one or two attributes
7497 in the definition of most insn patterns, as seen in the example in the
7500 The optional last argument of @code{define_insn} and
7501 @code{define_peephole} is a vector of expressions, each of which defines
7502 the value for a single attribute. The most general way of assigning an
7503 attribute's value is to use a @code{set} expression whose first operand is an
7504 @code{attr} expression giving the name of the attribute being set. The
7505 second operand of the @code{set} is an attribute expression
7506 (@pxref{Expressions}) giving the value of the attribute.
7508 When the attribute value depends on the @samp{alternative} attribute
7509 (i.e., which is the applicable alternative in the constraint of the
7510 insn), the @code{set_attr_alternative} expression can be used. It
7511 allows the specification of a vector of attribute expressions, one for
7515 When the generality of arbitrary attribute expressions is not required,
7516 the simpler @code{set_attr} expression can be used, which allows
7517 specifying a string giving either a single attribute value or a list
7518 of attribute values, one for each alternative.
7520 The form of each of the above specifications is shown below. In each case,
7521 @var{name} is a string specifying the attribute to be set.
7524 @item (set_attr @var{name} @var{value-string})
7525 @var{value-string} is either a string giving the desired attribute value,
7526 or a string containing a comma-separated list giving the values for
7527 succeeding alternatives. The number of elements must match the number
7528 of alternatives in the constraint of the insn pattern.
7530 Note that it may be useful to specify @samp{*} for some alternative, in
7531 which case the attribute will assume its default value for insns matching
7534 @findex set_attr_alternative
7535 @item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}])
7536 Depending on the alternative of the insn, the value will be one of the
7537 specified values. This is a shorthand for using a @code{cond} with
7538 tests on the @samp{alternative} attribute.
7541 @item (set (attr @var{name}) @var{value})
7542 The first operand of this @code{set} must be the special RTL expression
7543 @code{attr}, whose sole operand is a string giving the name of the
7544 attribute being set. @var{value} is the value of the attribute.
7547 The following shows three different ways of representing the same
7548 attribute value specification:
7551 (set_attr "type" "load,store,arith")
7553 (set_attr_alternative "type"
7554 [(const_string "load") (const_string "store")
7555 (const_string "arith")])
7558 (cond [(eq_attr "alternative" "1") (const_string "load")
7559 (eq_attr "alternative" "2") (const_string "store")]
7560 (const_string "arith")))
7564 @findex define_asm_attributes
7565 The @code{define_asm_attributes} expression provides a mechanism to
7566 specify the attributes assigned to insns produced from an @code{asm}
7567 statement. It has the form:
7570 (define_asm_attributes [@var{attr-sets}])
7574 where @var{attr-sets} is specified the same as for both the
7575 @code{define_insn} and the @code{define_peephole} expressions.
7577 These values will typically be the ``worst case'' attribute values. For
7578 example, they might indicate that the condition code will be clobbered.
7580 A specification for a @code{length} attribute is handled specially. The
7581 way to compute the length of an @code{asm} insn is to multiply the
7582 length specified in the expression @code{define_asm_attributes} by the
7583 number of machine instructions specified in the @code{asm} statement,
7584 determined by counting the number of semicolons and newlines in the
7585 string. Therefore, the value of the @code{length} attribute specified
7586 in a @code{define_asm_attributes} should be the maximum possible length
7587 of a single machine instruction.
7592 @subsection Example of Attribute Specifications
7593 @cindex attribute specifications example
7594 @cindex attribute specifications
7596 The judicious use of defaulting is important in the efficient use of
7597 insn attributes. Typically, insns are divided into @dfn{types} and an
7598 attribute, customarily called @code{type}, is used to represent this
7599 value. This attribute is normally used only to define the default value
7600 for other attributes. An example will clarify this usage.
7602 Assume we have a RISC machine with a condition code and in which only
7603 full-word operations are performed in registers. Let us assume that we
7604 can divide all insns into loads, stores, (integer) arithmetic
7605 operations, floating point operations, and branches.
7607 Here we will concern ourselves with determining the effect of an insn on
7608 the condition code and will limit ourselves to the following possible
7609 effects: The condition code can be set unpredictably (clobbered), not
7610 be changed, be set to agree with the results of the operation, or only
7611 changed if the item previously set into the condition code has been
7614 Here is part of a sample @file{md} file for such a machine:
7617 (define_attr "type" "load,store,arith,fp,branch" (const_string "arith"))
7619 (define_attr "cc" "clobber,unchanged,set,change0"
7620 (cond [(eq_attr "type" "load")
7621 (const_string "change0")
7622 (eq_attr "type" "store,branch")
7623 (const_string "unchanged")
7624 (eq_attr "type" "arith")
7625 (if_then_else (match_operand:SI 0 "" "")
7626 (const_string "set")
7627 (const_string "clobber"))]
7628 (const_string "clobber")))
7631 [(set (match_operand:SI 0 "general_operand" "=r,r,m")
7632 (match_operand:SI 1 "general_operand" "r,m,r"))]
7638 [(set_attr "type" "arith,load,store")])
7641 Note that we assume in the above example that arithmetic operations
7642 performed on quantities smaller than a machine word clobber the condition
7643 code since they will set the condition code to a value corresponding to the
7649 @subsection Computing the Length of an Insn
7650 @cindex insn lengths, computing
7651 @cindex computing the length of an insn
7653 For many machines, multiple types of branch instructions are provided, each
7654 for different length branch displacements. In most cases, the assembler
7655 will choose the correct instruction to use. However, when the assembler
7656 cannot do so, GCC can when a special attribute, the @code{length}
7657 attribute, is defined. This attribute must be defined to have numeric
7658 values by specifying a null string in its @code{define_attr}.
7660 In the case of the @code{length} attribute, two additional forms of
7661 arithmetic terms are allowed in test expressions:
7664 @cindex @code{match_dup} and attributes
7665 @item (match_dup @var{n})
7666 This refers to the address of operand @var{n} of the current insn, which
7667 must be a @code{label_ref}.
7669 @cindex @code{pc} and attributes
7671 This refers to the address of the @emph{current} insn. It might have
7672 been more consistent with other usage to make this the address of the
7673 @emph{next} insn but this would be confusing because the length of the
7674 current insn is to be computed.
7677 @cindex @code{addr_vec}, length of
7678 @cindex @code{addr_diff_vec}, length of
7679 For normal insns, the length will be determined by value of the
7680 @code{length} attribute. In the case of @code{addr_vec} and
7681 @code{addr_diff_vec} insn patterns, the length is computed as
7682 the number of vectors multiplied by the size of each vector.
7684 Lengths are measured in addressable storage units (bytes).
7686 The following macros can be used to refine the length computation:
7689 @findex ADJUST_INSN_LENGTH
7690 @item ADJUST_INSN_LENGTH (@var{insn}, @var{length})
7691 If defined, modifies the length assigned to instruction @var{insn} as a
7692 function of the context in which it is used. @var{length} is an lvalue
7693 that contains the initially computed length of the insn and should be
7694 updated with the correct length of the insn.
7696 This macro will normally not be required. A case in which it is
7697 required is the ROMP@. On this machine, the size of an @code{addr_vec}
7698 insn must be increased by two to compensate for the fact that alignment
7702 @findex get_attr_length
7703 The routine that returns @code{get_attr_length} (the value of the
7704 @code{length} attribute) can be used by the output routine to
7705 determine the form of the branch instruction to be written, as the
7706 example below illustrates.
7708 As an example of the specification of variable-length branches, consider
7709 the IBM 360. If we adopt the convention that a register will be set to
7710 the starting address of a function, we can jump to labels within 4k of
7711 the start using a four-byte instruction. Otherwise, we need a six-byte
7712 sequence to load the address from memory and then branch to it.
7714 On such a machine, a pattern for a branch instruction might be specified
7720 (label_ref (match_operand 0 "" "")))]
7723 return (get_attr_length (insn) == 4
7724 ? "b %l0" : "l r15,=a(%l0); br r15");
7726 [(set (attr "length")
7727 (if_then_else (lt (match_dup 0) (const_int 4096))
7734 @node Constant Attributes
7735 @subsection Constant Attributes
7736 @cindex constant attributes
7738 A special form of @code{define_attr}, where the expression for the
7739 default value is a @code{const} expression, indicates an attribute that
7740 is constant for a given run of the compiler. Constant attributes may be
7741 used to specify which variety of processor is used. For example,
7744 (define_attr "cpu" "m88100,m88110,m88000"
7746 (cond [(symbol_ref "TARGET_88100") (const_string "m88100")
7747 (symbol_ref "TARGET_88110") (const_string "m88110")]
7748 (const_string "m88000"))))
7750 (define_attr "memory" "fast,slow"
7752 (if_then_else (symbol_ref "TARGET_FAST_MEM")
7753 (const_string "fast")
7754 (const_string "slow"))))
7757 The routine generated for constant attributes has no parameters as it
7758 does not depend on any particular insn. RTL expressions used to define
7759 the value of a constant attribute may use the @code{symbol_ref} form,
7760 but may not use either the @code{match_operand} form or @code{eq_attr}
7761 forms involving insn attributes.
7766 @subsection Delay Slot Scheduling
7767 @cindex delay slots, defining
7769 The insn attribute mechanism can be used to specify the requirements for
7770 delay slots, if any, on a target machine. An instruction is said to
7771 require a @dfn{delay slot} if some instructions that are physically
7772 after the instruction are executed as if they were located before it.
7773 Classic examples are branch and call instructions, which often execute
7774 the following instruction before the branch or call is performed.
7776 On some machines, conditional branch instructions can optionally
7777 @dfn{annul} instructions in the delay slot. This means that the
7778 instruction will not be executed for certain branch outcomes. Both
7779 instructions that annul if the branch is true and instructions that
7780 annul if the branch is false are supported.
7782 Delay slot scheduling differs from instruction scheduling in that
7783 determining whether an instruction needs a delay slot is dependent only
7784 on the type of instruction being generated, not on data flow between the
7785 instructions. See the next section for a discussion of data-dependent
7786 instruction scheduling.
7788 @findex define_delay
7789 The requirement of an insn needing one or more delay slots is indicated
7790 via the @code{define_delay} expression. It has the following form:
7793 (define_delay @var{test}
7794 [@var{delay-1} @var{annul-true-1} @var{annul-false-1}
7795 @var{delay-2} @var{annul-true-2} @var{annul-false-2}
7799 @var{test} is an attribute test that indicates whether this
7800 @code{define_delay} applies to a particular insn. If so, the number of
7801 required delay slots is determined by the length of the vector specified
7802 as the second argument. An insn placed in delay slot @var{n} must
7803 satisfy attribute test @var{delay-n}. @var{annul-true-n} is an
7804 attribute test that specifies which insns may be annulled if the branch
7805 is true. Similarly, @var{annul-false-n} specifies which insns in the
7806 delay slot may be annulled if the branch is false. If annulling is not
7807 supported for that delay slot, @code{(nil)} should be coded.
7809 For example, in the common case where branch and call insns require
7810 a single delay slot, which may contain any insn other than a branch or
7811 call, the following would be placed in the @file{md} file:
7814 (define_delay (eq_attr "type" "branch,call")
7815 [(eq_attr "type" "!branch,call") (nil) (nil)])
7818 Multiple @code{define_delay} expressions may be specified. In this
7819 case, each such expression specifies different delay slot requirements
7820 and there must be no insn for which tests in two @code{define_delay}
7821 expressions are both true.
7823 For example, if we have a machine that requires one delay slot for branches
7824 but two for calls, no delay slot can contain a branch or call insn,
7825 and any valid insn in the delay slot for the branch can be annulled if the
7826 branch is true, we might represent this as follows:
7829 (define_delay (eq_attr "type" "branch")
7830 [(eq_attr "type" "!branch,call")
7831 (eq_attr "type" "!branch,call")
7834 (define_delay (eq_attr "type" "call")
7835 [(eq_attr "type" "!branch,call") (nil) (nil)
7836 (eq_attr "type" "!branch,call") (nil) (nil)])
7838 @c the above is *still* too long. --mew 4feb93
7842 @node Processor pipeline description
7843 @subsection Specifying processor pipeline description
7844 @cindex processor pipeline description
7845 @cindex processor functional units
7846 @cindex instruction latency time
7847 @cindex interlock delays
7848 @cindex data dependence delays
7849 @cindex reservation delays
7850 @cindex pipeline hazard recognizer
7851 @cindex automaton based pipeline description
7852 @cindex regular expressions
7853 @cindex deterministic finite state automaton
7854 @cindex automaton based scheduler
7858 To achieve better performance, most modern processors
7859 (super-pipelined, superscalar @acronym{RISC}, and @acronym{VLIW}
7860 processors) have many @dfn{functional units} on which several
7861 instructions can be executed simultaneously. An instruction starts
7862 execution if its issue conditions are satisfied. If not, the
7863 instruction is stalled until its conditions are satisfied. Such
7864 @dfn{interlock (pipeline) delay} causes interruption of the fetching
7865 of successor instructions (or demands nop instructions, e.g.@: for some
7868 There are two major kinds of interlock delays in modern processors.
7869 The first one is a data dependence delay determining @dfn{instruction
7870 latency time}. The instruction execution is not started until all
7871 source data have been evaluated by prior instructions (there are more
7872 complex cases when the instruction execution starts even when the data
7873 are not available but will be ready in given time after the
7874 instruction execution start). Taking the data dependence delays into
7875 account is simple. The data dependence (true, output, and
7876 anti-dependence) delay between two instructions is given by a
7877 constant. In most cases this approach is adequate. The second kind
7878 of interlock delays is a reservation delay. The reservation delay
7879 means that two instructions under execution will be in need of shared
7880 processors resources, i.e.@: buses, internal registers, and/or
7881 functional units, which are reserved for some time. Taking this kind
7882 of delay into account is complex especially for modern @acronym{RISC}
7885 The task of exploiting more processor parallelism is solved by an
7886 instruction scheduler. For a better solution to this problem, the
7887 instruction scheduler has to have an adequate description of the
7888 processor parallelism (or @dfn{pipeline description}). GCC
7889 machine descriptions describe processor parallelism and functional
7890 unit reservations for groups of instructions with the aid of
7891 @dfn{regular expressions}.
7893 The GCC instruction scheduler uses a @dfn{pipeline hazard recognizer} to
7894 figure out the possibility of the instruction issue by the processor
7895 on a given simulated processor cycle. The pipeline hazard recognizer is
7896 automatically generated from the processor pipeline description. The
7897 pipeline hazard recognizer generated from the machine description
7898 is based on a deterministic finite state automaton (@acronym{DFA}):
7899 the instruction issue is possible if there is a transition from one
7900 automaton state to another one. This algorithm is very fast, and
7901 furthermore, its speed is not dependent on processor
7902 complexity@footnote{However, the size of the automaton depends on
7903 processor complexity. To limit this effect, machine descriptions
7904 can split orthogonal parts of the machine description among several
7905 automata: but then, since each of these must be stepped independently,
7906 this does cause a small decrease in the algorithm's performance.}.
7908 @cindex automaton based pipeline description
7909 The rest of this section describes the directives that constitute
7910 an automaton-based processor pipeline description. The order of
7911 these constructions within the machine description file is not
7914 @findex define_automaton
7915 @cindex pipeline hazard recognizer
7916 The following optional construction describes names of automata
7917 generated and used for the pipeline hazards recognition. Sometimes
7918 the generated finite state automaton used by the pipeline hazard
7919 recognizer is large. If we use more than one automaton and bind functional
7920 units to the automata, the total size of the automata is usually
7921 less than the size of the single automaton. If there is no one such
7922 construction, only one finite state automaton is generated.
7925 (define_automaton @var{automata-names})
7928 @var{automata-names} is a string giving names of the automata. The
7929 names are separated by commas. All the automata should have unique names.
7930 The automaton name is used in the constructions @code{define_cpu_unit} and
7931 @code{define_query_cpu_unit}.
7933 @findex define_cpu_unit
7934 @cindex processor functional units
7935 Each processor functional unit used in the description of instruction
7936 reservations should be described by the following construction.
7939 (define_cpu_unit @var{unit-names} [@var{automaton-name}])
7942 @var{unit-names} is a string giving the names of the functional units
7943 separated by commas. Don't use name @samp{nothing}, it is reserved
7946 @var{automaton-name} is a string giving the name of the automaton with
7947 which the unit is bound. The automaton should be described in
7948 construction @code{define_automaton}. You should give
7949 @dfn{automaton-name}, if there is a defined automaton.
7951 The assignment of units to automata are constrained by the uses of the
7952 units in insn reservations. The most important constraint is: if a
7953 unit reservation is present on a particular cycle of an alternative
7954 for an insn reservation, then some unit from the same automaton must
7955 be present on the same cycle for the other alternatives of the insn
7956 reservation. The rest of the constraints are mentioned in the
7957 description of the subsequent constructions.
7959 @findex define_query_cpu_unit
7960 @cindex querying function unit reservations
7961 The following construction describes CPU functional units analogously
7962 to @code{define_cpu_unit}. The reservation of such units can be
7963 queried for an automaton state. The instruction scheduler never
7964 queries reservation of functional units for given automaton state. So
7965 as a rule, you don't need this construction. This construction could
7966 be used for future code generation goals (e.g.@: to generate
7967 @acronym{VLIW} insn templates).
7970 (define_query_cpu_unit @var{unit-names} [@var{automaton-name}])
7973 @var{unit-names} is a string giving names of the functional units
7974 separated by commas.
7976 @var{automaton-name} is a string giving the name of the automaton with
7977 which the unit is bound.
7979 @findex define_insn_reservation
7980 @cindex instruction latency time
7981 @cindex regular expressions
7983 The following construction is the major one to describe pipeline
7984 characteristics of an instruction.
7987 (define_insn_reservation @var{insn-name} @var{default_latency}
7988 @var{condition} @var{regexp})
7991 @var{default_latency} is a number giving latency time of the
7992 instruction. There is an important difference between the old
7993 description and the automaton based pipeline description. The latency
7994 time is used for all dependencies when we use the old description. In
7995 the automaton based pipeline description, the given latency time is only
7996 used for true dependencies. The cost of anti-dependencies is always
7997 zero and the cost of output dependencies is the difference between
7998 latency times of the producing and consuming insns (if the difference
7999 is negative, the cost is considered to be zero). You can always
8000 change the default costs for any description by using the target hook
8001 @code{TARGET_SCHED_ADJUST_COST} (@pxref{Scheduling}).
8003 @var{insn-name} is a string giving the internal name of the insn. The
8004 internal names are used in constructions @code{define_bypass} and in
8005 the automaton description file generated for debugging. The internal
8006 name has nothing in common with the names in @code{define_insn}. It is a
8007 good practice to use insn classes described in the processor manual.
8009 @var{condition} defines what RTL insns are described by this
8010 construction. You should remember that you will be in trouble if
8011 @var{condition} for two or more different
8012 @code{define_insn_reservation} constructions is TRUE for an insn. In
8013 this case what reservation will be used for the insn is not defined.
8014 Such cases are not checked during generation of the pipeline hazards
8015 recognizer because in general recognizing that two conditions may have
8016 the same value is quite difficult (especially if the conditions
8017 contain @code{symbol_ref}). It is also not checked during the
8018 pipeline hazard recognizer work because it would slow down the
8019 recognizer considerably.
8021 @var{regexp} is a string describing the reservation of the cpu's functional
8022 units by the instruction. The reservations are described by a regular
8023 expression according to the following syntax:
8026 regexp = regexp "," oneof
8029 oneof = oneof "|" allof
8032 allof = allof "+" repeat
8035 repeat = element "*" number
8038 element = cpu_function_unit_name
8047 @samp{,} is used for describing the start of the next cycle in
8051 @samp{|} is used for describing a reservation described by the first
8052 regular expression @strong{or} a reservation described by the second
8053 regular expression @strong{or} etc.
8056 @samp{+} is used for describing a reservation described by the first
8057 regular expression @strong{and} a reservation described by the
8058 second regular expression @strong{and} etc.
8061 @samp{*} is used for convenience and simply means a sequence in which
8062 the regular expression are repeated @var{number} times with cycle
8063 advancing (see @samp{,}).
8066 @samp{cpu_function_unit_name} denotes reservation of the named
8070 @samp{reservation_name} --- see description of construction
8071 @samp{define_reservation}.
8074 @samp{nothing} denotes no unit reservations.
8077 @findex define_reservation
8078 Sometimes unit reservations for different insns contain common parts.
8079 In such case, you can simplify the pipeline description by describing
8080 the common part by the following construction
8083 (define_reservation @var{reservation-name} @var{regexp})
8086 @var{reservation-name} is a string giving name of @var{regexp}.
8087 Functional unit names and reservation names are in the same name
8088 space. So the reservation names should be different from the
8089 functional unit names and can not be the reserved name @samp{nothing}.
8091 @findex define_bypass
8092 @cindex instruction latency time
8094 The following construction is used to describe exceptions in the
8095 latency time for given instruction pair. This is so called bypasses.
8098 (define_bypass @var{number} @var{out_insn_names} @var{in_insn_names}
8102 @var{number} defines when the result generated by the instructions
8103 given in string @var{out_insn_names} will be ready for the
8104 instructions given in string @var{in_insn_names}. Each of these
8105 strings is a comma-separated list of filename-style globs and
8106 they refer to the names of @code{define_insn_reservation}s.
8109 (define_bypass 1 "cpu1_load_*, cpu1_store_*" "cpu1_load_*")
8111 defines a bypass between instructions that start with
8112 @samp{cpu1_load_} or @samp{cpu1_store_} and those that start with
8115 @var{guard} is an optional string giving the name of a C function which
8116 defines an additional guard for the bypass. The function will get the
8117 two insns as parameters. If the function returns zero the bypass will
8118 be ignored for this case. The additional guard is necessary to
8119 recognize complicated bypasses, e.g.@: when the consumer is only an address
8120 of insn @samp{store} (not a stored value).
8122 If there are more one bypass with the same output and input insns, the
8123 chosen bypass is the first bypass with a guard in description whose
8124 guard function returns nonzero. If there is no such bypass, then
8125 bypass without the guard function is chosen.
8127 @findex exclusion_set
8128 @findex presence_set
8129 @findex final_presence_set
8131 @findex final_absence_set
8134 The following five constructions are usually used to describe
8135 @acronym{VLIW} processors, or more precisely, to describe a placement
8136 of small instructions into @acronym{VLIW} instruction slots. They
8137 can be used for @acronym{RISC} processors, too.
8140 (exclusion_set @var{unit-names} @var{unit-names})
8141 (presence_set @var{unit-names} @var{patterns})
8142 (final_presence_set @var{unit-names} @var{patterns})
8143 (absence_set @var{unit-names} @var{patterns})
8144 (final_absence_set @var{unit-names} @var{patterns})
8147 @var{unit-names} is a string giving names of functional units
8148 separated by commas.
8150 @var{patterns} is a string giving patterns of functional units
8151 separated by comma. Currently pattern is one unit or units
8152 separated by white-spaces.
8154 The first construction (@samp{exclusion_set}) means that each
8155 functional unit in the first string can not be reserved simultaneously
8156 with a unit whose name is in the second string and vice versa. For
8157 example, the construction is useful for describing processors
8158 (e.g.@: some SPARC processors) with a fully pipelined floating point
8159 functional unit which can execute simultaneously only single floating
8160 point insns or only double floating point insns.
8162 The second construction (@samp{presence_set}) means that each
8163 functional unit in the first string can not be reserved unless at
8164 least one of pattern of units whose names are in the second string is
8165 reserved. This is an asymmetric relation. For example, it is useful
8166 for description that @acronym{VLIW} @samp{slot1} is reserved after
8167 @samp{slot0} reservation. We could describe it by the following
8171 (presence_set "slot1" "slot0")
8174 Or @samp{slot1} is reserved only after @samp{slot0} and unit @samp{b0}
8175 reservation. In this case we could write
8178 (presence_set "slot1" "slot0 b0")
8181 The third construction (@samp{final_presence_set}) is analogous to
8182 @samp{presence_set}. The difference between them is when checking is
8183 done. When an instruction is issued in given automaton state
8184 reflecting all current and planned unit reservations, the automaton
8185 state is changed. The first state is a source state, the second one
8186 is a result state. Checking for @samp{presence_set} is done on the
8187 source state reservation, checking for @samp{final_presence_set} is
8188 done on the result reservation. This construction is useful to
8189 describe a reservation which is actually two subsequent reservations.
8190 For example, if we use
8193 (presence_set "slot1" "slot0")
8196 the following insn will be never issued (because @samp{slot1} requires
8197 @samp{slot0} which is absent in the source state).
8200 (define_reservation "insn_and_nop" "slot0 + slot1")
8203 but it can be issued if we use analogous @samp{final_presence_set}.
8205 The forth construction (@samp{absence_set}) means that each functional
8206 unit in the first string can be reserved only if each pattern of units
8207 whose names are in the second string is not reserved. This is an
8208 asymmetric relation (actually @samp{exclusion_set} is analogous to
8209 this one but it is symmetric). For example it might be useful in a
8210 @acronym{VLIW} description to say that @samp{slot0} cannot be reserved
8211 after either @samp{slot1} or @samp{slot2} have been reserved. This
8212 can be described as:
8215 (absence_set "slot0" "slot1, slot2")
8218 Or @samp{slot2} can not be reserved if @samp{slot0} and unit @samp{b0}
8219 are reserved or @samp{slot1} and unit @samp{b1} are reserved. In
8220 this case we could write
8223 (absence_set "slot2" "slot0 b0, slot1 b1")
8226 All functional units mentioned in a set should belong to the same
8229 The last construction (@samp{final_absence_set}) is analogous to
8230 @samp{absence_set} but checking is done on the result (state)
8231 reservation. See comments for @samp{final_presence_set}.
8233 @findex automata_option
8234 @cindex deterministic finite state automaton
8235 @cindex nondeterministic finite state automaton
8236 @cindex finite state automaton minimization
8237 You can control the generator of the pipeline hazard recognizer with
8238 the following construction.
8241 (automata_option @var{options})
8244 @var{options} is a string giving options which affect the generated
8245 code. Currently there are the following options:
8249 @dfn{no-minimization} makes no minimization of the automaton. This is
8250 only worth to do when we are debugging the description and need to
8251 look more accurately at reservations of states.
8254 @dfn{time} means printing time statistics about the generation of
8258 @dfn{stats} means printing statistics about the generated automata
8259 such as the number of DFA states, NDFA states and arcs.
8262 @dfn{v} means a generation of the file describing the result automata.
8263 The file has suffix @samp{.dfa} and can be used for the description
8264 verification and debugging.
8267 @dfn{w} means a generation of warning instead of error for
8268 non-critical errors.
8271 @dfn{no-comb-vect} prevents the automaton generator from generating
8272 two data structures and comparing them for space efficiency. Using
8273 a comb vector to represent transitions may be better, but it can be
8274 very expensive to construct. This option is useful if the build
8275 process spends an unacceptably long time in genautomata.
8278 @dfn{ndfa} makes nondeterministic finite state automata. This affects
8279 the treatment of operator @samp{|} in the regular expressions. The
8280 usual treatment of the operator is to try the first alternative and,
8281 if the reservation is not possible, the second alternative. The
8282 nondeterministic treatment means trying all alternatives, some of them
8283 may be rejected by reservations in the subsequent insns.
8286 @dfn{collapse-ndfa} modifies the behaviour of the generator when
8287 producing an automaton. An additional state transition to collapse a
8288 nondeterministic @acronym{NDFA} state to a deterministic @acronym{DFA}
8289 state is generated. It can be triggered by passing @code{const0_rtx} to
8290 state_transition. In such an automaton, cycle advance transitions are
8291 available only for these collapsed states. This option is useful for
8292 ports that want to use the @code{ndfa} option, but also want to use
8293 @code{define_query_cpu_unit} to assign units to insns issued in a cycle.
8296 @dfn{progress} means output of a progress bar showing how many states
8297 were generated so far for automaton being processed. This is useful
8298 during debugging a @acronym{DFA} description. If you see too many
8299 generated states, you could interrupt the generator of the pipeline
8300 hazard recognizer and try to figure out a reason for generation of the
8304 As an example, consider a superscalar @acronym{RISC} machine which can
8305 issue three insns (two integer insns and one floating point insn) on
8306 the cycle but can finish only two insns. To describe this, we define
8307 the following functional units.
8310 (define_cpu_unit "i0_pipeline, i1_pipeline, f_pipeline")
8311 (define_cpu_unit "port0, port1")
8314 All simple integer insns can be executed in any integer pipeline and
8315 their result is ready in two cycles. The simple integer insns are
8316 issued into the first pipeline unless it is reserved, otherwise they
8317 are issued into the second pipeline. Integer division and
8318 multiplication insns can be executed only in the second integer
8319 pipeline and their results are ready correspondingly in 8 and 4
8320 cycles. The integer division is not pipelined, i.e.@: the subsequent
8321 integer division insn can not be issued until the current division
8322 insn finished. Floating point insns are fully pipelined and their
8323 results are ready in 3 cycles. Where the result of a floating point
8324 insn is used by an integer insn, an additional delay of one cycle is
8325 incurred. To describe all of this we could specify
8328 (define_cpu_unit "div")
8330 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
8331 "(i0_pipeline | i1_pipeline), (port0 | port1)")
8333 (define_insn_reservation "mult" 4 (eq_attr "type" "mult")
8334 "i1_pipeline, nothing*2, (port0 | port1)")
8336 (define_insn_reservation "div" 8 (eq_attr "type" "div")
8337 "i1_pipeline, div*7, div + (port0 | port1)")
8339 (define_insn_reservation "float" 3 (eq_attr "type" "float")
8340 "f_pipeline, nothing, (port0 | port1))
8342 (define_bypass 4 "float" "simple,mult,div")
8345 To simplify the description we could describe the following reservation
8348 (define_reservation "finish" "port0|port1")
8351 and use it in all @code{define_insn_reservation} as in the following
8355 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
8356 "(i0_pipeline | i1_pipeline), finish")
8362 @node Conditional Execution
8363 @section Conditional Execution
8364 @cindex conditional execution
8367 A number of architectures provide for some form of conditional
8368 execution, or predication. The hallmark of this feature is the
8369 ability to nullify most of the instructions in the instruction set.
8370 When the instruction set is large and not entirely symmetric, it
8371 can be quite tedious to describe these forms directly in the
8372 @file{.md} file. An alternative is the @code{define_cond_exec} template.
8374 @findex define_cond_exec
8377 [@var{predicate-pattern}]
8379 "@var{output-template}")
8382 @var{predicate-pattern} is the condition that must be true for the
8383 insn to be executed at runtime and should match a relational operator.
8384 One can use @code{match_operator} to match several relational operators
8385 at once. Any @code{match_operand} operands must have no more than one
8388 @var{condition} is a C expression that must be true for the generated
8391 @findex current_insn_predicate
8392 @var{output-template} is a string similar to the @code{define_insn}
8393 output template (@pxref{Output Template}), except that the @samp{*}
8394 and @samp{@@} special cases do not apply. This is only useful if the
8395 assembly text for the predicate is a simple prefix to the main insn.
8396 In order to handle the general case, there is a global variable
8397 @code{current_insn_predicate} that will contain the entire predicate
8398 if the current insn is predicated, and will otherwise be @code{NULL}.
8400 When @code{define_cond_exec} is used, an implicit reference to
8401 the @code{predicable} instruction attribute is made.
8402 @xref{Insn Attributes}. This attribute must be a boolean (i.e.@: have
8403 exactly two elements in its @var{list-of-values}), with the possible
8404 values being @code{no} and @code{yes}. The default and all uses in
8405 the insns must be a simple constant, not a complex expressions. It
8406 may, however, depend on the alternative, by using a comma-separated
8407 list of values. If that is the case, the port should also define an
8408 @code{enabled} attribute (@pxref{Disable Insn Alternatives}), which
8409 should also allow only @code{no} and @code{yes} as its values.
8411 For each @code{define_insn} for which the @code{predicable}
8412 attribute is true, a new @code{define_insn} pattern will be
8413 generated that matches a predicated version of the instruction.
8417 (define_insn "addsi"
8418 [(set (match_operand:SI 0 "register_operand" "r")
8419 (plus:SI (match_operand:SI 1 "register_operand" "r")
8420 (match_operand:SI 2 "register_operand" "r")))]
8425 [(ne (match_operand:CC 0 "register_operand" "c")
8432 generates a new pattern
8437 (ne (match_operand:CC 3 "register_operand" "c") (const_int 0))
8438 (set (match_operand:SI 0 "register_operand" "r")
8439 (plus:SI (match_operand:SI 1 "register_operand" "r")
8440 (match_operand:SI 2 "register_operand" "r"))))]
8441 "(@var{test2}) && (@var{test1})"
8442 "(%3) add %2,%1,%0")
8447 @node Constant Definitions
8448 @section Constant Definitions
8449 @cindex constant definitions
8450 @findex define_constants
8452 Using literal constants inside instruction patterns reduces legibility and
8453 can be a maintenance problem.
8455 To overcome this problem, you may use the @code{define_constants}
8456 expression. It contains a vector of name-value pairs. From that
8457 point on, wherever any of the names appears in the MD file, it is as
8458 if the corresponding value had been written instead. You may use
8459 @code{define_constants} multiple times; each appearance adds more
8460 constants to the table. It is an error to redefine a constant with
8463 To come back to the a29k load multiple example, instead of
8467 [(match_parallel 0 "load_multiple_operation"
8468 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
8469 (match_operand:SI 2 "memory_operand" "m"))
8471 (clobber (reg:SI 179))])]
8487 [(match_parallel 0 "load_multiple_operation"
8488 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
8489 (match_operand:SI 2 "memory_operand" "m"))
8491 (clobber (reg:SI R_CR))])]
8496 The constants that are defined with a define_constant are also output
8497 in the insn-codes.h header file as #defines.
8499 @cindex enumerations
8500 @findex define_c_enum
8501 You can also use the machine description file to define enumerations.
8502 Like the constants defined by @code{define_constant}, these enumerations
8503 are visible to both the machine description file and the main C code.
8505 The syntax is as follows:
8508 (define_c_enum "@var{name}" [
8516 This definition causes the equivalent of the following C code to appear
8517 in @file{insn-constants.h}:
8524 @var{valuen} = @var{n}
8526 #define NUM_@var{cname}_VALUES (@var{n} + 1)
8529 where @var{cname} is the capitalized form of @var{name}.
8530 It also makes each @var{valuei} available in the machine description
8531 file, just as if it had been declared with:
8534 (define_constants [(@var{valuei} @var{i})])
8537 Each @var{valuei} is usually an upper-case identifier and usually
8538 begins with @var{cname}.
8540 You can split the enumeration definition into as many statements as
8541 you like. The above example is directly equivalent to:
8544 (define_c_enum "@var{name}" [@var{value0}])
8545 (define_c_enum "@var{name}" [@var{value1}])
8547 (define_c_enum "@var{name}" [@var{valuen}])
8550 Splitting the enumeration helps to improve the modularity of each
8551 individual @code{.md} file. For example, if a port defines its
8552 synchronization instructions in a separate @file{sync.md} file,
8553 it is convenient to define all synchronization-specific enumeration
8554 values in @file{sync.md} rather than in the main @file{.md} file.
8556 Some enumeration names have special significance to GCC:
8560 @findex unspec_volatile
8561 If an enumeration called @code{unspecv} is defined, GCC will use it
8562 when printing out @code{unspec_volatile} expressions. For example:
8565 (define_c_enum "unspecv" [
8570 causes GCC to print @samp{(unspec_volatile @dots{} 0)} as:
8573 (unspec_volatile ... UNSPECV_BLOCKAGE)
8578 If an enumeration called @code{unspec} is defined, GCC will use
8579 it when printing out @code{unspec} expressions. GCC will also use
8580 it when printing out @code{unspec_volatile} expressions unless an
8581 @code{unspecv} enumeration is also defined. You can therefore
8582 decide whether to keep separate enumerations for volatile and
8583 non-volatile expressions or whether to use the same enumeration
8588 @anchor{define_enum}
8589 Another way of defining an enumeration is to use @code{define_enum}:
8592 (define_enum "@var{name}" [
8600 This directive implies:
8603 (define_c_enum "@var{name}" [
8604 @var{cname}_@var{cvalue0}
8605 @var{cname}_@var{cvalue1}
8607 @var{cname}_@var{cvaluen}
8611 @findex define_enum_attr
8612 where @var{cvaluei} is the capitalized form of @var{valuei}.
8613 However, unlike @code{define_c_enum}, the enumerations defined
8614 by @code{define_enum} can be used in attribute specifications
8615 (@pxref{define_enum_attr}).
8620 @cindex iterators in @file{.md} files
8622 Ports often need to define similar patterns for more than one machine
8623 mode or for more than one rtx code. GCC provides some simple iterator
8624 facilities to make this process easier.
8627 * Mode Iterators:: Generating variations of patterns for different modes.
8628 * Code Iterators:: Doing the same for codes.
8631 @node Mode Iterators
8632 @subsection Mode Iterators
8633 @cindex mode iterators in @file{.md} files
8635 Ports often need to define similar patterns for two or more different modes.
8640 If a processor has hardware support for both single and double
8641 floating-point arithmetic, the @code{SFmode} patterns tend to be
8642 very similar to the @code{DFmode} ones.
8645 If a port uses @code{SImode} pointers in one configuration and
8646 @code{DImode} pointers in another, it will usually have very similar
8647 @code{SImode} and @code{DImode} patterns for manipulating pointers.
8650 Mode iterators allow several patterns to be instantiated from one
8651 @file{.md} file template. They can be used with any type of
8652 rtx-based construct, such as a @code{define_insn},
8653 @code{define_split}, or @code{define_peephole2}.
8656 * Defining Mode Iterators:: Defining a new mode iterator.
8657 * Substitutions:: Combining mode iterators with substitutions
8658 * Examples:: Examples
8661 @node Defining Mode Iterators
8662 @subsubsection Defining Mode Iterators
8663 @findex define_mode_iterator
8665 The syntax for defining a mode iterator is:
8668 (define_mode_iterator @var{name} [(@var{mode1} "@var{cond1}") @dots{} (@var{moden} "@var{condn}")])
8671 This allows subsequent @file{.md} file constructs to use the mode suffix
8672 @code{:@var{name}}. Every construct that does so will be expanded
8673 @var{n} times, once with every use of @code{:@var{name}} replaced by
8674 @code{:@var{mode1}}, once with every use replaced by @code{:@var{mode2}},
8675 and so on. In the expansion for a particular @var{modei}, every
8676 C condition will also require that @var{condi} be true.
8681 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
8684 defines a new mode suffix @code{:P}. Every construct that uses
8685 @code{:P} will be expanded twice, once with every @code{:P} replaced
8686 by @code{:SI} and once with every @code{:P} replaced by @code{:DI}.
8687 The @code{:SI} version will only apply if @code{Pmode == SImode} and
8688 the @code{:DI} version will only apply if @code{Pmode == DImode}.
8690 As with other @file{.md} conditions, an empty string is treated
8691 as ``always true''. @code{(@var{mode} "")} can also be abbreviated
8692 to @code{@var{mode}}. For example:
8695 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
8698 means that the @code{:DI} expansion only applies if @code{TARGET_64BIT}
8699 but that the @code{:SI} expansion has no such constraint.
8701 Iterators are applied in the order they are defined. This can be
8702 significant if two iterators are used in a construct that requires
8703 substitutions. @xref{Substitutions}.
8706 @subsubsection Substitution in Mode Iterators
8707 @findex define_mode_attr
8709 If an @file{.md} file construct uses mode iterators, each version of the
8710 construct will often need slightly different strings or modes. For
8715 When a @code{define_expand} defines several @code{add@var{m}3} patterns
8716 (@pxref{Standard Names}), each expander will need to use the
8717 appropriate mode name for @var{m}.
8720 When a @code{define_insn} defines several instruction patterns,
8721 each instruction will often use a different assembler mnemonic.
8724 When a @code{define_insn} requires operands with different modes,
8725 using an iterator for one of the operand modes usually requires a specific
8726 mode for the other operand(s).
8729 GCC supports such variations through a system of ``mode attributes''.
8730 There are two standard attributes: @code{mode}, which is the name of
8731 the mode in lower case, and @code{MODE}, which is the same thing in
8732 upper case. You can define other attributes using:
8735 (define_mode_attr @var{name} [(@var{mode1} "@var{value1}") @dots{} (@var{moden} "@var{valuen}")])
8738 where @var{name} is the name of the attribute and @var{valuei}
8739 is the value associated with @var{modei}.
8741 When GCC replaces some @var{:iterator} with @var{:mode}, it will scan
8742 each string and mode in the pattern for sequences of the form
8743 @code{<@var{iterator}:@var{attr}>}, where @var{attr} is the name of a
8744 mode attribute. If the attribute is defined for @var{mode}, the whole
8745 @code{<@dots{}>} sequence will be replaced by the appropriate attribute
8748 For example, suppose an @file{.md} file has:
8751 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
8752 (define_mode_attr load [(SI "lw") (DI "ld")])
8755 If one of the patterns that uses @code{:P} contains the string
8756 @code{"<P:load>\t%0,%1"}, the @code{SI} version of that pattern
8757 will use @code{"lw\t%0,%1"} and the @code{DI} version will use
8760 Here is an example of using an attribute for a mode:
8763 (define_mode_iterator LONG [SI DI])
8764 (define_mode_attr SHORT [(SI "HI") (DI "SI")])
8765 (define_insn @dots{}
8766 (sign_extend:LONG (match_operand:<LONG:SHORT> @dots{})) @dots{})
8769 The @code{@var{iterator}:} prefix may be omitted, in which case the
8770 substitution will be attempted for every iterator expansion.
8773 @subsubsection Mode Iterator Examples
8775 Here is an example from the MIPS port. It defines the following
8776 modes and attributes (among others):
8779 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
8780 (define_mode_attr d [(SI "") (DI "d")])
8783 and uses the following template to define both @code{subsi3}
8787 (define_insn "sub<mode>3"
8788 [(set (match_operand:GPR 0 "register_operand" "=d")
8789 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
8790 (match_operand:GPR 2 "register_operand" "d")))]
8793 [(set_attr "type" "arith")
8794 (set_attr "mode" "<MODE>")])
8797 This is exactly equivalent to:
8800 (define_insn "subsi3"
8801 [(set (match_operand:SI 0 "register_operand" "=d")
8802 (minus:SI (match_operand:SI 1 "register_operand" "d")
8803 (match_operand:SI 2 "register_operand" "d")))]
8806 [(set_attr "type" "arith")
8807 (set_attr "mode" "SI")])
8809 (define_insn "subdi3"
8810 [(set (match_operand:DI 0 "register_operand" "=d")
8811 (minus:DI (match_operand:DI 1 "register_operand" "d")
8812 (match_operand:DI 2 "register_operand" "d")))]
8815 [(set_attr "type" "arith")
8816 (set_attr "mode" "DI")])
8819 @node Code Iterators
8820 @subsection Code Iterators
8821 @cindex code iterators in @file{.md} files
8822 @findex define_code_iterator
8823 @findex define_code_attr
8825 Code iterators operate in a similar way to mode iterators. @xref{Mode Iterators}.
8830 (define_code_iterator @var{name} [(@var{code1} "@var{cond1}") @dots{} (@var{coden} "@var{condn}")])
8833 defines a pseudo rtx code @var{name} that can be instantiated as
8834 @var{codei} if condition @var{condi} is true. Each @var{codei}
8835 must have the same rtx format. @xref{RTL Classes}.
8837 As with mode iterators, each pattern that uses @var{name} will be
8838 expanded @var{n} times, once with all uses of @var{name} replaced by
8839 @var{code1}, once with all uses replaced by @var{code2}, and so on.
8840 @xref{Defining Mode Iterators}.
8842 It is possible to define attributes for codes as well as for modes.
8843 There are two standard code attributes: @code{code}, the name of the
8844 code in lower case, and @code{CODE}, the name of the code in upper case.
8845 Other attributes are defined using:
8848 (define_code_attr @var{name} [(@var{code1} "@var{value1}") @dots{} (@var{coden} "@var{valuen}")])
8851 Here's an example of code iterators in action, taken from the MIPS port:
8854 (define_code_iterator any_cond [unordered ordered unlt unge uneq ltgt unle ungt
8855 eq ne gt ge lt le gtu geu ltu leu])
8857 (define_expand "b<code>"
8859 (if_then_else (any_cond:CC (cc0)
8861 (label_ref (match_operand 0 ""))
8865 gen_conditional_branch (operands, <CODE>);
8870 This is equivalent to:
8873 (define_expand "bunordered"
8875 (if_then_else (unordered:CC (cc0)
8877 (label_ref (match_operand 0 ""))
8881 gen_conditional_branch (operands, UNORDERED);
8885 (define_expand "bordered"
8887 (if_then_else (ordered:CC (cc0)
8889 (label_ref (match_operand 0 ""))
8893 gen_conditional_branch (operands, ORDERED);