1 @c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1996, 1998, 1999, 2000, 2001,
2 @c 2002, 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
3 @c This is part of the GCC manual.
4 @c For copying conditions, see the file gcc.texi.
8 @chapter Machine Descriptions
9 @cindex machine descriptions
11 A machine description has two parts: a file of instruction patterns
12 (@file{.md} file) and a C header file of macro definitions.
14 The @file{.md} file for a target machine contains a pattern for each
15 instruction that the target machine supports (or at least each instruction
16 that is worth telling the compiler about). It may also contain comments.
17 A semicolon causes the rest of the line to be a comment, unless the semicolon
18 is inside a quoted string.
20 See the next chapter for information on the C header file.
23 * Overview:: How the machine description is used.
24 * Patterns:: How to write instruction patterns.
25 * Example:: An explained example of a @code{define_insn} pattern.
26 * RTL Template:: The RTL template defines what insns match a pattern.
27 * Output Template:: The output template says how to make assembler code
29 * Output Statement:: For more generality, write C code to output
31 * Predicates:: Controlling what kinds of operands can be used
33 * Constraints:: Fine-tuning operand selection.
34 * Standard Names:: Names mark patterns to use for code generation.
35 * Pattern Ordering:: When the order of patterns makes a difference.
36 * Dependent Patterns:: Having one pattern may make you need another.
37 * Jump Patterns:: Special considerations for patterns for jump insns.
38 * Looping Patterns:: How to define patterns for special looping insns.
39 * Insn Canonicalizations::Canonicalization of Instructions
40 * Expander Definitions::Generating a sequence of several RTL insns
41 for a standard operation.
42 * Insn Splitting:: Splitting Instructions into Multiple Instructions.
43 * Including Patterns:: Including Patterns in Machine Descriptions.
44 * Peephole Definitions::Defining machine-specific peephole optimizations.
45 * Insn Attributes:: Specifying the value of attributes for generated insns.
46 * Conditional Execution::Generating @code{define_insn} patterns for
48 * Constant Definitions::Defining symbolic constants that can be used in the
50 * Iterators:: Using iterators to generate patterns from a template.
54 @section Overview of How the Machine Description is Used
56 There are three main conversions that happen in the compiler:
61 The front end reads the source code and builds a parse tree.
64 The parse tree is used to generate an RTL insn list based on named
68 The insn list is matched against the RTL templates to produce assembler
73 For the generate pass, only the names of the insns matter, from either a
74 named @code{define_insn} or a @code{define_expand}. The compiler will
75 choose the pattern with the right name and apply the operands according
76 to the documentation later in this chapter, without regard for the RTL
77 template or operand constraints. Note that the names the compiler looks
78 for are hard-coded in the compiler---it will ignore unnamed patterns and
79 patterns with names it doesn't know about, but if you don't provide a
80 named pattern it needs, it will abort.
82 If a @code{define_insn} is used, the template given is inserted into the
83 insn list. If a @code{define_expand} is used, one of three things
84 happens, based on the condition logic. The condition logic may manually
85 create new insns for the insn list, say via @code{emit_insn()}, and
86 invoke @code{DONE}. For certain named patterns, it may invoke @code{FAIL} to tell the
87 compiler to use an alternate way of performing that task. If it invokes
88 neither @code{DONE} nor @code{FAIL}, the template given in the pattern
89 is inserted, as if the @code{define_expand} were a @code{define_insn}.
91 Once the insn list is generated, various optimization passes convert,
92 replace, and rearrange the insns in the insn list. This is where the
93 @code{define_split} and @code{define_peephole} patterns get used, for
96 Finally, the insn list's RTL is matched up with the RTL templates in the
97 @code{define_insn} patterns, and those patterns are used to emit the
98 final assembly code. For this purpose, each named @code{define_insn}
99 acts like it's unnamed, since the names are ignored.
102 @section Everything about Instruction Patterns
104 @cindex instruction patterns
107 Each instruction pattern contains an incomplete RTL expression, with pieces
108 to be filled in later, operand constraints that restrict how the pieces can
109 be filled in, and an output pattern or C code to generate the assembler
110 output, all wrapped up in a @code{define_insn} expression.
112 A @code{define_insn} is an RTL expression containing four or five operands:
116 An optional name. The presence of a name indicate that this instruction
117 pattern can perform a certain standard job for the RTL-generation
118 pass of the compiler. This pass knows certain names and will use
119 the instruction patterns with those names, if the names are defined
120 in the machine description.
122 The absence of a name is indicated by writing an empty string
123 where the name should go. Nameless instruction patterns are never
124 used for generating RTL code, but they may permit several simpler insns
125 to be combined later on.
127 Names that are not thus known and used in RTL-generation have no
128 effect; they are equivalent to no name at all.
130 For the purpose of debugging the compiler, you may also specify a
131 name beginning with the @samp{*} character. Such a name is used only
132 for identifying the instruction in RTL dumps; it is entirely equivalent
133 to having a nameless pattern for all other purposes.
136 The @dfn{RTL template} (@pxref{RTL Template}) is a vector of incomplete
137 RTL expressions which show what the instruction should look like. It is
138 incomplete because it may contain @code{match_operand},
139 @code{match_operator}, and @code{match_dup} expressions that stand for
140 operands of the instruction.
142 If the vector has only one element, that element is the template for the
143 instruction pattern. If the vector has multiple elements, then the
144 instruction pattern is a @code{parallel} expression containing the
148 @cindex pattern conditions
149 @cindex conditions, in patterns
150 A condition. This is a string which contains a C expression that is
151 the final test to decide whether an insn body matches this pattern.
153 @cindex named patterns and conditions
154 For a named pattern, the condition (if present) may not depend on
155 the data in the insn being matched, but only the target-machine-type
156 flags. The compiler needs to test these conditions during
157 initialization in order to learn exactly which named instructions are
158 available in a particular run.
161 For nameless patterns, the condition is applied only when matching an
162 individual insn, and only after the insn has matched the pattern's
163 recognition template. The insn's operands may be found in the vector
164 @code{operands}. For an insn where the condition has once matched, it
165 can't be used to control register allocation, for example by excluding
166 certain hard registers or hard register combinations.
169 The @dfn{output template}: a string that says how to output matching
170 insns as assembler code. @samp{%} in this string specifies where
171 to substitute the value of an operand. @xref{Output Template}.
173 When simple substitution isn't general enough, you can specify a piece
174 of C code to compute the output. @xref{Output Statement}.
177 Optionally, a vector containing the values of attributes for insns matching
178 this pattern. @xref{Insn Attributes}.
182 @section Example of @code{define_insn}
183 @cindex @code{define_insn} example
185 Here is an actual example of an instruction pattern, for the 68000/68020.
190 (match_operand:SI 0 "general_operand" "rm"))]
194 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
196 return \"cmpl #0,%0\";
201 This can also be written using braced strings:
206 (match_operand:SI 0 "general_operand" "rm"))]
209 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
215 This is an instruction that sets the condition codes based on the value of
216 a general operand. It has no condition, so any insn whose RTL description
217 has the form shown may be handled according to this pattern. The name
218 @samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL generation
219 pass that, when it is necessary to test such a value, an insn to do so
220 can be constructed using this pattern.
222 The output control string is a piece of C code which chooses which
223 output template to return based on the kind of operand and the specific
224 type of CPU for which code is being generated.
226 @samp{"rm"} is an operand constraint. Its meaning is explained below.
229 @section RTL Template
230 @cindex RTL insn template
231 @cindex generating insns
232 @cindex insns, generating
233 @cindex recognizing insns
234 @cindex insns, recognizing
236 The RTL template is used to define which insns match the particular pattern
237 and how to find their operands. For named patterns, the RTL template also
238 says how to construct an insn from specified operands.
240 Construction involves substituting specified operands into a copy of the
241 template. Matching involves determining the values that serve as the
242 operands in the insn being matched. Both of these activities are
243 controlled by special expression types that direct matching and
244 substitution of the operands.
247 @findex match_operand
248 @item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint})
249 This expression is a placeholder for operand number @var{n} of
250 the insn. When constructing an insn, operand number @var{n}
251 will be substituted at this point. When matching an insn, whatever
252 appears at this position in the insn will be taken as operand
253 number @var{n}; but it must satisfy @var{predicate} or this instruction
254 pattern will not match at all.
256 Operand numbers must be chosen consecutively counting from zero in
257 each instruction pattern. There may be only one @code{match_operand}
258 expression in the pattern for each operand number. Usually operands
259 are numbered in the order of appearance in @code{match_operand}
260 expressions. In the case of a @code{define_expand}, any operand numbers
261 used only in @code{match_dup} expressions have higher values than all
262 other operand numbers.
264 @var{predicate} is a string that is the name of a function that
265 accepts two arguments, an expression and a machine mode.
266 @xref{Predicates}. During matching, the function will be called with
267 the putative operand as the expression and @var{m} as the mode
268 argument (if @var{m} is not specified, @code{VOIDmode} will be used,
269 which normally causes @var{predicate} to accept any mode). If it
270 returns zero, this instruction pattern fails to match.
271 @var{predicate} may be an empty string; then it means no test is to be
272 done on the operand, so anything which occurs in this position is
275 Most of the time, @var{predicate} will reject modes other than @var{m}---but
276 not always. For example, the predicate @code{address_operand} uses
277 @var{m} as the mode of memory ref that the address should be valid for.
278 Many predicates accept @code{const_int} nodes even though their mode is
281 @var{constraint} controls reloading and the choice of the best register
282 class to use for a value, as explained later (@pxref{Constraints}).
283 If the constraint would be an empty string, it can be omitted.
285 People are often unclear on the difference between the constraint and the
286 predicate. The predicate helps decide whether a given insn matches the
287 pattern. The constraint plays no role in this decision; instead, it
288 controls various decisions in the case of an insn which does match.
290 @findex match_scratch
291 @item (match_scratch:@var{m} @var{n} @var{constraint})
292 This expression is also a placeholder for operand number @var{n}
293 and indicates that operand must be a @code{scratch} or @code{reg}
296 When matching patterns, this is equivalent to
299 (match_operand:@var{m} @var{n} "scratch_operand" @var{pred})
302 but, when generating RTL, it produces a (@code{scratch}:@var{m})
305 If the last few expressions in a @code{parallel} are @code{clobber}
306 expressions whose operands are either a hard register or
307 @code{match_scratch}, the combiner can add or delete them when
308 necessary. @xref{Side Effects}.
311 @item (match_dup @var{n})
312 This expression is also a placeholder for operand number @var{n}.
313 It is used when the operand needs to appear more than once in the
316 In construction, @code{match_dup} acts just like @code{match_operand}:
317 the operand is substituted into the insn being constructed. But in
318 matching, @code{match_dup} behaves differently. It assumes that operand
319 number @var{n} has already been determined by a @code{match_operand}
320 appearing earlier in the recognition template, and it matches only an
321 identical-looking expression.
323 Note that @code{match_dup} should not be used to tell the compiler that
324 a particular register is being used for two operands (example:
325 @code{add} that adds one register to another; the second register is
326 both an input operand and the output operand). Use a matching
327 constraint (@pxref{Simple Constraints}) for those. @code{match_dup} is for the cases where one
328 operand is used in two places in the template, such as an instruction
329 that computes both a quotient and a remainder, where the opcode takes
330 two input operands but the RTL template has to refer to each of those
331 twice; once for the quotient pattern and once for the remainder pattern.
333 @findex match_operator
334 @item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}])
335 This pattern is a kind of placeholder for a variable RTL expression
338 When constructing an insn, it stands for an RTL expression whose
339 expression code is taken from that of operand @var{n}, and whose
340 operands are constructed from the patterns @var{operands}.
342 When matching an expression, it matches an expression if the function
343 @var{predicate} returns nonzero on that expression @emph{and} the
344 patterns @var{operands} match the operands of the expression.
346 Suppose that the function @code{commutative_operator} is defined as
347 follows, to match any expression whose operator is one of the
348 commutative arithmetic operators of RTL and whose mode is @var{mode}:
352 commutative_integer_operator (x, mode)
354 enum machine_mode mode;
356 enum rtx_code code = GET_CODE (x);
357 if (GET_MODE (x) != mode)
359 return (GET_RTX_CLASS (code) == RTX_COMM_ARITH
360 || code == EQ || code == NE);
364 Then the following pattern will match any RTL expression consisting
365 of a commutative operator applied to two general operands:
368 (match_operator:SI 3 "commutative_operator"
369 [(match_operand:SI 1 "general_operand" "g")
370 (match_operand:SI 2 "general_operand" "g")])
373 Here the vector @code{[@var{operands}@dots{}]} contains two patterns
374 because the expressions to be matched all contain two operands.
376 When this pattern does match, the two operands of the commutative
377 operator are recorded as operands 1 and 2 of the insn. (This is done
378 by the two instances of @code{match_operand}.) Operand 3 of the insn
379 will be the entire commutative expression: use @code{GET_CODE
380 (operands[3])} to see which commutative operator was used.
382 The machine mode @var{m} of @code{match_operator} works like that of
383 @code{match_operand}: it is passed as the second argument to the
384 predicate function, and that function is solely responsible for
385 deciding whether the expression to be matched ``has'' that mode.
387 When constructing an insn, argument 3 of the gen-function will specify
388 the operation (i.e.@: the expression code) for the expression to be
389 made. It should be an RTL expression, whose expression code is copied
390 into a new expression whose operands are arguments 1 and 2 of the
391 gen-function. The subexpressions of argument 3 are not used;
392 only its expression code matters.
394 When @code{match_operator} is used in a pattern for matching an insn,
395 it usually best if the operand number of the @code{match_operator}
396 is higher than that of the actual operands of the insn. This improves
397 register allocation because the register allocator often looks at
398 operands 1 and 2 of insns to see if it can do register tying.
400 There is no way to specify constraints in @code{match_operator}. The
401 operand of the insn which corresponds to the @code{match_operator}
402 never has any constraints because it is never reloaded as a whole.
403 However, if parts of its @var{operands} are matched by
404 @code{match_operand} patterns, those parts may have constraints of
408 @item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}])
409 Like @code{match_dup}, except that it applies to operators instead of
410 operands. When constructing an insn, operand number @var{n} will be
411 substituted at this point. But in matching, @code{match_op_dup} behaves
412 differently. It assumes that operand number @var{n} has already been
413 determined by a @code{match_operator} appearing earlier in the
414 recognition template, and it matches only an identical-looking
417 @findex match_parallel
418 @item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}])
419 This pattern is a placeholder for an insn that consists of a
420 @code{parallel} expression with a variable number of elements. This
421 expression should only appear at the top level of an insn pattern.
423 When constructing an insn, operand number @var{n} will be substituted at
424 this point. When matching an insn, it matches if the body of the insn
425 is a @code{parallel} expression with at least as many elements as the
426 vector of @var{subpat} expressions in the @code{match_parallel}, if each
427 @var{subpat} matches the corresponding element of the @code{parallel},
428 @emph{and} the function @var{predicate} returns nonzero on the
429 @code{parallel} that is the body of the insn. It is the responsibility
430 of the predicate to validate elements of the @code{parallel} beyond
431 those listed in the @code{match_parallel}.
433 A typical use of @code{match_parallel} is to match load and store
434 multiple expressions, which can contain a variable number of elements
435 in a @code{parallel}. For example,
439 [(match_parallel 0 "load_multiple_operation"
440 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
441 (match_operand:SI 2 "memory_operand" "m"))
443 (clobber (reg:SI 179))])]
448 This example comes from @file{a29k.md}. The function
449 @code{load_multiple_operation} is defined in @file{a29k.c} and checks
450 that subsequent elements in the @code{parallel} are the same as the
451 @code{set} in the pattern, except that they are referencing subsequent
452 registers and memory locations.
454 An insn that matches this pattern might look like:
458 [(set (reg:SI 20) (mem:SI (reg:SI 100)))
460 (clobber (reg:SI 179))
462 (mem:SI (plus:SI (reg:SI 100)
465 (mem:SI (plus:SI (reg:SI 100)
469 @findex match_par_dup
470 @item (match_par_dup @var{n} [@var{subpat}@dots{}])
471 Like @code{match_op_dup}, but for @code{match_parallel} instead of
472 @code{match_operator}.
476 @node Output Template
477 @section Output Templates and Operand Substitution
478 @cindex output templates
479 @cindex operand substitution
481 @cindex @samp{%} in template
483 The @dfn{output template} is a string which specifies how to output the
484 assembler code for an instruction pattern. Most of the template is a
485 fixed string which is output literally. The character @samp{%} is used
486 to specify where to substitute an operand; it can also be used to
487 identify places where different variants of the assembler require
490 In the simplest case, a @samp{%} followed by a digit @var{n} says to output
491 operand @var{n} at that point in the string.
493 @samp{%} followed by a letter and a digit says to output an operand in an
494 alternate fashion. Four letters have standard, built-in meanings described
495 below. The machine description macro @code{PRINT_OPERAND} can define
496 additional letters with nonstandard meanings.
498 @samp{%c@var{digit}} can be used to substitute an operand that is a
499 constant value without the syntax that normally indicates an immediate
502 @samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of
503 the constant is negated before printing.
505 @samp{%a@var{digit}} can be used to substitute an operand as if it were a
506 memory reference, with the actual operand treated as the address. This may
507 be useful when outputting a ``load address'' instruction, because often the
508 assembler syntax for such an instruction requires you to write the operand
509 as if it were a memory reference.
511 @samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump
514 @samp{%=} outputs a number which is unique to each instruction in the
515 entire compilation. This is useful for making local labels to be
516 referred to more than once in a single template that generates multiple
517 assembler instructions.
519 @samp{%} followed by a punctuation character specifies a substitution that
520 does not use an operand. Only one case is standard: @samp{%%} outputs a
521 @samp{%} into the assembler code. Other nonstandard cases can be
522 defined in the @code{PRINT_OPERAND} macro. You must also define
523 which punctuation characters are valid with the
524 @code{PRINT_OPERAND_PUNCT_VALID_P} macro.
528 The template may generate multiple assembler instructions. Write the text
529 for the instructions, with @samp{\;} between them.
531 @cindex matching operands
532 When the RTL contains two operands which are required by constraint to match
533 each other, the output template must refer only to the lower-numbered operand.
534 Matching operands are not always identical, and the rest of the compiler
535 arranges to put the proper RTL expression for printing into the lower-numbered
538 One use of nonstandard letters or punctuation following @samp{%} is to
539 distinguish between different assembler languages for the same machine; for
540 example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax
541 requires periods in most opcode names, while MIT syntax does not. For
542 example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola
543 syntax. The same file of patterns is used for both kinds of output syntax,
544 but the character sequence @samp{%.} is used in each place where Motorola
545 syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax
546 defines the sequence to output a period; the macro for MIT syntax defines
549 @cindex @code{#} in template
550 As a special case, a template consisting of the single character @code{#}
551 instructs the compiler to first split the insn, and then output the
552 resulting instructions separately. This helps eliminate redundancy in the
553 output templates. If you have a @code{define_insn} that needs to emit
554 multiple assembler instructions, and there is an matching @code{define_split}
555 already defined, then you can simply use @code{#} as the output template
556 instead of writing an output template that emits the multiple assembler
559 If the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct
560 of the form @samp{@{option0|option1|option2@}} in the templates. These
561 describe multiple variants of assembler language syntax.
562 @xref{Instruction Output}.
564 @node Output Statement
565 @section C Statements for Assembler Output
566 @cindex output statements
567 @cindex C statements for assembler output
568 @cindex generating assembler output
570 Often a single fixed template string cannot produce correct and efficient
571 assembler code for all the cases that are recognized by a single
572 instruction pattern. For example, the opcodes may depend on the kinds of
573 operands; or some unfortunate combinations of operands may require extra
574 machine instructions.
576 If the output control string starts with a @samp{@@}, then it is actually
577 a series of templates, each on a separate line. (Blank lines and
578 leading spaces and tabs are ignored.) The templates correspond to the
579 pattern's constraint alternatives (@pxref{Multi-Alternative}). For example,
580 if a target machine has a two-address add instruction @samp{addr} to add
581 into a register and another @samp{addm} to add a register to memory, you
582 might write this pattern:
585 (define_insn "addsi3"
586 [(set (match_operand:SI 0 "general_operand" "=r,m")
587 (plus:SI (match_operand:SI 1 "general_operand" "0,0")
588 (match_operand:SI 2 "general_operand" "g,r")))]
595 @cindex @code{*} in template
596 @cindex asterisk in template
597 If the output control string starts with a @samp{*}, then it is not an
598 output template but rather a piece of C program that should compute a
599 template. It should execute a @code{return} statement to return the
600 template-string you want. Most such templates use C string literals, which
601 require doublequote characters to delimit them. To include these
602 doublequote characters in the string, prefix each one with @samp{\}.
604 If the output control string is written as a brace block instead of a
605 double-quoted string, it is automatically assumed to be C code. In that
606 case, it is not necessary to put in a leading asterisk, or to escape the
607 doublequotes surrounding C string literals.
609 The operands may be found in the array @code{operands}, whose C data type
612 It is very common to select different ways of generating assembler code
613 based on whether an immediate operand is within a certain range. Be
614 careful when doing this, because the result of @code{INTVAL} is an
615 integer on the host machine. If the host machine has more bits in an
616 @code{int} than the target machine has in the mode in which the constant
617 will be used, then some of the bits you get from @code{INTVAL} will be
618 superfluous. For proper results, you must carefully disregard the
619 values of those bits.
621 @findex output_asm_insn
622 It is possible to output an assembler instruction and then go on to output
623 or compute more of them, using the subroutine @code{output_asm_insn}. This
624 receives two arguments: a template-string and a vector of operands. The
625 vector may be @code{operands}, or it may be another array of @code{rtx}
626 that you declare locally and initialize yourself.
628 @findex which_alternative
629 When an insn pattern has multiple alternatives in its constraints, often
630 the appearance of the assembler code is determined mostly by which alternative
631 was matched. When this is so, the C code can test the variable
632 @code{which_alternative}, which is the ordinal number of the alternative
633 that was actually satisfied (0 for the first, 1 for the second alternative,
636 For example, suppose there are two opcodes for storing zero, @samp{clrreg}
637 for registers and @samp{clrmem} for memory locations. Here is how
638 a pattern could use @code{which_alternative} to choose between them:
642 [(set (match_operand:SI 0 "general_operand" "=r,m")
646 return (which_alternative == 0
647 ? "clrreg %0" : "clrmem %0");
651 The example above, where the assembler code to generate was
652 @emph{solely} determined by the alternative, could also have been specified
653 as follows, having the output control string start with a @samp{@@}:
658 [(set (match_operand:SI 0 "general_operand" "=r,m")
670 @cindex operand predicates
671 @cindex operator predicates
673 A predicate determines whether a @code{match_operand} or
674 @code{match_operator} expression matches, and therefore whether the
675 surrounding instruction pattern will be used for that combination of
676 operands. GCC has a number of machine-independent predicates, and you
677 can define machine-specific predicates as needed. By convention,
678 predicates used with @code{match_operand} have names that end in
679 @samp{_operand}, and those used with @code{match_operator} have names
680 that end in @samp{_operator}.
682 All predicates are Boolean functions (in the mathematical sense) of
683 two arguments: the RTL expression that is being considered at that
684 position in the instruction pattern, and the machine mode that the
685 @code{match_operand} or @code{match_operator} specifies. In this
686 section, the first argument is called @var{op} and the second argument
687 @var{mode}. Predicates can be called from C as ordinary two-argument
688 functions; this can be useful in output templates or other
689 machine-specific code.
691 Operand predicates can allow operands that are not actually acceptable
692 to the hardware, as long as the constraints give reload the ability to
693 fix them up (@pxref{Constraints}). However, GCC will usually generate
694 better code if the predicates specify the requirements of the machine
695 instructions as closely as possible. Reload cannot fix up operands
696 that must be constants (``immediate operands''); you must use a
697 predicate that allows only constants, or else enforce the requirement
698 in the extra condition.
700 @cindex predicates and machine modes
701 @cindex normal predicates
702 @cindex special predicates
703 Most predicates handle their @var{mode} argument in a uniform manner.
704 If @var{mode} is @code{VOIDmode} (unspecified), then @var{op} can have
705 any mode. If @var{mode} is anything else, then @var{op} must have the
706 same mode, unless @var{op} is a @code{CONST_INT} or integer
707 @code{CONST_DOUBLE}. These RTL expressions always have
708 @code{VOIDmode}, so it would be counterproductive to check that their
709 mode matches. Instead, predicates that accept @code{CONST_INT} and/or
710 integer @code{CONST_DOUBLE} check that the value stored in the
711 constant will fit in the requested mode.
713 Predicates with this behavior are called @dfn{normal}.
714 @command{genrecog} can optimize the instruction recognizer based on
715 knowledge of how normal predicates treat modes. It can also diagnose
716 certain kinds of common errors in the use of normal predicates; for
717 instance, it is almost always an error to use a normal predicate
718 without specifying a mode.
720 Predicates that do something different with their @var{mode} argument
721 are called @dfn{special}. The generic predicates
722 @code{address_operand} and @code{pmode_register_operand} are special
723 predicates. @command{genrecog} does not do any optimizations or
724 diagnosis when special predicates are used.
727 * Machine-Independent Predicates:: Predicates available to all back ends.
728 * Defining Predicates:: How to write machine-specific predicate
732 @node Machine-Independent Predicates
733 @subsection Machine-Independent Predicates
734 @cindex machine-independent predicates
735 @cindex generic predicates
737 These are the generic predicates available to all back ends. They are
738 defined in @file{recog.c}. The first category of predicates allow
739 only constant, or @dfn{immediate}, operands.
741 @defun immediate_operand
742 This predicate allows any sort of constant that fits in @var{mode}.
743 It is an appropriate choice for instructions that take operands that
747 @defun const_int_operand
748 This predicate allows any @code{CONST_INT} expression that fits in
749 @var{mode}. It is an appropriate choice for an immediate operand that
750 does not allow a symbol or label.
753 @defun const_double_operand
754 This predicate accepts any @code{CONST_DOUBLE} expression that has
755 exactly @var{mode}. If @var{mode} is @code{VOIDmode}, it will also
756 accept @code{CONST_INT}. It is intended for immediate floating point
761 The second category of predicates allow only some kind of machine
764 @defun register_operand
765 This predicate allows any @code{REG} or @code{SUBREG} expression that
766 is valid for @var{mode}. It is often suitable for arithmetic
767 instruction operands on a RISC machine.
770 @defun pmode_register_operand
771 This is a slight variant on @code{register_operand} which works around
772 a limitation in the machine-description reader.
775 (match_operand @var{n} "pmode_register_operand" @var{constraint})
782 (match_operand:P @var{n} "register_operand" @var{constraint})
786 would mean, if the machine-description reader accepted @samp{:P}
787 mode suffixes. Unfortunately, it cannot, because @code{Pmode} is an
788 alias for some other mode, and might vary with machine-specific
789 options. @xref{Misc}.
792 @defun scratch_operand
793 This predicate allows hard registers and @code{SCRATCH} expressions,
794 but not pseudo-registers. It is used internally by @code{match_scratch};
795 it should not be used directly.
799 The third category of predicates allow only some kind of memory reference.
801 @defun memory_operand
802 This predicate allows any valid reference to a quantity of mode
803 @var{mode} in memory, as determined by the weak form of
804 @code{GO_IF_LEGITIMATE_ADDRESS} (@pxref{Addressing Modes}).
807 @defun address_operand
808 This predicate is a little unusual; it allows any operand that is a
809 valid expression for the @emph{address} of a quantity of mode
810 @var{mode}, again determined by the weak form of
811 @code{GO_IF_LEGITIMATE_ADDRESS}. To first order, if
812 @samp{@w{(mem:@var{mode} (@var{exp}))}} is acceptable to
813 @code{memory_operand}, then @var{exp} is acceptable to
814 @code{address_operand}. Note that @var{exp} does not necessarily have
818 @defun indirect_operand
819 This is a stricter form of @code{memory_operand} which allows only
820 memory references with a @code{general_operand} as the address
821 expression. New uses of this predicate are discouraged, because
822 @code{general_operand} is very permissive, so it's hard to tell what
823 an @code{indirect_operand} does or does not allow. If a target has
824 different requirements for memory operands for different instructions,
825 it is better to define target-specific predicates which enforce the
826 hardware's requirements explicitly.
830 This predicate allows a memory reference suitable for pushing a value
831 onto the stack. This will be a @code{MEM} which refers to
832 @code{stack_pointer_rtx}, with a side-effect in its address expression
833 (@pxref{Incdec}); which one is determined by the
834 @code{STACK_PUSH_CODE} macro (@pxref{Frame Layout}).
838 This predicate allows a memory reference suitable for popping a value
839 off the stack. Again, this will be a @code{MEM} referring to
840 @code{stack_pointer_rtx}, with a side-effect in its address
841 expression. However, this time @code{STACK_POP_CODE} is expected.
845 The fourth category of predicates allow some combination of the above
848 @defun nonmemory_operand
849 This predicate allows any immediate or register operand valid for @var{mode}.
852 @defun nonimmediate_operand
853 This predicate allows any register or memory operand valid for @var{mode}.
856 @defun general_operand
857 This predicate allows any immediate, register, or memory operand
858 valid for @var{mode}.
862 Finally, there is one generic operator predicate.
864 @defun comparison_operator
865 This predicate matches any expression which performs an arithmetic
866 comparison in @var{mode}; that is, @code{COMPARISON_P} is true for the
870 @node Defining Predicates
871 @subsection Defining Machine-Specific Predicates
872 @cindex defining predicates
873 @findex define_predicate
874 @findex define_special_predicate
876 Many machines have requirements for their operands that cannot be
877 expressed precisely using the generic predicates. You can define
878 additional predicates using @code{define_predicate} and
879 @code{define_special_predicate} expressions. These expressions have
884 The name of the predicate, as it will be referred to in
885 @code{match_operand} or @code{match_operator} expressions.
888 An RTL expression which evaluates to true if the predicate allows the
889 operand @var{op}, false if it does not. This expression can only use
890 the following RTL codes:
894 When written inside a predicate expression, a @code{MATCH_OPERAND}
895 expression evaluates to true if the predicate it names would allow
896 @var{op}. The operand number and constraint are ignored. Due to
897 limitations in @command{genrecog}, you can only refer to generic
898 predicates and predicates that have already been defined.
901 This expression evaluates to true if @var{op} or a specified
902 subexpression of @var{op} has one of a given list of RTX codes.
904 The first operand of this expression is a string constant containing a
905 comma-separated list of RTX code names (in lower case). These are the
906 codes for which the @code{MATCH_CODE} will be true.
908 The second operand is a string constant which indicates what
909 subexpression of @var{op} to examine. If it is absent or the empty
910 string, @var{op} itself is examined. Otherwise, the string constant
911 must be a sequence of digits and/or lowercase letters. Each character
912 indicates a subexpression to extract from the current expression; for
913 the first character this is @var{op}, for the second and subsequent
914 characters it is the result of the previous character. A digit
915 @var{n} extracts @samp{@w{XEXP (@var{e}, @var{n})}}; a letter @var{l}
916 extracts @samp{@w{XVECEXP (@var{e}, 0, @var{n})}} where @var{n} is the
917 alphabetic ordinal of @var{l} (0 for `a', 1 for 'b', and so on). The
918 @code{MATCH_CODE} then examines the RTX code of the subexpression
919 extracted by the complete string. It is not possible to extract
920 components of an @code{rtvec} that is not at position 0 within its RTX
924 This expression has one operand, a string constant containing a C
925 expression. The predicate's arguments, @var{op} and @var{mode}, are
926 available with those names in the C expression. The @code{MATCH_TEST}
927 evaluates to true if the C expression evaluates to a nonzero value.
928 @code{MATCH_TEST} expressions must not have side effects.
934 The basic @samp{MATCH_} expressions can be combined using these
935 logical operators, which have the semantics of the C operators
936 @samp{&&}, @samp{||}, @samp{!}, and @samp{@w{? :}} respectively. As
937 in Common Lisp, you may give an @code{AND} or @code{IOR} expression an
938 arbitrary number of arguments; this has exactly the same effect as
939 writing a chain of two-argument @code{AND} or @code{IOR} expressions.
943 An optional block of C code, which should execute
944 @samp{@w{return true}} if the predicate is found to match and
945 @samp{@w{return false}} if it does not. It must not have any side
946 effects. The predicate arguments, @var{op} and @var{mode}, are
947 available with those names.
949 If a code block is present in a predicate definition, then the RTL
950 expression must evaluate to true @emph{and} the code block must
951 execute @samp{@w{return true}} for the predicate to allow the operand.
952 The RTL expression is evaluated first; do not re-check anything in the
953 code block that was checked in the RTL expression.
956 The program @command{genrecog} scans @code{define_predicate} and
957 @code{define_special_predicate} expressions to determine which RTX
958 codes are possibly allowed. You should always make this explicit in
959 the RTL predicate expression, using @code{MATCH_OPERAND} and
962 Here is an example of a simple predicate definition, from the IA64
967 ;; @r{True if @var{op} is a @code{SYMBOL_REF} which refers to the sdata section.}
968 (define_predicate "small_addr_symbolic_operand"
969 (and (match_code "symbol_ref")
970 (match_test "SYMBOL_REF_SMALL_ADDR_P (op)")))
975 And here is another, showing the use of the C block.
979 ;; @r{True if @var{op} is a register operand that is (or could be) a GR reg.}
980 (define_predicate "gr_register_operand"
981 (match_operand 0 "register_operand")
984 if (GET_CODE (op) == SUBREG)
985 op = SUBREG_REG (op);
988 return (regno >= FIRST_PSEUDO_REGISTER || GENERAL_REGNO_P (regno));
993 Predicates written with @code{define_predicate} automatically include
994 a test that @var{mode} is @code{VOIDmode}, or @var{op} has the same
995 mode as @var{mode}, or @var{op} is a @code{CONST_INT} or
996 @code{CONST_DOUBLE}. They do @emph{not} check specifically for
997 integer @code{CONST_DOUBLE}, nor do they test that the value of either
998 kind of constant fits in the requested mode. This is because
999 target-specific predicates that take constants usually have to do more
1000 stringent value checks anyway. If you need the exact same treatment
1001 of @code{CONST_INT} or @code{CONST_DOUBLE} that the generic predicates
1002 provide, use a @code{MATCH_OPERAND} subexpression to call
1003 @code{const_int_operand}, @code{const_double_operand}, or
1004 @code{immediate_operand}.
1006 Predicates written with @code{define_special_predicate} do not get any
1007 automatic mode checks, and are treated as having special mode handling
1008 by @command{genrecog}.
1010 The program @command{genpreds} is responsible for generating code to
1011 test predicates. It also writes a header file containing function
1012 declarations for all machine-specific predicates. It is not necessary
1013 to declare these predicates in @file{@var{cpu}-protos.h}.
1016 @c Most of this node appears by itself (in a different place) even
1017 @c when the INTERNALS flag is clear. Passages that require the internals
1018 @c manual's context are conditionalized to appear only in the internals manual.
1021 @section Operand Constraints
1022 @cindex operand constraints
1025 Each @code{match_operand} in an instruction pattern can specify
1026 constraints for the operands allowed. The constraints allow you to
1027 fine-tune matching within the set of operands allowed by the
1033 @section Constraints for @code{asm} Operands
1034 @cindex operand constraints, @code{asm}
1035 @cindex constraints, @code{asm}
1036 @cindex @code{asm} constraints
1038 Here are specific details on what constraint letters you can use with
1039 @code{asm} operands.
1041 Constraints can say whether
1042 an operand may be in a register, and which kinds of register; whether the
1043 operand can be a memory reference, and which kinds of address; whether the
1044 operand may be an immediate constant, and which possible values it may
1045 have. Constraints can also require two operands to match.
1049 * Simple Constraints:: Basic use of constraints.
1050 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1051 * Class Preferences:: Constraints guide which hard register to put things in.
1052 * Modifiers:: More precise control over effects of constraints.
1053 * Machine Constraints:: Existing constraints for some particular machines.
1054 * Define Constraints:: How to define machine-specific constraints.
1055 * C Constraint Interface:: How to test constraints from C code.
1061 * Simple Constraints:: Basic use of constraints.
1062 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1063 * Modifiers:: More precise control over effects of constraints.
1064 * Machine Constraints:: Special constraints for some particular machines.
1068 @node Simple Constraints
1069 @subsection Simple Constraints
1070 @cindex simple constraints
1072 The simplest kind of constraint is a string full of letters, each of
1073 which describes one kind of operand that is permitted. Here are
1074 the letters that are allowed:
1078 Whitespace characters are ignored and can be inserted at any position
1079 except the first. This enables each alternative for different operands to
1080 be visually aligned in the machine description even if they have different
1081 number of constraints and modifiers.
1083 @cindex @samp{m} in constraint
1084 @cindex memory references in constraints
1086 A memory operand is allowed, with any kind of address that the machine
1087 supports in general.
1089 @cindex offsettable address
1090 @cindex @samp{o} in constraint
1092 A memory operand is allowed, but only if the address is
1093 @dfn{offsettable}. This means that adding a small integer (actually,
1094 the width in bytes of the operand, as determined by its machine mode)
1095 may be added to the address and the result is also a valid memory
1098 @cindex autoincrement/decrement addressing
1099 For example, an address which is constant is offsettable; so is an
1100 address that is the sum of a register and a constant (as long as a
1101 slightly larger constant is also within the range of address-offsets
1102 supported by the machine); but an autoincrement or autodecrement
1103 address is not offsettable. More complicated indirect/indexed
1104 addresses may or may not be offsettable depending on the other
1105 addressing modes that the machine supports.
1107 Note that in an output operand which can be matched by another
1108 operand, the constraint letter @samp{o} is valid only when accompanied
1109 by both @samp{<} (if the target machine has predecrement addressing)
1110 and @samp{>} (if the target machine has preincrement addressing).
1112 @cindex @samp{V} in constraint
1114 A memory operand that is not offsettable. In other words, anything that
1115 would fit the @samp{m} constraint but not the @samp{o} constraint.
1117 @cindex @samp{<} in constraint
1119 A memory operand with autodecrement addressing (either predecrement or
1120 postdecrement) is allowed.
1122 @cindex @samp{>} in constraint
1124 A memory operand with autoincrement addressing (either preincrement or
1125 postincrement) is allowed.
1127 @cindex @samp{r} in constraint
1128 @cindex registers in constraints
1130 A register operand is allowed provided that it is in a general
1133 @cindex constants in constraints
1134 @cindex @samp{i} in constraint
1136 An immediate integer operand (one with constant value) is allowed.
1137 This includes symbolic constants whose values will be known only at
1138 assembly time or later.
1140 @cindex @samp{n} in constraint
1142 An immediate integer operand with a known numeric value is allowed.
1143 Many systems cannot support assembly-time constants for operands less
1144 than a word wide. Constraints for these operands should use @samp{n}
1145 rather than @samp{i}.
1147 @cindex @samp{I} in constraint
1148 @item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P}
1149 Other letters in the range @samp{I} through @samp{P} may be defined in
1150 a machine-dependent fashion to permit immediate integer operands with
1151 explicit integer values in specified ranges. For example, on the
1152 68000, @samp{I} is defined to stand for the range of values 1 to 8.
1153 This is the range permitted as a shift count in the shift
1156 @cindex @samp{E} in constraint
1158 An immediate floating operand (expression code @code{const_double}) is
1159 allowed, but only if the target floating point format is the same as
1160 that of the host machine (on which the compiler is running).
1162 @cindex @samp{F} in constraint
1164 An immediate floating operand (expression code @code{const_double} or
1165 @code{const_vector}) is allowed.
1167 @cindex @samp{G} in constraint
1168 @cindex @samp{H} in constraint
1169 @item @samp{G}, @samp{H}
1170 @samp{G} and @samp{H} may be defined in a machine-dependent fashion to
1171 permit immediate floating operands in particular ranges of values.
1173 @cindex @samp{s} in constraint
1175 An immediate integer operand whose value is not an explicit integer is
1178 This might appear strange; if an insn allows a constant operand with a
1179 value not known at compile time, it certainly must allow any known
1180 value. So why use @samp{s} instead of @samp{i}? Sometimes it allows
1181 better code to be generated.
1183 For example, on the 68000 in a fullword instruction it is possible to
1184 use an immediate operand; but if the immediate value is between @minus{}128
1185 and 127, better code results from loading the value into a register and
1186 using the register. This is because the load into the register can be
1187 done with a @samp{moveq} instruction. We arrange for this to happen
1188 by defining the letter @samp{K} to mean ``any integer outside the
1189 range @minus{}128 to 127'', and then specifying @samp{Ks} in the operand
1192 @cindex @samp{g} in constraint
1194 Any register, memory or immediate integer operand is allowed, except for
1195 registers that are not general registers.
1197 @cindex @samp{X} in constraint
1200 Any operand whatsoever is allowed, even if it does not satisfy
1201 @code{general_operand}. This is normally used in the constraint of
1202 a @code{match_scratch} when certain alternatives will not actually
1203 require a scratch register.
1206 Any operand whatsoever is allowed.
1209 @cindex @samp{0} in constraint
1210 @cindex digits in constraint
1211 @item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9}
1212 An operand that matches the specified operand number is allowed. If a
1213 digit is used together with letters within the same alternative, the
1214 digit should come last.
1216 This number is allowed to be more than a single digit. If multiple
1217 digits are encountered consecutively, they are interpreted as a single
1218 decimal integer. There is scant chance for ambiguity, since to-date
1219 it has never been desirable that @samp{10} be interpreted as matching
1220 either operand 1 @emph{or} operand 0. Should this be desired, one
1221 can use multiple alternatives instead.
1223 @cindex matching constraint
1224 @cindex constraint, matching
1225 This is called a @dfn{matching constraint} and what it really means is
1226 that the assembler has only a single operand that fills two roles
1228 considered separate in the RTL insn. For example, an add insn has two
1229 input operands and one output operand in the RTL, but on most CISC
1232 which @code{asm} distinguishes. For example, an add instruction uses
1233 two input operands and an output operand, but on most CISC
1235 machines an add instruction really has only two operands, one of them an
1236 input-output operand:
1242 Matching constraints are used in these circumstances.
1243 More precisely, the two operands that match must include one input-only
1244 operand and one output-only operand. Moreover, the digit must be a
1245 smaller number than the number of the operand that uses it in the
1249 For operands to match in a particular case usually means that they
1250 are identical-looking RTL expressions. But in a few special cases
1251 specific kinds of dissimilarity are allowed. For example, @code{*x}
1252 as an input operand will match @code{*x++} as an output operand.
1253 For proper results in such cases, the output template should always
1254 use the output-operand's number when printing the operand.
1257 @cindex load address instruction
1258 @cindex push address instruction
1259 @cindex address constraints
1260 @cindex @samp{p} in constraint
1262 An operand that is a valid memory address is allowed. This is
1263 for ``load address'' and ``push address'' instructions.
1265 @findex address_operand
1266 @samp{p} in the constraint must be accompanied by @code{address_operand}
1267 as the predicate in the @code{match_operand}. This predicate interprets
1268 the mode specified in the @code{match_operand} as the mode of the memory
1269 reference for which the address would be valid.
1271 @cindex other register constraints
1272 @cindex extensible constraints
1273 @item @var{other-letters}
1274 Other letters can be defined in machine-dependent fashion to stand for
1275 particular classes of registers or other arbitrary operand types.
1276 @samp{d}, @samp{a} and @samp{f} are defined on the 68000/68020 to stand
1277 for data, address and floating point registers.
1281 In order to have valid assembler code, each operand must satisfy
1282 its constraint. But a failure to do so does not prevent the pattern
1283 from applying to an insn. Instead, it directs the compiler to modify
1284 the code so that the constraint will be satisfied. Usually this is
1285 done by copying an operand into a register.
1287 Contrast, therefore, the two instruction patterns that follow:
1291 [(set (match_operand:SI 0 "general_operand" "=r")
1292 (plus:SI (match_dup 0)
1293 (match_operand:SI 1 "general_operand" "r")))]
1299 which has two operands, one of which must appear in two places, and
1303 [(set (match_operand:SI 0 "general_operand" "=r")
1304 (plus:SI (match_operand:SI 1 "general_operand" "0")
1305 (match_operand:SI 2 "general_operand" "r")))]
1311 which has three operands, two of which are required by a constraint to be
1312 identical. If we are considering an insn of the form
1315 (insn @var{n} @var{prev} @var{next}
1317 (plus:SI (reg:SI 6) (reg:SI 109)))
1322 the first pattern would not apply at all, because this insn does not
1323 contain two identical subexpressions in the right place. The pattern would
1324 say, ``That does not look like an add instruction; try other patterns''.
1325 The second pattern would say, ``Yes, that's an add instruction, but there
1326 is something wrong with it''. It would direct the reload pass of the
1327 compiler to generate additional insns to make the constraint true. The
1328 results might look like this:
1331 (insn @var{n2} @var{prev} @var{n}
1332 (set (reg:SI 3) (reg:SI 6))
1335 (insn @var{n} @var{n2} @var{next}
1337 (plus:SI (reg:SI 3) (reg:SI 109)))
1341 It is up to you to make sure that each operand, in each pattern, has
1342 constraints that can handle any RTL expression that could be present for
1343 that operand. (When multiple alternatives are in use, each pattern must,
1344 for each possible combination of operand expressions, have at least one
1345 alternative which can handle that combination of operands.) The
1346 constraints don't need to @emph{allow} any possible operand---when this is
1347 the case, they do not constrain---but they must at least point the way to
1348 reloading any possible operand so that it will fit.
1352 If the constraint accepts whatever operands the predicate permits,
1353 there is no problem: reloading is never necessary for this operand.
1355 For example, an operand whose constraints permit everything except
1356 registers is safe provided its predicate rejects registers.
1358 An operand whose predicate accepts only constant values is safe
1359 provided its constraints include the letter @samp{i}. If any possible
1360 constant value is accepted, then nothing less than @samp{i} will do;
1361 if the predicate is more selective, then the constraints may also be
1365 Any operand expression can be reloaded by copying it into a register.
1366 So if an operand's constraints allow some kind of register, it is
1367 certain to be safe. It need not permit all classes of registers; the
1368 compiler knows how to copy a register into another register of the
1369 proper class in order to make an instruction valid.
1371 @cindex nonoffsettable memory reference
1372 @cindex memory reference, nonoffsettable
1374 A nonoffsettable memory reference can be reloaded by copying the
1375 address into a register. So if the constraint uses the letter
1376 @samp{o}, all memory references are taken care of.
1379 A constant operand can be reloaded by allocating space in memory to
1380 hold it as preinitialized data. Then the memory reference can be used
1381 in place of the constant. So if the constraint uses the letters
1382 @samp{o} or @samp{m}, constant operands are not a problem.
1385 If the constraint permits a constant and a pseudo register used in an insn
1386 was not allocated to a hard register and is equivalent to a constant,
1387 the register will be replaced with the constant. If the predicate does
1388 not permit a constant and the insn is re-recognized for some reason, the
1389 compiler will crash. Thus the predicate must always recognize any
1390 objects allowed by the constraint.
1393 If the operand's predicate can recognize registers, but the constraint does
1394 not permit them, it can make the compiler crash. When this operand happens
1395 to be a register, the reload pass will be stymied, because it does not know
1396 how to copy a register temporarily into memory.
1398 If the predicate accepts a unary operator, the constraint applies to the
1399 operand. For example, the MIPS processor at ISA level 3 supports an
1400 instruction which adds two registers in @code{SImode} to produce a
1401 @code{DImode} result, but only if the registers are correctly sign
1402 extended. This predicate for the input operands accepts a
1403 @code{sign_extend} of an @code{SImode} register. Write the constraint
1404 to indicate the type of register that is required for the operand of the
1408 @node Multi-Alternative
1409 @subsection Multiple Alternative Constraints
1410 @cindex multiple alternative constraints
1412 Sometimes a single instruction has multiple alternative sets of possible
1413 operands. For example, on the 68000, a logical-or instruction can combine
1414 register or an immediate value into memory, or it can combine any kind of
1415 operand into a register; but it cannot combine one memory location into
1418 These constraints are represented as multiple alternatives. An alternative
1419 can be described by a series of letters for each operand. The overall
1420 constraint for an operand is made from the letters for this operand
1421 from the first alternative, a comma, the letters for this operand from
1422 the second alternative, a comma, and so on until the last alternative.
1424 Here is how it is done for fullword logical-or on the 68000:
1427 (define_insn "iorsi3"
1428 [(set (match_operand:SI 0 "general_operand" "=m,d")
1429 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
1430 (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
1434 The first alternative has @samp{m} (memory) for operand 0, @samp{0} for
1435 operand 1 (meaning it must match operand 0), and @samp{dKs} for operand
1436 2. The second alternative has @samp{d} (data register) for operand 0,
1437 @samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and
1438 @samp{%} in the constraints apply to all the alternatives; their
1439 meaning is explained in the next section (@pxref{Class Preferences}).
1442 @c FIXME Is this ? and ! stuff of use in asm()? If not, hide unless INTERNAL
1443 If all the operands fit any one alternative, the instruction is valid.
1444 Otherwise, for each alternative, the compiler counts how many instructions
1445 must be added to copy the operands so that that alternative applies.
1446 The alternative requiring the least copying is chosen. If two alternatives
1447 need the same amount of copying, the one that comes first is chosen.
1448 These choices can be altered with the @samp{?} and @samp{!} characters:
1451 @cindex @samp{?} in constraint
1452 @cindex question mark
1454 Disparage slightly the alternative that the @samp{?} appears in,
1455 as a choice when no alternative applies exactly. The compiler regards
1456 this alternative as one unit more costly for each @samp{?} that appears
1459 @cindex @samp{!} in constraint
1460 @cindex exclamation point
1462 Disparage severely the alternative that the @samp{!} appears in.
1463 This alternative can still be used if it fits without reloading,
1464 but if reloading is needed, some other alternative will be used.
1468 When an insn pattern has multiple alternatives in its constraints, often
1469 the appearance of the assembler code is determined mostly by which
1470 alternative was matched. When this is so, the C code for writing the
1471 assembler code can use the variable @code{which_alternative}, which is
1472 the ordinal number of the alternative that was actually satisfied (0 for
1473 the first, 1 for the second alternative, etc.). @xref{Output Statement}.
1477 @node Class Preferences
1478 @subsection Register Class Preferences
1479 @cindex class preference constraints
1480 @cindex register class preference constraints
1482 @cindex voting between constraint alternatives
1483 The operand constraints have another function: they enable the compiler
1484 to decide which kind of hardware register a pseudo register is best
1485 allocated to. The compiler examines the constraints that apply to the
1486 insns that use the pseudo register, looking for the machine-dependent
1487 letters such as @samp{d} and @samp{a} that specify classes of registers.
1488 The pseudo register is put in whichever class gets the most ``votes''.
1489 The constraint letters @samp{g} and @samp{r} also vote: they vote in
1490 favor of a general register. The machine description says which registers
1491 are considered general.
1493 Of course, on some machines all registers are equivalent, and no register
1494 classes are defined. Then none of this complexity is relevant.
1498 @subsection Constraint Modifier Characters
1499 @cindex modifiers in constraints
1500 @cindex constraint modifier characters
1502 @c prevent bad page break with this line
1503 Here are constraint modifier characters.
1506 @cindex @samp{=} in constraint
1508 Means that this operand is write-only for this instruction: the previous
1509 value is discarded and replaced by output data.
1511 @cindex @samp{+} in constraint
1513 Means that this operand is both read and written by the instruction.
1515 When the compiler fixes up the operands to satisfy the constraints,
1516 it needs to know which operands are inputs to the instruction and
1517 which are outputs from it. @samp{=} identifies an output; @samp{+}
1518 identifies an operand that is both input and output; all other operands
1519 are assumed to be input only.
1521 If you specify @samp{=} or @samp{+} in a constraint, you put it in the
1522 first character of the constraint string.
1524 @cindex @samp{&} in constraint
1525 @cindex earlyclobber operand
1527 Means (in a particular alternative) that this operand is an
1528 @dfn{earlyclobber} operand, which is modified before the instruction is
1529 finished using the input operands. Therefore, this operand may not lie
1530 in a register that is used as an input operand or as part of any memory
1533 @samp{&} applies only to the alternative in which it is written. In
1534 constraints with multiple alternatives, sometimes one alternative
1535 requires @samp{&} while others do not. See, for example, the
1536 @samp{movdf} insn of the 68000.
1538 An input operand can be tied to an earlyclobber operand if its only
1539 use as an input occurs before the early result is written. Adding
1540 alternatives of this form often allows GCC to produce better code
1541 when only some of the inputs can be affected by the earlyclobber.
1542 See, for example, the @samp{mulsi3} insn of the ARM@.
1544 @samp{&} does not obviate the need to write @samp{=}.
1546 @cindex @samp{%} in constraint
1548 Declares the instruction to be commutative for this operand and the
1549 following operand. This means that the compiler may interchange the
1550 two operands if that is the cheapest way to make all operands fit the
1553 This is often used in patterns for addition instructions
1554 that really have only two operands: the result must go in one of the
1555 arguments. Here for example, is how the 68000 halfword-add
1556 instruction is defined:
1559 (define_insn "addhi3"
1560 [(set (match_operand:HI 0 "general_operand" "=m,r")
1561 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
1562 (match_operand:HI 2 "general_operand" "di,g")))]
1566 GCC can only handle one commutative pair in an asm; if you use more,
1567 the compiler may fail. Note that you need not use the modifier if
1568 the two alternatives are strictly identical; this would only waste
1569 time in the reload pass. The modifier is not operational after
1570 register allocation, so the result of @code{define_peephole2}
1571 and @code{define_split}s performed after reload cannot rely on
1572 @samp{%} to make the intended insn match.
1574 @cindex @samp{#} in constraint
1576 Says that all following characters, up to the next comma, are to be
1577 ignored as a constraint. They are significant only for choosing
1578 register preferences.
1580 @cindex @samp{*} in constraint
1582 Says that the following character should be ignored when choosing
1583 register preferences. @samp{*} has no effect on the meaning of the
1584 constraint as a constraint, and no effect on reloading.
1587 Here is an example: the 68000 has an instruction to sign-extend a
1588 halfword in a data register, and can also sign-extend a value by
1589 copying it into an address register. While either kind of register is
1590 acceptable, the constraints on an address-register destination are
1591 less strict, so it is best if register allocation makes an address
1592 register its goal. Therefore, @samp{*} is used so that the @samp{d}
1593 constraint letter (for data register) is ignored when computing
1594 register preferences.
1597 (define_insn "extendhisi2"
1598 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1600 (match_operand:HI 1 "general_operand" "0,g")))]
1606 @node Machine Constraints
1607 @subsection Constraints for Particular Machines
1608 @cindex machine specific constraints
1609 @cindex constraints, machine specific
1611 Whenever possible, you should use the general-purpose constraint letters
1612 in @code{asm} arguments, since they will convey meaning more readily to
1613 people reading your code. Failing that, use the constraint letters
1614 that usually have very similar meanings across architectures. The most
1615 commonly used constraints are @samp{m} and @samp{r} (for memory and
1616 general-purpose registers respectively; @pxref{Simple Constraints}), and
1617 @samp{I}, usually the letter indicating the most common
1618 immediate-constant format.
1620 Each architecture defines additional constraints. These constraints
1621 are used by the compiler itself for instruction generation, as well as
1622 for @code{asm} statements; therefore, some of the constraints are not
1623 particularly useful for @code{asm}. Here is a summary of some of the
1624 machine-dependent constraints available on some particular machines;
1625 it includes both constraints that are useful for @code{asm} and
1626 constraints that aren't. The compiler source file mentioned in the
1627 table heading for each architecture is the definitive reference for
1628 the meanings of that architecture's constraints.
1631 @item ARM family---@file{config/arm/arm.h}
1634 Floating-point register
1637 VFP floating-point register
1640 One of the floating-point constants 0.0, 0.5, 1.0, 2.0, 3.0, 4.0, 5.0
1644 Floating-point constant that would satisfy the constraint @samp{F} if it
1648 Integer that is valid as an immediate operand in a data processing
1649 instruction. That is, an integer in the range 0 to 255 rotated by a
1653 Integer in the range @minus{}4095 to 4095
1656 Integer that satisfies constraint @samp{I} when inverted (ones complement)
1659 Integer that satisfies constraint @samp{I} when negated (twos complement)
1662 Integer in the range 0 to 32
1665 A memory reference where the exact address is in a single register
1666 (`@samp{m}' is preferable for @code{asm} statements)
1669 An item in the constant pool
1672 A symbol in the text segment of the current file
1675 A memory reference suitable for VFP load/store insns (reg+constant offset)
1678 A memory reference suitable for iWMMXt load/store instructions.
1681 A memory reference suitable for the ARMv4 ldrsb instruction.
1684 @item AVR family---@file{config/avr/constraints.md}
1687 Registers from r0 to r15
1690 Registers from r16 to r23
1693 Registers from r16 to r31
1696 Registers from r24 to r31. These registers can be used in @samp{adiw} command
1699 Pointer register (r26--r31)
1702 Base pointer register (r28--r31)
1705 Stack pointer register (SPH:SPL)
1708 Temporary register r0
1711 Register pair X (r27:r26)
1714 Register pair Y (r29:r28)
1717 Register pair Z (r31:r30)
1720 Constant greater than @minus{}1, less than 64
1723 Constant greater than @minus{}64, less than 1
1732 Constant that fits in 8 bits
1735 Constant integer @minus{}1
1738 Constant integer 8, 16, or 24
1744 A floating point constant 0.0
1747 Integer constant in the range -6 @dots{} 5.
1750 A memory address based on Y or Z pointer with displacement.
1753 @item CRX Architecture---@file{config/crx/crx.h}
1757 Registers from r0 to r14 (registers without stack pointer)
1760 Register r16 (64-bit accumulator lo register)
1763 Register r17 (64-bit accumulator hi register)
1766 Register pair r16-r17. (64-bit accumulator lo-hi pair)
1769 Constant that fits in 3 bits
1772 Constant that fits in 4 bits
1775 Constant that fits in 5 bits
1778 Constant that is one of -1, 4, -4, 7, 8, 12, 16, 20, 32, 48
1781 Floating point constant that is legal for store immediate
1784 @item Hewlett-Packard PA-RISC---@file{config/pa/pa.h}
1790 Floating point register
1793 Shift amount register
1796 Floating point register (deprecated)
1799 Upper floating point register (32-bit), floating point register (64-bit)
1805 Signed 11-bit integer constant
1808 Signed 14-bit integer constant
1811 Integer constant that can be deposited with a @code{zdepi} instruction
1814 Signed 5-bit integer constant
1820 Integer constant that can be loaded with a @code{ldil} instruction
1823 Integer constant whose value plus one is a power of 2
1826 Integer constant that can be used for @code{and} operations in @code{depi}
1827 and @code{extru} instructions
1836 Floating-point constant 0.0
1839 A @code{lo_sum} data-linkage-table memory operand
1842 A memory operand that can be used as the destination operand of an
1843 integer store instruction
1846 A scaled or unscaled indexed memory operand
1849 A memory operand for floating-point loads and stores
1852 A register indirect memory operand
1855 @item PowerPC and IBM RS6000---@file{config/rs6000/rs6000.h}
1858 Address base register
1861 Floating point register
1867 @samp{MQ}, @samp{CTR}, or @samp{LINK} register
1876 @samp{LINK} register
1879 @samp{CR} register (condition register) number 0
1882 @samp{CR} register (condition register)
1885 @samp{FPMEM} stack memory for FPR-GPR transfers
1888 Signed 16-bit constant
1891 Unsigned 16-bit constant shifted left 16 bits (use @samp{L} instead for
1892 @code{SImode} constants)
1895 Unsigned 16-bit constant
1898 Signed 16-bit constant shifted left 16 bits
1901 Constant larger than 31
1910 Constant whose negation is a signed 16-bit constant
1913 Floating point constant that can be loaded into a register with one
1914 instruction per word
1917 Integer/Floating point constant that can be loaded into a register using
1921 Memory operand that is an offset from a register (@samp{m} is preferable
1922 for @code{asm} statements)
1925 Memory operand that is an indexed or indirect from a register (@samp{m} is
1926 preferable for @code{asm} statements)
1932 Address operand that is an indexed or indirect from a register (@samp{p} is
1933 preferable for @code{asm} statements)
1936 Constant suitable as a 64-bit mask operand
1939 Constant suitable as a 32-bit mask operand
1942 System V Release 4 small data area reference
1945 AND masks that can be performed by two rldic@{l, r@} instructions
1948 Vector constant that does not require memory
1952 @item MorphoTech family---@file{config/mt/mt.h}
1955 Constant for an arithmetic insn (16-bit signed integer).
1961 Constant for a logical insn (16-bit zero-extended integer).
1964 A constant that can be loaded with @code{lui} (i.e.@: the bottom 16
1968 A constant that takes two words to load (i.e.@: not matched by
1969 @code{I}, @code{K}, or @code{L}).
1972 Negative 16-bit constants other than -65536.
1975 A 15-bit signed integer constant.
1978 A positive 16-bit constant.
1981 @item Intel 386---@file{config/i386/constraints.md}
1984 Legacy register---the eight integer registers available on all
1985 i386 processors (@code{a}, @code{b}, @code{c}, @code{d},
1986 @code{si}, @code{di}, @code{bp}, @code{sp}).
1989 Any register accessible as @code{@var{r}l}. In 32-bit mode, @code{a},
1990 @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.
1993 Any register accessible as @code{@var{r}h}: @code{a}, @code{b},
1994 @code{c}, and @code{d}.
1998 Any register that can be used as the index in a base+index memory
1999 access: that is, any general register except the stack pointer.
2003 The @code{a} register.
2006 The @code{b} register.
2009 The @code{c} register.
2012 The @code{d} register.
2015 The @code{si} register.
2018 The @code{di} register.
2021 The @code{a} and @code{d} registers, as a pair (for instructions that
2022 return half the result in one and half in the other).
2025 Any 80387 floating-point (stack) register.
2028 Top of 80387 floating-point stack (@code{%st(0)}).
2031 Second from top of 80387 floating-point stack (@code{%st(1)}).
2045 Integer constant in the range 0 @dots{} 31, for 32-bit shifts.
2048 Integer constant in the range 0 @dots{} 63, for 64-bit shifts.
2051 Signed 8-bit integer constant.
2054 @code{0xFF} or @code{0xFFFF}, for andsi as a zero-extending move.
2057 0, 1, 2, or 3 (shifts for the @code{lea} instruction).
2060 Unsigned 8-bit integer constant (for @code{in} and @code{out}
2065 Integer constant in the range 0 @dots{} 127, for 128-bit shifts.
2069 Standard 80387 floating point constant.
2072 Standard SSE floating point constant.
2075 32-bit signed integer constant, or a symbolic reference known
2076 to fit that range (for immediate operands in sign-extending x86-64
2080 32-bit unsigned integer constant, or a symbolic reference known
2081 to fit that range (for immediate operands in zero-extending x86-64
2086 @item Intel IA-64---@file{config/ia64/ia64.h}
2089 General register @code{r0} to @code{r3} for @code{addl} instruction
2095 Predicate register (@samp{c} as in ``conditional'')
2098 Application register residing in M-unit
2101 Application register residing in I-unit
2104 Floating-point register
2108 Remember that @samp{m} allows postincrement and postdecrement which
2109 require printing with @samp{%Pn} on IA-64.
2110 Use @samp{S} to disallow postincrement and postdecrement.
2113 Floating-point constant 0.0 or 1.0
2116 14-bit signed integer constant
2119 22-bit signed integer constant
2122 8-bit signed integer constant for logical instructions
2125 8-bit adjusted signed integer constant for compare pseudo-ops
2128 6-bit unsigned integer constant for shift counts
2131 9-bit signed integer constant for load and store postincrements
2137 0 or @minus{}1 for @code{dep} instruction
2140 Non-volatile memory for floating-point loads and stores
2143 Integer constant in the range 1 to 4 for @code{shladd} instruction
2146 Memory operand except postincrement and postdecrement
2149 @item FRV---@file{config/frv/frv.h}
2152 Register in the class @code{ACC_REGS} (@code{acc0} to @code{acc7}).
2155 Register in the class @code{EVEN_ACC_REGS} (@code{acc0} to @code{acc7}).
2158 Register in the class @code{CC_REGS} (@code{fcc0} to @code{fcc3} and
2159 @code{icc0} to @code{icc3}).
2162 Register in the class @code{GPR_REGS} (@code{gr0} to @code{gr63}).
2165 Register in the class @code{EVEN_REGS} (@code{gr0} to @code{gr63}).
2166 Odd registers are excluded not in the class but through the use of a machine
2167 mode larger than 4 bytes.
2170 Register in the class @code{FPR_REGS} (@code{fr0} to @code{fr63}).
2173 Register in the class @code{FEVEN_REGS} (@code{fr0} to @code{fr63}).
2174 Odd registers are excluded not in the class but through the use of a machine
2175 mode larger than 4 bytes.
2178 Register in the class @code{LR_REG} (the @code{lr} register).
2181 Register in the class @code{QUAD_REGS} (@code{gr2} to @code{gr63}).
2182 Register numbers not divisible by 4 are excluded not in the class but through
2183 the use of a machine mode larger than 8 bytes.
2186 Register in the class @code{ICC_REGS} (@code{icc0} to @code{icc3}).
2189 Register in the class @code{FCC_REGS} (@code{fcc0} to @code{fcc3}).
2192 Register in the class @code{ICR_REGS} (@code{cc4} to @code{cc7}).
2195 Register in the class @code{FCR_REGS} (@code{cc0} to @code{cc3}).
2198 Register in the class @code{QUAD_FPR_REGS} (@code{fr0} to @code{fr63}).
2199 Register numbers not divisible by 4 are excluded not in the class but through
2200 the use of a machine mode larger than 8 bytes.
2203 Register in the class @code{SPR_REGS} (@code{lcr} and @code{lr}).
2206 Register in the class @code{QUAD_ACC_REGS} (@code{acc0} to @code{acc7}).
2209 Register in the class @code{ACCG_REGS} (@code{accg0} to @code{accg7}).
2212 Register in the class @code{CR_REGS} (@code{cc0} to @code{cc7}).
2215 Floating point constant zero
2218 6-bit signed integer constant
2221 10-bit signed integer constant
2224 16-bit signed integer constant
2227 16-bit unsigned integer constant
2230 12-bit signed integer constant that is negative---i.e.@: in the
2231 range of @minus{}2048 to @minus{}1
2237 12-bit signed integer constant that is greater than zero---i.e.@: in the
2242 @item Blackfin family---@file{config/bfin/bfin.h}
2251 A call clobbered P register.
2254 A single register. If @var{n} is in the range 0 to 7, the corresponding D
2255 register. If it is @code{A}, then the register P0.
2258 Even-numbered D register
2261 Odd-numbered D register
2264 Accumulator register.
2267 Even-numbered accumulator register.
2270 Odd-numbered accumulator register.
2282 Registers used for circular buffering, i.e. I, B, or L registers.
2297 Any D, P, B, M, I or L register.
2300 Additional registers typically used only in prologues and epilogues: RETS,
2301 RETN, RETI, RETX, RETE, ASTAT, SEQSTAT and USP.
2304 Any register except accumulators or CC.
2307 Signed 16 bit integer (in the range -32768 to 32767)
2310 Unsigned 16 bit integer (in the range 0 to 65535)
2313 Signed 7 bit integer (in the range -64 to 63)
2316 Unsigned 7 bit integer (in the range 0 to 127)
2319 Unsigned 5 bit integer (in the range 0 to 31)
2322 Signed 4 bit integer (in the range -8 to 7)
2325 Signed 3 bit integer (in the range -3 to 4)
2328 Unsigned 3 bit integer (in the range 0 to 7)
2331 Constant @var{n}, where @var{n} is a single-digit constant in the range 0 to 4.
2334 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2335 use with either accumulator.
2338 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2339 use only with accumulator A1.
2348 An integer constant with exactly a single bit set.
2351 An integer constant with all bits set except exactly one.
2359 @item M32C---@file{config/m32c/m32c.c}
2364 @samp{$sp}, @samp{$fb}, @samp{$sb}.
2367 Any control register, when they're 16 bits wide (nothing if control
2368 registers are 24 bits wide)
2371 Any control register, when they're 24 bits wide.
2380 $r0 or $r2, or $r2r0 for 32 bit values.
2383 $r1 or $r3, or $r3r1 for 32 bit values.
2386 A register that can hold a 64 bit value.
2389 $r0 or $r1 (registers with addressable high/low bytes)
2398 Address registers when they're 16 bits wide.
2401 Address registers when they're 24 bits wide.
2404 Registers that can hold QI values.
2407 Registers that can be used with displacements ($a0, $a1, $sb).
2410 Registers that can hold 32 bit values.
2413 Registers that can hold 16 bit values.
2416 Registers chat can hold 16 bit values, including all control
2420 $r0 through R1, plus $a0 and $a1.
2426 The memory-based pseudo-registers $mem0 through $mem15.
2429 Registers that can hold pointers (16 bit registers for r8c, m16c; 24
2430 bit registers for m32cm, m32c).
2433 Matches multiple registers in a PARALLEL to form a larger register.
2434 Used to match function return values.
2443 -32768 @dots{} 32767
2449 -8 @dots{} -1 or 1 @dots{} 8
2452 -16 @dots{} -1 or 1 @dots{} 16
2455 -32 @dots{} -1 or 1 @dots{} 32
2461 An 8 bit value with exactly one bit set.
2464 A 16 bit value with exactly one bit set.
2467 The common src/dest memory addressing modes.
2470 Memory addressed using $a0 or $a1.
2473 Memory addressed with immediate addresses.
2476 Memory addressed using the stack pointer ($sp).
2479 Memory addressed using the frame base register ($fb).
2482 Memory addressed using the small base register ($sb).
2488 @item MIPS---@file{config/mips/constraints.md}
2491 An address register. This is equivalent to @code{r} unless
2492 generating MIPS16 code.
2495 A floating-point register (if available).
2498 The @code{hi} register.
2501 The @code{lo} register.
2504 The @code{hi} and @code{lo} registers.
2507 A register suitable for use in an indirect jump. This will always be
2508 @code{$25} for @option{-mabicalls}.
2511 Equivalent to @code{r}; retained for backwards compatibility.
2514 A floating-point condition code register.
2517 A signed 16-bit constant (for arithmetic instructions).
2523 An unsigned 16-bit constant (for logic instructions).
2526 A signed 32-bit constant in which the lower 16 bits are zero.
2527 Such constants can be loaded using @code{lui}.
2530 A constant that cannot be loaded using @code{lui}, @code{addiu}
2534 A constant in the range -65535 to -1 (inclusive).
2537 A signed 15-bit constant.
2540 A constant in the range 1 to 65535 (inclusive).
2543 Floating-point zero.
2546 An address that can be used in a non-macro load or store.
2549 @item Motorola 680x0---@file{config/m68k/constraints.md}
2558 68881 floating-point register, if available
2561 Integer in the range 1 to 8
2564 16-bit signed number
2567 Signed number whose magnitude is greater than 0x80
2570 Integer in the range @minus{}8 to @minus{}1
2573 Signed number whose magnitude is greater than 0x100
2576 Range 24 to 31, rotatert:SI 8 to 1 expressed as rotate
2579 16 (for rotate using swap)
2582 Range 8 to 15, rotatert:HI 8 to 1 expressed as rotate
2585 Numbers that mov3q can handle
2588 Floating point constant that is not a 68881 constant
2591 Operands that satisfy 'm' when -mpcrel is in effect
2594 Operands that satisfy 's' when -mpcrel is not in effect
2597 Address register indirect addressing mode
2600 Register offset addressing
2615 Range of signed numbers that don't fit in 16 bits
2618 Integers valid for mvq
2621 Integers valid for a moveq followed by a swap
2624 Integers valid for mvz
2627 Integers valid for mvs
2633 Non-register operands allowed in clr
2637 @item Motorola 68HC11 & 68HC12 families---@file{config/m68hc11/m68hc11.h}
2652 Temporary soft register _.tmp
2655 A soft register _.d1 to _.d31
2658 Stack pointer register
2667 Pseudo register `z' (replaced by `x' or `y' at the end)
2670 An address register: x, y or z
2673 An address register: x or y
2676 Register pair (x:d) to form a 32-bit value
2679 Constants in the range @minus{}65536 to 65535
2682 Constants whose 16-bit low part is zero
2685 Constant integer 1 or @minus{}1
2691 Constants in the range @minus{}8 to 2
2696 @item SPARC---@file{config/sparc/sparc.h}
2699 Floating-point register on the SPARC-V8 architecture and
2700 lower floating-point register on the SPARC-V9 architecture.
2703 Floating-point register. It is equivalent to @samp{f} on the
2704 SPARC-V8 architecture and contains both lower and upper
2705 floating-point registers on the SPARC-V9 architecture.
2708 Floating-point condition code register.
2711 Lower floating-point register. It is only valid on the SPARC-V9
2712 architecture when the Visual Instruction Set is available.
2715 Floating-point register. It is only valid on the SPARC-V9 architecture
2716 when the Visual Instruction Set is available.
2719 64-bit global or out register for the SPARC-V8+ architecture.
2722 Signed 13-bit constant
2728 32-bit constant with the low 12 bits clear (a constant that can be
2729 loaded with the @code{sethi} instruction)
2732 A constant in the range supported by @code{movcc} instructions
2735 A constant in the range supported by @code{movrcc} instructions
2738 Same as @samp{K}, except that it verifies that bits that are not in the
2739 lower 32-bit range are all zero. Must be used instead of @samp{K} for
2740 modes wider than @code{SImode}
2749 Signed 13-bit constant, sign-extended to 32 or 64 bits
2752 Floating-point constant whose integral representation can
2753 be moved into an integer register using a single sethi
2757 Floating-point constant whose integral representation can
2758 be moved into an integer register using a single mov
2762 Floating-point constant whose integral representation can
2763 be moved into an integer register using a high/lo_sum
2764 instruction sequence
2767 Memory address aligned to an 8-byte boundary
2773 Memory address for @samp{e} constraint registers
2780 @item SPU---@file{config/spu/spu.h}
2783 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 64 bit value.
2786 An immediate for and/xor/or instructions. const_int is treated as a 64 bit value.
2789 An immediate for the @code{iohl} instruction. const_int is treated as a 64 bit value.
2792 An immediate which can be loaded with @code{fsmbi}.
2795 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 32 bit value.
2798 An immediate for most arithmetic instructions. const_int is treated as a 32 bit value.
2801 An immediate for and/xor/or instructions. const_int is treated as a 32 bit value.
2804 An immediate for the @code{iohl} instruction. const_int is treated as a 32 bit value.
2807 A constant in the range [-64, 63] for shift/rotate instructions.
2810 An unsigned 7-bit constant for conversion/nop/channel instructions.
2813 A signed 10-bit constant for most arithmetic instructions.
2816 A signed 16 bit immediate for @code{stop}.
2819 An unsigned 16-bit constant for @code{iohl} and @code{fsmbi}.
2822 An unsigned 7-bit constant whose 3 least significant bits are 0.
2825 An unsigned 3-bit constant for 16-byte rotates and shifts
2828 Call operand, reg, for indirect calls
2831 Call operand, symbol, for relative calls.
2834 Call operand, const_int, for absolute calls.
2837 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is sign extended to 128 bit.
2840 An immediate for shift and rotate instructions. const_int is treated as a 32 bit value.
2843 An immediate for and/xor/or instructions. const_int is sign extended as a 128 bit.
2846 An immediate for the @code{iohl} instruction. const_int is sign extended to 128 bit.
2850 @item S/390 and zSeries---@file{config/s390/s390.h}
2853 Address register (general purpose register except r0)
2856 Condition code register
2859 Data register (arbitrary general purpose register)
2862 Floating-point register
2865 Unsigned 8-bit constant (0--255)
2868 Unsigned 12-bit constant (0--4095)
2871 Signed 16-bit constant (@minus{}32768--32767)
2874 Value appropriate as displacement.
2877 for short displacement
2878 @item (-524288..524287)
2879 for long displacement
2883 Constant integer with a value of 0x7fffffff.
2886 Multiple letter constraint followed by 4 parameter letters.
2889 number of the part counting from most to least significant
2893 mode of the containing operand
2895 value of the other parts (F---all bits set)
2897 The constraint matches if the specified part of a constant
2898 has a value different from its other parts.
2901 Memory reference without index register and with short displacement.
2904 Memory reference with index register and short displacement.
2907 Memory reference without index register but with long displacement.
2910 Memory reference with index register and long displacement.
2913 Pointer with short displacement.
2916 Pointer with long displacement.
2919 Shift count operand.
2923 @item Score family---@file{config/score/score.h}
2926 Registers from r0 to r32.
2929 Registers from r0 to r16.
2932 r8---r11 or r22---r27 registers.
2953 cnt + lcb + scb register.
2956 cr0---cr15 register.
2968 cp1 + cp2 + cp3 registers.
2971 High 16-bit constant (32-bit constant with 16 LSBs zero).
2974 Unsigned 5 bit integer (in the range 0 to 31).
2977 Unsigned 16 bit integer (in the range 0 to 65535).
2980 Signed 16 bit integer (in the range @minus{}32768 to 32767).
2983 Unsigned 14 bit integer (in the range 0 to 16383).
2986 Signed 14 bit integer (in the range @minus{}8192 to 8191).
2992 @item Xstormy16---@file{config/stormy16/stormy16.h}
3007 Registers r0 through r7.
3010 Registers r0 and r1.
3016 Registers r8 and r9.
3019 A constant between 0 and 3 inclusive.
3022 A constant that has exactly one bit set.
3025 A constant that has exactly one bit clear.
3028 A constant between 0 and 255 inclusive.
3031 A constant between @minus{}255 and 0 inclusive.
3034 A constant between @minus{}3 and 0 inclusive.
3037 A constant between 1 and 4 inclusive.
3040 A constant between @minus{}4 and @minus{}1 inclusive.
3043 A memory reference that is a stack push.
3046 A memory reference that is a stack pop.
3049 A memory reference that refers to a constant address of known value.
3052 The register indicated by Rx (not implemented yet).
3055 A constant that is not between 2 and 15 inclusive.
3062 @item Xtensa---@file{config/xtensa/constraints.md}
3065 General-purpose 32-bit register
3068 One-bit boolean register
3071 MAC16 40-bit accumulator register
3074 Signed 12-bit integer constant, for use in MOVI instructions
3077 Signed 8-bit integer constant, for use in ADDI instructions
3080 Integer constant valid for BccI instructions
3083 Unsigned constant valid for BccUI instructions
3090 @node Define Constraints
3091 @subsection Defining Machine-Specific Constraints
3092 @cindex defining constraints
3093 @cindex constraints, defining
3095 Machine-specific constraints fall into two categories: register and
3096 non-register constraints. Within the latter category, constraints
3097 which allow subsets of all possible memory or address operands should
3098 be specially marked, to give @code{reload} more information.
3100 Machine-specific constraints can be given names of arbitrary length,
3101 but they must be entirely composed of letters, digits, underscores
3102 (@samp{_}), and angle brackets (@samp{< >}). Like C identifiers, they
3103 must begin with a letter or underscore.
3105 In order to avoid ambiguity in operand constraint strings, no
3106 constraint can have a name that begins with any other constraint's
3107 name. For example, if @code{x} is defined as a constraint name,
3108 @code{xy} may not be, and vice versa. As a consequence of this rule,
3109 no constraint may begin with one of the generic constraint letters:
3110 @samp{E F V X g i m n o p r s}.
3112 Register constraints correspond directly to register classes.
3113 @xref{Register Classes}. There is thus not much flexibility in their
3116 @deffn {MD Expression} define_register_constraint name regclass docstring
3117 All three arguments are string constants.
3118 @var{name} is the name of the constraint, as it will appear in
3119 @code{match_operand} expressions. If @var{name} is a multi-letter
3120 constraint its length shall be the same for all constraints starting
3121 with the same letter. @var{regclass} can be either the
3122 name of the corresponding register class (@pxref{Register Classes}),
3123 or a C expression which evaluates to the appropriate register class.
3124 If it is an expression, it must have no side effects, and it cannot
3125 look at the operand. The usual use of expressions is to map some
3126 register constraints to @code{NO_REGS} when the register class
3127 is not available on a given subarchitecture.
3129 @var{docstring} is a sentence documenting the meaning of the
3130 constraint. Docstrings are explained further below.
3133 Non-register constraints are more like predicates: the constraint
3134 definition gives a Boolean expression which indicates whether the
3137 @deffn {MD Expression} define_constraint name docstring exp
3138 The @var{name} and @var{docstring} arguments are the same as for
3139 @code{define_register_constraint}, but note that the docstring comes
3140 immediately after the name for these expressions. @var{exp} is an RTL
3141 expression, obeying the same rules as the RTL expressions in predicate
3142 definitions. @xref{Defining Predicates}, for details. If it
3143 evaluates true, the constraint matches; if it evaluates false, it
3144 doesn't. Constraint expressions should indicate which RTL codes they
3145 might match, just like predicate expressions.
3147 @code{match_test} C expressions have access to the
3148 following variables:
3152 The RTL object defining the operand.
3154 The machine mode of @var{op}.
3156 @samp{INTVAL (@var{op})}, if @var{op} is a @code{const_int}.
3158 @samp{CONST_DOUBLE_HIGH (@var{op})}, if @var{op} is an integer
3159 @code{const_double}.
3161 @samp{CONST_DOUBLE_LOW (@var{op})}, if @var{op} is an integer
3162 @code{const_double}.
3164 @samp{CONST_DOUBLE_REAL_VALUE (@var{op})}, if @var{op} is a floating-point
3165 @code{const_double}.
3168 The @var{*val} variables should only be used once another piece of the
3169 expression has verified that @var{op} is the appropriate kind of RTL
3173 Most non-register constraints should be defined with
3174 @code{define_constraint}. The remaining two definition expressions
3175 are only appropriate for constraints that should be handled specially
3176 by @code{reload} if they fail to match.
3178 @deffn {MD Expression} define_memory_constraint name docstring exp
3179 Use this expression for constraints that match a subset of all memory
3180 operands: that is, @code{reload} can make them match by converting the
3181 operand to the form @samp{@w{(mem (reg @var{X}))}}, where @var{X} is a
3182 base register (from the register class specified by
3183 @code{BASE_REG_CLASS}, @pxref{Register Classes}).
3185 For example, on the S/390, some instructions do not accept arbitrary
3186 memory references, but only those that do not make use of an index
3187 register. The constraint letter @samp{Q} is defined to represent a
3188 memory address of this type. If @samp{Q} is defined with
3189 @code{define_memory_constraint}, a @samp{Q} constraint can handle any
3190 memory operand, because @code{reload} knows it can simply copy the
3191 memory address into a base register if required. This is analogous to
3192 the way a @samp{o} constraint can handle any memory operand.
3194 The syntax and semantics are otherwise identical to
3195 @code{define_constraint}.
3198 @deffn {MD Expression} define_address_constraint name docstring exp
3199 Use this expression for constraints that match a subset of all address
3200 operands: that is, @code{reload} can make the constraint match by
3201 converting the operand to the form @samp{@w{(reg @var{X})}}, again
3202 with @var{X} a base register.
3204 Constraints defined with @code{define_address_constraint} can only be
3205 used with the @code{address_operand} predicate, or machine-specific
3206 predicates that work the same way. They are treated analogously to
3207 the generic @samp{p} constraint.
3209 The syntax and semantics are otherwise identical to
3210 @code{define_constraint}.
3213 For historical reasons, names beginning with the letters @samp{G H}
3214 are reserved for constraints that match only @code{const_double}s, and
3215 names beginning with the letters @samp{I J K L M N O P} are reserved
3216 for constraints that match only @code{const_int}s. This may change in
3217 the future. For the time being, constraints with these names must be
3218 written in a stylized form, so that @code{genpreds} can tell you did
3223 (define_constraint "[@var{GHIJKLMNOP}]@dots{}"
3225 (and (match_code "const_int") ; @r{@code{const_double} for G/H}
3226 @var{condition}@dots{})) ; @r{usually a @code{match_test}}
3229 @c the semicolons line up in the formatted manual
3231 It is fine to use names beginning with other letters for constraints
3232 that match @code{const_double}s or @code{const_int}s.
3234 Each docstring in a constraint definition should be one or more complete
3235 sentences, marked up in Texinfo format. @emph{They are currently unused.}
3236 In the future they will be copied into the GCC manual, in @ref{Machine
3237 Constraints}, replacing the hand-maintained tables currently found in
3238 that section. Also, in the future the compiler may use this to give
3239 more helpful diagnostics when poor choice of @code{asm} constraints
3240 causes a reload failure.
3242 If you put the pseudo-Texinfo directive @samp{@@internal} at the
3243 beginning of a docstring, then (in the future) it will appear only in
3244 the internals manual's version of the machine-specific constraint tables.
3245 Use this for constraints that should not appear in @code{asm} statements.
3247 @node C Constraint Interface
3248 @subsection Testing constraints from C
3249 @cindex testing constraints
3250 @cindex constraints, testing
3252 It is occasionally useful to test a constraint from C code rather than
3253 implicitly via the constraint string in a @code{match_operand}. The
3254 generated file @file{tm_p.h} declares a few interfaces for working
3255 with machine-specific constraints. None of these interfaces work with
3256 the generic constraints described in @ref{Simple Constraints}. This
3257 may change in the future.
3259 @strong{Warning:} @file{tm_p.h} may declare other functions that
3260 operate on constraints, besides the ones documented here. Do not use
3261 those functions from machine-dependent code. They exist to implement
3262 the old constraint interface that machine-independent components of
3263 the compiler still expect. They will change or disappear in the
3266 Some valid constraint names are not valid C identifiers, so there is a
3267 mangling scheme for referring to them from C@. Constraint names that
3268 do not contain angle brackets or underscores are left unchanged.
3269 Underscores are doubled, each @samp{<} is replaced with @samp{_l}, and
3270 each @samp{>} with @samp{_g}. Here are some examples:
3272 @c the @c's prevent double blank lines in the printed manual.
3274 @multitable {Original} {Mangled}
3275 @item @strong{Original} @tab @strong{Mangled} @c
3276 @item @code{x} @tab @code{x} @c
3277 @item @code{P42x} @tab @code{P42x} @c
3278 @item @code{P4_x} @tab @code{P4__x} @c
3279 @item @code{P4>x} @tab @code{P4_gx} @c
3280 @item @code{P4>>} @tab @code{P4_g_g} @c
3281 @item @code{P4_g>} @tab @code{P4__g_g} @c
3285 Throughout this section, the variable @var{c} is either a constraint
3286 in the abstract sense, or a constant from @code{enum constraint_num};
3287 the variable @var{m} is a mangled constraint name (usually as part of
3288 a larger identifier).
3290 @deftp Enum constraint_num
3291 For each machine-specific constraint, there is a corresponding
3292 enumeration constant: @samp{CONSTRAINT_} plus the mangled name of the
3293 constraint. Functions that take an @code{enum constraint_num} as an
3294 argument expect one of these constants.
3296 Machine-independent constraints do not have associated constants.
3297 This may change in the future.
3300 @deftypefun {inline bool} satisfies_constraint_@var{m} (rtx @var{exp})
3301 For each machine-specific, non-register constraint @var{m}, there is
3302 one of these functions; it returns @code{true} if @var{exp} satisfies the
3303 constraint. These functions are only visible if @file{rtl.h} was included
3304 before @file{tm_p.h}.
3307 @deftypefun bool constraint_satisfied_p (rtx @var{exp}, enum constraint_num @var{c})
3308 Like the @code{satisfies_constraint_@var{m}} functions, but the
3309 constraint to test is given as an argument, @var{c}. If @var{c}
3310 specifies a register constraint, this function will always return
3314 @deftypefun {enum reg_class} regclass_for_constraint (enum constraint_num @var{c})
3315 Returns the register class associated with @var{c}. If @var{c} is not
3316 a register constraint, or those registers are not available for the
3317 currently selected subtarget, returns @code{NO_REGS}.
3320 Here is an example use of @code{satisfies_constraint_@var{m}}. In
3321 peephole optimizations (@pxref{Peephole Definitions}), operand
3322 constraint strings are ignored, so if there are relevant constraints,
3323 they must be tested in the C condition. In the example, the
3324 optimization is applied if operand 2 does @emph{not} satisfy the
3325 @samp{K} constraint. (This is a simplified version of a peephole
3326 definition from the i386 machine description.)
3330 [(match_scratch:SI 3 "r")
3331 (set (match_operand:SI 0 "register_operand" "")
3332 (mult:SI (match_operand:SI 1 "memory_operand" "")
3333 (match_operand:SI 2 "immediate_operand" "")))]
3335 "!satisfies_constraint_K (operands[2])"
3337 [(set (match_dup 3) (match_dup 1))
3338 (set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))]
3343 @node Standard Names
3344 @section Standard Pattern Names For Generation
3345 @cindex standard pattern names
3346 @cindex pattern names
3347 @cindex names, pattern
3349 Here is a table of the instruction names that are meaningful in the RTL
3350 generation pass of the compiler. Giving one of these names to an
3351 instruction pattern tells the RTL generation pass that it can use the
3352 pattern to accomplish a certain task.
3355 @cindex @code{mov@var{m}} instruction pattern
3356 @item @samp{mov@var{m}}
3357 Here @var{m} stands for a two-letter machine mode name, in lowercase.
3358 This instruction pattern moves data with that machine mode from operand
3359 1 to operand 0. For example, @samp{movsi} moves full-word data.
3361 If operand 0 is a @code{subreg} with mode @var{m} of a register whose
3362 own mode is wider than @var{m}, the effect of this instruction is
3363 to store the specified value in the part of the register that corresponds
3364 to mode @var{m}. Bits outside of @var{m}, but which are within the
3365 same target word as the @code{subreg} are undefined. Bits which are
3366 outside the target word are left unchanged.
3368 This class of patterns is special in several ways. First of all, each
3369 of these names up to and including full word size @emph{must} be defined,
3370 because there is no other way to copy a datum from one place to another.
3371 If there are patterns accepting operands in larger modes,
3372 @samp{mov@var{m}} must be defined for integer modes of those sizes.
3374 Second, these patterns are not used solely in the RTL generation pass.
3375 Even the reload pass can generate move insns to copy values from stack
3376 slots into temporary registers. When it does so, one of the operands is
3377 a hard register and the other is an operand that can need to be reloaded
3381 Therefore, when given such a pair of operands, the pattern must generate
3382 RTL which needs no reloading and needs no temporary registers---no
3383 registers other than the operands. For example, if you support the
3384 pattern with a @code{define_expand}, then in such a case the
3385 @code{define_expand} mustn't call @code{force_reg} or any other such
3386 function which might generate new pseudo registers.
3388 This requirement exists even for subword modes on a RISC machine where
3389 fetching those modes from memory normally requires several insns and
3390 some temporary registers.
3392 @findex change_address
3393 During reload a memory reference with an invalid address may be passed
3394 as an operand. Such an address will be replaced with a valid address
3395 later in the reload pass. In this case, nothing may be done with the
3396 address except to use it as it stands. If it is copied, it will not be
3397 replaced with a valid address. No attempt should be made to make such
3398 an address into a valid address and no routine (such as
3399 @code{change_address}) that will do so may be called. Note that
3400 @code{general_operand} will fail when applied to such an address.
3402 @findex reload_in_progress
3403 The global variable @code{reload_in_progress} (which must be explicitly
3404 declared if required) can be used to determine whether such special
3405 handling is required.
3407 The variety of operands that have reloads depends on the rest of the
3408 machine description, but typically on a RISC machine these can only be
3409 pseudo registers that did not get hard registers, while on other
3410 machines explicit memory references will get optional reloads.
3412 If a scratch register is required to move an object to or from memory,
3413 it can be allocated using @code{gen_reg_rtx} prior to life analysis.
3415 If there are cases which need scratch registers during or after reload,
3416 you must provide an appropriate secondary_reload target hook.
3418 @findex can_create_pseudo_p
3419 The macro @code{can_create_pseudo_p} can be used to determine if it
3420 is unsafe to create new pseudo registers. If this variable is nonzero, then
3421 it is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo.
3423 The constraints on a @samp{mov@var{m}} must permit moving any hard
3424 register to any other hard register provided that
3425 @code{HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and
3426 @code{REGISTER_MOVE_COST} applied to their classes returns a value of 2.
3428 It is obligatory to support floating point @samp{mov@var{m}}
3429 instructions into and out of any registers that can hold fixed point
3430 values, because unions and structures (which have modes @code{SImode} or
3431 @code{DImode}) can be in those registers and they may have floating
3434 There may also be a need to support fixed point @samp{mov@var{m}}
3435 instructions in and out of floating point registers. Unfortunately, I
3436 have forgotten why this was so, and I don't know whether it is still
3437 true. If @code{HARD_REGNO_MODE_OK} rejects fixed point values in
3438 floating point registers, then the constraints of the fixed point
3439 @samp{mov@var{m}} instructions must be designed to avoid ever trying to
3440 reload into a floating point register.
3442 @cindex @code{reload_in} instruction pattern
3443 @cindex @code{reload_out} instruction pattern
3444 @item @samp{reload_in@var{m}}
3445 @itemx @samp{reload_out@var{m}}
3446 These named patterns have been obsoleted by the target hook
3447 @code{secondary_reload}.
3449 Like @samp{mov@var{m}}, but used when a scratch register is required to
3450 move between operand 0 and operand 1. Operand 2 describes the scratch
3451 register. See the discussion of the @code{SECONDARY_RELOAD_CLASS}
3452 macro in @pxref{Register Classes}.
3454 There are special restrictions on the form of the @code{match_operand}s
3455 used in these patterns. First, only the predicate for the reload
3456 operand is examined, i.e., @code{reload_in} examines operand 1, but not
3457 the predicates for operand 0 or 2. Second, there may be only one
3458 alternative in the constraints. Third, only a single register class
3459 letter may be used for the constraint; subsequent constraint letters
3460 are ignored. As a special exception, an empty constraint string
3461 matches the @code{ALL_REGS} register class. This may relieve ports
3462 of the burden of defining an @code{ALL_REGS} constraint letter just
3465 @cindex @code{movstrict@var{m}} instruction pattern
3466 @item @samp{movstrict@var{m}}
3467 Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg}
3468 with mode @var{m} of a register whose natural mode is wider,
3469 the @samp{movstrict@var{m}} instruction is guaranteed not to alter
3470 any of the register except the part which belongs to mode @var{m}.
3472 @cindex @code{movmisalign@var{m}} instruction pattern
3473 @item @samp{movmisalign@var{m}}
3474 This variant of a move pattern is designed to load or store a value
3475 from a memory address that is not naturally aligned for its mode.
3476 For a store, the memory will be in operand 0; for a load, the memory
3477 will be in operand 1. The other operand is guaranteed not to be a
3478 memory, so that it's easy to tell whether this is a load or store.
3480 This pattern is used by the autovectorizer, and when expanding a
3481 @code{MISALIGNED_INDIRECT_REF} expression.
3483 @cindex @code{load_multiple} instruction pattern
3484 @item @samp{load_multiple}
3485 Load several consecutive memory locations into consecutive registers.
3486 Operand 0 is the first of the consecutive registers, operand 1
3487 is the first memory location, and operand 2 is a constant: the
3488 number of consecutive registers.
3490 Define this only if the target machine really has such an instruction;
3491 do not define this if the most efficient way of loading consecutive
3492 registers from memory is to do them one at a time.
3494 On some machines, there are restrictions as to which consecutive
3495 registers can be stored into memory, such as particular starting or
3496 ending register numbers or only a range of valid counts. For those
3497 machines, use a @code{define_expand} (@pxref{Expander Definitions})
3498 and make the pattern fail if the restrictions are not met.
3500 Write the generated insn as a @code{parallel} with elements being a
3501 @code{set} of one register from the appropriate memory location (you may
3502 also need @code{use} or @code{clobber} elements). Use a
3503 @code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See
3504 @file{rs6000.md} for examples of the use of this insn pattern.
3506 @cindex @samp{store_multiple} instruction pattern
3507 @item @samp{store_multiple}
3508 Similar to @samp{load_multiple}, but store several consecutive registers
3509 into consecutive memory locations. Operand 0 is the first of the
3510 consecutive memory locations, operand 1 is the first register, and
3511 operand 2 is a constant: the number of consecutive registers.
3513 @cindex @code{vec_set@var{m}} instruction pattern
3514 @item @samp{vec_set@var{m}}
3515 Set given field in the vector value. Operand 0 is the vector to modify,
3516 operand 1 is new value of field and operand 2 specify the field index.
3518 @cindex @code{vec_extract@var{m}} instruction pattern
3519 @item @samp{vec_extract@var{m}}
3520 Extract given field from the vector value. Operand 1 is the vector, operand 2
3521 specify field index and operand 0 place to store value into.
3523 @cindex @code{vec_extract_even@var{m}} instruction pattern
3524 @item @samp{vec_extract_even@var{m}}
3525 Extract even elements from the input vectors (operand 1 and operand 2).
3526 The even elements of operand 2 are concatenated to the even elements of operand
3527 1 in their original order. The result is stored in operand 0.
3528 The output and input vectors should have the same modes.
3530 @cindex @code{vec_extract_odd@var{m}} instruction pattern
3531 @item @samp{vec_extract_odd@var{m}}
3532 Extract odd elements from the input vectors (operand 1 and operand 2).
3533 The odd elements of operand 2 are concatenated to the odd elements of operand
3534 1 in their original order. The result is stored in operand 0.
3535 The output and input vectors should have the same modes.
3537 @cindex @code{vec_interleave_high@var{m}} instruction pattern
3538 @item @samp{vec_interleave_high@var{m}}
3539 Merge high elements of the two input vectors into the output vector. The output
3540 and input vectors should have the same modes (@code{N} elements). The high
3541 @code{N/2} elements of the first input vector are interleaved with the high
3542 @code{N/2} elements of the second input vector.
3544 @cindex @code{vec_interleave_low@var{m}} instruction pattern
3545 @item @samp{vec_interleave_low@var{m}}
3546 Merge low elements of the two input vectors into the output vector. The output
3547 and input vectors should have the same modes (@code{N} elements). The low
3548 @code{N/2} elements of the first input vector are interleaved with the low
3549 @code{N/2} elements of the second input vector.
3551 @cindex @code{vec_init@var{m}} instruction pattern
3552 @item @samp{vec_init@var{m}}
3553 Initialize the vector to given values. Operand 0 is the vector to initialize
3554 and operand 1 is parallel containing values for individual fields.
3556 @cindex @code{push@var{m}1} instruction pattern
3557 @item @samp{push@var{m}1}
3558 Output a push instruction. Operand 0 is value to push. Used only when
3559 @code{PUSH_ROUNDING} is defined. For historical reason, this pattern may be
3560 missing and in such case an @code{mov} expander is used instead, with a
3561 @code{MEM} expression forming the push operation. The @code{mov} expander
3562 method is deprecated.
3564 @cindex @code{add@var{m}3} instruction pattern
3565 @item @samp{add@var{m}3}
3566 Add operand 2 and operand 1, storing the result in operand 0. All operands
3567 must have mode @var{m}. This can be used even on two-address machines, by
3568 means of constraints requiring operands 1 and 0 to be the same location.
3570 @cindex @code{ssadd@var{m}3} instruction pattern
3571 @cindex @code{usadd@var{m}3} instruction pattern
3572 @cindex @code{sub@var{m}3} instruction pattern
3573 @cindex @code{sssub@var{m}3} instruction pattern
3574 @cindex @code{ussub@var{m}3} instruction pattern
3575 @cindex @code{mul@var{m}3} instruction pattern
3576 @cindex @code{ssmul@var{m}3} instruction pattern
3577 @cindex @code{usmul@var{m}3} instruction pattern
3578 @cindex @code{div@var{m}3} instruction pattern
3579 @cindex @code{ssdiv@var{m}3} instruction pattern
3580 @cindex @code{udiv@var{m}3} instruction pattern
3581 @cindex @code{usdiv@var{m}3} instruction pattern
3582 @cindex @code{mod@var{m}3} instruction pattern
3583 @cindex @code{umod@var{m}3} instruction pattern
3584 @cindex @code{umin@var{m}3} instruction pattern
3585 @cindex @code{umax@var{m}3} instruction pattern
3586 @cindex @code{and@var{m}3} instruction pattern
3587 @cindex @code{ior@var{m}3} instruction pattern
3588 @cindex @code{xor@var{m}3} instruction pattern
3589 @item @samp{ssadd@var{m}3}, @samp{usadd@var{m}3}
3590 @item @samp{sub@var{m}3}, @samp{sssub@var{m}3}, @samp{ussub@var{m}3}
3591 @item @samp{mul@var{m}3}, @samp{ssmul@var{m}3}, @samp{usmul@var{m}3}
3592 @itemx @samp{div@var{m}3}, @samp{ssdiv@var{m}3}
3593 @itemx @samp{udiv@var{m}3}, @samp{usdiv@var{m}3}
3594 @itemx @samp{mod@var{m}3}, @samp{umod@var{m}3}
3595 @itemx @samp{umin@var{m}3}, @samp{umax@var{m}3}
3596 @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3}
3597 Similar, for other arithmetic operations.
3599 @cindex @code{min@var{m}3} instruction pattern
3600 @cindex @code{max@var{m}3} instruction pattern
3601 @item @samp{smin@var{m}3}, @samp{smax@var{m}3}
3602 Signed minimum and maximum operations. When used with floating point,
3603 if both operands are zeros, or if either operand is @code{NaN}, then
3604 it is unspecified which of the two operands is returned as the result.
3606 @cindex @code{reduc_smin_@var{m}} instruction pattern
3607 @cindex @code{reduc_smax_@var{m}} instruction pattern
3608 @item @samp{reduc_smin_@var{m}}, @samp{reduc_smax_@var{m}}
3609 Find the signed minimum/maximum of the elements of a vector. The vector is
3610 operand 1, and the scalar result is stored in the least significant bits of
3611 operand 0 (also a vector). The output and input vector should have the same
3614 @cindex @code{reduc_umin_@var{m}} instruction pattern
3615 @cindex @code{reduc_umax_@var{m}} instruction pattern
3616 @item @samp{reduc_umin_@var{m}}, @samp{reduc_umax_@var{m}}
3617 Find the unsigned minimum/maximum of the elements of a vector. The vector is
3618 operand 1, and the scalar result is stored in the least significant bits of
3619 operand 0 (also a vector). The output and input vector should have the same
3622 @cindex @code{reduc_splus_@var{m}} instruction pattern
3623 @item @samp{reduc_splus_@var{m}}
3624 Compute the sum of the signed elements of a vector. The vector is operand 1,
3625 and the scalar result is stored in the least significant bits of operand 0
3626 (also a vector). The output and input vector should have the same modes.
3628 @cindex @code{reduc_uplus_@var{m}} instruction pattern
3629 @item @samp{reduc_uplus_@var{m}}
3630 Compute the sum of the unsigned elements of a vector. The vector is operand 1,
3631 and the scalar result is stored in the least significant bits of operand 0
3632 (also a vector). The output and input vector should have the same modes.
3634 @cindex @code{sdot_prod@var{m}} instruction pattern
3635 @item @samp{sdot_prod@var{m}}
3636 @cindex @code{udot_prod@var{m}} instruction pattern
3637 @item @samp{udot_prod@var{m}}
3638 Compute the sum of the products of two signed/unsigned elements.
3639 Operand 1 and operand 2 are of the same mode. Their product, which is of a
3640 wider mode, is computed and added to operand 3. Operand 3 is of a mode equal or
3641 wider than the mode of the product. The result is placed in operand 0, which
3642 is of the same mode as operand 3.
3644 @cindex @code{ssum_widen@var{m3}} instruction pattern
3645 @item @samp{ssum_widen@var{m3}}
3646 @cindex @code{usum_widen@var{m3}} instruction pattern
3647 @item @samp{usum_widen@var{m3}}
3648 Operands 0 and 2 are of the same mode, which is wider than the mode of
3649 operand 1. Add operand 1 to operand 2 and place the widened result in
3650 operand 0. (This is used express accumulation of elements into an accumulator
3653 @cindex @code{vec_shl_@var{m}} instruction pattern
3654 @cindex @code{vec_shr_@var{m}} instruction pattern
3655 @item @samp{vec_shl_@var{m}}, @samp{vec_shr_@var{m}}
3656 Whole vector left/right shift in bits.
3657 Operand 1 is a vector to be shifted.
3658 Operand 2 is an integer shift amount in bits.
3659 Operand 0 is where the resulting shifted vector is stored.
3660 The output and input vectors should have the same modes.
3662 @cindex @code{vec_pack_trunc_@var{m}} instruction pattern
3663 @item @samp{vec_pack_trunc_@var{m}}
3664 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
3665 are vectors of the same mode having N integral or floating point elements
3666 of size S. Operand 0 is the resulting vector in which 2*N elements of
3667 size N/2 are concatenated after narrowing them down using truncation.
3669 @cindex @code{vec_pack_ssat_@var{m}} instruction pattern
3670 @cindex @code{vec_pack_usat_@var{m}} instruction pattern
3671 @item @samp{vec_pack_ssat_@var{m}}, @samp{vec_pack_usat_@var{m}}
3672 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
3673 are vectors of the same mode having N integral elements of size S.
3674 Operand 0 is the resulting vector in which the elements of the two input
3675 vectors are concatenated after narrowing them down using signed/unsigned
3676 saturating arithmetic.
3678 @cindex @code{vec_pack_sfix_trunc_@var{m}} instruction pattern
3679 @cindex @code{vec_pack_ufix_trunc_@var{m}} instruction pattern
3680 @item @samp{vec_pack_sfix_trunc_@var{m}}, @samp{vec_pack_ufix_trunc_@var{m}}
3681 Narrow, convert to signed/unsigned integral type and merge the elements
3682 of two vectors. Operands 1 and 2 are vectors of the same mode having N
3683 floating point elements of size S. Operand 0 is the resulting vector
3684 in which 2*N elements of size N/2 are concatenated.
3686 @cindex @code{vec_unpacks_hi_@var{m}} instruction pattern
3687 @cindex @code{vec_unpacks_lo_@var{m}} instruction pattern
3688 @item @samp{vec_unpacks_hi_@var{m}}, @samp{vec_unpacks_lo_@var{m}}
3689 Extract and widen (promote) the high/low part of a vector of signed
3690 integral or floating point elements. The input vector (operand 1) has N
3691 elements of size S. Widen (promote) the high/low elements of the vector
3692 using signed or floating point extension and place the resulting N/2
3693 values of size 2*S in the output vector (operand 0).
3695 @cindex @code{vec_unpacku_hi_@var{m}} instruction pattern
3696 @cindex @code{vec_unpacku_lo_@var{m}} instruction pattern
3697 @item @samp{vec_unpacku_hi_@var{m}}, @samp{vec_unpacku_lo_@var{m}}
3698 Extract and widen (promote) the high/low part of a vector of unsigned
3699 integral elements. The input vector (operand 1) has N elements of size S.
3700 Widen (promote) the high/low elements of the vector using zero extension and
3701 place the resulting N/2 values of size 2*S in the output vector (operand 0).
3703 @cindex @code{vec_unpacks_float_hi_@var{m}} instruction pattern
3704 @cindex @code{vec_unpacks_float_lo_@var{m}} instruction pattern
3705 @cindex @code{vec_unpacku_float_hi_@var{m}} instruction pattern
3706 @cindex @code{vec_unpacku_float_lo_@var{m}} instruction pattern
3707 @item @samp{vec_unpacks_float_hi_@var{m}}, @samp{vec_unpacks_float_lo_@var{m}}
3708 @itemx @samp{vec_unpacku_float_hi_@var{m}}, @samp{vec_unpacku_float_lo_@var{m}}
3709 Extract, convert to floating point type and widen the high/low part of a
3710 vector of signed/unsigned integral elements. The input vector (operand 1)
3711 has N elements of size S. Convert the high/low elements of the vector using
3712 floating point conversion and place the resulting N/2 values of size 2*S in
3713 the output vector (operand 0).
3715 @cindex @code{vec_widen_umult_hi_@var{m}} instruction pattern
3716 @cindex @code{vec_widen_umult_lo__@var{m}} instruction pattern
3717 @cindex @code{vec_widen_smult_hi_@var{m}} instruction pattern
3718 @cindex @code{vec_widen_smult_lo_@var{m}} instruction pattern
3719 @item @samp{vec_widen_umult_hi_@var{m}}, @samp{vec_widen_umult_lo_@var{m}}
3720 @itemx @samp{vec_widen_smult_hi_@var{m}}, @samp{vec_widen_smult_lo_@var{m}}
3721 Signed/Unsigned widening multiplication. The two inputs (operands 1 and 2)
3722 are vectors with N signed/unsigned elements of size S. Multiply the high/low
3723 elements of the two vectors, and put the N/2 products of size 2*S in the
3724 output vector (operand 0).
3726 @cindex @code{mulhisi3} instruction pattern
3727 @item @samp{mulhisi3}
3728 Multiply operands 1 and 2, which have mode @code{HImode}, and store
3729 a @code{SImode} product in operand 0.
3731 @cindex @code{mulqihi3} instruction pattern
3732 @cindex @code{mulsidi3} instruction pattern
3733 @item @samp{mulqihi3}, @samp{mulsidi3}
3734 Similar widening-multiplication instructions of other widths.
3736 @cindex @code{umulqihi3} instruction pattern
3737 @cindex @code{umulhisi3} instruction pattern
3738 @cindex @code{umulsidi3} instruction pattern
3739 @item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3}
3740 Similar widening-multiplication instructions that do unsigned
3743 @cindex @code{usmulqihi3} instruction pattern
3744 @cindex @code{usmulhisi3} instruction pattern
3745 @cindex @code{usmulsidi3} instruction pattern
3746 @item @samp{usmulqihi3}, @samp{usmulhisi3}, @samp{usmulsidi3}
3747 Similar widening-multiplication instructions that interpret the first
3748 operand as unsigned and the second operand as signed, then do a signed
3751 @cindex @code{smul@var{m}3_highpart} instruction pattern
3752 @item @samp{smul@var{m}3_highpart}
3753 Perform a signed multiplication of operands 1 and 2, which have mode
3754 @var{m}, and store the most significant half of the product in operand 0.
3755 The least significant half of the product is discarded.
3757 @cindex @code{umul@var{m}3_highpart} instruction pattern
3758 @item @samp{umul@var{m}3_highpart}
3759 Similar, but the multiplication is unsigned.
3761 @cindex @code{madd@var{m}@var{n}4} instruction pattern
3762 @item @samp{madd@var{m}@var{n}4}
3763 Multiply operands 1 and 2, sign-extend them to mode @var{n}, add
3764 operand 3, and store the result in operand 0. Operands 1 and 2
3765 have mode @var{m} and operands 0 and 3 have mode @var{n}.
3766 Both modes must be integer or fixed-point modes and @var{n} must be twice
3767 the size of @var{m}.
3769 In other words, @code{madd@var{m}@var{n}4} is like
3770 @code{mul@var{m}@var{n}3} except that it also adds operand 3.
3772 These instructions are not allowed to @code{FAIL}.
3774 @cindex @code{umadd@var{m}@var{n}4} instruction pattern
3775 @item @samp{umadd@var{m}@var{n}4}
3776 Like @code{madd@var{m}@var{n}4}, but zero-extend the multiplication
3777 operands instead of sign-extending them.
3779 @cindex @code{ssmadd@var{m}@var{n}4} instruction pattern
3780 @item @samp{ssmadd@var{m}@var{n}4}
3781 Like @code{madd@var{m}@var{n}4}, but all involved operations must be
3784 @cindex @code{usmadd@var{m}@var{n}4} instruction pattern
3785 @item @samp{usmadd@var{m}@var{n}4}
3786 Like @code{umadd@var{m}@var{n}4}, but all involved operations must be
3787 unsigned-saturating.
3789 @cindex @code{msub@var{m}@var{n}4} instruction pattern
3790 @item @samp{msub@var{m}@var{n}4}
3791 Multiply operands 1 and 2, sign-extend them to mode @var{n}, subtract the
3792 result from operand 3, and store the result in operand 0. Operands 1 and 2
3793 have mode @var{m} and operands 0 and 3 have mode @var{n}.
3794 Both modes must be integer or fixed-point modes and @var{n} must be twice
3795 the size of @var{m}.
3797 In other words, @code{msub@var{m}@var{n}4} is like
3798 @code{mul@var{m}@var{n}3} except that it also subtracts the result
3801 These instructions are not allowed to @code{FAIL}.
3803 @cindex @code{umsub@var{m}@var{n}4} instruction pattern
3804 @item @samp{umsub@var{m}@var{n}4}
3805 Like @code{msub@var{m}@var{n}4}, but zero-extend the multiplication
3806 operands instead of sign-extending them.
3808 @cindex @code{ssmsub@var{m}@var{n}4} instruction pattern
3809 @item @samp{ssmsub@var{m}@var{n}4}
3810 Like @code{msub@var{m}@var{n}4}, but all involved operations must be
3813 @cindex @code{usmsub@var{m}@var{n}4} instruction pattern
3814 @item @samp{usmsub@var{m}@var{n}4}
3815 Like @code{umsub@var{m}@var{n}4}, but all involved operations must be
3816 unsigned-saturating.
3818 @cindex @code{divmod@var{m}4} instruction pattern
3819 @item @samp{divmod@var{m}4}
3820 Signed division that produces both a quotient and a remainder.
3821 Operand 1 is divided by operand 2 to produce a quotient stored
3822 in operand 0 and a remainder stored in operand 3.
3824 For machines with an instruction that produces both a quotient and a
3825 remainder, provide a pattern for @samp{divmod@var{m}4} but do not
3826 provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This
3827 allows optimization in the relatively common case when both the quotient
3828 and remainder are computed.
3830 If an instruction that just produces a quotient or just a remainder
3831 exists and is more efficient than the instruction that produces both,
3832 write the output routine of @samp{divmod@var{m}4} to call
3833 @code{find_reg_note} and look for a @code{REG_UNUSED} note on the
3834 quotient or remainder and generate the appropriate instruction.
3836 @cindex @code{udivmod@var{m}4} instruction pattern
3837 @item @samp{udivmod@var{m}4}
3838 Similar, but does unsigned division.
3840 @anchor{shift patterns}
3841 @cindex @code{ashl@var{m}3} instruction pattern
3842 @cindex @code{ssashl@var{m}3} instruction pattern
3843 @cindex @code{usashl@var{m}3} instruction pattern
3844 @item @samp{ashl@var{m}3}, @samp{ssashl@var{m}3}, @samp{usashl@var{m}3}
3845 Arithmetic-shift operand 1 left by a number of bits specified by operand
3846 2, and store the result in operand 0. Here @var{m} is the mode of
3847 operand 0 and operand 1; operand 2's mode is specified by the
3848 instruction pattern, and the compiler will convert the operand to that
3849 mode before generating the instruction. The meaning of out-of-range shift
3850 counts can optionally be specified by @code{TARGET_SHIFT_TRUNCATION_MASK}.
3851 @xref{TARGET_SHIFT_TRUNCATION_MASK}.
3853 @cindex @code{ashr@var{m}3} instruction pattern
3854 @cindex @code{lshr@var{m}3} instruction pattern
3855 @cindex @code{rotl@var{m}3} instruction pattern
3856 @cindex @code{rotr@var{m}3} instruction pattern
3857 @item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3}
3858 Other shift and rotate instructions, analogous to the
3859 @code{ashl@var{m}3} instructions.
3861 @cindex @code{neg@var{m}2} instruction pattern
3862 @cindex @code{ssneg@var{m}2} instruction pattern
3863 @cindex @code{usneg@var{m}2} instruction pattern
3864 @item @samp{neg@var{m}2}, @samp{ssneg@var{m}2}, @samp{usneg@var{m}2}
3865 Negate operand 1 and store the result in operand 0.
3867 @cindex @code{abs@var{m}2} instruction pattern
3868 @item @samp{abs@var{m}2}
3869 Store the absolute value of operand 1 into operand 0.
3871 @cindex @code{sqrt@var{m}2} instruction pattern
3872 @item @samp{sqrt@var{m}2}
3873 Store the square root of operand 1 into operand 0.
3875 The @code{sqrt} built-in function of C always uses the mode which
3876 corresponds to the C data type @code{double} and the @code{sqrtf}
3877 built-in function uses the mode which corresponds to the C data
3880 @cindex @code{fmod@var{m}3} instruction pattern
3881 @item @samp{fmod@var{m}3}
3882 Store the remainder of dividing operand 1 by operand 2 into
3883 operand 0, rounded towards zero to an integer.
3885 The @code{fmod} built-in function of C always uses the mode which
3886 corresponds to the C data type @code{double} and the @code{fmodf}
3887 built-in function uses the mode which corresponds to the C data
3890 @cindex @code{remainder@var{m}3} instruction pattern
3891 @item @samp{remainder@var{m}3}
3892 Store the remainder of dividing operand 1 by operand 2 into
3893 operand 0, rounded to the nearest integer.
3895 The @code{remainder} built-in function of C always uses the mode
3896 which corresponds to the C data type @code{double} and the
3897 @code{remainderf} built-in function uses the mode which corresponds
3898 to the C data type @code{float}.
3900 @cindex @code{cos@var{m}2} instruction pattern
3901 @item @samp{cos@var{m}2}
3902 Store the cosine of operand 1 into operand 0.
3904 The @code{cos} built-in function of C always uses the mode which
3905 corresponds to the C data type @code{double} and the @code{cosf}
3906 built-in function uses the mode which corresponds to the C data
3909 @cindex @code{sin@var{m}2} instruction pattern
3910 @item @samp{sin@var{m}2}
3911 Store the sine of operand 1 into operand 0.
3913 The @code{sin} built-in function of C always uses the mode which
3914 corresponds to the C data type @code{double} and the @code{sinf}
3915 built-in function uses the mode which corresponds to the C data
3918 @cindex @code{exp@var{m}2} instruction pattern
3919 @item @samp{exp@var{m}2}
3920 Store the exponential of operand 1 into operand 0.
3922 The @code{exp} built-in function of C always uses the mode which
3923 corresponds to the C data type @code{double} and the @code{expf}
3924 built-in function uses the mode which corresponds to the C data
3927 @cindex @code{log@var{m}2} instruction pattern
3928 @item @samp{log@var{m}2}
3929 Store the natural logarithm of operand 1 into operand 0.
3931 The @code{log} built-in function of C always uses the mode which
3932 corresponds to the C data type @code{double} and the @code{logf}
3933 built-in function uses the mode which corresponds to the C data
3936 @cindex @code{pow@var{m}3} instruction pattern
3937 @item @samp{pow@var{m}3}
3938 Store the value of operand 1 raised to the exponent operand 2
3941 The @code{pow} built-in function of C always uses the mode which
3942 corresponds to the C data type @code{double} and the @code{powf}
3943 built-in function uses the mode which corresponds to the C data
3946 @cindex @code{atan2@var{m}3} instruction pattern
3947 @item @samp{atan2@var{m}3}
3948 Store the arc tangent (inverse tangent) of operand 1 divided by
3949 operand 2 into operand 0, using the signs of both arguments to
3950 determine the quadrant of the result.
3952 The @code{atan2} built-in function of C always uses the mode which
3953 corresponds to the C data type @code{double} and the @code{atan2f}
3954 built-in function uses the mode which corresponds to the C data
3957 @cindex @code{floor@var{m}2} instruction pattern
3958 @item @samp{floor@var{m}2}
3959 Store the largest integral value not greater than argument.
3961 The @code{floor} built-in function of C always uses the mode which
3962 corresponds to the C data type @code{double} and the @code{floorf}
3963 built-in function uses the mode which corresponds to the C data
3966 @cindex @code{btrunc@var{m}2} instruction pattern
3967 @item @samp{btrunc@var{m}2}
3968 Store the argument rounded to integer towards zero.
3970 The @code{trunc} built-in function of C always uses the mode which
3971 corresponds to the C data type @code{double} and the @code{truncf}
3972 built-in function uses the mode which corresponds to the C data
3975 @cindex @code{round@var{m}2} instruction pattern
3976 @item @samp{round@var{m}2}
3977 Store the argument rounded to integer away from zero.
3979 The @code{round} built-in function of C always uses the mode which
3980 corresponds to the C data type @code{double} and the @code{roundf}
3981 built-in function uses the mode which corresponds to the C data
3984 @cindex @code{ceil@var{m}2} instruction pattern
3985 @item @samp{ceil@var{m}2}
3986 Store the argument rounded to integer away from zero.
3988 The @code{ceil} built-in function of C always uses the mode which
3989 corresponds to the C data type @code{double} and the @code{ceilf}
3990 built-in function uses the mode which corresponds to the C data
3993 @cindex @code{nearbyint@var{m}2} instruction pattern
3994 @item @samp{nearbyint@var{m}2}
3995 Store the argument rounded according to the default rounding mode
3997 The @code{nearbyint} built-in function of C always uses the mode which
3998 corresponds to the C data type @code{double} and the @code{nearbyintf}
3999 built-in function uses the mode which corresponds to the C data
4002 @cindex @code{rint@var{m}2} instruction pattern
4003 @item @samp{rint@var{m}2}
4004 Store the argument rounded according to the default rounding mode and
4005 raise the inexact exception when the result differs in value from
4008 The @code{rint} built-in function of C always uses the mode which
4009 corresponds to the C data type @code{double} and the @code{rintf}
4010 built-in function uses the mode which corresponds to the C data
4013 @cindex @code{lrint@var{m}@var{n}2}
4014 @item @samp{lrint@var{m}@var{n}2}
4015 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4016 point mode @var{n} as a signed number according to the current
4017 rounding mode and store in operand 0 (which has mode @var{n}).
4019 @cindex @code{lround@var{m}@var{n}2}
4020 @item @samp{lround@var{m}2}
4021 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4022 point mode @var{n} as a signed number rounding to nearest and away
4023 from zero and store in operand 0 (which has mode @var{n}).
4025 @cindex @code{lfloor@var{m}@var{n}2}
4026 @item @samp{lfloor@var{m}2}
4027 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4028 point mode @var{n} as a signed number rounding down and store in
4029 operand 0 (which has mode @var{n}).
4031 @cindex @code{lceil@var{m}@var{n}2}
4032 @item @samp{lceil@var{m}2}
4033 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4034 point mode @var{n} as a signed number rounding up and store in
4035 operand 0 (which has mode @var{n}).
4037 @cindex @code{copysign@var{m}3} instruction pattern
4038 @item @samp{copysign@var{m}3}
4039 Store a value with the magnitude of operand 1 and the sign of operand
4042 The @code{copysign} built-in function of C always uses the mode which
4043 corresponds to the C data type @code{double} and the @code{copysignf}
4044 built-in function uses the mode which corresponds to the C data
4047 @cindex @code{ffs@var{m}2} instruction pattern
4048 @item @samp{ffs@var{m}2}
4049 Store into operand 0 one plus the index of the least significant 1-bit
4050 of operand 1. If operand 1 is zero, store zero. @var{m} is the mode
4051 of operand 0; operand 1's mode is specified by the instruction
4052 pattern, and the compiler will convert the operand to that mode before
4053 generating the instruction.
4055 The @code{ffs} built-in function of C always uses the mode which
4056 corresponds to the C data type @code{int}.
4058 @cindex @code{clz@var{m}2} instruction pattern
4059 @item @samp{clz@var{m}2}
4060 Store into operand 0 the number of leading 0-bits in @var{x}, starting
4061 at the most significant bit position. If @var{x} is 0, the result is
4062 undefined. @var{m} is the mode of operand 0; operand 1's mode is
4063 specified by the instruction pattern, and the compiler will convert the
4064 operand to that mode before generating the instruction.
4066 @cindex @code{ctz@var{m}2} instruction pattern
4067 @item @samp{ctz@var{m}2}
4068 Store into operand 0 the number of trailing 0-bits in @var{x}, starting
4069 at the least significant bit position. If @var{x} is 0, the result is
4070 undefined. @var{m} is the mode of operand 0; operand 1's mode is
4071 specified by the instruction pattern, and the compiler will convert the
4072 operand to that mode before generating the instruction.
4074 @cindex @code{popcount@var{m}2} instruction pattern
4075 @item @samp{popcount@var{m}2}
4076 Store into operand 0 the number of 1-bits in @var{x}. @var{m} is the
4077 mode of operand 0; operand 1's mode is specified by the instruction
4078 pattern, and the compiler will convert the operand to that mode before
4079 generating the instruction.
4081 @cindex @code{parity@var{m}2} instruction pattern
4082 @item @samp{parity@var{m}2}
4083 Store into operand 0 the parity of @var{x}, i.e.@: the number of 1-bits
4084 in @var{x} modulo 2. @var{m} is the mode of operand 0; operand 1's mode
4085 is specified by the instruction pattern, and the compiler will convert
4086 the operand to that mode before generating the instruction.
4088 @cindex @code{one_cmpl@var{m}2} instruction pattern
4089 @item @samp{one_cmpl@var{m}2}
4090 Store the bitwise-complement of operand 1 into operand 0.
4092 @cindex @code{cmp@var{m}} instruction pattern
4093 @item @samp{cmp@var{m}}
4094 Compare operand 0 and operand 1, and set the condition codes.
4095 The RTL pattern should look like this:
4098 (set (cc0) (compare (match_operand:@var{m} 0 @dots{})
4099 (match_operand:@var{m} 1 @dots{})))
4102 @cindex @code{tst@var{m}} instruction pattern
4103 @item @samp{tst@var{m}}
4104 Compare operand 0 against zero, and set the condition codes.
4105 The RTL pattern should look like this:
4108 (set (cc0) (match_operand:@var{m} 0 @dots{}))
4111 @samp{tst@var{m}} patterns should not be defined for machines that do
4112 not use @code{(cc0)}. Doing so would confuse the optimizer since it
4113 would no longer be clear which @code{set} operations were comparisons.
4114 The @samp{cmp@var{m}} patterns should be used instead.
4116 @cindex @code{movmem@var{m}} instruction pattern
4117 @item @samp{movmem@var{m}}
4118 Block move instruction. The destination and source blocks of memory
4119 are the first two operands, and both are @code{mem:BLK}s with an
4120 address in mode @code{Pmode}.
4122 The number of bytes to move is the third operand, in mode @var{m}.
4123 Usually, you specify @code{word_mode} for @var{m}. However, if you can
4124 generate better code knowing the range of valid lengths is smaller than
4125 those representable in a full word, you should provide a pattern with a
4126 mode corresponding to the range of values you can handle efficiently
4127 (e.g., @code{QImode} for values in the range 0--127; note we avoid numbers
4128 that appear negative) and also a pattern with @code{word_mode}.
4130 The fourth operand is the known shared alignment of the source and
4131 destination, in the form of a @code{const_int} rtx. Thus, if the
4132 compiler knows that both source and destination are word-aligned,
4133 it may provide the value 4 for this operand.
4135 Optional operands 5 and 6 specify expected alignment and size of block
4136 respectively. The expected alignment differs from alignment in operand 4
4137 in a way that the blocks are not required to be aligned according to it in
4138 all cases. Expected size, when unknown, is set to @code{(const_int -1)}.
4140 Descriptions of multiple @code{movmem@var{m}} patterns can only be
4141 beneficial if the patterns for smaller modes have fewer restrictions
4142 on their first, second and fourth operands. Note that the mode @var{m}
4143 in @code{movmem@var{m}} does not impose any restriction on the mode of
4144 individually moved data units in the block.
4146 These patterns need not give special consideration to the possibility
4147 that the source and destination strings might overlap.
4149 @cindex @code{movstr} instruction pattern
4151 String copy instruction, with @code{stpcpy} semantics. Operand 0 is
4152 an output operand in mode @code{Pmode}. The addresses of the
4153 destination and source strings are operands 1 and 2, and both are
4154 @code{mem:BLK}s with addresses in mode @code{Pmode}. The execution of
4155 the expansion of this pattern should store in operand 0 the address in
4156 which the @code{NUL} terminator was stored in the destination string.
4158 @cindex @code{setmem@var{m}} instruction pattern
4159 @item @samp{setmem@var{m}}
4160 Block set instruction. The destination string is the first operand,
4161 given as a @code{mem:BLK} whose address is in mode @code{Pmode}. The
4162 number of bytes to set is the second operand, in mode @var{m}. The value to
4163 initialize the memory with is the third operand. Targets that only support the
4164 clearing of memory should reject any value that is not the constant 0. See
4165 @samp{movmem@var{m}} for a discussion of the choice of mode.
4167 The fourth operand is the known alignment of the destination, in the form
4168 of a @code{const_int} rtx. Thus, if the compiler knows that the
4169 destination is word-aligned, it may provide the value 4 for this
4172 Optional operands 5 and 6 specify expected alignment and size of block
4173 respectively. The expected alignment differs from alignment in operand 4
4174 in a way that the blocks are not required to be aligned according to it in
4175 all cases. Expected size, when unknown, is set to @code{(const_int -1)}.
4177 The use for multiple @code{setmem@var{m}} is as for @code{movmem@var{m}}.
4179 @cindex @code{cmpstrn@var{m}} instruction pattern
4180 @item @samp{cmpstrn@var{m}}
4181 String compare instruction, with five operands. Operand 0 is the output;
4182 it has mode @var{m}. The remaining four operands are like the operands
4183 of @samp{movmem@var{m}}. The two memory blocks specified are compared
4184 byte by byte in lexicographic order starting at the beginning of each
4185 string. The instruction is not allowed to prefetch more than one byte
4186 at a time since either string may end in the first byte and reading past
4187 that may access an invalid page or segment and cause a fault. The
4188 effect of the instruction is to store a value in operand 0 whose sign
4189 indicates the result of the comparison.
4191 @cindex @code{cmpstr@var{m}} instruction pattern
4192 @item @samp{cmpstr@var{m}}
4193 String compare instruction, without known maximum length. Operand 0 is the
4194 output; it has mode @var{m}. The second and third operand are the blocks of
4195 memory to be compared; both are @code{mem:BLK} with an address in mode
4198 The fourth operand is the known shared alignment of the source and
4199 destination, in the form of a @code{const_int} rtx. Thus, if the
4200 compiler knows that both source and destination are word-aligned,
4201 it may provide the value 4 for this operand.
4203 The two memory blocks specified are compared byte by byte in lexicographic
4204 order starting at the beginning of each string. The instruction is not allowed
4205 to prefetch more than one byte at a time since either string may end in the
4206 first byte and reading past that may access an invalid page or segment and
4207 cause a fault. The effect of the instruction is to store a value in operand 0
4208 whose sign indicates the result of the comparison.
4210 @cindex @code{cmpmem@var{m}} instruction pattern
4211 @item @samp{cmpmem@var{m}}
4212 Block compare instruction, with five operands like the operands
4213 of @samp{cmpstr@var{m}}. The two memory blocks specified are compared
4214 byte by byte in lexicographic order starting at the beginning of each
4215 block. Unlike @samp{cmpstr@var{m}} the instruction can prefetch
4216 any bytes in the two memory blocks. The effect of the instruction is
4217 to store a value in operand 0 whose sign indicates the result of the
4220 @cindex @code{strlen@var{m}} instruction pattern
4221 @item @samp{strlen@var{m}}
4222 Compute the length of a string, with three operands.
4223 Operand 0 is the result (of mode @var{m}), operand 1 is
4224 a @code{mem} referring to the first character of the string,
4225 operand 2 is the character to search for (normally zero),
4226 and operand 3 is a constant describing the known alignment
4227 of the beginning of the string.
4229 @cindex @code{float@var{mn}2} instruction pattern
4230 @item @samp{float@var{m}@var{n}2}
4231 Convert signed integer operand 1 (valid for fixed point mode @var{m}) to
4232 floating point mode @var{n} and store in operand 0 (which has mode
4235 @cindex @code{floatuns@var{mn}2} instruction pattern
4236 @item @samp{floatuns@var{m}@var{n}2}
4237 Convert unsigned integer operand 1 (valid for fixed point mode @var{m})
4238 to floating point mode @var{n} and store in operand 0 (which has mode
4241 @cindex @code{fix@var{mn}2} instruction pattern
4242 @item @samp{fix@var{m}@var{n}2}
4243 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4244 point mode @var{n} as a signed number and store in operand 0 (which
4245 has mode @var{n}). This instruction's result is defined only when
4246 the value of operand 1 is an integer.
4248 If the machine description defines this pattern, it also needs to
4249 define the @code{ftrunc} pattern.
4251 @cindex @code{fixuns@var{mn}2} instruction pattern
4252 @item @samp{fixuns@var{m}@var{n}2}
4253 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4254 point mode @var{n} as an unsigned number and store in operand 0 (which
4255 has mode @var{n}). This instruction's result is defined only when the
4256 value of operand 1 is an integer.
4258 @cindex @code{ftrunc@var{m}2} instruction pattern
4259 @item @samp{ftrunc@var{m}2}
4260 Convert operand 1 (valid for floating point mode @var{m}) to an
4261 integer value, still represented in floating point mode @var{m}, and
4262 store it in operand 0 (valid for floating point mode @var{m}).
4264 @cindex @code{fix_trunc@var{mn}2} instruction pattern
4265 @item @samp{fix_trunc@var{m}@var{n}2}
4266 Like @samp{fix@var{m}@var{n}2} but works for any floating point value
4267 of mode @var{m} by converting the value to an integer.
4269 @cindex @code{fixuns_trunc@var{mn}2} instruction pattern
4270 @item @samp{fixuns_trunc@var{m}@var{n}2}
4271 Like @samp{fixuns@var{m}@var{n}2} but works for any floating point
4272 value of mode @var{m} by converting the value to an integer.
4274 @cindex @code{trunc@var{mn}2} instruction pattern
4275 @item @samp{trunc@var{m}@var{n}2}
4276 Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and
4277 store in operand 0 (which has mode @var{n}). Both modes must be fixed
4278 point or both floating point.
4280 @cindex @code{extend@var{mn}2} instruction pattern
4281 @item @samp{extend@var{m}@var{n}2}
4282 Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
4283 store in operand 0 (which has mode @var{n}). Both modes must be fixed
4284 point or both floating point.
4286 @cindex @code{zero_extend@var{mn}2} instruction pattern
4287 @item @samp{zero_extend@var{m}@var{n}2}
4288 Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
4289 store in operand 0 (which has mode @var{n}). Both modes must be fixed
4292 @cindex @code{fract@var{mn}2} instruction pattern
4293 @item @samp{fract@var{m}@var{n}2}
4294 Convert operand 1 of mode @var{m} to mode @var{n} and store in
4295 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
4296 could be fixed-point to fixed-point, signed integer to fixed-point,
4297 fixed-point to signed integer, floating-point to fixed-point,
4298 or fixed-point to floating-point.
4299 When overflows or underflows happen, the results are undefined.
4301 @cindex @code{satfract@var{mn}2} instruction pattern
4302 @item @samp{satfract@var{m}@var{n}2}
4303 Convert operand 1 of mode @var{m} to mode @var{n} and store in
4304 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
4305 could be fixed-point to fixed-point, signed integer to fixed-point,
4306 or floating-point to fixed-point.
4307 When overflows or underflows happen, the instruction saturates the
4308 results to the maximum or the minimum.
4310 @cindex @code{fractuns@var{mn}2} instruction pattern
4311 @item @samp{fractuns@var{m}@var{n}2}
4312 Convert operand 1 of mode @var{m} to mode @var{n} and store in
4313 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
4314 could be unsigned integer to fixed-point, or
4315 fixed-point to unsigned integer.
4316 When overflows or underflows happen, the results are undefined.
4318 @cindex @code{satfractuns@var{mn}2} instruction pattern
4319 @item @samp{satfractuns@var{m}@var{n}2}
4320 Convert unsigned integer operand 1 of mode @var{m} to fixed-point mode
4321 @var{n} and store in operand 0 (which has mode @var{n}).
4322 When overflows or underflows happen, the instruction saturates the
4323 results to the maximum or the minimum.
4325 @cindex @code{extv} instruction pattern
4327 Extract a bit-field from operand 1 (a register or memory operand), where
4328 operand 2 specifies the width in bits and operand 3 the starting bit,
4329 and store it in operand 0. Operand 0 must have mode @code{word_mode}.
4330 Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often
4331 @code{word_mode} is allowed only for registers. Operands 2 and 3 must
4332 be valid for @code{word_mode}.
4334 The RTL generation pass generates this instruction only with constants
4335 for operands 2 and 3 and the constant is never zero for operand 2.
4337 The bit-field value is sign-extended to a full word integer
4338 before it is stored in operand 0.
4340 @cindex @code{extzv} instruction pattern
4342 Like @samp{extv} except that the bit-field value is zero-extended.
4344 @cindex @code{insv} instruction pattern
4346 Store operand 3 (which must be valid for @code{word_mode}) into a
4347 bit-field in operand 0, where operand 1 specifies the width in bits and
4348 operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or
4349 @code{word_mode}; often @code{word_mode} is allowed only for registers.
4350 Operands 1 and 2 must be valid for @code{word_mode}.
4352 The RTL generation pass generates this instruction only with constants
4353 for operands 1 and 2 and the constant is never zero for operand 1.
4355 @cindex @code{mov@var{mode}cc} instruction pattern
4356 @item @samp{mov@var{mode}cc}
4357 Conditionally move operand 2 or operand 3 into operand 0 according to the
4358 comparison in operand 1. If the comparison is true, operand 2 is moved
4359 into operand 0, otherwise operand 3 is moved.
4361 The mode of the operands being compared need not be the same as the operands
4362 being moved. Some machines, sparc64 for example, have instructions that
4363 conditionally move an integer value based on the floating point condition
4364 codes and vice versa.
4366 If the machine does not have conditional move instructions, do not
4367 define these patterns.
4369 @cindex @code{add@var{mode}cc} instruction pattern
4370 @item @samp{add@var{mode}cc}
4371 Similar to @samp{mov@var{mode}cc} but for conditional addition. Conditionally
4372 move operand 2 or (operands 2 + operand 3) into operand 0 according to the
4373 comparison in operand 1. If the comparison is true, operand 2 is moved into
4374 operand 0, otherwise (operand 2 + operand 3) is moved.
4376 @cindex @code{s@var{cond}} instruction pattern
4377 @item @samp{s@var{cond}}
4378 Store zero or nonzero in the operand according to the condition codes.
4379 Value stored is nonzero iff the condition @var{cond} is true.
4380 @var{cond} is the name of a comparison operation expression code, such
4381 as @code{eq}, @code{lt} or @code{leu}.
4383 You specify the mode that the operand must have when you write the
4384 @code{match_operand} expression. The compiler automatically sees
4385 which mode you have used and supplies an operand of that mode.
4387 The value stored for a true condition must have 1 as its low bit, or
4388 else must be negative. Otherwise the instruction is not suitable and
4389 you should omit it from the machine description. You describe to the
4390 compiler exactly which value is stored by defining the macro
4391 @code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be
4392 found that can be used for all the @samp{s@var{cond}} patterns, you
4393 should omit those operations from the machine description.
4395 These operations may fail, but should do so only in relatively
4396 uncommon cases; if they would fail for common cases involving
4397 integer comparisons, it is best to omit these patterns.
4399 If these operations are omitted, the compiler will usually generate code
4400 that copies the constant one to the target and branches around an
4401 assignment of zero to the target. If this code is more efficient than
4402 the potential instructions used for the @samp{s@var{cond}} pattern
4403 followed by those required to convert the result into a 1 or a zero in
4404 @code{SImode}, you should omit the @samp{s@var{cond}} operations from
4405 the machine description.
4407 @cindex @code{b@var{cond}} instruction pattern
4408 @item @samp{b@var{cond}}
4409 Conditional branch instruction. Operand 0 is a @code{label_ref} that
4410 refers to the label to jump to. Jump if the condition codes meet
4411 condition @var{cond}.
4413 Some machines do not follow the model assumed here where a comparison
4414 instruction is followed by a conditional branch instruction. In that
4415 case, the @samp{cmp@var{m}} (and @samp{tst@var{m}}) patterns should
4416 simply store the operands away and generate all the required insns in a
4417 @code{define_expand} (@pxref{Expander Definitions}) for the conditional
4418 branch operations. All calls to expand @samp{b@var{cond}} patterns are
4419 immediately preceded by calls to expand either a @samp{cmp@var{m}}
4420 pattern or a @samp{tst@var{m}} pattern.
4422 Machines that use a pseudo register for the condition code value, or
4423 where the mode used for the comparison depends on the condition being
4424 tested, should also use the above mechanism. @xref{Jump Patterns}.
4426 The above discussion also applies to the @samp{mov@var{mode}cc} and
4427 @samp{s@var{cond}} patterns.
4429 @cindex @code{cbranch@var{mode}4} instruction pattern
4430 @item @samp{cbranch@var{mode}4}
4431 Conditional branch instruction combined with a compare instruction.
4432 Operand 0 is a comparison operator. Operand 1 and operand 2 are the
4433 first and second operands of the comparison, respectively. Operand 3
4434 is a @code{label_ref} that refers to the label to jump to.
4436 @cindex @code{jump} instruction pattern
4438 A jump inside a function; an unconditional branch. Operand 0 is the
4439 @code{label_ref} of the label to jump to. This pattern name is mandatory
4442 @cindex @code{call} instruction pattern
4444 Subroutine call instruction returning no value. Operand 0 is the
4445 function to call; operand 1 is the number of bytes of arguments pushed
4446 as a @code{const_int}; operand 2 is the number of registers used as
4449 On most machines, operand 2 is not actually stored into the RTL
4450 pattern. It is supplied for the sake of some RISC machines which need
4451 to put this information into the assembler code; they can put it in
4452 the RTL instead of operand 1.
4454 Operand 0 should be a @code{mem} RTX whose address is the address of the
4455 function. Note, however, that this address can be a @code{symbol_ref}
4456 expression even if it would not be a legitimate memory address on the
4457 target machine. If it is also not a valid argument for a call
4458 instruction, the pattern for this operation should be a
4459 @code{define_expand} (@pxref{Expander Definitions}) that places the
4460 address into a register and uses that register in the call instruction.
4462 @cindex @code{call_value} instruction pattern
4463 @item @samp{call_value}
4464 Subroutine call instruction returning a value. Operand 0 is the hard
4465 register in which the value is returned. There are three more
4466 operands, the same as the three operands of the @samp{call}
4467 instruction (but with numbers increased by one).
4469 Subroutines that return @code{BLKmode} objects use the @samp{call}
4472 @cindex @code{call_pop} instruction pattern
4473 @cindex @code{call_value_pop} instruction pattern
4474 @item @samp{call_pop}, @samp{call_value_pop}
4475 Similar to @samp{call} and @samp{call_value}, except used if defined and
4476 if @code{RETURN_POPS_ARGS} is nonzero. They should emit a @code{parallel}
4477 that contains both the function call and a @code{set} to indicate the
4478 adjustment made to the frame pointer.
4480 For machines where @code{RETURN_POPS_ARGS} can be nonzero, the use of these
4481 patterns increases the number of functions for which the frame pointer
4482 can be eliminated, if desired.
4484 @cindex @code{untyped_call} instruction pattern
4485 @item @samp{untyped_call}
4486 Subroutine call instruction returning a value of any type. Operand 0 is
4487 the function to call; operand 1 is a memory location where the result of
4488 calling the function is to be stored; operand 2 is a @code{parallel}
4489 expression where each element is a @code{set} expression that indicates
4490 the saving of a function return value into the result block.
4492 This instruction pattern should be defined to support
4493 @code{__builtin_apply} on machines where special instructions are needed
4494 to call a subroutine with arbitrary arguments or to save the value
4495 returned. This instruction pattern is required on machines that have
4496 multiple registers that can hold a return value
4497 (i.e.@: @code{FUNCTION_VALUE_REGNO_P} is true for more than one register).
4499 @cindex @code{return} instruction pattern
4501 Subroutine return instruction. This instruction pattern name should be
4502 defined only if a single instruction can do all the work of returning
4505 Like the @samp{mov@var{m}} patterns, this pattern is also used after the
4506 RTL generation phase. In this case it is to support machines where
4507 multiple instructions are usually needed to return from a function, but
4508 some class of functions only requires one instruction to implement a
4509 return. Normally, the applicable functions are those which do not need
4510 to save any registers or allocate stack space.
4512 @findex reload_completed
4513 @findex leaf_function_p
4514 For such machines, the condition specified in this pattern should only
4515 be true when @code{reload_completed} is nonzero and the function's
4516 epilogue would only be a single instruction. For machines with register
4517 windows, the routine @code{leaf_function_p} may be used to determine if
4518 a register window push is required.
4520 Machines that have conditional return instructions should define patterns
4526 (if_then_else (match_operator
4527 0 "comparison_operator"
4528 [(cc0) (const_int 0)])
4535 where @var{condition} would normally be the same condition specified on the
4536 named @samp{return} pattern.
4538 @cindex @code{untyped_return} instruction pattern
4539 @item @samp{untyped_return}
4540 Untyped subroutine return instruction. This instruction pattern should
4541 be defined to support @code{__builtin_return} on machines where special
4542 instructions are needed to return a value of any type.
4544 Operand 0 is a memory location where the result of calling a function
4545 with @code{__builtin_apply} is stored; operand 1 is a @code{parallel}
4546 expression where each element is a @code{set} expression that indicates
4547 the restoring of a function return value from the result block.
4549 @cindex @code{nop} instruction pattern
4551 No-op instruction. This instruction pattern name should always be defined
4552 to output a no-op in assembler code. @code{(const_int 0)} will do as an
4555 @cindex @code{indirect_jump} instruction pattern
4556 @item @samp{indirect_jump}
4557 An instruction to jump to an address which is operand zero.
4558 This pattern name is mandatory on all machines.
4560 @cindex @code{casesi} instruction pattern
4562 Instruction to jump through a dispatch table, including bounds checking.
4563 This instruction takes five operands:
4567 The index to dispatch on, which has mode @code{SImode}.
4570 The lower bound for indices in the table, an integer constant.
4573 The total range of indices in the table---the largest index
4574 minus the smallest one (both inclusive).
4577 A label that precedes the table itself.
4580 A label to jump to if the index has a value outside the bounds.
4583 The table is a @code{addr_vec} or @code{addr_diff_vec} inside of a
4584 @code{jump_insn}. The number of elements in the table is one plus the
4585 difference between the upper bound and the lower bound.
4587 @cindex @code{tablejump} instruction pattern
4588 @item @samp{tablejump}
4589 Instruction to jump to a variable address. This is a low-level
4590 capability which can be used to implement a dispatch table when there
4591 is no @samp{casesi} pattern.
4593 This pattern requires two operands: the address or offset, and a label
4594 which should immediately precede the jump table. If the macro
4595 @code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first
4596 operand is an offset which counts from the address of the table; otherwise,
4597 it is an absolute address to jump to. In either case, the first operand has
4600 The @samp{tablejump} insn is always the last insn before the jump
4601 table it uses. Its assembler code normally has no need to use the
4602 second operand, but you should incorporate it in the RTL pattern so
4603 that the jump optimizer will not delete the table as unreachable code.
4606 @cindex @code{decrement_and_branch_until_zero} instruction pattern
4607 @item @samp{decrement_and_branch_until_zero}
4608 Conditional branch instruction that decrements a register and
4609 jumps if the register is nonzero. Operand 0 is the register to
4610 decrement and test; operand 1 is the label to jump to if the
4611 register is nonzero. @xref{Looping Patterns}.
4613 This optional instruction pattern is only used by the combiner,
4614 typically for loops reversed by the loop optimizer when strength
4615 reduction is enabled.
4617 @cindex @code{doloop_end} instruction pattern
4618 @item @samp{doloop_end}
4619 Conditional branch instruction that decrements a register and jumps if
4620 the register is nonzero. This instruction takes five operands: Operand
4621 0 is the register to decrement and test; operand 1 is the number of loop
4622 iterations as a @code{const_int} or @code{const0_rtx} if this cannot be
4623 determined until run-time; operand 2 is the actual or estimated maximum
4624 number of iterations as a @code{const_int}; operand 3 is the number of
4625 enclosed loops as a @code{const_int} (an innermost loop has a value of
4626 1); operand 4 is the label to jump to if the register is nonzero.
4627 @xref{Looping Patterns}.
4629 This optional instruction pattern should be defined for machines with
4630 low-overhead looping instructions as the loop optimizer will try to
4631 modify suitable loops to utilize it. If nested low-overhead looping is
4632 not supported, use a @code{define_expand} (@pxref{Expander Definitions})
4633 and make the pattern fail if operand 3 is not @code{const1_rtx}.
4634 Similarly, if the actual or estimated maximum number of iterations is
4635 too large for this instruction, make it fail.
4637 @cindex @code{doloop_begin} instruction pattern
4638 @item @samp{doloop_begin}
4639 Companion instruction to @code{doloop_end} required for machines that
4640 need to perform some initialization, such as loading special registers
4641 used by a low-overhead looping instruction. If initialization insns do
4642 not always need to be emitted, use a @code{define_expand}
4643 (@pxref{Expander Definitions}) and make it fail.
4646 @cindex @code{canonicalize_funcptr_for_compare} instruction pattern
4647 @item @samp{canonicalize_funcptr_for_compare}
4648 Canonicalize the function pointer in operand 1 and store the result
4651 Operand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1
4652 may be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc
4653 and also has mode @code{Pmode}.
4655 Canonicalization of a function pointer usually involves computing
4656 the address of the function which would be called if the function
4657 pointer were used in an indirect call.
4659 Only define this pattern if function pointers on the target machine
4660 can have different values but still call the same function when
4661 used in an indirect call.
4663 @cindex @code{save_stack_block} instruction pattern
4664 @cindex @code{save_stack_function} instruction pattern
4665 @cindex @code{save_stack_nonlocal} instruction pattern
4666 @cindex @code{restore_stack_block} instruction pattern
4667 @cindex @code{restore_stack_function} instruction pattern
4668 @cindex @code{restore_stack_nonlocal} instruction pattern
4669 @item @samp{save_stack_block}
4670 @itemx @samp{save_stack_function}
4671 @itemx @samp{save_stack_nonlocal}
4672 @itemx @samp{restore_stack_block}
4673 @itemx @samp{restore_stack_function}
4674 @itemx @samp{restore_stack_nonlocal}
4675 Most machines save and restore the stack pointer by copying it to or
4676 from an object of mode @code{Pmode}. Do not define these patterns on
4679 Some machines require special handling for stack pointer saves and
4680 restores. On those machines, define the patterns corresponding to the
4681 non-standard cases by using a @code{define_expand} (@pxref{Expander
4682 Definitions}) that produces the required insns. The three types of
4683 saves and restores are:
4687 @samp{save_stack_block} saves the stack pointer at the start of a block
4688 that allocates a variable-sized object, and @samp{restore_stack_block}
4689 restores the stack pointer when the block is exited.
4692 @samp{save_stack_function} and @samp{restore_stack_function} do a
4693 similar job for the outermost block of a function and are used when the
4694 function allocates variable-sized objects or calls @code{alloca}. Only
4695 the epilogue uses the restored stack pointer, allowing a simpler save or
4696 restore sequence on some machines.
4699 @samp{save_stack_nonlocal} is used in functions that contain labels
4700 branched to by nested functions. It saves the stack pointer in such a
4701 way that the inner function can use @samp{restore_stack_nonlocal} to
4702 restore the stack pointer. The compiler generates code to restore the
4703 frame and argument pointer registers, but some machines require saving
4704 and restoring additional data such as register window information or
4705 stack backchains. Place insns in these patterns to save and restore any
4709 When saving the stack pointer, operand 0 is the save area and operand 1
4710 is the stack pointer. The mode used to allocate the save area defaults
4711 to @code{Pmode} but you can override that choice by defining the
4712 @code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must
4713 specify an integral mode, or @code{VOIDmode} if no save area is needed
4714 for a particular type of save (either because no save is needed or
4715 because a machine-specific save area can be used). Operand 0 is the
4716 stack pointer and operand 1 is the save area for restore operations. If
4717 @samp{save_stack_block} is defined, operand 0 must not be
4718 @code{VOIDmode} since these saves can be arbitrarily nested.
4720 A save area is a @code{mem} that is at a constant offset from
4721 @code{virtual_stack_vars_rtx} when the stack pointer is saved for use by
4722 nonlocal gotos and a @code{reg} in the other two cases.
4724 @cindex @code{allocate_stack} instruction pattern
4725 @item @samp{allocate_stack}
4726 Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from
4727 the stack pointer to create space for dynamically allocated data.
4729 Store the resultant pointer to this space into operand 0. If you
4730 are allocating space from the main stack, do this by emitting a
4731 move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0.
4732 If you are allocating the space elsewhere, generate code to copy the
4733 location of the space to operand 0. In the latter case, you must
4734 ensure this space gets freed when the corresponding space on the main
4737 Do not define this pattern if all that must be done is the subtraction.
4738 Some machines require other operations such as stack probes or
4739 maintaining the back chain. Define this pattern to emit those
4740 operations in addition to updating the stack pointer.
4742 @cindex @code{check_stack} instruction pattern
4743 @item @samp{check_stack}
4744 If stack checking cannot be done on your system by probing the stack with
4745 a load or store instruction (@pxref{Stack Checking}), define this pattern
4746 to perform the needed check and signaling an error if the stack
4747 has overflowed. The single operand is the location in the stack furthest
4748 from the current stack pointer that you need to validate. Normally,
4749 on machines where this pattern is needed, you would obtain the stack
4750 limit from a global or thread-specific variable or register.
4752 @cindex @code{nonlocal_goto} instruction pattern
4753 @item @samp{nonlocal_goto}
4754 Emit code to generate a non-local goto, e.g., a jump from one function
4755 to a label in an outer function. This pattern has four arguments,
4756 each representing a value to be used in the jump. The first
4757 argument is to be loaded into the frame pointer, the second is
4758 the address to branch to (code to dispatch to the actual label),
4759 the third is the address of a location where the stack is saved,
4760 and the last is the address of the label, to be placed in the
4761 location for the incoming static chain.
4763 On most machines you need not define this pattern, since GCC will
4764 already generate the correct code, which is to load the frame pointer
4765 and static chain, restore the stack (using the
4766 @samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly
4767 to the dispatcher. You need only define this pattern if this code will
4768 not work on your machine.
4770 @cindex @code{nonlocal_goto_receiver} instruction pattern
4771 @item @samp{nonlocal_goto_receiver}
4772 This pattern, if defined, contains code needed at the target of a
4773 nonlocal goto after the code already generated by GCC@. You will not
4774 normally need to define this pattern. A typical reason why you might
4775 need this pattern is if some value, such as a pointer to a global table,
4776 must be restored when the frame pointer is restored. Note that a nonlocal
4777 goto only occurs within a unit-of-translation, so a global table pointer
4778 that is shared by all functions of a given module need not be restored.
4779 There are no arguments.
4781 @cindex @code{exception_receiver} instruction pattern
4782 @item @samp{exception_receiver}
4783 This pattern, if defined, contains code needed at the site of an
4784 exception handler that isn't needed at the site of a nonlocal goto. You
4785 will not normally need to define this pattern. A typical reason why you
4786 might need this pattern is if some value, such as a pointer to a global
4787 table, must be restored after control flow is branched to the handler of
4788 an exception. There are no arguments.
4790 @cindex @code{builtin_setjmp_setup} instruction pattern
4791 @item @samp{builtin_setjmp_setup}
4792 This pattern, if defined, contains additional code needed to initialize
4793 the @code{jmp_buf}. You will not normally need to define this pattern.
4794 A typical reason why you might need this pattern is if some value, such
4795 as a pointer to a global table, must be restored. Though it is
4796 preferred that the pointer value be recalculated if possible (given the
4797 address of a label for instance). The single argument is a pointer to
4798 the @code{jmp_buf}. Note that the buffer is five words long and that
4799 the first three are normally used by the generic mechanism.
4801 @cindex @code{builtin_setjmp_receiver} instruction pattern
4802 @item @samp{builtin_setjmp_receiver}
4803 This pattern, if defined, contains code needed at the site of an
4804 built-in setjmp that isn't needed at the site of a nonlocal goto. You
4805 will not normally need to define this pattern. A typical reason why you
4806 might need this pattern is if some value, such as a pointer to a global
4807 table, must be restored. It takes one argument, which is the label
4808 to which builtin_longjmp transfered control; this pattern may be emitted
4809 at a small offset from that label.
4811 @cindex @code{builtin_longjmp} instruction pattern
4812 @item @samp{builtin_longjmp}
4813 This pattern, if defined, performs the entire action of the longjmp.
4814 You will not normally need to define this pattern unless you also define
4815 @code{builtin_setjmp_setup}. The single argument is a pointer to the
4818 @cindex @code{eh_return} instruction pattern
4819 @item @samp{eh_return}
4820 This pattern, if defined, affects the way @code{__builtin_eh_return},
4821 and thence the call frame exception handling library routines, are
4822 built. It is intended to handle non-trivial actions needed along
4823 the abnormal return path.
4825 The address of the exception handler to which the function should return
4826 is passed as operand to this pattern. It will normally need to copied by
4827 the pattern to some special register or memory location.
4828 If the pattern needs to determine the location of the target call
4829 frame in order to do so, it may use @code{EH_RETURN_STACKADJ_RTX},
4830 if defined; it will have already been assigned.
4832 If this pattern is not defined, the default action will be to simply
4833 copy the return address to @code{EH_RETURN_HANDLER_RTX}. Either
4834 that macro or this pattern needs to be defined if call frame exception
4835 handling is to be used.
4837 @cindex @code{prologue} instruction pattern
4838 @anchor{prologue instruction pattern}
4839 @item @samp{prologue}
4840 This pattern, if defined, emits RTL for entry to a function. The function
4841 entry is responsible for setting up the stack frame, initializing the frame
4842 pointer register, saving callee saved registers, etc.
4844 Using a prologue pattern is generally preferred over defining
4845 @code{TARGET_ASM_FUNCTION_PROLOGUE} to emit assembly code for the prologue.
4847 The @code{prologue} pattern is particularly useful for targets which perform
4848 instruction scheduling.
4850 @cindex @code{epilogue} instruction pattern
4851 @anchor{epilogue instruction pattern}
4852 @item @samp{epilogue}
4853 This pattern emits RTL for exit from a function. The function
4854 exit is responsible for deallocating the stack frame, restoring callee saved
4855 registers and emitting the return instruction.
4857 Using an epilogue pattern is generally preferred over defining
4858 @code{TARGET_ASM_FUNCTION_EPILOGUE} to emit assembly code for the epilogue.
4860 The @code{epilogue} pattern is particularly useful for targets which perform
4861 instruction scheduling or which have delay slots for their return instruction.
4863 @cindex @code{sibcall_epilogue} instruction pattern
4864 @item @samp{sibcall_epilogue}
4865 This pattern, if defined, emits RTL for exit from a function without the final
4866 branch back to the calling function. This pattern will be emitted before any
4867 sibling call (aka tail call) sites.
4869 The @code{sibcall_epilogue} pattern must not clobber any arguments used for
4870 parameter passing or any stack slots for arguments passed to the current
4873 @cindex @code{trap} instruction pattern
4875 This pattern, if defined, signals an error, typically by causing some
4876 kind of signal to be raised. Among other places, it is used by the Java
4877 front end to signal `invalid array index' exceptions.
4879 @cindex @code{conditional_trap} instruction pattern
4880 @item @samp{conditional_trap}
4881 Conditional trap instruction. Operand 0 is a piece of RTL which
4882 performs a comparison. Operand 1 is the trap code, an integer.
4884 A typical @code{conditional_trap} pattern looks like
4887 (define_insn "conditional_trap"
4888 [(trap_if (match_operator 0 "trap_operator"
4889 [(cc0) (const_int 0)])
4890 (match_operand 1 "const_int_operand" "i"))]
4895 @cindex @code{prefetch} instruction pattern
4896 @item @samp{prefetch}
4898 This pattern, if defined, emits code for a non-faulting data prefetch
4899 instruction. Operand 0 is the address of the memory to prefetch. Operand 1
4900 is a constant 1 if the prefetch is preparing for a write to the memory
4901 address, or a constant 0 otherwise. Operand 2 is the expected degree of
4902 temporal locality of the data and is a value between 0 and 3, inclusive; 0
4903 means that the data has no temporal locality, so it need not be left in the
4904 cache after the access; 3 means that the data has a high degree of temporal
4905 locality and should be left in all levels of cache possible; 1 and 2 mean,
4906 respectively, a low or moderate degree of temporal locality.
4908 Targets that do not support write prefetches or locality hints can ignore
4909 the values of operands 1 and 2.
4911 @cindex @code{blockage} instruction pattern
4912 @item @samp{blockage}
4914 This pattern defines a pseudo insn that prevents the instruction
4915 scheduler from moving instructions across the boundary defined by the
4916 blockage insn. Normally an UNSPEC_VOLATILE pattern.
4918 @cindex @code{memory_barrier} instruction pattern
4919 @item @samp{memory_barrier}
4921 If the target memory model is not fully synchronous, then this pattern
4922 should be defined to an instruction that orders both loads and stores
4923 before the instruction with respect to loads and stores after the instruction.
4924 This pattern has no operands.
4926 @cindex @code{sync_compare_and_swap@var{mode}} instruction pattern
4927 @item @samp{sync_compare_and_swap@var{mode}}
4929 This pattern, if defined, emits code for an atomic compare-and-swap
4930 operation. Operand 1 is the memory on which the atomic operation is
4931 performed. Operand 2 is the ``old'' value to be compared against the
4932 current contents of the memory location. Operand 3 is the ``new'' value
4933 to store in the memory if the compare succeeds. Operand 0 is the result
4934 of the operation; it should contain the contents of the memory
4935 before the operation. If the compare succeeds, this should obviously be
4936 a copy of operand 2.
4938 This pattern must show that both operand 0 and operand 1 are modified.
4940 This pattern must issue any memory barrier instructions such that all
4941 memory operations before the atomic operation occur before the atomic
4942 operation and all memory operations after the atomic operation occur
4943 after the atomic operation.
4945 @cindex @code{sync_compare_and_swap_cc@var{mode}} instruction pattern
4946 @item @samp{sync_compare_and_swap_cc@var{mode}}
4948 This pattern is just like @code{sync_compare_and_swap@var{mode}}, except
4949 it should act as if compare part of the compare-and-swap were issued via
4950 @code{cmp@var{m}}. This comparison will only be used with @code{EQ} and
4951 @code{NE} branches and @code{setcc} operations.
4953 Some targets do expose the success or failure of the compare-and-swap
4954 operation via the status flags. Ideally we wouldn't need a separate
4955 named pattern in order to take advantage of this, but the combine pass
4956 does not handle patterns with multiple sets, which is required by
4957 definition for @code{sync_compare_and_swap@var{mode}}.
4959 @cindex @code{sync_add@var{mode}} instruction pattern
4960 @cindex @code{sync_sub@var{mode}} instruction pattern
4961 @cindex @code{sync_ior@var{mode}} instruction pattern
4962 @cindex @code{sync_and@var{mode}} instruction pattern
4963 @cindex @code{sync_xor@var{mode}} instruction pattern
4964 @cindex @code{sync_nand@var{mode}} instruction pattern
4965 @item @samp{sync_add@var{mode}}, @samp{sync_sub@var{mode}}
4966 @itemx @samp{sync_ior@var{mode}}, @samp{sync_and@var{mode}}
4967 @itemx @samp{sync_xor@var{mode}}, @samp{sync_nand@var{mode}}
4969 These patterns emit code for an atomic operation on memory.
4970 Operand 0 is the memory on which the atomic operation is performed.
4971 Operand 1 is the second operand to the binary operator.
4973 The ``nand'' operation is @code{~op0 & op1}.
4975 This pattern must issue any memory barrier instructions such that all
4976 memory operations before the atomic operation occur before the atomic
4977 operation and all memory operations after the atomic operation occur
4978 after the atomic operation.
4980 If these patterns are not defined, the operation will be constructed
4981 from a compare-and-swap operation, if defined.
4983 @cindex @code{sync_old_add@var{mode}} instruction pattern
4984 @cindex @code{sync_old_sub@var{mode}} instruction pattern
4985 @cindex @code{sync_old_ior@var{mode}} instruction pattern
4986 @cindex @code{sync_old_and@var{mode}} instruction pattern
4987 @cindex @code{sync_old_xor@var{mode}} instruction pattern
4988 @cindex @code{sync_old_nand@var{mode}} instruction pattern
4989 @item @samp{sync_old_add@var{mode}}, @samp{sync_old_sub@var{mode}}
4990 @itemx @samp{sync_old_ior@var{mode}}, @samp{sync_old_and@var{mode}}
4991 @itemx @samp{sync_old_xor@var{mode}}, @samp{sync_old_nand@var{mode}}
4993 These patterns are emit code for an atomic operation on memory,
4994 and return the value that the memory contained before the operation.
4995 Operand 0 is the result value, operand 1 is the memory on which the
4996 atomic operation is performed, and operand 2 is the second operand
4997 to the binary operator.
4999 This pattern must issue any memory barrier instructions such that all
5000 memory operations before the atomic operation occur before the atomic
5001 operation and all memory operations after the atomic operation occur
5002 after the atomic operation.
5004 If these patterns are not defined, the operation will be constructed
5005 from a compare-and-swap operation, if defined.
5007 @cindex @code{sync_new_add@var{mode}} instruction pattern
5008 @cindex @code{sync_new_sub@var{mode}} instruction pattern
5009 @cindex @code{sync_new_ior@var{mode}} instruction pattern
5010 @cindex @code{sync_new_and@var{mode}} instruction pattern
5011 @cindex @code{sync_new_xor@var{mode}} instruction pattern
5012 @cindex @code{sync_new_nand@var{mode}} instruction pattern
5013 @item @samp{sync_new_add@var{mode}}, @samp{sync_new_sub@var{mode}}
5014 @itemx @samp{sync_new_ior@var{mode}}, @samp{sync_new_and@var{mode}}
5015 @itemx @samp{sync_new_xor@var{mode}}, @samp{sync_new_nand@var{mode}}
5017 These patterns are like their @code{sync_old_@var{op}} counterparts,
5018 except that they return the value that exists in the memory location
5019 after the operation, rather than before the operation.
5021 @cindex @code{sync_lock_test_and_set@var{mode}} instruction pattern
5022 @item @samp{sync_lock_test_and_set@var{mode}}
5024 This pattern takes two forms, based on the capabilities of the target.
5025 In either case, operand 0 is the result of the operand, operand 1 is
5026 the memory on which the atomic operation is performed, and operand 2
5027 is the value to set in the lock.
5029 In the ideal case, this operation is an atomic exchange operation, in
5030 which the previous value in memory operand is copied into the result
5031 operand, and the value operand is stored in the memory operand.
5033 For less capable targets, any value operand that is not the constant 1
5034 should be rejected with @code{FAIL}. In this case the target may use
5035 an atomic test-and-set bit operation. The result operand should contain
5036 1 if the bit was previously set and 0 if the bit was previously clear.
5037 The true contents of the memory operand are implementation defined.
5039 This pattern must issue any memory barrier instructions such that the
5040 pattern as a whole acts as an acquire barrier, that is all memory
5041 operations after the pattern do not occur until the lock is acquired.
5043 If this pattern is not defined, the operation will be constructed from
5044 a compare-and-swap operation, if defined.
5046 @cindex @code{sync_lock_release@var{mode}} instruction pattern
5047 @item @samp{sync_lock_release@var{mode}}
5049 This pattern, if defined, releases a lock set by
5050 @code{sync_lock_test_and_set@var{mode}}. Operand 0 is the memory
5051 that contains the lock; operand 1 is the value to store in the lock.
5053 If the target doesn't implement full semantics for
5054 @code{sync_lock_test_and_set@var{mode}}, any value operand which is not
5055 the constant 0 should be rejected with @code{FAIL}, and the true contents
5056 of the memory operand are implementation defined.
5058 This pattern must issue any memory barrier instructions such that the
5059 pattern as a whole acts as a release barrier, that is the lock is
5060 released only after all previous memory operations have completed.
5062 If this pattern is not defined, then a @code{memory_barrier} pattern
5063 will be emitted, followed by a store of the value to the memory operand.
5065 @cindex @code{stack_protect_set} instruction pattern
5066 @item @samp{stack_protect_set}
5068 This pattern, if defined, moves a @code{Pmode} value from the memory
5069 in operand 1 to the memory in operand 0 without leaving the value in
5070 a register afterward. This is to avoid leaking the value some place
5071 that an attacker might use to rewrite the stack guard slot after
5072 having clobbered it.
5074 If this pattern is not defined, then a plain move pattern is generated.
5076 @cindex @code{stack_protect_test} instruction pattern
5077 @item @samp{stack_protect_test}
5079 This pattern, if defined, compares a @code{Pmode} value from the
5080 memory in operand 1 with the memory in operand 0 without leaving the
5081 value in a register afterward and branches to operand 2 if the values
5084 If this pattern is not defined, then a plain compare pattern and
5085 conditional branch pattern is used.
5087 @cindex @code{clear_cache} instruction pattern
5088 @item @samp{clear_cache}
5090 This pattern, if defined, flushes the instruction cache for a region of
5091 memory. The region is bounded to by the Pmode pointers in operand 0
5092 inclusive and operand 1 exclusive.
5094 If this pattern is not defined, a call to the library function
5095 @code{__clear_cache} is used.
5100 @c Each of the following nodes are wrapped in separate
5101 @c "@ifset INTERNALS" to work around memory limits for the default
5102 @c configuration in older tetex distributions. Known to not work:
5103 @c tetex-1.0.7, known to work: tetex-2.0.2.
5105 @node Pattern Ordering
5106 @section When the Order of Patterns Matters
5107 @cindex Pattern Ordering
5108 @cindex Ordering of Patterns
5110 Sometimes an insn can match more than one instruction pattern. Then the
5111 pattern that appears first in the machine description is the one used.
5112 Therefore, more specific patterns (patterns that will match fewer things)
5113 and faster instructions (those that will produce better code when they
5114 do match) should usually go first in the description.
5116 In some cases the effect of ordering the patterns can be used to hide
5117 a pattern when it is not valid. For example, the 68000 has an
5118 instruction for converting a fullword to floating point and another
5119 for converting a byte to floating point. An instruction converting
5120 an integer to floating point could match either one. We put the
5121 pattern to convert the fullword first to make sure that one will
5122 be used rather than the other. (Otherwise a large integer might
5123 be generated as a single-byte immediate quantity, which would not work.)
5124 Instead of using this pattern ordering it would be possible to make the
5125 pattern for convert-a-byte smart enough to deal properly with any
5130 @node Dependent Patterns
5131 @section Interdependence of Patterns
5132 @cindex Dependent Patterns
5133 @cindex Interdependence of Patterns
5135 Every machine description must have a named pattern for each of the
5136 conditional branch names @samp{b@var{cond}}. The recognition template
5137 must always have the form
5141 (if_then_else (@var{cond} (cc0) (const_int 0))
5142 (label_ref (match_operand 0 "" ""))
5147 In addition, every machine description must have an anonymous pattern
5148 for each of the possible reverse-conditional branches. Their templates
5153 (if_then_else (@var{cond} (cc0) (const_int 0))
5155 (label_ref (match_operand 0 "" ""))))
5159 They are necessary because jump optimization can turn direct-conditional
5160 branches into reverse-conditional branches.
5162 It is often convenient to use the @code{match_operator} construct to
5163 reduce the number of patterns that must be specified for branches. For
5169 (if_then_else (match_operator 0 "comparison_operator"
5170 [(cc0) (const_int 0)])
5172 (label_ref (match_operand 1 "" ""))))]
5177 In some cases machines support instructions identical except for the
5178 machine mode of one or more operands. For example, there may be
5179 ``sign-extend halfword'' and ``sign-extend byte'' instructions whose
5183 (set (match_operand:SI 0 @dots{})
5184 (extend:SI (match_operand:HI 1 @dots{})))
5186 (set (match_operand:SI 0 @dots{})
5187 (extend:SI (match_operand:QI 1 @dots{})))
5191 Constant integers do not specify a machine mode, so an instruction to
5192 extend a constant value could match either pattern. The pattern it
5193 actually will match is the one that appears first in the file. For correct
5194 results, this must be the one for the widest possible mode (@code{HImode},
5195 here). If the pattern matches the @code{QImode} instruction, the results
5196 will be incorrect if the constant value does not actually fit that mode.
5198 Such instructions to extend constants are rarely generated because they are
5199 optimized away, but they do occasionally happen in nonoptimized
5202 If a constraint in a pattern allows a constant, the reload pass may
5203 replace a register with a constant permitted by the constraint in some
5204 cases. Similarly for memory references. Because of this substitution,
5205 you should not provide separate patterns for increment and decrement
5206 instructions. Instead, they should be generated from the same pattern
5207 that supports register-register add insns by examining the operands and
5208 generating the appropriate machine instruction.
5213 @section Defining Jump Instruction Patterns
5214 @cindex jump instruction patterns
5215 @cindex defining jump instruction patterns
5217 For most machines, GCC assumes that the machine has a condition code.
5218 A comparison insn sets the condition code, recording the results of both
5219 signed and unsigned comparison of the given operands. A separate branch
5220 insn tests the condition code and branches or not according its value.
5221 The branch insns come in distinct signed and unsigned flavors. Many
5222 common machines, such as the VAX, the 68000 and the 32000, work this
5225 Some machines have distinct signed and unsigned compare instructions, and
5226 only one set of conditional branch instructions. The easiest way to handle
5227 these machines is to treat them just like the others until the final stage
5228 where assembly code is written. At this time, when outputting code for the
5229 compare instruction, peek ahead at the following branch using
5230 @code{next_cc0_user (insn)}. (The variable @code{insn} refers to the insn
5231 being output, in the output-writing code in an instruction pattern.) If
5232 the RTL says that is an unsigned branch, output an unsigned compare;
5233 otherwise output a signed compare. When the branch itself is output, you
5234 can treat signed and unsigned branches identically.
5236 The reason you can do this is that GCC always generates a pair of
5237 consecutive RTL insns, possibly separated by @code{note} insns, one to
5238 set the condition code and one to test it, and keeps the pair inviolate
5241 To go with this technique, you must define the machine-description macro
5242 @code{NOTICE_UPDATE_CC} to do @code{CC_STATUS_INIT}; in other words, no
5243 compare instruction is superfluous.
5245 Some machines have compare-and-branch instructions and no condition code.
5246 A similar technique works for them. When it is time to ``output'' a
5247 compare instruction, record its operands in two static variables. When
5248 outputting the branch-on-condition-code instruction that follows, actually
5249 output a compare-and-branch instruction that uses the remembered operands.
5251 It also works to define patterns for compare-and-branch instructions.
5252 In optimizing compilation, the pair of compare and branch instructions
5253 will be combined according to these patterns. But this does not happen
5254 if optimization is not requested. So you must use one of the solutions
5255 above in addition to any special patterns you define.
5257 In many RISC machines, most instructions do not affect the condition
5258 code and there may not even be a separate condition code register. On
5259 these machines, the restriction that the definition and use of the
5260 condition code be adjacent insns is not necessary and can prevent
5261 important optimizations. For example, on the IBM RS/6000, there is a
5262 delay for taken branches unless the condition code register is set three
5263 instructions earlier than the conditional branch. The instruction
5264 scheduler cannot perform this optimization if it is not permitted to
5265 separate the definition and use of the condition code register.
5267 On these machines, do not use @code{(cc0)}, but instead use a register
5268 to represent the condition code. If there is a specific condition code
5269 register in the machine, use a hard register. If the condition code or
5270 comparison result can be placed in any general register, or if there are
5271 multiple condition registers, use a pseudo register.
5273 @findex prev_cc0_setter
5274 @findex next_cc0_user
5275 On some machines, the type of branch instruction generated may depend on
5276 the way the condition code was produced; for example, on the 68k and
5277 SPARC, setting the condition code directly from an add or subtract
5278 instruction does not clear the overflow bit the way that a test
5279 instruction does, so a different branch instruction must be used for
5280 some conditional branches. For machines that use @code{(cc0)}, the set
5281 and use of the condition code must be adjacent (separated only by
5282 @code{note} insns) allowing flags in @code{cc_status} to be used.
5283 (@xref{Condition Code}.) Also, the comparison and branch insns can be
5284 located from each other by using the functions @code{prev_cc0_setter}
5285 and @code{next_cc0_user}.
5287 However, this is not true on machines that do not use @code{(cc0)}. On
5288 those machines, no assumptions can be made about the adjacency of the
5289 compare and branch insns and the above methods cannot be used. Instead,
5290 we use the machine mode of the condition code register to record
5291 different formats of the condition code register.
5293 Registers used to store the condition code value should have a mode that
5294 is in class @code{MODE_CC}. Normally, it will be @code{CCmode}. If
5295 additional modes are required (as for the add example mentioned above in
5296 the SPARC), define them in @file{@var{machine}-modes.def}
5297 (@pxref{Condition Code}). Also define @code{SELECT_CC_MODE} to choose
5298 a mode given an operand of a compare.
5300 If it is known during RTL generation that a different mode will be
5301 required (for example, if the machine has separate compare instructions
5302 for signed and unsigned quantities, like most IBM processors), they can
5303 be specified at that time.
5305 If the cases that require different modes would be made by instruction
5306 combination, the macro @code{SELECT_CC_MODE} determines which machine
5307 mode should be used for the comparison result. The patterns should be
5308 written using that mode. To support the case of the add on the SPARC
5309 discussed above, we have the pattern
5313 [(set (reg:CC_NOOV 0)
5315 (plus:SI (match_operand:SI 0 "register_operand" "%r")
5316 (match_operand:SI 1 "arith_operand" "rI"))
5322 The @code{SELECT_CC_MODE} macro on the SPARC returns @code{CC_NOOVmode}
5323 for comparisons whose argument is a @code{plus}.
5327 @node Looping Patterns
5328 @section Defining Looping Instruction Patterns
5329 @cindex looping instruction patterns
5330 @cindex defining looping instruction patterns
5332 Some machines have special jump instructions that can be utilized to
5333 make loops more efficient. A common example is the 68000 @samp{dbra}
5334 instruction which performs a decrement of a register and a branch if the
5335 result was greater than zero. Other machines, in particular digital
5336 signal processors (DSPs), have special block repeat instructions to
5337 provide low-overhead loop support. For example, the TI TMS320C3x/C4x
5338 DSPs have a block repeat instruction that loads special registers to
5339 mark the top and end of a loop and to count the number of loop
5340 iterations. This avoids the need for fetching and executing a
5341 @samp{dbra}-like instruction and avoids pipeline stalls associated with
5344 GCC has three special named patterns to support low overhead looping.
5345 They are @samp{decrement_and_branch_until_zero}, @samp{doloop_begin},
5346 and @samp{doloop_end}. The first pattern,
5347 @samp{decrement_and_branch_until_zero}, is not emitted during RTL
5348 generation but may be emitted during the instruction combination phase.
5349 This requires the assistance of the loop optimizer, using information
5350 collected during strength reduction, to reverse a loop to count down to
5351 zero. Some targets also require the loop optimizer to add a
5352 @code{REG_NONNEG} note to indicate that the iteration count is always
5353 positive. This is needed if the target performs a signed loop
5354 termination test. For example, the 68000 uses a pattern similar to the
5355 following for its @code{dbra} instruction:
5359 (define_insn "decrement_and_branch_until_zero"
5362 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
5365 (label_ref (match_operand 1 "" ""))
5368 (plus:SI (match_dup 0)
5370 "find_reg_note (insn, REG_NONNEG, 0)"
5375 Note that since the insn is both a jump insn and has an output, it must
5376 deal with its own reloads, hence the `m' constraints. Also note that
5377 since this insn is generated by the instruction combination phase
5378 combining two sequential insns together into an implicit parallel insn,
5379 the iteration counter needs to be biased by the same amount as the
5380 decrement operation, in this case @minus{}1. Note that the following similar
5381 pattern will not be matched by the combiner.
5385 (define_insn "decrement_and_branch_until_zero"
5388 (ge (match_operand:SI 0 "general_operand" "+d*am")
5390 (label_ref (match_operand 1 "" ""))
5393 (plus:SI (match_dup 0)
5395 "find_reg_note (insn, REG_NONNEG, 0)"
5400 The other two special looping patterns, @samp{doloop_begin} and
5401 @samp{doloop_end}, are emitted by the loop optimizer for certain
5402 well-behaved loops with a finite number of loop iterations using
5403 information collected during strength reduction.
5405 The @samp{doloop_end} pattern describes the actual looping instruction
5406 (or the implicit looping operation) and the @samp{doloop_begin} pattern
5407 is an optional companion pattern that can be used for initialization
5408 needed for some low-overhead looping instructions.
5410 Note that some machines require the actual looping instruction to be
5411 emitted at the top of the loop (e.g., the TMS320C3x/C4x DSPs). Emitting
5412 the true RTL for a looping instruction at the top of the loop can cause
5413 problems with flow analysis. So instead, a dummy @code{doloop} insn is
5414 emitted at the end of the loop. The machine dependent reorg pass checks
5415 for the presence of this @code{doloop} insn and then searches back to
5416 the top of the loop, where it inserts the true looping insn (provided
5417 there are no instructions in the loop which would cause problems). Any
5418 additional labels can be emitted at this point. In addition, if the
5419 desired special iteration counter register was not allocated, this
5420 machine dependent reorg pass could emit a traditional compare and jump
5423 The essential difference between the
5424 @samp{decrement_and_branch_until_zero} and the @samp{doloop_end}
5425 patterns is that the loop optimizer allocates an additional pseudo
5426 register for the latter as an iteration counter. This pseudo register
5427 cannot be used within the loop (i.e., general induction variables cannot
5428 be derived from it), however, in many cases the loop induction variable
5429 may become redundant and removed by the flow pass.
5434 @node Insn Canonicalizations
5435 @section Canonicalization of Instructions
5436 @cindex canonicalization of instructions
5437 @cindex insn canonicalization
5439 There are often cases where multiple RTL expressions could represent an
5440 operation performed by a single machine instruction. This situation is
5441 most commonly encountered with logical, branch, and multiply-accumulate
5442 instructions. In such cases, the compiler attempts to convert these
5443 multiple RTL expressions into a single canonical form to reduce the
5444 number of insn patterns required.
5446 In addition to algebraic simplifications, following canonicalizations
5451 For commutative and comparison operators, a constant is always made the
5452 second operand. If a machine only supports a constant as the second
5453 operand, only patterns that match a constant in the second operand need
5457 For associative operators, a sequence of operators will always chain
5458 to the left; for instance, only the left operand of an integer @code{plus}
5459 can itself be a @code{plus}. @code{and}, @code{ior}, @code{xor},
5460 @code{plus}, @code{mult}, @code{smin}, @code{smax}, @code{umin}, and
5461 @code{umax} are associative when applied to integers, and sometimes to
5465 @cindex @code{neg}, canonicalization of
5466 @cindex @code{not}, canonicalization of
5467 @cindex @code{mult}, canonicalization of
5468 @cindex @code{plus}, canonicalization of
5469 @cindex @code{minus}, canonicalization of
5470 For these operators, if only one operand is a @code{neg}, @code{not},
5471 @code{mult}, @code{plus}, or @code{minus} expression, it will be the
5475 In combinations of @code{neg}, @code{mult}, @code{plus}, and
5476 @code{minus}, the @code{neg} operations (if any) will be moved inside
5477 the operations as far as possible. For instance,
5478 @code{(neg (mult A B))} is canonicalized as @code{(mult (neg A) B)}, but
5479 @code{(plus (mult (neg A) B) C)} is canonicalized as
5480 @code{(minus A (mult B C))}.
5482 @cindex @code{compare}, canonicalization of
5484 For the @code{compare} operator, a constant is always the second operand
5485 on machines where @code{cc0} is used (@pxref{Jump Patterns}). On other
5486 machines, there are rare cases where the compiler might want to construct
5487 a @code{compare} with a constant as the first operand. However, these
5488 cases are not common enough for it to be worthwhile to provide a pattern
5489 matching a constant as the first operand unless the machine actually has
5490 such an instruction.
5492 An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or
5493 @code{minus} is made the first operand under the same conditions as
5497 @code{(ltu (plus @var{a} @var{b}) @var{b})} is converted to
5498 @code{(ltu (plus @var{a} @var{b}) @var{a})}. Likewise with @code{geu} instead
5502 @code{(minus @var{x} (const_int @var{n}))} is converted to
5503 @code{(plus @var{x} (const_int @var{-n}))}.
5506 Within address computations (i.e., inside @code{mem}), a left shift is
5507 converted into the appropriate multiplication by a power of two.
5509 @cindex @code{ior}, canonicalization of
5510 @cindex @code{and}, canonicalization of
5511 @cindex De Morgan's law
5513 De Morgan's Law is used to move bitwise negation inside a bitwise
5514 logical-and or logical-or operation. If this results in only one
5515 operand being a @code{not} expression, it will be the first one.
5517 A machine that has an instruction that performs a bitwise logical-and of one
5518 operand with the bitwise negation of the other should specify the pattern
5519 for that instruction as
5523 [(set (match_operand:@var{m} 0 @dots{})
5524 (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
5525 (match_operand:@var{m} 2 @dots{})))]
5531 Similarly, a pattern for a ``NAND'' instruction should be written
5535 [(set (match_operand:@var{m} 0 @dots{})
5536 (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
5537 (not:@var{m} (match_operand:@var{m} 2 @dots{}))))]
5542 In both cases, it is not necessary to include patterns for the many
5543 logically equivalent RTL expressions.
5545 @cindex @code{xor}, canonicalization of
5547 The only possible RTL expressions involving both bitwise exclusive-or
5548 and bitwise negation are @code{(xor:@var{m} @var{x} @var{y})}
5549 and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}.
5552 The sum of three items, one of which is a constant, will only appear in
5556 (plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant})
5560 On machines that do not use @code{cc0},
5561 @code{(compare @var{x} (const_int 0))} will be converted to
5564 @cindex @code{zero_extract}, canonicalization of
5565 @cindex @code{sign_extract}, canonicalization of
5567 Equality comparisons of a group of bits (usually a single bit) with zero
5568 will be written using @code{zero_extract} rather than the equivalent
5569 @code{and} or @code{sign_extract} operations.
5573 Further canonicalization rules are defined in the function
5574 @code{commutative_operand_precedence} in @file{gcc/rtlanal.c}.
5578 @node Expander Definitions
5579 @section Defining RTL Sequences for Code Generation
5580 @cindex expander definitions
5581 @cindex code generation RTL sequences
5582 @cindex defining RTL sequences for code generation
5584 On some target machines, some standard pattern names for RTL generation
5585 cannot be handled with single insn, but a sequence of RTL insns can
5586 represent them. For these target machines, you can write a
5587 @code{define_expand} to specify how to generate the sequence of RTL@.
5589 @findex define_expand
5590 A @code{define_expand} is an RTL expression that looks almost like a
5591 @code{define_insn}; but, unlike the latter, a @code{define_expand} is used
5592 only for RTL generation and it can produce more than one RTL insn.
5594 A @code{define_expand} RTX has four operands:
5598 The name. Each @code{define_expand} must have a name, since the only
5599 use for it is to refer to it by name.
5602 The RTL template. This is a vector of RTL expressions representing
5603 a sequence of separate instructions. Unlike @code{define_insn}, there
5604 is no implicit surrounding @code{PARALLEL}.
5607 The condition, a string containing a C expression. This expression is
5608 used to express how the availability of this pattern depends on
5609 subclasses of target machine, selected by command-line options when GCC
5610 is run. This is just like the condition of a @code{define_insn} that
5611 has a standard name. Therefore, the condition (if present) may not
5612 depend on the data in the insn being matched, but only the
5613 target-machine-type flags. The compiler needs to test these conditions
5614 during initialization in order to learn exactly which named instructions
5615 are available in a particular run.
5618 The preparation statements, a string containing zero or more C
5619 statements which are to be executed before RTL code is generated from
5622 Usually these statements prepare temporary registers for use as
5623 internal operands in the RTL template, but they can also generate RTL
5624 insns directly by calling routines such as @code{emit_insn}, etc.
5625 Any such insns precede the ones that come from the RTL template.
5628 Every RTL insn emitted by a @code{define_expand} must match some
5629 @code{define_insn} in the machine description. Otherwise, the compiler
5630 will crash when trying to generate code for the insn or trying to optimize
5633 The RTL template, in addition to controlling generation of RTL insns,
5634 also describes the operands that need to be specified when this pattern
5635 is used. In particular, it gives a predicate for each operand.
5637 A true operand, which needs to be specified in order to generate RTL from
5638 the pattern, should be described with a @code{match_operand} in its first
5639 occurrence in the RTL template. This enters information on the operand's
5640 predicate into the tables that record such things. GCC uses the
5641 information to preload the operand into a register if that is required for
5642 valid RTL code. If the operand is referred to more than once, subsequent
5643 references should use @code{match_dup}.
5645 The RTL template may also refer to internal ``operands'' which are
5646 temporary registers or labels used only within the sequence made by the
5647 @code{define_expand}. Internal operands are substituted into the RTL
5648 template with @code{match_dup}, never with @code{match_operand}. The
5649 values of the internal operands are not passed in as arguments by the
5650 compiler when it requests use of this pattern. Instead, they are computed
5651 within the pattern, in the preparation statements. These statements
5652 compute the values and store them into the appropriate elements of
5653 @code{operands} so that @code{match_dup} can find them.
5655 There are two special macros defined for use in the preparation statements:
5656 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
5663 Use the @code{DONE} macro to end RTL generation for the pattern. The
5664 only RTL insns resulting from the pattern on this occasion will be
5665 those already emitted by explicit calls to @code{emit_insn} within the
5666 preparation statements; the RTL template will not be generated.
5670 Make the pattern fail on this occasion. When a pattern fails, it means
5671 that the pattern was not truly available. The calling routines in the
5672 compiler will try other strategies for code generation using other patterns.
5674 Failure is currently supported only for binary (addition, multiplication,
5675 shifting, etc.) and bit-field (@code{extv}, @code{extzv}, and @code{insv})
5679 If the preparation falls through (invokes neither @code{DONE} nor
5680 @code{FAIL}), then the @code{define_expand} acts like a
5681 @code{define_insn} in that the RTL template is used to generate the
5684 The RTL template is not used for matching, only for generating the
5685 initial insn list. If the preparation statement always invokes
5686 @code{DONE} or @code{FAIL}, the RTL template may be reduced to a simple
5687 list of operands, such as this example:
5691 (define_expand "addsi3"
5692 [(match_operand:SI 0 "register_operand" "")
5693 (match_operand:SI 1 "register_operand" "")
5694 (match_operand:SI 2 "register_operand" "")]
5700 handle_add (operands[0], operands[1], operands[2]);
5706 Here is an example, the definition of left-shift for the SPUR chip:
5710 (define_expand "ashlsi3"
5711 [(set (match_operand:SI 0 "register_operand" "")
5715 (match_operand:SI 1 "register_operand" "")
5716 (match_operand:SI 2 "nonmemory_operand" "")))]
5725 if (GET_CODE (operands[2]) != CONST_INT
5726 || (unsigned) INTVAL (operands[2]) > 3)
5733 This example uses @code{define_expand} so that it can generate an RTL insn
5734 for shifting when the shift-count is in the supported range of 0 to 3 but
5735 fail in other cases where machine insns aren't available. When it fails,
5736 the compiler tries another strategy using different patterns (such as, a
5739 If the compiler were able to handle nontrivial condition-strings in
5740 patterns with names, then it would be possible to use a
5741 @code{define_insn} in that case. Here is another case (zero-extension
5742 on the 68000) which makes more use of the power of @code{define_expand}:
5745 (define_expand "zero_extendhisi2"
5746 [(set (match_operand:SI 0 "general_operand" "")
5748 (set (strict_low_part
5752 (match_operand:HI 1 "general_operand" ""))]
5754 "operands[1] = make_safe_from (operands[1], operands[0]);")
5758 @findex make_safe_from
5759 Here two RTL insns are generated, one to clear the entire output operand
5760 and the other to copy the input operand into its low half. This sequence
5761 is incorrect if the input operand refers to [the old value of] the output
5762 operand, so the preparation statement makes sure this isn't so. The
5763 function @code{make_safe_from} copies the @code{operands[1]} into a
5764 temporary register if it refers to @code{operands[0]}. It does this
5765 by emitting another RTL insn.
5767 Finally, a third example shows the use of an internal operand.
5768 Zero-extension on the SPUR chip is done by @code{and}-ing the result
5769 against a halfword mask. But this mask cannot be represented by a
5770 @code{const_int} because the constant value is too large to be legitimate
5771 on this machine. So it must be copied into a register with
5772 @code{force_reg} and then the register used in the @code{and}.
5775 (define_expand "zero_extendhisi2"
5776 [(set (match_operand:SI 0 "register_operand" "")
5778 (match_operand:HI 1 "register_operand" "")
5783 = force_reg (SImode, GEN_INT (65535)); ")
5786 @emph{Note:} If the @code{define_expand} is used to serve a
5787 standard binary or unary arithmetic operation or a bit-field operation,
5788 then the last insn it generates must not be a @code{code_label},
5789 @code{barrier} or @code{note}. It must be an @code{insn},
5790 @code{jump_insn} or @code{call_insn}. If you don't need a real insn
5791 at the end, emit an insn to copy the result of the operation into
5792 itself. Such an insn will generate no code, but it can avoid problems
5797 @node Insn Splitting
5798 @section Defining How to Split Instructions
5799 @cindex insn splitting
5800 @cindex instruction splitting
5801 @cindex splitting instructions
5803 There are two cases where you should specify how to split a pattern
5804 into multiple insns. On machines that have instructions requiring
5805 delay slots (@pxref{Delay Slots}) or that have instructions whose
5806 output is not available for multiple cycles (@pxref{Processor pipeline
5807 description}), the compiler phases that optimize these cases need to
5808 be able to move insns into one-instruction delay slots. However, some
5809 insns may generate more than one machine instruction. These insns
5810 cannot be placed into a delay slot.
5812 Often you can rewrite the single insn as a list of individual insns,
5813 each corresponding to one machine instruction. The disadvantage of
5814 doing so is that it will cause the compilation to be slower and require
5815 more space. If the resulting insns are too complex, it may also
5816 suppress some optimizations. The compiler splits the insn if there is a
5817 reason to believe that it might improve instruction or delay slot
5820 The insn combiner phase also splits putative insns. If three insns are
5821 merged into one insn with a complex expression that cannot be matched by
5822 some @code{define_insn} pattern, the combiner phase attempts to split
5823 the complex pattern into two insns that are recognized. Usually it can
5824 break the complex pattern into two patterns by splitting out some
5825 subexpression. However, in some other cases, such as performing an
5826 addition of a large constant in two insns on a RISC machine, the way to
5827 split the addition into two insns is machine-dependent.
5829 @findex define_split
5830 The @code{define_split} definition tells the compiler how to split a
5831 complex insn into several simpler insns. It looks like this:
5835 [@var{insn-pattern}]
5837 [@var{new-insn-pattern-1}
5838 @var{new-insn-pattern-2}
5840 "@var{preparation-statements}")
5843 @var{insn-pattern} is a pattern that needs to be split and
5844 @var{condition} is the final condition to be tested, as in a
5845 @code{define_insn}. When an insn matching @var{insn-pattern} and
5846 satisfying @var{condition} is found, it is replaced in the insn list
5847 with the insns given by @var{new-insn-pattern-1},
5848 @var{new-insn-pattern-2}, etc.
5850 The @var{preparation-statements} are similar to those statements that
5851 are specified for @code{define_expand} (@pxref{Expander Definitions})
5852 and are executed before the new RTL is generated to prepare for the
5853 generated code or emit some insns whose pattern is not fixed. Unlike
5854 those in @code{define_expand}, however, these statements must not
5855 generate any new pseudo-registers. Once reload has completed, they also
5856 must not allocate any space in the stack frame.
5858 Patterns are matched against @var{insn-pattern} in two different
5859 circumstances. If an insn needs to be split for delay slot scheduling
5860 or insn scheduling, the insn is already known to be valid, which means
5861 that it must have been matched by some @code{define_insn} and, if
5862 @code{reload_completed} is nonzero, is known to satisfy the constraints
5863 of that @code{define_insn}. In that case, the new insn patterns must
5864 also be insns that are matched by some @code{define_insn} and, if
5865 @code{reload_completed} is nonzero, must also satisfy the constraints
5866 of those definitions.
5868 As an example of this usage of @code{define_split}, consider the following
5869 example from @file{a29k.md}, which splits a @code{sign_extend} from
5870 @code{HImode} to @code{SImode} into a pair of shift insns:
5874 [(set (match_operand:SI 0 "gen_reg_operand" "")
5875 (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
5878 (ashift:SI (match_dup 1)
5881 (ashiftrt:SI (match_dup 0)
5884 @{ operands[1] = gen_lowpart (SImode, operands[1]); @}")
5887 When the combiner phase tries to split an insn pattern, it is always the
5888 case that the pattern is @emph{not} matched by any @code{define_insn}.
5889 The combiner pass first tries to split a single @code{set} expression
5890 and then the same @code{set} expression inside a @code{parallel}, but
5891 followed by a @code{clobber} of a pseudo-reg to use as a scratch
5892 register. In these cases, the combiner expects exactly two new insn
5893 patterns to be generated. It will verify that these patterns match some
5894 @code{define_insn} definitions, so you need not do this test in the
5895 @code{define_split} (of course, there is no point in writing a
5896 @code{define_split} that will never produce insns that match).
5898 Here is an example of this use of @code{define_split}, taken from
5903 [(set (match_operand:SI 0 "gen_reg_operand" "")
5904 (plus:SI (match_operand:SI 1 "gen_reg_operand" "")
5905 (match_operand:SI 2 "non_add_cint_operand" "")))]
5907 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
5908 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
5911 int low = INTVAL (operands[2]) & 0xffff;
5912 int high = (unsigned) INTVAL (operands[2]) >> 16;
5915 high++, low |= 0xffff0000;
5917 operands[3] = GEN_INT (high << 16);
5918 operands[4] = GEN_INT (low);
5922 Here the predicate @code{non_add_cint_operand} matches any
5923 @code{const_int} that is @emph{not} a valid operand of a single add
5924 insn. The add with the smaller displacement is written so that it
5925 can be substituted into the address of a subsequent operation.
5927 An example that uses a scratch register, from the same file, generates
5928 an equality comparison of a register and a large constant:
5932 [(set (match_operand:CC 0 "cc_reg_operand" "")
5933 (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
5934 (match_operand:SI 2 "non_short_cint_operand" "")))
5935 (clobber (match_operand:SI 3 "gen_reg_operand" ""))]
5936 "find_single_use (operands[0], insn, 0)
5937 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
5938 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
5939 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
5940 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
5943 /* @r{Get the constant we are comparing against, C, and see what it
5944 looks like sign-extended to 16 bits. Then see what constant
5945 could be XOR'ed with C to get the sign-extended value.} */
5947 int c = INTVAL (operands[2]);
5948 int sextc = (c << 16) >> 16;
5949 int xorv = c ^ sextc;
5951 operands[4] = GEN_INT (xorv);
5952 operands[5] = GEN_INT (sextc);
5956 To avoid confusion, don't write a single @code{define_split} that
5957 accepts some insns that match some @code{define_insn} as well as some
5958 insns that don't. Instead, write two separate @code{define_split}
5959 definitions, one for the insns that are valid and one for the insns that
5962 The splitter is allowed to split jump instructions into sequence of
5963 jumps or create new jumps in while splitting non-jump instructions. As
5964 the central flowgraph and branch prediction information needs to be updated,
5965 several restriction apply.
5967 Splitting of jump instruction into sequence that over by another jump
5968 instruction is always valid, as compiler expect identical behavior of new
5969 jump. When new sequence contains multiple jump instructions or new labels,
5970 more assistance is needed. Splitter is required to create only unconditional
5971 jumps, or simple conditional jump instructions. Additionally it must attach a
5972 @code{REG_BR_PROB} note to each conditional jump. A global variable
5973 @code{split_branch_probability} holds the probability of the original branch in case
5974 it was an simple conditional jump, @minus{}1 otherwise. To simplify
5975 recomputing of edge frequencies, the new sequence is required to have only
5976 forward jumps to the newly created labels.
5978 @findex define_insn_and_split
5979 For the common case where the pattern of a define_split exactly matches the
5980 pattern of a define_insn, use @code{define_insn_and_split}. It looks like
5984 (define_insn_and_split
5985 [@var{insn-pattern}]
5987 "@var{output-template}"
5988 "@var{split-condition}"
5989 [@var{new-insn-pattern-1}
5990 @var{new-insn-pattern-2}
5992 "@var{preparation-statements}"
5993 [@var{insn-attributes}])
5997 @var{insn-pattern}, @var{condition}, @var{output-template}, and
5998 @var{insn-attributes} are used as in @code{define_insn}. The
5999 @var{new-insn-pattern} vector and the @var{preparation-statements} are used as
6000 in a @code{define_split}. The @var{split-condition} is also used as in
6001 @code{define_split}, with the additional behavior that if the condition starts
6002 with @samp{&&}, the condition used for the split will be the constructed as a
6003 logical ``and'' of the split condition with the insn condition. For example,
6007 (define_insn_and_split "zero_extendhisi2_and"
6008 [(set (match_operand:SI 0 "register_operand" "=r")
6009 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
6010 (clobber (reg:CC 17))]
6011 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
6013 "&& reload_completed"
6014 [(parallel [(set (match_dup 0)
6015 (and:SI (match_dup 0) (const_int 65535)))
6016 (clobber (reg:CC 17))])]
6018 [(set_attr "type" "alu1")])
6022 In this case, the actual split condition will be
6023 @samp{TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed}.
6025 The @code{define_insn_and_split} construction provides exactly the same
6026 functionality as two separate @code{define_insn} and @code{define_split}
6027 patterns. It exists for compactness, and as a maintenance tool to prevent
6028 having to ensure the two patterns' templates match.
6032 @node Including Patterns
6033 @section Including Patterns in Machine Descriptions.
6034 @cindex insn includes
6037 The @code{include} pattern tells the compiler tools where to
6038 look for patterns that are in files other than in the file
6039 @file{.md}. This is used only at build time and there is no preprocessing allowed.
6053 (include "filestuff")
6057 Where @var{pathname} is a string that specifies the location of the file,
6058 specifies the include file to be in @file{gcc/config/target/filestuff}. The
6059 directory @file{gcc/config/target} is regarded as the default directory.
6062 Machine descriptions may be split up into smaller more manageable subsections
6063 and placed into subdirectories.
6069 (include "BOGUS/filestuff")
6073 the include file is specified to be in @file{gcc/config/@var{target}/BOGUS/filestuff}.
6075 Specifying an absolute path for the include file such as;
6078 (include "/u2/BOGUS/filestuff")
6081 is permitted but is not encouraged.
6083 @subsection RTL Generation Tool Options for Directory Search
6084 @cindex directory options .md
6085 @cindex options, directory search
6086 @cindex search options
6088 The @option{-I@var{dir}} option specifies directories to search for machine descriptions.
6093 genrecog -I/p1/abc/proc1 -I/p2/abcd/pro2 target.md
6098 Add the directory @var{dir} to the head of the list of directories to be
6099 searched for header files. This can be used to override a system machine definition
6100 file, substituting your own version, since these directories are
6101 searched before the default machine description file directories. If you use more than
6102 one @option{-I} option, the directories are scanned in left-to-right
6103 order; the standard default directory come after.
6108 @node Peephole Definitions
6109 @section Machine-Specific Peephole Optimizers
6110 @cindex peephole optimizer definitions
6111 @cindex defining peephole optimizers
6113 In addition to instruction patterns the @file{md} file may contain
6114 definitions of machine-specific peephole optimizations.
6116 The combiner does not notice certain peephole optimizations when the data
6117 flow in the program does not suggest that it should try them. For example,
6118 sometimes two consecutive insns related in purpose can be combined even
6119 though the second one does not appear to use a register computed in the
6120 first one. A machine-specific peephole optimizer can detect such
6123 There are two forms of peephole definitions that may be used. The
6124 original @code{define_peephole} is run at assembly output time to
6125 match insns and substitute assembly text. Use of @code{define_peephole}
6128 A newer @code{define_peephole2} matches insns and substitutes new
6129 insns. The @code{peephole2} pass is run after register allocation
6130 but before scheduling, which may result in much better code for
6131 targets that do scheduling.
6134 * define_peephole:: RTL to Text Peephole Optimizers
6135 * define_peephole2:: RTL to RTL Peephole Optimizers
6140 @node define_peephole
6141 @subsection RTL to Text Peephole Optimizers
6142 @findex define_peephole
6145 A definition looks like this:
6149 [@var{insn-pattern-1}
6150 @var{insn-pattern-2}
6154 "@var{optional-insn-attributes}")
6158 The last string operand may be omitted if you are not using any
6159 machine-specific information in this machine description. If present,
6160 it must obey the same rules as in a @code{define_insn}.
6162 In this skeleton, @var{insn-pattern-1} and so on are patterns to match
6163 consecutive insns. The optimization applies to a sequence of insns when
6164 @var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches
6165 the next, and so on.
6167 Each of the insns matched by a peephole must also match a
6168 @code{define_insn}. Peepholes are checked only at the last stage just
6169 before code generation, and only optionally. Therefore, any insn which
6170 would match a peephole but no @code{define_insn} will cause a crash in code
6171 generation in an unoptimized compilation, or at various optimization
6174 The operands of the insns are matched with @code{match_operands},
6175 @code{match_operator}, and @code{match_dup}, as usual. What is not
6176 usual is that the operand numbers apply to all the insn patterns in the
6177 definition. So, you can check for identical operands in two insns by
6178 using @code{match_operand} in one insn and @code{match_dup} in the
6181 The operand constraints used in @code{match_operand} patterns do not have
6182 any direct effect on the applicability of the peephole, but they will
6183 be validated afterward, so make sure your constraints are general enough
6184 to apply whenever the peephole matches. If the peephole matches
6185 but the constraints are not satisfied, the compiler will crash.
6187 It is safe to omit constraints in all the operands of the peephole; or
6188 you can write constraints which serve as a double-check on the criteria
6191 Once a sequence of insns matches the patterns, the @var{condition} is
6192 checked. This is a C expression which makes the final decision whether to
6193 perform the optimization (we do so if the expression is nonzero). If
6194 @var{condition} is omitted (in other words, the string is empty) then the
6195 optimization is applied to every sequence of insns that matches the
6198 The defined peephole optimizations are applied after register allocation
6199 is complete. Therefore, the peephole definition can check which
6200 operands have ended up in which kinds of registers, just by looking at
6203 @findex prev_active_insn
6204 The way to refer to the operands in @var{condition} is to write
6205 @code{operands[@var{i}]} for operand number @var{i} (as matched by
6206 @code{(match_operand @var{i} @dots{})}). Use the variable @code{insn}
6207 to refer to the last of the insns being matched; use
6208 @code{prev_active_insn} to find the preceding insns.
6210 @findex dead_or_set_p
6211 When optimizing computations with intermediate results, you can use
6212 @var{condition} to match only when the intermediate results are not used
6213 elsewhere. Use the C expression @code{dead_or_set_p (@var{insn},
6214 @var{op})}, where @var{insn} is the insn in which you expect the value
6215 to be used for the last time (from the value of @code{insn}, together
6216 with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate
6217 value (from @code{operands[@var{i}]}).
6219 Applying the optimization means replacing the sequence of insns with one
6220 new insn. The @var{template} controls ultimate output of assembler code
6221 for this combined insn. It works exactly like the template of a
6222 @code{define_insn}. Operand numbers in this template are the same ones
6223 used in matching the original sequence of insns.
6225 The result of a defined peephole optimizer does not need to match any of
6226 the insn patterns in the machine description; it does not even have an
6227 opportunity to match them. The peephole optimizer definition itself serves
6228 as the insn pattern to control how the insn is output.
6230 Defined peephole optimizers are run as assembler code is being output,
6231 so the insns they produce are never combined or rearranged in any way.
6233 Here is an example, taken from the 68000 machine description:
6237 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
6238 (set (match_operand:DF 0 "register_operand" "=f")
6239 (match_operand:DF 1 "register_operand" "ad"))]
6240 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
6243 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
6245 output_asm_insn ("move.l %1,(sp)", xoperands);
6246 output_asm_insn ("move.l %1,-(sp)", operands);
6247 return "fmove.d (sp)+,%0";
6249 output_asm_insn ("movel %1,sp@@", xoperands);
6250 output_asm_insn ("movel %1,sp@@-", operands);
6251 return "fmoved sp@@+,%0";
6257 The effect of this optimization is to change
6283 If a peephole matches a sequence including one or more jump insns, you must
6284 take account of the flags such as @code{CC_REVERSED} which specify that the
6285 condition codes are represented in an unusual manner. The compiler
6286 automatically alters any ordinary conditional jumps which occur in such
6287 situations, but the compiler cannot alter jumps which have been replaced by
6288 peephole optimizations. So it is up to you to alter the assembler code
6289 that the peephole produces. Supply C code to write the assembler output,
6290 and in this C code check the condition code status flags and change the
6291 assembler code as appropriate.
6294 @var{insn-pattern-1} and so on look @emph{almost} like the second
6295 operand of @code{define_insn}. There is one important difference: the
6296 second operand of @code{define_insn} consists of one or more RTX's
6297 enclosed in square brackets. Usually, there is only one: then the same
6298 action can be written as an element of a @code{define_peephole}. But
6299 when there are multiple actions in a @code{define_insn}, they are
6300 implicitly enclosed in a @code{parallel}. Then you must explicitly
6301 write the @code{parallel}, and the square brackets within it, in the
6302 @code{define_peephole}. Thus, if an insn pattern looks like this,
6305 (define_insn "divmodsi4"
6306 [(set (match_operand:SI 0 "general_operand" "=d")
6307 (div:SI (match_operand:SI 1 "general_operand" "0")
6308 (match_operand:SI 2 "general_operand" "dmsK")))
6309 (set (match_operand:SI 3 "general_operand" "=d")
6310 (mod:SI (match_dup 1) (match_dup 2)))]
6312 "divsl%.l %2,%3:%0")
6316 then the way to mention this insn in a peephole is as follows:
6322 [(set (match_operand:SI 0 "general_operand" "=d")
6323 (div:SI (match_operand:SI 1 "general_operand" "0")
6324 (match_operand:SI 2 "general_operand" "dmsK")))
6325 (set (match_operand:SI 3 "general_operand" "=d")
6326 (mod:SI (match_dup 1) (match_dup 2)))])
6333 @node define_peephole2
6334 @subsection RTL to RTL Peephole Optimizers
6335 @findex define_peephole2
6337 The @code{define_peephole2} definition tells the compiler how to
6338 substitute one sequence of instructions for another sequence,
6339 what additional scratch registers may be needed and what their
6344 [@var{insn-pattern-1}
6345 @var{insn-pattern-2}
6348 [@var{new-insn-pattern-1}
6349 @var{new-insn-pattern-2}
6351 "@var{preparation-statements}")
6354 The definition is almost identical to @code{define_split}
6355 (@pxref{Insn Splitting}) except that the pattern to match is not a
6356 single instruction, but a sequence of instructions.
6358 It is possible to request additional scratch registers for use in the
6359 output template. If appropriate registers are not free, the pattern
6360 will simply not match.
6362 @findex match_scratch
6364 Scratch registers are requested with a @code{match_scratch} pattern at
6365 the top level of the input pattern. The allocated register (initially) will
6366 be dead at the point requested within the original sequence. If the scratch
6367 is used at more than a single point, a @code{match_dup} pattern at the
6368 top level of the input pattern marks the last position in the input sequence
6369 at which the register must be available.
6371 Here is an example from the IA-32 machine description:
6375 [(match_scratch:SI 2 "r")
6376 (parallel [(set (match_operand:SI 0 "register_operand" "")
6377 (match_operator:SI 3 "arith_or_logical_operator"
6379 (match_operand:SI 1 "memory_operand" "")]))
6380 (clobber (reg:CC 17))])]
6381 "! optimize_size && ! TARGET_READ_MODIFY"
6382 [(set (match_dup 2) (match_dup 1))
6383 (parallel [(set (match_dup 0)
6384 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
6385 (clobber (reg:CC 17))])]
6390 This pattern tries to split a load from its use in the hopes that we'll be
6391 able to schedule around the memory load latency. It allocates a single
6392 @code{SImode} register of class @code{GENERAL_REGS} (@code{"r"}) that needs
6393 to be live only at the point just before the arithmetic.
6395 A real example requiring extended scratch lifetimes is harder to come by,
6396 so here's a silly made-up example:
6400 [(match_scratch:SI 4 "r")
6401 (set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
6402 (set (match_operand:SI 2 "" "") (match_dup 1))
6404 (set (match_operand:SI 3 "" "") (match_dup 1))]
6405 "/* @r{determine 1 does not overlap 0 and 2} */"
6406 [(set (match_dup 4) (match_dup 1))
6407 (set (match_dup 0) (match_dup 4))
6408 (set (match_dup 2) (match_dup 4))]
6409 (set (match_dup 3) (match_dup 4))]
6414 If we had not added the @code{(match_dup 4)} in the middle of the input
6415 sequence, it might have been the case that the register we chose at the
6416 beginning of the sequence is killed by the first or second @code{set}.
6420 @node Insn Attributes
6421 @section Instruction Attributes
6422 @cindex insn attributes
6423 @cindex instruction attributes
6425 In addition to describing the instruction supported by the target machine,
6426 the @file{md} file also defines a group of @dfn{attributes} and a set of
6427 values for each. Every generated insn is assigned a value for each attribute.
6428 One possible attribute would be the effect that the insn has on the machine's
6429 condition code. This attribute can then be used by @code{NOTICE_UPDATE_CC}
6430 to track the condition codes.
6433 * Defining Attributes:: Specifying attributes and their values.
6434 * Expressions:: Valid expressions for attribute values.
6435 * Tagging Insns:: Assigning attribute values to insns.
6436 * Attr Example:: An example of assigning attributes.
6437 * Insn Lengths:: Computing the length of insns.
6438 * Constant Attributes:: Defining attributes that are constant.
6439 * Delay Slots:: Defining delay slots required for a machine.
6440 * Processor pipeline description:: Specifying information for insn scheduling.
6445 @node Defining Attributes
6446 @subsection Defining Attributes and their Values
6447 @cindex defining attributes and their values
6448 @cindex attributes, defining
6451 The @code{define_attr} expression is used to define each attribute required
6452 by the target machine. It looks like:
6455 (define_attr @var{name} @var{list-of-values} @var{default})
6458 @var{name} is a string specifying the name of the attribute being defined.
6460 @var{list-of-values} is either a string that specifies a comma-separated
6461 list of values that can be assigned to the attribute, or a null string to
6462 indicate that the attribute takes numeric values.
6464 @var{default} is an attribute expression that gives the value of this
6465 attribute for insns that match patterns whose definition does not include
6466 an explicit value for this attribute. @xref{Attr Example}, for more
6467 information on the handling of defaults. @xref{Constant Attributes},
6468 for information on attributes that do not depend on any particular insn.
6471 For each defined attribute, a number of definitions are written to the
6472 @file{insn-attr.h} file. For cases where an explicit set of values is
6473 specified for an attribute, the following are defined:
6477 A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}.
6480 An enumerated class is defined for @samp{attr_@var{name}} with
6481 elements of the form @samp{@var{upper-name}_@var{upper-value}} where
6482 the attribute name and value are first converted to uppercase.
6485 A function @samp{get_attr_@var{name}} is defined that is passed an insn and
6486 returns the attribute value for that insn.
6489 For example, if the following is present in the @file{md} file:
6492 (define_attr "type" "branch,fp,load,store,arith" @dots{})
6496 the following lines will be written to the file @file{insn-attr.h}.
6499 #define HAVE_ATTR_type
6500 enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD,
6501 TYPE_STORE, TYPE_ARITH@};
6502 extern enum attr_type get_attr_type ();
6505 If the attribute takes numeric values, no @code{enum} type will be
6506 defined and the function to obtain the attribute's value will return
6512 @subsection Attribute Expressions
6513 @cindex attribute expressions
6515 RTL expressions used to define attributes use the codes described above
6516 plus a few specific to attribute definitions, to be discussed below.
6517 Attribute value expressions must have one of the following forms:
6520 @cindex @code{const_int} and attributes
6521 @item (const_int @var{i})
6522 The integer @var{i} specifies the value of a numeric attribute. @var{i}
6523 must be non-negative.
6525 The value of a numeric attribute can be specified either with a
6526 @code{const_int}, or as an integer represented as a string in
6527 @code{const_string}, @code{eq_attr} (see below), @code{attr},
6528 @code{symbol_ref}, simple arithmetic expressions, and @code{set_attr}
6529 overrides on specific instructions (@pxref{Tagging Insns}).
6531 @cindex @code{const_string} and attributes
6532 @item (const_string @var{value})
6533 The string @var{value} specifies a constant attribute value.
6534 If @var{value} is specified as @samp{"*"}, it means that the default value of
6535 the attribute is to be used for the insn containing this expression.
6536 @samp{"*"} obviously cannot be used in the @var{default} expression
6537 of a @code{define_attr}.
6539 If the attribute whose value is being specified is numeric, @var{value}
6540 must be a string containing a non-negative integer (normally
6541 @code{const_int} would be used in this case). Otherwise, it must
6542 contain one of the valid values for the attribute.
6544 @cindex @code{if_then_else} and attributes
6545 @item (if_then_else @var{test} @var{true-value} @var{false-value})
6546 @var{test} specifies an attribute test, whose format is defined below.
6547 The value of this expression is @var{true-value} if @var{test} is true,
6548 otherwise it is @var{false-value}.
6550 @cindex @code{cond} and attributes
6551 @item (cond [@var{test1} @var{value1} @dots{}] @var{default})
6552 The first operand of this expression is a vector containing an even
6553 number of expressions and consisting of pairs of @var{test} and @var{value}
6554 expressions. The value of the @code{cond} expression is that of the
6555 @var{value} corresponding to the first true @var{test} expression. If
6556 none of the @var{test} expressions are true, the value of the @code{cond}
6557 expression is that of the @var{default} expression.
6560 @var{test} expressions can have one of the following forms:
6563 @cindex @code{const_int} and attribute tests
6564 @item (const_int @var{i})
6565 This test is true if @var{i} is nonzero and false otherwise.
6567 @cindex @code{not} and attributes
6568 @cindex @code{ior} and attributes
6569 @cindex @code{and} and attributes
6570 @item (not @var{test})
6571 @itemx (ior @var{test1} @var{test2})
6572 @itemx (and @var{test1} @var{test2})
6573 These tests are true if the indicated logical function is true.
6575 @cindex @code{match_operand} and attributes
6576 @item (match_operand:@var{m} @var{n} @var{pred} @var{constraints})
6577 This test is true if operand @var{n} of the insn whose attribute value
6578 is being determined has mode @var{m} (this part of the test is ignored
6579 if @var{m} is @code{VOIDmode}) and the function specified by the string
6580 @var{pred} returns a nonzero value when passed operand @var{n} and mode
6581 @var{m} (this part of the test is ignored if @var{pred} is the null
6584 The @var{constraints} operand is ignored and should be the null string.
6586 @cindex @code{le} and attributes
6587 @cindex @code{leu} and attributes
6588 @cindex @code{lt} and attributes
6589 @cindex @code{gt} and attributes
6590 @cindex @code{gtu} and attributes
6591 @cindex @code{ge} and attributes
6592 @cindex @code{geu} and attributes
6593 @cindex @code{ne} and attributes
6594 @cindex @code{eq} and attributes
6595 @cindex @code{plus} and attributes
6596 @cindex @code{minus} and attributes
6597 @cindex @code{mult} and attributes
6598 @cindex @code{div} and attributes
6599 @cindex @code{mod} and attributes
6600 @cindex @code{abs} and attributes
6601 @cindex @code{neg} and attributes
6602 @cindex @code{ashift} and attributes
6603 @cindex @code{lshiftrt} and attributes
6604 @cindex @code{ashiftrt} and attributes
6605 @item (le @var{arith1} @var{arith2})
6606 @itemx (leu @var{arith1} @var{arith2})
6607 @itemx (lt @var{arith1} @var{arith2})
6608 @itemx (ltu @var{arith1} @var{arith2})
6609 @itemx (gt @var{arith1} @var{arith2})
6610 @itemx (gtu @var{arith1} @var{arith2})
6611 @itemx (ge @var{arith1} @var{arith2})
6612 @itemx (geu @var{arith1} @var{arith2})
6613 @itemx (ne @var{arith1} @var{arith2})
6614 @itemx (eq @var{arith1} @var{arith2})
6615 These tests are true if the indicated comparison of the two arithmetic
6616 expressions is true. Arithmetic expressions are formed with
6617 @code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod},
6618 @code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not},
6619 @code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions.
6622 @code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn
6623 Lengths},for additional forms). @code{symbol_ref} is a string
6624 denoting a C expression that yields an @code{int} when evaluated by the
6625 @samp{get_attr_@dots{}} routine. It should normally be a global
6629 @item (eq_attr @var{name} @var{value})
6630 @var{name} is a string specifying the name of an attribute.
6632 @var{value} is a string that is either a valid value for attribute
6633 @var{name}, a comma-separated list of values, or @samp{!} followed by a
6634 value or list. If @var{value} does not begin with a @samp{!}, this
6635 test is true if the value of the @var{name} attribute of the current
6636 insn is in the list specified by @var{value}. If @var{value} begins
6637 with a @samp{!}, this test is true if the attribute's value is
6638 @emph{not} in the specified list.
6643 (eq_attr "type" "load,store")
6650 (ior (eq_attr "type" "load") (eq_attr "type" "store"))
6653 If @var{name} specifies an attribute of @samp{alternative}, it refers to the
6654 value of the compiler variable @code{which_alternative}
6655 (@pxref{Output Statement}) and the values must be small integers. For
6659 (eq_attr "alternative" "2,3")
6666 (ior (eq (symbol_ref "which_alternative") (const_int 2))
6667 (eq (symbol_ref "which_alternative") (const_int 3)))
6670 Note that, for most attributes, an @code{eq_attr} test is simplified in cases
6671 where the value of the attribute being tested is known for all insns matching
6672 a particular pattern. This is by far the most common case.
6675 @item (attr_flag @var{name})
6676 The value of an @code{attr_flag} expression is true if the flag
6677 specified by @var{name} is true for the @code{insn} currently being
6680 @var{name} is a string specifying one of a fixed set of flags to test.
6681 Test the flags @code{forward} and @code{backward} to determine the
6682 direction of a conditional branch. Test the flags @code{very_likely},
6683 @code{likely}, @code{very_unlikely}, and @code{unlikely} to determine
6684 if a conditional branch is expected to be taken.
6686 If the @code{very_likely} flag is true, then the @code{likely} flag is also
6687 true. Likewise for the @code{very_unlikely} and @code{unlikely} flags.
6689 This example describes a conditional branch delay slot which
6690 can be nullified for forward branches that are taken (annul-true) or
6691 for backward branches which are not taken (annul-false).
6694 (define_delay (eq_attr "type" "cbranch")
6695 [(eq_attr "in_branch_delay" "true")
6696 (and (eq_attr "in_branch_delay" "true")
6697 (attr_flag "forward"))
6698 (and (eq_attr "in_branch_delay" "true")
6699 (attr_flag "backward"))])
6702 The @code{forward} and @code{backward} flags are false if the current
6703 @code{insn} being scheduled is not a conditional branch.
6705 The @code{very_likely} and @code{likely} flags are true if the
6706 @code{insn} being scheduled is not a conditional branch.
6707 The @code{very_unlikely} and @code{unlikely} flags are false if the
6708 @code{insn} being scheduled is not a conditional branch.
6710 @code{attr_flag} is only used during delay slot scheduling and has no
6711 meaning to other passes of the compiler.
6714 @item (attr @var{name})
6715 The value of another attribute is returned. This is most useful
6716 for numeric attributes, as @code{eq_attr} and @code{attr_flag}
6717 produce more efficient code for non-numeric attributes.
6723 @subsection Assigning Attribute Values to Insns
6724 @cindex tagging insns
6725 @cindex assigning attribute values to insns
6727 The value assigned to an attribute of an insn is primarily determined by
6728 which pattern is matched by that insn (or which @code{define_peephole}
6729 generated it). Every @code{define_insn} and @code{define_peephole} can
6730 have an optional last argument to specify the values of attributes for
6731 matching insns. The value of any attribute not specified in a particular
6732 insn is set to the default value for that attribute, as specified in its
6733 @code{define_attr}. Extensive use of default values for attributes
6734 permits the specification of the values for only one or two attributes
6735 in the definition of most insn patterns, as seen in the example in the
6738 The optional last argument of @code{define_insn} and
6739 @code{define_peephole} is a vector of expressions, each of which defines
6740 the value for a single attribute. The most general way of assigning an
6741 attribute's value is to use a @code{set} expression whose first operand is an
6742 @code{attr} expression giving the name of the attribute being set. The
6743 second operand of the @code{set} is an attribute expression
6744 (@pxref{Expressions}) giving the value of the attribute.
6746 When the attribute value depends on the @samp{alternative} attribute
6747 (i.e., which is the applicable alternative in the constraint of the
6748 insn), the @code{set_attr_alternative} expression can be used. It
6749 allows the specification of a vector of attribute expressions, one for
6753 When the generality of arbitrary attribute expressions is not required,
6754 the simpler @code{set_attr} expression can be used, which allows
6755 specifying a string giving either a single attribute value or a list
6756 of attribute values, one for each alternative.
6758 The form of each of the above specifications is shown below. In each case,
6759 @var{name} is a string specifying the attribute to be set.
6762 @item (set_attr @var{name} @var{value-string})
6763 @var{value-string} is either a string giving the desired attribute value,
6764 or a string containing a comma-separated list giving the values for
6765 succeeding alternatives. The number of elements must match the number
6766 of alternatives in the constraint of the insn pattern.
6768 Note that it may be useful to specify @samp{*} for some alternative, in
6769 which case the attribute will assume its default value for insns matching
6772 @findex set_attr_alternative
6773 @item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}])
6774 Depending on the alternative of the insn, the value will be one of the
6775 specified values. This is a shorthand for using a @code{cond} with
6776 tests on the @samp{alternative} attribute.
6779 @item (set (attr @var{name}) @var{value})
6780 The first operand of this @code{set} must be the special RTL expression
6781 @code{attr}, whose sole operand is a string giving the name of the
6782 attribute being set. @var{value} is the value of the attribute.
6785 The following shows three different ways of representing the same
6786 attribute value specification:
6789 (set_attr "type" "load,store,arith")
6791 (set_attr_alternative "type"
6792 [(const_string "load") (const_string "store")
6793 (const_string "arith")])
6796 (cond [(eq_attr "alternative" "1") (const_string "load")
6797 (eq_attr "alternative" "2") (const_string "store")]
6798 (const_string "arith")))
6802 @findex define_asm_attributes
6803 The @code{define_asm_attributes} expression provides a mechanism to
6804 specify the attributes assigned to insns produced from an @code{asm}
6805 statement. It has the form:
6808 (define_asm_attributes [@var{attr-sets}])
6812 where @var{attr-sets} is specified the same as for both the
6813 @code{define_insn} and the @code{define_peephole} expressions.
6815 These values will typically be the ``worst case'' attribute values. For
6816 example, they might indicate that the condition code will be clobbered.
6818 A specification for a @code{length} attribute is handled specially. The
6819 way to compute the length of an @code{asm} insn is to multiply the
6820 length specified in the expression @code{define_asm_attributes} by the
6821 number of machine instructions specified in the @code{asm} statement,
6822 determined by counting the number of semicolons and newlines in the
6823 string. Therefore, the value of the @code{length} attribute specified
6824 in a @code{define_asm_attributes} should be the maximum possible length
6825 of a single machine instruction.
6830 @subsection Example of Attribute Specifications
6831 @cindex attribute specifications example
6832 @cindex attribute specifications
6834 The judicious use of defaulting is important in the efficient use of
6835 insn attributes. Typically, insns are divided into @dfn{types} and an
6836 attribute, customarily called @code{type}, is used to represent this
6837 value. This attribute is normally used only to define the default value
6838 for other attributes. An example will clarify this usage.
6840 Assume we have a RISC machine with a condition code and in which only
6841 full-word operations are performed in registers. Let us assume that we
6842 can divide all insns into loads, stores, (integer) arithmetic
6843 operations, floating point operations, and branches.
6845 Here we will concern ourselves with determining the effect of an insn on
6846 the condition code and will limit ourselves to the following possible
6847 effects: The condition code can be set unpredictably (clobbered), not
6848 be changed, be set to agree with the results of the operation, or only
6849 changed if the item previously set into the condition code has been
6852 Here is part of a sample @file{md} file for such a machine:
6855 (define_attr "type" "load,store,arith,fp,branch" (const_string "arith"))
6857 (define_attr "cc" "clobber,unchanged,set,change0"
6858 (cond [(eq_attr "type" "load")
6859 (const_string "change0")
6860 (eq_attr "type" "store,branch")
6861 (const_string "unchanged")
6862 (eq_attr "type" "arith")
6863 (if_then_else (match_operand:SI 0 "" "")
6864 (const_string "set")
6865 (const_string "clobber"))]
6866 (const_string "clobber")))
6869 [(set (match_operand:SI 0 "general_operand" "=r,r,m")
6870 (match_operand:SI 1 "general_operand" "r,m,r"))]
6876 [(set_attr "type" "arith,load,store")])
6879 Note that we assume in the above example that arithmetic operations
6880 performed on quantities smaller than a machine word clobber the condition
6881 code since they will set the condition code to a value corresponding to the
6887 @subsection Computing the Length of an Insn
6888 @cindex insn lengths, computing
6889 @cindex computing the length of an insn
6891 For many machines, multiple types of branch instructions are provided, each
6892 for different length branch displacements. In most cases, the assembler
6893 will choose the correct instruction to use. However, when the assembler
6894 cannot do so, GCC can when a special attribute, the @code{length}
6895 attribute, is defined. This attribute must be defined to have numeric
6896 values by specifying a null string in its @code{define_attr}.
6898 In the case of the @code{length} attribute, two additional forms of
6899 arithmetic terms are allowed in test expressions:
6902 @cindex @code{match_dup} and attributes
6903 @item (match_dup @var{n})
6904 This refers to the address of operand @var{n} of the current insn, which
6905 must be a @code{label_ref}.
6907 @cindex @code{pc} and attributes
6909 This refers to the address of the @emph{current} insn. It might have
6910 been more consistent with other usage to make this the address of the
6911 @emph{next} insn but this would be confusing because the length of the
6912 current insn is to be computed.
6915 @cindex @code{addr_vec}, length of
6916 @cindex @code{addr_diff_vec}, length of
6917 For normal insns, the length will be determined by value of the
6918 @code{length} attribute. In the case of @code{addr_vec} and
6919 @code{addr_diff_vec} insn patterns, the length is computed as
6920 the number of vectors multiplied by the size of each vector.
6922 Lengths are measured in addressable storage units (bytes).
6924 The following macros can be used to refine the length computation:
6927 @findex ADJUST_INSN_LENGTH
6928 @item ADJUST_INSN_LENGTH (@var{insn}, @var{length})
6929 If defined, modifies the length assigned to instruction @var{insn} as a
6930 function of the context in which it is used. @var{length} is an lvalue
6931 that contains the initially computed length of the insn and should be
6932 updated with the correct length of the insn.
6934 This macro will normally not be required. A case in which it is
6935 required is the ROMP@. On this machine, the size of an @code{addr_vec}
6936 insn must be increased by two to compensate for the fact that alignment
6940 @findex get_attr_length
6941 The routine that returns @code{get_attr_length} (the value of the
6942 @code{length} attribute) can be used by the output routine to
6943 determine the form of the branch instruction to be written, as the
6944 example below illustrates.
6946 As an example of the specification of variable-length branches, consider
6947 the IBM 360. If we adopt the convention that a register will be set to
6948 the starting address of a function, we can jump to labels within 4k of
6949 the start using a four-byte instruction. Otherwise, we need a six-byte
6950 sequence to load the address from memory and then branch to it.
6952 On such a machine, a pattern for a branch instruction might be specified
6958 (label_ref (match_operand 0 "" "")))]
6961 return (get_attr_length (insn) == 4
6962 ? "b %l0" : "l r15,=a(%l0); br r15");
6964 [(set (attr "length")
6965 (if_then_else (lt (match_dup 0) (const_int 4096))
6972 @node Constant Attributes
6973 @subsection Constant Attributes
6974 @cindex constant attributes
6976 A special form of @code{define_attr}, where the expression for the
6977 default value is a @code{const} expression, indicates an attribute that
6978 is constant for a given run of the compiler. Constant attributes may be
6979 used to specify which variety of processor is used. For example,
6982 (define_attr "cpu" "m88100,m88110,m88000"
6984 (cond [(symbol_ref "TARGET_88100") (const_string "m88100")
6985 (symbol_ref "TARGET_88110") (const_string "m88110")]
6986 (const_string "m88000"))))
6988 (define_attr "memory" "fast,slow"
6990 (if_then_else (symbol_ref "TARGET_FAST_MEM")
6991 (const_string "fast")
6992 (const_string "slow"))))
6995 The routine generated for constant attributes has no parameters as it
6996 does not depend on any particular insn. RTL expressions used to define
6997 the value of a constant attribute may use the @code{symbol_ref} form,
6998 but may not use either the @code{match_operand} form or @code{eq_attr}
6999 forms involving insn attributes.
7004 @subsection Delay Slot Scheduling
7005 @cindex delay slots, defining
7007 The insn attribute mechanism can be used to specify the requirements for
7008 delay slots, if any, on a target machine. An instruction is said to
7009 require a @dfn{delay slot} if some instructions that are physically
7010 after the instruction are executed as if they were located before it.
7011 Classic examples are branch and call instructions, which often execute
7012 the following instruction before the branch or call is performed.
7014 On some machines, conditional branch instructions can optionally
7015 @dfn{annul} instructions in the delay slot. This means that the
7016 instruction will not be executed for certain branch outcomes. Both
7017 instructions that annul if the branch is true and instructions that
7018 annul if the branch is false are supported.
7020 Delay slot scheduling differs from instruction scheduling in that
7021 determining whether an instruction needs a delay slot is dependent only
7022 on the type of instruction being generated, not on data flow between the
7023 instructions. See the next section for a discussion of data-dependent
7024 instruction scheduling.
7026 @findex define_delay
7027 The requirement of an insn needing one or more delay slots is indicated
7028 via the @code{define_delay} expression. It has the following form:
7031 (define_delay @var{test}
7032 [@var{delay-1} @var{annul-true-1} @var{annul-false-1}
7033 @var{delay-2} @var{annul-true-2} @var{annul-false-2}
7037 @var{test} is an attribute test that indicates whether this
7038 @code{define_delay} applies to a particular insn. If so, the number of
7039 required delay slots is determined by the length of the vector specified
7040 as the second argument. An insn placed in delay slot @var{n} must
7041 satisfy attribute test @var{delay-n}. @var{annul-true-n} is an
7042 attribute test that specifies which insns may be annulled if the branch
7043 is true. Similarly, @var{annul-false-n} specifies which insns in the
7044 delay slot may be annulled if the branch is false. If annulling is not
7045 supported for that delay slot, @code{(nil)} should be coded.
7047 For example, in the common case where branch and call insns require
7048 a single delay slot, which may contain any insn other than a branch or
7049 call, the following would be placed in the @file{md} file:
7052 (define_delay (eq_attr "type" "branch,call")
7053 [(eq_attr "type" "!branch,call") (nil) (nil)])
7056 Multiple @code{define_delay} expressions may be specified. In this
7057 case, each such expression specifies different delay slot requirements
7058 and there must be no insn for which tests in two @code{define_delay}
7059 expressions are both true.
7061 For example, if we have a machine that requires one delay slot for branches
7062 but two for calls, no delay slot can contain a branch or call insn,
7063 and any valid insn in the delay slot for the branch can be annulled if the
7064 branch is true, we might represent this as follows:
7067 (define_delay (eq_attr "type" "branch")
7068 [(eq_attr "type" "!branch,call")
7069 (eq_attr "type" "!branch,call")
7072 (define_delay (eq_attr "type" "call")
7073 [(eq_attr "type" "!branch,call") (nil) (nil)
7074 (eq_attr "type" "!branch,call") (nil) (nil)])
7076 @c the above is *still* too long. --mew 4feb93
7080 @node Processor pipeline description
7081 @subsection Specifying processor pipeline description
7082 @cindex processor pipeline description
7083 @cindex processor functional units
7084 @cindex instruction latency time
7085 @cindex interlock delays
7086 @cindex data dependence delays
7087 @cindex reservation delays
7088 @cindex pipeline hazard recognizer
7089 @cindex automaton based pipeline description
7090 @cindex regular expressions
7091 @cindex deterministic finite state automaton
7092 @cindex automaton based scheduler
7096 To achieve better performance, most modern processors
7097 (super-pipelined, superscalar @acronym{RISC}, and @acronym{VLIW}
7098 processors) have many @dfn{functional units} on which several
7099 instructions can be executed simultaneously. An instruction starts
7100 execution if its issue conditions are satisfied. If not, the
7101 instruction is stalled until its conditions are satisfied. Such
7102 @dfn{interlock (pipeline) delay} causes interruption of the fetching
7103 of successor instructions (or demands nop instructions, e.g.@: for some
7106 There are two major kinds of interlock delays in modern processors.
7107 The first one is a data dependence delay determining @dfn{instruction
7108 latency time}. The instruction execution is not started until all
7109 source data have been evaluated by prior instructions (there are more
7110 complex cases when the instruction execution starts even when the data
7111 are not available but will be ready in given time after the
7112 instruction execution start). Taking the data dependence delays into
7113 account is simple. The data dependence (true, output, and
7114 anti-dependence) delay between two instructions is given by a
7115 constant. In most cases this approach is adequate. The second kind
7116 of interlock delays is a reservation delay. The reservation delay
7117 means that two instructions under execution will be in need of shared
7118 processors resources, i.e.@: buses, internal registers, and/or
7119 functional units, which are reserved for some time. Taking this kind
7120 of delay into account is complex especially for modern @acronym{RISC}
7123 The task of exploiting more processor parallelism is solved by an
7124 instruction scheduler. For a better solution to this problem, the
7125 instruction scheduler has to have an adequate description of the
7126 processor parallelism (or @dfn{pipeline description}). GCC
7127 machine descriptions describe processor parallelism and functional
7128 unit reservations for groups of instructions with the aid of
7129 @dfn{regular expressions}.
7131 The GCC instruction scheduler uses a @dfn{pipeline hazard recognizer} to
7132 figure out the possibility of the instruction issue by the processor
7133 on a given simulated processor cycle. The pipeline hazard recognizer is
7134 automatically generated from the processor pipeline description. The
7135 pipeline hazard recognizer generated from the machine description
7136 is based on a deterministic finite state automaton (@acronym{DFA}):
7137 the instruction issue is possible if there is a transition from one
7138 automaton state to another one. This algorithm is very fast, and
7139 furthermore, its speed is not dependent on processor
7140 complexity@footnote{However, the size of the automaton depends on
7141 processor complexity. To limit this effect, machine descriptions
7142 can split orthogonal parts of the machine description among several
7143 automata: but then, since each of these must be stepped independently,
7144 this does cause a small decrease in the algorithm's performance.}.
7146 @cindex automaton based pipeline description
7147 The rest of this section describes the directives that constitute
7148 an automaton-based processor pipeline description. The order of
7149 these constructions within the machine description file is not
7152 @findex define_automaton
7153 @cindex pipeline hazard recognizer
7154 The following optional construction describes names of automata
7155 generated and used for the pipeline hazards recognition. Sometimes
7156 the generated finite state automaton used by the pipeline hazard
7157 recognizer is large. If we use more than one automaton and bind functional
7158 units to the automata, the total size of the automata is usually
7159 less than the size of the single automaton. If there is no one such
7160 construction, only one finite state automaton is generated.
7163 (define_automaton @var{automata-names})
7166 @var{automata-names} is a string giving names of the automata. The
7167 names are separated by commas. All the automata should have unique names.
7168 The automaton name is used in the constructions @code{define_cpu_unit} and
7169 @code{define_query_cpu_unit}.
7171 @findex define_cpu_unit
7172 @cindex processor functional units
7173 Each processor functional unit used in the description of instruction
7174 reservations should be described by the following construction.
7177 (define_cpu_unit @var{unit-names} [@var{automaton-name}])
7180 @var{unit-names} is a string giving the names of the functional units
7181 separated by commas. Don't use name @samp{nothing}, it is reserved
7184 @var{automaton-name} is a string giving the name of the automaton with
7185 which the unit is bound. The automaton should be described in
7186 construction @code{define_automaton}. You should give
7187 @dfn{automaton-name}, if there is a defined automaton.
7189 The assignment of units to automata are constrained by the uses of the
7190 units in insn reservations. The most important constraint is: if a
7191 unit reservation is present on a particular cycle of an alternative
7192 for an insn reservation, then some unit from the same automaton must
7193 be present on the same cycle for the other alternatives of the insn
7194 reservation. The rest of the constraints are mentioned in the
7195 description of the subsequent constructions.
7197 @findex define_query_cpu_unit
7198 @cindex querying function unit reservations
7199 The following construction describes CPU functional units analogously
7200 to @code{define_cpu_unit}. The reservation of such units can be
7201 queried for an automaton state. The instruction scheduler never
7202 queries reservation of functional units for given automaton state. So
7203 as a rule, you don't need this construction. This construction could
7204 be used for future code generation goals (e.g.@: to generate
7205 @acronym{VLIW} insn templates).
7208 (define_query_cpu_unit @var{unit-names} [@var{automaton-name}])
7211 @var{unit-names} is a string giving names of the functional units
7212 separated by commas.
7214 @var{automaton-name} is a string giving the name of the automaton with
7215 which the unit is bound.
7217 @findex define_insn_reservation
7218 @cindex instruction latency time
7219 @cindex regular expressions
7221 The following construction is the major one to describe pipeline
7222 characteristics of an instruction.
7225 (define_insn_reservation @var{insn-name} @var{default_latency}
7226 @var{condition} @var{regexp})
7229 @var{default_latency} is a number giving latency time of the
7230 instruction. There is an important difference between the old
7231 description and the automaton based pipeline description. The latency
7232 time is used for all dependencies when we use the old description. In
7233 the automaton based pipeline description, the given latency time is only
7234 used for true dependencies. The cost of anti-dependencies is always
7235 zero and the cost of output dependencies is the difference between
7236 latency times of the producing and consuming insns (if the difference
7237 is negative, the cost is considered to be zero). You can always
7238 change the default costs for any description by using the target hook
7239 @code{TARGET_SCHED_ADJUST_COST} (@pxref{Scheduling}).
7241 @var{insn-name} is a string giving the internal name of the insn. The
7242 internal names are used in constructions @code{define_bypass} and in
7243 the automaton description file generated for debugging. The internal
7244 name has nothing in common with the names in @code{define_insn}. It is a
7245 good practice to use insn classes described in the processor manual.
7247 @var{condition} defines what RTL insns are described by this
7248 construction. You should remember that you will be in trouble if
7249 @var{condition} for two or more different
7250 @code{define_insn_reservation} constructions is TRUE for an insn. In
7251 this case what reservation will be used for the insn is not defined.
7252 Such cases are not checked during generation of the pipeline hazards
7253 recognizer because in general recognizing that two conditions may have
7254 the same value is quite difficult (especially if the conditions
7255 contain @code{symbol_ref}). It is also not checked during the
7256 pipeline hazard recognizer work because it would slow down the
7257 recognizer considerably.
7259 @var{regexp} is a string describing the reservation of the cpu's functional
7260 units by the instruction. The reservations are described by a regular
7261 expression according to the following syntax:
7264 regexp = regexp "," oneof
7267 oneof = oneof "|" allof
7270 allof = allof "+" repeat
7273 repeat = element "*" number
7276 element = cpu_function_unit_name
7285 @samp{,} is used for describing the start of the next cycle in
7289 @samp{|} is used for describing a reservation described by the first
7290 regular expression @strong{or} a reservation described by the second
7291 regular expression @strong{or} etc.
7294 @samp{+} is used for describing a reservation described by the first
7295 regular expression @strong{and} a reservation described by the
7296 second regular expression @strong{and} etc.
7299 @samp{*} is used for convenience and simply means a sequence in which
7300 the regular expression are repeated @var{number} times with cycle
7301 advancing (see @samp{,}).
7304 @samp{cpu_function_unit_name} denotes reservation of the named
7308 @samp{reservation_name} --- see description of construction
7309 @samp{define_reservation}.
7312 @samp{nothing} denotes no unit reservations.
7315 @findex define_reservation
7316 Sometimes unit reservations for different insns contain common parts.
7317 In such case, you can simplify the pipeline description by describing
7318 the common part by the following construction
7321 (define_reservation @var{reservation-name} @var{regexp})
7324 @var{reservation-name} is a string giving name of @var{regexp}.
7325 Functional unit names and reservation names are in the same name
7326 space. So the reservation names should be different from the
7327 functional unit names and can not be the reserved name @samp{nothing}.
7329 @findex define_bypass
7330 @cindex instruction latency time
7332 The following construction is used to describe exceptions in the
7333 latency time for given instruction pair. This is so called bypasses.
7336 (define_bypass @var{number} @var{out_insn_names} @var{in_insn_names}
7340 @var{number} defines when the result generated by the instructions
7341 given in string @var{out_insn_names} will be ready for the
7342 instructions given in string @var{in_insn_names}. The instructions in
7343 the string are separated by commas.
7345 @var{guard} is an optional string giving the name of a C function which
7346 defines an additional guard for the bypass. The function will get the
7347 two insns as parameters. If the function returns zero the bypass will
7348 be ignored for this case. The additional guard is necessary to
7349 recognize complicated bypasses, e.g.@: when the consumer is only an address
7350 of insn @samp{store} (not a stored value).
7352 @findex exclusion_set
7353 @findex presence_set
7354 @findex final_presence_set
7356 @findex final_absence_set
7359 The following five constructions are usually used to describe
7360 @acronym{VLIW} processors, or more precisely, to describe a placement
7361 of small instructions into @acronym{VLIW} instruction slots. They
7362 can be used for @acronym{RISC} processors, too.
7365 (exclusion_set @var{unit-names} @var{unit-names})
7366 (presence_set @var{unit-names} @var{patterns})
7367 (final_presence_set @var{unit-names} @var{patterns})
7368 (absence_set @var{unit-names} @var{patterns})
7369 (final_absence_set @var{unit-names} @var{patterns})
7372 @var{unit-names} is a string giving names of functional units
7373 separated by commas.
7375 @var{patterns} is a string giving patterns of functional units
7376 separated by comma. Currently pattern is one unit or units
7377 separated by white-spaces.
7379 The first construction (@samp{exclusion_set}) means that each
7380 functional unit in the first string can not be reserved simultaneously
7381 with a unit whose name is in the second string and vice versa. For
7382 example, the construction is useful for describing processors
7383 (e.g.@: some SPARC processors) with a fully pipelined floating point
7384 functional unit which can execute simultaneously only single floating
7385 point insns or only double floating point insns.
7387 The second construction (@samp{presence_set}) means that each
7388 functional unit in the first string can not be reserved unless at
7389 least one of pattern of units whose names are in the second string is
7390 reserved. This is an asymmetric relation. For example, it is useful
7391 for description that @acronym{VLIW} @samp{slot1} is reserved after
7392 @samp{slot0} reservation. We could describe it by the following
7396 (presence_set "slot1" "slot0")
7399 Or @samp{slot1} is reserved only after @samp{slot0} and unit @samp{b0}
7400 reservation. In this case we could write
7403 (presence_set "slot1" "slot0 b0")
7406 The third construction (@samp{final_presence_set}) is analogous to
7407 @samp{presence_set}. The difference between them is when checking is
7408 done. When an instruction is issued in given automaton state
7409 reflecting all current and planned unit reservations, the automaton
7410 state is changed. The first state is a source state, the second one
7411 is a result state. Checking for @samp{presence_set} is done on the
7412 source state reservation, checking for @samp{final_presence_set} is
7413 done on the result reservation. This construction is useful to
7414 describe a reservation which is actually two subsequent reservations.
7415 For example, if we use
7418 (presence_set "slot1" "slot0")
7421 the following insn will be never issued (because @samp{slot1} requires
7422 @samp{slot0} which is absent in the source state).
7425 (define_reservation "insn_and_nop" "slot0 + slot1")
7428 but it can be issued if we use analogous @samp{final_presence_set}.
7430 The forth construction (@samp{absence_set}) means that each functional
7431 unit in the first string can be reserved only if each pattern of units
7432 whose names are in the second string is not reserved. This is an
7433 asymmetric relation (actually @samp{exclusion_set} is analogous to
7434 this one but it is symmetric). For example it might be useful in a
7435 @acronym{VLIW} description to say that @samp{slot0} cannot be reserved
7436 after either @samp{slot1} or @samp{slot2} have been reserved. This
7437 can be described as:
7440 (absence_set "slot0" "slot1, slot2")
7443 Or @samp{slot2} can not be reserved if @samp{slot0} and unit @samp{b0}
7444 are reserved or @samp{slot1} and unit @samp{b1} are reserved. In
7445 this case we could write
7448 (absence_set "slot2" "slot0 b0, slot1 b1")
7451 All functional units mentioned in a set should belong to the same
7454 The last construction (@samp{final_absence_set}) is analogous to
7455 @samp{absence_set} but checking is done on the result (state)
7456 reservation. See comments for @samp{final_presence_set}.
7458 @findex automata_option
7459 @cindex deterministic finite state automaton
7460 @cindex nondeterministic finite state automaton
7461 @cindex finite state automaton minimization
7462 You can control the generator of the pipeline hazard recognizer with
7463 the following construction.
7466 (automata_option @var{options})
7469 @var{options} is a string giving options which affect the generated
7470 code. Currently there are the following options:
7474 @dfn{no-minimization} makes no minimization of the automaton. This is
7475 only worth to do when we are debugging the description and need to
7476 look more accurately at reservations of states.
7479 @dfn{time} means printing time statistics about the generation of
7483 @dfn{stats} means printing statistics about the generated automata
7484 such as the number of DFA states, NDFA states and arcs.
7487 @dfn{v} means a generation of the file describing the result automata.
7488 The file has suffix @samp{.dfa} and can be used for the description
7489 verification and debugging.
7492 @dfn{w} means a generation of warning instead of error for
7493 non-critical errors.
7496 @dfn{ndfa} makes nondeterministic finite state automata. This affects
7497 the treatment of operator @samp{|} in the regular expressions. The
7498 usual treatment of the operator is to try the first alternative and,
7499 if the reservation is not possible, the second alternative. The
7500 nondeterministic treatment means trying all alternatives, some of them
7501 may be rejected by reservations in the subsequent insns.
7504 @dfn{progress} means output of a progress bar showing how many states
7505 were generated so far for automaton being processed. This is useful
7506 during debugging a @acronym{DFA} description. If you see too many
7507 generated states, you could interrupt the generator of the pipeline
7508 hazard recognizer and try to figure out a reason for generation of the
7512 As an example, consider a superscalar @acronym{RISC} machine which can
7513 issue three insns (two integer insns and one floating point insn) on
7514 the cycle but can finish only two insns. To describe this, we define
7515 the following functional units.
7518 (define_cpu_unit "i0_pipeline, i1_pipeline, f_pipeline")
7519 (define_cpu_unit "port0, port1")
7522 All simple integer insns can be executed in any integer pipeline and
7523 their result is ready in two cycles. The simple integer insns are
7524 issued into the first pipeline unless it is reserved, otherwise they
7525 are issued into the second pipeline. Integer division and
7526 multiplication insns can be executed only in the second integer
7527 pipeline and their results are ready correspondingly in 8 and 4
7528 cycles. The integer division is not pipelined, i.e.@: the subsequent
7529 integer division insn can not be issued until the current division
7530 insn finished. Floating point insns are fully pipelined and their
7531 results are ready in 3 cycles. Where the result of a floating point
7532 insn is used by an integer insn, an additional delay of one cycle is
7533 incurred. To describe all of this we could specify
7536 (define_cpu_unit "div")
7538 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
7539 "(i0_pipeline | i1_pipeline), (port0 | port1)")
7541 (define_insn_reservation "mult" 4 (eq_attr "type" "mult")
7542 "i1_pipeline, nothing*2, (port0 | port1)")
7544 (define_insn_reservation "div" 8 (eq_attr "type" "div")
7545 "i1_pipeline, div*7, div + (port0 | port1)")
7547 (define_insn_reservation "float" 3 (eq_attr "type" "float")
7548 "f_pipeline, nothing, (port0 | port1))
7550 (define_bypass 4 "float" "simple,mult,div")
7553 To simplify the description we could describe the following reservation
7556 (define_reservation "finish" "port0|port1")
7559 and use it in all @code{define_insn_reservation} as in the following
7563 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
7564 "(i0_pipeline | i1_pipeline), finish")
7570 @node Conditional Execution
7571 @section Conditional Execution
7572 @cindex conditional execution
7575 A number of architectures provide for some form of conditional
7576 execution, or predication. The hallmark of this feature is the
7577 ability to nullify most of the instructions in the instruction set.
7578 When the instruction set is large and not entirely symmetric, it
7579 can be quite tedious to describe these forms directly in the
7580 @file{.md} file. An alternative is the @code{define_cond_exec} template.
7582 @findex define_cond_exec
7585 [@var{predicate-pattern}]
7587 "@var{output-template}")
7590 @var{predicate-pattern} is the condition that must be true for the
7591 insn to be executed at runtime and should match a relational operator.
7592 One can use @code{match_operator} to match several relational operators
7593 at once. Any @code{match_operand} operands must have no more than one
7596 @var{condition} is a C expression that must be true for the generated
7599 @findex current_insn_predicate
7600 @var{output-template} is a string similar to the @code{define_insn}
7601 output template (@pxref{Output Template}), except that the @samp{*}
7602 and @samp{@@} special cases do not apply. This is only useful if the
7603 assembly text for the predicate is a simple prefix to the main insn.
7604 In order to handle the general case, there is a global variable
7605 @code{current_insn_predicate} that will contain the entire predicate
7606 if the current insn is predicated, and will otherwise be @code{NULL}.
7608 When @code{define_cond_exec} is used, an implicit reference to
7609 the @code{predicable} instruction attribute is made.
7610 @xref{Insn Attributes}. This attribute must be boolean (i.e.@: have
7611 exactly two elements in its @var{list-of-values}). Further, it must
7612 not be used with complex expressions. That is, the default and all
7613 uses in the insns must be a simple constant, not dependent on the
7614 alternative or anything else.
7616 For each @code{define_insn} for which the @code{predicable}
7617 attribute is true, a new @code{define_insn} pattern will be
7618 generated that matches a predicated version of the instruction.
7622 (define_insn "addsi"
7623 [(set (match_operand:SI 0 "register_operand" "r")
7624 (plus:SI (match_operand:SI 1 "register_operand" "r")
7625 (match_operand:SI 2 "register_operand" "r")))]
7630 [(ne (match_operand:CC 0 "register_operand" "c")
7637 generates a new pattern
7642 (ne (match_operand:CC 3 "register_operand" "c") (const_int 0))
7643 (set (match_operand:SI 0 "register_operand" "r")
7644 (plus:SI (match_operand:SI 1 "register_operand" "r")
7645 (match_operand:SI 2 "register_operand" "r"))))]
7646 "(@var{test2}) && (@var{test1})"
7647 "(%3) add %2,%1,%0")
7652 @node Constant Definitions
7653 @section Constant Definitions
7654 @cindex constant definitions
7655 @findex define_constants
7657 Using literal constants inside instruction patterns reduces legibility and
7658 can be a maintenance problem.
7660 To overcome this problem, you may use the @code{define_constants}
7661 expression. It contains a vector of name-value pairs. From that
7662 point on, wherever any of the names appears in the MD file, it is as
7663 if the corresponding value had been written instead. You may use
7664 @code{define_constants} multiple times; each appearance adds more
7665 constants to the table. It is an error to redefine a constant with
7668 To come back to the a29k load multiple example, instead of
7672 [(match_parallel 0 "load_multiple_operation"
7673 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
7674 (match_operand:SI 2 "memory_operand" "m"))
7676 (clobber (reg:SI 179))])]
7692 [(match_parallel 0 "load_multiple_operation"
7693 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
7694 (match_operand:SI 2 "memory_operand" "m"))
7696 (clobber (reg:SI R_CR))])]
7701 The constants that are defined with a define_constant are also output
7702 in the insn-codes.h header file as #defines.
7707 @cindex iterators in @file{.md} files
7709 Ports often need to define similar patterns for more than one machine
7710 mode or for more than one rtx code. GCC provides some simple iterator
7711 facilities to make this process easier.
7714 * Mode Iterators:: Generating variations of patterns for different modes.
7715 * Code Iterators:: Doing the same for codes.
7718 @node Mode Iterators
7719 @subsection Mode Iterators
7720 @cindex mode iterators in @file{.md} files
7722 Ports often need to define similar patterns for two or more different modes.
7727 If a processor has hardware support for both single and double
7728 floating-point arithmetic, the @code{SFmode} patterns tend to be
7729 very similar to the @code{DFmode} ones.
7732 If a port uses @code{SImode} pointers in one configuration and
7733 @code{DImode} pointers in another, it will usually have very similar
7734 @code{SImode} and @code{DImode} patterns for manipulating pointers.
7737 Mode iterators allow several patterns to be instantiated from one
7738 @file{.md} file template. They can be used with any type of
7739 rtx-based construct, such as a @code{define_insn},
7740 @code{define_split}, or @code{define_peephole2}.
7743 * Defining Mode Iterators:: Defining a new mode iterator.
7744 * Substitutions:: Combining mode iterators with substitutions
7745 * Examples:: Examples
7748 @node Defining Mode Iterators
7749 @subsubsection Defining Mode Iterators
7750 @findex define_mode_iterator
7752 The syntax for defining a mode iterator is:
7755 (define_mode_iterator @var{name} [(@var{mode1} "@var{cond1}") ... (@var{moden} "@var{condn}")])
7758 This allows subsequent @file{.md} file constructs to use the mode suffix
7759 @code{:@var{name}}. Every construct that does so will be expanded
7760 @var{n} times, once with every use of @code{:@var{name}} replaced by
7761 @code{:@var{mode1}}, once with every use replaced by @code{:@var{mode2}},
7762 and so on. In the expansion for a particular @var{modei}, every
7763 C condition will also require that @var{condi} be true.
7768 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
7771 defines a new mode suffix @code{:P}. Every construct that uses
7772 @code{:P} will be expanded twice, once with every @code{:P} replaced
7773 by @code{:SI} and once with every @code{:P} replaced by @code{:DI}.
7774 The @code{:SI} version will only apply if @code{Pmode == SImode} and
7775 the @code{:DI} version will only apply if @code{Pmode == DImode}.
7777 As with other @file{.md} conditions, an empty string is treated
7778 as ``always true''. @code{(@var{mode} "")} can also be abbreviated
7779 to @code{@var{mode}}. For example:
7782 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
7785 means that the @code{:DI} expansion only applies if @code{TARGET_64BIT}
7786 but that the @code{:SI} expansion has no such constraint.
7788 Iterators are applied in the order they are defined. This can be
7789 significant if two iterators are used in a construct that requires
7790 substitutions. @xref{Substitutions}.
7793 @subsubsection Substitution in Mode Iterators
7794 @findex define_mode_attr
7796 If an @file{.md} file construct uses mode iterators, each version of the
7797 construct will often need slightly different strings or modes. For
7802 When a @code{define_expand} defines several @code{add@var{m}3} patterns
7803 (@pxref{Standard Names}), each expander will need to use the
7804 appropriate mode name for @var{m}.
7807 When a @code{define_insn} defines several instruction patterns,
7808 each instruction will often use a different assembler mnemonic.
7811 When a @code{define_insn} requires operands with different modes,
7812 using an iterator for one of the operand modes usually requires a specific
7813 mode for the other operand(s).
7816 GCC supports such variations through a system of ``mode attributes''.
7817 There are two standard attributes: @code{mode}, which is the name of
7818 the mode in lower case, and @code{MODE}, which is the same thing in
7819 upper case. You can define other attributes using:
7822 (define_mode_attr @var{name} [(@var{mode1} "@var{value1}") ... (@var{moden} "@var{valuen}")])
7825 where @var{name} is the name of the attribute and @var{valuei}
7826 is the value associated with @var{modei}.
7828 When GCC replaces some @var{:iterator} with @var{:mode}, it will scan
7829 each string and mode in the pattern for sequences of the form
7830 @code{<@var{iterator}:@var{attr}>}, where @var{attr} is the name of a
7831 mode attribute. If the attribute is defined for @var{mode}, the whole
7832 @code{<...>} sequence will be replaced by the appropriate attribute
7835 For example, suppose an @file{.md} file has:
7838 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
7839 (define_mode_attr load [(SI "lw") (DI "ld")])
7842 If one of the patterns that uses @code{:P} contains the string
7843 @code{"<P:load>\t%0,%1"}, the @code{SI} version of that pattern
7844 will use @code{"lw\t%0,%1"} and the @code{DI} version will use
7847 Here is an example of using an attribute for a mode:
7850 (define_mode_iterator LONG [SI DI])
7851 (define_mode_attr SHORT [(SI "HI") (DI "SI")])
7853 (sign_extend:LONG (match_operand:<LONG:SHORT> ...)) ...)
7856 The @code{@var{iterator}:} prefix may be omitted, in which case the
7857 substitution will be attempted for every iterator expansion.
7860 @subsubsection Mode Iterator Examples
7862 Here is an example from the MIPS port. It defines the following
7863 modes and attributes (among others):
7866 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
7867 (define_mode_attr d [(SI "") (DI "d")])
7870 and uses the following template to define both @code{subsi3}
7874 (define_insn "sub<mode>3"
7875 [(set (match_operand:GPR 0 "register_operand" "=d")
7876 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
7877 (match_operand:GPR 2 "register_operand" "d")))]
7880 [(set_attr "type" "arith")
7881 (set_attr "mode" "<MODE>")])
7884 This is exactly equivalent to:
7887 (define_insn "subsi3"
7888 [(set (match_operand:SI 0 "register_operand" "=d")
7889 (minus:SI (match_operand:SI 1 "register_operand" "d")
7890 (match_operand:SI 2 "register_operand" "d")))]
7893 [(set_attr "type" "arith")
7894 (set_attr "mode" "SI")])
7896 (define_insn "subdi3"
7897 [(set (match_operand:DI 0 "register_operand" "=d")
7898 (minus:DI (match_operand:DI 1 "register_operand" "d")
7899 (match_operand:DI 2 "register_operand" "d")))]
7902 [(set_attr "type" "arith")
7903 (set_attr "mode" "DI")])
7906 @node Code Iterators
7907 @subsection Code Iterators
7908 @cindex code iterators in @file{.md} files
7909 @findex define_code_iterator
7910 @findex define_code_attr
7912 Code iterators operate in a similar way to mode iterators. @xref{Mode Iterators}.
7917 (define_code_iterator @var{name} [(@var{code1} "@var{cond1}") ... (@var{coden} "@var{condn}")])
7920 defines a pseudo rtx code @var{name} that can be instantiated as
7921 @var{codei} if condition @var{condi} is true. Each @var{codei}
7922 must have the same rtx format. @xref{RTL Classes}.
7924 As with mode iterators, each pattern that uses @var{name} will be
7925 expanded @var{n} times, once with all uses of @var{name} replaced by
7926 @var{code1}, once with all uses replaced by @var{code2}, and so on.
7927 @xref{Defining Mode Iterators}.
7929 It is possible to define attributes for codes as well as for modes.
7930 There are two standard code attributes: @code{code}, the name of the
7931 code in lower case, and @code{CODE}, the name of the code in upper case.
7932 Other attributes are defined using:
7935 (define_code_attr @var{name} [(@var{code1} "@var{value1}") ... (@var{coden} "@var{valuen}")])
7938 Here's an example of code iterators in action, taken from the MIPS port:
7941 (define_code_iterator any_cond [unordered ordered unlt unge uneq ltgt unle ungt
7942 eq ne gt ge lt le gtu geu ltu leu])
7944 (define_expand "b<code>"
7946 (if_then_else (any_cond:CC (cc0)
7948 (label_ref (match_operand 0 ""))
7952 gen_conditional_branch (operands, <CODE>);
7957 This is equivalent to:
7960 (define_expand "bunordered"
7962 (if_then_else (unordered:CC (cc0)
7964 (label_ref (match_operand 0 ""))
7968 gen_conditional_branch (operands, UNORDERED);
7972 (define_expand "bordered"
7974 (if_then_else (ordered:CC (cc0)
7976 (label_ref (match_operand 0 ""))
7980 gen_conditional_branch (operands, ORDERED);