1 /* Definitions of Tensilica's Xtensa target machine for GNU compiler.
2 Copyright 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
3 Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* Get Xtensa configuration settings */
23 #include "xtensa-config.h"
25 /* Standard GCC variables that we reference. */
26 extern int current_function_calls_alloca;
27 extern int target_flags;
30 /* External variables defined in xtensa.c. */
34 CMP_SI, /* four byte integers */
35 CMP_DI, /* eight byte integers */
36 CMP_SF, /* single precision floats */
37 CMP_DF, /* double precision floats */
38 CMP_MAX /* max comparison type */
41 extern struct rtx_def * branch_cmp[2]; /* operands for compare */
42 extern enum cmp_type branch_type; /* what type of branch to use */
43 extern unsigned xtensa_current_frame_size;
45 /* Masks for the -m switches */
46 #define MASK_NO_FUSED_MADD 0x00000001 /* avoid f-p mul/add */
47 #define MASK_CONST16 0x00000002 /* use CONST16 instruction */
49 /* Macros used in the machine description to select various Xtensa
50 configuration options. */
51 #define TARGET_BIG_ENDIAN XCHAL_HAVE_BE
52 #define TARGET_DENSITY XCHAL_HAVE_DENSITY
53 #define TARGET_MAC16 XCHAL_HAVE_MAC16
54 #define TARGET_MUL16 XCHAL_HAVE_MUL16
55 #define TARGET_MUL32 XCHAL_HAVE_MUL32
56 #define TARGET_DIV32 XCHAL_HAVE_DIV32
57 #define TARGET_NSA XCHAL_HAVE_NSA
58 #define TARGET_MINMAX XCHAL_HAVE_MINMAX
59 #define TARGET_SEXT XCHAL_HAVE_SEXT
60 #define TARGET_BOOLEANS XCHAL_HAVE_BOOLEANS
61 #define TARGET_HARD_FLOAT XCHAL_HAVE_FP
62 #define TARGET_HARD_FLOAT_DIV XCHAL_HAVE_FP_DIV
63 #define TARGET_HARD_FLOAT_RECIP XCHAL_HAVE_FP_RECIP
64 #define TARGET_HARD_FLOAT_SQRT XCHAL_HAVE_FP_SQRT
65 #define TARGET_HARD_FLOAT_RSQRT XCHAL_HAVE_FP_RSQRT
66 #define TARGET_ABS XCHAL_HAVE_ABS
67 #define TARGET_ADDX XCHAL_HAVE_ADDX
69 /* Macros controlled by command-line options. */
70 #define TARGET_NO_FUSED_MADD (target_flags & MASK_NO_FUSED_MADD)
71 #define TARGET_CONST16 (target_flags & MASK_CONST16)
73 #define TARGET_DEFAULT ( \
74 (XCHAL_HAVE_L32R ? 0 : MASK_CONST16))
76 #define TARGET_SWITCHES \
78 {"const16", MASK_CONST16, \
79 N_("Use CONST16 instruction to load constants")}, \
80 {"no-const16", -MASK_CONST16, \
81 N_("Use PC-relative L32R instruction to load constants")}, \
82 {"no-fused-madd", MASK_NO_FUSED_MADD, \
83 N_("Disable fused multiply/add and multiply/subtract FP instructions")}, \
84 {"fused-madd", -MASK_NO_FUSED_MADD, \
85 N_("Enable fused multiply/add and multiply/subtract FP instructions")}, \
86 {"text-section-literals", 0, \
87 N_("Intersperse literal pools with code in the text section")}, \
88 {"no-text-section-literals", 0, \
89 N_("Put literal pools in a separate literal section")}, \
91 N_("Automatically align branch targets to reduce branch penalties")}, \
92 {"no-target-align", 0, \
93 N_("Do not automatically align branch targets")}, \
95 N_("Use indirect CALLXn instructions for large programs")}, \
97 N_("Use direct CALLn instructions for fast calls")}, \
98 {"", TARGET_DEFAULT, 0} \
102 #define OVERRIDE_OPTIONS override_options ()
104 /* Target CPU builtins. */
105 #define TARGET_CPU_CPP_BUILTINS() \
107 builtin_assert ("cpu=xtensa"); \
108 builtin_assert ("machine=xtensa"); \
109 builtin_define ("__XTENSA__"); \
110 builtin_define (TARGET_BIG_ENDIAN ? "__XTENSA_EB__" : "__XTENSA_EL__"); \
111 if (!TARGET_HARD_FLOAT) \
112 builtin_define ("__XTENSA_SOFT_FLOAT__"); \
115 builtin_define ("__PIC__"); \
116 builtin_define ("__pic__"); \
120 #define CPP_SPEC " %(subtarget_cpp_spec) "
122 #ifndef SUBTARGET_CPP_SPEC
123 #define SUBTARGET_CPP_SPEC ""
126 #define EXTRA_SPECS \
127 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC },
130 #define LIBGCC2_WORDS_BIG_ENDIAN 1
132 #define LIBGCC2_WORDS_BIG_ENDIAN 0
135 /* Show we can debug even without a frame pointer. */
136 #define CAN_DEBUG_WITHOUT_FP
139 /* Target machine storage layout */
141 /* Define this if most significant bit is lowest numbered
142 in instructions that operate on numbered bit-fields. */
143 #define BITS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
145 /* Define this if most significant byte of a word is the lowest numbered. */
146 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
148 /* Define this if most significant word of a multiword number is the lowest. */
149 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
151 #define MAX_BITS_PER_WORD 32
153 /* Width of a word, in units (bytes). */
154 #define UNITS_PER_WORD 4
155 #define MIN_UNITS_PER_WORD 4
157 /* Width of a floating point register. */
158 #define UNITS_PER_FPREG 4
160 /* Size in bits of various types on the target machine. */
161 #define INT_TYPE_SIZE 32
162 #define SHORT_TYPE_SIZE 16
163 #define LONG_TYPE_SIZE 32
164 #define LONG_LONG_TYPE_SIZE 64
165 #define FLOAT_TYPE_SIZE 32
166 #define DOUBLE_TYPE_SIZE 64
167 #define LONG_DOUBLE_TYPE_SIZE 64
169 /* Allocation boundary (in *bits*) for storing pointers in memory. */
170 #define POINTER_BOUNDARY 32
172 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
173 #define PARM_BOUNDARY 32
175 /* Allocation boundary (in *bits*) for the code of a function. */
176 #define FUNCTION_BOUNDARY 32
178 /* Alignment of field after 'int : 0' in a structure. */
179 #define EMPTY_FIELD_BOUNDARY 32
181 /* Every structure's size must be a multiple of this. */
182 #define STRUCTURE_SIZE_BOUNDARY 8
184 /* There is no point aligning anything to a rounder boundary than this. */
185 #define BIGGEST_ALIGNMENT 128
187 /* Set this nonzero if move instructions will actually fail to work
188 when given unaligned data. */
189 #define STRICT_ALIGNMENT 1
191 /* Promote integer modes smaller than a word to SImode. Set UNSIGNEDP
192 for QImode, because there is no 8-bit load from memory with sign
193 extension. Otherwise, leave UNSIGNEDP alone, since Xtensa has 16-bit
194 loads both with and without sign extension. */
195 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
197 if (GET_MODE_CLASS (MODE) == MODE_INT \
198 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
200 if ((MODE) == QImode) \
206 /* Imitate the way many other C compilers handle alignment of
207 bitfields and the structures that contain them. */
208 #define PCC_BITFIELD_TYPE_MATTERS 1
210 /* Align string constants and constructors to at least a word boundary.
211 The typical use of this macro is to increase alignment for string
212 constants to be word aligned so that 'strcpy' calls that copy
213 constants can be done inline. */
214 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
215 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
216 && (ALIGN) < BITS_PER_WORD \
220 /* Align arrays, unions and records to at least a word boundary.
221 One use of this macro is to increase alignment of medium-size
222 data to make it all fit in fewer cache lines. Another is to
223 cause character arrays to be word-aligned so that 'strcpy' calls
224 that copy constants to character arrays can be done inline. */
225 #undef DATA_ALIGNMENT
226 #define DATA_ALIGNMENT(TYPE, ALIGN) \
227 ((((ALIGN) < BITS_PER_WORD) \
228 && (TREE_CODE (TYPE) == ARRAY_TYPE \
229 || TREE_CODE (TYPE) == UNION_TYPE \
230 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
232 /* Operations between registers always perform the operation
233 on the full register even if a narrower mode is specified. */
234 #define WORD_REGISTER_OPERATIONS
236 /* Xtensa loads are zero-extended by default. */
237 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
239 /* Standard register usage. */
241 /* Number of actual hardware registers.
242 The hardware registers are assigned numbers for the compiler
243 from 0 to just below FIRST_PSEUDO_REGISTER.
244 All registers that the compiler knows about must be given numbers,
245 even those that are not normally considered general registers.
247 The fake frame pointer and argument pointer will never appear in
248 the generated code, since they will always be eliminated and replaced
249 by either the stack pointer or the hard frame pointer.
251 0 - 15 AR[0] - AR[15]
252 16 FRAME_POINTER (fake = initial sp)
253 17 ARG_POINTER (fake = initial sp + framesize)
254 18 BR[0] for floating-point CC
255 19 - 34 FR[0] - FR[15]
256 35 MAC16 accumulator */
258 #define FIRST_PSEUDO_REGISTER 36
260 /* Return the stabs register number to use for REGNO. */
261 #define DBX_REGISTER_NUMBER(REGNO) xtensa_dbx_register_number (REGNO)
263 /* 1 for registers that have pervasive standard uses
264 and are not available for the register allocator. */
265 #define FIXED_REGISTERS \
267 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
269 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
273 /* 1 for registers not available across function calls.
274 These must include the FIXED_REGISTERS and also any
275 registers that can be used without being saved.
276 The latter must include the registers where values are returned
277 and the register where structure-value addresses are passed.
278 Aside from that, you can include as many other registers as you like. */
279 #define CALL_USED_REGISTERS \
281 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
283 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
287 /* For non-leaf procedures on Xtensa processors, the allocation order
288 is as specified below by REG_ALLOC_ORDER. For leaf procedures, we
289 want to use the lowest numbered registers first to minimize
290 register window overflows. However, local-alloc is not smart
291 enough to consider conflicts with incoming arguments. If an
292 incoming argument in a2 is live throughout the function and
293 local-alloc decides to use a2, then the incoming argument must
294 either be spilled or copied to another register. To get around
295 this, we define ORDER_REGS_FOR_LOCAL_ALLOC to redefine
296 reg_alloc_order for leaf functions such that lowest numbered
297 registers are used first with the exception that the incoming
298 argument registers are not used until after other register choices
299 have been exhausted. */
301 #define REG_ALLOC_ORDER \
302 { 8, 9, 10, 11, 12, 13, 14, 15, 7, 6, 5, 4, 3, 2, \
304 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, \
309 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
311 /* For Xtensa, the only point of this is to prevent GCC from otherwise
312 giving preference to call-used registers. To minimize window
313 overflows for the AR registers, we want to give preference to the
314 lower-numbered AR registers. For other register files, which are
315 not windowed, we still prefer call-used registers, if there are any. */
316 extern const char xtensa_leaf_regs[FIRST_PSEUDO_REGISTER];
317 #define LEAF_REGISTERS xtensa_leaf_regs
319 /* For Xtensa, no remapping is necessary, but this macro must be
320 defined if LEAF_REGISTERS is defined. */
321 #define LEAF_REG_REMAP(REGNO) (REGNO)
323 /* This must be declared if LEAF_REGISTERS is set. */
324 extern int leaf_function;
326 /* Internal macros to classify a register number. */
328 /* 16 address registers + fake registers */
329 #define GP_REG_FIRST 0
330 #define GP_REG_LAST 17
331 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
333 /* Coprocessor registers */
334 #define BR_REG_FIRST 18
335 #define BR_REG_LAST 18
336 #define BR_REG_NUM (BR_REG_LAST - BR_REG_FIRST + 1)
338 /* 16 floating-point registers */
339 #define FP_REG_FIRST 19
340 #define FP_REG_LAST 34
341 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
343 /* MAC16 accumulator */
344 #define ACC_REG_FIRST 35
345 #define ACC_REG_LAST 35
346 #define ACC_REG_NUM (ACC_REG_LAST - ACC_REG_FIRST + 1)
348 #define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM)
349 #define BR_REG_P(REGNO) ((unsigned) ((REGNO) - BR_REG_FIRST) < BR_REG_NUM)
350 #define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM)
351 #define ACC_REG_P(REGNO) ((unsigned) ((REGNO) - ACC_REG_FIRST) < ACC_REG_NUM)
353 /* Return number of consecutive hard regs needed starting at reg REGNO
354 to hold something of mode MODE. */
355 #define HARD_REGNO_NREGS(REGNO, MODE) \
356 (FP_REG_P (REGNO) ? \
357 ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG) : \
358 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
360 /* Value is 1 if hard register REGNO can hold a value of machine-mode
362 extern char xtensa_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
364 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
365 xtensa_hard_regno_mode_ok[(int) (MODE)][(REGNO)]
367 /* Value is 1 if it is a good idea to tie two pseudo registers
368 when one has mode MODE1 and one has mode MODE2.
369 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
370 for any hard reg, then this must be 0 for correct output. */
371 #define MODES_TIEABLE_P(MODE1, MODE2) \
372 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
373 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
374 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
375 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
377 /* Register to use for pushing function arguments. */
378 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 1)
380 /* Base register for access to local variables of the function. */
381 #define HARD_FRAME_POINTER_REGNUM (GP_REG_FIRST + 7)
383 /* The register number of the frame pointer register, which is used to
384 access automatic variables in the stack frame. For Xtensa, this
385 register never appears in the output. It is always eliminated to
386 either the stack pointer or the hard frame pointer. */
387 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 16)
389 /* Value should be nonzero if functions must have frame pointers.
390 Zero means the frame pointer need not be set up (and parms
391 may be accessed via the stack pointer) in functions that seem suitable.
392 This is computed in 'reload', in reload1.c. */
393 #define FRAME_POINTER_REQUIRED xtensa_frame_pointer_required ()
395 /* Base register for access to arguments of the function. */
396 #define ARG_POINTER_REGNUM (GP_REG_FIRST + 17)
398 /* If the static chain is passed in memory, these macros provide rtx
399 giving 'mem' expressions that denote where they are stored.
400 'STATIC_CHAIN' and 'STATIC_CHAIN_INCOMING' give the locations as
401 seen by the calling and called functions, respectively. */
403 #define STATIC_CHAIN \
404 gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, -5 * UNITS_PER_WORD))
406 #define STATIC_CHAIN_INCOMING \
407 gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -5 * UNITS_PER_WORD))
409 /* For now we don't try to use the full set of boolean registers. Without
410 software pipelining of FP operations, there's not much to gain and it's
411 a real pain to get them reloaded. */
412 #define FPCC_REGNUM (BR_REG_FIRST + 0)
414 /* It is as good or better to call a constant function address than to
415 call an address kept in a register. */
416 #define NO_FUNCTION_CSE 1
418 /* It is as good or better for a function to call itself with an
419 explicit address than to call an address kept in a register. */
420 #define NO_RECURSIVE_FUNCTION_CSE 1
422 /* Xtensa processors have "register windows". GCC does not currently
423 take advantage of the possibility for variable-sized windows; instead,
424 we use a fixed window size of 8. */
426 #define INCOMING_REGNO(OUT) \
427 ((GP_REG_P (OUT) && \
428 ((unsigned) ((OUT) - GP_REG_FIRST) >= WINDOW_SIZE)) ? \
429 (OUT) - WINDOW_SIZE : (OUT))
431 #define OUTGOING_REGNO(IN) \
433 ((unsigned) ((IN) - GP_REG_FIRST) < WINDOW_SIZE)) ? \
434 (IN) + WINDOW_SIZE : (IN))
437 /* Define the classes of registers for register constraints in the
438 machine description. */
441 NO_REGS, /* no registers in set */
442 BR_REGS, /* coprocessor boolean registers */
443 FP_REGS, /* floating point registers */
444 ACC_REG, /* MAC16 accumulator */
445 SP_REG, /* sp register (aka a1) */
446 RL_REGS, /* preferred reload regs (not sp or fp) */
447 GR_REGS, /* integer registers except sp */
448 AR_REGS, /* all integer registers */
449 ALL_REGS, /* all registers */
450 LIM_REG_CLASSES /* max value + 1 */
453 #define N_REG_CLASSES (int) LIM_REG_CLASSES
455 #define GENERAL_REGS AR_REGS
457 /* An initializer containing the names of the register classes as C
458 string constants. These names are used in writing some of the
460 #define REG_CLASS_NAMES \
473 /* Contents of the register classes. The Nth integer specifies the
474 contents of class N. The way the integer MASK is interpreted is
475 that register R is in the class if 'MASK & (1 << R)' is 1. */
476 #define REG_CLASS_CONTENTS \
478 { 0x00000000, 0x00000000 }, /* no registers */ \
479 { 0x00040000, 0x00000000 }, /* coprocessor boolean registers */ \
480 { 0xfff80000, 0x00000007 }, /* floating-point registers */ \
481 { 0x00000000, 0x00000008 }, /* MAC16 accumulator */ \
482 { 0x00000002, 0x00000000 }, /* stack pointer register */ \
483 { 0x0000ff7d, 0x00000000 }, /* preferred reload registers */ \
484 { 0x0000fffd, 0x00000000 }, /* general-purpose registers */ \
485 { 0x0003ffff, 0x00000000 }, /* integer registers */ \
486 { 0xffffffff, 0x0000000f } /* all registers */ \
489 /* A C expression whose value is a register class containing hard
490 register REGNO. In general there is more that one such class;
491 choose a class which is "minimal", meaning that no smaller class
492 also contains the register. */
493 extern const enum reg_class xtensa_regno_to_class[FIRST_PSEUDO_REGISTER];
495 #define REGNO_REG_CLASS(REGNO) xtensa_regno_to_class[ (REGNO) ]
497 /* Use the Xtensa AR register file for base registers.
498 No index registers. */
499 #define BASE_REG_CLASS AR_REGS
500 #define INDEX_REG_CLASS NO_REGS
502 /* SMALL_REGISTER_CLASSES is required for Xtensa, because all of the
503 16 AR registers may be explicitly used in the RTL, as either
504 incoming or outgoing arguments. */
505 #define SMALL_REGISTER_CLASSES 1
508 /* REGISTER AND CONSTANT CLASSES */
510 /* Get reg_class from a letter such as appears in the machine
513 Available letters: a-f,h,j-l,q,t-z,A-D,W,Y-Z
515 DEFINED REGISTER CLASSES:
517 'a' general-purpose registers except sp
519 'D' general-purpose registers (only if density option enabled)
520 'd' general-purpose registers, including sp (only if density enabled)
521 'A' MAC16 accumulator (only if MAC16 option enabled)
522 'B' general-purpose registers (only if sext instruction enabled)
523 'C' general-purpose registers (only if mul16 option enabled)
524 'W' general-purpose registers (only if const16 option enabled)
525 'b' coprocessor boolean registers
526 'f' floating-point registers
529 extern enum reg_class xtensa_char_to_class[256];
531 #define REG_CLASS_FROM_LETTER(C) xtensa_char_to_class[ (int) (C) ]
533 /* The letters I, J, K, L, M, N, O, and P in a register constraint
534 string can be used to stand for particular ranges of immediate
535 operands. This macro defines what the ranges are. C is the
536 letter, and VALUE is a constant value. Return 1 if VALUE is
537 in the range specified by C.
541 I = 12-bit signed immediate for movi
542 J = 8-bit signed immediate for addi
543 K = 4-bit value in (b4const U {0})
544 L = 4-bit value in b4constu
545 M = 7-bit value in simm7
546 N = 8-bit unsigned immediate shifted left by 8 bits for addmi
547 O = 4-bit value in ai4const
548 P = valid immediate mask value for extui */
550 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
551 ((C) == 'I' ? (xtensa_simm12b (VALUE)) \
552 : (C) == 'J' ? (xtensa_simm8 (VALUE)) \
553 : (C) == 'K' ? (((VALUE) == 0) || xtensa_b4const (VALUE)) \
554 : (C) == 'L' ? (xtensa_b4constu (VALUE)) \
555 : (C) == 'M' ? (xtensa_simm7 (VALUE)) \
556 : (C) == 'N' ? (xtensa_simm8x256 (VALUE)) \
557 : (C) == 'O' ? (xtensa_ai4const (VALUE)) \
558 : (C) == 'P' ? (xtensa_mask_immediate (VALUE)) \
562 /* Similar, but for floating constants, and defining letters G and H.
563 Here VALUE is the CONST_DOUBLE rtx itself. */
564 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) (0)
567 /* Other letters can be defined in a machine-dependent fashion to
568 stand for particular classes of registers or other arbitrary
571 R = memory that can be accessed with a 4-bit unsigned offset
572 T = memory in a constant pool (addressable with a pc-relative load)
573 U = memory *NOT* in a constant pool
575 The offset range should not be checked here (except to distinguish
576 denser versions of the instructions for which more general versions
577 are available). Doing so leads to problems in reloading: an
578 argptr-relative address may become invalid when the phony argptr is
579 eliminated in favor of the stack pointer (the offset becomes too
580 large to fit in the instruction's immediate field); a reload is
581 generated to fix this but the RTL is not immediately updated; in
582 the meantime, the constraints are checked and none match. The
583 solution seems to be to simply skip the offset check here. The
584 address will be checked anyway because of the code in
585 GO_IF_LEGITIMATE_ADDRESS. */
587 #define EXTRA_CONSTRAINT(OP, CODE) \
588 ((GET_CODE (OP) != MEM) ? \
589 ((CODE) >= 'R' && (CODE) <= 'U' \
590 && reload_in_progress && GET_CODE (OP) == REG \
591 && REGNO (OP) >= FIRST_PSEUDO_REGISTER) \
592 : ((CODE) == 'R') ? smalloffset_mem_p (OP) \
593 : ((CODE) == 'T') ? !TARGET_CONST16 && constantpool_mem_p (OP) \
594 : ((CODE) == 'U') ? !constantpool_mem_p (OP) \
597 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
598 xtensa_preferred_reload_class (X, CLASS, 0)
600 #define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \
601 xtensa_preferred_reload_class (X, CLASS, 1)
603 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
604 xtensa_secondary_reload_class (CLASS, MODE, X, 0)
606 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
607 xtensa_secondary_reload_class (CLASS, MODE, X, 1)
609 /* Return the maximum number of consecutive registers
610 needed to represent mode MODE in a register of class CLASS. */
611 #define CLASS_UNITS(mode, size) \
612 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
614 #define CLASS_MAX_NREGS(CLASS, MODE) \
615 (CLASS_UNITS (MODE, UNITS_PER_WORD))
618 /* Stack layout; function entry, exit and calling. */
620 #define STACK_GROWS_DOWNWARD
622 /* Offset within stack frame to start allocating local variables at. */
623 #define STARTING_FRAME_OFFSET \
624 current_function_outgoing_args_size
626 /* The ARG_POINTER and FRAME_POINTER are not real Xtensa registers, so
627 they are eliminated to either the stack pointer or hard frame pointer. */
628 #define ELIMINABLE_REGS \
629 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
630 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
631 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
632 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
634 #define CAN_ELIMINATE(FROM, TO) 1
636 /* Specify the initial difference between the specified pair of registers. */
637 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
639 compute_frame_size (get_frame_size ()); \
640 if ((FROM) == FRAME_POINTER_REGNUM) \
642 else if ((FROM) == ARG_POINTER_REGNUM) \
643 (OFFSET) = xtensa_current_frame_size; \
648 /* If defined, the maximum amount of space required for outgoing
649 arguments will be computed and placed into the variable
650 'current_function_outgoing_args_size'. No space will be pushed
651 onto the stack for each call; instead, the function prologue
652 should increase the stack frame size by this amount. */
653 #define ACCUMULATE_OUTGOING_ARGS 1
655 /* Offset from the argument pointer register to the first argument's
656 address. On some machines it may depend on the data type of the
657 function. If 'ARGS_GROW_DOWNWARD', this is the offset to the
658 location above the first argument's address. */
659 #define FIRST_PARM_OFFSET(FNDECL) 0
661 /* Align stack frames on 128 bits for Xtensa. This is necessary for
662 128-bit datatypes defined in TIE (e.g., for Vectra). */
663 #define STACK_BOUNDARY 128
665 /* Functions do not pop arguments off the stack. */
666 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
668 /* Use a fixed register window size of 8. */
669 #define WINDOW_SIZE 8
671 /* Symbolic macros for the registers used to return integer, floating
672 point, and values of coprocessor and user-defined modes. */
673 #define GP_RETURN (GP_REG_FIRST + 2 + WINDOW_SIZE)
674 #define GP_OUTGOING_RETURN (GP_REG_FIRST + 2)
676 /* Symbolic macros for the first/last argument registers. */
677 #define GP_ARG_FIRST (GP_REG_FIRST + 2)
678 #define GP_ARG_LAST (GP_REG_FIRST + 7)
679 #define GP_OUTGOING_ARG_FIRST (GP_REG_FIRST + 2 + WINDOW_SIZE)
680 #define GP_OUTGOING_ARG_LAST (GP_REG_FIRST + 7 + WINDOW_SIZE)
682 #define MAX_ARGS_IN_REGISTERS 6
684 /* Don't worry about compatibility with PCC. */
685 #define DEFAULT_PCC_STRUCT_RETURN 0
687 /* Define how to find the value returned by a library function
688 assuming the value has mode MODE. Because we have defined
689 TARGET_PROMOTE_FUNCTION_RETURN that returns true, we have to
690 perform the same promotions as PROMOTE_MODE. */
691 #define XTENSA_LIBCALL_VALUE(MODE, OUTGOINGP) \
692 gen_rtx_REG ((GET_MODE_CLASS (MODE) == MODE_INT \
693 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
695 OUTGOINGP ? GP_OUTGOING_RETURN : GP_RETURN)
697 #define LIBCALL_VALUE(MODE) \
698 XTENSA_LIBCALL_VALUE ((MODE), 0)
700 #define LIBCALL_OUTGOING_VALUE(MODE) \
701 XTENSA_LIBCALL_VALUE ((MODE), 1)
703 /* Define how to find the value returned by a function.
704 VALTYPE is the data type of the value (as a tree).
705 If the precise function being called is known, FUNC is its FUNCTION_DECL;
706 otherwise, FUNC is 0. */
707 #define XTENSA_FUNCTION_VALUE(VALTYPE, FUNC, OUTGOINGP) \
708 gen_rtx_REG ((INTEGRAL_TYPE_P (VALTYPE) \
709 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
710 ? SImode: TYPE_MODE (VALTYPE), \
711 OUTGOINGP ? GP_OUTGOING_RETURN : GP_RETURN)
713 #define FUNCTION_VALUE(VALTYPE, FUNC) \
714 XTENSA_FUNCTION_VALUE (VALTYPE, FUNC, 0)
716 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
717 XTENSA_FUNCTION_VALUE (VALTYPE, FUNC, 1)
719 /* A C expression that is nonzero if REGNO is the number of a hard
720 register in which the values of called function may come back. A
721 register whose use for returning values is limited to serving as
722 the second of a pair (for a value of type 'double', say) need not
723 be recognized by this macro. If the machine has register windows,
724 so that the caller and the called function use different registers
725 for the return value, this macro should recognize only the caller's
727 #define FUNCTION_VALUE_REGNO_P(N) \
730 /* A C expression that is nonzero if REGNO is the number of a hard
731 register in which function arguments are sometimes passed. This
732 does *not* include implicit arguments such as the static chain and
733 the structure-value address. On many machines, no registers can be
734 used for this purpose since all function arguments are pushed on
736 #define FUNCTION_ARG_REGNO_P(N) \
737 ((N) >= GP_OUTGOING_ARG_FIRST && (N) <= GP_OUTGOING_ARG_LAST)
739 /* Record the number of argument words seen so far, along with a flag to
740 indicate whether these are incoming arguments. (FUNCTION_INCOMING_ARG
741 is used for both incoming and outgoing args, so a separate flag is
743 typedef struct xtensa_args
749 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
750 init_cumulative_args (&CUM, 0)
752 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
753 init_cumulative_args (&CUM, 1)
755 /* Update the data in CUM to advance over an argument
756 of mode MODE and data type TYPE.
757 (TYPE is null for libcalls where that information may not be available.) */
758 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
759 function_arg_advance (&CUM, MODE, TYPE)
761 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
762 function_arg (&CUM, MODE, TYPE, FALSE)
764 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
765 function_arg (&CUM, MODE, TYPE, TRUE)
767 /* Arguments are never passed partly in memory and partly in registers. */
768 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) (0)
770 /* Specify function argument alignment. */
771 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
773 ? (TYPE_ALIGN (TYPE) <= PARM_BOUNDARY \
775 : TYPE_ALIGN (TYPE)) \
776 : (GET_MODE_ALIGNMENT (MODE) <= PARM_BOUNDARY \
778 : GET_MODE_ALIGNMENT (MODE)))
780 /* Nonzero if we do not know how to pass TYPE solely in registers.
781 We cannot do so in the following cases:
783 - if the type has variable size
784 - if the type is marked as addressable (it is required to be constructed
787 This differs from the default in that it does not check if the padding
788 and mode of the type are such that a copy into a register would put it
789 into the wrong part of the register. */
791 #define MUST_PASS_IN_STACK(MODE, TYPE) \
793 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
794 || TREE_ADDRESSABLE (TYPE)))
796 /* Pass complex arguments independently. */
797 #define SPLIT_COMPLEX_ARGS 1
799 /* Profiling Xtensa code is typically done with the built-in profiling
800 feature of Tensilica's instruction set simulator, which does not
801 require any compiler support. Profiling code on a real (i.e.,
802 non-simulated) Xtensa processor is currently only supported by
803 GNU/Linux with glibc. The glibc version of _mcount doesn't require
804 counter variables. The _mcount function needs the current PC and
805 the current return address to identify an arc in the call graph.
806 Pass the current return address as the first argument; the current
807 PC is available as a0 in _mcount's register window. Both of these
808 values contain window size information in the two most significant
809 bits; we assume that _mcount will mask off those bits. The call to
810 _mcount uses a window size of 8 to make sure that it doesn't clobber
811 any incoming argument values. */
813 #define NO_PROFILE_COUNTERS 1
815 #define FUNCTION_PROFILER(FILE, LABELNO) \
817 fprintf (FILE, "\t%s\ta10, a0\n", TARGET_DENSITY ? "mov.n" : "mov"); \
820 fprintf (FILE, "\tmovi\ta8, _mcount@PLT\n"); \
821 fprintf (FILE, "\tcallx8\ta8\n"); \
824 fprintf (FILE, "\tcall8\t_mcount\n"); \
827 /* Stack pointer value doesn't matter at exit. */
828 #define EXIT_IGNORE_STACK 1
830 /* A C statement to output, on the stream FILE, assembler code for a
831 block of data that contains the constant parts of a trampoline.
832 This code should not include a label--the label is taken care of
835 For Xtensa, the trampoline must perform an entry instruction with a
836 minimal stack frame in order to get some free registers. Once the
837 actual call target is known, the proper stack frame size is extracted
838 from the entry instruction at the target and the current frame is
839 adjusted to match. The trampoline then transfers control to the
840 instruction following the entry at the target. Note: this assumes
841 that the target begins with an entry instruction. */
843 /* minimum frame = reg save area (4 words) plus static chain (1 word)
844 and the total number of words must be a multiple of 128 bits */
845 #define MIN_FRAME_SIZE (8 * UNITS_PER_WORD)
847 #define TRAMPOLINE_TEMPLATE(STREAM) \
849 fprintf (STREAM, "\t.begin no-generics\n"); \
850 fprintf (STREAM, "\tentry\tsp, %d\n", MIN_FRAME_SIZE); \
852 /* save the return address */ \
853 fprintf (STREAM, "\tmov\ta10, a0\n"); \
855 /* Use a CALL0 instruction to skip past the constants and in the \
856 process get the PC into A0. This allows PC-relative access to \
857 the constants without relying on L32R, which may not always be \
860 fprintf (STREAM, "\tcall0\t.Lskipconsts\n"); \
861 fprintf (STREAM, "\t.align\t4\n"); \
862 fprintf (STREAM, ".Lchainval:%s0\n", integer_asm_op (4, TRUE)); \
863 fprintf (STREAM, ".Lfnaddr:%s0\n", integer_asm_op (4, TRUE)); \
864 fprintf (STREAM, ".Lskipconsts:\n"); \
866 /* store the static chain */ \
867 fprintf (STREAM, "\taddi\ta0, a0, 3\n"); \
868 fprintf (STREAM, "\tl32i\ta8, a0, 0\n"); \
869 fprintf (STREAM, "\ts32i\ta8, sp, %d\n", MIN_FRAME_SIZE - 20); \
871 /* set the proper stack pointer value */ \
872 fprintf (STREAM, "\tl32i\ta8, a0, 4\n"); \
873 fprintf (STREAM, "\tl32i\ta9, a8, 0\n"); \
874 fprintf (STREAM, "\textui\ta9, a9, %d, 12\n", \
875 TARGET_BIG_ENDIAN ? 8 : 12); \
876 fprintf (STREAM, "\tslli\ta9, a9, 3\n"); \
877 fprintf (STREAM, "\taddi\ta9, a9, %d\n", -MIN_FRAME_SIZE); \
878 fprintf (STREAM, "\tsub\ta9, sp, a9\n"); \
879 fprintf (STREAM, "\tmovsp\tsp, a9\n"); \
881 /* restore the return address */ \
882 fprintf (STREAM, "\tmov\ta0, a10\n"); \
884 /* jump to the instruction following the entry */ \
885 fprintf (STREAM, "\taddi\ta8, a8, 3\n"); \
886 fprintf (STREAM, "\tjx\ta8\n"); \
887 fprintf (STREAM, "\t.end no-generics\n"); \
890 /* Size in bytes of the trampoline, as an integer. */
891 #define TRAMPOLINE_SIZE 59
893 /* Alignment required for trampolines, in bits. */
894 #define TRAMPOLINE_ALIGNMENT (32)
896 /* A C statement to initialize the variable parts of a trampoline. */
897 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
900 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 12)), CHAIN); \
901 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 16)), FUNC); \
902 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_sync_caches"), \
903 0, VOIDmode, 1, addr, Pmode); \
906 /* Implement `va_start' for varargs and stdarg. */
907 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
908 xtensa_va_start (valist, nextarg)
910 /* Implement `va_arg'. */
911 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
912 xtensa_va_arg (valist, type)
914 /* If defined, a C expression that produces the machine-specific code
915 to setup the stack so that arbitrary frames can be accessed.
917 On Xtensa, a stack back-trace must always begin from the stack pointer,
918 so that the register overflow save area can be located. However, the
919 stack-walking code in GCC always begins from the hard_frame_pointer
920 register, not the stack pointer. The frame pointer is usually equal
921 to the stack pointer, but the __builtin_return_address and
922 __builtin_frame_address functions will not work if count > 0 and
923 they are called from a routine that uses alloca. These functions
924 are not guaranteed to work at all if count > 0 so maybe that is OK.
926 A nicer solution would be to allow the architecture-specific files to
927 specify whether to start from the stack pointer or frame pointer. That
928 would also allow us to skip the machine->accesses_prev_frame stuff that
929 we currently need to ensure that there is a frame pointer when these
930 builtin functions are used. */
932 #define SETUP_FRAME_ADDRESSES xtensa_setup_frame_addresses
934 /* A C expression whose value is RTL representing the address in a
935 stack frame where the pointer to the caller's frame is stored.
936 Assume that FRAMEADDR is an RTL expression for the address of the
939 For Xtensa, there is no easy way to get the frame pointer if it is
940 not equivalent to the stack pointer. Moreover, the result of this
941 macro is used for continuing to walk back up the stack, so it must
942 return the stack pointer address. Thus, there is some inconsistency
943 here in that __builtin_frame_address will return the frame pointer
944 when count == 0 and the stack pointer when count > 0. */
946 #define DYNAMIC_CHAIN_ADDRESS(frame) \
947 gen_rtx_PLUS (Pmode, frame, GEN_INT (-3 * UNITS_PER_WORD))
949 /* Define this if the return address of a particular stack frame is
950 accessed from the frame pointer of the previous stack frame. */
951 #define RETURN_ADDR_IN_PREVIOUS_FRAME
953 /* A C expression whose value is RTL representing the value of the
954 return address for the frame COUNT steps up from the current
955 frame, after the prologue. */
956 #define RETURN_ADDR_RTX xtensa_return_addr
958 /* Addressing modes, and classification of registers for them. */
960 /* C expressions which are nonzero if register number NUM is suitable
961 for use as a base or index register in operand addresses. It may
962 be either a suitable hard register or a pseudo register that has
963 been allocated such a hard register. The difference between an
964 index register and a base register is that the index register may
967 #define REGNO_OK_FOR_BASE_P(NUM) \
968 (GP_REG_P (NUM) || GP_REG_P ((unsigned) reg_renumber[NUM]))
970 #define REGNO_OK_FOR_INDEX_P(NUM) 0
972 /* C expressions that are nonzero if X (assumed to be a `reg' RTX) is
973 valid for use as a base or index register. For hard registers, it
974 should always accept those which the hardware permits and reject
975 the others. Whether the macro accepts or rejects pseudo registers
976 must be controlled by `REG_OK_STRICT'. This usually requires two
977 variant definitions, of which `REG_OK_STRICT' controls the one
978 actually used. The difference between an index register and a base
979 register is that the index register may be scaled. */
983 #define REG_OK_FOR_INDEX_P(X) 0
984 #define REG_OK_FOR_BASE_P(X) \
985 REGNO_OK_FOR_BASE_P (REGNO (X))
987 #else /* !REG_OK_STRICT */
989 #define REG_OK_FOR_INDEX_P(X) 0
990 #define REG_OK_FOR_BASE_P(X) \
991 ((REGNO (X) >= FIRST_PSEUDO_REGISTER) || (GP_REG_P (REGNO (X))))
993 #endif /* !REG_OK_STRICT */
995 /* Maximum number of registers that can appear in a valid memory address. */
996 #define MAX_REGS_PER_ADDRESS 1
998 /* Identify valid Xtensa addresses. */
999 #define GO_IF_LEGITIMATE_ADDRESS(MODE, ADDR, LABEL) \
1001 rtx xinsn = (ADDR); \
1003 /* allow constant pool addresses */ \
1004 if ((MODE) != BLKmode && GET_MODE_SIZE (MODE) >= UNITS_PER_WORD \
1005 && !TARGET_CONST16 && constantpool_address_p (xinsn)) \
1008 while (GET_CODE (xinsn) == SUBREG) \
1009 xinsn = SUBREG_REG (xinsn); \
1011 /* allow base registers */ \
1012 if (GET_CODE (xinsn) == REG && REG_OK_FOR_BASE_P (xinsn)) \
1015 /* check for "register + offset" addressing */ \
1016 if (GET_CODE (xinsn) == PLUS) \
1018 rtx xplus0 = XEXP (xinsn, 0); \
1019 rtx xplus1 = XEXP (xinsn, 1); \
1020 enum rtx_code code0; \
1021 enum rtx_code code1; \
1023 while (GET_CODE (xplus0) == SUBREG) \
1024 xplus0 = SUBREG_REG (xplus0); \
1025 code0 = GET_CODE (xplus0); \
1027 while (GET_CODE (xplus1) == SUBREG) \
1028 xplus1 = SUBREG_REG (xplus1); \
1029 code1 = GET_CODE (xplus1); \
1031 /* swap operands if necessary so the register is first */ \
1032 if (code0 != REG && code1 == REG) \
1034 xplus0 = XEXP (xinsn, 1); \
1035 xplus1 = XEXP (xinsn, 0); \
1036 code0 = GET_CODE (xplus0); \
1037 code1 = GET_CODE (xplus1); \
1040 if (code0 == REG && REG_OK_FOR_BASE_P (xplus0) \
1041 && code1 == CONST_INT \
1042 && xtensa_mem_offset (INTVAL (xplus1), (MODE))) \
1049 /* A C expression that is 1 if the RTX X is a constant which is a
1050 valid address. This is defined to be the same as 'CONSTANT_P (X)',
1051 but rejecting CONST_DOUBLE. */
1052 #define CONSTANT_ADDRESS_P(X) \
1053 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1054 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
1055 || (GET_CODE (X) == CONST)))
1057 /* Nonzero if the constant value X is a legitimate general operand.
1058 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1059 #define LEGITIMATE_CONSTANT_P(X) 1
1061 /* A C expression that is nonzero if X is a legitimate immediate
1062 operand on the target machine when generating position independent
1064 #define LEGITIMATE_PIC_OPERAND_P(X) \
1065 ((GET_CODE (X) != SYMBOL_REF || SYMBOL_REF_LOCAL_P (X)) \
1066 && GET_CODE (X) != LABEL_REF \
1067 && GET_CODE (X) != CONST)
1069 /* Tell GCC how to use ADDMI to generate addresses. */
1070 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1073 if (GET_CODE (xinsn) == PLUS) \
1075 rtx plus0 = XEXP (xinsn, 0); \
1076 rtx plus1 = XEXP (xinsn, 1); \
1078 if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG) \
1080 plus0 = XEXP (xinsn, 1); \
1081 plus1 = XEXP (xinsn, 0); \
1084 if (GET_CODE (plus0) == REG \
1085 && GET_CODE (plus1) == CONST_INT \
1086 && !xtensa_mem_offset (INTVAL (plus1), MODE) \
1087 && !xtensa_simm8 (INTVAL (plus1)) \
1088 && xtensa_mem_offset (INTVAL (plus1) & 0xff, MODE) \
1089 && xtensa_simm8x256 (INTVAL (plus1) & ~0xff)) \
1091 rtx temp = gen_reg_rtx (Pmode); \
1092 emit_insn (gen_rtx_SET (Pmode, temp, \
1093 gen_rtx_PLUS (Pmode, plus0, \
1094 GEN_INT (INTVAL (plus1) & ~0xff)))); \
1095 (X) = gen_rtx_PLUS (Pmode, temp, \
1096 GEN_INT (INTVAL (plus1) & 0xff)); \
1103 /* Treat constant-pool references as "mode dependent" since they can
1104 only be accessed with SImode loads. This works around a bug in the
1105 combiner where a constant pool reference is temporarily converted
1106 to an HImode load, which is then assumed to zero-extend based on
1107 our definition of LOAD_EXTEND_OP. This is wrong because the high
1108 bits of a 16-bit value in the constant pool are now sign-extended
1111 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1113 if (constantpool_address_p (ADDR)) \
1117 /* Specify the machine mode that this machine uses
1118 for the index in the tablejump instruction. */
1119 #define CASE_VECTOR_MODE (SImode)
1121 /* Define this if the tablejump instruction expects the table
1122 to contain offsets from the address of the table.
1123 Do not define this if the table should contain absolute addresses. */
1124 /* #define CASE_VECTOR_PC_RELATIVE */
1126 /* Define this as 1 if 'char' should by default be signed; else as 0. */
1127 #define DEFAULT_SIGNED_CHAR 0
1129 /* Max number of bytes we can move from memory to memory
1130 in one reasonably fast instruction. */
1132 #define MAX_MOVE_MAX 4
1134 /* Prefer word-sized loads. */
1135 #define SLOW_BYTE_ACCESS 1
1137 /* Shift instructions ignore all but the low-order few bits. */
1138 #define SHIFT_COUNT_TRUNCATED 1
1140 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1141 is done just by pretending it is already truncated. */
1142 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1144 /* Specify the machine mode that pointers have.
1145 After generation of rtl, the compiler makes no further distinction
1146 between pointers and any other objects of this machine mode. */
1147 #define Pmode SImode
1149 /* A function address in a call instruction is a word address (for
1150 indexing purposes) so give the MEM rtx a words's mode. */
1151 #define FUNCTION_MODE SImode
1153 /* A C expression for the cost of moving data from a register in
1154 class FROM to one in class TO. The classes are expressed using
1155 the enumeration values such as 'GENERAL_REGS'. A value of 2 is
1156 the default; other values are interpreted relative to that. */
1157 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1158 (((FROM) == (TO) && (FROM) != BR_REGS && (TO) != BR_REGS) \
1160 : (reg_class_subset_p ((FROM), AR_REGS) \
1161 && reg_class_subset_p ((TO), AR_REGS) \
1163 : (reg_class_subset_p ((FROM), AR_REGS) \
1164 && (TO) == ACC_REG \
1166 : ((FROM) == ACC_REG \
1167 && reg_class_subset_p ((TO), AR_REGS) \
1171 #define MEMORY_MOVE_COST(MODE, CLASS, IN) 4
1173 #define BRANCH_COST 3
1175 /* Optionally define this if you have added predicates to
1176 'MACHINE.c'. This macro is called within an initializer of an
1177 array of structures. The first field in the structure is the
1178 name of a predicate and the second field is an array of rtl
1179 codes. For each predicate, list all rtl codes that can be in
1180 expressions matched by the predicate. The list should have a
1183 #define PREDICATE_CODES \
1184 {"add_operand", { REG, CONST_INT, SUBREG }}, \
1185 {"arith_operand", { REG, CONST_INT, SUBREG }}, \
1186 {"nonimmed_operand", { REG, SUBREG, MEM }}, \
1187 {"mem_operand", { MEM }}, \
1188 {"mask_operand", { REG, CONST_INT, SUBREG }}, \
1189 {"extui_fldsz_operand", { CONST_INT }}, \
1190 {"sext_fldsz_operand", { CONST_INT }}, \
1191 {"lsbitnum_operand", { CONST_INT }}, \
1192 {"fpmem_offset_operand", { CONST_INT }}, \
1193 {"sext_operand", { REG, SUBREG, MEM }}, \
1194 {"branch_operand", { REG, CONST_INT, SUBREG }}, \
1195 {"ubranch_operand", { REG, CONST_INT, SUBREG }}, \
1196 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG }}, \
1197 {"move_operand", { REG, SUBREG, MEM, CONST_INT, CONST_DOUBLE, \
1198 CONST, SYMBOL_REF, LABEL_REF }}, \
1199 {"const_float_1_operand", { CONST_DOUBLE }}, \
1200 {"branch_operator", { EQ, NE, LT, GE }}, \
1201 {"ubranch_operator", { LTU, GEU }}, \
1202 {"boolean_operator", { EQ, NE }},
1204 /* Control the assembler format that we output. */
1206 /* How to refer to registers in assembler output.
1207 This sequence is indexed by compiler's hard-register-number (see above). */
1208 #define REGISTER_NAMES \
1210 "a0", "sp", "a2", "a3", "a4", "a5", "a6", "a7", \
1211 "a8", "a9", "a10", "a11", "a12", "a13", "a14", "a15", \
1212 "fp", "argp", "b0", \
1213 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
1214 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
1218 /* If defined, a C initializer for an array of structures containing a
1219 name and a register number. This macro defines additional names
1220 for hard registers, thus allowing the 'asm' option in declarations
1221 to refer to registers using alternate names. */
1222 #define ADDITIONAL_REGISTER_NAMES \
1224 { "a1", 1 + GP_REG_FIRST } \
1227 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1228 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
1230 /* Recognize machine-specific patterns that may appear within
1231 constants. Used for PIC-specific UNSPECs. */
1232 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
1234 if (flag_pic && GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \
1236 switch (XINT ((X), 1)) \
1239 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
1240 fputs ("@PLT", (STREAM)); \
1251 /* Globalizing directive for a label. */
1252 #define GLOBAL_ASM_OP "\t.global\t"
1254 /* Declare an uninitialized external linkage data object. */
1255 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1256 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
1258 /* This is how to output an element of a case-vector that is absolute. */
1259 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
1260 fprintf (STREAM, "%s%sL%u\n", integer_asm_op (4, TRUE), \
1261 LOCAL_LABEL_PREFIX, VALUE)
1263 /* This is how to output an element of a case-vector that is relative.
1264 This is used for pc-relative code. */
1265 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
1267 fprintf (STREAM, "%s%sL%u-%sL%u\n", integer_asm_op (4, TRUE), \
1268 LOCAL_LABEL_PREFIX, (VALUE), \
1269 LOCAL_LABEL_PREFIX, (REL)); \
1272 /* This is how to output an assembler line that says to advance the
1273 location counter to a multiple of 2**LOG bytes. */
1274 #define ASM_OUTPUT_ALIGN(STREAM, LOG) \
1277 fprintf (STREAM, "\t.align\t%d\n", 1 << (LOG)); \
1280 /* Indicate that jump tables go in the text section. This is
1281 necessary when compiling PIC code. */
1282 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
1285 /* Define the strings to put out for each section in the object file. */
1286 #define TEXT_SECTION_ASM_OP "\t.text"
1287 #define DATA_SECTION_ASM_OP "\t.data"
1288 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
1291 /* Define output to appear before the constant pool. If the function
1292 has been assigned to a specific ELF section, or if it goes into a
1293 unique section, set the name of that section to be the literal
1295 #define ASM_OUTPUT_POOL_PROLOGUE(FILE, FUNNAME, FUNDECL, SIZE) \
1298 resolve_unique_section ((FUNDECL), 0, flag_function_sections); \
1299 fnsection = DECL_SECTION_NAME (FUNDECL); \
1300 if (fnsection != NULL_TREE) \
1302 const char *fnsectname = TREE_STRING_POINTER (fnsection); \
1303 fprintf (FILE, "\t.begin\tliteral_prefix %s\n", \
1304 strcmp (fnsectname, ".text") ? fnsectname : ""); \
1308 function_section (FUNDECL); \
1309 fprintf (FILE, "\t.literal_position\n"); \
1314 /* Define code to write out the ".end literal_prefix" directive for a
1315 function in a special section. This is appended to the standard ELF
1316 code for ASM_DECLARE_FUNCTION_SIZE. */
1317 #define XTENSA_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL) \
1318 if (DECL_SECTION_NAME (DECL) != NULL_TREE) \
1319 fprintf (FILE, "\t.end\tliteral_prefix\n")
1321 /* A C statement (with or without semicolon) to output a constant in
1322 the constant pool, if it needs special treatment. */
1323 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, JUMPTO) \
1325 xtensa_output_literal (FILE, X, MODE, LABELNO); \
1329 /* How to start an assembler comment. */
1330 #define ASM_COMMENT_START "#"
1332 /* Exception handling TODO!! */
1333 #define DWARF_UNWIND_INFO 0
1335 /* Xtensa constant pool breaks the devices in crtstuff.c to control
1336 section in where code resides. We have to write it as asm code. Use
1337 a MOVI and let the assembler relax it -- for the .init and .fini
1338 sections, the assembler knows to put the literal in the right
1340 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
1341 asm (SECTION_OP "\n\
1342 movi\ta8, " USER_LABEL_PREFIX #FUNC "\n\
1344 TEXT_SECTION_ASM_OP);
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