1 /* Definitions of Tensilica's Xtensa target machine for GNU compiler.
2 Copyright (C) 2001 Free Software Foundation, Inc.
3 Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* Get Xtensa configuration settings */
23 #include "xtensa/xtensa-config.h"
25 /* Standard GCC variables that we reference. */
26 extern int current_function_calls_alloca;
27 extern int target_flags;
30 /* External variables defined in xtensa.c. */
34 CMP_SI, /* four byte integers */
35 CMP_DI, /* eight byte integers */
36 CMP_SF, /* single precision floats */
37 CMP_DF, /* double precision floats */
38 CMP_MAX /* max comparison type */
41 extern struct rtx_def * branch_cmp[2]; /* operands for compare */
42 extern enum cmp_type branch_type; /* what type of branch to use */
43 extern unsigned xtensa_current_frame_size;
45 /* Run-time compilation parameters selecting different hardware subsets. */
47 #define MASK_BIG_ENDIAN 0x00000001 /* big or little endian */
48 #define MASK_DENSITY 0x00000002 /* code density option */
49 #define MASK_MAC16 0x00000004 /* MAC16 option */
50 #define MASK_MUL16 0x00000008 /* 16-bit integer multiply */
51 #define MASK_MUL32 0x00000010 /* integer multiply/divide */
52 #define MASK_DIV32 0x00000020 /* integer multiply/divide */
53 #define MASK_NSA 0x00000040 /* nsa instruction option */
54 #define MASK_MINMAX 0x00000080 /* min/max instructions */
55 #define MASK_SEXT 0x00000100 /* sign extend insn option */
56 #define MASK_BOOLEANS 0x00000200 /* boolean register option */
57 #define MASK_HARD_FLOAT 0x00000400 /* floating-point option */
58 #define MASK_HARD_FLOAT_DIV 0x00000800 /* floating-point divide */
59 #define MASK_HARD_FLOAT_RECIP 0x00001000 /* floating-point reciprocal */
60 #define MASK_HARD_FLOAT_SQRT 0x00002000 /* floating-point sqrt */
61 #define MASK_HARD_FLOAT_RSQRT 0x00004000 /* floating-point recip sqrt */
62 #define MASK_NO_FUSED_MADD 0x00008000 /* avoid f-p mul/add */
63 #define MASK_SERIALIZE_VOLATILE 0x00010000 /* serialize volatile refs */
65 /* Macros used in the machine description to test the flags. */
67 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
68 #define TARGET_DENSITY (target_flags & MASK_DENSITY)
69 #define TARGET_MAC16 (target_flags & MASK_MAC16)
70 #define TARGET_MUL16 (target_flags & MASK_MUL16)
71 #define TARGET_MUL32 (target_flags & MASK_MUL32)
72 #define TARGET_DIV32 (target_flags & MASK_DIV32)
73 #define TARGET_NSA (target_flags & MASK_NSA)
74 #define TARGET_MINMAX (target_flags & MASK_MINMAX)
75 #define TARGET_SEXT (target_flags & MASK_SEXT)
76 #define TARGET_BOOLEANS (target_flags & MASK_BOOLEANS)
77 #define TARGET_HARD_FLOAT (target_flags & MASK_HARD_FLOAT)
78 #define TARGET_HARD_FLOAT_DIV (target_flags & MASK_HARD_FLOAT_DIV)
79 #define TARGET_HARD_FLOAT_RECIP (target_flags & MASK_HARD_FLOAT_RECIP)
80 #define TARGET_HARD_FLOAT_SQRT (target_flags & MASK_HARD_FLOAT_SQRT)
81 #define TARGET_HARD_FLOAT_RSQRT (target_flags & MASK_HARD_FLOAT_RSQRT)
82 #define TARGET_NO_FUSED_MADD (target_flags & MASK_NO_FUSED_MADD)
83 #define TARGET_SERIALIZE_VOLATILE (target_flags & MASK_SERIALIZE_VOLATILE)
85 /* Default target_flags if no switches are specified */
87 #define TARGET_DEFAULT ( \
88 (XCHAL_HAVE_BE ? MASK_BIG_ENDIAN : 0) | \
89 (XCHAL_HAVE_DENSITY ? MASK_DENSITY : 0) | \
90 (XCHAL_HAVE_MAC16 ? MASK_MAC16 : 0) | \
91 (XCHAL_HAVE_MUL16 ? MASK_MUL16 : 0) | \
92 (XCHAL_HAVE_MUL32 ? MASK_MUL32 : 0) | \
93 (XCHAL_HAVE_DIV32 ? MASK_DIV32 : 0) | \
94 (XCHAL_HAVE_NSA ? MASK_NSA : 0) | \
95 (XCHAL_HAVE_MINMAX ? MASK_MINMAX : 0) | \
96 (XCHAL_HAVE_SEXT ? MASK_SEXT : 0) | \
97 (XCHAL_HAVE_BOOLEANS ? MASK_BOOLEANS : 0) | \
98 (XCHAL_HAVE_FP ? MASK_HARD_FLOAT : 0) | \
99 (XCHAL_HAVE_FP_DIV ? MASK_HARD_FLOAT_DIV : 0) | \
100 (XCHAL_HAVE_FP_RECIP ? MASK_HARD_FLOAT_RECIP : 0) | \
101 (XCHAL_HAVE_FP_SQRT ? MASK_HARD_FLOAT_SQRT : 0) | \
102 (XCHAL_HAVE_FP_RSQRT ? MASK_HARD_FLOAT_RSQRT : 0) | \
103 MASK_SERIALIZE_VOLATILE)
105 /* Macro to define tables used to set the flags. */
107 #define TARGET_SWITCHES \
109 {"big-endian", MASK_BIG_ENDIAN, \
110 N_("Use big-endian byte order")}, \
111 {"little-endian", -MASK_BIG_ENDIAN, \
112 N_("Use little-endian byte order")}, \
113 {"density", MASK_DENSITY, \
114 N_("Use the Xtensa code density option")}, \
115 {"no-density", -MASK_DENSITY, \
116 N_("Do not use the Xtensa code density option")}, \
117 {"mac16", MASK_MAC16, \
118 N_("Use the Xtensa MAC16 option")}, \
119 {"no-mac16", -MASK_MAC16, \
120 N_("Do not use the Xtensa MAC16 option")}, \
121 {"mul16", MASK_MUL16, \
122 N_("Use the Xtensa MUL16 option")}, \
123 {"no-mul16", -MASK_MUL16, \
124 N_("Do not use the Xtensa MUL16 option")}, \
125 {"mul32", MASK_MUL32, \
126 N_("Use the Xtensa MUL32 option")}, \
127 {"no-mul32", -MASK_MUL32, \
128 N_("Do not use the Xtensa MUL32 option")}, \
129 {"div32", MASK_DIV32, \
130 0 /* undocumented */}, \
131 {"no-div32", -MASK_DIV32, \
132 0 /* undocumented */}, \
134 N_("Use the Xtensa NSA option")}, \
135 {"no-nsa", -MASK_NSA, \
136 N_("Do not use the Xtensa NSA option")}, \
137 {"minmax", MASK_MINMAX, \
138 N_("Use the Xtensa MIN/MAX option")}, \
139 {"no-minmax", -MASK_MINMAX, \
140 N_("Do not use the Xtensa MIN/MAX option")}, \
141 {"sext", MASK_SEXT, \
142 N_("Use the Xtensa SEXT option")}, \
143 {"no-sext", -MASK_SEXT, \
144 N_("Do not use the Xtensa SEXT option")}, \
145 {"booleans", MASK_BOOLEANS, \
146 N_("Use the Xtensa boolean register option")}, \
147 {"no-booleans", -MASK_BOOLEANS, \
148 N_("Do not use the Xtensa boolean register option")}, \
149 {"hard-float", MASK_HARD_FLOAT, \
150 N_("Use the Xtensa floating-point unit")}, \
151 {"soft-float", -MASK_HARD_FLOAT, \
152 N_("Do not use the Xtensa floating-point unit")}, \
153 {"hard-float-div", MASK_HARD_FLOAT_DIV, \
154 0 /* undocumented */}, \
155 {"no-hard-float-div", -MASK_HARD_FLOAT_DIV, \
156 0 /* undocumented */}, \
157 {"hard-float-recip", MASK_HARD_FLOAT_RECIP, \
158 0 /* undocumented */}, \
159 {"no-hard-float-recip", -MASK_HARD_FLOAT_RECIP, \
160 0 /* undocumented */}, \
161 {"hard-float-sqrt", MASK_HARD_FLOAT_SQRT, \
162 0 /* undocumented */}, \
163 {"no-hard-float-sqrt", -MASK_HARD_FLOAT_SQRT, \
164 0 /* undocumented */}, \
165 {"hard-float-rsqrt", MASK_HARD_FLOAT_RSQRT, \
166 0 /* undocumented */}, \
167 {"no-hard-float-rsqrt", -MASK_HARD_FLOAT_RSQRT, \
168 0 /* undocumented */}, \
169 {"no-fused-madd", MASK_NO_FUSED_MADD, \
170 N_("Disable fused multiply/add and multiply/subtract FP instructions")}, \
171 {"fused-madd", -MASK_NO_FUSED_MADD, \
172 N_("Enable fused multiply/add and multiply/subtract FP instructions")}, \
173 {"serialize-volatile", MASK_SERIALIZE_VOLATILE, \
174 N_("Serialize volatile memory references with MEMW instructions")}, \
175 {"no-serialize-volatile", -MASK_SERIALIZE_VOLATILE, \
176 N_("Do not serialize volatile memory references with MEMW instructions")},\
177 {"text-section-literals", 0, \
178 N_("Intersperse literal pools with code in the text section")}, \
179 {"no-text-section-literals", 0, \
180 N_("Put literal pools in a separate literal section")}, \
181 {"target-align", 0, \
182 N_("Automatically align branch targets to reduce branch penalties")}, \
183 {"no-target-align", 0, \
184 N_("Do not automatically align branch targets")}, \
186 N_("Use indirect CALLXn instructions for large programs")}, \
187 {"no-longcalls", 0, \
188 N_("Use direct CALLn instructions for fast calls")}, \
189 {"", TARGET_DEFAULT, 0} \
193 #define OVERRIDE_OPTIONS override_options ()
196 #define CPP_ENDIAN_SPEC "\
197 %{mlittle-endian:-D__XTENSA_EL__} \
198 %{!mlittle-endian:-D__XTENSA_EB__} "
199 #else /* !XCHAL_HAVE_BE */
200 #define CPP_ENDIAN_SPEC "\
201 %{mbig-endian:-D__XTENSA_EB__} \
202 %{!mbig-endian:-D__XTENSA_EL__} "
203 #endif /* !XCHAL_HAVE_BE */
206 #define CPP_FLOAT_SPEC "%{msoft-float:-D__XTENSA_SOFT_FLOAT__}"
208 #define CPP_FLOAT_SPEC "%{!mhard-float:-D__XTENSA_SOFT_FLOAT__}"
212 #define CPP_SPEC CPP_ENDIAN_SPEC CPP_FLOAT_SPEC
214 /* Define this to set the endianness to use in libgcc2.c, which can
215 not depend on target_flags. */
216 #define LIBGCC2_WORDS_BIG_ENDIAN XCHAL_HAVE_BE
218 /* Show we can debug even without a frame pointer. */
219 #define CAN_DEBUG_WITHOUT_FP
222 /* Target machine storage layout */
224 /* Define in order to support both big and little endian float formats
225 in the same gcc binary. */
226 #define REAL_ARITHMETIC
228 /* Define this if most significant bit is lowest numbered
229 in instructions that operate on numbered bit-fields. */
230 #define BITS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
232 /* Define this if most significant byte of a word is the lowest numbered. */
233 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
235 /* Define this if most significant word of a multiword number is the lowest. */
236 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
238 /* Width in bits of a "word", which is the contents of a machine register. */
239 #define BITS_PER_WORD 32
240 #define MAX_BITS_PER_WORD 32
242 /* Width of a word, in units (bytes). */
243 #define UNITS_PER_WORD 4
244 #define MIN_UNITS_PER_WORD 4
246 /* Width of a floating point register. */
247 #define UNITS_PER_FPREG 4
249 /* Size in bits of various types on the target machine. */
250 #define INT_TYPE_SIZE 32
251 #define MAX_INT_TYPE_SIZE 32
252 #define SHORT_TYPE_SIZE 16
253 #define LONG_TYPE_SIZE 32
254 #define MAX_LONG_TYPE_SIZE 32
255 #define LONG_LONG_TYPE_SIZE 64
256 #define FLOAT_TYPE_SIZE 32
257 #define DOUBLE_TYPE_SIZE 64
258 #define LONG_DOUBLE_TYPE_SIZE 64
259 #define POINTER_SIZE 32
261 /* Tell the preprocessor the maximum size of wchar_t. */
262 #ifndef MAX_WCHAR_TYPE_SIZE
263 #ifndef WCHAR_TYPE_SIZE
264 #define MAX_WCHAR_TYPE_SIZE MAX_INT_TYPE_SIZE
268 /* Allocation boundary (in *bits*) for storing pointers in memory. */
269 #define POINTER_BOUNDARY 32
271 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
272 #define PARM_BOUNDARY 32
274 /* Allocation boundary (in *bits*) for the code of a function. */
275 #define FUNCTION_BOUNDARY 32
277 /* Alignment of field after 'int : 0' in a structure. */
278 #define EMPTY_FIELD_BOUNDARY 32
280 /* Every structure's size must be a multiple of this. */
281 #define STRUCTURE_SIZE_BOUNDARY 8
283 /* There is no point aligning anything to a rounder boundary than this. */
284 #define BIGGEST_ALIGNMENT 128
286 /* Set this nonzero if move instructions will actually fail to work
287 when given unaligned data. */
288 #define STRICT_ALIGNMENT 1
290 /* Promote integer modes smaller than a word to SImode. Set UNSIGNEDP
291 for QImode, because there is no 8-bit load from memory with sign
292 extension. Otherwise, leave UNSIGNEDP alone, since Xtensa has 16-bit
293 loads both with and without sign extension. */
294 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
296 if (GET_MODE_CLASS (MODE) == MODE_INT \
297 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
299 if ((MODE) == QImode) \
305 /* The promotion described by `PROMOTE_MODE' should also be done for
306 outgoing function arguments. */
307 #define PROMOTE_FUNCTION_ARGS
309 /* The promotion described by `PROMOTE_MODE' should also be done for
310 the return value of functions. Note: `FUNCTION_VALUE' must perform
311 the same promotions done by `PROMOTE_MODE'. */
312 #define PROMOTE_FUNCTION_RETURN
314 /* Imitate the way many other C compilers handle alignment of
315 bitfields and the structures that contain them. */
316 #define PCC_BITFIELD_TYPE_MATTERS 1
318 /* Align string constants and constructors to at least a word boundary.
319 The typical use of this macro is to increase alignment for string
320 constants to be word aligned so that 'strcpy' calls that copy
321 constants can be done inline. */
322 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
323 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
324 && (ALIGN) < BITS_PER_WORD \
328 /* Align arrays, unions and records to at least a word boundary.
329 One use of this macro is to increase alignment of medium-size
330 data to make it all fit in fewer cache lines. Another is to
331 cause character arrays to be word-aligned so that 'strcpy' calls
332 that copy constants to character arrays can be done inline. */
333 #undef DATA_ALIGNMENT
334 #define DATA_ALIGNMENT(TYPE, ALIGN) \
335 ((((ALIGN) < BITS_PER_WORD) \
336 && (TREE_CODE (TYPE) == ARRAY_TYPE \
337 || TREE_CODE (TYPE) == UNION_TYPE \
338 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
340 /* An argument declared as 'char' or 'short' in a prototype should
341 actually be passed as an 'int'. */
342 #define PROMOTE_PROTOTYPES 1
344 /* Operations between registers always perform the operation
345 on the full register even if a narrower mode is specified. */
346 #define WORD_REGISTER_OPERATIONS
348 /* Xtensa loads are zero-extended by default. */
349 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
351 /* Standard register usage. */
353 /* Number of actual hardware registers.
354 The hardware registers are assigned numbers for the compiler
355 from 0 to just below FIRST_PSEUDO_REGISTER.
356 All registers that the compiler knows about must be given numbers,
357 even those that are not normally considered general registers.
359 The fake frame pointer and argument pointer will never appear in
360 the generated code, since they will always be eliminated and replaced
361 by either the stack pointer or the hard frame pointer.
363 0 - 15 AR[0] - AR[15]
364 16 FRAME_POINTER (fake = initial sp)
365 17 ARG_POINTER (fake = initial sp + framesize)
366 18 LOOP_COUNT (loop count special register)
367 18 BR[0] for floating-point CC
368 19 - 34 FR[0] - FR[15]
369 35 MAC16 accumulator */
371 #define FIRST_PSEUDO_REGISTER 36
373 /* Return the stabs register number to use for REGNO. */
374 #define DBX_REGISTER_NUMBER(REGNO) xtensa_dbx_register_number (REGNO)
376 /* 1 for registers that have pervasive standard uses
377 and are not available for the register allocator. */
378 #define FIXED_REGISTERS \
380 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
382 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
386 /* 1 for registers not available across function calls.
387 These must include the FIXED_REGISTERS and also any
388 registers that can be used without being saved.
389 The latter must include the registers where values are returned
390 and the register where structure-value addresses are passed.
391 Aside from that, you can include as many other registers as you like. */
392 #define CALL_USED_REGISTERS \
394 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
396 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
400 /* For non-leaf procedures on Xtensa processors, the allocation order
401 is as specified below by REG_ALLOC_ORDER. For leaf procedures, we
402 want to use the lowest numbered registers first to minimize
403 register window overflows. However, local-alloc is not smart
404 enough to consider conflicts with incoming arguments. If an
405 incoming argument in a2 is live throughout the function and
406 local-alloc decides to use a2, then the incoming argument must
407 either be spilled or copied to another register. To get around
408 this, we define ORDER_REGS_FOR_LOCAL_ALLOC to redefine
409 reg_alloc_order for leaf functions such that lowest numbered
410 registers are used first with the exception that the incoming
411 argument registers are not used until after other register choices
412 have been exhausted. */
414 #define REG_ALLOC_ORDER \
415 { 8, 9, 10, 11, 12, 13, 14, 15, 7, 6, 5, 4, 3, 2, 19, \
416 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, \
421 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
423 /* For Xtensa, the only point of this is to prevent GCC from otherwise
424 giving preference to call-used registers. To minimize window
425 overflows for the AR registers, we want to give preference to the
426 lower-numbered AR registers. For other register files, which are
427 not windowed, we still prefer call-used registers, if there are any. */
428 extern const char xtensa_leaf_regs[FIRST_PSEUDO_REGISTER];
429 #define LEAF_REGISTERS xtensa_leaf_regs
431 /* For Xtensa, no remapping is necessary, but this macro must be
432 defined if LEAF_REGISTERS is defined. */
433 #define LEAF_REG_REMAP(REGNO) (REGNO)
435 /* this must be declared if LEAF_REGISTERS is set */
436 extern int leaf_function;
438 /* Internal macros to classify a register number. */
440 /* 16 address registers + fake registers */
441 #define GP_REG_FIRST 0
442 #define GP_REG_LAST 17
443 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
445 /* Special registers */
446 #define SPEC_REG_FIRST 18
447 #define SPEC_REG_LAST 18
448 #define SPEC_REG_NUM (SPEC_REG_LAST - SPEC_REG_FIRST + 1)
450 /* Coprocessor registers */
451 #define BR_REG_FIRST 18
452 #define BR_REG_LAST 18
453 #define BR_REG_NUM (BR_REG_LAST - BR_REG_FIRST + 1)
455 /* 16 floating-point registers */
456 #define FP_REG_FIRST 19
457 #define FP_REG_LAST 34
458 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
460 /* MAC16 accumulator */
461 #define ACC_REG_FIRST 35
462 #define ACC_REG_LAST 35
463 #define ACC_REG_NUM (ACC_REG_LAST - ACC_REG_FIRST + 1)
465 #define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM)
466 #define BR_REG_P(REGNO) ((unsigned) ((REGNO) - BR_REG_FIRST) < BR_REG_NUM)
467 #define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM)
468 #define ACC_REG_P(REGNO) ((unsigned) ((REGNO) - ACC_REG_FIRST) < ACC_REG_NUM)
470 /* Return number of consecutive hard regs needed starting at reg REGNO
471 to hold something of mode MODE. */
472 #define HARD_REGNO_NREGS(REGNO, MODE) \
473 (FP_REG_P (REGNO) ? \
474 ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG) : \
475 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
477 /* Value is 1 if hard register REGNO can hold a value of machine-mode
479 extern char xtensa_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
481 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
482 xtensa_hard_regno_mode_ok[(int) (MODE)][(REGNO)]
484 /* Value is 1 if it is a good idea to tie two pseudo registers
485 when one has mode MODE1 and one has mode MODE2.
486 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
487 for any hard reg, then this must be 0 for correct output. */
488 #define MODES_TIEABLE_P(MODE1, MODE2) \
489 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
490 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
491 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
492 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
494 /* Register to use for LCOUNT special register. */
495 #define COUNT_REGISTER_REGNUM (SPEC_REG_FIRST + 0)
497 /* Register to use for pushing function arguments. */
498 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 1)
500 /* Base register for access to local variables of the function. */
501 #define HARD_FRAME_POINTER_REGNUM (GP_REG_FIRST + 7)
503 /* The register number of the frame pointer register, which is used to
504 access automatic variables in the stack frame. For Xtensa, this
505 register never appears in the output. It is always eliminated to
506 either the stack pointer or the hard frame pointer. */
507 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 16)
509 /* Value should be nonzero if functions must have frame pointers.
510 Zero means the frame pointer need not be set up (and parms
511 may be accessed via the stack pointer) in functions that seem suitable.
512 This is computed in 'reload', in reload1.c. */
513 #define FRAME_POINTER_REQUIRED xtensa_frame_pointer_required ()
515 /* Base register for access to arguments of the function. */
516 #define ARG_POINTER_REGNUM (GP_REG_FIRST + 17)
518 /* If the static chain is passed in memory, these macros provide rtx
519 giving 'mem' expressions that denote where they are stored.
520 'STATIC_CHAIN' and 'STATIC_CHAIN_INCOMING' give the locations as
521 seen by the calling and called functions, respectively. */
523 #define STATIC_CHAIN \
524 gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, -5 * UNITS_PER_WORD))
526 #define STATIC_CHAIN_INCOMING \
527 gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -5 * UNITS_PER_WORD))
529 /* For now we don't try to use the full set of boolean registers. Without
530 software pipelining of FP operations, there's not much to gain and it's
531 a real pain to get them reloaded. */
532 #define FPCC_REGNUM (BR_REG_FIRST + 0)
534 /* Pass structure value address as an "invisible" first argument. */
535 #define STRUCT_VALUE 0
537 /* It is as good or better to call a constant function address than to
538 call an address kept in a register. */
539 #define NO_FUNCTION_CSE 1
541 /* It is as good or better for a function to call itself with an
542 explicit address than to call an address kept in a register. */
543 #define NO_RECURSIVE_FUNCTION_CSE 1
545 /* Xtensa processors have "register windows". GCC does not currently
546 take advantage of the possibility for variable-sized windows; instead,
547 we use a fixed window size of 8. */
549 #define INCOMING_REGNO(OUT) \
550 ((GP_REG_P (OUT) && \
551 ((unsigned) ((OUT) - GP_REG_FIRST) >= WINDOW_SIZE)) ? \
552 (OUT) - WINDOW_SIZE : (OUT))
554 #define OUTGOING_REGNO(IN) \
556 ((unsigned) ((IN) - GP_REG_FIRST) < WINDOW_SIZE)) ? \
557 (IN) + WINDOW_SIZE : (IN))
560 /* Define the classes of registers for register constraints in the
561 machine description. */
564 NO_REGS, /* no registers in set */
565 BR_REGS, /* coprocessor boolean registers */
566 FP_REGS, /* floating point registers */
567 ACC_REG, /* MAC16 accumulator */
568 SP_REG, /* sp register (aka a1) */
569 GR_REGS, /* integer registers except sp */
570 AR_REGS, /* all integer registers */
571 ALL_REGS, /* all registers */
572 LIM_REG_CLASSES /* max value + 1 */
575 #define N_REG_CLASSES (int) LIM_REG_CLASSES
577 #define GENERAL_REGS AR_REGS
579 /* An initializer containing the names of the register classes as C
580 string constants. These names are used in writing some of the
582 #define REG_CLASS_NAMES \
594 /* Contents of the register classes. The Nth integer specifies the
595 contents of class N. The way the integer MASK is interpreted is
596 that register R is in the class if 'MASK & (1 << R)' is 1. */
597 #define REG_CLASS_CONTENTS \
599 { 0x00000000, 0x00000000 }, /* no registers */ \
600 { 0x00040000, 0x00000000 }, /* coprocessor boolean registers */ \
601 { 0xfff80000, 0x00000007 }, /* floating-point registers */ \
602 { 0x00000000, 0x00000008 }, /* MAC16 accumulator */ \
603 { 0x00000002, 0x00000000 }, /* stack pointer register */ \
604 { 0x0000fffd, 0x00000000 }, /* general-purpose registers */ \
605 { 0x0003ffff, 0x00000000 }, /* integer registers */ \
606 { 0xffffffff, 0x0000000f } /* all registers */ \
609 /* A C expression whose value is a register class containing hard
610 register REGNO. In general there is more that one such class;
611 choose a class which is "minimal", meaning that no smaller class
612 also contains the register. */
613 extern const enum reg_class xtensa_regno_to_class[FIRST_PSEUDO_REGISTER];
615 #define REGNO_REG_CLASS(REGNO) xtensa_regno_to_class[ (REGNO) ]
617 /* Use the Xtensa AR register file for base registers.
618 No index registers. */
619 #define BASE_REG_CLASS AR_REGS
620 #define INDEX_REG_CLASS NO_REGS
622 /* SMALL_REGISTER_CLASSES is required for Xtensa, because all of the
623 16 AR registers may be explicitly used in the RTL, as either
624 incoming or outgoing arguments. */
625 #define SMALL_REGISTER_CLASSES 1
628 /* REGISTER AND CONSTANT CLASSES */
630 /* Get reg_class from a letter such as appears in the machine
633 Available letters: a-f,h,j-l,q,t-z,A-D,W,Y-Z
635 DEFINED REGISTER CLASSES:
637 'a' general-purpose registers except sp
639 'D' general-purpose registers (only if density option enabled)
640 'd' general-purpose registers, including sp (only if density enabled)
641 'A' MAC16 accumulator (only if MAC16 option enabled)
642 'B' general-purpose registers (only if sext instruction enabled)
643 'C' general-purpose registers (only if mul16 option enabled)
644 'b' coprocessor boolean registers
645 'f' floating-point registers
648 extern enum reg_class xtensa_char_to_class[256];
650 #define REG_CLASS_FROM_LETTER(C) xtensa_char_to_class[ (int) (C) ]
652 /* The letters I, J, K, L, M, N, O, and P in a register constraint
653 string can be used to stand for particular ranges of immediate
654 operands. This macro defines what the ranges are. C is the
655 letter, and VALUE is a constant value. Return 1 if VALUE is
656 in the range specified by C.
660 I = 12-bit signed immediate for movi
661 J = 8-bit signed immediate for addi
662 K = 4-bit value in (b4const U {0})
663 L = 4-bit value in b4constu
664 M = 7-bit value in simm7
665 N = 8-bit unsigned immediate shifted left by 8 bits for addmi
666 O = 4-bit value in ai4const
667 P = valid immediate mask value for extui */
669 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
670 ((C) == 'I' ? (xtensa_simm12b (VALUE)) \
671 : (C) == 'J' ? (xtensa_simm8 (VALUE)) \
672 : (C) == 'K' ? (((VALUE) == 0) || xtensa_b4const (VALUE)) \
673 : (C) == 'L' ? (xtensa_b4constu (VALUE)) \
674 : (C) == 'M' ? (xtensa_simm7 (VALUE)) \
675 : (C) == 'N' ? (xtensa_simm8x256 (VALUE)) \
676 : (C) == 'O' ? (xtensa_ai4const (VALUE)) \
677 : (C) == 'P' ? (xtensa_mask_immediate (VALUE)) \
681 /* Similar, but for floating constants, and defining letters G and H.
682 Here VALUE is the CONST_DOUBLE rtx itself. */
683 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) (0)
686 /* Other letters can be defined in a machine-dependent fashion to
687 stand for particular classes of registers or other arbitrary
690 R = memory that can be accessed with a 4-bit unsigned offset
691 S = memory where the second word can be addressed with a 4-bit offset
692 T = memory in a constant pool (addressable with a pc-relative load)
693 U = memory *NOT* in a constant pool
695 The offset range should not be checked here (except to distinguish
696 denser versions of the instructions for which more general versions
697 are available). Doing so leads to problems in reloading: an
698 argptr-relative address may become invalid when the phony argptr is
699 eliminated in favor of the stack pointer (the offset becomes too
700 large to fit in the instruction's immediate field); a reload is
701 generated to fix this but the RTL is not immediately updated; in
702 the meantime, the constraints are checked and none match. The
703 solution seems to be to simply skip the offset check here. The
704 address will be checked anyway because of the code in
705 GO_IF_LEGITIMATE_ADDRESS. */
707 #define EXTRA_CONSTRAINT(OP, CODE) \
708 ((GET_CODE (OP) != MEM) ? \
709 ((CODE) >= 'R' && (CODE) <= 'U' \
710 && reload_in_progress && GET_CODE (OP) == REG \
711 && REGNO (OP) >= FIRST_PSEUDO_REGISTER) \
712 : ((CODE) == 'R') ? smalloffset_mem_p (OP) \
713 : ((CODE) == 'S') ? smalloffset_double_mem_p (OP) \
714 : ((CODE) == 'T') ? constantpool_mem_p (OP) \
715 : ((CODE) == 'U') ? !constantpool_mem_p (OP) \
718 /* Given an rtx X being reloaded into a reg required to be
719 in class CLASS, return the class of reg to actually use. */
720 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
722 ? (GET_CODE (X) == CONST_DOUBLE) ? NO_REGS : (CLASS) \
725 #define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \
728 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
729 xtensa_secondary_reload_class (CLASS, MODE, X, 0)
731 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
732 xtensa_secondary_reload_class (CLASS, MODE, X, 1)
734 /* Return the maximum number of consecutive registers
735 needed to represent mode MODE in a register of class CLASS. */
736 #define CLASS_UNITS(mode, size) \
737 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
739 #define CLASS_MAX_NREGS(CLASS, MODE) \
740 (CLASS_UNITS (MODE, UNITS_PER_WORD))
743 /* Stack layout; function entry, exit and calling. */
745 #define STACK_GROWS_DOWNWARD
747 /* Offset within stack frame to start allocating local variables at. */
748 #define STARTING_FRAME_OFFSET \
749 current_function_outgoing_args_size
751 /* The ARG_POINTER and FRAME_POINTER are not real Xtensa registers, so
752 they are eliminated to either the stack pointer or hard frame pointer. */
753 #define ELIMINABLE_REGS \
754 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
755 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
756 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
757 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
759 #define CAN_ELIMINATE(FROM, TO) 1
761 /* Specify the initial difference between the specified pair of registers. */
762 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
764 compute_frame_size (get_frame_size ()); \
765 if ((FROM) == FRAME_POINTER_REGNUM) \
767 else if ((FROM) == ARG_POINTER_REGNUM) \
768 (OFFSET) = xtensa_current_frame_size; \
773 /* If defined, the maximum amount of space required for outgoing
774 arguments will be computed and placed into the variable
775 'current_function_outgoing_args_size'. No space will be pushed
776 onto the stack for each call; instead, the function prologue
777 should increase the stack frame size by this amount. */
778 #define ACCUMULATE_OUTGOING_ARGS 1
780 /* Offset from the argument pointer register to the first argument's
781 address. On some machines it may depend on the data type of the
782 function. If 'ARGS_GROW_DOWNWARD', this is the offset to the
783 location above the first argument's address. */
784 #define FIRST_PARM_OFFSET(FNDECL) 0
786 /* Align stack frames on 128 bits for Xtensa. This is necessary for
787 128-bit datatypes defined in TIE (e.g., for Vectra). */
788 #define STACK_BOUNDARY 128
790 /* Functions do not pop arguments off the stack. */
791 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
793 /* Use a fixed register window size of 8. */
794 #define WINDOW_SIZE 8
796 /* Symbolic macros for the registers used to return integer, floating
797 point, and values of coprocessor and user-defined modes. */
798 #define GP_RETURN (GP_REG_FIRST + 2 + WINDOW_SIZE)
799 #define GP_OUTGOING_RETURN (GP_REG_FIRST + 2)
801 /* Symbolic macros for the first/last argument registers. */
802 #define GP_ARG_FIRST (GP_REG_FIRST + 2)
803 #define GP_ARG_LAST (GP_REG_FIRST + 7)
804 #define GP_OUTGOING_ARG_FIRST (GP_REG_FIRST + 2 + WINDOW_SIZE)
805 #define GP_OUTGOING_ARG_LAST (GP_REG_FIRST + 7 + WINDOW_SIZE)
807 #define MAX_ARGS_IN_REGISTERS 6
809 /* Don't worry about compatibility with PCC. */
810 #define DEFAULT_PCC_STRUCT_RETURN 0
812 /* For Xtensa, we would like to be able to return up to 6 words in
813 memory but GCC cannot support that. The return value must be given
814 one of the standard MODE_INT modes, and there is no 6 word mode.
815 Instead, if we try to return a 6 word structure, GCC selects the
816 next biggest mode (OImode, 8 words) and then the register allocator
817 fails because there is no 8-register group beginning with a10. So
818 we have to fall back on the next largest size which is 4 words... */
819 #define RETURN_IN_MEMORY(TYPE) \
820 ((unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) > 4 * UNITS_PER_WORD)
822 /* Define how to find the value returned by a library function
823 assuming the value has mode MODE. Because we have defined
824 PROMOTE_FUNCTION_RETURN, we have to perform the same promotions as
826 #define XTENSA_LIBCALL_VALUE(MODE, OUTGOINGP) \
827 gen_rtx_REG ((GET_MODE_CLASS (MODE) == MODE_INT \
828 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
830 OUTGOINGP ? GP_OUTGOING_RETURN : GP_RETURN)
832 #define LIBCALL_VALUE(MODE) \
833 XTENSA_LIBCALL_VALUE ((MODE), 0)
835 #define LIBCALL_OUTGOING_VALUE(MODE) \
836 XTENSA_LIBCALL_VALUE ((MODE), 1)
838 /* Define how to find the value returned by a function.
839 VALTYPE is the data type of the value (as a tree).
840 If the precise function being called is known, FUNC is its FUNCTION_DECL;
841 otherwise, FUNC is 0. */
842 #define XTENSA_FUNCTION_VALUE(VALTYPE, FUNC, OUTGOINGP) \
843 gen_rtx_REG ((INTEGRAL_TYPE_P (VALTYPE) \
844 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
845 ? SImode: TYPE_MODE (VALTYPE), \
846 OUTGOINGP ? GP_OUTGOING_RETURN : GP_RETURN)
848 #define FUNCTION_VALUE(VALTYPE, FUNC) \
849 XTENSA_FUNCTION_VALUE (VALTYPE, FUNC, 0)
851 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
852 XTENSA_FUNCTION_VALUE (VALTYPE, FUNC, 1)
854 /* A C expression that is nonzero if REGNO is the number of a hard
855 register in which the values of called function may come back. A
856 register whose use for returning values is limited to serving as
857 the second of a pair (for a value of type 'double', say) need not
858 be recognized by this macro. If the machine has register windows,
859 so that the caller and the called function use different registers
860 for the return value, this macro should recognize only the caller's
862 #define FUNCTION_VALUE_REGNO_P(N) \
865 /* A C expression that is nonzero if REGNO is the number of a hard
866 register in which function arguments are sometimes passed. This
867 does *not* include implicit arguments such as the static chain and
868 the structure-value address. On many machines, no registers can be
869 used for this purpose since all function arguments are pushed on
871 #define FUNCTION_ARG_REGNO_P(N) \
872 ((N) >= GP_OUTGOING_ARG_FIRST && (N) <= GP_OUTGOING_ARG_LAST)
874 /* Use IEEE floating-point format. */
875 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
877 /* Define a data type for recording info about an argument list
878 during the scan of that argument list. This data type should
879 hold all necessary information about the function itself
880 and about the args processed so far, enough to enable macros
881 such as FUNCTION_ARG to determine where the next arg should go. */
882 typedef struct xtensa_args {
883 int arg_words; /* # total words the arguments take */
886 /* Initialize a variable CUM of type CUMULATIVE_ARGS
887 for a call to a function whose data type is FNTYPE.
888 For a library call, FNTYPE is 0. */
889 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
890 init_cumulative_args (&CUM, FNTYPE, LIBNAME)
892 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
893 init_cumulative_args (&CUM, FNTYPE, LIBNAME)
895 /* Update the data in CUM to advance over an argument
896 of mode MODE and data type TYPE.
897 (TYPE is null for libcalls where that information may not be available.) */
898 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
899 function_arg_advance (&CUM, MODE, TYPE)
901 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
902 function_arg (&CUM, MODE, TYPE, FALSE)
904 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
905 function_arg (&CUM, MODE, TYPE, TRUE)
907 /* Arguments are never passed partly in memory and partly in registers. */
908 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) (0)
910 /* Specify function argument alignment. */
911 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
913 ? (TYPE_ALIGN (TYPE) <= PARM_BOUNDARY \
915 : TYPE_ALIGN (TYPE)) \
916 : (GET_MODE_ALIGNMENT (MODE) <= PARM_BOUNDARY \
918 : GET_MODE_ALIGNMENT (MODE)))
921 /* Nonzero if we do not know how to pass TYPE solely in registers.
922 We cannot do so in the following cases:
924 - if the type has variable size
925 - if the type is marked as addressable (it is required to be constructed
928 This differs from the default in that it does not check if the padding
929 and mode of the type are such that a copy into a register would put it
930 into the wrong part of the register. */
932 #define MUST_PASS_IN_STACK(MODE, TYPE) \
934 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
935 || TREE_ADDRESSABLE (TYPE)))
937 /* Output assembler code to FILE to increment profiler label LABELNO
938 for profiling a function entry.
940 The mcount code in glibc doesn't seem to use this LABELNO stuff.
941 Some ports (e.g., MIPS) don't even bother to pass the label
942 address, and even those that do (e.g., i386) don't seem to use it.
943 The information needed by mcount() is the current PC and the
944 current return address, so that mcount can identify an arc in the
945 call graph. For Xtensa, we pass the current return address as
946 the first argument to mcount, and the current PC is available as
947 a0 in mcount's register window. Both of these values contain
948 window size information in the two most significant bits; we assume
949 that the mcount code will mask off those bits. The call to mcount
950 uses a window size of 8 to make sure that mcount doesn't clobber
951 any incoming argument values. */
953 #define FUNCTION_PROFILER(FILE, LABELNO) \
955 fprintf (FILE, "\taddi\t%s, %s, 0\t# save current return address\n", \
956 reg_names[GP_REG_FIRST+10], \
957 reg_names[GP_REG_FIRST+0]); \
958 fprintf (FILE, "\tcall8\t_mcount\n"); \
961 /* Stack pointer value doesn't matter at exit. */
962 #define EXIT_IGNORE_STACK 1
964 /* A C statement to output, on the stream FILE, assembler code for a
965 block of data that contains the constant parts of a trampoline.
966 This code should not include a label--the label is taken care of
969 For Xtensa, the trampoline must perform an entry instruction with a
970 minimal stack frame in order to get some free registers. Once the
971 actual call target is known, the proper stack frame size is extracted
972 from the entry instruction at the target and the current frame is
973 adjusted to match. The trampoline then transfers control to the
974 instruction following the entry at the target. Note: this assumes
975 that the target begins with an entry instruction. */
977 /* minimum frame = reg save area (4 words) plus static chain (1 word)
978 and the total number of words must be a multiple of 128 bits */
979 #define MIN_FRAME_SIZE (8 * UNITS_PER_WORD)
981 #define TRAMPOLINE_TEMPLATE(STREAM) \
983 fprintf (STREAM, "\t.begin no-generics\n"); \
984 fprintf (STREAM, "\tentry\tsp, %d\n", MIN_FRAME_SIZE); \
986 /* GCC isn't prepared to deal with data at the beginning of the \
987 trampoline, and the Xtensa l32r instruction requires that the \
988 constant pool be located before the code. We put the constant \
989 pool in the middle of the trampoline and jump around it. */ \
991 fprintf (STREAM, "\tj\t.Lskipconsts\n"); \
992 fprintf (STREAM, "\t.align\t4\n"); \
993 fprintf (STREAM, ".Lfnaddr:%s0\n", integer_asm_op (4, TRUE)); \
994 fprintf (STREAM, ".Lchainval:%s0\n", integer_asm_op (4, TRUE)); \
995 fprintf (STREAM, ".Lskipconsts:\n"); \
997 /* store the static chain */ \
998 fprintf (STREAM, "\tl32r\ta8, .Lchainval\n"); \
999 fprintf (STREAM, "\ts32i\ta8, sp, %d\n", \
1000 MIN_FRAME_SIZE - (5 * UNITS_PER_WORD)); \
1002 /* set the proper stack pointer value */ \
1003 fprintf (STREAM, "\tl32r\ta8, .Lfnaddr\n"); \
1004 fprintf (STREAM, "\tl32i\ta9, a8, 0\n"); \
1005 fprintf (STREAM, "\textui\ta9, a9, %d, 12\n", \
1006 TARGET_BIG_ENDIAN ? 8 : 12); \
1007 fprintf (STREAM, "\tslli\ta9, a9, 3\n"); \
1008 fprintf (STREAM, "\taddi\ta9, a9, %d\n", -MIN_FRAME_SIZE); \
1009 fprintf (STREAM, "\tsub\ta9, sp, a9\n"); \
1010 fprintf (STREAM, "\tmovsp\tsp, a9\n"); \
1012 /* jump to the instruction following the entry */ \
1013 fprintf (STREAM, "\taddi\ta8, a8, 3\n"); \
1014 fprintf (STREAM, "\tjx\ta8\n"); \
1015 fprintf (STREAM, "\t.end no-generics\n"); \
1018 /* Size in bytes of the trampoline, as an integer. */
1019 #define TRAMPOLINE_SIZE 49
1021 /* Alignment required for trampolines, in bits. */
1022 #define TRAMPOLINE_ALIGNMENT (32)
1024 /* A C statement to initialize the variable parts of a trampoline. */
1025 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
1028 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 8)), FUNC); \
1029 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 12)), CHAIN); \
1030 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__xtensa_sync_caches"), \
1031 0, VOIDmode, 1, addr, Pmode); \
1034 /* Define the `__builtin_va_list' type for the ABI. */
1035 #define BUILD_VA_LIST_TYPE(VALIST) \
1036 (VALIST) = xtensa_build_va_list ()
1038 /* If defined, is a C expression that produces the machine-specific
1039 code for a call to '__builtin_saveregs'. This code will be moved
1040 to the very beginning of the function, before any parameter access
1041 are made. The return value of this function should be an RTX that
1042 contains the value to use as the return of '__builtin_saveregs'. */
1043 #define EXPAND_BUILTIN_SAVEREGS \
1044 xtensa_builtin_saveregs
1046 /* Implement `va_start' for varargs and stdarg. */
1047 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
1048 xtensa_va_start (stdarg, valist, nextarg)
1050 /* Implement `va_arg'. */
1051 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1052 xtensa_va_arg (valist, type)
1054 /* If defined, a C expression that produces the machine-specific code
1055 to setup the stack so that arbitrary frames can be accessed.
1057 On Xtensa, a stack back-trace must always begin from the stack pointer,
1058 so that the register overflow save area can be located. However, the
1059 stack-walking code in GCC always begins from the hard_frame_pointer
1060 register, not the stack pointer. The frame pointer is usually equal
1061 to the stack pointer, but the __builtin_return_address and
1062 __builtin_frame_address functions will not work if count > 0 and
1063 they are called from a routine that uses alloca. These functions
1064 are not guaranteed to work at all if count > 0 so maybe that is OK.
1066 A nicer solution would be to allow the architecture-specific files to
1067 specify whether to start from the stack pointer or frame pointer. That
1068 would also allow us to skip the machine->accesses_prev_frame stuff that
1069 we currently need to ensure that there is a frame pointer when these
1070 builtin functions are used. */
1072 #define SETUP_FRAME_ADDRESSES() \
1073 xtensa_setup_frame_addresses ()
1075 /* A C expression whose value is RTL representing the address in a
1076 stack frame where the pointer to the caller's frame is stored.
1077 Assume that FRAMEADDR is an RTL expression for the address of the
1080 For Xtensa, there is no easy way to get the frame pointer if it is
1081 not equivalent to the stack pointer. Moreover, the result of this
1082 macro is used for continuing to walk back up the stack, so it must
1083 return the stack pointer address. Thus, there is some inconsistency
1084 here in that __builtin_frame_address will return the frame pointer
1085 when count == 0 and the stack pointer when count > 0. */
1087 #define DYNAMIC_CHAIN_ADDRESS(frame) \
1088 gen_rtx (PLUS, Pmode, frame, \
1089 gen_rtx_CONST_INT (VOIDmode, -3 * UNITS_PER_WORD))
1091 /* Define this if the return address of a particular stack frame is
1092 accessed from the frame pointer of the previous stack frame. */
1093 #define RETURN_ADDR_IN_PREVIOUS_FRAME
1095 /* A C expression whose value is RTL representing the value of the
1096 return address for the frame COUNT steps up from the current
1097 frame, after the prologue. FRAMEADDR is the frame pointer of the
1098 COUNT frame, or the frame pointer of the COUNT - 1 frame if
1099 'RETURN_ADDR_IN_PREVIOUS_FRAME' is defined.
1101 The 2 most-significant bits of the return address on Xtensa hold
1102 the register window size. To get the real return address, these bits
1103 must be masked off and replaced with the high bits from the current
1104 PC. Since it is unclear how the __builtin_return_address function
1105 is used, the current code does not do this masking and simply returns
1106 the raw return address from the a0 register. */
1107 #define RETURN_ADDR_RTX(count, frame) \
1109 ? gen_rtx_REG (Pmode, 0) \
1110 : gen_rtx_MEM (Pmode, memory_address \
1111 (Pmode, plus_constant (frame, -4 * UNITS_PER_WORD))))
1114 /* Addressing modes, and classification of registers for them. */
1116 /* C expressions which are nonzero if register number NUM is suitable
1117 for use as a base or index register in operand addresses. It may
1118 be either a suitable hard register or a pseudo register that has
1119 been allocated such a hard register. The difference between an
1120 index register and a base register is that the index register may
1123 #define REGNO_OK_FOR_BASE_P(NUM) \
1124 (GP_REG_P (NUM) || GP_REG_P ((unsigned) reg_renumber[NUM]))
1126 #define REGNO_OK_FOR_INDEX_P(NUM) 0
1128 /* C expressions that are nonzero if X (assumed to be a `reg' RTX) is
1129 valid for use as a base or index register. For hard registers, it
1130 should always accept those which the hardware permits and reject
1131 the others. Whether the macro accepts or rejects pseudo registers
1132 must be controlled by `REG_OK_STRICT'. This usually requires two
1133 variant definitions, of which `REG_OK_STRICT' controls the one
1134 actually used. The difference between an index register and a base
1135 register is that the index register may be scaled. */
1137 #ifdef REG_OK_STRICT
1139 #define REG_OK_FOR_INDEX_P(X) 0
1140 #define REG_OK_FOR_BASE_P(X) \
1141 REGNO_OK_FOR_BASE_P (REGNO (X))
1143 #else /* !REG_OK_STRICT */
1145 #define REG_OK_FOR_INDEX_P(X) 0
1146 #define REG_OK_FOR_BASE_P(X) \
1147 ((REGNO (X) >= FIRST_PSEUDO_REGISTER) || (GP_REG_P (REGNO (X))))
1149 #endif /* !REG_OK_STRICT */
1151 /* Maximum number of registers that can appear in a valid memory address. */
1152 #define MAX_REGS_PER_ADDRESS 1
1154 /* Identify valid Xtensa addresses. */
1155 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1159 /* allow constant pool addresses */ \
1160 if ((MODE) != BLKmode && GET_MODE_SIZE (MODE) >= UNITS_PER_WORD \
1161 && constantpool_address_p (xinsn)) \
1164 while (GET_CODE (xinsn) == SUBREG) \
1165 xinsn = SUBREG_REG (xinsn); \
1167 /* allow base registers */ \
1168 if (GET_CODE (xinsn) == REG && REG_OK_FOR_BASE_P (xinsn)) \
1171 /* check for "register + offset" addressing */ \
1172 if (GET_CODE (xinsn) == PLUS) \
1174 rtx xplus0 = XEXP (xinsn, 0); \
1175 rtx xplus1 = XEXP (xinsn, 1); \
1176 enum rtx_code code0; \
1177 enum rtx_code code1; \
1179 while (GET_CODE (xplus0) == SUBREG) \
1180 xplus0 = SUBREG_REG (xplus0); \
1181 code0 = GET_CODE (xplus0); \
1183 while (GET_CODE (xplus1) == SUBREG) \
1184 xplus1 = SUBREG_REG (xplus1); \
1185 code1 = GET_CODE (xplus1); \
1187 /* swap operands if necessary so the register is first */ \
1188 if (code0 != REG && code1 == REG) \
1190 xplus0 = XEXP (xinsn, 1); \
1191 xplus1 = XEXP (xinsn, 0); \
1192 code0 = GET_CODE (xplus0); \
1193 code1 = GET_CODE (xplus1); \
1196 if (code0 == REG && REG_OK_FOR_BASE_P (xplus0) \
1197 && code1 == CONST_INT \
1198 && xtensa_mem_offset (INTVAL (xplus1), (MODE))) \
1205 /* A C expression that is 1 if the RTX X is a constant which is a
1206 valid address. This is defined to be the same as 'CONSTANT_P (X)',
1207 but rejecting CONST_DOUBLE. */
1208 #define CONSTANT_ADDRESS_P(X) \
1209 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1210 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
1211 || (GET_CODE (X) == CONST)))
1213 /* Nonzero if the constant value X is a legitimate general operand.
1214 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1215 #define LEGITIMATE_CONSTANT_P(X) 1
1217 /* A C expression that is nonzero if X is a legitimate immediate
1218 operand on the target machine when generating position independent
1220 #define LEGITIMATE_PIC_OPERAND_P(X) \
1221 ((GET_CODE (X) != SYMBOL_REF || SYMBOL_REF_FLAG (X)) \
1222 && GET_CODE (X) != LABEL_REF \
1223 && GET_CODE (X) != CONST)
1225 /* Tell GCC how to use ADDMI to generate addresses. */
1226 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1229 if (GET_CODE (xinsn) == PLUS) \
1231 rtx plus0 = XEXP (xinsn, 0); \
1232 rtx plus1 = XEXP (xinsn, 1); \
1234 if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG) \
1236 plus0 = XEXP (xinsn, 1); \
1237 plus1 = XEXP (xinsn, 0); \
1240 if (GET_CODE (plus0) == REG \
1241 && GET_CODE (plus1) == CONST_INT \
1242 && !xtensa_mem_offset (INTVAL (plus1), MODE) \
1243 && !xtensa_simm8 (INTVAL (plus1)) \
1244 && xtensa_mem_offset (INTVAL (plus1) & 0xff, MODE) \
1245 && xtensa_simm8x256 (INTVAL (plus1) & ~0xff)) \
1247 rtx temp = gen_reg_rtx (Pmode); \
1248 emit_insn (gen_rtx (SET, Pmode, temp, \
1249 gen_rtx (PLUS, Pmode, plus0, \
1250 GEN_INT (INTVAL (plus1) & ~0xff)))); \
1251 (X) = gen_rtx (PLUS, Pmode, temp, \
1252 GEN_INT (INTVAL (plus1) & 0xff)); \
1259 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) {}
1261 /* If we are referencing a function that is static, make the SYMBOL_REF
1262 special so that we can generate direct calls to it even with -fpic. */
1263 #define ENCODE_SECTION_INFO(DECL, FIRST) \
1265 if (TREE_CODE (DECL) == FUNCTION_DECL && ! TREE_PUBLIC (DECL)) \
1266 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
1269 /* Specify the machine mode that this machine uses
1270 for the index in the tablejump instruction. */
1271 #define CASE_VECTOR_MODE (SImode)
1273 /* Define this if the tablejump instruction expects the table
1274 to contain offsets from the address of the table.
1275 Do not define this if the table should contain absolute addresses. */
1276 /* #define CASE_VECTOR_PC_RELATIVE */
1278 /* Specify the tree operation to be used to convert reals to integers. */
1279 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1281 /* This is the kind of divide that is easiest to do in the general case. */
1282 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1284 /* Define this as 1 if 'char' should by default be signed; else as 0. */
1285 #define DEFAULT_SIGNED_CHAR 0
1287 /* Max number of bytes we can move from memory to memory
1288 in one reasonably fast instruction. */
1290 #define MAX_MOVE_MAX 4
1292 /* Prefer word-sized loads. */
1293 #define SLOW_BYTE_ACCESS 1
1295 /* Xtensa doesn't have any instructions that set integer values based on the
1296 results of comparisons, but the simplification code in the combiner also
1297 uses this macro. The value should be either 1 or -1 to enable some
1298 optimizations in the combiner; I'm not sure which is better for us.
1299 Since we've been using 1 for a while, it should probably stay that way for
1301 #define STORE_FLAG_VALUE 1
1303 /* Shift instructions ignore all but the low-order few bits. */
1304 #define SHIFT_COUNT_TRUNCATED 1
1306 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1307 is done just by pretending it is already truncated. */
1308 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1310 /* Specify the machine mode that pointers have.
1311 After generation of rtl, the compiler makes no further distinction
1312 between pointers and any other objects of this machine mode. */
1313 #define Pmode SImode
1315 /* A function address in a call instruction is a word address (for
1316 indexing purposes) so give the MEM rtx a words's mode. */
1317 #define FUNCTION_MODE SImode
1319 /* A C expression that evaluates to true if it is ok to perform a
1320 sibling call to DECL. */
1321 /* TODO: fix this up to allow at least some sibcalls */
1322 #define FUNCTION_OK_FOR_SIBCALL(DECL) 0
1324 /* Xtensa constant costs. */
1325 #define CONST_COSTS(X, CODE, OUTER_CODE) \
1327 switch (OUTER_CODE) \
1330 if (xtensa_simm12b (INTVAL (X))) return 4; \
1333 if (xtensa_simm8 (INTVAL (X))) return 0; \
1334 if (xtensa_simm8x256 (INTVAL (X))) return 0; \
1337 if (xtensa_mask_immediate (INTVAL (X))) return 0; \
1340 if ((INTVAL (X) == 0) || xtensa_b4const (INTVAL (X))) return 0; \
1347 /* no way to tell if X is the 2nd operand so be conservative */ \
1350 if (xtensa_simm12b (INTVAL (X))) return 5; \
1356 case CONST_DOUBLE: \
1359 /* Costs of various Xtensa operations. */
1360 #define RTX_COSTS(X, CODE, OUTER_CODE) \
1364 (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
1365 if (memory_address_p (GET_MODE (X), XEXP ((X), 0))) \
1366 return COSTS_N_INSNS (num_words); \
1368 return COSTS_N_INSNS (2*num_words); \
1372 return COSTS_N_INSNS (TARGET_NSA ? 5 : 50); \
1375 return COSTS_N_INSNS ((GET_MODE (X) == DImode) ? 3 : 2); \
1380 if (GET_MODE (X) == DImode) return COSTS_N_INSNS (2); \
1381 return COSTS_N_INSNS (1); \
1386 if (GET_MODE (X) == DImode) return COSTS_N_INSNS (50); \
1387 return COSTS_N_INSNS (1); \
1391 enum machine_mode xmode = GET_MODE (X); \
1392 if (xmode == SFmode) \
1393 return COSTS_N_INSNS (TARGET_HARD_FLOAT ? 1 : 50); \
1394 if (xmode == DFmode) \
1395 return COSTS_N_INSNS (50); \
1396 return COSTS_N_INSNS (4); \
1402 enum machine_mode xmode = GET_MODE (X); \
1403 if (xmode == SFmode) \
1404 return COSTS_N_INSNS (TARGET_HARD_FLOAT ? 1 : 50); \
1405 if (xmode == DFmode || xmode == DImode) \
1406 return COSTS_N_INSNS (50); \
1407 return COSTS_N_INSNS (1); \
1411 return COSTS_N_INSNS ((GET_MODE (X) == DImode) ? 4 : 2); \
1415 enum machine_mode xmode = GET_MODE (X); \
1416 if (xmode == SFmode) \
1417 return COSTS_N_INSNS (TARGET_HARD_FLOAT ? 4 : 50); \
1418 if (xmode == DFmode || xmode == DImode) \
1419 return COSTS_N_INSNS (50); \
1421 return COSTS_N_INSNS (4); \
1423 return COSTS_N_INSNS (16); \
1425 return COSTS_N_INSNS (12); \
1426 return COSTS_N_INSNS (50); \
1432 enum machine_mode xmode = GET_MODE (X); \
1433 if (xmode == SFmode) \
1434 return COSTS_N_INSNS (TARGET_HARD_FLOAT_DIV ? 8 : 50); \
1435 if (xmode == DFmode) \
1436 return COSTS_N_INSNS (50); \
1438 /* fall through */ \
1443 enum machine_mode xmode = GET_MODE (X); \
1444 if (xmode == DImode) \
1445 return COSTS_N_INSNS (50); \
1447 return COSTS_N_INSNS (32); \
1448 return COSTS_N_INSNS (50); \
1452 if (GET_MODE (X) == SFmode) \
1453 return COSTS_N_INSNS (TARGET_HARD_FLOAT_SQRT ? 8 : 50); \
1454 return COSTS_N_INSNS (50); \
1460 return COSTS_N_INSNS (TARGET_MINMAX ? 1 : 50); \
1462 case SIGN_EXTRACT: \
1464 return COSTS_N_INSNS (TARGET_SEXT ? 1 : 2); \
1466 case ZERO_EXTRACT: \
1468 return COSTS_N_INSNS (1);
1471 /* An expression giving the cost of an addressing mode that
1472 contains ADDRESS. */
1473 #define ADDRESS_COST(ADDR) 1
1475 /* A C expression for the cost of moving data from a register in
1476 class FROM to one in class TO. The classes are expressed using
1477 the enumeration values such as 'GENERAL_REGS'. A value of 2 is
1478 the default; other values are interpreted relative to that. */
1479 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1480 (((FROM) == (TO) && (FROM) != BR_REGS && (TO) != BR_REGS) \
1482 : (reg_class_subset_p ((FROM), AR_REGS) \
1483 && reg_class_subset_p ((TO), AR_REGS) \
1485 : (reg_class_subset_p ((FROM), AR_REGS) \
1486 && (TO) == ACC_REG \
1488 : ((FROM) == ACC_REG \
1489 && reg_class_subset_p ((TO), AR_REGS) \
1493 #define MEMORY_MOVE_COST(MODE, CLASS, IN) 4
1495 #define BRANCH_COST 3
1497 /* Optionally define this if you have added predicates to
1498 'MACHINE.c'. This macro is called within an initializer of an
1499 array of structures. The first field in the structure is the
1500 name of a predicate and the second field is an array of rtl
1501 codes. For each predicate, list all rtl codes that can be in
1502 expressions matched by the predicate. The list should have a
1505 #define PREDICATE_CODES \
1506 {"add_operand", { REG, CONST_INT, SUBREG }}, \
1507 {"arith_operand", { REG, CONST_INT, SUBREG }}, \
1508 {"nonimmed_operand", { REG, SUBREG, MEM }}, \
1509 {"non_acc_reg_operand", { REG, SUBREG }}, \
1510 {"mem_operand", { MEM }}, \
1511 {"mask_operand", { REG, CONST_INT, SUBREG }}, \
1512 {"extui_fldsz_operand", { CONST_INT }}, \
1513 {"sext_fldsz_operand", { CONST_INT }}, \
1514 {"lsbitnum_operand", { CONST_INT }}, \
1515 {"fpmem_offset_operand", { CONST_INT }}, \
1516 {"sext_operand", { REG, SUBREG, MEM }}, \
1517 {"branch_operand", { REG, CONST_INT, SUBREG }}, \
1518 {"ubranch_operand", { REG, CONST_INT, SUBREG }}, \
1519 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG }}, \
1520 {"move_operand", { REG, SUBREG, MEM, CONST_INT, CONST_DOUBLE, \
1521 CONST, SYMBOL_REF, LABEL_REF }}, \
1522 {"non_const_move_operand", { REG, SUBREG, MEM }}, \
1523 {"const_float_1_operand", { CONST_DOUBLE }}, \
1524 {"branch_operator", { EQ, NE, LT, GE }}, \
1525 {"ubranch_operator", { LTU, GEU }}, \
1526 {"boolean_operator", { EQ, NE }},
1528 /* Control the assembler format that we output. */
1530 /* How to refer to registers in assembler output.
1531 This sequence is indexed by compiler's hard-register-number (see above). */
1532 #define REGISTER_NAMES \
1534 "a0", "sp", "a2", "a3", "a4", "a5", "a6", "a7", \
1535 "a8", "a9", "a10", "a11", "a12", "a13", "a14", "a15", \
1536 "fp", "argp", "b0", \
1537 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
1538 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
1542 /* If defined, a C initializer for an array of structures containing a
1543 name and a register number. This macro defines additional names
1544 for hard registers, thus allowing the 'asm' option in declarations
1545 to refer to registers using alternate names. */
1546 #define ADDITIONAL_REGISTER_NAMES \
1548 { "a1", 1 + GP_REG_FIRST } \
1551 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1552 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
1554 /* Recognize machine-specific patterns that may appear within
1555 constants. Used for PIC-specific UNSPECs. */
1556 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
1558 if (flag_pic && GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \
1560 switch (XINT ((X), 1)) \
1563 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
1564 fputs ("@PLT", (STREAM)); \
1576 /* This is how to output the definition of a user-level label named NAME,
1577 such as the label on a static function or variable NAME. */
1578 #define ASM_OUTPUT_LABEL(STREAM, NAME) \
1580 assemble_name (STREAM, NAME); \
1581 fputs (":\n", STREAM); \
1584 /* This is how to output a command to make the user-level label named NAME
1585 defined for reference from other files. */
1586 #define ASM_GLOBALIZE_LABEL(STREAM, NAME) \
1588 fputs ("\t.global\t", STREAM); \
1589 assemble_name (STREAM, NAME); \
1590 fputs ("\n", STREAM); \
1593 /* This says how to define a global common symbol. */
1594 #define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \
1595 xtensa_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", (SIZE))
1597 /* This says how to define a local common symbol (ie, not visible to
1599 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
1600 xtensa_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE))
1602 /* This is how to output an element of a case-vector that is absolute. */
1603 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
1604 fprintf (STREAM, "%s%sL%u\n", integer_asm_op (4, TRUE), \
1605 LOCAL_LABEL_PREFIX, VALUE)
1607 /* This is how to output an element of a case-vector that is relative.
1608 This is used for pc-relative code. */
1609 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
1611 fprintf (STREAM, "%s%sL%u-%sL%u\n", integer_asm_op (4, TRUE), \
1612 LOCAL_LABEL_PREFIX, (VALUE), \
1613 LOCAL_LABEL_PREFIX, (REL)); \
1616 /* This is how to output an assembler line that says to advance the
1617 location counter to a multiple of 2**LOG bytes. */
1618 #define ASM_OUTPUT_ALIGN(STREAM, LOG) \
1621 fprintf (STREAM, "\t.align\t%d\n", 1 << (LOG)); \
1624 /* Indicate that jump tables go in the text section. This is
1625 necessary when compiling PIC code. */
1626 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
1629 /* Define this macro for the rare case where the RTL needs some sort of
1630 machine-dependent fixup immediately before register allocation is done.
1632 If the stack frame size is too big to fit in the immediate field of
1633 the ENTRY instruction, we need to store the frame size in the
1634 constant pool. However, the code in xtensa_function_prologue runs too
1635 late to be able to add anything to the constant pool. Since the
1636 final frame size isn't known until reload is complete, this seems
1637 like the best place to do it.
1639 There may also be some fixup required if there is an incoming argument
1640 in a7 and the function requires a frame pointer. */
1642 #define MACHINE_DEPENDENT_REORG(INSN) xtensa_reorg (INSN)
1645 /* Define the strings to put out for each section in the object file. */
1646 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
1647 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
1650 /* Define output to appear before the constant pool. If the function
1651 has been assigned to a specific ELF section, or if it goes into a
1652 unique section, set the name of that section to be the literal
1654 #define ASM_OUTPUT_POOL_PROLOGUE(FILE, FUNNAME, FUNDECL, SIZE) \
1657 resolve_unique_section ((FUNDECL), 0); \
1658 fnsection = DECL_SECTION_NAME (FUNDECL); \
1659 if (fnsection != NULL_TREE) \
1661 const char *fnsectname = TREE_STRING_POINTER (fnsection); \
1662 fprintf (FILE, "\t.begin\tliteral_prefix %s\n", \
1663 strcmp (fnsectname, ".text") ? fnsectname : ""); \
1668 /* Define code to write out the ".end literal_prefix" directive for a
1669 function in a special section. This is appended to the standard ELF
1670 code for ASM_DECLARE_FUNCTION_SIZE. */
1671 #define XTENSA_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL) \
1672 if (DECL_SECTION_NAME (DECL) != NULL_TREE) \
1673 fprintf (FILE, "\t.end\tliteral_prefix\n")
1675 /* A C statement (with or without semicolon) to output a constant in
1676 the constant pool, if it needs special treatment. */
1677 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, JUMPTO) \
1679 xtensa_output_literal (FILE, X, MODE, LABELNO); \
1683 /* Store in OUTPUT a string (made with alloca) containing
1684 an assembler-name for a local static variable named NAME.
1685 LABELNO is an integer which is different for each call. */
1686 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1688 (OUTPUT) = (char *) alloca (strlen (NAME) + 10); \
1689 sprintf ((OUTPUT), "%s.%u", (NAME), (LABELNO)); \
1692 /* How to start an assembler comment. */
1693 #define ASM_COMMENT_START "#"
1695 /* Exception handling TODO!! */
1696 #define DWARF_UNWIND_INFO 0
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