1 /* Definitions of Tensilica's Xtensa target machine for GNU compiler.
2 Copyright (C) 2001 Free Software Foundation, Inc.
3 Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* Get Xtensa configuration settings */
23 #include "xtensa/xtensa-config.h"
25 /* Standard GCC variables that we reference. */
26 extern int current_function_calls_alloca;
27 extern int target_flags;
30 /* External variables defined in xtensa.c. */
34 CMP_SI, /* four byte integers */
35 CMP_DI, /* eight byte integers */
36 CMP_SF, /* single precision floats */
37 CMP_DF, /* double precision floats */
38 CMP_MAX /* max comparison type */
41 extern struct rtx_def * branch_cmp[2]; /* operands for compare */
42 extern enum cmp_type branch_type; /* what type of branch to use */
43 extern unsigned xtensa_current_frame_size;
45 /* Run-time compilation parameters selecting different hardware subsets. */
47 #define MASK_BIG_ENDIAN 0x00000001 /* big or little endian */
48 #define MASK_DENSITY 0x00000002 /* code density option */
49 #define MASK_MAC16 0x00000004 /* MAC16 option */
50 #define MASK_MUL16 0x00000008 /* 16-bit integer multiply */
51 #define MASK_MUL32 0x00000010 /* integer multiply/divide */
52 #define MASK_DIV32 0x00000020 /* integer multiply/divide */
53 #define MASK_NSA 0x00000040 /* nsa instruction option */
54 #define MASK_MINMAX 0x00000080 /* min/max instructions */
55 #define MASK_SEXT 0x00000100 /* sign extend insn option */
56 #define MASK_BOOLEANS 0x00000200 /* boolean register option */
57 #define MASK_HARD_FLOAT 0x00000400 /* floating-point option */
58 #define MASK_HARD_FLOAT_DIV 0x00000800 /* floating-point divide */
59 #define MASK_HARD_FLOAT_RECIP 0x00001000 /* floating-point reciprocal */
60 #define MASK_HARD_FLOAT_SQRT 0x00002000 /* floating-point sqrt */
61 #define MASK_HARD_FLOAT_RSQRT 0x00004000 /* floating-point recip sqrt */
62 #define MASK_NO_FUSED_MADD 0x00008000 /* avoid f-p mul/add */
63 #define MASK_SERIALIZE_VOLATILE 0x00010000 /* serialize volatile refs */
65 /* Macros used in the machine description to test the flags. */
67 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
68 #define TARGET_DENSITY (target_flags & MASK_DENSITY)
69 #define TARGET_MAC16 (target_flags & MASK_MAC16)
70 #define TARGET_MUL16 (target_flags & MASK_MUL16)
71 #define TARGET_MUL32 (target_flags & MASK_MUL32)
72 #define TARGET_DIV32 (target_flags & MASK_DIV32)
73 #define TARGET_NSA (target_flags & MASK_NSA)
74 #define TARGET_MINMAX (target_flags & MASK_MINMAX)
75 #define TARGET_SEXT (target_flags & MASK_SEXT)
76 #define TARGET_BOOLEANS (target_flags & MASK_BOOLEANS)
77 #define TARGET_HARD_FLOAT (target_flags & MASK_HARD_FLOAT)
78 #define TARGET_HARD_FLOAT_DIV (target_flags & MASK_HARD_FLOAT_DIV)
79 #define TARGET_HARD_FLOAT_RECIP (target_flags & MASK_HARD_FLOAT_RECIP)
80 #define TARGET_HARD_FLOAT_SQRT (target_flags & MASK_HARD_FLOAT_SQRT)
81 #define TARGET_HARD_FLOAT_RSQRT (target_flags & MASK_HARD_FLOAT_RSQRT)
82 #define TARGET_NO_FUSED_MADD (target_flags & MASK_NO_FUSED_MADD)
83 #define TARGET_SERIALIZE_VOLATILE (target_flags & MASK_SERIALIZE_VOLATILE)
85 /* Default target_flags if no switches are specified */
87 #define TARGET_DEFAULT ( \
88 (XCHAL_HAVE_BE ? MASK_BIG_ENDIAN : 0) | \
89 (XCHAL_HAVE_DENSITY ? MASK_DENSITY : 0) | \
90 (XCHAL_HAVE_MAC16 ? MASK_MAC16 : 0) | \
91 (XCHAL_HAVE_MUL16 ? MASK_MUL16 : 0) | \
92 (XCHAL_HAVE_MUL32 ? MASK_MUL32 : 0) | \
93 (XCHAL_HAVE_DIV32 ? MASK_DIV32 : 0) | \
94 (XCHAL_HAVE_NSA ? MASK_NSA : 0) | \
95 (XCHAL_HAVE_MINMAX ? MASK_MINMAX : 0) | \
96 (XCHAL_HAVE_SEXT ? MASK_SEXT : 0) | \
97 (XCHAL_HAVE_BOOLEANS ? MASK_BOOLEANS : 0) | \
98 (XCHAL_HAVE_FP ? MASK_HARD_FLOAT : 0) | \
99 (XCHAL_HAVE_FP_DIV ? MASK_HARD_FLOAT_DIV : 0) | \
100 (XCHAL_HAVE_FP_RECIP ? MASK_HARD_FLOAT_RECIP : 0) | \
101 (XCHAL_HAVE_FP_SQRT ? MASK_HARD_FLOAT_SQRT : 0) | \
102 (XCHAL_HAVE_FP_RSQRT ? MASK_HARD_FLOAT_RSQRT : 0) | \
103 MASK_SERIALIZE_VOLATILE)
105 /* Macro to define tables used to set the flags. */
107 #define TARGET_SWITCHES \
109 {"big-endian", MASK_BIG_ENDIAN, \
110 N_("Use big-endian byte order")}, \
111 {"little-endian", -MASK_BIG_ENDIAN, \
112 N_("Use little-endian byte order")}, \
113 {"density", MASK_DENSITY, \
114 N_("Use the Xtensa code density option")}, \
115 {"no-density", -MASK_DENSITY, \
116 N_("Do not use the Xtensa code density option")}, \
117 {"mac16", MASK_MAC16, \
118 N_("Use the Xtensa MAC16 option")}, \
119 {"no-mac16", -MASK_MAC16, \
120 N_("Do not use the Xtensa MAC16 option")}, \
121 {"mul16", MASK_MUL16, \
122 N_("Use the Xtensa MUL16 option")}, \
123 {"no-mul16", -MASK_MUL16, \
124 N_("Do not use the Xtensa MUL16 option")}, \
125 {"mul32", MASK_MUL32, \
126 N_("Use the Xtensa MUL32 option")}, \
127 {"no-mul32", -MASK_MUL32, \
128 N_("Do not use the Xtensa MUL32 option")}, \
129 {"div32", MASK_DIV32, \
130 0 /* undocumented */}, \
131 {"no-div32", -MASK_DIV32, \
132 0 /* undocumented */}, \
134 N_("Use the Xtensa NSA option")}, \
135 {"no-nsa", -MASK_NSA, \
136 N_("Do not use the Xtensa NSA option")}, \
137 {"minmax", MASK_MINMAX, \
138 N_("Use the Xtensa MIN/MAX option")}, \
139 {"no-minmax", -MASK_MINMAX, \
140 N_("Do not use the Xtensa MIN/MAX option")}, \
141 {"sext", MASK_SEXT, \
142 N_("Use the Xtensa SEXT option")}, \
143 {"no-sext", -MASK_SEXT, \
144 N_("Do not use the Xtensa SEXT option")}, \
145 {"booleans", MASK_BOOLEANS, \
146 N_("Use the Xtensa boolean register option")}, \
147 {"no-booleans", -MASK_BOOLEANS, \
148 N_("Do not use the Xtensa boolean register option")}, \
149 {"hard-float", MASK_HARD_FLOAT, \
150 N_("Use the Xtensa floating-point unit")}, \
151 {"soft-float", -MASK_HARD_FLOAT, \
152 N_("Do not use the Xtensa floating-point unit")}, \
153 {"hard-float-div", MASK_HARD_FLOAT_DIV, \
154 0 /* undocumented */}, \
155 {"no-hard-float-div", -MASK_HARD_FLOAT_DIV, \
156 0 /* undocumented */}, \
157 {"hard-float-recip", MASK_HARD_FLOAT_RECIP, \
158 0 /* undocumented */}, \
159 {"no-hard-float-recip", -MASK_HARD_FLOAT_RECIP, \
160 0 /* undocumented */}, \
161 {"hard-float-sqrt", MASK_HARD_FLOAT_SQRT, \
162 0 /* undocumented */}, \
163 {"no-hard-float-sqrt", -MASK_HARD_FLOAT_SQRT, \
164 0 /* undocumented */}, \
165 {"hard-float-rsqrt", MASK_HARD_FLOAT_RSQRT, \
166 0 /* undocumented */}, \
167 {"no-hard-float-rsqrt", -MASK_HARD_FLOAT_RSQRT, \
168 0 /* undocumented */}, \
169 {"no-fused-madd", MASK_NO_FUSED_MADD, \
170 N_("Disable fused multiply/add and multiply/subtract FP instructions")}, \
171 {"fused-madd", -MASK_NO_FUSED_MADD, \
172 N_("Enable fused multiply/add and multiply/subtract FP instructions")}, \
173 {"serialize-volatile", MASK_SERIALIZE_VOLATILE, \
174 N_("Serialize volatile memory references with MEMW instructions")}, \
175 {"no-serialize-volatile", -MASK_SERIALIZE_VOLATILE, \
176 N_("Do not serialize volatile memory references with MEMW instructions")},\
177 {"text-section-literals", 0, \
178 N_("Intersperse literal pools with code in the text section")}, \
179 {"no-text-section-literals", 0, \
180 N_("Put literal pools in a separate literal section")}, \
181 {"target-align", 0, \
182 N_("Automatically align branch targets to reduce branch penalties")}, \
183 {"no-target-align", 0, \
184 N_("Do not automatically align branch targets")}, \
186 N_("Use indirect CALLXn instructions for large programs")}, \
187 {"no-longcalls", 0, \
188 N_("Use direct CALLn instructions for fast calls")}, \
189 {"", TARGET_DEFAULT, 0} \
193 #define OVERRIDE_OPTIONS override_options ()
196 #define CPP_ENDIAN_SPEC "\
197 %{mlittle-endian:-D__XTENSA_EL__} \
198 %{!mlittle-endian:-D__XTENSA_EB__} "
199 #else /* !XCHAL_HAVE_BE */
200 #define CPP_ENDIAN_SPEC "\
201 %{mbig-endian:-D__XTENSA_EB__} \
202 %{!mbig-endian:-D__XTENSA_EL__} "
203 #endif /* !XCHAL_HAVE_BE */
206 #define CPP_FLOAT_SPEC "%{msoft-float:-D__XTENSA_SOFT_FLOAT__}"
208 #define CPP_FLOAT_SPEC "%{!mhard-float:-D__XTENSA_SOFT_FLOAT__}"
212 #define CPP_SPEC CPP_ENDIAN_SPEC CPP_FLOAT_SPEC
214 /* Define this to set the endianness to use in libgcc2.c, which can
215 not depend on target_flags. */
216 #define LIBGCC2_WORDS_BIG_ENDIAN XCHAL_HAVE_BE
218 /* Show we can debug even without a frame pointer. */
219 #define CAN_DEBUG_WITHOUT_FP
222 /* Target machine storage layout */
224 /* Define in order to support both big and little endian float formats
225 in the same gcc binary. */
226 #define REAL_ARITHMETIC
228 /* Define this if most significant bit is lowest numbered
229 in instructions that operate on numbered bit-fields. */
230 #define BITS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
232 /* Define this if most significant byte of a word is the lowest numbered. */
233 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
235 /* Define this if most significant word of a multiword number is the lowest. */
236 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
238 #define MAX_BITS_PER_WORD 32
240 /* Width of a word, in units (bytes). */
241 #define UNITS_PER_WORD 4
242 #define MIN_UNITS_PER_WORD 4
244 /* Width of a floating point register. */
245 #define UNITS_PER_FPREG 4
247 /* Size in bits of various types on the target machine. */
248 #define INT_TYPE_SIZE 32
249 #define MAX_INT_TYPE_SIZE 32
250 #define SHORT_TYPE_SIZE 16
251 #define LONG_TYPE_SIZE 32
252 #define MAX_LONG_TYPE_SIZE 32
253 #define LONG_LONG_TYPE_SIZE 64
254 #define FLOAT_TYPE_SIZE 32
255 #define DOUBLE_TYPE_SIZE 64
256 #define LONG_DOUBLE_TYPE_SIZE 64
257 #define POINTER_SIZE 32
259 /* Tell the preprocessor the maximum size of wchar_t. */
260 #ifndef MAX_WCHAR_TYPE_SIZE
261 #ifndef WCHAR_TYPE_SIZE
262 #define MAX_WCHAR_TYPE_SIZE MAX_INT_TYPE_SIZE
266 /* Allocation boundary (in *bits*) for storing pointers in memory. */
267 #define POINTER_BOUNDARY 32
269 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
270 #define PARM_BOUNDARY 32
272 /* Allocation boundary (in *bits*) for the code of a function. */
273 #define FUNCTION_BOUNDARY 32
275 /* Alignment of field after 'int : 0' in a structure. */
276 #define EMPTY_FIELD_BOUNDARY 32
278 /* Every structure's size must be a multiple of this. */
279 #define STRUCTURE_SIZE_BOUNDARY 8
281 /* There is no point aligning anything to a rounder boundary than this. */
282 #define BIGGEST_ALIGNMENT 128
284 /* Set this nonzero if move instructions will actually fail to work
285 when given unaligned data. */
286 #define STRICT_ALIGNMENT 1
288 /* Promote integer modes smaller than a word to SImode. Set UNSIGNEDP
289 for QImode, because there is no 8-bit load from memory with sign
290 extension. Otherwise, leave UNSIGNEDP alone, since Xtensa has 16-bit
291 loads both with and without sign extension. */
292 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
294 if (GET_MODE_CLASS (MODE) == MODE_INT \
295 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
297 if ((MODE) == QImode) \
303 /* The promotion described by `PROMOTE_MODE' should also be done for
304 outgoing function arguments. */
305 #define PROMOTE_FUNCTION_ARGS
307 /* The promotion described by `PROMOTE_MODE' should also be done for
308 the return value of functions. Note: `FUNCTION_VALUE' must perform
309 the same promotions done by `PROMOTE_MODE'. */
310 #define PROMOTE_FUNCTION_RETURN
312 /* Imitate the way many other C compilers handle alignment of
313 bitfields and the structures that contain them. */
314 #define PCC_BITFIELD_TYPE_MATTERS 1
316 /* Align string constants and constructors to at least a word boundary.
317 The typical use of this macro is to increase alignment for string
318 constants to be word aligned so that 'strcpy' calls that copy
319 constants can be done inline. */
320 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
321 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
322 && (ALIGN) < BITS_PER_WORD \
326 /* Align arrays, unions and records to at least a word boundary.
327 One use of this macro is to increase alignment of medium-size
328 data to make it all fit in fewer cache lines. Another is to
329 cause character arrays to be word-aligned so that 'strcpy' calls
330 that copy constants to character arrays can be done inline. */
331 #undef DATA_ALIGNMENT
332 #define DATA_ALIGNMENT(TYPE, ALIGN) \
333 ((((ALIGN) < BITS_PER_WORD) \
334 && (TREE_CODE (TYPE) == ARRAY_TYPE \
335 || TREE_CODE (TYPE) == UNION_TYPE \
336 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
338 /* An argument declared as 'char' or 'short' in a prototype should
339 actually be passed as an 'int'. */
340 #define PROMOTE_PROTOTYPES 1
342 /* Operations between registers always perform the operation
343 on the full register even if a narrower mode is specified. */
344 #define WORD_REGISTER_OPERATIONS
346 /* Xtensa loads are zero-extended by default. */
347 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
349 /* Standard register usage. */
351 /* Number of actual hardware registers.
352 The hardware registers are assigned numbers for the compiler
353 from 0 to just below FIRST_PSEUDO_REGISTER.
354 All registers that the compiler knows about must be given numbers,
355 even those that are not normally considered general registers.
357 The fake frame pointer and argument pointer will never appear in
358 the generated code, since they will always be eliminated and replaced
359 by either the stack pointer or the hard frame pointer.
361 0 - 15 AR[0] - AR[15]
362 16 FRAME_POINTER (fake = initial sp)
363 17 ARG_POINTER (fake = initial sp + framesize)
364 18 LOOP_COUNT (loop count special register)
365 18 BR[0] for floating-point CC
366 19 - 34 FR[0] - FR[15]
367 35 MAC16 accumulator */
369 #define FIRST_PSEUDO_REGISTER 36
371 /* Return the stabs register number to use for REGNO. */
372 #define DBX_REGISTER_NUMBER(REGNO) xtensa_dbx_register_number (REGNO)
374 /* 1 for registers that have pervasive standard uses
375 and are not available for the register allocator. */
376 #define FIXED_REGISTERS \
378 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
380 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
384 /* 1 for registers not available across function calls.
385 These must include the FIXED_REGISTERS and also any
386 registers that can be used without being saved.
387 The latter must include the registers where values are returned
388 and the register where structure-value addresses are passed.
389 Aside from that, you can include as many other registers as you like. */
390 #define CALL_USED_REGISTERS \
392 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
394 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
398 /* For non-leaf procedures on Xtensa processors, the allocation order
399 is as specified below by REG_ALLOC_ORDER. For leaf procedures, we
400 want to use the lowest numbered registers first to minimize
401 register window overflows. However, local-alloc is not smart
402 enough to consider conflicts with incoming arguments. If an
403 incoming argument in a2 is live throughout the function and
404 local-alloc decides to use a2, then the incoming argument must
405 either be spilled or copied to another register. To get around
406 this, we define ORDER_REGS_FOR_LOCAL_ALLOC to redefine
407 reg_alloc_order for leaf functions such that lowest numbered
408 registers are used first with the exception that the incoming
409 argument registers are not used until after other register choices
410 have been exhausted. */
412 #define REG_ALLOC_ORDER \
413 { 8, 9, 10, 11, 12, 13, 14, 15, 7, 6, 5, 4, 3, 2, 19, \
414 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, \
419 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
421 /* For Xtensa, the only point of this is to prevent GCC from otherwise
422 giving preference to call-used registers. To minimize window
423 overflows for the AR registers, we want to give preference to the
424 lower-numbered AR registers. For other register files, which are
425 not windowed, we still prefer call-used registers, if there are any. */
426 extern const char xtensa_leaf_regs[FIRST_PSEUDO_REGISTER];
427 #define LEAF_REGISTERS xtensa_leaf_regs
429 /* For Xtensa, no remapping is necessary, but this macro must be
430 defined if LEAF_REGISTERS is defined. */
431 #define LEAF_REG_REMAP(REGNO) (REGNO)
433 /* this must be declared if LEAF_REGISTERS is set */
434 extern int leaf_function;
436 /* Internal macros to classify a register number. */
438 /* 16 address registers + fake registers */
439 #define GP_REG_FIRST 0
440 #define GP_REG_LAST 17
441 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
443 /* Special registers */
444 #define SPEC_REG_FIRST 18
445 #define SPEC_REG_LAST 18
446 #define SPEC_REG_NUM (SPEC_REG_LAST - SPEC_REG_FIRST + 1)
448 /* Coprocessor registers */
449 #define BR_REG_FIRST 18
450 #define BR_REG_LAST 18
451 #define BR_REG_NUM (BR_REG_LAST - BR_REG_FIRST + 1)
453 /* 16 floating-point registers */
454 #define FP_REG_FIRST 19
455 #define FP_REG_LAST 34
456 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
458 /* MAC16 accumulator */
459 #define ACC_REG_FIRST 35
460 #define ACC_REG_LAST 35
461 #define ACC_REG_NUM (ACC_REG_LAST - ACC_REG_FIRST + 1)
463 #define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM)
464 #define BR_REG_P(REGNO) ((unsigned) ((REGNO) - BR_REG_FIRST) < BR_REG_NUM)
465 #define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM)
466 #define ACC_REG_P(REGNO) ((unsigned) ((REGNO) - ACC_REG_FIRST) < ACC_REG_NUM)
468 /* Return number of consecutive hard regs needed starting at reg REGNO
469 to hold something of mode MODE. */
470 #define HARD_REGNO_NREGS(REGNO, MODE) \
471 (FP_REG_P (REGNO) ? \
472 ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG) : \
473 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
475 /* Value is 1 if hard register REGNO can hold a value of machine-mode
477 extern char xtensa_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
479 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
480 xtensa_hard_regno_mode_ok[(int) (MODE)][(REGNO)]
482 /* Value is 1 if it is a good idea to tie two pseudo registers
483 when one has mode MODE1 and one has mode MODE2.
484 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
485 for any hard reg, then this must be 0 for correct output. */
486 #define MODES_TIEABLE_P(MODE1, MODE2) \
487 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
488 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
489 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
490 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
492 /* Register to use for LCOUNT special register. */
493 #define COUNT_REGISTER_REGNUM (SPEC_REG_FIRST + 0)
495 /* Register to use for pushing function arguments. */
496 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 1)
498 /* Base register for access to local variables of the function. */
499 #define HARD_FRAME_POINTER_REGNUM (GP_REG_FIRST + 7)
501 /* The register number of the frame pointer register, which is used to
502 access automatic variables in the stack frame. For Xtensa, this
503 register never appears in the output. It is always eliminated to
504 either the stack pointer or the hard frame pointer. */
505 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 16)
507 /* Value should be nonzero if functions must have frame pointers.
508 Zero means the frame pointer need not be set up (and parms
509 may be accessed via the stack pointer) in functions that seem suitable.
510 This is computed in 'reload', in reload1.c. */
511 #define FRAME_POINTER_REQUIRED xtensa_frame_pointer_required ()
513 /* Base register for access to arguments of the function. */
514 #define ARG_POINTER_REGNUM (GP_REG_FIRST + 17)
516 /* If the static chain is passed in memory, these macros provide rtx
517 giving 'mem' expressions that denote where they are stored.
518 'STATIC_CHAIN' and 'STATIC_CHAIN_INCOMING' give the locations as
519 seen by the calling and called functions, respectively. */
521 #define STATIC_CHAIN \
522 gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, -5 * UNITS_PER_WORD))
524 #define STATIC_CHAIN_INCOMING \
525 gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -5 * UNITS_PER_WORD))
527 /* For now we don't try to use the full set of boolean registers. Without
528 software pipelining of FP operations, there's not much to gain and it's
529 a real pain to get them reloaded. */
530 #define FPCC_REGNUM (BR_REG_FIRST + 0)
532 /* Pass structure value address as an "invisible" first argument. */
533 #define STRUCT_VALUE 0
535 /* It is as good or better to call a constant function address than to
536 call an address kept in a register. */
537 #define NO_FUNCTION_CSE 1
539 /* It is as good or better for a function to call itself with an
540 explicit address than to call an address kept in a register. */
541 #define NO_RECURSIVE_FUNCTION_CSE 1
543 /* Xtensa processors have "register windows". GCC does not currently
544 take advantage of the possibility for variable-sized windows; instead,
545 we use a fixed window size of 8. */
547 #define INCOMING_REGNO(OUT) \
548 ((GP_REG_P (OUT) && \
549 ((unsigned) ((OUT) - GP_REG_FIRST) >= WINDOW_SIZE)) ? \
550 (OUT) - WINDOW_SIZE : (OUT))
552 #define OUTGOING_REGNO(IN) \
554 ((unsigned) ((IN) - GP_REG_FIRST) < WINDOW_SIZE)) ? \
555 (IN) + WINDOW_SIZE : (IN))
558 /* Define the classes of registers for register constraints in the
559 machine description. */
562 NO_REGS, /* no registers in set */
563 BR_REGS, /* coprocessor boolean registers */
564 FP_REGS, /* floating point registers */
565 ACC_REG, /* MAC16 accumulator */
566 SP_REG, /* sp register (aka a1) */
567 GR_REGS, /* integer registers except sp */
568 AR_REGS, /* all integer registers */
569 ALL_REGS, /* all registers */
570 LIM_REG_CLASSES /* max value + 1 */
573 #define N_REG_CLASSES (int) LIM_REG_CLASSES
575 #define GENERAL_REGS AR_REGS
577 /* An initializer containing the names of the register classes as C
578 string constants. These names are used in writing some of the
580 #define REG_CLASS_NAMES \
592 /* Contents of the register classes. The Nth integer specifies the
593 contents of class N. The way the integer MASK is interpreted is
594 that register R is in the class if 'MASK & (1 << R)' is 1. */
595 #define REG_CLASS_CONTENTS \
597 { 0x00000000, 0x00000000 }, /* no registers */ \
598 { 0x00040000, 0x00000000 }, /* coprocessor boolean registers */ \
599 { 0xfff80000, 0x00000007 }, /* floating-point registers */ \
600 { 0x00000000, 0x00000008 }, /* MAC16 accumulator */ \
601 { 0x00000002, 0x00000000 }, /* stack pointer register */ \
602 { 0x0000fffd, 0x00000000 }, /* general-purpose registers */ \
603 { 0x0003ffff, 0x00000000 }, /* integer registers */ \
604 { 0xffffffff, 0x0000000f } /* all registers */ \
607 /* A C expression whose value is a register class containing hard
608 register REGNO. In general there is more that one such class;
609 choose a class which is "minimal", meaning that no smaller class
610 also contains the register. */
611 extern const enum reg_class xtensa_regno_to_class[FIRST_PSEUDO_REGISTER];
613 #define REGNO_REG_CLASS(REGNO) xtensa_regno_to_class[ (REGNO) ]
615 /* Use the Xtensa AR register file for base registers.
616 No index registers. */
617 #define BASE_REG_CLASS AR_REGS
618 #define INDEX_REG_CLASS NO_REGS
620 /* SMALL_REGISTER_CLASSES is required for Xtensa, because all of the
621 16 AR registers may be explicitly used in the RTL, as either
622 incoming or outgoing arguments. */
623 #define SMALL_REGISTER_CLASSES 1
626 /* REGISTER AND CONSTANT CLASSES */
628 /* Get reg_class from a letter such as appears in the machine
631 Available letters: a-f,h,j-l,q,t-z,A-D,W,Y-Z
633 DEFINED REGISTER CLASSES:
635 'a' general-purpose registers except sp
637 'D' general-purpose registers (only if density option enabled)
638 'd' general-purpose registers, including sp (only if density enabled)
639 'A' MAC16 accumulator (only if MAC16 option enabled)
640 'B' general-purpose registers (only if sext instruction enabled)
641 'C' general-purpose registers (only if mul16 option enabled)
642 'b' coprocessor boolean registers
643 'f' floating-point registers
646 extern enum reg_class xtensa_char_to_class[256];
648 #define REG_CLASS_FROM_LETTER(C) xtensa_char_to_class[ (int) (C) ]
650 /* The letters I, J, K, L, M, N, O, and P in a register constraint
651 string can be used to stand for particular ranges of immediate
652 operands. This macro defines what the ranges are. C is the
653 letter, and VALUE is a constant value. Return 1 if VALUE is
654 in the range specified by C.
658 I = 12-bit signed immediate for movi
659 J = 8-bit signed immediate for addi
660 K = 4-bit value in (b4const U {0})
661 L = 4-bit value in b4constu
662 M = 7-bit value in simm7
663 N = 8-bit unsigned immediate shifted left by 8 bits for addmi
664 O = 4-bit value in ai4const
665 P = valid immediate mask value for extui */
667 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
668 ((C) == 'I' ? (xtensa_simm12b (VALUE)) \
669 : (C) == 'J' ? (xtensa_simm8 (VALUE)) \
670 : (C) == 'K' ? (((VALUE) == 0) || xtensa_b4const (VALUE)) \
671 : (C) == 'L' ? (xtensa_b4constu (VALUE)) \
672 : (C) == 'M' ? (xtensa_simm7 (VALUE)) \
673 : (C) == 'N' ? (xtensa_simm8x256 (VALUE)) \
674 : (C) == 'O' ? (xtensa_ai4const (VALUE)) \
675 : (C) == 'P' ? (xtensa_mask_immediate (VALUE)) \
679 /* Similar, but for floating constants, and defining letters G and H.
680 Here VALUE is the CONST_DOUBLE rtx itself. */
681 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) (0)
684 /* Other letters can be defined in a machine-dependent fashion to
685 stand for particular classes of registers or other arbitrary
688 R = memory that can be accessed with a 4-bit unsigned offset
689 S = memory where the second word can be addressed with a 4-bit offset
690 T = memory in a constant pool (addressable with a pc-relative load)
691 U = memory *NOT* in a constant pool
693 The offset range should not be checked here (except to distinguish
694 denser versions of the instructions for which more general versions
695 are available). Doing so leads to problems in reloading: an
696 argptr-relative address may become invalid when the phony argptr is
697 eliminated in favor of the stack pointer (the offset becomes too
698 large to fit in the instruction's immediate field); a reload is
699 generated to fix this but the RTL is not immediately updated; in
700 the meantime, the constraints are checked and none match. The
701 solution seems to be to simply skip the offset check here. The
702 address will be checked anyway because of the code in
703 GO_IF_LEGITIMATE_ADDRESS. */
705 #define EXTRA_CONSTRAINT(OP, CODE) \
706 ((GET_CODE (OP) != MEM) ? \
707 ((CODE) >= 'R' && (CODE) <= 'U' \
708 && reload_in_progress && GET_CODE (OP) == REG \
709 && REGNO (OP) >= FIRST_PSEUDO_REGISTER) \
710 : ((CODE) == 'R') ? smalloffset_mem_p (OP) \
711 : ((CODE) == 'S') ? smalloffset_double_mem_p (OP) \
712 : ((CODE) == 'T') ? constantpool_mem_p (OP) \
713 : ((CODE) == 'U') ? !constantpool_mem_p (OP) \
716 /* Given an rtx X being reloaded into a reg required to be
717 in class CLASS, return the class of reg to actually use. */
718 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
720 ? (GET_CODE (X) == CONST_DOUBLE) ? NO_REGS : (CLASS) \
723 #define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \
726 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
727 xtensa_secondary_reload_class (CLASS, MODE, X, 0)
729 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
730 xtensa_secondary_reload_class (CLASS, MODE, X, 1)
732 /* Return the maximum number of consecutive registers
733 needed to represent mode MODE in a register of class CLASS. */
734 #define CLASS_UNITS(mode, size) \
735 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
737 #define CLASS_MAX_NREGS(CLASS, MODE) \
738 (CLASS_UNITS (MODE, UNITS_PER_WORD))
741 /* Stack layout; function entry, exit and calling. */
743 #define STACK_GROWS_DOWNWARD
745 /* Offset within stack frame to start allocating local variables at. */
746 #define STARTING_FRAME_OFFSET \
747 current_function_outgoing_args_size
749 /* The ARG_POINTER and FRAME_POINTER are not real Xtensa registers, so
750 they are eliminated to either the stack pointer or hard frame pointer. */
751 #define ELIMINABLE_REGS \
752 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
753 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
754 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
755 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
757 #define CAN_ELIMINATE(FROM, TO) 1
759 /* Specify the initial difference between the specified pair of registers. */
760 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
762 compute_frame_size (get_frame_size ()); \
763 if ((FROM) == FRAME_POINTER_REGNUM) \
765 else if ((FROM) == ARG_POINTER_REGNUM) \
766 (OFFSET) = xtensa_current_frame_size; \
771 /* If defined, the maximum amount of space required for outgoing
772 arguments will be computed and placed into the variable
773 'current_function_outgoing_args_size'. No space will be pushed
774 onto the stack for each call; instead, the function prologue
775 should increase the stack frame size by this amount. */
776 #define ACCUMULATE_OUTGOING_ARGS 1
778 /* Offset from the argument pointer register to the first argument's
779 address. On some machines it may depend on the data type of the
780 function. If 'ARGS_GROW_DOWNWARD', this is the offset to the
781 location above the first argument's address. */
782 #define FIRST_PARM_OFFSET(FNDECL) 0
784 /* Align stack frames on 128 bits for Xtensa. This is necessary for
785 128-bit datatypes defined in TIE (e.g., for Vectra). */
786 #define STACK_BOUNDARY 128
788 /* Functions do not pop arguments off the stack. */
789 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
791 /* Use a fixed register window size of 8. */
792 #define WINDOW_SIZE 8
794 /* Symbolic macros for the registers used to return integer, floating
795 point, and values of coprocessor and user-defined modes. */
796 #define GP_RETURN (GP_REG_FIRST + 2 + WINDOW_SIZE)
797 #define GP_OUTGOING_RETURN (GP_REG_FIRST + 2)
799 /* Symbolic macros for the first/last argument registers. */
800 #define GP_ARG_FIRST (GP_REG_FIRST + 2)
801 #define GP_ARG_LAST (GP_REG_FIRST + 7)
802 #define GP_OUTGOING_ARG_FIRST (GP_REG_FIRST + 2 + WINDOW_SIZE)
803 #define GP_OUTGOING_ARG_LAST (GP_REG_FIRST + 7 + WINDOW_SIZE)
805 #define MAX_ARGS_IN_REGISTERS 6
807 /* Don't worry about compatibility with PCC. */
808 #define DEFAULT_PCC_STRUCT_RETURN 0
810 /* For Xtensa, we would like to be able to return up to 6 words in
811 memory but GCC cannot support that. The return value must be given
812 one of the standard MODE_INT modes, and there is no 6 word mode.
813 Instead, if we try to return a 6 word structure, GCC selects the
814 next biggest mode (OImode, 8 words) and then the register allocator
815 fails because there is no 8-register group beginning with a10. So
816 we have to fall back on the next largest size which is 4 words... */
817 #define RETURN_IN_MEMORY(TYPE) \
818 ((unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) > 4 * UNITS_PER_WORD)
820 /* Define how to find the value returned by a library function
821 assuming the value has mode MODE. Because we have defined
822 PROMOTE_FUNCTION_RETURN, we have to perform the same promotions as
824 #define XTENSA_LIBCALL_VALUE(MODE, OUTGOINGP) \
825 gen_rtx_REG ((GET_MODE_CLASS (MODE) == MODE_INT \
826 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
828 OUTGOINGP ? GP_OUTGOING_RETURN : GP_RETURN)
830 #define LIBCALL_VALUE(MODE) \
831 XTENSA_LIBCALL_VALUE ((MODE), 0)
833 #define LIBCALL_OUTGOING_VALUE(MODE) \
834 XTENSA_LIBCALL_VALUE ((MODE), 1)
836 /* Define how to find the value returned by a function.
837 VALTYPE is the data type of the value (as a tree).
838 If the precise function being called is known, FUNC is its FUNCTION_DECL;
839 otherwise, FUNC is 0. */
840 #define XTENSA_FUNCTION_VALUE(VALTYPE, FUNC, OUTGOINGP) \
841 gen_rtx_REG ((INTEGRAL_TYPE_P (VALTYPE) \
842 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
843 ? SImode: TYPE_MODE (VALTYPE), \
844 OUTGOINGP ? GP_OUTGOING_RETURN : GP_RETURN)
846 #define FUNCTION_VALUE(VALTYPE, FUNC) \
847 XTENSA_FUNCTION_VALUE (VALTYPE, FUNC, 0)
849 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
850 XTENSA_FUNCTION_VALUE (VALTYPE, FUNC, 1)
852 /* A C expression that is nonzero if REGNO is the number of a hard
853 register in which the values of called function may come back. A
854 register whose use for returning values is limited to serving as
855 the second of a pair (for a value of type 'double', say) need not
856 be recognized by this macro. If the machine has register windows,
857 so that the caller and the called function use different registers
858 for the return value, this macro should recognize only the caller's
860 #define FUNCTION_VALUE_REGNO_P(N) \
863 /* A C expression that is nonzero if REGNO is the number of a hard
864 register in which function arguments are sometimes passed. This
865 does *not* include implicit arguments such as the static chain and
866 the structure-value address. On many machines, no registers can be
867 used for this purpose since all function arguments are pushed on
869 #define FUNCTION_ARG_REGNO_P(N) \
870 ((N) >= GP_OUTGOING_ARG_FIRST && (N) <= GP_OUTGOING_ARG_LAST)
872 /* Use IEEE floating-point format. */
873 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
875 /* Define a data type for recording info about an argument list
876 during the scan of that argument list. This data type should
877 hold all necessary information about the function itself
878 and about the args processed so far, enough to enable macros
879 such as FUNCTION_ARG to determine where the next arg should go. */
880 typedef struct xtensa_args {
881 int arg_words; /* # total words the arguments take */
884 /* Initialize a variable CUM of type CUMULATIVE_ARGS
885 for a call to a function whose data type is FNTYPE.
886 For a library call, FNTYPE is 0. */
887 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
888 init_cumulative_args (&CUM, FNTYPE, LIBNAME)
890 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
891 init_cumulative_args (&CUM, FNTYPE, LIBNAME)
893 /* Update the data in CUM to advance over an argument
894 of mode MODE and data type TYPE.
895 (TYPE is null for libcalls where that information may not be available.) */
896 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
897 function_arg_advance (&CUM, MODE, TYPE)
899 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
900 function_arg (&CUM, MODE, TYPE, FALSE)
902 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
903 function_arg (&CUM, MODE, TYPE, TRUE)
905 /* Arguments are never passed partly in memory and partly in registers. */
906 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) (0)
908 /* Specify function argument alignment. */
909 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
911 ? (TYPE_ALIGN (TYPE) <= PARM_BOUNDARY \
913 : TYPE_ALIGN (TYPE)) \
914 : (GET_MODE_ALIGNMENT (MODE) <= PARM_BOUNDARY \
916 : GET_MODE_ALIGNMENT (MODE)))
919 /* Nonzero if we do not know how to pass TYPE solely in registers.
920 We cannot do so in the following cases:
922 - if the type has variable size
923 - if the type is marked as addressable (it is required to be constructed
926 This differs from the default in that it does not check if the padding
927 and mode of the type are such that a copy into a register would put it
928 into the wrong part of the register. */
930 #define MUST_PASS_IN_STACK(MODE, TYPE) \
932 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
933 || TREE_ADDRESSABLE (TYPE)))
935 /* Output assembler code to FILE to increment profiler label LABELNO
936 for profiling a function entry.
938 The mcount code in glibc doesn't seem to use this LABELNO stuff.
939 Some ports (e.g., MIPS) don't even bother to pass the label
940 address, and even those that do (e.g., i386) don't seem to use it.
941 The information needed by mcount() is the current PC and the
942 current return address, so that mcount can identify an arc in the
943 call graph. For Xtensa, we pass the current return address as
944 the first argument to mcount, and the current PC is available as
945 a0 in mcount's register window. Both of these values contain
946 window size information in the two most significant bits; we assume
947 that the mcount code will mask off those bits. The call to mcount
948 uses a window size of 8 to make sure that mcount doesn't clobber
949 any incoming argument values. */
951 #define FUNCTION_PROFILER(FILE, LABELNO) \
953 fprintf (FILE, "\taddi\t%s, %s, 0\t# save current return address\n", \
954 reg_names[GP_REG_FIRST+10], \
955 reg_names[GP_REG_FIRST+0]); \
956 fprintf (FILE, "\tcall8\t_mcount\n"); \
959 /* Stack pointer value doesn't matter at exit. */
960 #define EXIT_IGNORE_STACK 1
962 /* A C statement to output, on the stream FILE, assembler code for a
963 block of data that contains the constant parts of a trampoline.
964 This code should not include a label--the label is taken care of
967 For Xtensa, the trampoline must perform an entry instruction with a
968 minimal stack frame in order to get some free registers. Once the
969 actual call target is known, the proper stack frame size is extracted
970 from the entry instruction at the target and the current frame is
971 adjusted to match. The trampoline then transfers control to the
972 instruction following the entry at the target. Note: this assumes
973 that the target begins with an entry instruction. */
975 /* minimum frame = reg save area (4 words) plus static chain (1 word)
976 and the total number of words must be a multiple of 128 bits */
977 #define MIN_FRAME_SIZE (8 * UNITS_PER_WORD)
979 #define TRAMPOLINE_TEMPLATE(STREAM) \
981 fprintf (STREAM, "\t.begin no-generics\n"); \
982 fprintf (STREAM, "\tentry\tsp, %d\n", MIN_FRAME_SIZE); \
984 /* GCC isn't prepared to deal with data at the beginning of the \
985 trampoline, and the Xtensa l32r instruction requires that the \
986 constant pool be located before the code. We put the constant \
987 pool in the middle of the trampoline and jump around it. */ \
989 fprintf (STREAM, "\tj\t.Lskipconsts\n"); \
990 fprintf (STREAM, "\t.align\t4\n"); \
991 fprintf (STREAM, ".Lfnaddr:%s0\n", integer_asm_op (4, TRUE)); \
992 fprintf (STREAM, ".Lchainval:%s0\n", integer_asm_op (4, TRUE)); \
993 fprintf (STREAM, ".Lskipconsts:\n"); \
995 /* store the static chain */ \
996 fprintf (STREAM, "\tl32r\ta8, .Lchainval\n"); \
997 fprintf (STREAM, "\ts32i\ta8, sp, %d\n", \
998 MIN_FRAME_SIZE - (5 * UNITS_PER_WORD)); \
1000 /* set the proper stack pointer value */ \
1001 fprintf (STREAM, "\tl32r\ta8, .Lfnaddr\n"); \
1002 fprintf (STREAM, "\tl32i\ta9, a8, 0\n"); \
1003 fprintf (STREAM, "\textui\ta9, a9, %d, 12\n", \
1004 TARGET_BIG_ENDIAN ? 8 : 12); \
1005 fprintf (STREAM, "\tslli\ta9, a9, 3\n"); \
1006 fprintf (STREAM, "\taddi\ta9, a9, %d\n", -MIN_FRAME_SIZE); \
1007 fprintf (STREAM, "\tsub\ta9, sp, a9\n"); \
1008 fprintf (STREAM, "\tmovsp\tsp, a9\n"); \
1010 /* jump to the instruction following the entry */ \
1011 fprintf (STREAM, "\taddi\ta8, a8, 3\n"); \
1012 fprintf (STREAM, "\tjx\ta8\n"); \
1013 fprintf (STREAM, "\t.end no-generics\n"); \
1016 /* Size in bytes of the trampoline, as an integer. */
1017 #define TRAMPOLINE_SIZE 49
1019 /* Alignment required for trampolines, in bits. */
1020 #define TRAMPOLINE_ALIGNMENT (32)
1022 /* A C statement to initialize the variable parts of a trampoline. */
1023 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
1026 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 8)), FUNC); \
1027 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 12)), CHAIN); \
1028 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__xtensa_sync_caches"), \
1029 0, VOIDmode, 1, addr, Pmode); \
1032 /* Define the `__builtin_va_list' type for the ABI. */
1033 #define BUILD_VA_LIST_TYPE(VALIST) \
1034 (VALIST) = xtensa_build_va_list ()
1036 /* If defined, is a C expression that produces the machine-specific
1037 code for a call to '__builtin_saveregs'. This code will be moved
1038 to the very beginning of the function, before any parameter access
1039 are made. The return value of this function should be an RTX that
1040 contains the value to use as the return of '__builtin_saveregs'. */
1041 #define EXPAND_BUILTIN_SAVEREGS \
1042 xtensa_builtin_saveregs
1044 /* Implement `va_start' for varargs and stdarg. */
1045 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
1046 xtensa_va_start (stdarg, valist, nextarg)
1048 /* Implement `va_arg'. */
1049 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1050 xtensa_va_arg (valist, type)
1052 /* If defined, a C expression that produces the machine-specific code
1053 to setup the stack so that arbitrary frames can be accessed.
1055 On Xtensa, a stack back-trace must always begin from the stack pointer,
1056 so that the register overflow save area can be located. However, the
1057 stack-walking code in GCC always begins from the hard_frame_pointer
1058 register, not the stack pointer. The frame pointer is usually equal
1059 to the stack pointer, but the __builtin_return_address and
1060 __builtin_frame_address functions will not work if count > 0 and
1061 they are called from a routine that uses alloca. These functions
1062 are not guaranteed to work at all if count > 0 so maybe that is OK.
1064 A nicer solution would be to allow the architecture-specific files to
1065 specify whether to start from the stack pointer or frame pointer. That
1066 would also allow us to skip the machine->accesses_prev_frame stuff that
1067 we currently need to ensure that there is a frame pointer when these
1068 builtin functions are used. */
1070 #define SETUP_FRAME_ADDRESSES() \
1071 xtensa_setup_frame_addresses ()
1073 /* A C expression whose value is RTL representing the address in a
1074 stack frame where the pointer to the caller's frame is stored.
1075 Assume that FRAMEADDR is an RTL expression for the address of the
1078 For Xtensa, there is no easy way to get the frame pointer if it is
1079 not equivalent to the stack pointer. Moreover, the result of this
1080 macro is used for continuing to walk back up the stack, so it must
1081 return the stack pointer address. Thus, there is some inconsistency
1082 here in that __builtin_frame_address will return the frame pointer
1083 when count == 0 and the stack pointer when count > 0. */
1085 #define DYNAMIC_CHAIN_ADDRESS(frame) \
1086 gen_rtx (PLUS, Pmode, frame, \
1087 gen_rtx_CONST_INT (VOIDmode, -3 * UNITS_PER_WORD))
1089 /* Define this if the return address of a particular stack frame is
1090 accessed from the frame pointer of the previous stack frame. */
1091 #define RETURN_ADDR_IN_PREVIOUS_FRAME
1093 /* A C expression whose value is RTL representing the value of the
1094 return address for the frame COUNT steps up from the current
1095 frame, after the prologue. FRAMEADDR is the frame pointer of the
1096 COUNT frame, or the frame pointer of the COUNT - 1 frame if
1097 'RETURN_ADDR_IN_PREVIOUS_FRAME' is defined.
1099 The 2 most-significant bits of the return address on Xtensa hold
1100 the register window size. To get the real return address, these bits
1101 must be masked off and replaced with the high bits from the current
1102 PC. Since it is unclear how the __builtin_return_address function
1103 is used, the current code does not do this masking and simply returns
1104 the raw return address from the a0 register. */
1105 #define RETURN_ADDR_RTX(count, frame) \
1107 ? gen_rtx_REG (Pmode, 0) \
1108 : gen_rtx_MEM (Pmode, memory_address \
1109 (Pmode, plus_constant (frame, -4 * UNITS_PER_WORD))))
1112 /* Addressing modes, and classification of registers for them. */
1114 /* C expressions which are nonzero if register number NUM is suitable
1115 for use as a base or index register in operand addresses. It may
1116 be either a suitable hard register or a pseudo register that has
1117 been allocated such a hard register. The difference between an
1118 index register and a base register is that the index register may
1121 #define REGNO_OK_FOR_BASE_P(NUM) \
1122 (GP_REG_P (NUM) || GP_REG_P ((unsigned) reg_renumber[NUM]))
1124 #define REGNO_OK_FOR_INDEX_P(NUM) 0
1126 /* C expressions that are nonzero if X (assumed to be a `reg' RTX) is
1127 valid for use as a base or index register. For hard registers, it
1128 should always accept those which the hardware permits and reject
1129 the others. Whether the macro accepts or rejects pseudo registers
1130 must be controlled by `REG_OK_STRICT'. This usually requires two
1131 variant definitions, of which `REG_OK_STRICT' controls the one
1132 actually used. The difference between an index register and a base
1133 register is that the index register may be scaled. */
1135 #ifdef REG_OK_STRICT
1137 #define REG_OK_FOR_INDEX_P(X) 0
1138 #define REG_OK_FOR_BASE_P(X) \
1139 REGNO_OK_FOR_BASE_P (REGNO (X))
1141 #else /* !REG_OK_STRICT */
1143 #define REG_OK_FOR_INDEX_P(X) 0
1144 #define REG_OK_FOR_BASE_P(X) \
1145 ((REGNO (X) >= FIRST_PSEUDO_REGISTER) || (GP_REG_P (REGNO (X))))
1147 #endif /* !REG_OK_STRICT */
1149 /* Maximum number of registers that can appear in a valid memory address. */
1150 #define MAX_REGS_PER_ADDRESS 1
1152 /* Identify valid Xtensa addresses. */
1153 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1157 /* allow constant pool addresses */ \
1158 if ((MODE) != BLKmode && GET_MODE_SIZE (MODE) >= UNITS_PER_WORD \
1159 && constantpool_address_p (xinsn)) \
1162 while (GET_CODE (xinsn) == SUBREG) \
1163 xinsn = SUBREG_REG (xinsn); \
1165 /* allow base registers */ \
1166 if (GET_CODE (xinsn) == REG && REG_OK_FOR_BASE_P (xinsn)) \
1169 /* check for "register + offset" addressing */ \
1170 if (GET_CODE (xinsn) == PLUS) \
1172 rtx xplus0 = XEXP (xinsn, 0); \
1173 rtx xplus1 = XEXP (xinsn, 1); \
1174 enum rtx_code code0; \
1175 enum rtx_code code1; \
1177 while (GET_CODE (xplus0) == SUBREG) \
1178 xplus0 = SUBREG_REG (xplus0); \
1179 code0 = GET_CODE (xplus0); \
1181 while (GET_CODE (xplus1) == SUBREG) \
1182 xplus1 = SUBREG_REG (xplus1); \
1183 code1 = GET_CODE (xplus1); \
1185 /* swap operands if necessary so the register is first */ \
1186 if (code0 != REG && code1 == REG) \
1188 xplus0 = XEXP (xinsn, 1); \
1189 xplus1 = XEXP (xinsn, 0); \
1190 code0 = GET_CODE (xplus0); \
1191 code1 = GET_CODE (xplus1); \
1194 if (code0 == REG && REG_OK_FOR_BASE_P (xplus0) \
1195 && code1 == CONST_INT \
1196 && xtensa_mem_offset (INTVAL (xplus1), (MODE))) \
1203 /* A C expression that is 1 if the RTX X is a constant which is a
1204 valid address. This is defined to be the same as 'CONSTANT_P (X)',
1205 but rejecting CONST_DOUBLE. */
1206 #define CONSTANT_ADDRESS_P(X) \
1207 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1208 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
1209 || (GET_CODE (X) == CONST)))
1211 /* Nonzero if the constant value X is a legitimate general operand.
1212 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1213 #define LEGITIMATE_CONSTANT_P(X) 1
1215 /* A C expression that is nonzero if X is a legitimate immediate
1216 operand on the target machine when generating position independent
1218 #define LEGITIMATE_PIC_OPERAND_P(X) \
1219 ((GET_CODE (X) != SYMBOL_REF || SYMBOL_REF_FLAG (X)) \
1220 && GET_CODE (X) != LABEL_REF \
1221 && GET_CODE (X) != CONST)
1223 /* Tell GCC how to use ADDMI to generate addresses. */
1224 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1227 if (GET_CODE (xinsn) == PLUS) \
1229 rtx plus0 = XEXP (xinsn, 0); \
1230 rtx plus1 = XEXP (xinsn, 1); \
1232 if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG) \
1234 plus0 = XEXP (xinsn, 1); \
1235 plus1 = XEXP (xinsn, 0); \
1238 if (GET_CODE (plus0) == REG \
1239 && GET_CODE (plus1) == CONST_INT \
1240 && !xtensa_mem_offset (INTVAL (plus1), MODE) \
1241 && !xtensa_simm8 (INTVAL (plus1)) \
1242 && xtensa_mem_offset (INTVAL (plus1) & 0xff, MODE) \
1243 && xtensa_simm8x256 (INTVAL (plus1) & ~0xff)) \
1245 rtx temp = gen_reg_rtx (Pmode); \
1246 emit_insn (gen_rtx (SET, Pmode, temp, \
1247 gen_rtx (PLUS, Pmode, plus0, \
1248 GEN_INT (INTVAL (plus1) & ~0xff)))); \
1249 (X) = gen_rtx (PLUS, Pmode, temp, \
1250 GEN_INT (INTVAL (plus1) & 0xff)); \
1257 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) {}
1259 /* If we are referencing a function that is static, make the SYMBOL_REF
1260 special so that we can generate direct calls to it even with -fpic. */
1261 #define ENCODE_SECTION_INFO(DECL, FIRST) \
1263 if (TREE_CODE (DECL) == FUNCTION_DECL && ! TREE_PUBLIC (DECL)) \
1264 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
1267 /* Specify the machine mode that this machine uses
1268 for the index in the tablejump instruction. */
1269 #define CASE_VECTOR_MODE (SImode)
1271 /* Define this if the tablejump instruction expects the table
1272 to contain offsets from the address of the table.
1273 Do not define this if the table should contain absolute addresses. */
1274 /* #define CASE_VECTOR_PC_RELATIVE */
1276 /* Specify the tree operation to be used to convert reals to integers. */
1277 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1279 /* This is the kind of divide that is easiest to do in the general case. */
1280 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1282 /* Define this as 1 if 'char' should by default be signed; else as 0. */
1283 #define DEFAULT_SIGNED_CHAR 0
1285 /* Max number of bytes we can move from memory to memory
1286 in one reasonably fast instruction. */
1288 #define MAX_MOVE_MAX 4
1290 /* Prefer word-sized loads. */
1291 #define SLOW_BYTE_ACCESS 1
1293 /* Xtensa doesn't have any instructions that set integer values based on the
1294 results of comparisons, but the simplification code in the combiner also
1295 uses this macro. The value should be either 1 or -1 to enable some
1296 optimizations in the combiner; I'm not sure which is better for us.
1297 Since we've been using 1 for a while, it should probably stay that way for
1299 #define STORE_FLAG_VALUE 1
1301 /* Shift instructions ignore all but the low-order few bits. */
1302 #define SHIFT_COUNT_TRUNCATED 1
1304 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1305 is done just by pretending it is already truncated. */
1306 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1308 /* Specify the machine mode that pointers have.
1309 After generation of rtl, the compiler makes no further distinction
1310 between pointers and any other objects of this machine mode. */
1311 #define Pmode SImode
1313 /* A function address in a call instruction is a word address (for
1314 indexing purposes) so give the MEM rtx a words's mode. */
1315 #define FUNCTION_MODE SImode
1317 /* A C expression that evaluates to true if it is ok to perform a
1318 sibling call to DECL. */
1319 /* TODO: fix this up to allow at least some sibcalls */
1320 #define FUNCTION_OK_FOR_SIBCALL(DECL) 0
1322 /* Xtensa constant costs. */
1323 #define CONST_COSTS(X, CODE, OUTER_CODE) \
1325 switch (OUTER_CODE) \
1328 if (xtensa_simm12b (INTVAL (X))) return 4; \
1331 if (xtensa_simm8 (INTVAL (X))) return 0; \
1332 if (xtensa_simm8x256 (INTVAL (X))) return 0; \
1335 if (xtensa_mask_immediate (INTVAL (X))) return 0; \
1338 if ((INTVAL (X) == 0) || xtensa_b4const (INTVAL (X))) return 0; \
1345 /* no way to tell if X is the 2nd operand so be conservative */ \
1348 if (xtensa_simm12b (INTVAL (X))) return 5; \
1354 case CONST_DOUBLE: \
1357 /* Costs of various Xtensa operations. */
1358 #define RTX_COSTS(X, CODE, OUTER_CODE) \
1362 (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
1363 if (memory_address_p (GET_MODE (X), XEXP ((X), 0))) \
1364 return COSTS_N_INSNS (num_words); \
1366 return COSTS_N_INSNS (2*num_words); \
1370 return COSTS_N_INSNS (TARGET_NSA ? 5 : 50); \
1373 return COSTS_N_INSNS ((GET_MODE (X) == DImode) ? 3 : 2); \
1378 if (GET_MODE (X) == DImode) return COSTS_N_INSNS (2); \
1379 return COSTS_N_INSNS (1); \
1384 if (GET_MODE (X) == DImode) return COSTS_N_INSNS (50); \
1385 return COSTS_N_INSNS (1); \
1389 enum machine_mode xmode = GET_MODE (X); \
1390 if (xmode == SFmode) \
1391 return COSTS_N_INSNS (TARGET_HARD_FLOAT ? 1 : 50); \
1392 if (xmode == DFmode) \
1393 return COSTS_N_INSNS (50); \
1394 return COSTS_N_INSNS (4); \
1400 enum machine_mode xmode = GET_MODE (X); \
1401 if (xmode == SFmode) \
1402 return COSTS_N_INSNS (TARGET_HARD_FLOAT ? 1 : 50); \
1403 if (xmode == DFmode || xmode == DImode) \
1404 return COSTS_N_INSNS (50); \
1405 return COSTS_N_INSNS (1); \
1409 return COSTS_N_INSNS ((GET_MODE (X) == DImode) ? 4 : 2); \
1413 enum machine_mode xmode = GET_MODE (X); \
1414 if (xmode == SFmode) \
1415 return COSTS_N_INSNS (TARGET_HARD_FLOAT ? 4 : 50); \
1416 if (xmode == DFmode || xmode == DImode) \
1417 return COSTS_N_INSNS (50); \
1419 return COSTS_N_INSNS (4); \
1421 return COSTS_N_INSNS (16); \
1423 return COSTS_N_INSNS (12); \
1424 return COSTS_N_INSNS (50); \
1430 enum machine_mode xmode = GET_MODE (X); \
1431 if (xmode == SFmode) \
1432 return COSTS_N_INSNS (TARGET_HARD_FLOAT_DIV ? 8 : 50); \
1433 if (xmode == DFmode) \
1434 return COSTS_N_INSNS (50); \
1436 /* fall through */ \
1441 enum machine_mode xmode = GET_MODE (X); \
1442 if (xmode == DImode) \
1443 return COSTS_N_INSNS (50); \
1445 return COSTS_N_INSNS (32); \
1446 return COSTS_N_INSNS (50); \
1450 if (GET_MODE (X) == SFmode) \
1451 return COSTS_N_INSNS (TARGET_HARD_FLOAT_SQRT ? 8 : 50); \
1452 return COSTS_N_INSNS (50); \
1458 return COSTS_N_INSNS (TARGET_MINMAX ? 1 : 50); \
1460 case SIGN_EXTRACT: \
1462 return COSTS_N_INSNS (TARGET_SEXT ? 1 : 2); \
1464 case ZERO_EXTRACT: \
1466 return COSTS_N_INSNS (1);
1469 /* An expression giving the cost of an addressing mode that
1470 contains ADDRESS. */
1471 #define ADDRESS_COST(ADDR) 1
1473 /* A C expression for the cost of moving data from a register in
1474 class FROM to one in class TO. The classes are expressed using
1475 the enumeration values such as 'GENERAL_REGS'. A value of 2 is
1476 the default; other values are interpreted relative to that. */
1477 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1478 (((FROM) == (TO) && (FROM) != BR_REGS && (TO) != BR_REGS) \
1480 : (reg_class_subset_p ((FROM), AR_REGS) \
1481 && reg_class_subset_p ((TO), AR_REGS) \
1483 : (reg_class_subset_p ((FROM), AR_REGS) \
1484 && (TO) == ACC_REG \
1486 : ((FROM) == ACC_REG \
1487 && reg_class_subset_p ((TO), AR_REGS) \
1491 #define MEMORY_MOVE_COST(MODE, CLASS, IN) 4
1493 #define BRANCH_COST 3
1495 /* Optionally define this if you have added predicates to
1496 'MACHINE.c'. This macro is called within an initializer of an
1497 array of structures. The first field in the structure is the
1498 name of a predicate and the second field is an array of rtl
1499 codes. For each predicate, list all rtl codes that can be in
1500 expressions matched by the predicate. The list should have a
1503 #define PREDICATE_CODES \
1504 {"add_operand", { REG, CONST_INT, SUBREG }}, \
1505 {"arith_operand", { REG, CONST_INT, SUBREG }}, \
1506 {"nonimmed_operand", { REG, SUBREG, MEM }}, \
1507 {"non_acc_reg_operand", { REG, SUBREG }}, \
1508 {"mem_operand", { MEM }}, \
1509 {"mask_operand", { REG, CONST_INT, SUBREG }}, \
1510 {"extui_fldsz_operand", { CONST_INT }}, \
1511 {"sext_fldsz_operand", { CONST_INT }}, \
1512 {"lsbitnum_operand", { CONST_INT }}, \
1513 {"fpmem_offset_operand", { CONST_INT }}, \
1514 {"sext_operand", { REG, SUBREG, MEM }}, \
1515 {"branch_operand", { REG, CONST_INT, SUBREG }}, \
1516 {"ubranch_operand", { REG, CONST_INT, SUBREG }}, \
1517 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG }}, \
1518 {"move_operand", { REG, SUBREG, MEM, CONST_INT, CONST_DOUBLE, \
1519 CONST, SYMBOL_REF, LABEL_REF }}, \
1520 {"non_const_move_operand", { REG, SUBREG, MEM }}, \
1521 {"const_float_1_operand", { CONST_DOUBLE }}, \
1522 {"branch_operator", { EQ, NE, LT, GE }}, \
1523 {"ubranch_operator", { LTU, GEU }}, \
1524 {"boolean_operator", { EQ, NE }},
1526 /* Control the assembler format that we output. */
1528 /* How to refer to registers in assembler output.
1529 This sequence is indexed by compiler's hard-register-number (see above). */
1530 #define REGISTER_NAMES \
1532 "a0", "sp", "a2", "a3", "a4", "a5", "a6", "a7", \
1533 "a8", "a9", "a10", "a11", "a12", "a13", "a14", "a15", \
1534 "fp", "argp", "b0", \
1535 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
1536 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
1540 /* If defined, a C initializer for an array of structures containing a
1541 name and a register number. This macro defines additional names
1542 for hard registers, thus allowing the 'asm' option in declarations
1543 to refer to registers using alternate names. */
1544 #define ADDITIONAL_REGISTER_NAMES \
1546 { "a1", 1 + GP_REG_FIRST } \
1549 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1550 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
1552 /* Recognize machine-specific patterns that may appear within
1553 constants. Used for PIC-specific UNSPECs. */
1554 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
1556 if (flag_pic && GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \
1558 switch (XINT ((X), 1)) \
1561 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
1562 fputs ("@PLT", (STREAM)); \
1574 /* This is how to output the definition of a user-level label named NAME,
1575 such as the label on a static function or variable NAME. */
1576 #define ASM_OUTPUT_LABEL(STREAM, NAME) \
1578 assemble_name (STREAM, NAME); \
1579 fputs (":\n", STREAM); \
1582 /* This is how to output a command to make the user-level label named NAME
1583 defined for reference from other files. */
1584 #define ASM_GLOBALIZE_LABEL(STREAM, NAME) \
1586 fputs ("\t.global\t", STREAM); \
1587 assemble_name (STREAM, NAME); \
1588 fputs ("\n", STREAM); \
1591 /* This says how to define a global common symbol. */
1592 #define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \
1593 xtensa_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", (SIZE))
1595 /* This says how to define a local common symbol (ie, not visible to
1597 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
1598 xtensa_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE))
1600 /* This is how to output an element of a case-vector that is absolute. */
1601 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
1602 fprintf (STREAM, "%s%sL%u\n", integer_asm_op (4, TRUE), \
1603 LOCAL_LABEL_PREFIX, VALUE)
1605 /* This is how to output an element of a case-vector that is relative.
1606 This is used for pc-relative code. */
1607 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
1609 fprintf (STREAM, "%s%sL%u-%sL%u\n", integer_asm_op (4, TRUE), \
1610 LOCAL_LABEL_PREFIX, (VALUE), \
1611 LOCAL_LABEL_PREFIX, (REL)); \
1614 /* This is how to output an assembler line that says to advance the
1615 location counter to a multiple of 2**LOG bytes. */
1616 #define ASM_OUTPUT_ALIGN(STREAM, LOG) \
1619 fprintf (STREAM, "\t.align\t%d\n", 1 << (LOG)); \
1622 /* Indicate that jump tables go in the text section. This is
1623 necessary when compiling PIC code. */
1624 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
1627 /* Define this macro for the rare case where the RTL needs some sort of
1628 machine-dependent fixup immediately before register allocation is done.
1630 If the stack frame size is too big to fit in the immediate field of
1631 the ENTRY instruction, we need to store the frame size in the
1632 constant pool. However, the code in xtensa_function_prologue runs too
1633 late to be able to add anything to the constant pool. Since the
1634 final frame size isn't known until reload is complete, this seems
1635 like the best place to do it.
1637 There may also be some fixup required if there is an incoming argument
1638 in a7 and the function requires a frame pointer. */
1640 #define MACHINE_DEPENDENT_REORG(INSN) xtensa_reorg (INSN)
1643 /* Define the strings to put out for each section in the object file. */
1644 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
1645 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
1648 /* Define output to appear before the constant pool. If the function
1649 has been assigned to a specific ELF section, or if it goes into a
1650 unique section, set the name of that section to be the literal
1652 #define ASM_OUTPUT_POOL_PROLOGUE(FILE, FUNNAME, FUNDECL, SIZE) \
1655 resolve_unique_section ((FUNDECL), 0); \
1656 fnsection = DECL_SECTION_NAME (FUNDECL); \
1657 if (fnsection != NULL_TREE) \
1659 const char *fnsectname = TREE_STRING_POINTER (fnsection); \
1660 fprintf (FILE, "\t.begin\tliteral_prefix %s\n", \
1661 strcmp (fnsectname, ".text") ? fnsectname : ""); \
1666 /* Define code to write out the ".end literal_prefix" directive for a
1667 function in a special section. This is appended to the standard ELF
1668 code for ASM_DECLARE_FUNCTION_SIZE. */
1669 #define XTENSA_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL) \
1670 if (DECL_SECTION_NAME (DECL) != NULL_TREE) \
1671 fprintf (FILE, "\t.end\tliteral_prefix\n")
1673 /* A C statement (with or without semicolon) to output a constant in
1674 the constant pool, if it needs special treatment. */
1675 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, JUMPTO) \
1677 xtensa_output_literal (FILE, X, MODE, LABELNO); \
1681 /* Store in OUTPUT a string (made with alloca) containing
1682 an assembler-name for a local static variable named NAME.
1683 LABELNO is an integer which is different for each call. */
1684 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1686 (OUTPUT) = (char *) alloca (strlen (NAME) + 10); \
1687 sprintf ((OUTPUT), "%s.%u", (NAME), (LABELNO)); \
1690 /* How to start an assembler comment. */
1691 #define ASM_COMMENT_START "#"
1693 /* Exception handling TODO!! */
1694 #define DWARF_UNWIND_INFO 0
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