1 /* Definitions of Tensilica's Xtensa target machine for GNU compiler.
2 Copyright 2001,2002,2003 Free Software Foundation, Inc.
3 Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* Get Xtensa configuration settings */
23 #include "xtensa/xtensa-config.h"
25 /* Standard GCC variables that we reference. */
26 extern int current_function_calls_alloca;
27 extern int target_flags;
30 /* External variables defined in xtensa.c. */
34 CMP_SI, /* four byte integers */
35 CMP_DI, /* eight byte integers */
36 CMP_SF, /* single precision floats */
37 CMP_DF, /* double precision floats */
38 CMP_MAX /* max comparison type */
41 extern struct rtx_def * branch_cmp[2]; /* operands for compare */
42 extern enum cmp_type branch_type; /* what type of branch to use */
43 extern unsigned xtensa_current_frame_size;
45 /* Run-time compilation parameters selecting different hardware subsets. */
47 #define MASK_BIG_ENDIAN 0x00000001 /* big or little endian */
48 #define MASK_DENSITY 0x00000002 /* code density option */
49 #define MASK_MAC16 0x00000004 /* MAC16 option */
50 #define MASK_MUL16 0x00000008 /* 16-bit integer multiply */
51 #define MASK_MUL32 0x00000010 /* integer multiply/divide */
52 #define MASK_DIV32 0x00000020 /* integer multiply/divide */
53 #define MASK_NSA 0x00000040 /* nsa instruction option */
54 #define MASK_MINMAX 0x00000080 /* min/max instructions */
55 #define MASK_SEXT 0x00000100 /* sign extend insn option */
56 #define MASK_BOOLEANS 0x00000200 /* boolean register option */
57 #define MASK_HARD_FLOAT 0x00000400 /* floating-point option */
58 #define MASK_HARD_FLOAT_DIV 0x00000800 /* floating-point divide */
59 #define MASK_HARD_FLOAT_RECIP 0x00001000 /* floating-point reciprocal */
60 #define MASK_HARD_FLOAT_SQRT 0x00002000 /* floating-point sqrt */
61 #define MASK_HARD_FLOAT_RSQRT 0x00004000 /* floating-point recip sqrt */
62 #define MASK_NO_FUSED_MADD 0x00008000 /* avoid f-p mul/add */
63 #define MASK_SERIALIZE_VOLATILE 0x00010000 /* serialize volatile refs */
65 /* Macros used in the machine description to test the flags. */
67 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
68 #define TARGET_DENSITY (target_flags & MASK_DENSITY)
69 #define TARGET_MAC16 (target_flags & MASK_MAC16)
70 #define TARGET_MUL16 (target_flags & MASK_MUL16)
71 #define TARGET_MUL32 (target_flags & MASK_MUL32)
72 #define TARGET_DIV32 (target_flags & MASK_DIV32)
73 #define TARGET_NSA (target_flags & MASK_NSA)
74 #define TARGET_MINMAX (target_flags & MASK_MINMAX)
75 #define TARGET_SEXT (target_flags & MASK_SEXT)
76 #define TARGET_BOOLEANS (target_flags & MASK_BOOLEANS)
77 #define TARGET_HARD_FLOAT (target_flags & MASK_HARD_FLOAT)
78 #define TARGET_HARD_FLOAT_DIV (target_flags & MASK_HARD_FLOAT_DIV)
79 #define TARGET_HARD_FLOAT_RECIP (target_flags & MASK_HARD_FLOAT_RECIP)
80 #define TARGET_HARD_FLOAT_SQRT (target_flags & MASK_HARD_FLOAT_SQRT)
81 #define TARGET_HARD_FLOAT_RSQRT (target_flags & MASK_HARD_FLOAT_RSQRT)
82 #define TARGET_NO_FUSED_MADD (target_flags & MASK_NO_FUSED_MADD)
83 #define TARGET_SERIALIZE_VOLATILE (target_flags & MASK_SERIALIZE_VOLATILE)
85 /* Default target_flags if no switches are specified */
87 #define TARGET_DEFAULT ( \
88 (XCHAL_HAVE_BE ? MASK_BIG_ENDIAN : 0) | \
89 (XCHAL_HAVE_DENSITY ? MASK_DENSITY : 0) | \
90 (XCHAL_HAVE_MAC16 ? MASK_MAC16 : 0) | \
91 (XCHAL_HAVE_MUL16 ? MASK_MUL16 : 0) | \
92 (XCHAL_HAVE_MUL32 ? MASK_MUL32 : 0) | \
93 (XCHAL_HAVE_DIV32 ? MASK_DIV32 : 0) | \
94 (XCHAL_HAVE_NSA ? MASK_NSA : 0) | \
95 (XCHAL_HAVE_MINMAX ? MASK_MINMAX : 0) | \
96 (XCHAL_HAVE_SEXT ? MASK_SEXT : 0) | \
97 (XCHAL_HAVE_BOOLEANS ? MASK_BOOLEANS : 0) | \
98 (XCHAL_HAVE_FP ? MASK_HARD_FLOAT : 0) | \
99 (XCHAL_HAVE_FP_DIV ? MASK_HARD_FLOAT_DIV : 0) | \
100 (XCHAL_HAVE_FP_RECIP ? MASK_HARD_FLOAT_RECIP : 0) | \
101 (XCHAL_HAVE_FP_SQRT ? MASK_HARD_FLOAT_SQRT : 0) | \
102 (XCHAL_HAVE_FP_RSQRT ? MASK_HARD_FLOAT_RSQRT : 0) | \
103 MASK_SERIALIZE_VOLATILE)
105 /* Macro to define tables used to set the flags. */
107 #define TARGET_SWITCHES \
109 {"big-endian", MASK_BIG_ENDIAN, \
110 N_("Use big-endian byte order")}, \
111 {"little-endian", -MASK_BIG_ENDIAN, \
112 N_("Use little-endian byte order")}, \
113 {"density", MASK_DENSITY, \
114 N_("Use the Xtensa code density option")}, \
115 {"no-density", -MASK_DENSITY, \
116 N_("Do not use the Xtensa code density option")}, \
117 {"mac16", MASK_MAC16, \
118 N_("Use the Xtensa MAC16 option")}, \
119 {"no-mac16", -MASK_MAC16, \
120 N_("Do not use the Xtensa MAC16 option")}, \
121 {"mul16", MASK_MUL16, \
122 N_("Use the Xtensa MUL16 option")}, \
123 {"no-mul16", -MASK_MUL16, \
124 N_("Do not use the Xtensa MUL16 option")}, \
125 {"mul32", MASK_MUL32, \
126 N_("Use the Xtensa MUL32 option")}, \
127 {"no-mul32", -MASK_MUL32, \
128 N_("Do not use the Xtensa MUL32 option")}, \
129 {"div32", MASK_DIV32, \
130 0 /* undocumented */}, \
131 {"no-div32", -MASK_DIV32, \
132 0 /* undocumented */}, \
134 N_("Use the Xtensa NSA option")}, \
135 {"no-nsa", -MASK_NSA, \
136 N_("Do not use the Xtensa NSA option")}, \
137 {"minmax", MASK_MINMAX, \
138 N_("Use the Xtensa MIN/MAX option")}, \
139 {"no-minmax", -MASK_MINMAX, \
140 N_("Do not use the Xtensa MIN/MAX option")}, \
141 {"sext", MASK_SEXT, \
142 N_("Use the Xtensa SEXT option")}, \
143 {"no-sext", -MASK_SEXT, \
144 N_("Do not use the Xtensa SEXT option")}, \
145 {"booleans", MASK_BOOLEANS, \
146 N_("Use the Xtensa boolean register option")}, \
147 {"no-booleans", -MASK_BOOLEANS, \
148 N_("Do not use the Xtensa boolean register option")}, \
149 {"hard-float", MASK_HARD_FLOAT, \
150 N_("Use the Xtensa floating-point unit")}, \
151 {"soft-float", -MASK_HARD_FLOAT, \
152 N_("Do not use the Xtensa floating-point unit")}, \
153 {"hard-float-div", MASK_HARD_FLOAT_DIV, \
154 0 /* undocumented */}, \
155 {"no-hard-float-div", -MASK_HARD_FLOAT_DIV, \
156 0 /* undocumented */}, \
157 {"hard-float-recip", MASK_HARD_FLOAT_RECIP, \
158 0 /* undocumented */}, \
159 {"no-hard-float-recip", -MASK_HARD_FLOAT_RECIP, \
160 0 /* undocumented */}, \
161 {"hard-float-sqrt", MASK_HARD_FLOAT_SQRT, \
162 0 /* undocumented */}, \
163 {"no-hard-float-sqrt", -MASK_HARD_FLOAT_SQRT, \
164 0 /* undocumented */}, \
165 {"hard-float-rsqrt", MASK_HARD_FLOAT_RSQRT, \
166 0 /* undocumented */}, \
167 {"no-hard-float-rsqrt", -MASK_HARD_FLOAT_RSQRT, \
168 0 /* undocumented */}, \
169 {"no-fused-madd", MASK_NO_FUSED_MADD, \
170 N_("Disable fused multiply/add and multiply/subtract FP instructions")}, \
171 {"fused-madd", -MASK_NO_FUSED_MADD, \
172 N_("Enable fused multiply/add and multiply/subtract FP instructions")}, \
173 {"serialize-volatile", MASK_SERIALIZE_VOLATILE, \
174 N_("Serialize volatile memory references with MEMW instructions")}, \
175 {"no-serialize-volatile", -MASK_SERIALIZE_VOLATILE, \
176 N_("Do not serialize volatile memory references with MEMW instructions")},\
177 {"text-section-literals", 0, \
178 N_("Intersperse literal pools with code in the text section")}, \
179 {"no-text-section-literals", 0, \
180 N_("Put literal pools in a separate literal section")}, \
181 {"target-align", 0, \
182 N_("Automatically align branch targets to reduce branch penalties")}, \
183 {"no-target-align", 0, \
184 N_("Do not automatically align branch targets")}, \
186 N_("Use indirect CALLXn instructions for large programs")}, \
187 {"no-longcalls", 0, \
188 N_("Use direct CALLn instructions for fast calls")}, \
189 {"", TARGET_DEFAULT, 0} \
193 #define OVERRIDE_OPTIONS override_options ()
195 /* Target CPU builtins. */
196 #define TARGET_CPU_CPP_BUILTINS() \
198 builtin_assert ("cpu=xtensa"); \
199 builtin_assert ("machine=xtensa"); \
200 builtin_define ("__XTENSA__"); \
201 builtin_define (TARGET_BIG_ENDIAN ? "__XTENSA_EB__" : "__XTENSA_EL__"); \
202 if (!TARGET_HARD_FLOAT) \
203 builtin_define ("__XTENSA_SOFT_FLOAT__"); \
206 builtin_define ("__PIC__"); \
207 builtin_define ("__pic__"); \
211 #define CPP_SPEC " %(subtarget_cpp_spec) "
213 #ifndef SUBTARGET_CPP_SPEC
214 #define SUBTARGET_CPP_SPEC ""
217 #define EXTRA_SPECS \
218 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC },
221 #define LIBGCC2_WORDS_BIG_ENDIAN 1
223 #define LIBGCC2_WORDS_BIG_ENDIAN 0
226 /* Show we can debug even without a frame pointer. */
227 #define CAN_DEBUG_WITHOUT_FP
230 /* Target machine storage layout */
232 /* Define this if most significant bit is lowest numbered
233 in instructions that operate on numbered bit-fields. */
234 #define BITS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
236 /* Define this if most significant byte of a word is the lowest numbered. */
237 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
239 /* Define this if most significant word of a multiword number is the lowest. */
240 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
242 #define MAX_BITS_PER_WORD 32
244 /* Width of a word, in units (bytes). */
245 #define UNITS_PER_WORD 4
246 #define MIN_UNITS_PER_WORD 4
248 /* Width of a floating point register. */
249 #define UNITS_PER_FPREG 4
251 /* Size in bits of various types on the target machine. */
252 #define INT_TYPE_SIZE 32
253 #define SHORT_TYPE_SIZE 16
254 #define LONG_TYPE_SIZE 32
255 #define MAX_LONG_TYPE_SIZE 32
256 #define LONG_LONG_TYPE_SIZE 64
257 #define FLOAT_TYPE_SIZE 32
258 #define DOUBLE_TYPE_SIZE 64
259 #define LONG_DOUBLE_TYPE_SIZE 64
261 /* Allocation boundary (in *bits*) for storing pointers in memory. */
262 #define POINTER_BOUNDARY 32
264 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
265 #define PARM_BOUNDARY 32
267 /* Allocation boundary (in *bits*) for the code of a function. */
268 #define FUNCTION_BOUNDARY 32
270 /* Alignment of field after 'int : 0' in a structure. */
271 #define EMPTY_FIELD_BOUNDARY 32
273 /* Every structure's size must be a multiple of this. */
274 #define STRUCTURE_SIZE_BOUNDARY 8
276 /* There is no point aligning anything to a rounder boundary than this. */
277 #define BIGGEST_ALIGNMENT 128
279 /* Set this nonzero if move instructions will actually fail to work
280 when given unaligned data. */
281 #define STRICT_ALIGNMENT 1
283 /* Promote integer modes smaller than a word to SImode. Set UNSIGNEDP
284 for QImode, because there is no 8-bit load from memory with sign
285 extension. Otherwise, leave UNSIGNEDP alone, since Xtensa has 16-bit
286 loads both with and without sign extension. */
287 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
289 if (GET_MODE_CLASS (MODE) == MODE_INT \
290 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
292 if ((MODE) == QImode) \
298 /* The promotion described by `PROMOTE_MODE' should also be done for
299 outgoing function arguments. */
300 #define PROMOTE_FUNCTION_ARGS
302 /* The promotion described by `PROMOTE_MODE' should also be done for
303 the return value of functions. Note: `FUNCTION_VALUE' must perform
304 the same promotions done by `PROMOTE_MODE'. */
305 #define PROMOTE_FUNCTION_RETURN
307 /* Imitate the way many other C compilers handle alignment of
308 bitfields and the structures that contain them. */
309 #define PCC_BITFIELD_TYPE_MATTERS 1
311 /* Align string constants and constructors to at least a word boundary.
312 The typical use of this macro is to increase alignment for string
313 constants to be word aligned so that 'strcpy' calls that copy
314 constants can be done inline. */
315 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
316 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
317 && (ALIGN) < BITS_PER_WORD \
321 /* Align arrays, unions and records to at least a word boundary.
322 One use of this macro is to increase alignment of medium-size
323 data to make it all fit in fewer cache lines. Another is to
324 cause character arrays to be word-aligned so that 'strcpy' calls
325 that copy constants to character arrays can be done inline. */
326 #undef DATA_ALIGNMENT
327 #define DATA_ALIGNMENT(TYPE, ALIGN) \
328 ((((ALIGN) < BITS_PER_WORD) \
329 && (TREE_CODE (TYPE) == ARRAY_TYPE \
330 || TREE_CODE (TYPE) == UNION_TYPE \
331 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
333 /* An argument declared as 'char' or 'short' in a prototype should
334 actually be passed as an 'int'. */
335 #define PROMOTE_PROTOTYPES 1
337 /* Operations between registers always perform the operation
338 on the full register even if a narrower mode is specified. */
339 #define WORD_REGISTER_OPERATIONS
341 /* Xtensa loads are zero-extended by default. */
342 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
344 /* Standard register usage. */
346 /* Number of actual hardware registers.
347 The hardware registers are assigned numbers for the compiler
348 from 0 to just below FIRST_PSEUDO_REGISTER.
349 All registers that the compiler knows about must be given numbers,
350 even those that are not normally considered general registers.
352 The fake frame pointer and argument pointer will never appear in
353 the generated code, since they will always be eliminated and replaced
354 by either the stack pointer or the hard frame pointer.
356 0 - 15 AR[0] - AR[15]
357 16 FRAME_POINTER (fake = initial sp)
358 17 ARG_POINTER (fake = initial sp + framesize)
359 18 BR[0] for floating-point CC
360 19 - 34 FR[0] - FR[15]
361 35 MAC16 accumulator */
363 #define FIRST_PSEUDO_REGISTER 36
365 /* Return the stabs register number to use for REGNO. */
366 #define DBX_REGISTER_NUMBER(REGNO) xtensa_dbx_register_number (REGNO)
368 /* 1 for registers that have pervasive standard uses
369 and are not available for the register allocator. */
370 #define FIXED_REGISTERS \
372 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
374 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
378 /* 1 for registers not available across function calls.
379 These must include the FIXED_REGISTERS and also any
380 registers that can be used without being saved.
381 The latter must include the registers where values are returned
382 and the register where structure-value addresses are passed.
383 Aside from that, you can include as many other registers as you like. */
384 #define CALL_USED_REGISTERS \
386 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
388 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
392 /* For non-leaf procedures on Xtensa processors, the allocation order
393 is as specified below by REG_ALLOC_ORDER. For leaf procedures, we
394 want to use the lowest numbered registers first to minimize
395 register window overflows. However, local-alloc is not smart
396 enough to consider conflicts with incoming arguments. If an
397 incoming argument in a2 is live throughout the function and
398 local-alloc decides to use a2, then the incoming argument must
399 either be spilled or copied to another register. To get around
400 this, we define ORDER_REGS_FOR_LOCAL_ALLOC to redefine
401 reg_alloc_order for leaf functions such that lowest numbered
402 registers are used first with the exception that the incoming
403 argument registers are not used until after other register choices
404 have been exhausted. */
406 #define REG_ALLOC_ORDER \
407 { 8, 9, 10, 11, 12, 13, 14, 15, 7, 6, 5, 4, 3, 2, \
409 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, \
414 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
416 /* For Xtensa, the only point of this is to prevent GCC from otherwise
417 giving preference to call-used registers. To minimize window
418 overflows for the AR registers, we want to give preference to the
419 lower-numbered AR registers. For other register files, which are
420 not windowed, we still prefer call-used registers, if there are any. */
421 extern const char xtensa_leaf_regs[FIRST_PSEUDO_REGISTER];
422 #define LEAF_REGISTERS xtensa_leaf_regs
424 /* For Xtensa, no remapping is necessary, but this macro must be
425 defined if LEAF_REGISTERS is defined. */
426 #define LEAF_REG_REMAP(REGNO) (REGNO)
428 /* this must be declared if LEAF_REGISTERS is set */
429 extern int leaf_function;
431 /* Internal macros to classify a register number. */
433 /* 16 address registers + fake registers */
434 #define GP_REG_FIRST 0
435 #define GP_REG_LAST 17
436 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
438 /* Coprocessor registers */
439 #define BR_REG_FIRST 18
440 #define BR_REG_LAST 18
441 #define BR_REG_NUM (BR_REG_LAST - BR_REG_FIRST + 1)
443 /* 16 floating-point registers */
444 #define FP_REG_FIRST 19
445 #define FP_REG_LAST 34
446 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
448 /* MAC16 accumulator */
449 #define ACC_REG_FIRST 35
450 #define ACC_REG_LAST 35
451 #define ACC_REG_NUM (ACC_REG_LAST - ACC_REG_FIRST + 1)
453 #define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM)
454 #define BR_REG_P(REGNO) ((unsigned) ((REGNO) - BR_REG_FIRST) < BR_REG_NUM)
455 #define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM)
456 #define ACC_REG_P(REGNO) ((unsigned) ((REGNO) - ACC_REG_FIRST) < ACC_REG_NUM)
458 /* Return number of consecutive hard regs needed starting at reg REGNO
459 to hold something of mode MODE. */
460 #define HARD_REGNO_NREGS(REGNO, MODE) \
461 (FP_REG_P (REGNO) ? \
462 ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG) : \
463 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
465 /* Value is 1 if hard register REGNO can hold a value of machine-mode
467 extern char xtensa_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
469 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
470 xtensa_hard_regno_mode_ok[(int) (MODE)][(REGNO)]
472 /* Value is 1 if it is a good idea to tie two pseudo registers
473 when one has mode MODE1 and one has mode MODE2.
474 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
475 for any hard reg, then this must be 0 for correct output. */
476 #define MODES_TIEABLE_P(MODE1, MODE2) \
477 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
478 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
479 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
480 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
482 /* Register to use for pushing function arguments. */
483 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 1)
485 /* Base register for access to local variables of the function. */
486 #define HARD_FRAME_POINTER_REGNUM (GP_REG_FIRST + 7)
488 /* The register number of the frame pointer register, which is used to
489 access automatic variables in the stack frame. For Xtensa, this
490 register never appears in the output. It is always eliminated to
491 either the stack pointer or the hard frame pointer. */
492 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 16)
494 /* Value should be nonzero if functions must have frame pointers.
495 Zero means the frame pointer need not be set up (and parms
496 may be accessed via the stack pointer) in functions that seem suitable.
497 This is computed in 'reload', in reload1.c. */
498 #define FRAME_POINTER_REQUIRED xtensa_frame_pointer_required ()
500 /* Base register for access to arguments of the function. */
501 #define ARG_POINTER_REGNUM (GP_REG_FIRST + 17)
503 /* If the static chain is passed in memory, these macros provide rtx
504 giving 'mem' expressions that denote where they are stored.
505 'STATIC_CHAIN' and 'STATIC_CHAIN_INCOMING' give the locations as
506 seen by the calling and called functions, respectively. */
508 #define STATIC_CHAIN \
509 gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, -5 * UNITS_PER_WORD))
511 #define STATIC_CHAIN_INCOMING \
512 gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -5 * UNITS_PER_WORD))
514 /* For now we don't try to use the full set of boolean registers. Without
515 software pipelining of FP operations, there's not much to gain and it's
516 a real pain to get them reloaded. */
517 #define FPCC_REGNUM (BR_REG_FIRST + 0)
519 /* Pass structure value address as an "invisible" first argument. */
520 #define STRUCT_VALUE 0
522 /* It is as good or better to call a constant function address than to
523 call an address kept in a register. */
524 #define NO_FUNCTION_CSE 1
526 /* It is as good or better for a function to call itself with an
527 explicit address than to call an address kept in a register. */
528 #define NO_RECURSIVE_FUNCTION_CSE 1
530 /* Xtensa processors have "register windows". GCC does not currently
531 take advantage of the possibility for variable-sized windows; instead,
532 we use a fixed window size of 8. */
534 #define INCOMING_REGNO(OUT) \
535 ((GP_REG_P (OUT) && \
536 ((unsigned) ((OUT) - GP_REG_FIRST) >= WINDOW_SIZE)) ? \
537 (OUT) - WINDOW_SIZE : (OUT))
539 #define OUTGOING_REGNO(IN) \
541 ((unsigned) ((IN) - GP_REG_FIRST) < WINDOW_SIZE)) ? \
542 (IN) + WINDOW_SIZE : (IN))
545 /* Define the classes of registers for register constraints in the
546 machine description. */
549 NO_REGS, /* no registers in set */
550 BR_REGS, /* coprocessor boolean registers */
551 FP_REGS, /* floating point registers */
552 ACC_REG, /* MAC16 accumulator */
553 SP_REG, /* sp register (aka a1) */
554 RL_REGS, /* preferred reload regs (not sp or fp) */
555 GR_REGS, /* integer registers except sp */
556 AR_REGS, /* all integer registers */
557 ALL_REGS, /* all registers */
558 LIM_REG_CLASSES /* max value + 1 */
561 #define N_REG_CLASSES (int) LIM_REG_CLASSES
563 #define GENERAL_REGS AR_REGS
565 /* An initializer containing the names of the register classes as C
566 string constants. These names are used in writing some of the
568 #define REG_CLASS_NAMES \
581 /* Contents of the register classes. The Nth integer specifies the
582 contents of class N. The way the integer MASK is interpreted is
583 that register R is in the class if 'MASK & (1 << R)' is 1. */
584 #define REG_CLASS_CONTENTS \
586 { 0x00000000, 0x00000000 }, /* no registers */ \
587 { 0x00040000, 0x00000000 }, /* coprocessor boolean registers */ \
588 { 0xfff80000, 0x00000007 }, /* floating-point registers */ \
589 { 0x00000000, 0x00000008 }, /* MAC16 accumulator */ \
590 { 0x00000002, 0x00000000 }, /* stack pointer register */ \
591 { 0x0000ff7d, 0x00000000 }, /* preferred reload registers */ \
592 { 0x0000fffd, 0x00000000 }, /* general-purpose registers */ \
593 { 0x0003ffff, 0x00000000 }, /* integer registers */ \
594 { 0xffffffff, 0x0000000f } /* all registers */ \
597 /* A C expression whose value is a register class containing hard
598 register REGNO. In general there is more that one such class;
599 choose a class which is "minimal", meaning that no smaller class
600 also contains the register. */
601 extern const enum reg_class xtensa_regno_to_class[FIRST_PSEUDO_REGISTER];
603 #define REGNO_REG_CLASS(REGNO) xtensa_regno_to_class[ (REGNO) ]
605 /* Use the Xtensa AR register file for base registers.
606 No index registers. */
607 #define BASE_REG_CLASS AR_REGS
608 #define INDEX_REG_CLASS NO_REGS
610 /* SMALL_REGISTER_CLASSES is required for Xtensa, because all of the
611 16 AR registers may be explicitly used in the RTL, as either
612 incoming or outgoing arguments. */
613 #define SMALL_REGISTER_CLASSES 1
616 /* REGISTER AND CONSTANT CLASSES */
618 /* Get reg_class from a letter such as appears in the machine
621 Available letters: a-f,h,j-l,q,t-z,A-D,W,Y-Z
623 DEFINED REGISTER CLASSES:
625 'a' general-purpose registers except sp
627 'D' general-purpose registers (only if density option enabled)
628 'd' general-purpose registers, including sp (only if density enabled)
629 'A' MAC16 accumulator (only if MAC16 option enabled)
630 'B' general-purpose registers (only if sext instruction enabled)
631 'C' general-purpose registers (only if mul16 option enabled)
632 'b' coprocessor boolean registers
633 'f' floating-point registers
636 extern enum reg_class xtensa_char_to_class[256];
638 #define REG_CLASS_FROM_LETTER(C) xtensa_char_to_class[ (int) (C) ]
640 /* The letters I, J, K, L, M, N, O, and P in a register constraint
641 string can be used to stand for particular ranges of immediate
642 operands. This macro defines what the ranges are. C is the
643 letter, and VALUE is a constant value. Return 1 if VALUE is
644 in the range specified by C.
648 I = 12-bit signed immediate for movi
649 J = 8-bit signed immediate for addi
650 K = 4-bit value in (b4const U {0})
651 L = 4-bit value in b4constu
652 M = 7-bit value in simm7
653 N = 8-bit unsigned immediate shifted left by 8 bits for addmi
654 O = 4-bit value in ai4const
655 P = valid immediate mask value for extui */
657 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
658 ((C) == 'I' ? (xtensa_simm12b (VALUE)) \
659 : (C) == 'J' ? (xtensa_simm8 (VALUE)) \
660 : (C) == 'K' ? (((VALUE) == 0) || xtensa_b4const (VALUE)) \
661 : (C) == 'L' ? (xtensa_b4constu (VALUE)) \
662 : (C) == 'M' ? (xtensa_simm7 (VALUE)) \
663 : (C) == 'N' ? (xtensa_simm8x256 (VALUE)) \
664 : (C) == 'O' ? (xtensa_ai4const (VALUE)) \
665 : (C) == 'P' ? (xtensa_mask_immediate (VALUE)) \
669 /* Similar, but for floating constants, and defining letters G and H.
670 Here VALUE is the CONST_DOUBLE rtx itself. */
671 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) (0)
674 /* Other letters can be defined in a machine-dependent fashion to
675 stand for particular classes of registers or other arbitrary
678 R = memory that can be accessed with a 4-bit unsigned offset
679 S = memory where the second word can be addressed with a 4-bit offset
680 T = memory in a constant pool (addressable with a pc-relative load)
681 U = memory *NOT* in a constant pool
683 The offset range should not be checked here (except to distinguish
684 denser versions of the instructions for which more general versions
685 are available). Doing so leads to problems in reloading: an
686 argptr-relative address may become invalid when the phony argptr is
687 eliminated in favor of the stack pointer (the offset becomes too
688 large to fit in the instruction's immediate field); a reload is
689 generated to fix this but the RTL is not immediately updated; in
690 the meantime, the constraints are checked and none match. The
691 solution seems to be to simply skip the offset check here. The
692 address will be checked anyway because of the code in
693 GO_IF_LEGITIMATE_ADDRESS. */
695 #define EXTRA_CONSTRAINT(OP, CODE) \
696 ((GET_CODE (OP) != MEM) ? \
697 ((CODE) >= 'R' && (CODE) <= 'U' \
698 && reload_in_progress && GET_CODE (OP) == REG \
699 && REGNO (OP) >= FIRST_PSEUDO_REGISTER) \
700 : ((CODE) == 'R') ? smalloffset_mem_p (OP) \
701 : ((CODE) == 'S') ? smalloffset_double_mem_p (OP) \
702 : ((CODE) == 'T') ? constantpool_mem_p (OP) \
703 : ((CODE) == 'U') ? !constantpool_mem_p (OP) \
706 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
707 xtensa_preferred_reload_class (X, CLASS, 0)
709 #define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \
710 xtensa_preferred_reload_class (X, CLASS, 1)
712 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
713 xtensa_secondary_reload_class (CLASS, MODE, X, 0)
715 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
716 xtensa_secondary_reload_class (CLASS, MODE, X, 1)
718 /* Return the maximum number of consecutive registers
719 needed to represent mode MODE in a register of class CLASS. */
720 #define CLASS_UNITS(mode, size) \
721 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
723 #define CLASS_MAX_NREGS(CLASS, MODE) \
724 (CLASS_UNITS (MODE, UNITS_PER_WORD))
727 /* Stack layout; function entry, exit and calling. */
729 #define STACK_GROWS_DOWNWARD
731 /* Offset within stack frame to start allocating local variables at. */
732 #define STARTING_FRAME_OFFSET \
733 current_function_outgoing_args_size
735 /* The ARG_POINTER and FRAME_POINTER are not real Xtensa registers, so
736 they are eliminated to either the stack pointer or hard frame pointer. */
737 #define ELIMINABLE_REGS \
738 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
739 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
740 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
741 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
743 #define CAN_ELIMINATE(FROM, TO) 1
745 /* Specify the initial difference between the specified pair of registers. */
746 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
748 compute_frame_size (get_frame_size ()); \
749 if ((FROM) == FRAME_POINTER_REGNUM) \
751 else if ((FROM) == ARG_POINTER_REGNUM) \
752 (OFFSET) = xtensa_current_frame_size; \
757 /* If defined, the maximum amount of space required for outgoing
758 arguments will be computed and placed into the variable
759 'current_function_outgoing_args_size'. No space will be pushed
760 onto the stack for each call; instead, the function prologue
761 should increase the stack frame size by this amount. */
762 #define ACCUMULATE_OUTGOING_ARGS 1
764 /* Offset from the argument pointer register to the first argument's
765 address. On some machines it may depend on the data type of the
766 function. If 'ARGS_GROW_DOWNWARD', this is the offset to the
767 location above the first argument's address. */
768 #define FIRST_PARM_OFFSET(FNDECL) 0
770 /* Align stack frames on 128 bits for Xtensa. This is necessary for
771 128-bit datatypes defined in TIE (e.g., for Vectra). */
772 #define STACK_BOUNDARY 128
774 /* Functions do not pop arguments off the stack. */
775 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
777 /* Use a fixed register window size of 8. */
778 #define WINDOW_SIZE 8
780 /* Symbolic macros for the registers used to return integer, floating
781 point, and values of coprocessor and user-defined modes. */
782 #define GP_RETURN (GP_REG_FIRST + 2 + WINDOW_SIZE)
783 #define GP_OUTGOING_RETURN (GP_REG_FIRST + 2)
785 /* Symbolic macros for the first/last argument registers. */
786 #define GP_ARG_FIRST (GP_REG_FIRST + 2)
787 #define GP_ARG_LAST (GP_REG_FIRST + 7)
788 #define GP_OUTGOING_ARG_FIRST (GP_REG_FIRST + 2 + WINDOW_SIZE)
789 #define GP_OUTGOING_ARG_LAST (GP_REG_FIRST + 7 + WINDOW_SIZE)
791 #define MAX_ARGS_IN_REGISTERS 6
793 /* Don't worry about compatibility with PCC. */
794 #define DEFAULT_PCC_STRUCT_RETURN 0
796 /* For Xtensa, up to 4 words can be returned in registers. (It would
797 have been nice to allow up to 6 words in registers but GCC cannot
798 support that. The return value must be given one of the standard
799 MODE_INT modes, and there is no 6 word mode. Instead, if we try to
800 return a 6 word structure, GCC selects the next biggest mode
801 (OImode, 8 words) and then the register allocator fails because
802 there is no 8-register group beginning with a10.) */
803 #define RETURN_IN_MEMORY(TYPE) \
804 ((unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) > 4 * UNITS_PER_WORD)
806 /* Define how to find the value returned by a library function
807 assuming the value has mode MODE. Because we have defined
808 PROMOTE_FUNCTION_RETURN, we have to perform the same promotions as
810 #define XTENSA_LIBCALL_VALUE(MODE, OUTGOINGP) \
811 gen_rtx_REG ((GET_MODE_CLASS (MODE) == MODE_INT \
812 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
814 OUTGOINGP ? GP_OUTGOING_RETURN : GP_RETURN)
816 #define LIBCALL_VALUE(MODE) \
817 XTENSA_LIBCALL_VALUE ((MODE), 0)
819 #define LIBCALL_OUTGOING_VALUE(MODE) \
820 XTENSA_LIBCALL_VALUE ((MODE), 1)
822 /* Define how to find the value returned by a function.
823 VALTYPE is the data type of the value (as a tree).
824 If the precise function being called is known, FUNC is its FUNCTION_DECL;
825 otherwise, FUNC is 0. */
826 #define XTENSA_FUNCTION_VALUE(VALTYPE, FUNC, OUTGOINGP) \
827 gen_rtx_REG ((INTEGRAL_TYPE_P (VALTYPE) \
828 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
829 ? SImode: TYPE_MODE (VALTYPE), \
830 OUTGOINGP ? GP_OUTGOING_RETURN : GP_RETURN)
832 #define FUNCTION_VALUE(VALTYPE, FUNC) \
833 XTENSA_FUNCTION_VALUE (VALTYPE, FUNC, 0)
835 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
836 XTENSA_FUNCTION_VALUE (VALTYPE, FUNC, 1)
838 /* A C expression that is nonzero if REGNO is the number of a hard
839 register in which the values of called function may come back. A
840 register whose use for returning values is limited to serving as
841 the second of a pair (for a value of type 'double', say) need not
842 be recognized by this macro. If the machine has register windows,
843 so that the caller and the called function use different registers
844 for the return value, this macro should recognize only the caller's
846 #define FUNCTION_VALUE_REGNO_P(N) \
849 /* A C expression that is nonzero if REGNO is the number of a hard
850 register in which function arguments are sometimes passed. This
851 does *not* include implicit arguments such as the static chain and
852 the structure-value address. On many machines, no registers can be
853 used for this purpose since all function arguments are pushed on
855 #define FUNCTION_ARG_REGNO_P(N) \
856 ((N) >= GP_OUTGOING_ARG_FIRST && (N) <= GP_OUTGOING_ARG_LAST)
858 /* Define a data type for recording info about an argument list
859 during the scan of that argument list. This data type should
860 hold all necessary information about the function itself
861 and about the args processed so far, enough to enable macros
862 such as FUNCTION_ARG to determine where the next arg should go. */
863 typedef struct xtensa_args {
864 int arg_words; /* # total words the arguments take */
867 /* Initialize a variable CUM of type CUMULATIVE_ARGS
868 for a call to a function whose data type is FNTYPE.
869 For a library call, FNTYPE is 0. */
870 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
871 init_cumulative_args (&CUM, FNTYPE, LIBNAME)
873 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
874 init_cumulative_args (&CUM, FNTYPE, LIBNAME)
876 /* Update the data in CUM to advance over an argument
877 of mode MODE and data type TYPE.
878 (TYPE is null for libcalls where that information may not be available.) */
879 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
880 function_arg_advance (&CUM, MODE, TYPE)
882 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
883 function_arg (&CUM, MODE, TYPE, FALSE)
885 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
886 function_arg (&CUM, MODE, TYPE, TRUE)
888 /* Arguments are never passed partly in memory and partly in registers. */
889 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) (0)
891 /* Specify function argument alignment. */
892 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
894 ? (TYPE_ALIGN (TYPE) <= PARM_BOUNDARY \
896 : TYPE_ALIGN (TYPE)) \
897 : (GET_MODE_ALIGNMENT (MODE) <= PARM_BOUNDARY \
899 : GET_MODE_ALIGNMENT (MODE)))
902 /* Nonzero if we do not know how to pass TYPE solely in registers.
903 We cannot do so in the following cases:
905 - if the type has variable size
906 - if the type is marked as addressable (it is required to be constructed
909 This differs from the default in that it does not check if the padding
910 and mode of the type are such that a copy into a register would put it
911 into the wrong part of the register. */
913 #define MUST_PASS_IN_STACK(MODE, TYPE) \
915 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
916 || TREE_ADDRESSABLE (TYPE)))
918 /* Profiling Xtensa code is typically done with the built-in profiling
919 feature of Tensilica's instruction set simulator, which does not
920 require any compiler support. Profiling code on a real (i.e.,
921 non-simulated) Xtensa processor is currently only supported by
922 GNU/Linux with glibc. The glibc version of _mcount doesn't require
923 counter variables. The _mcount function needs the current PC and
924 the current return address to identify an arc in the call graph.
925 Pass the current return address as the first argument; the current
926 PC is available as a0 in _mcount's register window. Both of these
927 values contain window size information in the two most significant
928 bits; we assume that _mcount will mask off those bits. The call to
929 _mcount uses a window size of 8 to make sure that it doesn't clobber
930 any incoming argument values. */
932 #define NO_PROFILE_COUNTERS
934 #define FUNCTION_PROFILER(FILE, LABELNO) \
936 fprintf (FILE, "\t%s\ta10, a0\n", TARGET_DENSITY ? "mov.n" : "mov"); \
939 fprintf (FILE, "\tmovi\ta8, _mcount@PLT\n"); \
940 fprintf (FILE, "\tcallx8\ta8\n"); \
943 fprintf (FILE, "\tcall8\t_mcount\n"); \
946 /* Stack pointer value doesn't matter at exit. */
947 #define EXIT_IGNORE_STACK 1
949 /* A C statement to output, on the stream FILE, assembler code for a
950 block of data that contains the constant parts of a trampoline.
951 This code should not include a label--the label is taken care of
954 For Xtensa, the trampoline must perform an entry instruction with a
955 minimal stack frame in order to get some free registers. Once the
956 actual call target is known, the proper stack frame size is extracted
957 from the entry instruction at the target and the current frame is
958 adjusted to match. The trampoline then transfers control to the
959 instruction following the entry at the target. Note: this assumes
960 that the target begins with an entry instruction. */
962 /* minimum frame = reg save area (4 words) plus static chain (1 word)
963 and the total number of words must be a multiple of 128 bits */
964 #define MIN_FRAME_SIZE (8 * UNITS_PER_WORD)
966 #define TRAMPOLINE_TEMPLATE(STREAM) \
968 fprintf (STREAM, "\t.begin no-generics\n"); \
969 fprintf (STREAM, "\tentry\tsp, %d\n", MIN_FRAME_SIZE); \
971 /* GCC isn't prepared to deal with data at the beginning of the \
972 trampoline, and the Xtensa l32r instruction requires that the \
973 constant pool be located before the code. We put the constant \
974 pool in the middle of the trampoline and jump around it. */ \
976 fprintf (STREAM, "\tj\t.Lskipconsts\n"); \
977 fprintf (STREAM, "\t.align\t4\n"); \
978 fprintf (STREAM, ".Lfnaddr:%s0\n", integer_asm_op (4, TRUE)); \
979 fprintf (STREAM, ".Lchainval:%s0\n", integer_asm_op (4, TRUE)); \
980 fprintf (STREAM, ".Lskipconsts:\n"); \
982 /* store the static chain */ \
983 fprintf (STREAM, "\tl32r\ta8, .Lchainval\n"); \
984 fprintf (STREAM, "\ts32i\ta8, sp, %d\n", \
985 MIN_FRAME_SIZE - (5 * UNITS_PER_WORD)); \
987 /* set the proper stack pointer value */ \
988 fprintf (STREAM, "\tl32r\ta8, .Lfnaddr\n"); \
989 fprintf (STREAM, "\tl32i\ta9, a8, 0\n"); \
990 fprintf (STREAM, "\textui\ta9, a9, %d, 12\n", \
991 TARGET_BIG_ENDIAN ? 8 : 12); \
992 fprintf (STREAM, "\tslli\ta9, a9, 3\n"); \
993 fprintf (STREAM, "\taddi\ta9, a9, %d\n", -MIN_FRAME_SIZE); \
994 fprintf (STREAM, "\tsub\ta9, sp, a9\n"); \
995 fprintf (STREAM, "\tmovsp\tsp, a9\n"); \
997 /* jump to the instruction following the entry */ \
998 fprintf (STREAM, "\taddi\ta8, a8, 3\n"); \
999 fprintf (STREAM, "\tjx\ta8\n"); \
1000 fprintf (STREAM, "\t.end no-generics\n"); \
1003 /* Size in bytes of the trampoline, as an integer. */
1004 #define TRAMPOLINE_SIZE 49
1006 /* Alignment required for trampolines, in bits. */
1007 #define TRAMPOLINE_ALIGNMENT (32)
1009 /* A C statement to initialize the variable parts of a trampoline. */
1010 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
1013 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 8)), FUNC); \
1014 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 12)), CHAIN); \
1015 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__xtensa_sync_caches"), \
1016 0, VOIDmode, 1, addr, Pmode); \
1019 /* Define the `__builtin_va_list' type for the ABI. */
1020 #define BUILD_VA_LIST_TYPE(VALIST) \
1021 (VALIST) = xtensa_build_va_list ()
1023 /* If defined, is a C expression that produces the machine-specific
1024 code for a call to '__builtin_saveregs'. This code will be moved
1025 to the very beginning of the function, before any parameter access
1026 are made. The return value of this function should be an RTX that
1027 contains the value to use as the return of '__builtin_saveregs'. */
1028 #define EXPAND_BUILTIN_SAVEREGS \
1029 xtensa_builtin_saveregs
1031 /* Implement `va_start' for varargs and stdarg. */
1032 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
1033 xtensa_va_start (valist, nextarg)
1035 /* Implement `va_arg'. */
1036 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1037 xtensa_va_arg (valist, type)
1039 /* If defined, a C expression that produces the machine-specific code
1040 to setup the stack so that arbitrary frames can be accessed.
1042 On Xtensa, a stack back-trace must always begin from the stack pointer,
1043 so that the register overflow save area can be located. However, the
1044 stack-walking code in GCC always begins from the hard_frame_pointer
1045 register, not the stack pointer. The frame pointer is usually equal
1046 to the stack pointer, but the __builtin_return_address and
1047 __builtin_frame_address functions will not work if count > 0 and
1048 they are called from a routine that uses alloca. These functions
1049 are not guaranteed to work at all if count > 0 so maybe that is OK.
1051 A nicer solution would be to allow the architecture-specific files to
1052 specify whether to start from the stack pointer or frame pointer. That
1053 would also allow us to skip the machine->accesses_prev_frame stuff that
1054 we currently need to ensure that there is a frame pointer when these
1055 builtin functions are used. */
1057 #define SETUP_FRAME_ADDRESSES xtensa_setup_frame_addresses
1059 /* A C expression whose value is RTL representing the address in a
1060 stack frame where the pointer to the caller's frame is stored.
1061 Assume that FRAMEADDR is an RTL expression for the address of the
1064 For Xtensa, there is no easy way to get the frame pointer if it is
1065 not equivalent to the stack pointer. Moreover, the result of this
1066 macro is used for continuing to walk back up the stack, so it must
1067 return the stack pointer address. Thus, there is some inconsistency
1068 here in that __builtin_frame_address will return the frame pointer
1069 when count == 0 and the stack pointer when count > 0. */
1071 #define DYNAMIC_CHAIN_ADDRESS(frame) \
1072 gen_rtx (PLUS, Pmode, frame, \
1073 gen_rtx_CONST_INT (VOIDmode, -3 * UNITS_PER_WORD))
1075 /* Define this if the return address of a particular stack frame is
1076 accessed from the frame pointer of the previous stack frame. */
1077 #define RETURN_ADDR_IN_PREVIOUS_FRAME
1079 /* A C expression whose value is RTL representing the value of the
1080 return address for the frame COUNT steps up from the current
1081 frame, after the prologue. */
1082 #define RETURN_ADDR_RTX xtensa_return_addr
1084 /* Addressing modes, and classification of registers for them. */
1086 /* C expressions which are nonzero if register number NUM is suitable
1087 for use as a base or index register in operand addresses. It may
1088 be either a suitable hard register or a pseudo register that has
1089 been allocated such a hard register. The difference between an
1090 index register and a base register is that the index register may
1093 #define REGNO_OK_FOR_BASE_P(NUM) \
1094 (GP_REG_P (NUM) || GP_REG_P ((unsigned) reg_renumber[NUM]))
1096 #define REGNO_OK_FOR_INDEX_P(NUM) 0
1098 /* C expressions that are nonzero if X (assumed to be a `reg' RTX) is
1099 valid for use as a base or index register. For hard registers, it
1100 should always accept those which the hardware permits and reject
1101 the others. Whether the macro accepts or rejects pseudo registers
1102 must be controlled by `REG_OK_STRICT'. This usually requires two
1103 variant definitions, of which `REG_OK_STRICT' controls the one
1104 actually used. The difference between an index register and a base
1105 register is that the index register may be scaled. */
1107 #ifdef REG_OK_STRICT
1109 #define REG_OK_FOR_INDEX_P(X) 0
1110 #define REG_OK_FOR_BASE_P(X) \
1111 REGNO_OK_FOR_BASE_P (REGNO (X))
1113 #else /* !REG_OK_STRICT */
1115 #define REG_OK_FOR_INDEX_P(X) 0
1116 #define REG_OK_FOR_BASE_P(X) \
1117 ((REGNO (X) >= FIRST_PSEUDO_REGISTER) || (GP_REG_P (REGNO (X))))
1119 #endif /* !REG_OK_STRICT */
1121 /* Maximum number of registers that can appear in a valid memory address. */
1122 #define MAX_REGS_PER_ADDRESS 1
1124 /* Identify valid Xtensa addresses. */
1125 #define GO_IF_LEGITIMATE_ADDRESS(MODE, ADDR, LABEL) \
1127 rtx xinsn = (ADDR); \
1129 /* allow constant pool addresses */ \
1130 if ((MODE) != BLKmode && GET_MODE_SIZE (MODE) >= UNITS_PER_WORD \
1131 && constantpool_address_p (xinsn)) \
1134 while (GET_CODE (xinsn) == SUBREG) \
1135 xinsn = SUBREG_REG (xinsn); \
1137 /* allow base registers */ \
1138 if (GET_CODE (xinsn) == REG && REG_OK_FOR_BASE_P (xinsn)) \
1141 /* check for "register + offset" addressing */ \
1142 if (GET_CODE (xinsn) == PLUS) \
1144 rtx xplus0 = XEXP (xinsn, 0); \
1145 rtx xplus1 = XEXP (xinsn, 1); \
1146 enum rtx_code code0; \
1147 enum rtx_code code1; \
1149 while (GET_CODE (xplus0) == SUBREG) \
1150 xplus0 = SUBREG_REG (xplus0); \
1151 code0 = GET_CODE (xplus0); \
1153 while (GET_CODE (xplus1) == SUBREG) \
1154 xplus1 = SUBREG_REG (xplus1); \
1155 code1 = GET_CODE (xplus1); \
1157 /* swap operands if necessary so the register is first */ \
1158 if (code0 != REG && code1 == REG) \
1160 xplus0 = XEXP (xinsn, 1); \
1161 xplus1 = XEXP (xinsn, 0); \
1162 code0 = GET_CODE (xplus0); \
1163 code1 = GET_CODE (xplus1); \
1166 if (code0 == REG && REG_OK_FOR_BASE_P (xplus0) \
1167 && code1 == CONST_INT \
1168 && xtensa_mem_offset (INTVAL (xplus1), (MODE))) \
1175 /* A C expression that is 1 if the RTX X is a constant which is a
1176 valid address. This is defined to be the same as 'CONSTANT_P (X)',
1177 but rejecting CONST_DOUBLE. */
1178 #define CONSTANT_ADDRESS_P(X) \
1179 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1180 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
1181 || (GET_CODE (X) == CONST)))
1183 /* Nonzero if the constant value X is a legitimate general operand.
1184 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1185 #define LEGITIMATE_CONSTANT_P(X) 1
1187 /* A C expression that is nonzero if X is a legitimate immediate
1188 operand on the target machine when generating position independent
1190 #define LEGITIMATE_PIC_OPERAND_P(X) \
1191 ((GET_CODE (X) != SYMBOL_REF || SYMBOL_REF_FLAG (X)) \
1192 && GET_CODE (X) != LABEL_REF \
1193 && GET_CODE (X) != CONST)
1195 /* Tell GCC how to use ADDMI to generate addresses. */
1196 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1199 if (GET_CODE (xinsn) == PLUS) \
1201 rtx plus0 = XEXP (xinsn, 0); \
1202 rtx plus1 = XEXP (xinsn, 1); \
1204 if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG) \
1206 plus0 = XEXP (xinsn, 1); \
1207 plus1 = XEXP (xinsn, 0); \
1210 if (GET_CODE (plus0) == REG \
1211 && GET_CODE (plus1) == CONST_INT \
1212 && !xtensa_mem_offset (INTVAL (plus1), MODE) \
1213 && !xtensa_simm8 (INTVAL (plus1)) \
1214 && xtensa_mem_offset (INTVAL (plus1) & 0xff, MODE) \
1215 && xtensa_simm8x256 (INTVAL (plus1) & ~0xff)) \
1217 rtx temp = gen_reg_rtx (Pmode); \
1218 emit_insn (gen_rtx (SET, Pmode, temp, \
1219 gen_rtx (PLUS, Pmode, plus0, \
1220 GEN_INT (INTVAL (plus1) & ~0xff)))); \
1221 (X) = gen_rtx (PLUS, Pmode, temp, \
1222 GEN_INT (INTVAL (plus1) & 0xff)); \
1229 /* Treat constant-pool references as "mode dependent" since they can
1230 only be accessed with SImode loads. This works around a bug in the
1231 combiner where a constant pool reference is temporarily converted
1232 to an HImode load, which is then assumed to zero-extend based on
1233 our definition of LOAD_EXTEND_OP. This is wrong because the high
1234 bits of a 16-bit value in the constant pool are now sign-extended
1237 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1239 if (constantpool_address_p (ADDR)) \
1243 /* Specify the machine mode that this machine uses
1244 for the index in the tablejump instruction. */
1245 #define CASE_VECTOR_MODE (SImode)
1247 /* Define this if the tablejump instruction expects the table
1248 to contain offsets from the address of the table.
1249 Do not define this if the table should contain absolute addresses. */
1250 /* #define CASE_VECTOR_PC_RELATIVE */
1252 /* Define this as 1 if 'char' should by default be signed; else as 0. */
1253 #define DEFAULT_SIGNED_CHAR 0
1255 /* Max number of bytes we can move from memory to memory
1256 in one reasonably fast instruction. */
1258 #define MAX_MOVE_MAX 4
1260 /* Prefer word-sized loads. */
1261 #define SLOW_BYTE_ACCESS 1
1263 /* Xtensa doesn't have any instructions that set integer values based on the
1264 results of comparisons, but the simplification code in the combiner also
1265 uses this macro. The value should be either 1 or -1 to enable some
1266 optimizations in the combiner; I'm not sure which is better for us.
1267 Since we've been using 1 for a while, it should probably stay that way for
1269 #define STORE_FLAG_VALUE 1
1271 /* Shift instructions ignore all but the low-order few bits. */
1272 #define SHIFT_COUNT_TRUNCATED 1
1274 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1275 is done just by pretending it is already truncated. */
1276 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1278 /* Specify the machine mode that pointers have.
1279 After generation of rtl, the compiler makes no further distinction
1280 between pointers and any other objects of this machine mode. */
1281 #define Pmode SImode
1283 /* A function address in a call instruction is a word address (for
1284 indexing purposes) so give the MEM rtx a words's mode. */
1285 #define FUNCTION_MODE SImode
1287 /* A C expression for the cost of moving data from a register in
1288 class FROM to one in class TO. The classes are expressed using
1289 the enumeration values such as 'GENERAL_REGS'. A value of 2 is
1290 the default; other values are interpreted relative to that. */
1291 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1292 (((FROM) == (TO) && (FROM) != BR_REGS && (TO) != BR_REGS) \
1294 : (reg_class_subset_p ((FROM), AR_REGS) \
1295 && reg_class_subset_p ((TO), AR_REGS) \
1297 : (reg_class_subset_p ((FROM), AR_REGS) \
1298 && (TO) == ACC_REG \
1300 : ((FROM) == ACC_REG \
1301 && reg_class_subset_p ((TO), AR_REGS) \
1305 #define MEMORY_MOVE_COST(MODE, CLASS, IN) 4
1307 #define BRANCH_COST 3
1309 /* Optionally define this if you have added predicates to
1310 'MACHINE.c'. This macro is called within an initializer of an
1311 array of structures. The first field in the structure is the
1312 name of a predicate and the second field is an array of rtl
1313 codes. For each predicate, list all rtl codes that can be in
1314 expressions matched by the predicate. The list should have a
1317 #define PREDICATE_CODES \
1318 {"add_operand", { REG, CONST_INT, SUBREG }}, \
1319 {"arith_operand", { REG, CONST_INT, SUBREG }}, \
1320 {"nonimmed_operand", { REG, SUBREG, MEM }}, \
1321 {"mem_operand", { MEM }}, \
1322 {"mask_operand", { REG, CONST_INT, SUBREG }}, \
1323 {"extui_fldsz_operand", { CONST_INT }}, \
1324 {"sext_fldsz_operand", { CONST_INT }}, \
1325 {"lsbitnum_operand", { CONST_INT }}, \
1326 {"fpmem_offset_operand", { CONST_INT }}, \
1327 {"sext_operand", { REG, SUBREG, MEM }}, \
1328 {"branch_operand", { REG, CONST_INT, SUBREG }}, \
1329 {"ubranch_operand", { REG, CONST_INT, SUBREG }}, \
1330 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG }}, \
1331 {"move_operand", { REG, SUBREG, MEM, CONST_INT, CONST_DOUBLE, \
1332 CONST, SYMBOL_REF, LABEL_REF }}, \
1333 {"non_const_move_operand", { REG, SUBREG, MEM }}, \
1334 {"const_float_1_operand", { CONST_DOUBLE }}, \
1335 {"branch_operator", { EQ, NE, LT, GE }}, \
1336 {"ubranch_operator", { LTU, GEU }}, \
1337 {"boolean_operator", { EQ, NE }},
1339 /* Control the assembler format that we output. */
1341 /* How to refer to registers in assembler output.
1342 This sequence is indexed by compiler's hard-register-number (see above). */
1343 #define REGISTER_NAMES \
1345 "a0", "sp", "a2", "a3", "a4", "a5", "a6", "a7", \
1346 "a8", "a9", "a10", "a11", "a12", "a13", "a14", "a15", \
1347 "fp", "argp", "b0", \
1348 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
1349 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
1353 /* If defined, a C initializer for an array of structures containing a
1354 name and a register number. This macro defines additional names
1355 for hard registers, thus allowing the 'asm' option in declarations
1356 to refer to registers using alternate names. */
1357 #define ADDITIONAL_REGISTER_NAMES \
1359 { "a1", 1 + GP_REG_FIRST } \
1362 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1363 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
1365 /* Recognize machine-specific patterns that may appear within
1366 constants. Used for PIC-specific UNSPECs. */
1367 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
1369 if (flag_pic && GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \
1371 switch (XINT ((X), 1)) \
1374 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
1375 fputs ("@PLT", (STREAM)); \
1386 /* Globalizing directive for a label. */
1387 #define GLOBAL_ASM_OP "\t.global\t"
1389 /* Declare an uninitialized external linkage data object. */
1390 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1391 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
1393 /* This is how to output an element of a case-vector that is absolute. */
1394 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
1395 fprintf (STREAM, "%s%sL%u\n", integer_asm_op (4, TRUE), \
1396 LOCAL_LABEL_PREFIX, VALUE)
1398 /* This is how to output an element of a case-vector that is relative.
1399 This is used for pc-relative code. */
1400 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
1402 fprintf (STREAM, "%s%sL%u-%sL%u\n", integer_asm_op (4, TRUE), \
1403 LOCAL_LABEL_PREFIX, (VALUE), \
1404 LOCAL_LABEL_PREFIX, (REL)); \
1407 /* This is how to output an assembler line that says to advance the
1408 location counter to a multiple of 2**LOG bytes. */
1409 #define ASM_OUTPUT_ALIGN(STREAM, LOG) \
1412 fprintf (STREAM, "\t.align\t%d\n", 1 << (LOG)); \
1415 /* Indicate that jump tables go in the text section. This is
1416 necessary when compiling PIC code. */
1417 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
1420 /* Define the strings to put out for each section in the object file. */
1421 #define TEXT_SECTION_ASM_OP "\t.text"
1422 #define DATA_SECTION_ASM_OP "\t.data"
1423 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
1426 /* Define output to appear before the constant pool. If the function
1427 has been assigned to a specific ELF section, or if it goes into a
1428 unique section, set the name of that section to be the literal
1430 #define ASM_OUTPUT_POOL_PROLOGUE(FILE, FUNNAME, FUNDECL, SIZE) \
1433 resolve_unique_section ((FUNDECL), 0, flag_function_sections); \
1434 fnsection = DECL_SECTION_NAME (FUNDECL); \
1435 if (fnsection != NULL_TREE) \
1437 const char *fnsectname = TREE_STRING_POINTER (fnsection); \
1438 fprintf (FILE, "\t.begin\tliteral_prefix %s\n", \
1439 strcmp (fnsectname, ".text") ? fnsectname : ""); \
1443 function_section (FUNDECL); \
1444 fprintf (FILE, "\t.literal_position\n"); \
1449 /* Define code to write out the ".end literal_prefix" directive for a
1450 function in a special section. This is appended to the standard ELF
1451 code for ASM_DECLARE_FUNCTION_SIZE. */
1452 #define XTENSA_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL) \
1453 if (DECL_SECTION_NAME (DECL) != NULL_TREE) \
1454 fprintf (FILE, "\t.end\tliteral_prefix\n")
1456 /* A C statement (with or without semicolon) to output a constant in
1457 the constant pool, if it needs special treatment. */
1458 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, JUMPTO) \
1460 xtensa_output_literal (FILE, X, MODE, LABELNO); \
1464 /* How to start an assembler comment. */
1465 #define ASM_COMMENT_START "#"
1467 /* Exception handling TODO!! */
1468 #define DWARF_UNWIND_INFO 0
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