1 /* Subroutines for insn-output.c for Tensilica's Xtensa architecture.
2 Copyright 2001, 2002, 2003, 2004, 2005, 2006, 2007
3 Free Software Foundation, Inc.
4 Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "basic-block.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
34 #include "insn-attr.h"
35 #include "insn-codes.h"
49 #include "target-def.h"
50 #include "langhooks.h"
51 #include "tree-gimple.h"
55 /* Enumeration for all of the relational tests, so that we can build
56 arrays indexed by the test type, and not worry about the order
74 /* Cached operands, and operator to compare for use in set/branch on
78 /* what type of branch to use */
79 enum cmp_type branch_type;
81 /* Array giving truth value on whether or not a given hard register
82 can support a given mode. */
83 char xtensa_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
85 /* Current frame size calculated by compute_frame_size. */
86 unsigned xtensa_current_frame_size;
88 /* Largest block move to handle in-line. */
89 #define LARGEST_MOVE_RATIO 15
91 /* Define the structure for the machine field in struct function. */
92 struct machine_function GTY(())
94 int accesses_prev_frame;
98 rtx set_frame_ptr_insn;
101 /* Vector, indexed by hard register number, which contains 1 for a
102 register that is allowable in a candidate for leaf function
105 const char xtensa_leaf_regs[FIRST_PSEUDO_REGISTER] =
107 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
109 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
113 /* Map hard register number to register class */
114 const enum reg_class xtensa_regno_to_class[FIRST_PSEUDO_REGISTER] =
116 RL_REGS, SP_REG, RL_REGS, RL_REGS,
117 RL_REGS, RL_REGS, RL_REGS, GR_REGS,
118 RL_REGS, RL_REGS, RL_REGS, RL_REGS,
119 RL_REGS, RL_REGS, RL_REGS, RL_REGS,
120 AR_REGS, AR_REGS, BR_REGS,
121 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
122 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
123 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
124 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
128 static enum internal_test map_test_to_internal_test (enum rtx_code);
129 static rtx gen_int_relational (enum rtx_code, rtx, rtx, int *);
130 static rtx gen_float_relational (enum rtx_code, rtx, rtx);
131 static rtx gen_conditional_move (rtx);
132 static rtx fixup_subreg_mem (rtx);
133 static struct machine_function * xtensa_init_machine_status (void);
134 static bool xtensa_return_in_msb (const_tree);
135 static void printx (FILE *, signed int);
136 static void xtensa_function_epilogue (FILE *, HOST_WIDE_INT);
137 static rtx xtensa_builtin_saveregs (void);
138 static unsigned int xtensa_multibss_section_type_flags (tree, const char *,
139 int) ATTRIBUTE_UNUSED;
140 static section *xtensa_select_rtx_section (enum machine_mode, rtx,
141 unsigned HOST_WIDE_INT);
142 static bool xtensa_rtx_costs (rtx, int, int, int *);
143 static tree xtensa_build_builtin_va_list (void);
144 static bool xtensa_return_in_memory (const_tree, const_tree);
145 static tree xtensa_gimplify_va_arg_expr (tree, tree, tree *, tree *);
146 static void xtensa_init_builtins (void);
147 static tree xtensa_fold_builtin (tree, tree, bool);
148 static rtx xtensa_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
150 static const int reg_nonleaf_alloc_order[FIRST_PSEUDO_REGISTER] =
154 /* This macro generates the assembly code for function exit,
155 on machines that need it. If FUNCTION_EPILOGUE is not defined
156 then individual return instructions are generated for each
157 return statement. Args are same as for FUNCTION_PROLOGUE. */
159 #undef TARGET_ASM_FUNCTION_EPILOGUE
160 #define TARGET_ASM_FUNCTION_EPILOGUE xtensa_function_epilogue
162 /* These hooks specify assembly directives for creating certain kinds
163 of integer object. */
165 #undef TARGET_ASM_ALIGNED_SI_OP
166 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
168 #undef TARGET_ASM_SELECT_RTX_SECTION
169 #define TARGET_ASM_SELECT_RTX_SECTION xtensa_select_rtx_section
171 #undef TARGET_DEFAULT_TARGET_FLAGS
172 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD)
174 #undef TARGET_RTX_COSTS
175 #define TARGET_RTX_COSTS xtensa_rtx_costs
176 #undef TARGET_ADDRESS_COST
177 #define TARGET_ADDRESS_COST hook_int_rtx_0
179 #undef TARGET_BUILD_BUILTIN_VA_LIST
180 #define TARGET_BUILD_BUILTIN_VA_LIST xtensa_build_builtin_va_list
182 #undef TARGET_PROMOTE_FUNCTION_ARGS
183 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
184 #undef TARGET_PROMOTE_FUNCTION_RETURN
185 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
186 #undef TARGET_PROMOTE_PROTOTYPES
187 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
189 #undef TARGET_RETURN_IN_MEMORY
190 #define TARGET_RETURN_IN_MEMORY xtensa_return_in_memory
191 #undef TARGET_SPLIT_COMPLEX_ARG
192 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
193 #undef TARGET_MUST_PASS_IN_STACK
194 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
196 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
197 #define TARGET_EXPAND_BUILTIN_SAVEREGS xtensa_builtin_saveregs
198 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
199 #define TARGET_GIMPLIFY_VA_ARG_EXPR xtensa_gimplify_va_arg_expr
201 #undef TARGET_RETURN_IN_MSB
202 #define TARGET_RETURN_IN_MSB xtensa_return_in_msb
204 #undef TARGET_INIT_BUILTINS
205 #define TARGET_INIT_BUILTINS xtensa_init_builtins
206 #undef TARGET_FOLD_BUILTIN
207 #define TARGET_FOLD_BUILTIN xtensa_fold_builtin
208 #undef TARGET_EXPAND_BUILTIN
209 #define TARGET_EXPAND_BUILTIN xtensa_expand_builtin
211 struct gcc_target targetm = TARGET_INITIALIZER;
214 /* Functions to test Xtensa immediate operand validity. */
217 xtensa_simm8 (HOST_WIDE_INT v)
219 return v >= -128 && v <= 127;
224 xtensa_simm8x256 (HOST_WIDE_INT v)
226 return (v & 255) == 0 && (v >= -32768 && v <= 32512);
231 xtensa_simm12b (HOST_WIDE_INT v)
233 return v >= -2048 && v <= 2047;
238 xtensa_uimm8 (HOST_WIDE_INT v)
240 return v >= 0 && v <= 255;
245 xtensa_uimm8x2 (HOST_WIDE_INT v)
247 return (v & 1) == 0 && (v >= 0 && v <= 510);
252 xtensa_uimm8x4 (HOST_WIDE_INT v)
254 return (v & 3) == 0 && (v >= 0 && v <= 1020);
259 xtensa_b4const (HOST_WIDE_INT v)
286 xtensa_b4const_or_zero (HOST_WIDE_INT v)
290 return xtensa_b4const (v);
295 xtensa_b4constu (HOST_WIDE_INT v)
322 xtensa_mask_immediate (HOST_WIDE_INT v)
324 #define MAX_MASK_SIZE 16
327 for (mask_size = 1; mask_size <= MAX_MASK_SIZE; mask_size++)
340 /* This is just like the standard true_regnum() function except that it
341 works even when reg_renumber is not initialized. */
344 xt_true_regnum (rtx x)
346 if (GET_CODE (x) == REG)
349 && REGNO (x) >= FIRST_PSEUDO_REGISTER
350 && reg_renumber[REGNO (x)] >= 0)
351 return reg_renumber[REGNO (x)];
354 if (GET_CODE (x) == SUBREG)
356 int base = xt_true_regnum (SUBREG_REG (x));
357 if (base >= 0 && base < FIRST_PSEUDO_REGISTER)
358 return base + subreg_regno_offset (REGNO (SUBREG_REG (x)),
359 GET_MODE (SUBREG_REG (x)),
360 SUBREG_BYTE (x), GET_MODE (x));
367 xtensa_valid_move (enum machine_mode mode, rtx *operands)
369 /* Either the destination or source must be a register, and the
370 MAC16 accumulator doesn't count. */
372 if (register_operand (operands[0], mode))
374 int dst_regnum = xt_true_regnum (operands[0]);
376 /* The stack pointer can only be assigned with a MOVSP opcode. */
377 if (dst_regnum == STACK_POINTER_REGNUM)
378 return (mode == SImode
379 && register_operand (operands[1], mode)
380 && !ACC_REG_P (xt_true_regnum (operands[1])));
382 if (!ACC_REG_P (dst_regnum))
385 if (register_operand (operands[1], mode))
387 int src_regnum = xt_true_regnum (operands[1]);
388 if (!ACC_REG_P (src_regnum))
396 smalloffset_mem_p (rtx op)
398 if (GET_CODE (op) == MEM)
400 rtx addr = XEXP (op, 0);
401 if (GET_CODE (addr) == REG)
402 return BASE_REG_P (addr, 0);
403 if (GET_CODE (addr) == PLUS)
405 rtx offset = XEXP (addr, 0);
407 if (GET_CODE (offset) != CONST_INT)
408 offset = XEXP (addr, 1);
409 if (GET_CODE (offset) != CONST_INT)
412 val = INTVAL (offset);
413 return (val & 3) == 0 && (val >= 0 && val <= 60);
421 constantpool_address_p (rtx addr)
425 if (GET_CODE (addr) == CONST)
429 /* Only handle (PLUS (SYM, OFFSET)) form. */
430 addr = XEXP (addr, 0);
431 if (GET_CODE (addr) != PLUS)
434 /* Make sure the address is word aligned. */
435 offset = XEXP (addr, 1);
436 if ((GET_CODE (offset) != CONST_INT)
437 || ((INTVAL (offset) & 3) != 0))
440 sym = XEXP (addr, 0);
443 if ((GET_CODE (sym) == SYMBOL_REF)
444 && CONSTANT_POOL_ADDRESS_P (sym))
451 constantpool_mem_p (rtx op)
453 if (GET_CODE (op) == SUBREG)
454 op = SUBREG_REG (op);
455 if (GET_CODE (op) == MEM)
456 return constantpool_address_p (XEXP (op, 0));
462 xtensa_extend_reg (rtx dst, rtx src)
464 rtx temp = gen_reg_rtx (SImode);
465 rtx shift = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (GET_MODE (src)));
467 /* Generate paradoxical subregs as needed so that the modes match. */
468 src = simplify_gen_subreg (SImode, src, GET_MODE (src), 0);
469 dst = simplify_gen_subreg (SImode, dst, GET_MODE (dst), 0);
471 emit_insn (gen_ashlsi3 (temp, src, shift));
472 emit_insn (gen_ashrsi3 (dst, temp, shift));
477 xtensa_mem_offset (unsigned v, enum machine_mode mode)
482 /* Handle the worst case for block moves. See xtensa_expand_block_move
483 where we emit an optimized block move operation if the block can be
484 moved in < "move_ratio" pieces. The worst case is when the block is
485 aligned but has a size of (3 mod 4) (does this happen?) so that the
486 last piece requires a byte load/store. */
487 return (xtensa_uimm8 (v)
488 && xtensa_uimm8 (v + MOVE_MAX * LARGEST_MOVE_RATIO));
491 return xtensa_uimm8 (v);
494 return xtensa_uimm8x2 (v);
497 return (xtensa_uimm8x4 (v) && xtensa_uimm8x4 (v + 4));
503 return xtensa_uimm8x4 (v);
507 /* Make normal rtx_code into something we can index from an array. */
509 static enum internal_test
510 map_test_to_internal_test (enum rtx_code test_code)
512 enum internal_test test = ITEST_MAX;
517 case EQ: test = ITEST_EQ; break;
518 case NE: test = ITEST_NE; break;
519 case GT: test = ITEST_GT; break;
520 case GE: test = ITEST_GE; break;
521 case LT: test = ITEST_LT; break;
522 case LE: test = ITEST_LE; break;
523 case GTU: test = ITEST_GTU; break;
524 case GEU: test = ITEST_GEU; break;
525 case LTU: test = ITEST_LTU; break;
526 case LEU: test = ITEST_LEU; break;
533 /* Generate the code to compare two integer values. The return value is
534 the comparison expression. */
537 gen_int_relational (enum rtx_code test_code, /* relational test (EQ, etc) */
538 rtx cmp0, /* first operand to compare */
539 rtx cmp1, /* second operand to compare */
540 int *p_invert /* whether branch needs to reverse test */)
544 enum rtx_code test_code; /* test code to use in insn */
545 bool (*const_range_p) (HOST_WIDE_INT); /* range check function */
546 int const_add; /* constant to add (convert LE -> LT) */
547 int reverse_regs; /* reverse registers in test */
548 int invert_const; /* != 0 if invert value if cmp1 is constant */
549 int invert_reg; /* != 0 if invert value if cmp1 is register */
550 int unsignedp; /* != 0 for unsigned comparisons. */
553 static struct cmp_info info[ (int)ITEST_MAX ] = {
555 { EQ, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* EQ */
556 { NE, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* NE */
558 { LT, xtensa_b4const_or_zero, 1, 1, 1, 0, 0 }, /* GT */
559 { GE, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* GE */
560 { LT, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* LT */
561 { GE, xtensa_b4const_or_zero, 1, 1, 1, 0, 0 }, /* LE */
563 { LTU, xtensa_b4constu, 1, 1, 1, 0, 1 }, /* GTU */
564 { GEU, xtensa_b4constu, 0, 0, 0, 0, 1 }, /* GEU */
565 { LTU, xtensa_b4constu, 0, 0, 0, 0, 1 }, /* LTU */
566 { GEU, xtensa_b4constu, 1, 1, 1, 0, 1 }, /* LEU */
569 enum internal_test test;
570 enum machine_mode mode;
571 struct cmp_info *p_info;
573 test = map_test_to_internal_test (test_code);
574 gcc_assert (test != ITEST_MAX);
576 p_info = &info[ (int)test ];
578 mode = GET_MODE (cmp0);
579 if (mode == VOIDmode)
580 mode = GET_MODE (cmp1);
582 /* Make sure we can handle any constants given to us. */
583 if (GET_CODE (cmp1) == CONST_INT)
585 HOST_WIDE_INT value = INTVAL (cmp1);
586 unsigned HOST_WIDE_INT uvalue = (unsigned HOST_WIDE_INT)value;
588 /* if the immediate overflows or does not fit in the immediate field,
589 spill it to a register */
591 if ((p_info->unsignedp ?
592 (uvalue + p_info->const_add > uvalue) :
593 (value + p_info->const_add > value)) != (p_info->const_add > 0))
595 cmp1 = force_reg (mode, cmp1);
597 else if (!(p_info->const_range_p) (value + p_info->const_add))
599 cmp1 = force_reg (mode, cmp1);
602 else if ((GET_CODE (cmp1) != REG) && (GET_CODE (cmp1) != SUBREG))
604 cmp1 = force_reg (mode, cmp1);
607 /* See if we need to invert the result. */
608 *p_invert = ((GET_CODE (cmp1) == CONST_INT)
609 ? p_info->invert_const
610 : p_info->invert_reg);
612 /* Comparison to constants, may involve adding 1 to change a LT into LE.
613 Comparison between two registers, may involve switching operands. */
614 if (GET_CODE (cmp1) == CONST_INT)
616 if (p_info->const_add != 0)
617 cmp1 = GEN_INT (INTVAL (cmp1) + p_info->const_add);
620 else if (p_info->reverse_regs)
627 return gen_rtx_fmt_ee (p_info->test_code, VOIDmode, cmp0, cmp1);
631 /* Generate the code to compare two float values. The return value is
632 the comparison expression. */
635 gen_float_relational (enum rtx_code test_code, /* relational test (EQ, etc) */
636 rtx cmp0, /* first operand to compare */
637 rtx cmp1 /* second operand to compare */)
639 rtx (*gen_fn) (rtx, rtx, rtx);
641 int reverse_regs, invert;
645 case EQ: reverse_regs = 0; invert = 0; gen_fn = gen_seq_sf; break;
646 case NE: reverse_regs = 0; invert = 1; gen_fn = gen_seq_sf; break;
647 case LE: reverse_regs = 0; invert = 0; gen_fn = gen_sle_sf; break;
648 case GT: reverse_regs = 1; invert = 0; gen_fn = gen_slt_sf; break;
649 case LT: reverse_regs = 0; invert = 0; gen_fn = gen_slt_sf; break;
650 case GE: reverse_regs = 1; invert = 0; gen_fn = gen_sle_sf; break;
652 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode, cmp0, cmp1));
653 reverse_regs = 0; invert = 0; gen_fn = 0; /* avoid compiler warnings */
663 brtmp = gen_rtx_REG (CCmode, FPCC_REGNUM);
664 emit_insn (gen_fn (brtmp, cmp0, cmp1));
666 return gen_rtx_fmt_ee (invert ? EQ : NE, VOIDmode, brtmp, const0_rtx);
671 xtensa_expand_conditional_branch (rtx *operands, enum rtx_code test_code)
673 enum cmp_type type = branch_type;
674 rtx cmp0 = branch_cmp[0];
675 rtx cmp1 = branch_cmp[1];
684 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode, cmp0, cmp1));
688 cmp = gen_int_relational (test_code, cmp0, cmp1, &invert);
692 if (!TARGET_HARD_FLOAT)
693 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode,
696 cmp = gen_float_relational (test_code, cmp0, cmp1);
700 /* Generate the branch. */
702 label1 = gen_rtx_LABEL_REF (VOIDmode, operands[0]);
711 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
712 gen_rtx_IF_THEN_ELSE (VOIDmode, cmp,
719 gen_conditional_move (rtx cmp)
721 enum rtx_code code = GET_CODE (cmp);
722 rtx op0 = branch_cmp[0];
723 rtx op1 = branch_cmp[1];
725 if (branch_type == CMP_SI)
727 /* Jump optimization calls get_condition() which canonicalizes
728 comparisons like (GE x <const>) to (GT x <const-1>).
729 Transform those comparisons back to GE, since that is the
730 comparison supported in Xtensa. We shouldn't have to
731 transform <LE x const> comparisons, because neither
732 xtensa_expand_conditional_branch() nor get_condition() will
735 if ((code == GT) && (op1 == constm1_rtx))
740 cmp = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx);
742 if (boolean_operator (cmp, VOIDmode))
744 /* Swap the operands to make const0 second. */
745 if (op0 == const0_rtx)
751 /* If not comparing against zero, emit a comparison (subtract). */
752 if (op1 != const0_rtx)
754 op0 = expand_binop (SImode, sub_optab, op0, op1,
755 0, 0, OPTAB_LIB_WIDEN);
759 else if (branch_operator (cmp, VOIDmode))
761 /* Swap the operands to make const0 second. */
762 if (op0 == const0_rtx)
769 case LT: code = GE; break;
770 case GE: code = LT; break;
771 default: gcc_unreachable ();
775 if (op1 != const0_rtx)
781 return gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
784 if (TARGET_HARD_FLOAT && (branch_type == CMP_SF))
785 return gen_float_relational (code, op0, op1);
792 xtensa_expand_conditional_move (rtx *operands, int isflt)
795 rtx (*gen_fn) (rtx, rtx, rtx, rtx, rtx);
797 if (!(cmp = gen_conditional_move (operands[1])))
801 gen_fn = (branch_type == CMP_SI
802 ? gen_movsfcc_internal0
803 : gen_movsfcc_internal1);
805 gen_fn = (branch_type == CMP_SI
806 ? gen_movsicc_internal0
807 : gen_movsicc_internal1);
809 emit_insn (gen_fn (operands[0], XEXP (cmp, 0),
810 operands[2], operands[3], cmp));
816 xtensa_expand_scc (rtx *operands)
818 rtx dest = operands[0];
819 rtx cmp = operands[1];
820 rtx one_tmp, zero_tmp;
821 rtx (*gen_fn) (rtx, rtx, rtx, rtx, rtx);
823 if (!(cmp = gen_conditional_move (cmp)))
826 one_tmp = gen_reg_rtx (SImode);
827 zero_tmp = gen_reg_rtx (SImode);
828 emit_insn (gen_movsi (one_tmp, const_true_rtx));
829 emit_insn (gen_movsi (zero_tmp, const0_rtx));
831 gen_fn = (branch_type == CMP_SI
832 ? gen_movsicc_internal0
833 : gen_movsicc_internal1);
834 emit_insn (gen_fn (dest, XEXP (cmp, 0), one_tmp, zero_tmp, cmp));
839 /* Split OP[1] into OP[2,3] and likewise for OP[0] into OP[0,1]. MODE is
840 for the output, i.e., the input operands are twice as big as MODE. */
843 xtensa_split_operand_pair (rtx operands[4], enum machine_mode mode)
845 switch (GET_CODE (operands[1]))
848 operands[3] = gen_rtx_REG (mode, REGNO (operands[1]) + 1);
849 operands[2] = gen_rtx_REG (mode, REGNO (operands[1]));
853 operands[3] = adjust_address (operands[1], mode, GET_MODE_SIZE (mode));
854 operands[2] = adjust_address (operands[1], mode, 0);
859 split_double (operands[1], &operands[2], &operands[3]);
866 switch (GET_CODE (operands[0]))
869 operands[1] = gen_rtx_REG (mode, REGNO (operands[0]) + 1);
870 operands[0] = gen_rtx_REG (mode, REGNO (operands[0]));
874 operands[1] = adjust_address (operands[0], mode, GET_MODE_SIZE (mode));
875 operands[0] = adjust_address (operands[0], mode, 0);
884 /* Emit insns to move operands[1] into operands[0].
885 Return 1 if we have written out everything that needs to be done to
886 do the move. Otherwise, return 0 and the caller will emit the move
890 xtensa_emit_move_sequence (rtx *operands, enum machine_mode mode)
892 if (CONSTANT_P (operands[1])
893 && (GET_CODE (operands[1]) != CONST_INT
894 || !xtensa_simm12b (INTVAL (operands[1]))))
897 operands[1] = force_const_mem (SImode, operands[1]);
899 /* PC-relative loads are always SImode, and CONST16 is only
900 supported in the movsi pattern, so add a SUBREG for any other
905 if (register_operand (operands[0], mode))
907 operands[0] = simplify_gen_subreg (SImode, operands[0], mode, 0);
908 emit_move_insn (operands[0], operands[1]);
913 operands[1] = force_reg (SImode, operands[1]);
914 operands[1] = gen_lowpart_SUBREG (mode, operands[1]);
919 if (!(reload_in_progress | reload_completed)
920 && !xtensa_valid_move (mode, operands))
921 operands[1] = force_reg (mode, operands[1]);
923 operands[1] = xtensa_copy_incoming_a7 (operands[1]);
925 /* During reload we don't want to emit (subreg:X (mem:Y)) since that
926 instruction won't be recognized after reload, so we remove the
927 subreg and adjust mem accordingly. */
928 if (reload_in_progress)
930 operands[0] = fixup_subreg_mem (operands[0]);
931 operands[1] = fixup_subreg_mem (operands[1]);
938 fixup_subreg_mem (rtx x)
940 if (GET_CODE (x) == SUBREG
941 && GET_CODE (SUBREG_REG (x)) == REG
942 && REGNO (SUBREG_REG (x)) >= FIRST_PSEUDO_REGISTER)
945 gen_rtx_SUBREG (GET_MODE (x),
946 reg_equiv_mem [REGNO (SUBREG_REG (x))],
948 x = alter_subreg (&temp);
954 /* Check if an incoming argument in a7 is expected to be used soon and
955 if OPND is a register or register pair that includes a7. If so,
956 create a new pseudo and copy a7 into that pseudo at the very
957 beginning of the function, followed by the special "set_frame_ptr"
958 unspec_volatile insn. The return value is either the original
959 operand, if it is not a7, or the new pseudo containing a copy of
960 the incoming argument. This is necessary because the register
961 allocator will ignore conflicts with a7 and may either assign some
962 other pseudo to a7 or use a7 as the hard_frame_pointer, clobbering
963 the incoming argument in a7. By copying the argument out of a7 as
964 the very first thing, and then immediately following that with an
965 unspec_volatile to keep the scheduler away, we should avoid any
966 problems. Putting the set_frame_ptr insn at the beginning, with
967 only the a7 copy before it, also makes it easier for the prologue
968 expander to initialize the frame pointer after the a7 copy and to
969 fix up the a7 copy to use the stack pointer instead of the frame
973 xtensa_copy_incoming_a7 (rtx opnd)
977 enum machine_mode mode;
979 if (!cfun->machine->need_a7_copy)
982 /* This function should never be called again once a7 has been copied. */
983 gcc_assert (!cfun->machine->set_frame_ptr_insn);
985 mode = GET_MODE (opnd);
987 /* The operand using a7 may come in a later instruction, so just return
988 the original operand if it doesn't use a7. */
990 if (GET_CODE (reg) == SUBREG)
992 gcc_assert (SUBREG_BYTE (reg) == 0);
993 reg = SUBREG_REG (reg);
995 if (GET_CODE (reg) != REG
996 || REGNO (reg) > A7_REG
997 || REGNO (reg) + HARD_REGNO_NREGS (A7_REG, mode) <= A7_REG)
1000 /* 1-word args will always be in a7; 2-word args in a6/a7. */
1001 gcc_assert (REGNO (reg) + HARD_REGNO_NREGS (A7_REG, mode) - 1 == A7_REG);
1003 cfun->machine->need_a7_copy = false;
1005 /* Copy a7 to a new pseudo at the function entry. Use gen_raw_REG to
1006 create the REG for a7 so that hard_frame_pointer_rtx is not used. */
1009 tmp = gen_reg_rtx (mode);
1015 emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode, tmp, 0),
1016 gen_rtx_REG (SImode, A7_REG - 1)));
1017 emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode, tmp, 4),
1018 gen_raw_REG (SImode, A7_REG)));
1021 emit_insn (gen_movsf_internal (tmp, gen_raw_REG (mode, A7_REG)));
1024 emit_insn (gen_movsi_internal (tmp, gen_raw_REG (mode, A7_REG)));
1027 emit_insn (gen_movhi_internal (tmp, gen_raw_REG (mode, A7_REG)));
1030 emit_insn (gen_movqi_internal (tmp, gen_raw_REG (mode, A7_REG)));
1036 cfun->machine->set_frame_ptr_insn = emit_insn (gen_set_frame_ptr ());
1037 entry_insns = get_insns ();
1040 if (cfun->machine->vararg_a7)
1042 /* This is called from within builtin_saveregs, which will insert the
1043 saveregs code at the function entry, ahead of anything placed at
1044 the function entry now. Instead, save the sequence to be inserted
1045 at the beginning of the saveregs code. */
1046 cfun->machine->vararg_a7_copy = entry_insns;
1050 /* Put entry_insns after the NOTE that starts the function. If
1051 this is inside a start_sequence, make the outer-level insn
1052 chain current, so the code is placed at the start of the
1054 push_topmost_sequence ();
1055 /* Do not use entry_of_function() here. This is called from within
1056 expand_function_start, when the CFG still holds GIMPLE. */
1057 emit_insn_after (entry_insns, get_insns ());
1058 pop_topmost_sequence ();
1065 /* Try to expand a block move operation to a sequence of RTL move
1066 instructions. If not optimizing, or if the block size is not a
1067 constant, or if the block is too large, the expansion fails and GCC
1068 falls back to calling memcpy().
1070 operands[0] is the destination
1071 operands[1] is the source
1072 operands[2] is the length
1073 operands[3] is the alignment */
1076 xtensa_expand_block_move (rtx *operands)
1078 static const enum machine_mode mode_from_align[] =
1080 VOIDmode, QImode, HImode, VOIDmode, SImode,
1083 rtx dst_mem = operands[0];
1084 rtx src_mem = operands[1];
1085 HOST_WIDE_INT bytes, align;
1086 int num_pieces, move_ratio;
1088 enum machine_mode mode[2];
1097 /* If this is not a fixed size move, just call memcpy. */
1098 if (!optimize || (GET_CODE (operands[2]) != CONST_INT))
1101 bytes = INTVAL (operands[2]);
1102 align = INTVAL (operands[3]);
1104 /* Anything to move? */
1108 if (align > MOVE_MAX)
1111 /* Decide whether to expand inline based on the optimization level. */
1114 move_ratio = LARGEST_MOVE_RATIO;
1115 num_pieces = (bytes / align) + (bytes % align); /* Close enough anyway. */
1116 if (num_pieces > move_ratio)
1119 x = XEXP (dst_mem, 0);
1122 x = force_reg (Pmode, x);
1123 dst_mem = replace_equiv_address (dst_mem, x);
1126 x = XEXP (src_mem, 0);
1129 x = force_reg (Pmode, x);
1130 src_mem = replace_equiv_address (src_mem, x);
1133 active[0] = active[1] = false;
1144 next_amount = (bytes >= 4 ? 4 : (bytes >= 2 ? 2 : 1));
1145 next_amount = MIN (next_amount, align);
1147 amount[next] = next_amount;
1148 mode[next] = mode_from_align[next_amount];
1149 temp[next] = gen_reg_rtx (mode[next]);
1151 x = adjust_address (src_mem, mode[next], offset_ld);
1152 emit_insn (gen_rtx_SET (VOIDmode, temp[next], x));
1154 offset_ld += next_amount;
1155 bytes -= next_amount;
1156 active[next] = true;
1161 active[phase] = false;
1163 x = adjust_address (dst_mem, mode[phase], offset_st);
1164 emit_insn (gen_rtx_SET (VOIDmode, x, temp[phase]));
1166 offset_st += amount[phase];
1169 while (active[next]);
1176 xtensa_expand_nonlocal_goto (rtx *operands)
1178 rtx goto_handler = operands[1];
1179 rtx containing_fp = operands[3];
1181 /* Generate a call to "__xtensa_nonlocal_goto" (in libgcc); the code
1182 is too big to generate in-line. */
1184 if (GET_CODE (containing_fp) != REG)
1185 containing_fp = force_reg (Pmode, containing_fp);
1187 goto_handler = copy_rtx (goto_handler);
1188 validate_replace_rtx (virtual_stack_vars_rtx, containing_fp, goto_handler);
1190 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_nonlocal_goto"),
1192 containing_fp, Pmode,
1193 goto_handler, Pmode);
1197 static struct machine_function *
1198 xtensa_init_machine_status (void)
1200 return ggc_alloc_cleared (sizeof (struct machine_function));
1204 /* Shift VAL of mode MODE left by COUNT bits. */
1207 xtensa_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
1209 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
1210 NULL_RTX, 1, OPTAB_DIRECT);
1211 return expand_simple_binop (SImode, ASHIFT, val, count,
1212 NULL_RTX, 1, OPTAB_DIRECT);
1216 /* Structure to hold the initial parameters for a compare_and_swap operation
1217 in HImode and QImode. */
1219 struct alignment_context
1221 rtx memsi; /* SI aligned memory location. */
1222 rtx shift; /* Bit offset with regard to lsb. */
1223 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
1224 rtx modemaski; /* ~modemask */
1228 /* Initialize structure AC for word access to HI and QI mode memory. */
1231 init_alignment_context (struct alignment_context *ac, rtx mem)
1233 enum machine_mode mode = GET_MODE (mem);
1234 rtx byteoffset = NULL_RTX;
1235 bool aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
1238 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
1241 /* Alignment is unknown. */
1244 /* Force the address into a register. */
1245 addr = force_reg (Pmode, XEXP (mem, 0));
1247 /* Align it to SImode. */
1248 align = expand_simple_binop (Pmode, AND, addr,
1249 GEN_INT (-GET_MODE_SIZE (SImode)),
1250 NULL_RTX, 1, OPTAB_DIRECT);
1252 ac->memsi = gen_rtx_MEM (SImode, align);
1253 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
1254 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
1255 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
1257 byteoffset = expand_simple_binop (Pmode, AND, addr,
1258 GEN_INT (GET_MODE_SIZE (SImode) - 1),
1259 NULL_RTX, 1, OPTAB_DIRECT);
1262 /* Calculate shiftcount. */
1263 if (TARGET_BIG_ENDIAN)
1265 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
1267 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
1268 NULL_RTX, 1, OPTAB_DIRECT);
1273 ac->shift = NULL_RTX;
1275 ac->shift = byteoffset;
1278 if (ac->shift != NULL_RTX)
1280 /* Shift is the byte count, but we need the bitcount. */
1281 ac->shift = expand_simple_binop (SImode, MULT, ac->shift,
1282 GEN_INT (BITS_PER_UNIT),
1283 NULL_RTX, 1, OPTAB_DIRECT);
1284 ac->modemask = expand_simple_binop (SImode, ASHIFT,
1285 GEN_INT (GET_MODE_MASK (mode)),
1287 NULL_RTX, 1, OPTAB_DIRECT);
1290 ac->modemask = GEN_INT (GET_MODE_MASK (mode));
1292 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1);
1296 /* Expand an atomic compare and swap operation for HImode and QImode.
1297 MEM is the memory location, CMP the old value to compare MEM with
1298 and NEW the value to set if CMP == MEM. */
1301 xtensa_expand_compare_and_swap (rtx target, rtx mem, rtx cmp, rtx new)
1303 enum machine_mode mode = GET_MODE (mem);
1304 struct alignment_context ac;
1305 rtx tmp, cmpv, newv, val;
1306 rtx oldval = gen_reg_rtx (SImode);
1307 rtx res = gen_reg_rtx (SImode);
1308 rtx csloop = gen_label_rtx ();
1309 rtx csend = gen_label_rtx ();
1311 init_alignment_context (&ac, mem);
1313 if (ac.shift != NULL_RTX)
1315 cmp = xtensa_expand_mask_and_shift (cmp, mode, ac.shift);
1316 new = xtensa_expand_mask_and_shift (new, mode, ac.shift);
1319 /* Load the surrounding word into VAL with the MEM value masked out. */
1320 val = force_reg (SImode, expand_simple_binop (SImode, AND, ac.memsi,
1321 ac.modemaski, NULL_RTX, 1,
1323 emit_label (csloop);
1325 /* Patch CMP and NEW into VAL at correct position. */
1326 cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val,
1327 NULL_RTX, 1, OPTAB_DIRECT));
1328 newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new, val,
1329 NULL_RTX, 1, OPTAB_DIRECT));
1331 /* Jump to end if we're done. */
1332 emit_insn (gen_sync_compare_and_swapsi (res, ac.memsi, cmpv, newv));
1333 emit_cmp_and_jump_insns (res, cmpv, EQ, const0_rtx, SImode, true, csend);
1335 /* Check for changes outside mode. */
1336 emit_move_insn (oldval, val);
1337 tmp = expand_simple_binop (SImode, AND, res, ac.modemaski,
1338 val, 1, OPTAB_DIRECT);
1340 emit_move_insn (val, tmp);
1342 /* Loop internal if so. */
1343 emit_cmp_and_jump_insns (oldval, val, NE, const0_rtx, SImode, true, csloop);
1347 /* Return the correct part of the bitfield. */
1348 convert_move (target,
1349 (ac.shift == NULL_RTX ? res
1350 : expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
1351 NULL_RTX, 1, OPTAB_DIRECT)),
1356 /* Expand an atomic operation CODE of mode MODE (either HImode or QImode --
1357 the default expansion works fine for SImode). MEM is the memory location
1358 and VAL the value to play with. If AFTER is true then store the value
1359 MEM holds after the operation, if AFTER is false then store the value MEM
1360 holds before the operation. If TARGET is zero then discard that value, else
1361 store it to TARGET. */
1364 xtensa_expand_atomic (enum rtx_code code, rtx target, rtx mem, rtx val,
1367 enum machine_mode mode = GET_MODE (mem);
1368 struct alignment_context ac;
1369 rtx csloop = gen_label_rtx ();
1371 rtx old = gen_reg_rtx (SImode);
1372 rtx new = gen_reg_rtx (SImode);
1373 rtx orig = NULL_RTX;
1375 init_alignment_context (&ac, mem);
1377 /* Prepare values before the compare-and-swap loop. */
1378 if (ac.shift != NULL_RTX)
1379 val = xtensa_expand_mask_and_shift (val, mode, ac.shift);
1384 orig = gen_reg_rtx (SImode);
1385 convert_move (orig, val, 1);
1393 case MULT: /* NAND */
1395 /* val = "11..1<val>11..1" */
1396 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
1397 NULL_RTX, 1, OPTAB_DIRECT);
1404 /* Load full word. Subsequent loads are performed by S32C1I. */
1405 cmp = force_reg (SImode, ac.memsi);
1407 emit_label (csloop);
1408 emit_move_insn (old, cmp);
1414 val = expand_simple_binop (SImode, code, old, orig,
1415 NULL_RTX, 1, OPTAB_DIRECT);
1416 val = expand_simple_binop (SImode, AND, val, ac.modemask,
1417 NULL_RTX, 1, OPTAB_DIRECT);
1420 tmp = expand_simple_binop (SImode, AND, old, ac.modemaski,
1421 NULL_RTX, 1, OPTAB_DIRECT);
1422 tmp = expand_simple_binop (SImode, IOR, tmp, val,
1423 new, 1, OPTAB_DIRECT);
1429 tmp = expand_simple_binop (SImode, code, old, val,
1430 new, 1, OPTAB_DIRECT);
1433 case MULT: /* NAND */
1434 tmp = expand_simple_binop (SImode, XOR, old, ac.modemask,
1435 NULL_RTX, 1, OPTAB_DIRECT);
1436 tmp = expand_simple_binop (SImode, AND, tmp, val,
1437 new, 1, OPTAB_DIRECT);
1445 emit_move_insn (new, tmp);
1446 emit_insn (gen_sync_compare_and_swapsi (cmp, ac.memsi, old, new));
1447 emit_cmp_and_jump_insns (cmp, old, NE, const0_rtx, SImode, true, csloop);
1451 tmp = (after ? new : cmp);
1452 convert_move (target,
1453 (ac.shift == NULL_RTX ? tmp
1454 : expand_simple_binop (SImode, LSHIFTRT, tmp, ac.shift,
1455 NULL_RTX, 1, OPTAB_DIRECT)),
1462 xtensa_setup_frame_addresses (void)
1464 /* Set flag to cause FRAME_POINTER_REQUIRED to be set. */
1465 cfun->machine->accesses_prev_frame = 1;
1468 (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_libgcc_window_spill"),
1473 /* Emit the assembly for the end of a zero-cost loop. Normally we just emit
1474 a comment showing where the end of the loop is. However, if there is a
1475 label or a branch at the end of the loop then we need to place a nop
1476 there. If the loop ends with a label we need the nop so that branches
1477 targeting that label will target the nop (and thus remain in the loop),
1478 instead of targeting the instruction after the loop (and thus exiting
1479 the loop). If the loop ends with a branch, we need the nop in case the
1480 branch is targeting a location inside the loop. When the branch
1481 executes it will cause the loop count to be decremented even if it is
1482 taken (because it is the last instruction in the loop), so we need to
1483 nop after the branch to prevent the loop count from being decremented
1484 when the branch is taken. */
1487 xtensa_emit_loop_end (rtx insn, rtx *operands)
1491 for (insn = PREV_INSN (insn); insn && !done; insn = PREV_INSN (insn))
1493 switch (GET_CODE (insn))
1500 output_asm_insn (TARGET_DENSITY ? "nop.n" : "nop", operands);
1506 rtx body = PATTERN (insn);
1508 if (GET_CODE (body) == JUMP_INSN)
1510 output_asm_insn (TARGET_DENSITY ? "nop.n" : "nop", operands);
1513 else if ((GET_CODE (body) != USE)
1514 && (GET_CODE (body) != CLOBBER))
1521 output_asm_insn ("# loop end for %0", operands);
1526 xtensa_emit_branch (bool inverted, bool immed, rtx *operands)
1528 static char result[64];
1532 code = GET_CODE (operands[3]);
1535 case EQ: op = inverted ? "ne" : "eq"; break;
1536 case NE: op = inverted ? "eq" : "ne"; break;
1537 case LT: op = inverted ? "ge" : "lt"; break;
1538 case GE: op = inverted ? "lt" : "ge"; break;
1539 case LTU: op = inverted ? "geu" : "ltu"; break;
1540 case GEU: op = inverted ? "ltu" : "geu"; break;
1541 default: gcc_unreachable ();
1546 if (INTVAL (operands[1]) == 0)
1547 sprintf (result, "b%sz%s\t%%0, %%2", op,
1548 (TARGET_DENSITY && (code == EQ || code == NE)) ? ".n" : "");
1550 sprintf (result, "b%si\t%%0, %%d1, %%2", op);
1553 sprintf (result, "b%s\t%%0, %%1, %%2", op);
1560 xtensa_emit_bit_branch (bool inverted, bool immed, rtx *operands)
1562 static char result[64];
1565 switch (GET_CODE (operands[3]))
1567 case EQ: op = inverted ? "bs" : "bc"; break;
1568 case NE: op = inverted ? "bc" : "bs"; break;
1569 default: gcc_unreachable ();
1574 unsigned bitnum = INTVAL (operands[1]) & 0x1f;
1575 operands[1] = GEN_INT (bitnum);
1576 sprintf (result, "b%si\t%%0, %%d1, %%2", op);
1579 sprintf (result, "b%s\t%%0, %%1, %%2", op);
1586 xtensa_emit_movcc (bool inverted, bool isfp, bool isbool, rtx *operands)
1588 static char result[64];
1592 code = GET_CODE (operands[4]);
1597 case EQ: op = inverted ? "t" : "f"; break;
1598 case NE: op = inverted ? "f" : "t"; break;
1599 default: gcc_unreachable ();
1606 case EQ: op = inverted ? "nez" : "eqz"; break;
1607 case NE: op = inverted ? "eqz" : "nez"; break;
1608 case LT: op = inverted ? "gez" : "ltz"; break;
1609 case GE: op = inverted ? "ltz" : "gez"; break;
1610 default: gcc_unreachable ();
1614 sprintf (result, "mov%s%s\t%%0, %%%d, %%1",
1615 op, isfp ? ".s" : "", inverted ? 3 : 2);
1621 xtensa_emit_call (int callop, rtx *operands)
1623 static char result[64];
1624 rtx tgt = operands[callop];
1626 if (GET_CODE (tgt) == CONST_INT)
1627 sprintf (result, "call8\t0x%lx", INTVAL (tgt));
1628 else if (register_operand (tgt, VOIDmode))
1629 sprintf (result, "callx8\t%%%d", callop);
1631 sprintf (result, "call8\t%%%d", callop);
1638 xtensa_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict)
1640 /* Allow constant pool addresses. */
1641 if (mode != BLKmode && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
1642 && ! TARGET_CONST16 && constantpool_address_p (addr))
1645 while (GET_CODE (addr) == SUBREG)
1646 addr = SUBREG_REG (addr);
1648 /* Allow base registers. */
1649 if (GET_CODE (addr) == REG && BASE_REG_P (addr, strict))
1652 /* Check for "register + offset" addressing. */
1653 if (GET_CODE (addr) == PLUS)
1655 rtx xplus0 = XEXP (addr, 0);
1656 rtx xplus1 = XEXP (addr, 1);
1657 enum rtx_code code0;
1658 enum rtx_code code1;
1660 while (GET_CODE (xplus0) == SUBREG)
1661 xplus0 = SUBREG_REG (xplus0);
1662 code0 = GET_CODE (xplus0);
1664 while (GET_CODE (xplus1) == SUBREG)
1665 xplus1 = SUBREG_REG (xplus1);
1666 code1 = GET_CODE (xplus1);
1668 /* Swap operands if necessary so the register is first. */
1669 if (code0 != REG && code1 == REG)
1671 xplus0 = XEXP (addr, 1);
1672 xplus1 = XEXP (addr, 0);
1673 code0 = GET_CODE (xplus0);
1674 code1 = GET_CODE (xplus1);
1677 if (code0 == REG && BASE_REG_P (xplus0, strict)
1678 && code1 == CONST_INT
1679 && xtensa_mem_offset (INTVAL (xplus1), mode))
1688 xtensa_legitimize_address (rtx x,
1689 rtx oldx ATTRIBUTE_UNUSED,
1690 enum machine_mode mode)
1692 if (GET_CODE (x) == PLUS)
1694 rtx plus0 = XEXP (x, 0);
1695 rtx plus1 = XEXP (x, 1);
1697 if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG)
1699 plus0 = XEXP (x, 1);
1700 plus1 = XEXP (x, 0);
1703 /* Try to split up the offset to use an ADDMI instruction. */
1704 if (GET_CODE (plus0) == REG
1705 && GET_CODE (plus1) == CONST_INT
1706 && !xtensa_mem_offset (INTVAL (plus1), mode)
1707 && !xtensa_simm8 (INTVAL (plus1))
1708 && xtensa_mem_offset (INTVAL (plus1) & 0xff, mode)
1709 && xtensa_simm8x256 (INTVAL (plus1) & ~0xff))
1711 rtx temp = gen_reg_rtx (Pmode);
1712 rtx addmi_offset = GEN_INT (INTVAL (plus1) & ~0xff);
1713 emit_insn (gen_rtx_SET (Pmode, temp,
1714 gen_rtx_PLUS (Pmode, plus0, addmi_offset)));
1715 return gen_rtx_PLUS (Pmode, temp, GEN_INT (INTVAL (plus1) & 0xff));
1723 /* Return the debugger register number to use for 'regno'. */
1726 xtensa_dbx_register_number (int regno)
1730 if (GP_REG_P (regno))
1732 regno -= GP_REG_FIRST;
1735 else if (BR_REG_P (regno))
1737 regno -= BR_REG_FIRST;
1740 else if (FP_REG_P (regno))
1742 regno -= FP_REG_FIRST;
1745 else if (ACC_REG_P (regno))
1747 first = 0x200; /* Start of Xtensa special registers. */
1748 regno = 16; /* ACCLO is special register 16. */
1751 /* When optimizing, we sometimes get asked about pseudo-registers
1752 that don't represent hard registers. Return 0 for these. */
1756 return first + regno;
1760 /* Argument support functions. */
1762 /* Initialize CUMULATIVE_ARGS for a function. */
1765 init_cumulative_args (CUMULATIVE_ARGS *cum, int incoming)
1768 cum->incoming = incoming;
1772 /* Advance the argument to the next argument position. */
1775 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type)
1780 arg_words = &cum->arg_words;
1781 max = MAX_ARGS_IN_REGISTERS;
1783 words = (((mode != BLKmode)
1784 ? (int) GET_MODE_SIZE (mode)
1785 : int_size_in_bytes (type)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1787 if (*arg_words < max
1788 && (targetm.calls.must_pass_in_stack (mode, type)
1789 || *arg_words + words > max))
1792 *arg_words += words;
1796 /* Return an RTL expression containing the register for the given mode,
1797 or 0 if the argument is to be passed on the stack. INCOMING_P is nonzero
1798 if this is an incoming argument to the current function. */
1801 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
1804 int regbase, words, max;
1808 arg_words = &cum->arg_words;
1809 regbase = (incoming_p ? GP_ARG_FIRST : GP_OUTGOING_ARG_FIRST);
1810 max = MAX_ARGS_IN_REGISTERS;
1812 words = (((mode != BLKmode)
1813 ? (int) GET_MODE_SIZE (mode)
1814 : int_size_in_bytes (type)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1816 if (type && (TYPE_ALIGN (type) > BITS_PER_WORD))
1818 int align = MIN (TYPE_ALIGN (type), STACK_BOUNDARY) / BITS_PER_WORD;
1819 *arg_words = (*arg_words + align - 1) & -align;
1822 if (*arg_words + words > max)
1825 regno = regbase + *arg_words;
1827 if (cum->incoming && regno <= A7_REG && regno + words > A7_REG)
1828 cfun->machine->need_a7_copy = true;
1830 return gen_rtx_REG (mode, regno);
1835 function_arg_boundary (enum machine_mode mode, tree type)
1837 unsigned int alignment;
1839 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
1840 if (alignment < PARM_BOUNDARY)
1841 alignment = PARM_BOUNDARY;
1842 if (alignment > STACK_BOUNDARY)
1843 alignment = STACK_BOUNDARY;
1849 xtensa_return_in_msb (const_tree valtype)
1851 return (TARGET_BIG_ENDIAN
1852 && AGGREGATE_TYPE_P (valtype)
1853 && int_size_in_bytes (valtype) >= UNITS_PER_WORD);
1858 override_options (void)
1861 enum machine_mode mode;
1863 if (!TARGET_BOOLEANS && TARGET_HARD_FLOAT)
1864 error ("boolean registers required for the floating-point option");
1866 /* Set up array giving whether a given register can hold a given mode. */
1867 for (mode = VOIDmode;
1868 mode != MAX_MACHINE_MODE;
1869 mode = (enum machine_mode) ((int) mode + 1))
1871 int size = GET_MODE_SIZE (mode);
1872 enum mode_class class = GET_MODE_CLASS (mode);
1874 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1878 if (ACC_REG_P (regno))
1879 temp = (TARGET_MAC16
1880 && (class == MODE_INT) && (size <= UNITS_PER_WORD));
1881 else if (GP_REG_P (regno))
1882 temp = ((regno & 1) == 0 || (size <= UNITS_PER_WORD));
1883 else if (FP_REG_P (regno))
1884 temp = (TARGET_HARD_FLOAT && (mode == SFmode));
1885 else if (BR_REG_P (regno))
1886 temp = (TARGET_BOOLEANS && (mode == CCmode));
1890 xtensa_hard_regno_mode_ok[(int) mode][regno] = temp;
1894 init_machine_status = xtensa_init_machine_status;
1896 /* Check PIC settings. PIC is only supported when using L32R
1897 instructions, and some targets need to always use PIC. */
1898 if (flag_pic && TARGET_CONST16)
1899 error ("-f%s is not supported with CONST16 instructions",
1900 (flag_pic > 1 ? "PIC" : "pic"));
1901 else if (XTENSA_ALWAYS_PIC)
1904 error ("PIC is required but not supported with CONST16 instructions");
1907 /* There's no need for -fPIC (as opposed to -fpic) on Xtensa. */
1911 /* Hot/cold partitioning does not work on this architecture, because of
1912 constant pools (the load instruction cannot necessarily reach that far).
1913 Therefore disable it on this architecture. */
1914 if (flag_reorder_blocks_and_partition)
1916 flag_reorder_blocks_and_partition = 0;
1917 flag_reorder_blocks = 1;
1922 /* A C compound statement to output to stdio stream STREAM the
1923 assembler syntax for an instruction operand X. X is an RTL
1926 CODE is a value that can be used to specify one of several ways
1927 of printing the operand. It is used when identical operands
1928 must be printed differently depending on the context. CODE
1929 comes from the '%' specification that was used to request
1930 printing of the operand. If the specification was just '%DIGIT'
1931 then CODE is 0; if the specification was '%LTR DIGIT' then CODE
1932 is the ASCII code for LTR.
1934 If X is a register, this macro should print the register's name.
1935 The names can be found in an array 'reg_names' whose type is
1936 'char *[]'. 'reg_names' is initialized from 'REGISTER_NAMES'.
1938 When the machine description has a specification '%PUNCT' (a '%'
1939 followed by a punctuation character), this macro is called with
1940 a null pointer for X and the punctuation character for CODE.
1942 'a', 'c', 'l', and 'n' are reserved.
1944 The Xtensa specific codes are:
1946 'd' CONST_INT, print as signed decimal
1947 'x' CONST_INT, print as signed hexadecimal
1948 'K' CONST_INT, print number of bits in mask for EXTUI
1949 'R' CONST_INT, print (X & 0x1f)
1950 'L' CONST_INT, print ((32 - X) & 0x1f)
1951 'D' REG, print second register of double-word register operand
1952 'N' MEM, print address of next word following a memory operand
1953 'v' MEM, if memory reference is volatile, output a MEMW before it
1954 't' any constant, add "@h" suffix for top 16 bits
1955 'b' any constant, add "@l" suffix for bottom 16 bits
1959 printx (FILE *file, signed int val)
1961 /* Print a hexadecimal value in a nice way. */
1962 if ((val > -0xa) && (val < 0xa))
1963 fprintf (file, "%d", val);
1965 fprintf (file, "-0x%x", -val);
1967 fprintf (file, "0x%x", val);
1972 print_operand (FILE *file, rtx x, int letter)
1975 error ("PRINT_OPERAND null pointer");
1980 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
1981 fprintf (file, "%s", reg_names[xt_true_regnum (x) + 1]);
1983 output_operand_lossage ("invalid %%D value");
1987 if (GET_CODE (x) == MEM)
1989 /* For a volatile memory reference, emit a MEMW before the
1991 if (MEM_VOLATILE_P (x))
1992 fprintf (file, "memw\n\t");
1995 output_operand_lossage ("invalid %%v value");
1999 if (GET_CODE (x) == MEM
2000 && (GET_MODE (x) == DFmode || GET_MODE (x) == DImode))
2002 x = adjust_address (x, GET_MODE (x) == DFmode ? SFmode : SImode, 4);
2003 output_address (XEXP (x, 0));
2006 output_operand_lossage ("invalid %%N value");
2010 if (GET_CODE (x) == CONST_INT)
2013 unsigned val = INTVAL (x);
2019 if ((val != 0) || (num_bits == 0) || (num_bits > 16))
2020 fatal_insn ("invalid mask", x);
2022 fprintf (file, "%d", num_bits);
2025 output_operand_lossage ("invalid %%K value");
2029 if (GET_CODE (x) == CONST_INT)
2030 fprintf (file, "%ld", (32 - INTVAL (x)) & 0x1f);
2032 output_operand_lossage ("invalid %%L value");
2036 if (GET_CODE (x) == CONST_INT)
2037 fprintf (file, "%ld", INTVAL (x) & 0x1f);
2039 output_operand_lossage ("invalid %%R value");
2043 if (GET_CODE (x) == CONST_INT)
2044 printx (file, INTVAL (x));
2046 output_operand_lossage ("invalid %%x value");
2050 if (GET_CODE (x) == CONST_INT)
2051 fprintf (file, "%ld", INTVAL (x));
2053 output_operand_lossage ("invalid %%d value");
2058 if (GET_CODE (x) == CONST_INT)
2060 printx (file, INTVAL (x));
2061 fputs (letter == 't' ? "@h" : "@l", file);
2063 else if (GET_CODE (x) == CONST_DOUBLE)
2066 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2067 if (GET_MODE (x) == SFmode)
2070 REAL_VALUE_TO_TARGET_SINGLE (r, l);
2071 fprintf (file, "0x%08lx@%c", l, letter == 't' ? 'h' : 'l');
2074 output_operand_lossage ("invalid %%t/%%b value");
2076 else if (GET_CODE (x) == CONST)
2078 /* X must be a symbolic constant on ELF. Write an expression
2079 suitable for 'const16' that sets the high or low 16 bits. */
2080 if (GET_CODE (XEXP (x, 0)) != PLUS
2081 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
2082 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
2083 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
2084 output_operand_lossage ("invalid %%t/%%b value");
2085 print_operand (file, XEXP (XEXP (x, 0), 0), 0);
2086 fputs (letter == 't' ? "@h" : "@l", file);
2087 /* There must be a non-alphanumeric character between 'h' or 'l'
2088 and the number. The '-' is added by print_operand() already. */
2089 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
2091 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
2095 output_addr_const (file, x);
2096 fputs (letter == 't' ? "@h" : "@l", file);
2101 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
2102 fprintf (file, "%s", reg_names[xt_true_regnum (x)]);
2103 else if (GET_CODE (x) == MEM)
2104 output_address (XEXP (x, 0));
2105 else if (GET_CODE (x) == CONST_INT)
2106 fprintf (file, "%ld", INTVAL (x));
2108 output_addr_const (file, x);
2113 /* A C compound statement to output to stdio stream STREAM the
2114 assembler syntax for an instruction operand that is a memory
2115 reference whose address is ADDR. ADDR is an RTL expression. */
2118 print_operand_address (FILE *file, rtx addr)
2121 error ("PRINT_OPERAND_ADDRESS, null pointer");
2123 switch (GET_CODE (addr))
2126 fatal_insn ("invalid address", addr);
2130 fprintf (file, "%s, 0", reg_names [REGNO (addr)]);
2136 rtx offset = (rtx)0;
2137 rtx arg0 = XEXP (addr, 0);
2138 rtx arg1 = XEXP (addr, 1);
2140 if (GET_CODE (arg0) == REG)
2145 else if (GET_CODE (arg1) == REG)
2151 fatal_insn ("no register in address", addr);
2153 if (CONSTANT_P (offset))
2155 fprintf (file, "%s, ", reg_names [REGNO (reg)]);
2156 output_addr_const (file, offset);
2159 fatal_insn ("address offset not a constant", addr);
2167 output_addr_const (file, addr);
2174 xtensa_output_addr_const_extra (FILE *fp, rtx x)
2176 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
2178 switch (XINT (x, 1))
2183 output_addr_const (fp, XVECEXP (x, 0, 0));
2197 xtensa_output_literal (FILE *file, rtx x, enum machine_mode mode, int labelno)
2204 fprintf (file, "\t.literal .LC%u, ", (unsigned) labelno);
2206 switch (GET_MODE_CLASS (mode))
2209 gcc_assert (GET_CODE (x) == CONST_DOUBLE);
2211 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2215 REAL_VALUE_TO_TARGET_SINGLE (r, value_long[0]);
2216 if (HOST_BITS_PER_LONG > 32)
2217 value_long[0] &= 0xffffffff;
2218 fprintf (file, "0x%08lx\n", value_long[0]);
2222 REAL_VALUE_TO_TARGET_DOUBLE (r, value_long);
2223 if (HOST_BITS_PER_LONG > 32)
2225 value_long[0] &= 0xffffffff;
2226 value_long[1] &= 0xffffffff;
2228 fprintf (file, "0x%08lx, 0x%08lx\n",
2229 value_long[0], value_long[1]);
2239 case MODE_PARTIAL_INT:
2240 size = GET_MODE_SIZE (mode);
2244 output_addr_const (file, x);
2249 split_double (x, &first, &second);
2250 output_addr_const (file, first);
2252 output_addr_const (file, second);
2267 /* Return the bytes needed to compute the frame pointer from the current
2270 #define STACK_BYTES (STACK_BOUNDARY / BITS_PER_UNIT)
2271 #define XTENSA_STACK_ALIGN(LOC) (((LOC) + STACK_BYTES-1) & ~(STACK_BYTES-1))
2274 compute_frame_size (int size)
2276 /* Add space for the incoming static chain value. */
2277 if (cfun->static_chain_decl != NULL)
2278 size += (1 * UNITS_PER_WORD);
2280 xtensa_current_frame_size =
2281 XTENSA_STACK_ALIGN (size
2282 + current_function_outgoing_args_size
2283 + (WINDOW_SIZE * UNITS_PER_WORD));
2284 return xtensa_current_frame_size;
2289 xtensa_frame_pointer_required (void)
2291 /* The code to expand builtin_frame_addr and builtin_return_addr
2292 currently uses the hard_frame_pointer instead of frame_pointer.
2293 This seems wrong but maybe it's necessary for other architectures.
2294 This function is derived from the i386 code. */
2296 if (cfun->machine->accesses_prev_frame)
2304 xtensa_expand_prologue (void)
2306 HOST_WIDE_INT total_size;
2310 total_size = compute_frame_size (get_frame_size ());
2311 size_rtx = GEN_INT (total_size);
2313 if (total_size < (1 << (12+3)))
2314 insn = emit_insn (gen_entry (size_rtx, size_rtx));
2317 /* Use a8 as a temporary since a0-a7 may be live. */
2318 rtx tmp_reg = gen_rtx_REG (Pmode, A8_REG);
2319 emit_insn (gen_entry (size_rtx, GEN_INT (MIN_FRAME_SIZE)));
2320 emit_move_insn (tmp_reg, GEN_INT (total_size - MIN_FRAME_SIZE));
2321 emit_insn (gen_subsi3 (tmp_reg, stack_pointer_rtx, tmp_reg));
2322 insn = emit_insn (gen_movsi (stack_pointer_rtx, tmp_reg));
2325 if (frame_pointer_needed)
2327 if (cfun->machine->set_frame_ptr_insn)
2331 push_topmost_sequence ();
2332 first = get_insns ();
2333 pop_topmost_sequence ();
2335 /* For all instructions prior to set_frame_ptr_insn, replace
2336 hard_frame_pointer references with stack_pointer. */
2338 insn != cfun->machine->set_frame_ptr_insn;
2339 insn = NEXT_INSN (insn))
2343 PATTERN (insn) = replace_rtx (copy_rtx (PATTERN (insn)),
2344 hard_frame_pointer_rtx,
2346 df_insn_rescan (insn);
2351 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
2352 stack_pointer_rtx));
2355 /* Create a note to describe the CFA. Because this is only used to set
2356 DW_AT_frame_base for debug info, don't bother tracking changes through
2357 each instruction in the prologue. It just takes up space. */
2358 note_rtx = gen_rtx_SET (VOIDmode, (frame_pointer_needed
2359 ? hard_frame_pointer_rtx
2360 : stack_pointer_rtx),
2361 plus_constant (stack_pointer_rtx, -total_size));
2362 RTX_FRAME_RELATED_P (insn) = 1;
2363 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
2364 note_rtx, REG_NOTES (insn));
2368 /* Clear variables at function end. */
2371 xtensa_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
2372 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
2374 xtensa_current_frame_size = 0;
2379 xtensa_return_addr (int count, rtx frame)
2381 rtx result, retaddr;
2384 retaddr = gen_rtx_REG (Pmode, A0_REG);
2387 rtx addr = plus_constant (frame, -4 * UNITS_PER_WORD);
2388 addr = memory_address (Pmode, addr);
2389 retaddr = gen_reg_rtx (Pmode);
2390 emit_move_insn (retaddr, gen_rtx_MEM (Pmode, addr));
2393 /* The 2 most-significant bits of the return address on Xtensa hold
2394 the register window size. To get the real return address, these
2395 bits must be replaced with the high bits from the current PC. */
2397 result = gen_reg_rtx (Pmode);
2398 emit_insn (gen_fix_return_addr (result, retaddr));
2403 /* Create the va_list data type.
2405 This structure is set up by __builtin_saveregs. The __va_reg field
2406 points to a stack-allocated region holding the contents of the
2407 incoming argument registers. The __va_ndx field is an index
2408 initialized to the position of the first unnamed (variable)
2409 argument. This same index is also used to address the arguments
2410 passed in memory. Thus, the __va_stk field is initialized to point
2411 to the position of the first argument in memory offset to account
2412 for the arguments passed in registers and to account for the size
2413 of the argument registers not being 16-byte aligned. E.G., there
2414 are 6 argument registers of 4 bytes each, but we want the __va_ndx
2415 for the first stack argument to have the maximal alignment of 16
2416 bytes, so we offset the __va_stk address by 32 bytes so that
2417 __va_stk[32] references the first argument on the stack. */
2420 xtensa_build_builtin_va_list (void)
2422 tree f_stk, f_reg, f_ndx, record, type_decl;
2424 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
2425 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
2427 f_stk = build_decl (FIELD_DECL, get_identifier ("__va_stk"),
2429 f_reg = build_decl (FIELD_DECL, get_identifier ("__va_reg"),
2431 f_ndx = build_decl (FIELD_DECL, get_identifier ("__va_ndx"),
2434 DECL_FIELD_CONTEXT (f_stk) = record;
2435 DECL_FIELD_CONTEXT (f_reg) = record;
2436 DECL_FIELD_CONTEXT (f_ndx) = record;
2438 TREE_CHAIN (record) = type_decl;
2439 TYPE_NAME (record) = type_decl;
2440 TYPE_FIELDS (record) = f_stk;
2441 TREE_CHAIN (f_stk) = f_reg;
2442 TREE_CHAIN (f_reg) = f_ndx;
2444 layout_type (record);
2449 /* Save the incoming argument registers on the stack. Returns the
2450 address of the saved registers. */
2453 xtensa_builtin_saveregs (void)
2456 int arg_words = current_function_args_info.arg_words;
2457 int gp_left = MAX_ARGS_IN_REGISTERS - arg_words;
2462 /* Allocate the general-purpose register space. */
2463 gp_regs = assign_stack_local
2464 (BLKmode, MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD, -1);
2465 set_mem_alias_set (gp_regs, get_varargs_alias_set ());
2467 /* Now store the incoming registers. */
2468 cfun->machine->need_a7_copy = true;
2469 cfun->machine->vararg_a7 = true;
2470 move_block_from_reg (GP_ARG_FIRST + arg_words,
2471 adjust_address (gp_regs, BLKmode,
2472 arg_words * UNITS_PER_WORD),
2474 gcc_assert (cfun->machine->vararg_a7_copy != 0);
2475 emit_insn_before (cfun->machine->vararg_a7_copy, get_insns ());
2477 return XEXP (gp_regs, 0);
2481 /* Implement `va_start' for varargs and stdarg. We look at the
2482 current function to fill in an initial va_list. */
2485 xtensa_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
2493 arg_words = current_function_args_info.arg_words;
2495 f_stk = TYPE_FIELDS (va_list_type_node);
2496 f_reg = TREE_CHAIN (f_stk);
2497 f_ndx = TREE_CHAIN (f_reg);
2499 stk = build3 (COMPONENT_REF, TREE_TYPE (f_stk), valist, f_stk, NULL_TREE);
2500 reg = build3 (COMPONENT_REF, TREE_TYPE (f_reg), valist, f_reg, NULL_TREE);
2501 ndx = build3 (COMPONENT_REF, TREE_TYPE (f_ndx), valist, f_ndx, NULL_TREE);
2503 /* Call __builtin_saveregs; save the result in __va_reg */
2504 u = make_tree (sizetype, expand_builtin_saveregs ());
2505 u = fold_convert (ptr_type_node, u);
2506 t = build2 (GIMPLE_MODIFY_STMT, ptr_type_node, reg, u);
2507 TREE_SIDE_EFFECTS (t) = 1;
2508 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2510 /* Set the __va_stk member to ($arg_ptr - 32). */
2511 u = make_tree (ptr_type_node, virtual_incoming_args_rtx);
2512 u = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, u, size_int (-32));
2513 t = build2 (GIMPLE_MODIFY_STMT, ptr_type_node, stk, u);
2514 TREE_SIDE_EFFECTS (t) = 1;
2515 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2517 /* Set the __va_ndx member. If the first variable argument is on
2518 the stack, adjust __va_ndx by 2 words to account for the extra
2519 alignment offset for __va_stk. */
2520 if (arg_words >= MAX_ARGS_IN_REGISTERS)
2522 t = build2 (GIMPLE_MODIFY_STMT, integer_type_node, ndx,
2523 size_int (arg_words * UNITS_PER_WORD));
2524 TREE_SIDE_EFFECTS (t) = 1;
2525 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2529 /* Implement `va_arg'. */
2532 xtensa_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p,
2533 tree *post_p ATTRIBUTE_UNUSED)
2538 tree type_size, array, orig_ndx, addr, size, va_size, t;
2539 tree lab_false, lab_over, lab_false2;
2542 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, false);
2544 type = build_pointer_type (type);
2546 /* Handle complex values as separate real and imaginary parts. */
2547 if (TREE_CODE (type) == COMPLEX_TYPE)
2549 tree real_part, imag_part;
2551 real_part = xtensa_gimplify_va_arg_expr (valist, TREE_TYPE (type),
2553 real_part = get_initialized_tmp_var (real_part, pre_p, NULL);
2555 imag_part = xtensa_gimplify_va_arg_expr (valist, TREE_TYPE (type),
2557 imag_part = get_initialized_tmp_var (imag_part, pre_p, NULL);
2559 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
2562 f_stk = TYPE_FIELDS (va_list_type_node);
2563 f_reg = TREE_CHAIN (f_stk);
2564 f_ndx = TREE_CHAIN (f_reg);
2566 stk = build3 (COMPONENT_REF, TREE_TYPE (f_stk), valist, f_stk, NULL_TREE);
2567 reg = build3 (COMPONENT_REF, TREE_TYPE (f_reg), valist, f_reg, NULL_TREE);
2568 ndx = build3 (COMPONENT_REF, TREE_TYPE (f_ndx), valist, f_ndx, NULL_TREE);
2570 type_size = size_in_bytes (type);
2571 va_size = round_up (type_size, UNITS_PER_WORD);
2572 gimplify_expr (&va_size, pre_p, NULL, is_gimple_val, fb_rvalue);
2575 /* First align __va_ndx if necessary for this arg:
2577 orig_ndx = (AP).__va_ndx;
2578 if (__alignof__ (TYPE) > 4 )
2579 orig_ndx = ((orig_ndx + __alignof__ (TYPE) - 1)
2580 & -__alignof__ (TYPE)); */
2582 orig_ndx = get_initialized_tmp_var (ndx, pre_p, NULL);
2584 if (TYPE_ALIGN (type) > BITS_PER_WORD)
2586 int align = MIN (TYPE_ALIGN (type), STACK_BOUNDARY) / BITS_PER_UNIT;
2588 t = build2 (PLUS_EXPR, integer_type_node, orig_ndx, size_int (align - 1));
2589 t = build2 (BIT_AND_EXPR, integer_type_node, t, size_int (-align));
2590 t = build2 (GIMPLE_MODIFY_STMT, integer_type_node, orig_ndx, t);
2591 gimplify_and_add (t, pre_p);
2595 /* Increment __va_ndx to point past the argument:
2597 (AP).__va_ndx = orig_ndx + __va_size (TYPE); */
2599 t = fold_convert (integer_type_node, va_size);
2600 t = build2 (PLUS_EXPR, integer_type_node, orig_ndx, t);
2601 t = build2 (GIMPLE_MODIFY_STMT, integer_type_node, ndx, t);
2602 gimplify_and_add (t, pre_p);
2605 /* Check if the argument is in registers:
2607 if ((AP).__va_ndx <= __MAX_ARGS_IN_REGISTERS * 4
2608 && !must_pass_in_stack (type))
2609 __array = (AP).__va_reg; */
2611 array = create_tmp_var (ptr_type_node, NULL);
2614 if (!targetm.calls.must_pass_in_stack (TYPE_MODE (type), type))
2616 lab_false = create_artificial_label ();
2617 lab_over = create_artificial_label ();
2619 t = build2 (GT_EXPR, boolean_type_node, ndx,
2620 size_int (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD));
2621 t = build3 (COND_EXPR, void_type_node, t,
2622 build1 (GOTO_EXPR, void_type_node, lab_false),
2624 gimplify_and_add (t, pre_p);
2626 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, array, reg);
2627 gimplify_and_add (t, pre_p);
2629 t = build1 (GOTO_EXPR, void_type_node, lab_over);
2630 gimplify_and_add (t, pre_p);
2632 t = build1 (LABEL_EXPR, void_type_node, lab_false);
2633 gimplify_and_add (t, pre_p);
2637 /* ...otherwise, the argument is on the stack (never split between
2638 registers and the stack -- change __va_ndx if necessary):
2642 if (orig_ndx <= __MAX_ARGS_IN_REGISTERS * 4)
2643 (AP).__va_ndx = 32 + __va_size (TYPE);
2644 __array = (AP).__va_stk;
2647 lab_false2 = create_artificial_label ();
2649 t = build2 (GT_EXPR, boolean_type_node, orig_ndx,
2650 size_int (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD));
2651 t = build3 (COND_EXPR, void_type_node, t,
2652 build1 (GOTO_EXPR, void_type_node, lab_false2),
2654 gimplify_and_add (t, pre_p);
2656 t = size_binop (PLUS_EXPR, va_size, size_int (32));
2657 t = fold_convert (integer_type_node, t);
2658 t = build2 (GIMPLE_MODIFY_STMT, integer_type_node, ndx, t);
2659 gimplify_and_add (t, pre_p);
2661 t = build1 (LABEL_EXPR, void_type_node, lab_false2);
2662 gimplify_and_add (t, pre_p);
2664 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, array, stk);
2665 gimplify_and_add (t, pre_p);
2669 t = build1 (LABEL_EXPR, void_type_node, lab_over);
2670 gimplify_and_add (t, pre_p);
2674 /* Given the base array pointer (__array) and index to the subsequent
2675 argument (__va_ndx), find the address:
2677 __array + (AP).__va_ndx - (BYTES_BIG_ENDIAN && sizeof (TYPE) < 4
2681 The results are endian-dependent because values smaller than one word
2682 are aligned differently. */
2685 if (BYTES_BIG_ENDIAN && TREE_CODE (type_size) == INTEGER_CST)
2687 t = fold_build2 (GE_EXPR, boolean_type_node, type_size,
2688 size_int (PARM_BOUNDARY / BITS_PER_UNIT));
2689 t = fold_build3 (COND_EXPR, sizetype, t, va_size, type_size);
2695 t = build2 (MINUS_EXPR, sizetype, ndx, size);
2696 addr = build2 (POINTER_PLUS_EXPR, ptr_type_node, array, t);
2698 addr = fold_convert (build_pointer_type (type), addr);
2700 addr = build_va_arg_indirect_ref (addr);
2701 return build_va_arg_indirect_ref (addr);
2709 XTENSA_BUILTIN_UMULSIDI3,
2715 xtensa_init_builtins (void)
2719 ftype = build_function_type_list (unsigned_intDI_type_node,
2720 unsigned_intSI_type_node,
2721 unsigned_intSI_type_node, NULL_TREE);
2723 add_builtin_function ("__builtin_umulsidi3", ftype,
2724 XTENSA_BUILTIN_UMULSIDI3, BUILT_IN_MD,
2725 "__umulsidi3", NULL_TREE);
2730 xtensa_fold_builtin (tree fndecl, tree arglist, bool ignore ATTRIBUTE_UNUSED)
2732 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
2735 if (fcode == XTENSA_BUILTIN_UMULSIDI3)
2737 arg0 = TREE_VALUE (arglist);
2738 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
2739 if ((TREE_CODE (arg0) == INTEGER_CST && TREE_CODE (arg1) == INTEGER_CST)
2740 || TARGET_MUL32_HIGH)
2741 return fold_build2 (MULT_EXPR, unsigned_intDI_type_node,
2742 fold_convert (unsigned_intDI_type_node, arg0),
2743 fold_convert (unsigned_intDI_type_node, arg1));
2748 internal_error ("bad builtin code");
2754 xtensa_expand_builtin (tree exp, rtx target,
2755 rtx subtarget ATTRIBUTE_UNUSED,
2756 enum machine_mode mode ATTRIBUTE_UNUSED,
2759 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
2760 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
2762 /* The umulsidi3 builtin is just a mechanism to avoid calling the real
2763 __umulsidi3 function when the Xtensa configuration can directly
2764 implement it. If not, just call the function. */
2765 if (fcode == XTENSA_BUILTIN_UMULSIDI3)
2766 return expand_call (exp, target, ignore);
2768 internal_error ("bad builtin code");
2774 xtensa_preferred_reload_class (rtx x, enum reg_class class, int isoutput)
2776 if (!isoutput && CONSTANT_P (x) && GET_CODE (x) == CONST_DOUBLE)
2779 /* Don't use the stack pointer or hard frame pointer for reloads!
2780 The hard frame pointer would normally be OK except that it may
2781 briefly hold an incoming argument in the prologue, and reload
2782 won't know that it is live because the hard frame pointer is
2783 treated specially. */
2785 if (class == AR_REGS || class == GR_REGS)
2793 xtensa_secondary_reload_class (enum reg_class class,
2794 enum machine_mode mode ATTRIBUTE_UNUSED,
2795 rtx x, int isoutput)
2799 if (GET_CODE (x) == SIGN_EXTEND)
2801 regno = xt_true_regnum (x);
2805 if (class == FP_REGS && constantpool_mem_p (x))
2809 if (ACC_REG_P (regno))
2810 return ((class == GR_REGS || class == RL_REGS) ? NO_REGS : RL_REGS);
2811 if (class == ACC_REG)
2812 return (GP_REG_P (regno) ? NO_REGS : RL_REGS);
2819 order_regs_for_local_alloc (void)
2821 if (!leaf_function_p ())
2823 memcpy (reg_alloc_order, reg_nonleaf_alloc_order,
2824 FIRST_PSEUDO_REGISTER * sizeof (int));
2828 int i, num_arg_regs;
2831 /* Use the AR registers in increasing order (skipping a0 and a1)
2832 but save the incoming argument registers for a last resort. */
2833 num_arg_regs = current_function_args_info.arg_words;
2834 if (num_arg_regs > MAX_ARGS_IN_REGISTERS)
2835 num_arg_regs = MAX_ARGS_IN_REGISTERS;
2836 for (i = GP_ARG_FIRST; i < 16 - num_arg_regs; i++)
2837 reg_alloc_order[nxt++] = i + num_arg_regs;
2838 for (i = 0; i < num_arg_regs; i++)
2839 reg_alloc_order[nxt++] = GP_ARG_FIRST + i;
2841 /* List the coprocessor registers in order. */
2842 for (i = 0; i < BR_REG_NUM; i++)
2843 reg_alloc_order[nxt++] = BR_REG_FIRST + i;
2845 /* List the FP registers in order for now. */
2846 for (i = 0; i < 16; i++)
2847 reg_alloc_order[nxt++] = FP_REG_FIRST + i;
2849 /* GCC requires that we list *all* the registers.... */
2850 reg_alloc_order[nxt++] = 0; /* a0 = return address */
2851 reg_alloc_order[nxt++] = 1; /* a1 = stack pointer */
2852 reg_alloc_order[nxt++] = 16; /* pseudo frame pointer */
2853 reg_alloc_order[nxt++] = 17; /* pseudo arg pointer */
2855 reg_alloc_order[nxt++] = ACC_REG_FIRST; /* MAC16 accumulator */
2860 /* Some Xtensa targets support multiple bss sections. If the section
2861 name ends with ".bss", add SECTION_BSS to the flags. */
2864 xtensa_multibss_section_type_flags (tree decl, const char *name, int reloc)
2866 unsigned int flags = default_section_type_flags (decl, name, reloc);
2869 suffix = strrchr (name, '.');
2870 if (suffix && strcmp (suffix, ".bss") == 0)
2872 if (!decl || (TREE_CODE (decl) == VAR_DECL
2873 && DECL_INITIAL (decl) == NULL_TREE))
2874 flags |= SECTION_BSS; /* @nobits */
2876 warning (0, "only uninitialized variables can be placed in a "
2884 /* The literal pool stays with the function. */
2887 xtensa_select_rtx_section (enum machine_mode mode ATTRIBUTE_UNUSED,
2888 rtx x ATTRIBUTE_UNUSED,
2889 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
2891 return function_section (current_function_decl);
2895 /* Compute a (partial) cost for rtx X. Return true if the complete
2896 cost has been computed, and false if subexpressions should be
2897 scanned. In either case, *TOTAL contains the cost result. */
2900 xtensa_rtx_costs (rtx x, int code, int outer_code, int *total)
2908 if (xtensa_simm12b (INTVAL (x)))
2915 if (xtensa_simm8 (INTVAL (x))
2916 || xtensa_simm8x256 (INTVAL (x)))
2923 if (xtensa_mask_immediate (INTVAL (x)))
2930 if ((INTVAL (x) == 0) || xtensa_b4const (INTVAL (x)))
2941 /* No way to tell if X is the 2nd operand so be conservative. */
2944 if (xtensa_simm12b (INTVAL (x)))
2946 else if (TARGET_CONST16)
2947 *total = COSTS_N_INSNS (2);
2956 *total = COSTS_N_INSNS (2);
2963 *total = COSTS_N_INSNS (4);
2971 (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD) ? 2 : 1;
2973 if (memory_address_p (GET_MODE (x), XEXP ((x), 0)))
2974 *total = COSTS_N_INSNS (num_words);
2976 *total = COSTS_N_INSNS (2*num_words);
2982 *total = COSTS_N_INSNS (TARGET_NSA ? 5 : 50);
2986 *total = COSTS_N_INSNS (TARGET_NSA ? 1 : 50);
2990 *total = COSTS_N_INSNS ((GET_MODE (x) == DImode) ? 3 : 2);
2996 if (GET_MODE (x) == DImode)
2997 *total = COSTS_N_INSNS (2);
2999 *total = COSTS_N_INSNS (1);
3005 if (GET_MODE (x) == DImode)
3006 *total = COSTS_N_INSNS (50);
3008 *total = COSTS_N_INSNS (1);
3013 enum machine_mode xmode = GET_MODE (x);
3014 if (xmode == SFmode)
3015 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 1 : 50);
3016 else if (xmode == DFmode)
3017 *total = COSTS_N_INSNS (50);
3019 *total = COSTS_N_INSNS (4);
3026 enum machine_mode xmode = GET_MODE (x);
3027 if (xmode == SFmode)
3028 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 1 : 50);
3029 else if (xmode == DFmode || xmode == DImode)
3030 *total = COSTS_N_INSNS (50);
3032 *total = COSTS_N_INSNS (1);
3037 *total = COSTS_N_INSNS ((GET_MODE (x) == DImode) ? 4 : 2);
3042 enum machine_mode xmode = GET_MODE (x);
3043 if (xmode == SFmode)
3044 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 4 : 50);
3045 else if (xmode == DFmode)
3046 *total = COSTS_N_INSNS (50);
3047 else if (xmode == DImode)
3048 *total = COSTS_N_INSNS (TARGET_MUL32_HIGH ? 10 : 50);
3049 else if (TARGET_MUL32)
3050 *total = COSTS_N_INSNS (4);
3051 else if (TARGET_MAC16)
3052 *total = COSTS_N_INSNS (16);
3053 else if (TARGET_MUL16)
3054 *total = COSTS_N_INSNS (12);
3056 *total = COSTS_N_INSNS (50);
3063 enum machine_mode xmode = GET_MODE (x);
3064 if (xmode == SFmode)
3066 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT_DIV ? 8 : 50);
3069 else if (xmode == DFmode)
3071 *total = COSTS_N_INSNS (50);
3080 enum machine_mode xmode = GET_MODE (x);
3081 if (xmode == DImode)
3082 *total = COSTS_N_INSNS (50);
3083 else if (TARGET_DIV32)
3084 *total = COSTS_N_INSNS (32);
3086 *total = COSTS_N_INSNS (50);
3091 if (GET_MODE (x) == SFmode)
3092 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT_SQRT ? 8 : 50);
3094 *total = COSTS_N_INSNS (50);
3101 *total = COSTS_N_INSNS (TARGET_MINMAX ? 1 : 50);
3106 *total = COSTS_N_INSNS (TARGET_SEXT ? 1 : 2);
3111 *total = COSTS_N_INSNS (1);
3119 /* Worker function for TARGET_RETURN_IN_MEMORY. */
3122 xtensa_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
3124 return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type)
3125 > 4 * UNITS_PER_WORD);
3128 #include "gt-xtensa.h"