1 ;; Machine description for GNU compiler, VAX Version
2 ;; Copyright (C) 1987, 1988, 1991, 1994, 1995, 1996, 1998, 1999, 2000, 2001,
3 ;; 2002, 2004, 2005, 2007, 2009 Free Software Foundation, Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
22 ;;- Instruction patterns. When multiple patterns apply,
23 ;;- the first one in the file is chosen.
25 ;;- See file "rtl.def" for documentation on define_insn, match_*, et al.
27 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
28 ;;- updates for most instructions.
30 ;; UNSPEC_VOLATILE usage:
33 [(VUNSPEC_BLOCKAGE 0) ; `blockage' insn to prevent scheduling across an
35 (VUNSPEC_SYNC_ISTREAM 1) ; sequence of insns to sync the I-stream
36 (VAX_AP_REGNUM 12) ; Register 12 contains the argument pointer
37 (VAX_FP_REGNUM 13) ; Register 13 contains the frame pointer
38 (VAX_SP_REGNUM 14) ; Register 14 contains the stack pointer
39 (VAX_PC_REGNUM 15) ; Register 15 contains the program counter
43 ;; Integer modes supported on VAX, with a mapping from machine mode
44 ;; to mnemonic suffix. DImode is always a special case.
45 (define_mode_iterator VAXint [QI HI SI])
46 (define_mode_iterator VAXintQH [QI HI])
47 (define_mode_iterator VAXintQHSD [QI HI SI DI])
48 (define_mode_attr isfx [(QI "b") (HI "w") (SI "l") (DI "q")])
50 ;; Similar for float modes supported on VAX.
51 (define_mode_iterator VAXfp [SF DF])
52 (define_mode_attr fsfx [(SF "f") (DF "%#")])
54 ;; Some output patterns want integer immediates with a prefix...
55 (define_mode_attr iprefx [(QI "B") (HI "H") (SI "N")])
58 (include "constraints.md")
59 (include "predicates.md")
61 (define_insn "*cmp<mode>"
63 (compare (match_operand:VAXint 0 "nonimmediate_operand" "nrmT,nrmT")
64 (match_operand:VAXint 1 "general_operand" "I,nrmT")))]
68 cmp<VAXint:isfx> %0,%1")
70 (define_insn "*cmp<mode>"
72 (compare (match_operand:VAXfp 0 "general_operand" "gF,gF")
73 (match_operand:VAXfp 1 "general_operand" "G,gF")))]
77 cmp<VAXfp:fsfx> %0,%1")
79 (define_insn "*bit<mode>"
81 (compare (and:VAXint (match_operand:VAXint 0 "general_operand" "nrmT")
82 (match_operand:VAXint 1 "general_operand" "nrmT"))
85 "bit<VAXint:isfx> %0,%1")
87 ;; The VAX has no sCOND insns. It does have add/subtract with carry
88 ;; which could be used to implement the sltu and sgeu patterns. However,
89 ;; to do this properly requires a complete rewrite of the compare insns
90 ;; to keep them together with the sltu/sgeu insns until after the
91 ;; reload pass is complete. The previous implementation didn't do this
92 ;; and has been deleted.
95 (define_insn "mov<mode>"
96 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g")
97 (match_operand:VAXfp 1 "general_operand" "G,gF"))]
101 mov<VAXfp:fsfx> %1,%0")
103 ;; Some VAXen don't support this instruction.
104 ;;(define_insn "movti"
105 ;; [(set (match_operand:TI 0 "general_operand" "=g")
106 ;; (match_operand:TI 1 "general_operand" "g"))]
111 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
112 (match_operand:DI 1 "general_operand" "g"))]
114 "* return vax_output_int_move (insn, operands, DImode);")
116 ;; The VAX move instructions have space-time tradeoffs. On a MicroVAX
117 ;; register-register mov instructions take 3 bytes and 2 CPU cycles. clrl
118 ;; takes 2 bytes and 3 cycles. mov from constant to register takes 2 cycles
119 ;; if the constant is smaller than 4 bytes, 3 cycles for a longword
120 ;; constant. movz, mneg, and mcom are as fast as mov, so movzwl is faster
121 ;; than movl for positive constants that fit in 16 bits but not 6 bits. cvt
122 ;; instructions take 4 cycles. inc takes 3 cycles. The machine description
123 ;; is willing to trade 1 byte for 1 cycle (clrl instead of movl $0; cvtwl
126 ;; Cycle counts for other models may vary (on a VAX 750 they are similar,
127 ;; but on a VAX 9000 most move and add instructions with one constant
128 ;; operand take 1 cycle).
130 ;; Loads of constants between 64 and 128 used to be done with
131 ;; "addl3 $63,#,dst" but this is slower than movzbl and takes as much space.
133 (define_expand "movsi"
134 [(set (match_operand:SI 0 "nonimmediate_operand" "")
135 (match_operand:SI 1 "general_operand" ""))]
139 #ifdef NO_EXTERNAL_INDIRECT_ADDRESS
141 && GET_CODE (operands[1]) == CONST
142 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF
143 && !SYMBOL_REF_LOCAL_P (XEXP (XEXP (operands[1], 0), 0)))
145 rtx symbol_ref = XEXP (XEXP (operands[1], 0), 0);
146 rtx const_int = XEXP (XEXP (operands[1], 0), 1);
147 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
148 emit_move_insn (temp, symbol_ref);
149 emit_move_insn (operands[0], gen_rtx_PLUS (SImode, temp, const_int));
155 (define_insn "movsi_2"
156 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
157 (match_operand:SI 1 "nonsymbolic_operand" "nrmT"))]
159 "* return vax_output_int_move (insn, operands, SImode);")
161 (define_insn "mov<mode>"
162 [(set (match_operand:VAXintQH 0 "nonimmediate_operand" "=g")
163 (match_operand:VAXintQH 1 "general_operand" "g"))]
165 "* return vax_output_int_move (insn, operands, <MODE>mode);")
167 (define_insn "movstricthi"
168 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+g"))
169 (match_operand:HI 1 "general_operand" "g"))]
173 if (CONST_INT_P (operands[1]))
175 int i = INTVAL (operands[1]);
178 else if ((unsigned int)i < 64)
179 return \"movw %1,%0\";
180 else if ((unsigned int)~i < 64)
181 return \"mcomw %H1,%0\";
182 else if ((unsigned int)i < 256)
183 return \"movzbw %1,%0\";
185 return \"movw %1,%0\";
188 (define_insn "movstrictqi"
189 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+g"))
190 (match_operand:QI 1 "general_operand" "g"))]
194 if (CONST_INT_P (operands[1]))
196 int i = INTVAL (operands[1]);
199 else if ((unsigned int)~i < 64)
200 return \"mcomb %B1,%0\";
202 return \"movb %1,%0\";
205 ;; This is here to accept 4 arguments and pass the first 3 along
206 ;; to the movmemhi1 pattern that really does the work.
207 (define_expand "movmemhi"
208 [(set (match_operand:BLK 0 "general_operand" "=g")
209 (match_operand:BLK 1 "general_operand" "g"))
210 (use (match_operand:HI 2 "general_operand" "g"))
211 (match_operand 3 "" "")]
215 emit_insn (gen_movmemhi1 (operands[0], operands[1], operands[2]));
219 ;; The definition of this insn does not really explain what it does,
220 ;; but it should suffice
221 ;; that anything generated as this insn will be recognized as one
222 ;; and that it won't successfully combine with anything.
224 (define_insn "movmemhi1"
225 [(set (match_operand:BLK 0 "memory_operand" "=o")
226 (match_operand:BLK 1 "memory_operand" "o"))
227 (use (match_operand:HI 2 "general_operand" "g"))
233 (clobber (reg:SI 5))]
237 ;; Extension and truncation insns.
239 (define_insn "truncsiqi2"
240 [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
241 (truncate:QI (match_operand:SI 1 "nonimmediate_operand" "nrmT")))]
245 (define_insn "truncsihi2"
246 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
247 (truncate:HI (match_operand:SI 1 "nonimmediate_operand" "nrmT")))]
251 (define_insn "trunchiqi2"
252 [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
253 (truncate:QI (match_operand:HI 1 "nonimmediate_operand" "g")))]
257 (define_insn "extendhisi2"
258 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
259 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
263 (define_insn "extendqihi2"
264 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
265 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
269 (define_insn "extendqisi2"
270 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
271 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
275 (define_insn "extendsfdf2"
276 [(set (match_operand:DF 0 "nonimmediate_operand" "=g")
277 (float_extend:DF (match_operand:SF 1 "general_operand" "gF")))]
281 (define_insn "truncdfsf2"
282 [(set (match_operand:SF 0 "nonimmediate_operand" "=g")
283 (float_truncate:SF (match_operand:DF 1 "general_operand" "gF")))]
287 (define_insn "zero_extendhisi2"
288 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
289 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
293 (define_insn "zero_extendqihi2"
294 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
295 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
299 (define_insn "zero_extendqisi2"
300 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
301 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
305 ;; Fix-to-float conversion insns.
307 (define_insn "float<VAXint:mode><VAXfp:mode>2"
308 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g")
309 (float:VAXfp (match_operand:VAXint 1 "nonimmediate_operand" "g")))]
311 "cvt<VAXint:isfx><VAXfp:fsfx> %1,%0")
313 ;; Float-to-fix conversion insns.
315 (define_insn "fix_trunc<VAXfp:mode><VAXint:mode>2"
316 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
317 (fix:VAXint (fix:VAXfp (match_operand:VAXfp 1 "general_operand" "gF"))))]
319 "cvt<VAXfp:fsfx><VAXint:isfx> %1,%0")
321 ;;- All kinds of add instructions.
323 (define_insn "add<mode>3"
324 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g,g")
325 (plus:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF,gF")
326 (match_operand:VAXfp 2 "general_operand" "gF,0,gF")))]
329 add<VAXfp:fsfx>2 %2,%0
330 add<VAXfp:fsfx>2 %1,%0
331 add<VAXfp:fsfx>3 %1,%2,%0")
333 (define_insn "pushlclsymreg"
334 [(set (match_operand:SI 0 "push_operand" "=g")
335 (plus:SI (match_operand:SI 1 "register_operand" "%r")
336 (match_operand:SI 2 "local_symbolic_operand" "i")))]
340 (define_insn "pushextsymreg"
341 [(set (match_operand:SI 0 "push_operand" "=g")
342 (plus:SI (match_operand:SI 1 "register_operand" "%r")
343 (match_operand:SI 2 "external_symbolic_operand" "i")))]
347 (define_insn "movlclsymreg"
348 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
349 (plus:SI (match_operand:SI 1 "register_operand" "%r")
350 (match_operand:SI 2 "local_symbolic_operand" "i")))]
354 (define_insn "movextsymreg"
355 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
356 (plus:SI (match_operand:SI 1 "register_operand" "%r")
357 (match_operand:SI 2 "external_symbolic_operand" "i")))]
361 (define_insn "add<mode>3"
362 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
363 (plus:VAXint (match_operand:VAXint 1 "general_operand" "nrmT")
364 (match_operand:VAXint 2 "general_operand" "nrmT")))]
366 "* return vax_output_int_add (insn, operands, <MODE>mode);")
368 (define_expand "adddi3"
369 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
370 (plus:DI (match_operand:DI 1 "general_operand" "g")
371 (match_operand:DI 2 "general_operand" "g")))]
372 "!reload_in_progress"
373 "vax_expand_addsub_di_operands (operands, PLUS); DONE;")
375 (define_insn "adcdi3"
376 [(set (match_operand:DI 0 "nonimmediate_addsub_di_operand" "=Rr")
377 (plus:DI (match_operand:DI 1 "general_addsub_di_operand" "%0")
378 (match_operand:DI 2 "general_addsub_di_operand" "nRr")))]
380 "* return vax_output_int_add (insn, operands, DImode);")
382 ;; The add-with-carry (adwc) instruction only accepts two operands.
383 (define_insn "adddi3_old"
384 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro>,ro>")
385 (plus:DI (match_operand:DI 1 "general_operand" "%0,ro>")
386 (match_operand:DI 2 "general_operand" "Fsro,Fs")))]
388 "* return vax_output_int_add (insn, operands, DImode);")
390 ;;- All kinds of subtract instructions.
392 (define_insn "sub<mode>3"
393 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g")
394 (minus:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF")
395 (match_operand:VAXfp 2 "general_operand" "gF,gF")))]
398 sub<VAXfp:fsfx>2 %2,%0
399 sub<VAXfp:fsfx>3 %2,%1,%0")
401 (define_insn "sub<mode>3"
402 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
403 (minus:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT")
404 (match_operand:VAXint 2 "general_operand" "nrmT,nrmT")))]
407 sub<VAXint:isfx>2 %2,%0
408 sub<VAXint:isfx>3 %2,%1,%0")
410 (define_expand "subdi3"
411 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
412 (minus:DI (match_operand:DI 1 "general_operand" "g")
413 (match_operand:DI 2 "general_operand" "g")))]
414 "!reload_in_progress"
415 "vax_expand_addsub_di_operands (operands, MINUS); DONE;")
417 (define_insn "sbcdi3"
418 [(set (match_operand:DI 0 "nonimmediate_addsub_di_operand" "=Rr,=Rr")
419 (minus:DI (match_operand:DI 1 "general_addsub_di_operand" "0,I")
420 (match_operand:DI 2 "general_addsub_di_operand" "nRr,Rr")))]
422 "* return vax_output_int_subtract (insn, operands, DImode);")
424 ;; The subtract-with-carry (sbwc) instruction only takes two operands.
425 (define_insn "subdi3_old"
426 [(set (match_operand:DI 0 "nonimmediate_operand" "=or>,or>")
427 (minus:DI (match_operand:DI 1 "general_operand" "0,or>")
428 (match_operand:DI 2 "general_operand" "Fsor,Fs")))]
430 "* return vax_output_int_subtract (insn, operands, DImode);")
432 ;;- Multiply instructions.
434 (define_insn "mul<mode>3"
435 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g,g")
436 (mult:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF,gF")
437 (match_operand:VAXfp 2 "general_operand" "gF,0,gF")))]
440 mul<VAXfp:fsfx>2 %2,%0
441 mul<VAXfp:fsfx>2 %1,%0
442 mul<VAXfp:fsfx>3 %1,%2,%0")
444 (define_insn "mul<mode>3"
445 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g")
446 (mult:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT")
447 (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT")))]
450 mul<VAXint:isfx>2 %2,%0
451 mul<VAXint:isfx>2 %1,%0
452 mul<VAXint:isfx>3 %1,%2,%0")
454 (define_insn "mulsidi3"
455 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
456 (mult:DI (sign_extend:DI
457 (match_operand:SI 1 "nonimmediate_operand" "nrmT"))
459 (match_operand:SI 2 "nonimmediate_operand" "nrmT"))))]
464 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
466 (mult:DI (sign_extend:DI
467 (match_operand:SI 1 "nonimmediate_operand" "nrmT"))
469 (match_operand:SI 2 "nonimmediate_operand" "nrmT")))
470 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "g"))))]
474 ;; 'F' constraint means type CONST_DOUBLE
476 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
478 (mult:DI (sign_extend:DI
479 (match_operand:SI 1 "nonimmediate_operand" "nrmT"))
481 (match_operand:SI 2 "nonimmediate_operand" "nrmT")))
482 (match_operand:DI 3 "immediate_operand" "F")))]
483 "GET_CODE (operands[3]) == CONST_DOUBLE
484 && CONST_DOUBLE_HIGH (operands[3]) == (CONST_DOUBLE_LOW (operands[3]) >> 31)"
487 if (CONST_DOUBLE_HIGH (operands[3]))
488 operands[3] = GEN_INT (CONST_DOUBLE_LOW (operands[3]));
489 return \"emul %1,%2,%3,%0\";
492 ;;- Divide instructions.
494 (define_insn "div<mode>3"
495 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g")
496 (div:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF")
497 (match_operand:VAXfp 2 "general_operand" "gF,gF")))]
500 div<VAXfp:fsfx>2 %2,%0
501 div<VAXfp:fsfx>3 %2,%1,%0")
503 (define_insn "div<mode>3"
504 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
505 (div:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT")
506 (match_operand:VAXint 2 "general_operand" "nrmT,nrmT")))]
509 div<VAXint:isfx>2 %2,%0
510 div<VAXint:isfx>3 %2,%1,%0")
512 ;This is left out because it is very slow;
513 ;we are better off programming around the "lack" of this insn.
514 ;(define_insn "divmoddisi4"
515 ; [(set (match_operand:SI 0 "general_operand" "=g")
516 ; (div:SI (match_operand:DI 1 "general_operand" "g")
517 ; (match_operand:SI 2 "general_operand" "g")))
518 ; (set (match_operand:SI 3 "general_operand" "=g")
519 ; (mod:SI (match_operand:DI 1 "general_operand" "g")
520 ; (match_operand:SI 2 "general_operand" "g")))]
522 ; "ediv %2,%1,%0,%3")
524 ;; Bit-and on the VAX is done with a clear-bits insn.
525 (define_expand "and<mode>3"
526 [(set (match_operand:VAXint 0 "nonimmediate_operand" "")
527 (and:VAXint (not:VAXint (match_operand:VAXint 1 "general_operand" ""))
528 (match_operand:VAXint 2 "general_operand" "")))]
532 rtx op1 = operands[1];
534 /* If there is a constant argument, complement that one. */
535 if (CONST_INT_P (operands[2]) && ! CONST_INT_P (op1))
537 operands[1] = operands[2];
542 if (CONST_INT_P (op1))
543 operands[1] = GEN_INT (~INTVAL (op1));
545 operands[1] = expand_unop (<MODE>mode, one_cmpl_optab, op1, 0, 1);
548 (define_insn "*and<mode>"
549 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
550 (and:VAXint (not:VAXint (match_operand:VAXint 1 "general_operand" "nrmT,nrmT"))
551 (match_operand:VAXint 2 "general_operand" "0,nrmT")))]
554 bic<VAXint:isfx>2 %1,%0
555 bic<VAXint:isfx>3 %1,%2,%0")
557 ;; The following used to be needed because constant propagation can
558 ;; create them starting from the bic insn patterns above. This is no
559 ;; longer a problem. However, having these patterns allows optimization
560 ;; opportunities in combine.c.
562 (define_insn "*and<mode>_const_int"
563 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
564 (and:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT")
565 (match_operand:VAXint 2 "const_int_operand" "n,n")))]
568 bic<VAXint:isfx>2 %<VAXint:iprefx>2,%0
569 bic<VAXint:isfx>3 %<VAXint:iprefx>2,%1,%0")
572 ;;- Bit set instructions.
574 (define_insn "ior<mode>3"
575 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g")
576 (ior:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT")
577 (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT")))]
580 bis<VAXint:isfx>2 %2,%0
581 bis<VAXint:isfx>2 %1,%0
582 bis<VAXint:isfx>3 %2,%1,%0")
584 ;;- xor instructions.
586 (define_insn "xor<mode>3"
587 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g")
588 (xor:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT")
589 (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT")))]
592 xor<VAXint:isfx>2 %2,%0
593 xor<VAXint:isfx>2 %1,%0
594 xor<VAXint:isfx>3 %2,%1,%0")
597 (define_insn "neg<mode>2"
598 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g")
599 (neg:VAXfp (match_operand:VAXfp 1 "general_operand" "gF")))]
601 "mneg<VAXfp:fsfx> %1,%0")
603 (define_insn "neg<mode>2"
604 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
605 (neg:VAXint (match_operand:VAXint 1 "general_operand" "nrmT")))]
607 "mneg<VAXint:isfx> %1,%0")
609 (define_insn "one_cmpl<mode>2"
610 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
611 (not:VAXint (match_operand:VAXint 1 "general_operand" "nrmT")))]
613 "mcom<VAXint:isfx> %1,%0")
616 ;; Arithmetic right shift on the VAX works by negating the shift count,
617 ;; then emitting a right shift with the shift count negated. This means
618 ;; that all actual shift counts in the RTL will be positive. This
619 ;; prevents converting shifts to ZERO_EXTRACTs with negative positions,
620 ;; which isn't valid.
621 (define_expand "ashrsi3"
622 [(set (match_operand:SI 0 "general_operand" "=g")
623 (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
624 (match_operand:QI 2 "general_operand" "g")))]
628 if (! CONST_INT_P(operands[2]))
629 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
633 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
634 (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT")
635 (match_operand:QI 2 "const_int_operand" "n")))]
640 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
641 (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT")
642 (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
646 (define_insn "ashlsi3"
647 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
648 (ashift:SI (match_operand:SI 1 "general_operand" "nrmT")
649 (match_operand:QI 2 "general_operand" "g")))]
653 if (operands[2] == const1_rtx && rtx_equal_p (operands[0], operands[1]))
654 return \"addl2 %0,%0\";
655 if (REG_P (operands[1]) && CONST_INT_P (operands[2]))
657 int i = INTVAL (operands[2]);
659 return \"addl3 %1,%1,%0\";
660 if (i == 2 && !optimize_size)
662 if (push_operand (operands[0], SImode))
663 return \"pushal 0[%1]\";
664 return \"moval 0[%1],%0\";
666 if (i == 3 && !optimize_size)
668 if (push_operand (operands[0], SImode))
669 return \"pushaq 0[%1]\";
670 return \"movaq 0[%1],%0\";
673 return \"ashl %2,%1,%0\";
676 ;; Arithmetic right shift on the VAX works by negating the shift count.
677 (define_expand "ashrdi3"
678 [(set (match_operand:DI 0 "general_operand" "=g")
679 (ashiftrt:DI (match_operand:DI 1 "general_operand" "g")
680 (match_operand:QI 2 "general_operand" "g")))]
684 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
687 (define_insn "ashldi3"
688 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
689 (ashift:DI (match_operand:DI 1 "general_operand" "g")
690 (match_operand:QI 2 "general_operand" "g")))]
695 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
696 (ashiftrt:DI (match_operand:DI 1 "general_operand" "g")
697 (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
701 ;; We used to have expand_shift handle logical right shifts by using extzv,
702 ;; but this make it very difficult to do lshrdi3. Since the VAX is the
703 ;; only machine with this kludge, it's better to just do this with a
704 ;; define_expand and remove that case from expand_shift.
706 (define_expand "lshrsi3"
708 (minus:QI (const_int 32)
710 (set (match_operand:SI 0 "nonimmediate_operand" "=g")
711 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
713 (match_operand:SI 2 "register_operand" "g")))]
717 operands[3] = gen_reg_rtx (QImode);
718 operands[4] = gen_lowpart (QImode, operands[2]);
721 ;; Rotate right on the VAX works by negating the shift count.
722 (define_expand "rotrsi3"
723 [(set (match_operand:SI 0 "general_operand" "=g")
724 (rotatert:SI (match_operand:SI 1 "general_operand" "g")
725 (match_operand:QI 2 "general_operand" "g")))]
729 if (! CONST_INT_P (operands[2]))
730 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
733 (define_insn "rotlsi3"
734 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
735 (rotate:SI (match_operand:SI 1 "general_operand" "nrmT")
736 (match_operand:QI 2 "general_operand" "g")))]
741 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
742 (rotatert:SI (match_operand:SI 1 "general_operand" "nrmT")
743 (match_operand:QI 2 "const_int_operand" "n")))]
748 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
749 (rotatert:SI (match_operand:SI 1 "general_operand" "nrmT")
750 (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
754 ;This insn is probably slower than a multiply and an add.
756 ; [(set (match_operand:SI 0 "general_operand" "=g")
757 ; (mult:SI (plus:SI (match_operand:SI 1 "general_operand" "g")
758 ; (match_operand:SI 2 "general_operand" "g"))
759 ; (match_operand:SI 3 "general_operand" "g")))]
761 ; "index %1,$0x80000000,$0x7fffffff,%3,%2,%0")
763 ;; Special cases of bit-field insns which we should
764 ;; recognize in preference to the general case.
765 ;; These handle aligned 8-bit and 16-bit fields,
766 ;; which can usually be done with move instructions.
769 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+ro")
770 (match_operand:QI 1 "const_int_operand" "n")
771 (match_operand:SI 2 "const_int_operand" "n"))
772 (match_operand:SI 3 "general_operand" "g"))]
773 "(INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
774 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
775 && (REG_P (operands[0])
776 || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
779 if (REG_P (operands[0]))
781 if (INTVAL (operands[2]) != 0)
782 return \"insv %3,%2,%1,%0\";
786 = adjust_address (operands[0],
787 INTVAL (operands[1]) == 8 ? QImode : HImode,
788 INTVAL (operands[2]) / 8);
791 if (INTVAL (operands[1]) == 8)
792 return \"movb %3,%0\";
793 return \"movw %3,%0\";
797 [(set (match_operand:SI 0 "nonimmediate_operand" "=&g")
798 (zero_extract:SI (match_operand:SI 1 "register_operand" "ro")
799 (match_operand:QI 2 "const_int_operand" "n")
800 (match_operand:SI 3 "const_int_operand" "n")))]
801 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
802 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
803 && (REG_P (operands[1])
804 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
807 if (REG_P (operands[1]))
809 if (INTVAL (operands[3]) != 0)
810 return \"extzv %3,%2,%1,%0\";
814 = adjust_address (operands[1],
815 INTVAL (operands[2]) == 8 ? QImode : HImode,
816 INTVAL (operands[3]) / 8);
818 if (INTVAL (operands[2]) == 8)
819 return \"movzbl %1,%0\";
820 return \"movzwl %1,%0\";
824 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
825 (sign_extract:SI (match_operand:SI 1 "register_operand" "ro")
826 (match_operand:QI 2 "const_int_operand" "n")
827 (match_operand:SI 3 "const_int_operand" "n")))]
828 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
829 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
830 && (REG_P (operands[1])
831 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
834 if (REG_P (operands[1]))
836 if (INTVAL (operands[3]) != 0)
837 return \"extv %3,%2,%1,%0\";
841 = adjust_address (operands[1],
842 INTVAL (operands[2]) == 8 ? QImode : HImode,
843 INTVAL (operands[3]) / 8);
845 if (INTVAL (operands[2]) == 8)
846 return \"cvtbl %1,%0\";
847 return \"cvtwl %1,%0\";
850 ;; Register-only SImode cases of bit-field insns.
855 (sign_extract:SI (match_operand:SI 0 "register_operand" "r")
856 (match_operand:QI 1 "general_operand" "g")
857 (match_operand:SI 2 "general_operand" "nrmT"))
858 (match_operand:SI 3 "general_operand" "nrmT")))]
865 (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
866 (match_operand:QI 1 "general_operand" "g")
867 (match_operand:SI 2 "general_operand" "nrmT"))
868 (match_operand:SI 3 "general_operand" "nrmT")))]
872 ;; When the field position and size are constant and the destination
873 ;; is a register, extv and extzv are much slower than a rotate followed
874 ;; by a bicl or sign extension. Because we might end up choosing ext[z]v
875 ;; anyway, we can't allow immediate values for the primary source operand.
878 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
879 (sign_extract:SI (match_operand:SI 1 "register_operand" "ro")
880 (match_operand:QI 2 "general_operand" "g")
881 (match_operand:SI 3 "general_operand" "nrmT")))]
885 if (! CONST_INT_P (operands[3]) || ! CONST_INT_P (operands[2])
886 || ! REG_P (operands[0])
887 || (INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16))
888 return \"extv %3,%2,%1,%0\";
889 if (INTVAL (operands[2]) == 8)
890 return \"rotl %R3,%1,%0\;cvtbl %0,%0\";
891 return \"rotl %R3,%1,%0\;cvtwl %0,%0\";
895 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
896 (zero_extract:SI (match_operand:SI 1 "register_operand" "ro")
897 (match_operand:QI 2 "general_operand" "g")
898 (match_operand:SI 3 "general_operand" "nrmT")))]
902 if (! CONST_INT_P (operands[3]) || ! CONST_INT_P (operands[2])
903 || ! REG_P (operands[0]))
904 return \"extzv %3,%2,%1,%0\";
905 if (INTVAL (operands[2]) == 8)
906 return \"rotl %R3,%1,%0\;movzbl %0,%0\";
907 if (INTVAL (operands[2]) == 16)
908 return \"rotl %R3,%1,%0\;movzwl %0,%0\";
909 if (INTVAL (operands[3]) & 31)
910 return \"rotl %R3,%1,%0\;bicl2 %M2,%0\";
911 if (rtx_equal_p (operands[0], operands[1]))
912 return \"bicl2 %M2,%0\";
913 return \"bicl3 %M2,%1,%0\";
916 ;; Non-register cases.
917 ;; nonimmediate_operand is used to make sure that mode-ambiguous cases
918 ;; don't match these (and therefore match the cases above instead).
923 (sign_extract:SI (match_operand:QI 0 "memory_operand" "m")
924 (match_operand:QI 1 "general_operand" "g")
925 (match_operand:SI 2 "general_operand" "nrmT"))
926 (match_operand:SI 3 "general_operand" "nrmT")))]
933 (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rm")
934 (match_operand:QI 1 "general_operand" "g")
935 (match_operand:SI 2 "general_operand" "nrmT"))
936 (match_operand:SI 3 "general_operand" "nrmT")))]
941 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
942 (sign_extract:SI (match_operand:QI 1 "memory_operand" "m")
943 (match_operand:QI 2 "general_operand" "g")
944 (match_operand:SI 3 "general_operand" "nrmT")))]
948 if (!REG_P (operands[0]) || !CONST_INT_P (operands[2])
949 || !CONST_INT_P (operands[3])
950 || (INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16)
951 || INTVAL (operands[2]) + INTVAL (operands[3]) > 32
952 || side_effects_p (operands[1])
953 || (MEM_P (operands[1])
954 && mode_dependent_address_p (XEXP (operands[1], 0))))
955 return \"extv %3,%2,%1,%0\";
956 if (INTVAL (operands[2]) == 8)
957 return \"rotl %R3,%1,%0\;cvtbl %0,%0\";
958 return \"rotl %R3,%1,%0\;cvtwl %0,%0\";
961 (define_expand "extzv"
962 [(set (match_operand:SI 0 "general_operand" "")
963 (zero_extract:SI (match_operand:SI 1 "general_operand" "")
964 (match_operand:QI 2 "general_operand" "")
965 (match_operand:SI 3 "general_operand" "")))]
970 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
971 (zero_extract:SI (match_operand:QI 1 "memory_operand" "m")
972 (match_operand:QI 2 "general_operand" "g")
973 (match_operand:SI 3 "general_operand" "nrmT")))]
977 if (!REG_P (operands[0]) || !CONST_INT_P (operands[2])
978 || !CONST_INT_P (operands[3])
979 || INTVAL (operands[2]) + INTVAL (operands[3]) > 32
980 || side_effects_p (operands[1])
981 || (MEM_P (operands[1])
982 && mode_dependent_address_p (XEXP (operands[1], 0))))
983 return \"extzv %3,%2,%1,%0\";
984 if (INTVAL (operands[2]) == 8)
985 return \"rotl %R3,%1,%0\;movzbl %0,%0\";
986 if (INTVAL (operands[2]) == 16)
987 return \"rotl %R3,%1,%0\;movzwl %0,%0\";
988 if (MEM_P (operands[1])
989 && GET_CODE (XEXP (operands[1], 0)) == PLUS
990 && REG_P (XEXP (XEXP (operands[1], 0), 0))
991 && CONST_INT_P (XEXP (XEXP (operands[1], 0), 1))
992 && CONST_INT_P (operands[2])
993 && CONST_INT_P (operands[3]))
995 HOST_WIDE_INT o = INTVAL (XEXP (XEXP (operands[1], 0), 1));
996 HOST_WIDE_INT l = INTVAL (operands[2]);
997 HOST_WIDE_INT v = INTVAL (operands[3]);
998 if ((o & 3) && (o & 3) * 8 + v + l <= 32)
1001 tmp = XEXP (XEXP (operands[1], 0), 0);
1003 tmp = gen_rtx_PLUS (SImode, tmp, GEN_INT (o & ~3));
1004 operands[1] = gen_rtx_MEM (QImode, tmp);
1005 operands[3] = GEN_INT (v + (o & 3) * 8);
1008 return \"extzv %3,%2,%1,%0\";
1010 return \"rotl %R3,%1,%0\;bicl2 %M2,%0\";
1013 (define_expand "insv"
1014 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
1015 (match_operand:QI 1 "general_operand" "")
1016 (match_operand:SI 2 "general_operand" ""))
1017 (match_operand:SI 3 "general_operand" ""))]
1022 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+g")
1023 (match_operand:QI 1 "general_operand" "g")
1024 (match_operand:SI 2 "general_operand" "nrmT"))
1025 (match_operand:SI 3 "general_operand" "nrmT"))]
1029 if (MEM_P (operands[0])
1030 && GET_CODE (XEXP (operands[0], 0)) == PLUS
1031 && REG_P (XEXP (XEXP (operands[0], 0), 0))
1032 && CONST_INT_P (XEXP (XEXP (operands[0], 0), 1))
1033 && CONST_INT_P (operands[1])
1034 && CONST_INT_P (operands[2]))
1036 HOST_WIDE_INT o = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1037 HOST_WIDE_INT v = INTVAL (operands[2]);
1038 HOST_WIDE_INT l = INTVAL (operands[1]);
1039 if ((o & 3) && (o & 3) * 8 + v + l <= 32)
1042 tmp = XEXP (XEXP (operands[0], 0), 0);
1044 tmp = gen_rtx_PLUS (SImode, tmp, GEN_INT (o & ~3));
1045 operands[0] = gen_rtx_MEM (QImode, tmp);
1046 operands[2] = GEN_INT (v + (o & 3) * 8);
1049 return \"insv %3,%2,%1,%0\";
1053 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
1054 (match_operand:QI 1 "general_operand" "g")
1055 (match_operand:SI 2 "general_operand" "nrmT"))
1056 (match_operand:SI 3 "general_operand" "nrmT"))]
1060 ;; Unconditional jump
1063 (label_ref (match_operand 0 "" "")))]
1067 ;; Conditional jumps
1069 (define_expand "cbranch<mode>4"
1071 (compare (match_operand:VAXint 1 "nonimmediate_operand" "")
1072 (match_operand:VAXint 2 "general_operand" "")))
1075 (match_operator 0 "ordered_comparison_operator" [(cc0)
1077 (label_ref (match_operand 3 "" ""))
1081 (define_expand "cbranch<mode>4"
1083 (compare (match_operand:VAXfp 1 "general_operand" "")
1084 (match_operand:VAXfp 2 "general_operand" "")))
1087 (match_operator 0 "ordered_comparison_operator" [(cc0)
1089 (label_ref (match_operand 3 "" ""))
1093 (define_insn "*branch"
1095 (if_then_else (match_operator 0 "ordered_comparison_operator"
1098 (label_ref (match_operand 1 "" ""))
1103 ;; Recognize reversed jumps.
1104 (define_insn "*branch_reversed"
1106 (if_then_else (match_operator 0 "ordered_comparison_operator"
1110 (label_ref (match_operand 1 "" ""))))]
1112 "j%C0 %l1") ; %C0 negates condition
1114 ;; Recognize jbs, jlbs, jbc and jlbc instructions. Note that the operand
1115 ;; of jlbs and jlbc insns are SImode in the hardware. However, if it is
1116 ;; memory, we use QImode in the insn. So we can't use those instructions
1117 ;; for mode-dependent addresses.
1122 (ne (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g")
1124 (match_operand:SI 1 "general_operand" "I,nrmT"))
1126 (label_ref (match_operand 2 "" ""))
1136 (eq (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g")
1138 (match_operand:SI 1 "general_operand" "I,nrmT"))
1140 (label_ref (match_operand 2 "" ""))
1150 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r")
1152 (match_operand:SI 1 "general_operand" "I,nrmT"))
1154 (label_ref (match_operand 2 "" ""))
1164 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r")
1166 (match_operand:SI 1 "general_operand" "I,nrmT"))
1168 (label_ref (match_operand 2 "" ""))
1175 ;; Subtract-and-jump and Add-and-jump insns.
1176 ;; These are not used when output is for the Unix assembler
1177 ;; because it does not know how to modify them to reach far.
1179 ;; Normal sob insns.
1184 (gt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
1187 (label_ref (match_operand 1 "" ""))
1190 (plus:SI (match_dup 0)
1198 (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
1201 (label_ref (match_operand 1 "" ""))
1204 (plus:SI (match_dup 0)
1209 ;; Normal aob insns. Define a version for when operands[1] is a constant.
1213 (lt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
1215 (match_operand:SI 1 "general_operand" "nrmT"))
1216 (label_ref (match_operand 2 "" ""))
1219 (plus:SI (match_dup 0)
1222 "jaoblss %1,%0,%l2")
1227 (lt (match_operand:SI 0 "nonimmediate_operand" "+g")
1228 (match_operand:SI 1 "general_operand" "nrmT"))
1229 (label_ref (match_operand 2 "" ""))
1232 (plus:SI (match_dup 0)
1234 "!TARGET_UNIX_ASM && CONST_INT_P (operands[1])"
1235 "jaoblss %P1,%0,%l2")
1240 (le (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
1242 (match_operand:SI 1 "general_operand" "nrmT"))
1243 (label_ref (match_operand 2 "" ""))
1246 (plus:SI (match_dup 0)
1249 "jaobleq %1,%0,%l2")
1254 (le (match_operand:SI 0 "nonimmediate_operand" "+g")
1255 (match_operand:SI 1 "general_operand" "nrmT"))
1256 (label_ref (match_operand 2 "" ""))
1259 (plus:SI (match_dup 0)
1261 "!TARGET_UNIX_ASM && CONST_INT_P (operands[1])"
1262 "jaobleq %P1,%0,%l2")
1264 ;; Something like a sob insn, but compares against -1.
1265 ;; This finds `while (foo--)' which was changed to `while (--foo != -1)'.
1270 (ne (match_operand:SI 0 "nonimmediate_operand" "+g")
1272 (label_ref (match_operand 1 "" ""))
1275 (plus:SI (match_dup 0)
1278 "decl %0\;jgequ %l1")
1280 (define_expand "call_pop"
1281 [(parallel [(call (match_operand:QI 0 "memory_operand" "")
1282 (match_operand:SI 1 "const_int_operand" ""))
1283 (set (reg:SI VAX_SP_REGNUM)
1284 (plus:SI (reg:SI VAX_SP_REGNUM)
1285 (match_operand:SI 3 "immediate_operand" "")))])]
1288 gcc_assert (INTVAL (operands[3]) <= 255 * 4 && INTVAL (operands[3]) % 4 == 0);
1290 /* Operand 1 is the number of bytes to be popped by DW_CFA_GNU_args_size
1291 during EH unwinding. We must include the argument count pushed by
1292 the calls instruction. */
1293 operands[1] = GEN_INT (INTVAL (operands[3]) + 4);
1296 (define_insn "*call_pop"
1297 [(call (match_operand:QI 0 "memory_operand" "m")
1298 (match_operand:SI 1 "const_int_operand" "n"))
1299 (set (reg:SI VAX_SP_REGNUM) (plus:SI (reg:SI VAX_SP_REGNUM)
1300 (match_operand:SI 2 "immediate_operand" "i")))]
1303 operands[1] = GEN_INT ((INTVAL (operands[1]) - 4) / 4);
1304 return "calls %1,%0";
1307 (define_expand "call_value_pop"
1308 [(parallel [(set (match_operand 0 "" "")
1309 (call (match_operand:QI 1 "memory_operand" "")
1310 (match_operand:SI 2 "const_int_operand" "")))
1311 (set (reg:SI VAX_SP_REGNUM)
1312 (plus:SI (reg:SI VAX_SP_REGNUM)
1313 (match_operand:SI 4 "immediate_operand" "")))])]
1316 gcc_assert (INTVAL (operands[4]) <= 255 * 4 && INTVAL (operands[4]) % 4 == 0);
1318 /* Operand 2 is the number of bytes to be popped by DW_CFA_GNU_args_size
1319 during EH unwinding. We must include the argument count pushed by
1320 the calls instruction. */
1321 operands[2] = GEN_INT (INTVAL (operands[4]) + 4);
1324 (define_insn "*call_value_pop"
1325 [(set (match_operand 0 "" "")
1326 (call (match_operand:QI 1 "memory_operand" "m")
1327 (match_operand:SI 2 "const_int_operand" "n")))
1328 (set (reg:SI VAX_SP_REGNUM) (plus:SI (reg:SI VAX_SP_REGNUM)
1329 (match_operand:SI 3 "immediate_operand" "i")))]
1333 operands[2] = GEN_INT ((INTVAL (operands[2]) - 4) / 4);
1334 return \"calls %2,%1\";
1337 (define_expand "call"
1338 [(call (match_operand:QI 0 "memory_operand" "")
1339 (match_operand:SI 1 "const_int_operand" ""))]
1343 /* Operand 1 is the number of bytes to be popped by DW_CFA_GNU_args_size
1344 during EH unwinding. We must include the argument count pushed by
1345 the calls instruction. */
1346 operands[1] = GEN_INT (INTVAL (operands[1]) + 4);
1349 (define_insn "*call"
1350 [(call (match_operand:QI 0 "memory_operand" "m")
1351 (match_operand:SI 1 "const_int_operand" ""))]
1355 (define_expand "call_value"
1356 [(set (match_operand 0 "" "")
1357 (call (match_operand:QI 1 "memory_operand" "")
1358 (match_operand:SI 2 "const_int_operand" "")))]
1362 /* Operand 2 is the number of bytes to be popped by DW_CFA_GNU_args_size
1363 during EH unwinding. We must include the argument count pushed by
1364 the calls instruction. */
1365 operands[2] = GEN_INT (INTVAL (operands[2]) + 4);
1368 (define_insn "*call_value"
1369 [(set (match_operand 0 "" "")
1370 (call (match_operand:QI 1 "memory_operand" "m")
1371 (match_operand:SI 2 "const_int_operand" "")))]
1375 ;; Call subroutine returning any type.
1377 (define_expand "untyped_call"
1378 [(parallel [(call (match_operand 0 "" "")
1380 (match_operand 1 "" "")
1381 (match_operand 2 "" "")])]
1387 emit_call_insn (gen_call_pop (operands[0], const0_rtx, NULL, const0_rtx));
1389 for (i = 0; i < XVECLEN (operands[2], 0); i++)
1391 rtx set = XVECEXP (operands[2], 0, i);
1392 emit_move_insn (SET_DEST (set), SET_SRC (set));
1395 /* The optimizer does not know that the call sets the function value
1396 registers we stored in the result block. We avoid problems by
1397 claiming that all hard registers are used and clobbered at this
1399 emit_insn (gen_blockage ());
1404 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
1405 ;; all of memory. This blocks insns from being moved across this point.
1407 (define_insn "blockage"
1408 [(unspec_volatile [(const_int 0)] VUNSPEC_BLOCKAGE)]
1412 (define_insn "return"
1417 (define_expand "epilogue"
1422 emit_jump_insn (gen_return ());
1431 ;; This had a wider constraint once, and it had trouble.
1432 ;; If you are tempted to try `g', please don't--it's not worth
1433 ;; the risk we will reopen the same bug.
1434 (define_insn "indirect_jump"
1435 [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
1439 ;; This is here to accept 5 arguments (as passed by expand_end_case)
1440 ;; and pass the first 4 along to the casesi1 pattern that really does
1441 ;; the actual casesi work. We emit a jump here to the default label
1442 ;; _before_ the casesi so that we can be sure that the casesi never
1444 ;; This is suboptimal perhaps, but so is much of the rest of this
1445 ;; machine description. For what it's worth, HPPA uses the same trick.
1447 ;; operand 0 is index
1448 ;; operand 1 is the minimum bound (a const_int)
1449 ;; operand 2 is the maximum bound - minimum bound + 1 (also a const_int)
1450 ;; operand 3 is CODE_LABEL for the table;
1451 ;; operand 4 is the CODE_LABEL to go to if index out of range (ie. default).
1454 ;; i = index - minimum_bound
1455 ;; if (i > (maximum_bound - minimum_bound + 1) goto default;
1456 ;; casesi (i, 0, table);
1458 (define_expand "casesi"
1459 [(match_operand:SI 0 "general_operand" "")
1460 (match_operand:SI 1 "general_operand" "")
1461 (match_operand:SI 2 "general_operand" "")
1462 (match_operand 3 "" "")
1463 (match_operand 4 "" "")]
1468 /* i = index - minimum_bound;
1469 But only if the lower bound is not already zero. */
1470 if (operands[1] != const0_rtx)
1472 rtx index = gen_reg_rtx (SImode);
1473 emit_insn (gen_addsi3 (index,
1475 GEN_INT (-INTVAL (operands[1]))));
1476 operands[0] = index;
1479 /* if (i > (maximum_bound - minimum_bound + 1)) goto default; */
1480 test = gen_rtx_fmt_ee (GTU, VOIDmode, operands[0], operands[2]);
1481 emit_jump_insn (gen_cbranchsi4 (test, operands[0], operands[2], operands[4]));
1483 /* casesi (i, 0, table); */
1484 emit_jump_insn (gen_casesi1 (operands[0], operands[2], operands[3]));
1488 ;; This insn is a bit of a lier. It actually falls through if no case
1489 ;; matches. But, we prevent that from ever happening by emitting a jump
1490 ;; before this, see the define_expand above.
1491 (define_insn "casesi1"
1492 [(match_operand:SI 1 "const_int_operand" "n")
1494 (plus:SI (sign_extend:SI
1495 (mem:HI (plus:SI (mult:SI (match_operand:SI 0 "general_operand" "nrmT")
1498 (label_ref:SI (match_operand 2 "" ""))))]
1502 (define_insn "pushextsym"
1503 [(set (match_operand:SI 0 "push_operand" "=g")
1504 (match_operand:SI 1 "external_symbolic_operand" "i"))]
1508 (define_insn "movextsym"
1509 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1510 (match_operand:SI 1 "external_symbolic_operand" "i"))]
1514 (define_insn "pushlclsym"
1515 [(set (match_operand:SI 0 "push_operand" "=g")
1516 (match_operand:SI 1 "local_symbolic_operand" "i"))]
1520 (define_insn "movlclsym"
1521 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1522 (match_operand:SI 1 "local_symbolic_operand" "i"))]
1526 ;;- load or push effective address
1527 ;; These come after the move and add/sub patterns
1528 ;; because we don't want pushl $1 turned into pushad 1.
1529 ;; or addl3 r1,r2,r3 turned into movab 0(r1)[r2],r3.
1531 ;; It does not work to use constraints to distinguish pushes from moves,
1532 ;; because < matches any autodecrement, not just a push.
1534 (define_insn "pushaddr<mode>"
1535 [(set (match_operand:SI 0 "push_operand" "=g")
1536 (match_operand:VAXintQHSD 1 "address_operand" "p"))]
1538 "pusha<VAXintQHSD:isfx> %a1")
1540 (define_insn "movaddr<mode>"
1541 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1542 (match_operand:VAXintQHSD 1 "address_operand" "p"))]
1544 "mova<VAXintQHSD:isfx> %a1,%0")
1546 (define_insn "pushaddr<mode>"
1547 [(set (match_operand:SI 0 "push_operand" "=g")
1548 (match_operand:VAXfp 1 "address_operand" "p"))]
1550 "pusha<VAXfp:fsfx> %a1")
1552 (define_insn "movaddr<mode>"
1553 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1554 (match_operand:VAXfp 1 "address_operand" "p"))]
1556 "mova<VAXfp:fsfx> %a1,%0")
1558 ;; These used to be peepholes, but it is more straightforward to do them
1559 ;; as single insns. However, we must force the output to be a register
1560 ;; if it is not an offsettable address so that we know that we can assign
1563 ;; If we had a good way of evaluating the relative costs, these could be
1564 ;; machine-independent.
1566 ;; Optimize extzv ...,z; andl2 ...,z
1567 ;; or ashl ...,z; andl2 ...,z
1568 ;; with other operands constant. This is what the combiner converts the
1569 ;; above sequences to before attempting to recognize the new insn.
1572 [(set (match_operand:SI 0 "nonimmediate_operand" "=ro")
1573 (and:SI (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT")
1574 (match_operand:QI 2 "const_int_operand" "n"))
1575 (match_operand:SI 3 "const_int_operand" "n")))]
1576 "(INTVAL (operands[3]) & ~((1 << (32 - INTVAL (operands[2]))) - 1)) == 0"
1579 unsigned long mask1 = INTVAL (operands[3]);
1580 unsigned long mask2 = (1 << (32 - INTVAL (operands[2]))) - 1;
1582 if ((mask1 & mask2) != mask1)
1583 operands[3] = GEN_INT (mask1 & mask2);
1585 return \"rotl %R2,%1,%0\;bicl2 %N3,%0\";
1588 ;; left-shift and mask
1589 ;; The only case where `ashl' is better is if the mask only turns off
1590 ;; bits that the ashl would anyways, in which case it should have been
1594 [(set (match_operand:SI 0 "nonimmediate_operand" "=ro")
1595 (and:SI (ashift:SI (match_operand:SI 1 "general_operand" "nrmT")
1596 (match_operand:QI 2 "const_int_operand" "n"))
1597 (match_operand:SI 3 "const_int_operand" "n")))]
1602 = GEN_INT (INTVAL (operands[3]) & ~((1 << INTVAL (operands[2])) - 1));
1603 return \"rotl %2,%1,%0\;bicl2 %N3,%0\";
1606 ;; Instruction sequence to sync the VAX instruction stream.
1607 (define_insn "sync_istream"
1608 [(unspec_volatile [(const_int 0)] VUNSPEC_SYNC_ISTREAM)]
1610 "movpsl -(%|sp)\;pushal 1(%|pc)\;rei")
1612 (define_expand "nonlocal_goto"
1613 [(use (match_operand 0 "general_operand" ""))
1614 (use (match_operand 1 "general_operand" ""))
1615 (use (match_operand 2 "general_operand" ""))
1616 (use (match_operand 3 "general_operand" ""))]
1619 rtx lab = operands[1];
1620 rtx stack = operands[2];
1621 rtx fp = operands[3];
1623 emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode)));
1624 emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx));
1626 emit_move_insn (hard_frame_pointer_rtx, fp);
1627 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
1629 emit_use (hard_frame_pointer_rtx);
1630 emit_use (stack_pointer_rtx);
1632 /* We'll convert this to direct jump via a peephole optimization. */
1633 emit_indirect_jump (copy_to_reg (lab));