1 ;; Machine description for GNU compiler, VAX Version
2 ;; Copyright (C) 1987, 1988, 1991, 1994, 1995, 1996, 1998, 1999, 2000, 2001,
3 ;; 2002 Free Software Foundation, Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
23 ;;- Instruction patterns. When multiple patterns apply,
24 ;;- the first one in the file is chosen.
26 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
28 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
29 ;;- updates for most instructions.
31 ;; UNSPEC_VOLATILE usage:
34 [(VUNSPEC_BLOCKAGE 0) ; `blockage' insn to prevent scheduling across an
36 (VUNSPEC_SYNC_ISTREAM 1) ; sequence of insns to sync the I-stream
40 ;; We don't want to allow a constant operand for test insns because
41 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
42 ;; be folded while optimizing anyway.
46 (match_operand:SI 0 "nonimmediate_operand" "g"))]
52 (match_operand:HI 0 "nonimmediate_operand" "g"))]
58 (match_operand:QI 0 "nonimmediate_operand" "g"))]
64 (match_operand:DF 0 "general_operand" "gF"))]
70 (match_operand:SF 0 "general_operand" "gF"))]
76 (compare (match_operand:SI 0 "nonimmediate_operand" "g")
77 (match_operand:SI 1 "general_operand" "g")))]
83 (compare (match_operand:HI 0 "nonimmediate_operand" "g")
84 (match_operand:HI 1 "general_operand" "g")))]
90 (compare (match_operand:QI 0 "nonimmediate_operand" "g")
91 (match_operand:QI 1 "general_operand" "g")))]
97 (compare (match_operand:DF 0 "general_operand" "gF,gF")
98 (match_operand:DF 1 "general_operand" "G,gF")))]
106 (compare (match_operand:SF 0 "general_operand" "gF,gF")
107 (match_operand:SF 1 "general_operand" "G,gF")))]
115 (and:SI (match_operand:SI 0 "general_operand" "g")
116 (match_operand:SI 1 "general_operand" "g")))]
122 (and:HI (match_operand:HI 0 "general_operand" "g")
123 (match_operand:HI 1 "general_operand" "g")))]
129 (and:QI (match_operand:QI 0 "general_operand" "g")
130 (match_operand:QI 1 "general_operand" "g")))]
134 ;; The VAX has no sCOND insns. It does have add/subtract with carry
135 ;; which could be used to implement the sltu and sgeu patterns. However,
136 ;; to do this properly requires a complete rewrite of the compare insns
137 ;; to keep them together with the sltu/sgeu insns until after the
138 ;; reload pass is complete. The previous implementation didn't do this
139 ;; and has been deleted.
143 [(set (match_operand:DF 0 "nonimmediate_operand" "=g,g")
144 (match_operand:DF 1 "general_operand" "G,gF"))]
151 [(set (match_operand:SF 0 "nonimmediate_operand" "=g,g")
152 (match_operand:SF 1 "general_operand" "G,gF"))]
158 ;; Some VAXen don't support this instruction.
159 ;;(define_insn "movti"
160 ;; [(set (match_operand:TI 0 "general_operand" "=g")
161 ;; (match_operand:TI 1 "general_operand" "g"))]
166 [(set (match_operand:DI 0 "nonimmediate_operand" "=g,g")
167 (match_operand:DI 1 "general_operand" "I,g"))]
173 ;; The VAX move instructions have space-time tradeoffs. On a MicroVAX
174 ;; register-register mov instructions take 3 bytes and 2 CPU cycles. clrl
175 ;; takes 2 bytes and 3 cycles. mov from constant to register takes 2 cycles
176 ;; if the constant is smaller than 4 bytes, 3 cycles for a longword
177 ;; constant. movz, mneg, and mcom are as fast as mov, so movzwl is faster
178 ;; than movl for positive constants that fit in 16 bits but not 6 bits. cvt
179 ;; instructions take 4 cycles. inc takes 3 cycles. The machine description
180 ;; is willing to trade 1 byte for 1 cycle (clrl instead of movl $0; cvtwl
183 ;; Cycle counts for other models may vary (on a VAX 750 they are similar,
184 ;; but on a VAX 9000 most move and add instructions with one constant
185 ;; operand take 1 cycle).
187 ;; Loads of constants between 64 and 128 used to be done with
188 ;; "addl3 $63,#,dst" but this is slower than movzbl and takes as much space.
191 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
192 (match_operand:SI 1 "general_operand" "g"))]
196 if (operands[1] == const1_rtx && reg_was_0_p (insn, operands[0]))
199 if (GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == CONST)
201 if (push_operand (operands[0], SImode))
202 return \"pushab %a1\";
203 return \"movab %a1,%0\";
205 if (operands[1] == const0_rtx)
207 if (GET_CODE (operands[1]) == CONST_INT
208 && (unsigned) INTVAL (operands[1]) >= 64)
210 int i = INTVAL (operands[1]);
211 if ((unsigned)(~i) < 64)
212 return \"mcoml %N1,%0\";
213 if ((unsigned)i < 0x100)
214 return \"movzbl %1,%0\";
215 if (i >= -0x80 && i < 0)
216 return \"cvtbl %1,%0\";
217 if ((unsigned)i < 0x10000)
218 return \"movzwl %1,%0\";
219 if (i >= -0x8000 && i < 0)
220 return \"cvtwl %1,%0\";
222 if (push_operand (operands[0], SImode))
224 return \"movl %1,%0\";
228 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
229 (match_operand:HI 1 "general_operand" "g"))]
233 if (operands[1] == const1_rtx && reg_was_0_p (insn, operands[0]))
236 if (GET_CODE (operands[1]) == CONST_INT)
238 int i = INTVAL (operands[1]);
241 else if ((unsigned int)i < 64)
242 return \"movw %1,%0\";
243 else if ((unsigned int)~i < 64)
244 return \"mcomw %H1,%0\";
245 else if ((unsigned int)i < 256)
246 return \"movzbw %1,%0\";
248 return \"movw %1,%0\";
251 (define_insn "movstricthi"
252 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+g"))
253 (match_operand:HI 1 "general_operand" "g"))]
257 if (GET_CODE (operands[1]) == CONST_INT)
259 int i = INTVAL (operands[1]);
262 else if ((unsigned int)i < 64)
263 return \"movw %1,%0\";
264 else if ((unsigned int)~i < 64)
265 return \"mcomw %H1,%0\";
266 else if ((unsigned int)i < 256)
267 return \"movzbw %1,%0\";
269 return \"movw %1,%0\";
273 [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
274 (match_operand:QI 1 "general_operand" "g"))]
278 if (operands[1] == const1_rtx && reg_was_0_p (insn, operands[0]))
281 if (GET_CODE (operands[1]) == CONST_INT)
283 int i = INTVAL (operands[1]);
286 else if ((unsigned int)~i < 64)
287 return \"mcomb %B1,%0\";
289 return \"movb %1,%0\";
292 (define_insn "movstrictqi"
293 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+g"))
294 (match_operand:QI 1 "general_operand" "g"))]
298 if (GET_CODE (operands[1]) == CONST_INT)
300 int i = INTVAL (operands[1]);
303 else if ((unsigned int)~i < 64)
304 return \"mcomb %B1,%0\";
306 return \"movb %1,%0\";
309 ;; This is here to accept 4 arguments and pass the first 3 along
310 ;; to the movstrhi1 pattern that really does the work.
311 (define_expand "movstrhi"
312 [(set (match_operand:BLK 0 "general_operand" "=g")
313 (match_operand:BLK 1 "general_operand" "g"))
314 (use (match_operand:HI 2 "general_operand" "g"))
315 (match_operand 3 "" "")]
318 emit_insn (gen_movstrhi1 (operands[0], operands[1], operands[2]));
322 ;; The definition of this insn does not really explain what it does,
323 ;; but it should suffice
324 ;; that anything generated as this insn will be recognized as one
325 ;; and that it won't successfully combine with anything.
326 (define_insn "movstrhi1"
327 [(set (match_operand:BLK 0 "memory_operand" "=m")
328 (match_operand:BLK 1 "memory_operand" "m"))
329 (use (match_operand:HI 2 "general_operand" "g"))
335 (clobber (reg:SI 5))]
339 ;; Extension and truncation insns.
341 (define_insn "truncsiqi2"
342 [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
343 (truncate:QI (match_operand:SI 1 "nonimmediate_operand" "g")))]
347 (define_insn "truncsihi2"
348 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
349 (truncate:HI (match_operand:SI 1 "nonimmediate_operand" "g")))]
353 (define_insn "trunchiqi2"
354 [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
355 (truncate:QI (match_operand:HI 1 "nonimmediate_operand" "g")))]
359 (define_insn "extendhisi2"
360 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
361 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
365 (define_insn "extendqihi2"
366 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
367 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
371 (define_insn "extendqisi2"
372 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
373 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
377 (define_insn "extendsfdf2"
378 [(set (match_operand:DF 0 "nonimmediate_operand" "=g")
379 (float_extend:DF (match_operand:SF 1 "general_operand" "gF")))]
383 (define_insn "truncdfsf2"
384 [(set (match_operand:SF 0 "nonimmediate_operand" "=g")
385 (float_truncate:SF (match_operand:DF 1 "general_operand" "gF")))]
389 (define_insn "zero_extendhisi2"
390 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
391 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
395 (define_insn "zero_extendqihi2"
396 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
397 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
401 (define_insn "zero_extendqisi2"
402 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
403 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
407 ;; Fix-to-float conversion insns.
409 (define_insn "floatsisf2"
410 [(set (match_operand:SF 0 "nonimmediate_operand" "=g")
411 (float:SF (match_operand:SI 1 "nonimmediate_operand" "g")))]
415 (define_insn "floatsidf2"
416 [(set (match_operand:DF 0 "nonimmediate_operand" "=g")
417 (float:DF (match_operand:SI 1 "nonimmediate_operand" "g")))]
421 (define_insn "floathisf2"
422 [(set (match_operand:SF 0 "nonimmediate_operand" "=g")
423 (float:SF (match_operand:HI 1 "nonimmediate_operand" "g")))]
427 (define_insn "floathidf2"
428 [(set (match_operand:DF 0 "nonimmediate_operand" "=g")
429 (float:DF (match_operand:HI 1 "nonimmediate_operand" "g")))]
433 (define_insn "floatqisf2"
434 [(set (match_operand:SF 0 "nonimmediate_operand" "=g")
435 (float:SF (match_operand:QI 1 "nonimmediate_operand" "g")))]
439 (define_insn "floatqidf2"
440 [(set (match_operand:DF 0 "nonimmediate_operand" "=g")
441 (float:DF (match_operand:QI 1 "nonimmediate_operand" "g")))]
445 ;; Float-to-fix conversion insns.
447 (define_insn "fix_truncsfqi2"
448 [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
449 (fix:QI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))]
453 (define_insn "fix_truncsfhi2"
454 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
455 (fix:HI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))]
459 (define_insn "fix_truncsfsi2"
460 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
461 (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))]
465 (define_insn "fix_truncdfqi2"
466 [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
467 (fix:QI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))]
471 (define_insn "fix_truncdfhi2"
472 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
473 (fix:HI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))]
477 (define_insn "fix_truncdfsi2"
478 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
479 (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))]
483 ;;- All kinds of add instructions.
485 (define_insn "adddf3"
486 [(set (match_operand:DF 0 "nonimmediate_operand" "=g,g,g")
487 (plus:DF (match_operand:DF 1 "general_operand" "0,gF,gF")
488 (match_operand:DF 2 "general_operand" "gF,0,gF")))]
495 (define_insn "addsf3"
496 [(set (match_operand:SF 0 "nonimmediate_operand" "=g,g,g")
497 (plus:SF (match_operand:SF 1 "general_operand" "0,gF,gF")
498 (match_operand:SF 2 "general_operand" "gF,0,gF")))]
505 /* The space-time-opcode tradeoffs for addition vary by model of VAX.
507 On a VAX 3 "movab (r1)[r2],r3" is faster than "addl3 r1,r2,r3",
508 but it not faster on other models.
510 "movab #(r1),r2" is usually shorter than "addl3 #,r1,r2", and is
511 faster on a VAX 3, but some VAXen (e.g. VAX 9000) will stall if
512 a register is used in an address too soon after it is set.
513 Compromise by using movab only when it is shorter than the add
514 or the base register in the address is one of sp, ap, and fp,
515 which are not modified very often. */
518 (define_insn "addsi3"
519 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
520 (plus:SI (match_operand:SI 1 "general_operand" "g")
521 (match_operand:SI 2 "general_operand" "g")))]
525 if (rtx_equal_p (operands[0], operands[1]))
527 if (operands[2] == const1_rtx)
529 if (operands[2] == constm1_rtx)
531 if (GET_CODE (operands[2]) == CONST_INT
532 && (unsigned) (- INTVAL (operands[2])) < 64)
533 return \"subl2 $%n2,%0\";
534 if (GET_CODE (operands[2]) == CONST_INT
535 && (unsigned) INTVAL (operands[2]) >= 64
536 && GET_CODE (operands[1]) == REG
537 && ((INTVAL (operands[2]) < 32767 && INTVAL (operands[2]) > -32768)
538 || REGNO (operands[1]) > 11))
539 return \"movab %c2(%1),%0\";
540 return \"addl2 %2,%0\";
542 if (rtx_equal_p (operands[0], operands[2]))
543 return \"addl2 %1,%0\";
545 if (GET_CODE (operands[2]) == CONST_INT
546 && INTVAL (operands[2]) < 32767
547 && INTVAL (operands[2]) > -32768
548 && GET_CODE (operands[1]) == REG
549 && push_operand (operands[0], SImode))
550 return \"pushab %c2(%1)\";
552 if (GET_CODE (operands[2]) == CONST_INT
553 && (unsigned) (- INTVAL (operands[2])) < 64)
554 return \"subl3 $%n2,%1,%0\";
556 if (GET_CODE (operands[2]) == CONST_INT
557 && (unsigned) INTVAL (operands[2]) >= 64
558 && GET_CODE (operands[1]) == REG
559 && ((INTVAL (operands[2]) < 32767 && INTVAL (operands[2]) > -32768)
560 || REGNO (operands[1]) > 11))
561 return \"movab %c2(%1),%0\";
563 /* Add this if using gcc on a VAX 3xxx:
564 if (REG_P (operands[1]) && REG_P (operands[2]))
565 return \"movab (%1)[%2],%0\";
567 return \"addl3 %1,%2,%0\";
570 (define_insn "addhi3"
571 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
572 (plus:HI (match_operand:HI 1 "general_operand" "g")
573 (match_operand:HI 2 "general_operand" "g")))]
577 if (rtx_equal_p (operands[0], operands[1]))
579 if (operands[2] == const1_rtx)
581 if (operands[2] == constm1_rtx)
583 if (GET_CODE (operands[2]) == CONST_INT
584 && (unsigned) (- INTVAL (operands[2])) < 64)
585 return \"subw2 $%n2,%0\";
586 return \"addw2 %2,%0\";
588 if (rtx_equal_p (operands[0], operands[2]))
589 return \"addw2 %1,%0\";
590 if (GET_CODE (operands[2]) == CONST_INT
591 && (unsigned) (- INTVAL (operands[2])) < 64)
592 return \"subw3 $%n2,%1,%0\";
593 return \"addw3 %1,%2,%0\";
596 (define_insn "addqi3"
597 [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
598 (plus:QI (match_operand:QI 1 "general_operand" "g")
599 (match_operand:QI 2 "general_operand" "g")))]
603 if (rtx_equal_p (operands[0], operands[1]))
605 if (operands[2] == const1_rtx)
607 if (operands[2] == constm1_rtx)
609 if (GET_CODE (operands[2]) == CONST_INT
610 && (unsigned) (- INTVAL (operands[2])) < 64)
611 return \"subb2 $%n2,%0\";
612 return \"addb2 %2,%0\";
614 if (rtx_equal_p (operands[0], operands[2]))
615 return \"addb2 %1,%0\";
616 if (GET_CODE (operands[2]) == CONST_INT
617 && (unsigned) (- INTVAL (operands[2])) < 64)
618 return \"subb3 $%n2,%1,%0\";
619 return \"addb3 %1,%2,%0\";
622 ;; The add-with-carry (adwc) instruction only accepts two operands.
623 (define_insn "adddi3"
624 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro>,ro>")
625 (plus:DI (match_operand:DI 1 "general_operand" "%0,ro>")
626 (match_operand:DI 2 "general_operand" "Fro,F")))]
634 split_quadword_operands (operands, low, 3);
636 if (rtx_equal_p (operands[0], operands[1]))
638 if (low[2] == const0_rtx)
639 /* Should examine operand, punt if not POST_INC. */
640 pattern = \"tstl %0\", carry = 0;
641 else if (low[2] == const1_rtx)
642 pattern = \"incl %0\";
644 pattern = \"addl2 %2,%0\";
648 if (low[2] == const0_rtx)
649 pattern = \"movl %1,%0\", carry = 0;
651 pattern = \"addl3 %2,%1,%0\";
654 output_asm_insn (pattern, low);
656 /* If CARRY is 0, we don't have any carry value to worry about. */
657 return get_insn_template (CODE_FOR_addsi3, insn);
658 /* %0 = C + %1 + %2 */
659 if (!rtx_equal_p (operands[0], operands[1]))
660 output_asm_insn ((operands[1] == const0_rtx
662 : \"movl %1,%0\"), operands);
663 return \"adwc %2,%0\";
666 ;;- All kinds of subtract instructions.
668 (define_insn "subdf3"
669 [(set (match_operand:DF 0 "nonimmediate_operand" "=g,g")
670 (minus:DF (match_operand:DF 1 "general_operand" "0,gF")
671 (match_operand:DF 2 "general_operand" "gF,gF")))]
677 (define_insn "subsf3"
678 [(set (match_operand:SF 0 "nonimmediate_operand" "=g,g")
679 (minus:SF (match_operand:SF 1 "general_operand" "0,gF")
680 (match_operand:SF 2 "general_operand" "gF,gF")))]
686 (define_insn "subsi3"
687 [(set (match_operand:SI 0 "nonimmediate_operand" "=g,g")
688 (minus:SI (match_operand:SI 1 "general_operand" "0,g")
689 (match_operand:SI 2 "general_operand" "g,g")))]
695 (define_insn "subhi3"
696 [(set (match_operand:HI 0 "nonimmediate_operand" "=g,g")
697 (minus:HI (match_operand:HI 1 "general_operand" "0,g")
698 (match_operand:HI 2 "general_operand" "g,g")))]
704 (define_insn "subqi3"
705 [(set (match_operand:QI 0 "nonimmediate_operand" "=g,g")
706 (minus:QI (match_operand:QI 1 "general_operand" "0,g")
707 (match_operand:QI 2 "general_operand" "g,g")))]
713 ;; The subtract-with-carry (sbwc) instruction only takes two operands.
714 (define_insn "subdi3"
715 [(set (match_operand:DI 0 "nonimmediate_operand" "=or>,or>")
716 (minus:DI (match_operand:DI 1 "general_operand" "0,or>")
717 (match_operand:DI 2 "general_operand" "For,F")))]
725 split_quadword_operands (operands, low, 3);
726 /* Subtract low parts. */
727 if (rtx_equal_p (operands[0], operands[1]))
729 if (low[2] == const0_rtx)
730 pattern = 0, carry = 0;
731 else if (low[2] == constm1_rtx)
732 pattern = \"decl %0\";
734 pattern = \"subl2 %2,%0\";
738 if (low[2] == constm1_rtx)
739 pattern = \"decl %0\";
740 else if (low[2] == const0_rtx)
741 pattern = get_insn_template (CODE_FOR_movsi, insn), carry = 0;
743 pattern = \"subl3 %2,%1,%0\";
746 output_asm_insn (pattern, low);
749 if (!rtx_equal_p (operands[0], operands[1]))
750 return \"movl %1,%0\;sbwc %2,%0\";
751 return \"sbwc %2,%0\";
752 /* %0 = %2 - %1 - C */
754 return get_insn_template (CODE_FOR_subsi3, insn);
757 ;;- Multiply instructions.
759 (define_insn "muldf3"
760 [(set (match_operand:DF 0 "nonimmediate_operand" "=g,g,g")
761 (mult:DF (match_operand:DF 1 "general_operand" "0,gF,gF")
762 (match_operand:DF 2 "general_operand" "gF,0,gF")))]
769 (define_insn "mulsf3"
770 [(set (match_operand:SF 0 "nonimmediate_operand" "=g,g,g")
771 (mult:SF (match_operand:SF 1 "general_operand" "0,gF,gF")
772 (match_operand:SF 2 "general_operand" "gF,0,gF")))]
779 (define_insn "mulsi3"
780 [(set (match_operand:SI 0 "nonimmediate_operand" "=g,g,g")
781 (mult:SI (match_operand:SI 1 "general_operand" "0,g,g")
782 (match_operand:SI 2 "general_operand" "g,0,g")))]
789 (define_insn "mulhi3"
790 [(set (match_operand:HI 0 "nonimmediate_operand" "=g,g,")
791 (mult:HI (match_operand:HI 1 "general_operand" "0,g,g")
792 (match_operand:HI 2 "general_operand" "g,0,g")))]
799 (define_insn "mulqi3"
800 [(set (match_operand:QI 0 "nonimmediate_operand" "=g,g,g")
801 (mult:QI (match_operand:QI 1 "general_operand" "0,g,g")
802 (match_operand:QI 2 "general_operand" "g,0,g")))]
809 (define_insn "mulsidi3"
810 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
811 (mult:DI (sign_extend:DI
812 (match_operand:SI 1 "nonimmediate_operand" "g"))
814 (match_operand:SI 2 "nonimmediate_operand" "g"))))]
819 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
821 (mult:DI (sign_extend:DI
822 (match_operand:SI 1 "nonimmediate_operand" "g"))
824 (match_operand:SI 2 "nonimmediate_operand" "g")))
825 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "g"))))]
829 ;; 'F' constraint means type CONST_DOUBLE
831 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
833 (mult:DI (sign_extend:DI
834 (match_operand:SI 1 "nonimmediate_operand" "g"))
836 (match_operand:SI 2 "nonimmediate_operand" "g")))
837 (match_operand:DI 3 "immediate_operand" "F")))]
838 "GET_CODE (operands[3]) == CONST_DOUBLE
839 && CONST_DOUBLE_HIGH (operands[3]) == (CONST_DOUBLE_LOW (operands[3]) >> 31)"
842 if (CONST_DOUBLE_HIGH (operands[3]))
843 operands[3] = GEN_INT (CONST_DOUBLE_LOW (operands[3]));
844 return \"emul %1,%2,%3,%0\";
847 ;;- Divide instructions.
849 (define_insn "divdf3"
850 [(set (match_operand:DF 0 "nonimmediate_operand" "=g,g")
851 (div:DF (match_operand:DF 1 "general_operand" "0,gF")
852 (match_operand:DF 2 "general_operand" "gF,gF")))]
858 (define_insn "divsf3"
859 [(set (match_operand:SF 0 "nonimmediate_operand" "=g,g")
860 (div:SF (match_operand:SF 1 "general_operand" "0,gF")
861 (match_operand:SF 2 "general_operand" "gF,gF")))]
867 (define_insn "divsi3"
868 [(set (match_operand:SI 0 "nonimmediate_operand" "=g,g")
869 (div:SI (match_operand:SI 1 "general_operand" "0,g")
870 (match_operand:SI 2 "general_operand" "g,g")))]
876 (define_insn "divhi3"
877 [(set (match_operand:HI 0 "nonimmediate_operand" "=g,g")
878 (div:HI (match_operand:HI 1 "general_operand" "0,g")
879 (match_operand:HI 2 "general_operand" "g,g")))]
885 (define_insn "divqi3"
886 [(set (match_operand:QI 0 "nonimmediate_operand" "=g,g")
887 (div:QI (match_operand:QI 1 "general_operand" "0,g")
888 (match_operand:QI 2 "general_operand" "g,g")))]
894 ;This is left out because it is very slow;
895 ;we are better off programming around the "lack" of this insn.
896 ;(define_insn "divmoddisi4"
897 ; [(set (match_operand:SI 0 "general_operand" "=g")
898 ; (div:SI (match_operand:DI 1 "general_operand" "g")
899 ; (match_operand:SI 2 "general_operand" "g")))
900 ; (set (match_operand:SI 3 "general_operand" "=g")
901 ; (mod:SI (match_operand:DI 1 "general_operand" "g")
902 ; (match_operand:SI 2 "general_operand" "g")))]
904 ; "ediv %2,%1,%0,%3")
906 ;; Bit-and on the VAX is done with a clear-bits insn.
907 (define_expand "andsi3"
908 [(set (match_operand:SI 0 "nonimmediate_operand" "")
909 (and:SI (not:SI (match_operand:SI 1 "general_operand" ""))
910 (match_operand:SI 2 "general_operand" "")))]
914 rtx op1 = operands[1];
916 /* If there is a constant argument, complement that one. */
917 if (GET_CODE (operands[2]) == CONST_INT && GET_CODE (op1) != CONST_INT)
919 operands[1] = operands[2];
924 if (GET_CODE (op1) == CONST_INT)
925 operands[1] = GEN_INT (~INTVAL (op1));
927 operands[1] = expand_unop (SImode, one_cmpl_optab, op1, 0, 1);
930 (define_expand "andhi3"
931 [(set (match_operand:HI 0 "nonimmediate_operand" "")
932 (and:HI (not:HI (match_operand:HI 1 "general_operand" ""))
933 (match_operand:HI 2 "general_operand" "")))]
937 rtx op1 = operands[1];
939 if (GET_CODE (operands[2]) == CONST_INT && GET_CODE (op1) != CONST_INT)
941 operands[1] = operands[2];
946 if (GET_CODE (op1) == CONST_INT)
947 operands[1] = GEN_INT (~INTVAL (op1));
949 operands[1] = expand_unop (HImode, one_cmpl_optab, op1, 0, 1);
952 (define_expand "andqi3"
953 [(set (match_operand:QI 0 "nonimmediate_operand" "")
954 (and:QI (not:QI (match_operand:QI 1 "general_operand" ""))
955 (match_operand:QI 2 "general_operand" "")))]
959 rtx op1 = operands[1];
961 if (GET_CODE (operands[2]) == CONST_INT && GET_CODE (op1) != CONST_INT)
963 operands[1] = operands[2];
968 if (GET_CODE (op1) == CONST_INT)
969 operands[1] = GEN_INT (~INTVAL (op1));
971 operands[1] = expand_unop (QImode, one_cmpl_optab, op1, 0, 1);
975 [(set (match_operand:SI 0 "nonimmediate_operand" "=g,g")
976 (and:SI (not:SI (match_operand:SI 1 "general_operand" "g,g"))
977 (match_operand:SI 2 "general_operand" "0,g")))]
984 [(set (match_operand:HI 0 "nonimmediate_operand" "=g,g")
985 (and:HI (not:HI (match_operand:HI 1 "general_operand" "g,g"))
986 (match_operand:HI 2 "general_operand" "0,g")))]
993 [(set (match_operand:QI 0 "nonimmediate_operand" "=g,g")
994 (and:QI (not:QI (match_operand:QI 1 "general_operand" "g,g"))
995 (match_operand:QI 2 "general_operand" "0,g")))]
1001 ;; The following used to be needed because constant propagation can
1002 ;; create them starting from the bic insn patterns above. This is no
1003 ;; longer a problem. However, having these patterns allows optimization
1004 ;; opportunities in combine.c.
1007 [(set (match_operand:SI 0 "nonimmediate_operand" "=g,g")
1008 (and:SI (match_operand:SI 1 "general_operand" "0,g")
1009 (match_operand:SI 2 "const_int_operand" "n,n")))]
1016 [(set (match_operand:HI 0 "nonimmediate_operand" "=g,g")
1017 (and:HI (match_operand:HI 1 "general_operand" "0,g")
1018 (match_operand:HI 2 "const_int_operand" "n,n")))]
1025 [(set (match_operand:QI 0 "nonimmediate_operand" "=g,g")
1026 (and:QI (match_operand:QI 1 "general_operand" "0,g")
1027 (match_operand:QI 2 "const_int_operand" "n,n")))]
1033 ;;- Bit set instructions.
1035 (define_insn "iorsi3"
1036 [(set (match_operand:SI 0 "nonimmediate_operand" "=g,g,g")
1037 (ior:SI (match_operand:SI 1 "general_operand" "0,g,g")
1038 (match_operand:SI 2 "general_operand" "g,0,g")))]
1045 (define_insn "iorhi3"
1046 [(set (match_operand:HI 0 "nonimmediate_operand" "=g,g,g")
1047 (ior:HI (match_operand:HI 1 "general_operand" "0,g,g")
1048 (match_operand:HI 2 "general_operand" "g,0,g")))]
1055 (define_insn "iorqi3"
1056 [(set (match_operand:QI 0 "nonimmediate_operand" "=g,g,g")
1057 (ior:QI (match_operand:QI 1 "general_operand" "0,g,g")
1058 (match_operand:QI 2 "general_operand" "g,0,g")))]
1065 ;;- xor instructions.
1067 (define_insn "xorsi3"
1068 [(set (match_operand:SI 0 "nonimmediate_operand" "=g,g,g")
1069 (xor:SI (match_operand:SI 1 "general_operand" "0,g,g")
1070 (match_operand:SI 2 "general_operand" "g,0,g")))]
1077 (define_insn "xorhi3"
1078 [(set (match_operand:HI 0 "nonimmediate_operand" "=g,g,g")
1079 (xor:HI (match_operand:HI 1 "general_operand" "0,g,g")
1080 (match_operand:HI 2 "general_operand" "g,0,g")))]
1087 (define_insn "xorqi3"
1088 [(set (match_operand:QI 0 "nonimmediate_operand" "=g,g,g")
1089 (xor:QI (match_operand:QI 1 "general_operand" "0,g,g")
1090 (match_operand:QI 2 "general_operand" "g,0,g")))]
1097 (define_insn "negdf2"
1098 [(set (match_operand:DF 0 "nonimmediate_operand" "=g")
1099 (neg:DF (match_operand:DF 1 "general_operand" "gF")))]
1103 (define_insn "negsf2"
1104 [(set (match_operand:SF 0 "nonimmediate_operand" "=g")
1105 (neg:SF (match_operand:SF 1 "general_operand" "gF")))]
1109 (define_insn "negsi2"
1110 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1111 (neg:SI (match_operand:SI 1 "general_operand" "g")))]
1115 (define_insn "neghi2"
1116 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
1117 (neg:HI (match_operand:HI 1 "general_operand" "g")))]
1121 (define_insn "negqi2"
1122 [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
1123 (neg:QI (match_operand:QI 1 "general_operand" "g")))]
1127 (define_insn "one_cmplsi2"
1128 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1129 (not:SI (match_operand:SI 1 "general_operand" "g")))]
1133 (define_insn "one_cmplhi2"
1134 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
1135 (not:HI (match_operand:HI 1 "general_operand" "g")))]
1139 (define_insn "one_cmplqi2"
1140 [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
1141 (not:QI (match_operand:QI 1 "general_operand" "g")))]
1145 ;; Arithmetic right shift on the VAX works by negating the shift count,
1146 ;; then emitting a right shift with the shift count negated. This means
1147 ;; that all actual shift counts in the RTL will be positive. This
1148 ;; prevents converting shifts to ZERO_EXTRACTs with negative positions,
1149 ;; which isn't valid.
1150 (define_expand "ashrsi3"
1151 [(set (match_operand:SI 0 "general_operand" "=g")
1152 (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
1153 (match_operand:QI 2 "general_operand" "g")))]
1157 if (GET_CODE (operands[2]) != CONST_INT)
1158 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
1162 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1163 (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
1164 (match_operand:QI 2 "const_int_operand" "n")))]
1169 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1170 (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
1171 (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
1175 (define_insn "ashlsi3"
1176 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1177 (ashift:SI (match_operand:SI 1 "general_operand" "g")
1178 (match_operand:QI 2 "general_operand" "g")))]
1182 if (operands[2] == const1_rtx && rtx_equal_p (operands[0], operands[1]))
1183 return \"addl2 %0,%0\";
1184 if (GET_CODE (operands[1]) == REG
1185 && GET_CODE (operands[2]) == CONST_INT)
1187 int i = INTVAL (operands[2]);
1189 return \"addl3 %1,%1,%0\";
1191 return \"moval 0[%1],%0\";
1193 return \"movad 0[%1],%0\";
1195 return \"ashl %2,%1,%0\";
1198 ;; Arithmetic right shift on the VAX works by negating the shift count.
1199 (define_expand "ashrdi3"
1200 [(set (match_operand:DI 0 "general_operand" "=g")
1201 (ashiftrt:DI (match_operand:DI 1 "general_operand" "g")
1202 (match_operand:QI 2 "general_operand" "g")))]
1206 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
1209 (define_insn "ashldi3"
1210 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
1211 (ashift:DI (match_operand:DI 1 "general_operand" "g")
1212 (match_operand:QI 2 "general_operand" "g")))]
1217 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
1218 (ashiftrt:DI (match_operand:DI 1 "general_operand" "g")
1219 (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
1223 ;; We used to have expand_shift handle logical right shifts by using extzv,
1224 ;; but this make it very difficult to do lshrdi3. Since the VAX is the
1225 ;; only machine with this kludge, it's better to just do this with a
1226 ;; define_expand and remove that case from expand_shift.
1228 (define_expand "lshrsi3"
1230 (minus:QI (const_int 32)
1232 (set (match_operand:SI 0 "general_operand" "=g")
1233 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
1235 (match_operand:SI 2 "register_operand" "g")))]
1239 operands[3] = gen_reg_rtx (QImode);
1240 operands[4] = gen_lowpart (QImode, operands[2]);
1243 ;; Rotate right on the VAX works by negating the shift count.
1244 (define_expand "rotrsi3"
1245 [(set (match_operand:SI 0 "general_operand" "=g")
1246 (rotatert:SI (match_operand:SI 1 "general_operand" "g")
1247 (match_operand:QI 2 "general_operand" "g")))]
1251 if (GET_CODE (operands[2]) != CONST_INT)
1252 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
1255 (define_insn "rotlsi3"
1256 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1257 (rotate:SI (match_operand:SI 1 "general_operand" "g")
1258 (match_operand:QI 2 "general_operand" "g")))]
1263 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1264 (rotatert:SI (match_operand:SI 1 "general_operand" "g")
1265 (match_operand:QI 2 "const_int_operand" "n")))]
1270 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1271 (rotatert:SI (match_operand:SI 1 "general_operand" "g")
1272 (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
1276 ;This insn is probably slower than a multiply and an add.
1278 ; [(set (match_operand:SI 0 "general_operand" "=g")
1279 ; (mult:SI (plus:SI (match_operand:SI 1 "general_operand" "g")
1280 ; (match_operand:SI 2 "general_operand" "g"))
1281 ; (match_operand:SI 3 "general_operand" "g")))]
1283 ; "index %1,$0x80000000,$0x7fffffff,%3,%2,%0")
1285 ;; Special cases of bit-field insns which we should
1286 ;; recognize in preference to the general case.
1287 ;; These handle aligned 8-bit and 16-bit fields,
1288 ;; which can usually be done with move instructions.
1291 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+ro")
1292 (match_operand:QI 1 "const_int_operand" "n")
1293 (match_operand:SI 2 "const_int_operand" "n"))
1294 (match_operand:SI 3 "general_operand" "g"))]
1295 "(INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
1296 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
1297 && (GET_CODE (operands[0]) == REG
1298 || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
1301 if (REG_P (operands[0]))
1303 if (INTVAL (operands[2]) != 0)
1304 return \"insv %3,%2,%1,%0\";
1308 = adjust_address (operands[0],
1309 INTVAL (operands[1]) == 8 ? QImode : HImode,
1310 INTVAL (operands[2]) / 8);
1313 if (INTVAL (operands[1]) == 8)
1314 return \"movb %3,%0\";
1315 return \"movw %3,%0\";
1319 [(set (match_operand:SI 0 "nonimmediate_operand" "=&g")
1320 (zero_extract:SI (match_operand:SI 1 "register_operand" "ro")
1321 (match_operand:QI 2 "const_int_operand" "n")
1322 (match_operand:SI 3 "const_int_operand" "n")))]
1323 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1324 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
1325 && (GET_CODE (operands[1]) == REG
1326 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
1329 if (REG_P (operands[1]))
1331 if (INTVAL (operands[3]) != 0)
1332 return \"extzv %3,%2,%1,%0\";
1336 = adjust_address (operands[1],
1337 INTVAL (operands[2]) == 8 ? QImode : HImode,
1338 INTVAL (operands[3]) / 8);
1340 if (INTVAL (operands[2]) == 8)
1341 return \"movzbl %1,%0\";
1342 return \"movzwl %1,%0\";
1346 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1347 (sign_extract:SI (match_operand:SI 1 "register_operand" "ro")
1348 (match_operand:QI 2 "const_int_operand" "n")
1349 (match_operand:SI 3 "const_int_operand" "n")))]
1350 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1351 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
1352 && (GET_CODE (operands[1]) == REG
1353 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
1356 if (REG_P (operands[1]))
1358 if (INTVAL (operands[3]) != 0)
1359 return \"extv %3,%2,%1,%0\";
1363 = adjust_address (operands[1],
1364 INTVAL (operands[2]) == 8 ? QImode : HImode,
1365 INTVAL (operands[3]) / 8);
1367 if (INTVAL (operands[2]) == 8)
1368 return \"cvtbl %1,%0\";
1369 return \"cvtwl %1,%0\";
1372 ;; Register-only SImode cases of bit-field insns.
1377 (sign_extract:SI (match_operand:SI 0 "register_operand" "r")
1378 (match_operand:QI 1 "general_operand" "g")
1379 (match_operand:SI 2 "general_operand" "g"))
1380 (match_operand:SI 3 "general_operand" "g")))]
1387 (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1388 (match_operand:QI 1 "general_operand" "g")
1389 (match_operand:SI 2 "general_operand" "g"))
1390 (match_operand:SI 3 "general_operand" "g")))]
1392 "cmpzv %2,%1,%0,%3")
1394 ;; When the field position and size are constant and the destination
1395 ;; is a register, extv and extzv are much slower than a rotate followed
1396 ;; by a bicl or sign extension. Because we might end up choosing ext[z]v
1397 ;; anyway, we can't allow immediate values for the primary source operand.
1400 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1401 (sign_extract:SI (match_operand:SI 1 "register_operand" "ro")
1402 (match_operand:QI 2 "general_operand" "g")
1403 (match_operand:SI 3 "general_operand" "g")))]
1407 if (GET_CODE (operands[3]) != CONST_INT || GET_CODE (operands[2]) != CONST_INT
1408 || GET_CODE (operands[0]) != REG
1409 || (INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16))
1410 return \"extv %3,%2,%1,%0\";
1411 if (INTVAL (operands[2]) == 8)
1412 return \"rotl %R3,%1,%0\;cvtbl %0,%0\";
1413 return \"rotl %R3,%1,%0\;cvtwl %0,%0\";
1417 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1418 (zero_extract:SI (match_operand:SI 1 "register_operand" "ro")
1419 (match_operand:QI 2 "general_operand" "g")
1420 (match_operand:SI 3 "general_operand" "g")))]
1424 if (GET_CODE (operands[3]) != CONST_INT || GET_CODE (operands[2]) != CONST_INT
1425 || GET_CODE (operands[0]) != REG)
1426 return \"extzv %3,%2,%1,%0\";
1427 if (INTVAL (operands[2]) == 8)
1428 return \"rotl %R3,%1,%0\;movzbl %0,%0\";
1429 if (INTVAL (operands[2]) == 16)
1430 return \"rotl %R3,%1,%0\;movzwl %0,%0\";
1431 if (INTVAL (operands[3]) & 31)
1432 return \"rotl %R3,%1,%0\;bicl2 %M2,%0\";
1433 if (rtx_equal_p (operands[0], operands[1]))
1434 return \"bicl2 %M2,%0\";
1435 return \"bicl3 %M2,%1,%0\";
1438 ;; Non-register cases.
1439 ;; nonimmediate_operand is used to make sure that mode-ambiguous cases
1440 ;; don't match these (and therefore match the cases above instead).
1445 (sign_extract:SI (match_operand:QI 0 "memory_operand" "m")
1446 (match_operand:QI 1 "general_operand" "g")
1447 (match_operand:SI 2 "general_operand" "g"))
1448 (match_operand:SI 3 "general_operand" "g")))]
1455 (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rm")
1456 (match_operand:QI 1 "general_operand" "g")
1457 (match_operand:SI 2 "general_operand" "g"))
1458 (match_operand:SI 3 "general_operand" "g")))]
1460 "cmpzv %2,%1,%0,%3")
1463 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1464 (sign_extract:SI (match_operand:QI 1 "memory_operand" "m")
1465 (match_operand:QI 2 "general_operand" "g")
1466 (match_operand:SI 3 "general_operand" "g")))]
1470 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[2]) != CONST_INT
1471 || GET_CODE (operands[3]) != CONST_INT
1472 || (INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16)
1473 || INTVAL (operands[2]) + INTVAL (operands[3]) > 32
1474 || side_effects_p (operands[1])
1475 || (GET_CODE (operands[1]) == MEM
1476 && mode_dependent_address_p (XEXP (operands[1], 0))))
1477 return \"extv %3,%2,%1,%0\";
1478 if (INTVAL (operands[2]) == 8)
1479 return \"rotl %R3,%1,%0\;cvtbl %0,%0\";
1480 return \"rotl %R3,%1,%0\;cvtwl %0,%0\";
1483 (define_expand "extzv"
1484 [(set (match_operand:SI 0 "general_operand" "")
1485 (zero_extract:SI (match_operand:SI 1 "general_operand" "")
1486 (match_operand:QI 2 "general_operand" "")
1487 (match_operand:SI 3 "general_operand" "")))]
1492 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1493 (zero_extract:SI (match_operand:QI 1 "memory_operand" "m")
1494 (match_operand:QI 2 "general_operand" "g")
1495 (match_operand:SI 3 "general_operand" "g")))]
1499 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[2]) != CONST_INT
1500 || GET_CODE (operands[3]) != CONST_INT
1501 || INTVAL (operands[2]) + INTVAL (operands[3]) > 32
1502 || side_effects_p (operands[1])
1503 || (GET_CODE (operands[1]) == MEM
1504 && mode_dependent_address_p (XEXP (operands[1], 0))))
1505 return \"extzv %3,%2,%1,%0\";
1506 if (INTVAL (operands[2]) == 8)
1507 return \"rotl %R3,%1,%0\;movzbl %0,%0\";
1508 if (INTVAL (operands[2]) == 16)
1509 return \"rotl %R3,%1,%0\;movzwl %0,%0\";
1510 return \"rotl %R3,%1,%0\;bicl2 %M2,%0\";
1513 (define_expand "insv"
1514 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
1515 (match_operand:QI 1 "general_operand" "")
1516 (match_operand:SI 2 "general_operand" ""))
1517 (match_operand:SI 3 "general_operand" ""))]
1522 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+g")
1523 (match_operand:QI 1 "general_operand" "g")
1524 (match_operand:SI 2 "general_operand" "g"))
1525 (match_operand:SI 3 "general_operand" "g"))]
1530 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
1531 (match_operand:QI 1 "general_operand" "g")
1532 (match_operand:SI 2 "general_operand" "g"))
1533 (match_operand:SI 3 "general_operand" "g"))]
1539 (label_ref (match_operand 0 "" "")))]
1545 (if_then_else (eq (cc0)
1547 (label_ref (match_operand 0 "" ""))
1554 (if_then_else (ne (cc0)
1556 (label_ref (match_operand 0 "" ""))
1563 (if_then_else (gt (cc0)
1565 (label_ref (match_operand 0 "" ""))
1572 (if_then_else (gtu (cc0)
1574 (label_ref (match_operand 0 "" ""))
1581 (if_then_else (lt (cc0)
1583 (label_ref (match_operand 0 "" ""))
1590 (if_then_else (ltu (cc0)
1592 (label_ref (match_operand 0 "" ""))
1599 (if_then_else (ge (cc0)
1601 (label_ref (match_operand 0 "" ""))
1608 (if_then_else (geu (cc0)
1610 (label_ref (match_operand 0 "" ""))
1617 (if_then_else (le (cc0)
1619 (label_ref (match_operand 0 "" ""))
1626 (if_then_else (leu (cc0)
1628 (label_ref (match_operand 0 "" ""))
1633 ;; Recognize reversed jumps.
1636 (if_then_else (match_operator 0 "comparison_operator"
1640 (label_ref (match_operand 1 "" ""))))]
1642 "j%C0 %l1") ; %C0 negates condition
1644 ;; Recognize jbs, jlbs, jbc and jlbc instructions. Note that the operand
1645 ;; of jlbs and jlbc insns are SImode in the hardware. However, if it is
1646 ;; memory, we use QImode in the insn. So we can't use those instructions
1647 ;; for mode-dependent addresses.
1652 (ne (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g")
1654 (match_operand:SI 1 "general_operand" "I,g"))
1656 (label_ref (match_operand 2 "" ""))
1666 (eq (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g")
1668 (match_operand:SI 1 "general_operand" "I,g"))
1670 (label_ref (match_operand 2 "" ""))
1680 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r")
1682 (match_operand:SI 1 "general_operand" "I,g"))
1684 (label_ref (match_operand 2 "" ""))
1694 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r")
1696 (match_operand:SI 1 "general_operand" "I,g"))
1698 (label_ref (match_operand 2 "" ""))
1705 ;; Subtract-and-jump and Add-and-jump insns.
1706 ;; These are not used when output is for the Unix assembler
1707 ;; because it does not know how to modify them to reach far.
1709 ;; Normal sob insns.
1714 (gt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
1717 (label_ref (match_operand 1 "" ""))
1720 (plus:SI (match_dup 0)
1728 (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
1731 (label_ref (match_operand 1 "" ""))
1734 (plus:SI (match_dup 0)
1739 ;; Normal aob insns. Define a version for when operands[1] is a constant.
1743 (lt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
1745 (match_operand:SI 1 "general_operand" "g"))
1746 (label_ref (match_operand 2 "" ""))
1749 (plus:SI (match_dup 0)
1752 "jaoblss %1,%0,%l2")
1757 (lt (match_operand:SI 0 "nonimmediate_operand" "+g")
1758 (match_operand:SI 1 "general_operand" "g"))
1759 (label_ref (match_operand 2 "" ""))
1762 (plus:SI (match_dup 0)
1764 "!TARGET_UNIX_ASM && GET_CODE (operands[1]) == CONST_INT"
1765 "jaoblss %P1,%0,%l2")
1770 (le (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
1772 (match_operand:SI 1 "general_operand" "g"))
1773 (label_ref (match_operand 2 "" ""))
1776 (plus:SI (match_dup 0)
1779 "jaobleq %1,%0,%l2")
1784 (le (match_operand:SI 0 "nonimmediate_operand" "+g")
1785 (match_operand:SI 1 "general_operand" "g"))
1786 (label_ref (match_operand 2 "" ""))
1789 (plus:SI (match_dup 0)
1791 "!TARGET_UNIX_ASM && GET_CODE (operands[1]) == CONST_INT"
1792 "jaobleq %P1,%0,%l2")
1794 ;; Something like a sob insn, but compares against -1.
1795 ;; This finds `while (foo--)' which was changed to `while (--foo != -1)'.
1800 (ne (match_operand:SI 0 "nonimmediate_operand" "+g")
1802 (label_ref (match_operand 1 "" ""))
1805 (plus:SI (match_dup 0)
1808 "decl %0\;jgequ %l1")
1810 (define_expand "call_pop"
1811 [(parallel [(call (match_operand:QI 0 "memory_operand" "")
1812 (match_operand:SI 1 "const_int_operand" ""))
1814 (plus:SI (reg:SI 14)
1815 (match_operand:SI 3 "immediate_operand" "")))])]
1818 if (INTVAL (operands[3]) > 255 * 4 || INTVAL (operands[3]) % 4)
1821 /* Operand 1 is the number of bytes to be popped by DW_CFA_GNU_args_size
1822 during EH unwinding. We must include the argument count pushed by
1823 the calls instruction. */
1824 operands[1] = GEN_INT (INTVAL (operands[3]) + 4);
1827 (define_insn "*call_pop"
1828 [(call (match_operand:QI 0 "memory_operand" "m")
1829 (match_operand:SI 1 "const_int_operand" "n"))
1830 (set (reg:SI 14) (plus:SI (reg:SI 14)
1831 (match_operand:SI 2 "immediate_operand" "i")))]
1834 operands[1] = GEN_INT ((INTVAL (operands[1]) - 4) / 4);
1835 return "calls %1,%0";
1838 (define_expand "call_value_pop"
1839 [(parallel [(set (match_operand 0 "" "")
1840 (call (match_operand:QI 1 "memory_operand" "")
1841 (match_operand:SI 2 "const_int_operand" "")))
1843 (plus:SI (reg:SI 14)
1844 (match_operand:SI 4 "immediate_operand" "")))])]
1847 if (INTVAL (operands[4]) > 255 * 4 || INTVAL (operands[4]) % 4)
1850 /* Operand 2 is the number of bytes to be popped by DW_CFA_GNU_args_size
1851 during EH unwinding. We must include the argument count pushed by
1852 the calls instruction. */
1853 operands[2] = GEN_INT (INTVAL (operands[4]) + 4);
1856 (define_insn "*call_value_pop"
1857 [(set (match_operand 0 "" "")
1858 (call (match_operand:QI 1 "memory_operand" "m")
1859 (match_operand:SI 2 "const_int_operand" "n")))
1860 (set (reg:SI 14) (plus:SI (reg:SI 14)
1861 (match_operand:SI 3 "immediate_operand" "i")))]
1865 operands[2] = GEN_INT ((INTVAL (operands[2]) - 4) / 4);
1866 return \"calls %2,%1\";
1869 (define_expand "call"
1870 [(call (match_operand:QI 0 "memory_operand" "")
1871 (match_operand:SI 1 "const_int_operand" ""))]
1875 /* Operand 1 is the number of bytes to be popped by DW_CFA_GNU_args_size
1876 during EH unwinding. We must include the argument count pushed by
1877 the calls instruction. */
1878 operands[1] = GEN_INT (INTVAL (operands[1]) + 4);
1881 (define_insn "*call"
1882 [(call (match_operand:QI 0 "memory_operand" "m")
1883 (match_operand:SI 1 "const_int_operand" ""))]
1887 (define_expand "call_value"
1888 [(set (match_operand 0 "" "")
1889 (call (match_operand:QI 1 "memory_operand" "")
1890 (match_operand:SI 2 "const_int_operand" "")))]
1894 /* Operand 2 is the number of bytes to be popped by DW_CFA_GNU_args_size
1895 during EH unwinding. We must include the argument count pushed by
1896 the calls instruction. */
1897 operands[2] = GEN_INT (INTVAL (operands[2]) + 4);
1900 (define_insn "*call_value"
1901 [(set (match_operand 0 "" "")
1902 (call (match_operand:QI 1 "memory_operand" "m")
1903 (match_operand:SI 2 "const_int_operand" "")))]
1907 ;; Call subroutine returning any type.
1909 (define_expand "untyped_call"
1910 [(parallel [(call (match_operand 0 "" "")
1912 (match_operand 1 "" "")
1913 (match_operand 2 "" "")])]
1919 emit_call_insn (gen_call_pop (operands[0], const0_rtx, NULL, const0_rtx));
1921 for (i = 0; i < XVECLEN (operands[2], 0); i++)
1923 rtx set = XVECEXP (operands[2], 0, i);
1924 emit_move_insn (SET_DEST (set), SET_SRC (set));
1927 /* The optimizer does not know that the call sets the function value
1928 registers we stored in the result block. We avoid problems by
1929 claiming that all hard registers are used and clobbered at this
1931 emit_insn (gen_blockage ());
1936 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
1937 ;; all of memory. This blocks insns from being moved across this point.
1939 (define_insn "blockage"
1940 [(unspec_volatile [(const_int 0)] VUNSPEC_BLOCKAGE)]
1944 (define_insn "return"
1949 (define_expand "epilogue"
1954 emit_jump_insn (gen_return ());
1963 ;; This had a wider constraint once, and it had trouble.
1964 ;; If you are tempted to try `g', please don't--it's not worth
1965 ;; the risk we will reopen the same bug.
1966 (define_insn "indirect_jump"
1967 [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
1971 ;; This is here to accept 5 arguments (as passed by expand_end_case)
1972 ;; and pass the first 4 along to the casesi1 pattern that really does the work.
1973 (define_expand "casesi"
1974 [(match_operand:SI 0 "general_operand" "") ; index
1975 (match_operand:SI 1 "general_operand" "") ; lower
1976 (match_operand:SI 2 "general_operand" "") ; upper-lower
1977 (match_operand 3 "" "") ; table label
1978 (match_operand 4 "" "")] ; default label
1981 emit_jump_insn (gen_casesi1 (operands[0], operands[1],
1982 operands[2], operands[3]));
1986 (define_insn "casesi1"
1989 (leu (minus:SI (match_operand:SI 0 "general_operand" "g")
1990 (match_operand:SI 1 "general_operand" "g"))
1991 (match_operand:SI 2 "general_operand" "g"))
1992 (plus:SI (sign_extend:SI
1993 (mem:HI (plus:SI (mult:SI (minus:SI (match_dup 0)
1997 (label_ref:SI (match_operand 3 "" "")))
2002 ;; This can arise by simplification when operand 1 is a constant int.
2006 (leu (plus:SI (match_operand:SI 0 "general_operand" "g")
2007 (match_operand:SI 1 "const_int_operand" "n"))
2008 (match_operand:SI 2 "general_operand" "g"))
2009 (plus:SI (sign_extend:SI
2010 (mem:HI (plus:SI (mult:SI (plus:SI (match_dup 0)
2014 (label_ref:SI (match_operand 3 "" "")))
2019 operands[1] = GEN_INT (-INTVAL (operands[1]));
2020 return \"casel %0,%1,%2\";
2023 ;; This can arise by simplification when the base for the case insn is zero.
2026 (if_then_else (leu (match_operand:SI 0 "general_operand" "g")
2027 (match_operand:SI 1 "general_operand" "g"))
2028 (plus:SI (sign_extend:SI
2029 (mem:HI (plus:SI (mult:SI (match_dup 0)
2032 (label_ref:SI (match_operand 2 "" "")))
2037 ;;- load or push effective address
2038 ;; These come after the move and add/sub patterns
2039 ;; because we don't want pushl $1 turned into pushad 1.
2040 ;; or addl3 r1,r2,r3 turned into movab 0(r1)[r2],r3.
2042 ;; It does not work to use constraints to distinguish pushes from moves,
2043 ;; because < matches any autodecrement, not just a push.
2046 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
2047 (match_operand:QI 1 "address_operand" "p"))]
2051 if (push_operand (operands[0], SImode))
2052 return \"pushab %a1\";
2054 return \"movab %a1,%0\";
2058 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
2059 (match_operand:HI 1 "address_operand" "p"))]
2063 if (push_operand (operands[0], SImode))
2064 return \"pushaw %a1\";
2066 return \"movaw %a1,%0\";
2070 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
2071 (match_operand:SI 1 "address_operand" "p"))]
2075 if (push_operand (operands[0], SImode))
2076 return \"pushal %a1\";
2078 return \"moval %a1,%0\";
2082 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
2083 (match_operand:DI 1 "address_operand" "p"))]
2087 if (push_operand (operands[0], SImode))
2088 return \"pushaq %a1\";
2090 return \"movaq %a1,%0\";
2094 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
2095 (match_operand:SF 1 "address_operand" "p"))]
2099 if (push_operand (operands[0], SImode))
2100 return \"pushaf %a1\";
2102 return \"movaf %a1,%0\";
2106 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
2107 (match_operand:DF 1 "address_operand" "p"))]
2111 if (push_operand (operands[0], SImode))
2112 return \"pushad %a1\";
2114 return \"movad %a1,%0\";
2117 ;; These used to be peepholes, but it is more straightforward to do them
2118 ;; as single insns. However, we must force the output to be a register
2119 ;; if it is not an offsettable address so that we know that we can assign
2122 ;; If we had a good way of evaluating the relative costs, these could be
2123 ;; machine-independent.
2125 ;; Optimize extzv ...,z; andl2 ...,z
2126 ;; or ashl ...,z; andl2 ...,z
2127 ;; with other operands constant. This is what the combiner converts the
2128 ;; above sequences to before attempting to recognize the new insn.
2131 [(set (match_operand:SI 0 "nonimmediate_operand" "=ro")
2132 (and:SI (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
2133 (match_operand:QI 2 "const_int_operand" "n"))
2134 (match_operand:SI 3 "const_int_operand" "n")))]
2135 "(INTVAL (operands[3]) & ~((1 << (32 - INTVAL (operands[2]))) - 1)) == 0"
2138 unsigned long mask1 = INTVAL (operands[3]);
2139 unsigned long mask2 = (1 << (32 - INTVAL (operands[2]))) - 1;
2141 if ((mask1 & mask2) != mask1)
2142 operands[3] = GEN_INT (mask1 & mask2);
2144 return \"rotl %R2,%1,%0\;bicl2 %N3,%0\";
2147 ;; left-shift and mask
2148 ;; The only case where `ashl' is better is if the mask only turns off
2149 ;; bits that the ashl would anyways, in which case it should have been
2153 [(set (match_operand:SI 0 "nonimmediate_operand" "=ro")
2154 (and:SI (ashift:SI (match_operand:SI 1 "general_operand" "g")
2155 (match_operand:QI 2 "const_int_operand" "n"))
2156 (match_operand:SI 3 "const_int_operand" "n")))]
2161 = GEN_INT (INTVAL (operands[3]) & ~((1 << INTVAL (operands[2])) - 1));
2162 return \"rotl %2,%1,%0\;bicl2 %N3,%0\";
2165 ;; Instruction sequence to sync the VAX instruction stream.
2166 (define_insn "sync_istream"
2167 [(unspec_volatile [(const_int 0)] VUNSPEC_SYNC_ISTREAM)]
2169 "movpsl -(%|sp)\;pushal 1(%|pc)\;rei")