1 ;; Machine description for GNU compiler, VAX Version
2 ;; Copyright (C) 1987, 1988, 1991, 1994, 1995, 1996, 1998, 1999, 2000, 2001,
3 ;; 2002, 2004, 2005 Free Software Foundation, Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
23 ;;- Instruction patterns. When multiple patterns apply,
24 ;;- the first one in the file is chosen.
26 ;;- See file "rtl.def" for documentation on define_insn, match_*, et al.
28 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
29 ;;- updates for most instructions.
31 ;; UNSPEC_VOLATILE usage:
34 [(VUNSPEC_BLOCKAGE 0) ; `blockage' insn to prevent scheduling across an
36 (VUNSPEC_SYNC_ISTREAM 1) ; sequence of insns to sync the I-stream
40 ;; Integer modes supported on VAX, with a mapping from machine mode
41 ;; to mnemonic suffix. DImode is always a special case.
42 (define_mode_macro VAXint [QI HI SI])
43 (define_mode_attr isfx [(QI "b") (HI "w") (SI "l")])
45 ;; Similar for float modes supported on VAX.
46 (define_mode_macro VAXfp [SF DF])
47 (define_mode_attr fsfx [(SF "f") (DF "%#")])
49 ;; Some output patterns want integer immediates with a prefix...
50 (define_mode_attr iprefx [(QI "B") (HI "H") (SI "N")])
52 ;; We don't want to allow a constant operand for test insns because
53 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
54 ;; be folded while optimizing anyway.
56 (define_insn "tst<mode>"
58 (match_operand:VAXint 0 "nonimmediate_operand" "g"))]
60 "tst<VAXint:isfx> %0")
62 (define_insn "tst<mode>"
64 (match_operand:VAXfp 0 "general_operand" "gF"))]
68 (define_insn "cmp<mode>"
70 (compare (match_operand:VAXint 0 "nonimmediate_operand" "g")
71 (match_operand:VAXint 1 "general_operand" "g")))]
73 "cmp<VAXint:isfx> %0,%1")
75 (define_insn "cmp<mode>"
77 (compare (match_operand:VAXfp 0 "general_operand" "gF,gF")
78 (match_operand:VAXfp 1 "general_operand" "G,gF")))]
82 cmp<VAXfp:fsfx> %0,%1")
84 (define_insn "*bit<mode>"
86 (and:VAXint (match_operand:VAXint 0 "general_operand" "g")
87 (match_operand:VAXint 1 "general_operand" "g")))]
89 "bit<VAXint:isfx> %0,%1")
91 ;; The VAX has no sCOND insns. It does have add/subtract with carry
92 ;; which could be used to implement the sltu and sgeu patterns. However,
93 ;; to do this properly requires a complete rewrite of the compare insns
94 ;; to keep them together with the sltu/sgeu insns until after the
95 ;; reload pass is complete. The previous implementation didn't do this
96 ;; and has been deleted.
99 (define_insn "mov<mode>"
100 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g")
101 (match_operand:VAXfp 1 "general_operand" "G,gF"))]
105 mov<VAXfp:fsfx> %1,%0")
107 ;; Some VAXen don't support this instruction.
108 ;;(define_insn "movti"
109 ;; [(set (match_operand:TI 0 "general_operand" "=g")
110 ;; (match_operand:TI 1 "general_operand" "g"))]
115 [(set (match_operand:DI 0 "nonimmediate_operand" "=g,g")
116 (match_operand:DI 1 "general_operand" "I,g"))]
122 ;; The VAX move instructions have space-time tradeoffs. On a MicroVAX
123 ;; register-register mov instructions take 3 bytes and 2 CPU cycles. clrl
124 ;; takes 2 bytes and 3 cycles. mov from constant to register takes 2 cycles
125 ;; if the constant is smaller than 4 bytes, 3 cycles for a longword
126 ;; constant. movz, mneg, and mcom are as fast as mov, so movzwl is faster
127 ;; than movl for positive constants that fit in 16 bits but not 6 bits. cvt
128 ;; instructions take 4 cycles. inc takes 3 cycles. The machine description
129 ;; is willing to trade 1 byte for 1 cycle (clrl instead of movl $0; cvtwl
132 ;; Cycle counts for other models may vary (on a VAX 750 they are similar,
133 ;; but on a VAX 9000 most move and add instructions with one constant
134 ;; operand take 1 cycle).
136 ;; Loads of constants between 64 and 128 used to be done with
137 ;; "addl3 $63,#,dst" but this is slower than movzbl and takes as much space.
139 (define_insn "mov<mode>"
140 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
141 (match_operand:VAXint 1 "general_operand" "g"))]
143 "* return vax_output_int_move (insn, operands, <MODE>mode);")
145 (define_insn "movstricthi"
146 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+g"))
147 (match_operand:HI 1 "general_operand" "g"))]
151 if (GET_CODE (operands[1]) == CONST_INT)
153 int i = INTVAL (operands[1]);
156 else if ((unsigned int)i < 64)
157 return \"movw %1,%0\";
158 else if ((unsigned int)~i < 64)
159 return \"mcomw %H1,%0\";
160 else if ((unsigned int)i < 256)
161 return \"movzbw %1,%0\";
163 return \"movw %1,%0\";
166 (define_insn "movstrictqi"
167 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+g"))
168 (match_operand:QI 1 "general_operand" "g"))]
172 if (GET_CODE (operands[1]) == CONST_INT)
174 int i = INTVAL (operands[1]);
177 else if ((unsigned int)~i < 64)
178 return \"mcomb %B1,%0\";
180 return \"movb %1,%0\";
183 ;; This is here to accept 4 arguments and pass the first 3 along
184 ;; to the movmemhi1 pattern that really does the work.
185 (define_expand "movmemhi"
186 [(set (match_operand:BLK 0 "general_operand" "=g")
187 (match_operand:BLK 1 "general_operand" "g"))
188 (use (match_operand:HI 2 "general_operand" "g"))
189 (match_operand 3 "" "")]
192 emit_insn (gen_movmemhi1 (operands[0], operands[1], operands[2]));
196 ;; The definition of this insn does not really explain what it does,
197 ;; but it should suffice
198 ;; that anything generated as this insn will be recognized as one
199 ;; and that it won't successfully combine with anything.
200 (define_insn "movmemhi1"
201 [(set (match_operand:BLK 0 "memory_operand" "=m")
202 (match_operand:BLK 1 "memory_operand" "m"))
203 (use (match_operand:HI 2 "general_operand" "g"))
209 (clobber (reg:SI 5))]
213 ;; Extension and truncation insns.
215 (define_insn "truncsiqi2"
216 [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
217 (truncate:QI (match_operand:SI 1 "nonimmediate_operand" "g")))]
221 (define_insn "truncsihi2"
222 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
223 (truncate:HI (match_operand:SI 1 "nonimmediate_operand" "g")))]
227 (define_insn "trunchiqi2"
228 [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
229 (truncate:QI (match_operand:HI 1 "nonimmediate_operand" "g")))]
233 (define_insn "extendhisi2"
234 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
235 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
239 (define_insn "extendqihi2"
240 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
241 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
245 (define_insn "extendqisi2"
246 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
247 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
251 (define_insn "extendsfdf2"
252 [(set (match_operand:DF 0 "nonimmediate_operand" "=g")
253 (float_extend:DF (match_operand:SF 1 "general_operand" "gF")))]
257 (define_insn "truncdfsf2"
258 [(set (match_operand:SF 0 "nonimmediate_operand" "=g")
259 (float_truncate:SF (match_operand:DF 1 "general_operand" "gF")))]
263 (define_insn "zero_extendhisi2"
264 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
265 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
269 (define_insn "zero_extendqihi2"
270 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
271 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
275 (define_insn "zero_extendqisi2"
276 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
277 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
281 ;; Fix-to-float conversion insns.
283 (define_insn "float<VAXint:mode><VAXfp:mode>2"
284 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g")
285 (float:VAXfp (match_operand:VAXint 1 "nonimmediate_operand" "g")))]
287 "cvt<VAXint:isfx><VAXfp:fsfx> %1,%0")
289 ;; Float-to-fix conversion insns.
291 (define_insn "fix_trunc<VAXfp:mode><VAXint:mode>2"
292 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
293 (fix:VAXint (fix:VAXfp (match_operand:VAXfp 1 "general_operand" "gF"))))]
295 "cvt<VAXfp:fsfx><VAXint:isfx> %1,%0")
297 ;;- All kinds of add instructions.
299 (define_insn "add<mode>3"
300 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g,g")
301 (plus:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF,gF")
302 (match_operand:VAXfp 2 "general_operand" "gF,0,gF")))]
305 add<VAXfp:fsfx>2 %2,%0
306 add<VAXfp:fsfx>2 %1,%0
307 add<VAXfp:fsfx>3 %1,%2,%0")
309 (define_insn "add<mode>3"
310 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
311 (plus:VAXint (match_operand:VAXint 1 "general_operand" "g")
312 (match_operand:VAXint 2 "general_operand" "g")))]
314 "* return vax_output_int_add (insn, operands, <MODE>mode);")
316 ;; The add-with-carry (adwc) instruction only accepts two operands.
317 (define_insn "adddi3"
318 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro>,ro>")
319 (plus:DI (match_operand:DI 1 "general_operand" "%0,ro>")
320 (match_operand:DI 2 "general_operand" "Fro,F")))]
328 split_quadword_operands (operands, low, 3);
330 if (rtx_equal_p (operands[0], operands[1]))
332 if (low[2] == const0_rtx)
333 /* Should examine operand, punt if not POST_INC. */
334 pattern = \"tstl %0\", carry = 0;
335 else if (low[2] == const1_rtx)
336 pattern = \"incl %0\";
338 pattern = \"addl2 %2,%0\";
342 if (low[2] == const0_rtx)
343 pattern = \"movl %1,%0\", carry = 0;
345 pattern = \"addl3 %2,%1,%0\";
348 output_asm_insn (pattern, low);
350 /* If CARRY is 0, we don't have any carry value to worry about. */
351 return get_insn_template (CODE_FOR_addsi3, insn);
352 /* %0 = C + %1 + %2 */
353 if (!rtx_equal_p (operands[0], operands[1]))
354 output_asm_insn ((operands[1] == const0_rtx
356 : \"movl %1,%0\"), operands);
357 return \"adwc %2,%0\";
360 ;;- All kinds of subtract instructions.
362 (define_insn "sub<mode>3"
363 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g")
364 (minus:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF")
365 (match_operand:VAXfp 2 "general_operand" "gF,gF")))]
368 sub<VAXfp:fsfx>2 %2,%0
369 sub<VAXfp:fsfx>3 %2,%1,%0")
371 (define_insn "sub<mode>3"
372 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
373 (minus:VAXint (match_operand:VAXint 1 "general_operand" "0,g")
374 (match_operand:VAXint 2 "general_operand" "g,g")))]
377 sub<VAXint:isfx>2 %2,%0
378 sub<VAXint:isfx>3 %2,%1,%0")
380 ;; The subtract-with-carry (sbwc) instruction only takes two operands.
381 (define_insn "subdi3"
382 [(set (match_operand:DI 0 "nonimmediate_operand" "=or>,or>")
383 (minus:DI (match_operand:DI 1 "general_operand" "0,or>")
384 (match_operand:DI 2 "general_operand" "For,F")))]
392 split_quadword_operands (operands, low, 3);
393 /* Subtract low parts. */
394 if (rtx_equal_p (operands[0], operands[1]))
396 if (low[2] == const0_rtx)
397 pattern = 0, carry = 0;
398 else if (low[2] == constm1_rtx)
399 pattern = \"decl %0\";
401 pattern = \"subl2 %2,%0\";
405 if (low[2] == constm1_rtx)
406 pattern = \"decl %0\";
407 else if (low[2] == const0_rtx)
408 pattern = get_insn_template (CODE_FOR_movsi, insn), carry = 0;
410 pattern = \"subl3 %2,%1,%0\";
413 output_asm_insn (pattern, low);
416 if (!rtx_equal_p (operands[0], operands[1]))
417 return \"movl %1,%0\;sbwc %2,%0\";
418 return \"sbwc %2,%0\";
419 /* %0 = %2 - %1 - C */
421 return get_insn_template (CODE_FOR_subsi3, insn);
424 ;;- Multiply instructions.
426 (define_insn "mul<mode>3"
427 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g,g")
428 (mult:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF,gF")
429 (match_operand:VAXfp 2 "general_operand" "gF,0,gF")))]
432 mul<VAXfp:fsfx>2 %2,%0
433 mul<VAXfp:fsfx>2 %1,%0
434 mul<VAXfp:fsfx>3 %1,%2,%0")
436 (define_insn "mul<mode>3"
437 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g")
438 (mult:VAXint (match_operand:VAXint 1 "general_operand" "0,g,g")
439 (match_operand:VAXint 2 "general_operand" "g,0,g")))]
442 mul<VAXint:isfx>2 %2,%0
443 mul<VAXint:isfx>2 %1,%0
444 mul<VAXint:isfx>3 %1,%2,%0")
446 (define_insn "mulsidi3"
447 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
448 (mult:DI (sign_extend:DI
449 (match_operand:SI 1 "nonimmediate_operand" "g"))
451 (match_operand:SI 2 "nonimmediate_operand" "g"))))]
456 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
458 (mult:DI (sign_extend:DI
459 (match_operand:SI 1 "nonimmediate_operand" "g"))
461 (match_operand:SI 2 "nonimmediate_operand" "g")))
462 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "g"))))]
466 ;; 'F' constraint means type CONST_DOUBLE
468 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
470 (mult:DI (sign_extend:DI
471 (match_operand:SI 1 "nonimmediate_operand" "g"))
473 (match_operand:SI 2 "nonimmediate_operand" "g")))
474 (match_operand:DI 3 "immediate_operand" "F")))]
475 "GET_CODE (operands[3]) == CONST_DOUBLE
476 && CONST_DOUBLE_HIGH (operands[3]) == (CONST_DOUBLE_LOW (operands[3]) >> 31)"
479 if (CONST_DOUBLE_HIGH (operands[3]))
480 operands[3] = GEN_INT (CONST_DOUBLE_LOW (operands[3]));
481 return \"emul %1,%2,%3,%0\";
484 ;;- Divide instructions.
486 (define_insn "div<mode>3"
487 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g")
488 (div:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF")
489 (match_operand:VAXfp 2 "general_operand" "gF,gF")))]
492 div<VAXfp:fsfx>2 %2,%0
493 div<VAXfp:fsfx>3 %2,%1,%0")
495 (define_insn "div<mode>3"
496 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
497 (div:VAXint (match_operand:VAXint 1 "general_operand" "0,g")
498 (match_operand:VAXint 2 "general_operand" "g,g")))]
501 div<VAXint:isfx>2 %2,%0
502 div<VAXint:isfx>3 %2,%1,%0")
504 ;This is left out because it is very slow;
505 ;we are better off programming around the "lack" of this insn.
506 ;(define_insn "divmoddisi4"
507 ; [(set (match_operand:SI 0 "general_operand" "=g")
508 ; (div:SI (match_operand:DI 1 "general_operand" "g")
509 ; (match_operand:SI 2 "general_operand" "g")))
510 ; (set (match_operand:SI 3 "general_operand" "=g")
511 ; (mod:SI (match_operand:DI 1 "general_operand" "g")
512 ; (match_operand:SI 2 "general_operand" "g")))]
514 ; "ediv %2,%1,%0,%3")
516 ;; Bit-and on the VAX is done with a clear-bits insn.
517 (define_expand "and<mode>3"
518 [(set (match_operand:VAXint 0 "nonimmediate_operand" "")
519 (and:VAXint (not:VAXint (match_operand:VAXint 1 "general_operand" ""))
520 (match_operand:VAXint 2 "general_operand" "")))]
524 rtx op1 = operands[1];
526 /* If there is a constant argument, complement that one. */
527 if (GET_CODE (operands[2]) == CONST_INT && GET_CODE (op1) != CONST_INT)
529 operands[1] = operands[2];
534 if (GET_CODE (op1) == CONST_INT)
535 operands[1] = GEN_INT (~INTVAL (op1));
537 operands[1] = expand_unop (<MODE>mode, one_cmpl_optab, op1, 0, 1);
540 (define_insn "*and<mode>"
541 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
542 (and:VAXint (not:VAXint (match_operand:VAXint 1 "general_operand" "g,g"))
543 (match_operand:VAXint 2 "general_operand" "0,g")))]
546 bic<VAXint:isfx>2 %1,%0
547 bic<VAXint:isfx>3 %1,%2,%0")
549 ;; The following used to be needed because constant propagation can
550 ;; create them starting from the bic insn patterns above. This is no
551 ;; longer a problem. However, having these patterns allows optimization
552 ;; opportunities in combine.c.
554 (define_insn "*and<mode>_const_int"
555 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
556 (and:VAXint (match_operand:VAXint 1 "general_operand" "0,g")
557 (match_operand:VAXint 2 "const_int_operand" "n,n")))]
560 bic<VAXint:isfx>2 %<VAXint:iprefx>2,%0
561 bic<VAXint:isfx>3 %<VAXint:iprefx>2,%1,%0")
564 ;;- Bit set instructions.
566 (define_insn "ior<mode>3"
567 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g")
568 (ior:VAXint (match_operand:VAXint 1 "general_operand" "0,g,g")
569 (match_operand:VAXint 2 "general_operand" "g,0,g")))]
572 bis<VAXint:isfx>2 %2,%0
573 bis<VAXint:isfx>2 %1,%0
574 bis<VAXint:isfx>3 %2,%1,%0")
576 ;;- xor instructions.
578 (define_insn "xor<mode>3"
579 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g")
580 (xor:VAXint (match_operand:VAXint 1 "general_operand" "0,g,g")
581 (match_operand:VAXint 2 "general_operand" "g,0,g")))]
584 xor<VAXint:isfx>2 %2,%0
585 xor<VAXint:isfx>2 %1,%0
586 xor<VAXint:isfx>3 %2,%1,%0")
589 (define_insn "neg<mode>2"
590 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g")
591 (neg:VAXfp (match_operand:VAXfp 1 "general_operand" "gF")))]
593 "mneg<VAXfp:fsfx> %1,%0")
595 (define_insn "neg<mode>2"
596 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
597 (neg:VAXint (match_operand:VAXint 1 "general_operand" "g")))]
599 "mneg<VAXint:isfx> %1,%0")
601 (define_insn "one_cmpl<mode>2"
602 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
603 (not:VAXint (match_operand:VAXint 1 "general_operand" "g")))]
605 "mcom<VAXint:isfx> %1,%0")
608 ;; Arithmetic right shift on the VAX works by negating the shift count,
609 ;; then emitting a right shift with the shift count negated. This means
610 ;; that all actual shift counts in the RTL will be positive. This
611 ;; prevents converting shifts to ZERO_EXTRACTs with negative positions,
612 ;; which isn't valid.
613 (define_expand "ashrsi3"
614 [(set (match_operand:SI 0 "general_operand" "=g")
615 (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
616 (match_operand:QI 2 "general_operand" "g")))]
620 if (GET_CODE (operands[2]) != CONST_INT)
621 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
625 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
626 (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
627 (match_operand:QI 2 "const_int_operand" "n")))]
632 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
633 (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
634 (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
638 (define_insn "ashlsi3"
639 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
640 (ashift:SI (match_operand:SI 1 "general_operand" "g")
641 (match_operand:QI 2 "general_operand" "g")))]
645 if (operands[2] == const1_rtx && rtx_equal_p (operands[0], operands[1]))
646 return \"addl2 %0,%0\";
647 if (GET_CODE (operands[1]) == REG
648 && GET_CODE (operands[2]) == CONST_INT)
650 int i = INTVAL (operands[2]);
652 return \"addl3 %1,%1,%0\";
654 return \"moval 0[%1],%0\";
656 return \"movad 0[%1],%0\";
658 return \"ashl %2,%1,%0\";
661 ;; Arithmetic right shift on the VAX works by negating the shift count.
662 (define_expand "ashrdi3"
663 [(set (match_operand:DI 0 "general_operand" "=g")
664 (ashiftrt:DI (match_operand:DI 1 "general_operand" "g")
665 (match_operand:QI 2 "general_operand" "g")))]
669 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
672 (define_insn "ashldi3"
673 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
674 (ashift:DI (match_operand:DI 1 "general_operand" "g")
675 (match_operand:QI 2 "general_operand" "g")))]
680 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
681 (ashiftrt:DI (match_operand:DI 1 "general_operand" "g")
682 (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
686 ;; We used to have expand_shift handle logical right shifts by using extzv,
687 ;; but this make it very difficult to do lshrdi3. Since the VAX is the
688 ;; only machine with this kludge, it's better to just do this with a
689 ;; define_expand and remove that case from expand_shift.
691 (define_expand "lshrsi3"
693 (minus:QI (const_int 32)
695 (set (match_operand:SI 0 "general_operand" "=g")
696 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
698 (match_operand:SI 2 "register_operand" "g")))]
702 operands[3] = gen_reg_rtx (QImode);
703 operands[4] = gen_lowpart (QImode, operands[2]);
706 ;; Rotate right on the VAX works by negating the shift count.
707 (define_expand "rotrsi3"
708 [(set (match_operand:SI 0 "general_operand" "=g")
709 (rotatert:SI (match_operand:SI 1 "general_operand" "g")
710 (match_operand:QI 2 "general_operand" "g")))]
714 if (GET_CODE (operands[2]) != CONST_INT)
715 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
718 (define_insn "rotlsi3"
719 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
720 (rotate:SI (match_operand:SI 1 "general_operand" "g")
721 (match_operand:QI 2 "general_operand" "g")))]
726 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
727 (rotatert:SI (match_operand:SI 1 "general_operand" "g")
728 (match_operand:QI 2 "const_int_operand" "n")))]
733 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
734 (rotatert:SI (match_operand:SI 1 "general_operand" "g")
735 (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
739 ;This insn is probably slower than a multiply and an add.
741 ; [(set (match_operand:SI 0 "general_operand" "=g")
742 ; (mult:SI (plus:SI (match_operand:SI 1 "general_operand" "g")
743 ; (match_operand:SI 2 "general_operand" "g"))
744 ; (match_operand:SI 3 "general_operand" "g")))]
746 ; "index %1,$0x80000000,$0x7fffffff,%3,%2,%0")
748 ;; Special cases of bit-field insns which we should
749 ;; recognize in preference to the general case.
750 ;; These handle aligned 8-bit and 16-bit fields,
751 ;; which can usually be done with move instructions.
754 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+ro")
755 (match_operand:QI 1 "const_int_operand" "n")
756 (match_operand:SI 2 "const_int_operand" "n"))
757 (match_operand:SI 3 "general_operand" "g"))]
758 "(INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
759 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
760 && (GET_CODE (operands[0]) == REG
761 || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
764 if (REG_P (operands[0]))
766 if (INTVAL (operands[2]) != 0)
767 return \"insv %3,%2,%1,%0\";
771 = adjust_address (operands[0],
772 INTVAL (operands[1]) == 8 ? QImode : HImode,
773 INTVAL (operands[2]) / 8);
776 if (INTVAL (operands[1]) == 8)
777 return \"movb %3,%0\";
778 return \"movw %3,%0\";
782 [(set (match_operand:SI 0 "nonimmediate_operand" "=&g")
783 (zero_extract:SI (match_operand:SI 1 "register_operand" "ro")
784 (match_operand:QI 2 "const_int_operand" "n")
785 (match_operand:SI 3 "const_int_operand" "n")))]
786 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
787 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
788 && (GET_CODE (operands[1]) == REG
789 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
792 if (REG_P (operands[1]))
794 if (INTVAL (operands[3]) != 0)
795 return \"extzv %3,%2,%1,%0\";
799 = adjust_address (operands[1],
800 INTVAL (operands[2]) == 8 ? QImode : HImode,
801 INTVAL (operands[3]) / 8);
803 if (INTVAL (operands[2]) == 8)
804 return \"movzbl %1,%0\";
805 return \"movzwl %1,%0\";
809 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
810 (sign_extract:SI (match_operand:SI 1 "register_operand" "ro")
811 (match_operand:QI 2 "const_int_operand" "n")
812 (match_operand:SI 3 "const_int_operand" "n")))]
813 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
814 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
815 && (GET_CODE (operands[1]) == REG
816 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
819 if (REG_P (operands[1]))
821 if (INTVAL (operands[3]) != 0)
822 return \"extv %3,%2,%1,%0\";
826 = adjust_address (operands[1],
827 INTVAL (operands[2]) == 8 ? QImode : HImode,
828 INTVAL (operands[3]) / 8);
830 if (INTVAL (operands[2]) == 8)
831 return \"cvtbl %1,%0\";
832 return \"cvtwl %1,%0\";
835 ;; Register-only SImode cases of bit-field insns.
840 (sign_extract:SI (match_operand:SI 0 "register_operand" "r")
841 (match_operand:QI 1 "general_operand" "g")
842 (match_operand:SI 2 "general_operand" "g"))
843 (match_operand:SI 3 "general_operand" "g")))]
850 (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
851 (match_operand:QI 1 "general_operand" "g")
852 (match_operand:SI 2 "general_operand" "g"))
853 (match_operand:SI 3 "general_operand" "g")))]
857 ;; When the field position and size are constant and the destination
858 ;; is a register, extv and extzv are much slower than a rotate followed
859 ;; by a bicl or sign extension. Because we might end up choosing ext[z]v
860 ;; anyway, we can't allow immediate values for the primary source operand.
863 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
864 (sign_extract:SI (match_operand:SI 1 "register_operand" "ro")
865 (match_operand:QI 2 "general_operand" "g")
866 (match_operand:SI 3 "general_operand" "g")))]
870 if (GET_CODE (operands[3]) != CONST_INT || GET_CODE (operands[2]) != CONST_INT
871 || GET_CODE (operands[0]) != REG
872 || (INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16))
873 return \"extv %3,%2,%1,%0\";
874 if (INTVAL (operands[2]) == 8)
875 return \"rotl %R3,%1,%0\;cvtbl %0,%0\";
876 return \"rotl %R3,%1,%0\;cvtwl %0,%0\";
880 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
881 (zero_extract:SI (match_operand:SI 1 "register_operand" "ro")
882 (match_operand:QI 2 "general_operand" "g")
883 (match_operand:SI 3 "general_operand" "g")))]
887 if (GET_CODE (operands[3]) != CONST_INT || GET_CODE (operands[2]) != CONST_INT
888 || GET_CODE (operands[0]) != REG)
889 return \"extzv %3,%2,%1,%0\";
890 if (INTVAL (operands[2]) == 8)
891 return \"rotl %R3,%1,%0\;movzbl %0,%0\";
892 if (INTVAL (operands[2]) == 16)
893 return \"rotl %R3,%1,%0\;movzwl %0,%0\";
894 if (INTVAL (operands[3]) & 31)
895 return \"rotl %R3,%1,%0\;bicl2 %M2,%0\";
896 if (rtx_equal_p (operands[0], operands[1]))
897 return \"bicl2 %M2,%0\";
898 return \"bicl3 %M2,%1,%0\";
901 ;; Non-register cases.
902 ;; nonimmediate_operand is used to make sure that mode-ambiguous cases
903 ;; don't match these (and therefore match the cases above instead).
908 (sign_extract:SI (match_operand:QI 0 "memory_operand" "m")
909 (match_operand:QI 1 "general_operand" "g")
910 (match_operand:SI 2 "general_operand" "g"))
911 (match_operand:SI 3 "general_operand" "g")))]
918 (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rm")
919 (match_operand:QI 1 "general_operand" "g")
920 (match_operand:SI 2 "general_operand" "g"))
921 (match_operand:SI 3 "general_operand" "g")))]
926 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
927 (sign_extract:SI (match_operand:QI 1 "memory_operand" "m")
928 (match_operand:QI 2 "general_operand" "g")
929 (match_operand:SI 3 "general_operand" "g")))]
933 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[2]) != CONST_INT
934 || GET_CODE (operands[3]) != CONST_INT
935 || (INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16)
936 || INTVAL (operands[2]) + INTVAL (operands[3]) > 32
937 || side_effects_p (operands[1])
938 || (GET_CODE (operands[1]) == MEM
939 && mode_dependent_address_p (XEXP (operands[1], 0))))
940 return \"extv %3,%2,%1,%0\";
941 if (INTVAL (operands[2]) == 8)
942 return \"rotl %R3,%1,%0\;cvtbl %0,%0\";
943 return \"rotl %R3,%1,%0\;cvtwl %0,%0\";
946 (define_expand "extzv"
947 [(set (match_operand:SI 0 "general_operand" "")
948 (zero_extract:SI (match_operand:SI 1 "general_operand" "")
949 (match_operand:QI 2 "general_operand" "")
950 (match_operand:SI 3 "general_operand" "")))]
955 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
956 (zero_extract:SI (match_operand:QI 1 "memory_operand" "m")
957 (match_operand:QI 2 "general_operand" "g")
958 (match_operand:SI 3 "general_operand" "g")))]
962 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[2]) != CONST_INT
963 || GET_CODE (operands[3]) != CONST_INT
964 || INTVAL (operands[2]) + INTVAL (operands[3]) > 32
965 || side_effects_p (operands[1])
966 || (GET_CODE (operands[1]) == MEM
967 && mode_dependent_address_p (XEXP (operands[1], 0))))
968 return \"extzv %3,%2,%1,%0\";
969 if (INTVAL (operands[2]) == 8)
970 return \"rotl %R3,%1,%0\;movzbl %0,%0\";
971 if (INTVAL (operands[2]) == 16)
972 return \"rotl %R3,%1,%0\;movzwl %0,%0\";
973 return \"rotl %R3,%1,%0\;bicl2 %M2,%0\";
976 (define_expand "insv"
977 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
978 (match_operand:QI 1 "general_operand" "")
979 (match_operand:SI 2 "general_operand" ""))
980 (match_operand:SI 3 "general_operand" ""))]
985 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+g")
986 (match_operand:QI 1 "general_operand" "g")
987 (match_operand:SI 2 "general_operand" "g"))
988 (match_operand:SI 3 "general_operand" "g"))]
993 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
994 (match_operand:QI 1 "general_operand" "g")
995 (match_operand:SI 2 "general_operand" "g"))
996 (match_operand:SI 3 "general_operand" "g"))]
1000 ;; Unconditional jump
1003 (label_ref (match_operand 0 "" "")))]
1007 ;; Conditional jumps
1008 (define_code_macro any_cond [eq ne gt lt gtu ltu ge le geu leu])
1010 (define_insn "b<code>"
1012 (if_then_else (any_cond (cc0)
1014 (label_ref (match_operand 0 "" ""))
1017 "* return vax_output_conditional_branch (<CODE>);")
1019 ;; Recognize reversed jumps.
1022 (if_then_else (match_operator 0 "comparison_operator"
1026 (label_ref (match_operand 1 "" ""))))]
1028 "j%C0 %l1") ; %C0 negates condition
1030 ;; Recognize jbs, jlbs, jbc and jlbc instructions. Note that the operand
1031 ;; of jlbs and jlbc insns are SImode in the hardware. However, if it is
1032 ;; memory, we use QImode in the insn. So we can't use those instructions
1033 ;; for mode-dependent addresses.
1038 (ne (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g")
1040 (match_operand:SI 1 "general_operand" "I,g"))
1042 (label_ref (match_operand 2 "" ""))
1052 (eq (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g")
1054 (match_operand:SI 1 "general_operand" "I,g"))
1056 (label_ref (match_operand 2 "" ""))
1066 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r")
1068 (match_operand:SI 1 "general_operand" "I,g"))
1070 (label_ref (match_operand 2 "" ""))
1080 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r")
1082 (match_operand:SI 1 "general_operand" "I,g"))
1084 (label_ref (match_operand 2 "" ""))
1091 ;; Subtract-and-jump and Add-and-jump insns.
1092 ;; These are not used when output is for the Unix assembler
1093 ;; because it does not know how to modify them to reach far.
1095 ;; Normal sob insns.
1100 (gt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
1103 (label_ref (match_operand 1 "" ""))
1106 (plus:SI (match_dup 0)
1114 (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
1117 (label_ref (match_operand 1 "" ""))
1120 (plus:SI (match_dup 0)
1125 ;; Normal aob insns. Define a version for when operands[1] is a constant.
1129 (lt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
1131 (match_operand:SI 1 "general_operand" "g"))
1132 (label_ref (match_operand 2 "" ""))
1135 (plus:SI (match_dup 0)
1138 "jaoblss %1,%0,%l2")
1143 (lt (match_operand:SI 0 "nonimmediate_operand" "+g")
1144 (match_operand:SI 1 "general_operand" "g"))
1145 (label_ref (match_operand 2 "" ""))
1148 (plus:SI (match_dup 0)
1150 "!TARGET_UNIX_ASM && GET_CODE (operands[1]) == CONST_INT"
1151 "jaoblss %P1,%0,%l2")
1156 (le (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
1158 (match_operand:SI 1 "general_operand" "g"))
1159 (label_ref (match_operand 2 "" ""))
1162 (plus:SI (match_dup 0)
1165 "jaobleq %1,%0,%l2")
1170 (le (match_operand:SI 0 "nonimmediate_operand" "+g")
1171 (match_operand:SI 1 "general_operand" "g"))
1172 (label_ref (match_operand 2 "" ""))
1175 (plus:SI (match_dup 0)
1177 "!TARGET_UNIX_ASM && GET_CODE (operands[1]) == CONST_INT"
1178 "jaobleq %P1,%0,%l2")
1180 ;; Something like a sob insn, but compares against -1.
1181 ;; This finds `while (foo--)' which was changed to `while (--foo != -1)'.
1186 (ne (match_operand:SI 0 "nonimmediate_operand" "+g")
1188 (label_ref (match_operand 1 "" ""))
1191 (plus:SI (match_dup 0)
1194 "decl %0\;jgequ %l1")
1196 (define_expand "call_pop"
1197 [(parallel [(call (match_operand:QI 0 "memory_operand" "")
1198 (match_operand:SI 1 "const_int_operand" ""))
1200 (plus:SI (reg:SI 14)
1201 (match_operand:SI 3 "immediate_operand" "")))])]
1204 if (INTVAL (operands[3]) > 255 * 4 || INTVAL (operands[3]) % 4)
1207 /* Operand 1 is the number of bytes to be popped by DW_CFA_GNU_args_size
1208 during EH unwinding. We must include the argument count pushed by
1209 the calls instruction. */
1210 operands[1] = GEN_INT (INTVAL (operands[3]) + 4);
1213 (define_insn "*call_pop"
1214 [(call (match_operand:QI 0 "memory_operand" "m")
1215 (match_operand:SI 1 "const_int_operand" "n"))
1216 (set (reg:SI 14) (plus:SI (reg:SI 14)
1217 (match_operand:SI 2 "immediate_operand" "i")))]
1220 operands[1] = GEN_INT ((INTVAL (operands[1]) - 4) / 4);
1221 return "calls %1,%0";
1224 (define_expand "call_value_pop"
1225 [(parallel [(set (match_operand 0 "" "")
1226 (call (match_operand:QI 1 "memory_operand" "")
1227 (match_operand:SI 2 "const_int_operand" "")))
1229 (plus:SI (reg:SI 14)
1230 (match_operand:SI 4 "immediate_operand" "")))])]
1233 if (INTVAL (operands[4]) > 255 * 4 || INTVAL (operands[4]) % 4)
1236 /* Operand 2 is the number of bytes to be popped by DW_CFA_GNU_args_size
1237 during EH unwinding. We must include the argument count pushed by
1238 the calls instruction. */
1239 operands[2] = GEN_INT (INTVAL (operands[4]) + 4);
1242 (define_insn "*call_value_pop"
1243 [(set (match_operand 0 "" "")
1244 (call (match_operand:QI 1 "memory_operand" "m")
1245 (match_operand:SI 2 "const_int_operand" "n")))
1246 (set (reg:SI 14) (plus:SI (reg:SI 14)
1247 (match_operand:SI 3 "immediate_operand" "i")))]
1251 operands[2] = GEN_INT ((INTVAL (operands[2]) - 4) / 4);
1252 return \"calls %2,%1\";
1255 (define_expand "call"
1256 [(call (match_operand:QI 0 "memory_operand" "")
1257 (match_operand:SI 1 "const_int_operand" ""))]
1261 /* Operand 1 is the number of bytes to be popped by DW_CFA_GNU_args_size
1262 during EH unwinding. We must include the argument count pushed by
1263 the calls instruction. */
1264 operands[1] = GEN_INT (INTVAL (operands[1]) + 4);
1267 (define_insn "*call"
1268 [(call (match_operand:QI 0 "memory_operand" "m")
1269 (match_operand:SI 1 "const_int_operand" ""))]
1273 (define_expand "call_value"
1274 [(set (match_operand 0 "" "")
1275 (call (match_operand:QI 1 "memory_operand" "")
1276 (match_operand:SI 2 "const_int_operand" "")))]
1280 /* Operand 2 is the number of bytes to be popped by DW_CFA_GNU_args_size
1281 during EH unwinding. We must include the argument count pushed by
1282 the calls instruction. */
1283 operands[2] = GEN_INT (INTVAL (operands[2]) + 4);
1286 (define_insn "*call_value"
1287 [(set (match_operand 0 "" "")
1288 (call (match_operand:QI 1 "memory_operand" "m")
1289 (match_operand:SI 2 "const_int_operand" "")))]
1293 ;; Call subroutine returning any type.
1295 (define_expand "untyped_call"
1296 [(parallel [(call (match_operand 0 "" "")
1298 (match_operand 1 "" "")
1299 (match_operand 2 "" "")])]
1305 emit_call_insn (gen_call_pop (operands[0], const0_rtx, NULL, const0_rtx));
1307 for (i = 0; i < XVECLEN (operands[2], 0); i++)
1309 rtx set = XVECEXP (operands[2], 0, i);
1310 emit_move_insn (SET_DEST (set), SET_SRC (set));
1313 /* The optimizer does not know that the call sets the function value
1314 registers we stored in the result block. We avoid problems by
1315 claiming that all hard registers are used and clobbered at this
1317 emit_insn (gen_blockage ());
1322 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
1323 ;; all of memory. This blocks insns from being moved across this point.
1325 (define_insn "blockage"
1326 [(unspec_volatile [(const_int 0)] VUNSPEC_BLOCKAGE)]
1330 (define_insn "return"
1335 (define_expand "epilogue"
1340 emit_jump_insn (gen_return ());
1349 ;; This had a wider constraint once, and it had trouble.
1350 ;; If you are tempted to try `g', please don't--it's not worth
1351 ;; the risk we will reopen the same bug.
1352 (define_insn "indirect_jump"
1353 [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
1357 ;; This is here to accept 5 arguments (as passed by expand_end_case)
1358 ;; and pass the first 4 along to the casesi1 pattern that really does
1359 ;; the actual casesi work. We emit a jump here to the default label
1360 ;; _before_ the casesi so that we can be sure that the casesi never
1362 ;; This is suboptimal perhaps, but so is much of the rest of this
1363 ;; machine description. For what it's worth, HPPA uses the same trick.
1365 ;; operand 0 is index
1366 ;; operand 1 is the minimum bound (a const_int)
1367 ;; operand 2 is the maximum bound - minimum bound + 1 (also a const_int)
1368 ;; operand 3 is CODE_LABEL for the table;
1369 ;; operand 4 is the CODE_LABEL to go to if index out of range (ie. default).
1372 ;; i = index - minimum_bound
1373 ;; if (i > (maximum_bound - minimum_bound + 1) goto default;
1374 ;; casesi (i, 0, table);
1376 (define_expand "casesi"
1377 [(match_operand:SI 0 "general_operand" "")
1378 (match_operand:SI 1 "general_operand" "")
1379 (match_operand:SI 2 "general_operand" "")
1380 (match_operand 3 "" "")
1381 (match_operand 4 "" "")]
1384 /* i = index - minimum_bound;
1385 But only if the lower bound is not already zero. */
1386 if (operands[1] != const0_rtx)
1388 rtx index = gen_reg_rtx (SImode);
1389 emit_insn (gen_addsi3 (index,
1391 GEN_INT (-INTVAL (operands[1]))));
1392 operands[0] = index;
1395 /* if (i > (maximum_bound - minimum_bound + 1) goto default; */
1396 emit_insn (gen_cmpsi (operands[0], operands[2]));
1397 emit_jump_insn (gen_bgtu (operands[4]));
1399 /* casesi (i, 0, table); */
1400 emit_jump_insn (gen_casesi1 (operands[0], operands[2], operands[3]));
1404 ;; This insn is a bit of a lier. It actually falls through if no case
1405 ;; matches. But, we prevent that from ever happening by emitting a jump
1406 ;; before this, see the define_expand above.
1407 (define_insn "casesi1"
1408 [(match_operand:SI 1 "const_int_operand" "n")
1410 (plus:SI (sign_extend:SI
1411 (mem:HI (plus:SI (mult:SI (match_operand:SI 0 "general_operand" "g")
1414 (label_ref:SI (match_operand 2 "" ""))))]
1418 ;;- load or push effective address
1419 ;; These come after the move and add/sub patterns
1420 ;; because we don't want pushl $1 turned into pushad 1.
1421 ;; or addl3 r1,r2,r3 turned into movab 0(r1)[r2],r3.
1423 ;; It does not work to use constraints to distinguish pushes from moves,
1424 ;; because < matches any autodecrement, not just a push.
1427 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1428 (match_operand:QI 1 "address_operand" "p"))]
1432 if (push_operand (operands[0], SImode))
1433 return \"pushab %a1\";
1435 return \"movab %a1,%0\";
1439 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1440 (match_operand:HI 1 "address_operand" "p"))]
1444 if (push_operand (operands[0], SImode))
1445 return \"pushaw %a1\";
1447 return \"movaw %a1,%0\";
1451 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1452 (match_operand:SI 1 "address_operand" "p"))]
1456 if (push_operand (operands[0], SImode))
1457 return \"pushal %a1\";
1459 return \"moval %a1,%0\";
1463 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1464 (match_operand:DI 1 "address_operand" "p"))]
1468 if (push_operand (operands[0], SImode))
1469 return \"pushaq %a1\";
1471 return \"movaq %a1,%0\";
1475 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1476 (match_operand:SF 1 "address_operand" "p"))]
1480 if (push_operand (operands[0], SImode))
1481 return \"pushaf %a1\";
1483 return \"movaf %a1,%0\";
1487 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1488 (match_operand:DF 1 "address_operand" "p"))]
1492 if (push_operand (operands[0], SImode))
1493 return \"pushad %a1\";
1495 return \"movad %a1,%0\";
1498 ;; These used to be peepholes, but it is more straightforward to do them
1499 ;; as single insns. However, we must force the output to be a register
1500 ;; if it is not an offsettable address so that we know that we can assign
1503 ;; If we had a good way of evaluating the relative costs, these could be
1504 ;; machine-independent.
1506 ;; Optimize extzv ...,z; andl2 ...,z
1507 ;; or ashl ...,z; andl2 ...,z
1508 ;; with other operands constant. This is what the combiner converts the
1509 ;; above sequences to before attempting to recognize the new insn.
1512 [(set (match_operand:SI 0 "nonimmediate_operand" "=ro")
1513 (and:SI (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
1514 (match_operand:QI 2 "const_int_operand" "n"))
1515 (match_operand:SI 3 "const_int_operand" "n")))]
1516 "(INTVAL (operands[3]) & ~((1 << (32 - INTVAL (operands[2]))) - 1)) == 0"
1519 unsigned long mask1 = INTVAL (operands[3]);
1520 unsigned long mask2 = (1 << (32 - INTVAL (operands[2]))) - 1;
1522 if ((mask1 & mask2) != mask1)
1523 operands[3] = GEN_INT (mask1 & mask2);
1525 return \"rotl %R2,%1,%0\;bicl2 %N3,%0\";
1528 ;; left-shift and mask
1529 ;; The only case where `ashl' is better is if the mask only turns off
1530 ;; bits that the ashl would anyways, in which case it should have been
1534 [(set (match_operand:SI 0 "nonimmediate_operand" "=ro")
1535 (and:SI (ashift:SI (match_operand:SI 1 "general_operand" "g")
1536 (match_operand:QI 2 "const_int_operand" "n"))
1537 (match_operand:SI 3 "const_int_operand" "n")))]
1542 = GEN_INT (INTVAL (operands[3]) & ~((1 << INTVAL (operands[2])) - 1));
1543 return \"rotl %2,%1,%0\;bicl2 %N3,%0\";
1546 ;; Instruction sequence to sync the VAX instruction stream.
1547 (define_insn "sync_istream"
1548 [(unspec_volatile [(const_int 0)] VUNSPEC_SYNC_ISTREAM)]
1550 "movpsl -(%|sp)\;pushal 1(%|pc)\;rei")