1 /* Xstormy16 cpu description.
2 Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2007,
3 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
4 Contributed by Red Hat, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
23 /* Driver configuration. */
29 #define LINK_SPEC "%{h*} %{v:-V} \
30 %{static:-Bstatic} %{shared:-shared} %{symbolic:-Bsymbolic}"
33 - If -msim is specified, everything is built and linked as for the sim.
34 - If -T is specified, that linker script is used, and it should provide
35 appropriate libraries.
36 - If neither is specified, everything is built as for the sim, but no
37 I/O support is assumed. */
39 #define LIB_SPEC "-( -lc %{msim:-lsim}%{!msim:%{!T*:-lnosys}} -)"
42 #define STARTFILE_SPEC "crt0.o%s crti.o%s crtbegin.o%s"
45 #define ENDFILE_SPEC "crtend.o%s crtn.o%s"
48 /* Run-time target specifications. */
50 #define TARGET_CPU_CPP_BUILTINS() \
53 builtin_define_std ("xstormy16"); \
54 builtin_assert ("machine=xstormy16"); \
55 builtin_assert ("cpu=xstormy16"); \
61 #define BITS_BIG_ENDIAN 1
63 #define BYTES_BIG_ENDIAN 0
65 #define WORDS_BIG_ENDIAN 0
67 #define UNITS_PER_WORD 2
69 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
72 if (GET_MODE_CLASS (MODE) == MODE_INT \
73 && GET_MODE_SIZE (MODE) < 2) \
78 #define PARM_BOUNDARY 16
80 #define STACK_BOUNDARY 16
82 #define FUNCTION_BOUNDARY 16
84 #define BIGGEST_ALIGNMENT 16
86 #define DATA_ALIGNMENT(TYPE, ALIGN) \
87 (TREE_CODE (TYPE) == ARRAY_TYPE \
88 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
89 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
91 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
92 (TREE_CODE (EXP) == STRING_CST \
93 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
95 #define STRICT_ALIGNMENT 1
97 #define PCC_BITFIELD_TYPE_MATTERS 1
99 /* Layout of Source Language Data Types. */
101 #define INT_TYPE_SIZE 16
103 #define SHORT_TYPE_SIZE 16
105 #define LONG_TYPE_SIZE 32
107 #define LONG_LONG_TYPE_SIZE 64
109 #define FLOAT_TYPE_SIZE 32
111 #define DOUBLE_TYPE_SIZE 64
113 #define LONG_DOUBLE_TYPE_SIZE 64
115 #define DEFAULT_SIGNED_CHAR 0
117 #define SIZE_TYPE "unsigned int"
119 #define PTRDIFF_TYPE "int"
122 #define WCHAR_TYPE "long int"
124 #undef WCHAR_TYPE_SIZE
125 #define WCHAR_TYPE_SIZE 32
128 /* Register Basics. */
130 #define FIRST_PSEUDO_REGISTER 19
132 #define FIXED_REGISTERS \
133 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1 }
135 #define CALL_USED_REGISTERS \
136 { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1 }
139 /* Order of allocation of registers. */
141 #define REG_ALLOC_ORDER { 7, 6, 5, 4, 3, 2, 1, 0, 9, 8, 10, 11, 12, 13, 14, 15, 16 }
144 /* How Values Fit in Registers. */
146 #define HARD_REGNO_NREGS(REGNO, MODE) \
147 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
149 #define HARD_REGNO_MODE_OK(REGNO, MODE) ((REGNO) != 16 || (MODE) == BImode)
151 /* A C expression that is nonzero if it is desirable to choose register
152 allocation so as to avoid move instructions between a value of mode MODE1
153 and a value of mode MODE2.
155 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are
156 ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be
158 #define MODES_TIEABLE_P(MODE1, MODE2) ((MODE1) != BImode && (MODE2) != BImode)
161 /* Register Classes. */
178 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
180 #define REG_CLASS_NAMES \
194 #define REG_CLASS_CONTENTS \
205 { (1 << FIRST_PSEUDO_REGISTER) - 1 } \
208 #define REGNO_REG_CLASS(REGNO) \
209 ( (REGNO) == 0 ? R0_REGS \
210 : (REGNO) == 1 ? R1_REGS \
211 : (REGNO) == 2 ? R2_REGS \
212 : (REGNO) < 8 ? EIGHT_REGS \
213 : (REGNO) == 8 ? R8_REGS \
214 : (REGNO) <= 18 ? GENERAL_REGS \
217 #define BASE_REG_CLASS GENERAL_REGS
219 #define INDEX_REG_CLASS GENERAL_REGS
221 #define REGNO_OK_FOR_BASE_P(NUM) 1
223 #define REGNO_OK_FOR_INDEX_P(NUM) REGNO_OK_FOR_BASE_P (NUM)
225 /* This chip has the interesting property that only the first eight
226 registers can be moved to/from memory. */
227 #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \
228 xstormy16_secondary_reload_class (CLASS, MODE, X)
230 #define CLASS_MAX_NREGS(CLASS, MODE) \
231 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
234 /* Basic Stack Layout. */
236 /* We want to use post-increment instructions to push things on the stack,
237 because we don't have any pre-increment ones. */
238 #define STACK_PUSH_CODE POST_INC
240 #define FRAME_GROWS_DOWNWARD 0
242 #define ARGS_GROW_DOWNWARD 1
244 #define STARTING_FRAME_OFFSET 0
246 #define FIRST_PARM_OFFSET(FUNDECL) 0
248 #define RETURN_ADDR_RTX(COUNT, FRAMEADDR) \
250 ? gen_rtx_MEM (Pmode, arg_pointer_rtx) \
253 #define INCOMING_RETURN_ADDR_RTX \
254 gen_rtx_MEM (SImode, gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-4)))
256 #define INCOMING_FRAME_SP_OFFSET (xstormy16_interrupt_function_p () ? -6 : -4)
259 /* Register That Address the Stack Frame. */
261 #define STATIC_CHAIN_REGNUM 1
262 #define HARD_FRAME_POINTER_REGNUM 13
263 #define STACK_POINTER_REGNUM 15
264 #define CARRY_REGNUM 16
265 #define FRAME_POINTER_REGNUM 17
266 #define ARG_POINTER_REGNUM 18
269 /* Eliminating the Frame Pointer and the Arg Pointer. */
271 #define ELIMINABLE_REGS \
273 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
274 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
275 {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
276 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
279 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
280 (OFFSET) = xstormy16_initial_elimination_offset (FROM, TO)
283 /* Passing Function Arguments on the Stack. */
285 #define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & ~1)
288 /* Function Arguments in Registers. */
290 #define NUM_ARGUMENT_REGISTERS 6
291 #define FIRST_ARGUMENT_REGISTER 2
293 #define XSTORMY16_WORD_SIZE(TYPE, MODE) \
294 ((((TYPE) ? int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) \
298 /* For this platform, the value of CUMULATIVE_ARGS is the number of words
299 of arguments that have been passed in registers so far. */
300 #define CUMULATIVE_ARGS int
302 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
305 #define FUNCTION_ARG_REGNO_P(REGNO) \
306 ((REGNO) >= FIRST_ARGUMENT_REGISTER \
307 && (REGNO) < FIRST_ARGUMENT_REGISTER + NUM_ARGUMENT_REGISTERS)
310 /* How Scalar Function Values are Returned. */
312 /* The number of the hard register that is used to return a scalar value from a
314 #define RETURN_VALUE_REGNUM FIRST_ARGUMENT_REGISTER
317 /* Function Entry and Exit. */
319 #define EPILOGUE_USES(REGNO) \
320 xstormy16_epilogue_uses (REGNO)
323 /* Generating Code for Profiling. */
325 /* This declaration must be present, but it can be an abort if profiling is
328 #define FUNCTION_PROFILER(FILE, LABELNO) xstormy16_function_profiler ()
331 /* Trampolines for Nested Functions. */
333 #define TRAMPOLINE_SIZE 8
334 #define TRAMPOLINE_ALIGNMENT 16
337 /* Addressing Modes. */
339 #define HAVE_POST_INCREMENT 1
341 #define HAVE_PRE_DECREMENT 1
343 #define MAX_REGS_PER_ADDRESS 1
346 /* Describing Relative Costs of Operations. */
348 #define BRANCH_COST(speed_p, predictable_p) 5
350 #define SLOW_BYTE_ACCESS 0
352 #define NO_FUNCTION_CSE
355 /* Dividing the output into sections. */
357 #define TEXT_SECTION_ASM_OP ".text"
359 #define DATA_SECTION_ASM_OP ".data"
361 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
363 /* Define the pseudo-ops used to switch to the .ctors and .dtors sections.
364 There are no shared libraries on this target so these sections need
367 Defined in elfos.h. */
369 #undef CTORS_SECTION_ASM_OP
370 #undef DTORS_SECTION_ASM_OP
371 #define CTORS_SECTION_ASM_OP "\t.section\t.ctors,\"a\""
372 #define DTORS_SECTION_ASM_OP "\t.section\t.dtors,\"a\""
374 #define TARGET_ASM_INIT_SECTIONS xstormy16_asm_init_sections
376 #define JUMP_TABLES_IN_TEXT_SECTION 1
378 /* The Overall Framework of an Assembler File. */
380 #define ASM_COMMENT_START ";"
382 #define ASM_APP_ON "#APP\n"
384 #define ASM_APP_OFF "#NO_APP\n"
386 /* Output of Data. */
388 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == '|')
390 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
391 xstormy16_asm_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 1)
392 #define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
393 xstormy16_asm_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 0)
396 /* Output and Generation of Labels. */
397 #define SYMBOL_FLAG_XSTORMY16_BELOW100 (SYMBOL_FLAG_MACH_DEP << 0)
399 #define ASM_OUTPUT_SYMBOL_REF(STREAM, SYMBOL) \
402 const char *rn = XSTR (SYMBOL, 0); \
404 if (SYMBOL_REF_FUNCTION_P (SYMBOL)) \
405 ASM_OUTPUT_LABEL_REF ((STREAM), rn); \
407 assemble_name (STREAM, rn); \
411 #define ASM_OUTPUT_LABEL_REF(STREAM, NAME) \
414 fputs ("@fptr(", STREAM); \
415 assemble_name (STREAM, NAME); \
416 fputc (')', STREAM); \
420 /* Globalizing directive for a label. */
421 #define GLOBAL_ASM_OP "\t.globl "
424 /* Output of Assembler Instructions. */
426 #define REGISTER_NAMES \
427 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", \
428 "r11", "r12", "r13", "psw", "sp", "carry", "fp", "ap" }
430 #define ADDITIONAL_REGISTER_NAMES \
434 #define REGISTER_PREFIX ""
435 #define LOCAL_LABEL_PREFIX "."
436 #define USER_LABEL_PREFIX ""
437 #define IMMEDIATE_PREFIX "#"
439 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
440 fprintf (STREAM, "\tpush %d\n", REGNO)
442 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
443 fprintf (STREAM, "\tpop %d\n", REGNO)
446 /* Output of dispatch tables. */
448 /* This port does not use the ASM_OUTPUT_ADDR_VEC_ELT macro, because
449 this could cause label alignment to appear between the 'br' and the table,
450 which would be bad. Instead, it controls the output of the table
452 #define ASM_OUTPUT_ADDR_VEC(LABEL, BODY) \
453 xstormy16_output_addr_vec (file, LABEL, BODY)
455 /* Alignment for ADDR_VECs is the same as for code. */
456 #define ADDR_VEC_ALIGN(ADDR_VEC) 1
459 /* Assembler Commands for Exception Regions. */
461 #define DWARF2_UNWIND_INFO 0
462 #define DWARF_CIE_DATA_ALIGNMENT 1
464 #undef DONT_USE_BUILTIN_SETJMP
465 #define JMP_BUF_SIZE 8
467 /* Assembler Commands for Alignment. */
469 #define ASM_OUTPUT_ALIGN(STREAM, POWER) \
470 fprintf ((STREAM), "\t.p2align %d\n", (POWER))
473 /* Macros Affecting all Debug Formats. */
475 #undef PREFERRED_DEBUGGING_TYPE
476 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
479 /* Macros for SDB and Dwarf Output. */
481 /* Define this macro if addresses in Dwarf 2 debugging info should not
482 be the same size as pointers on the target architecture. The
483 macro's value should be the size, in bytes, to use for addresses in
486 Some architectures use word addresses to refer to code locations,
487 but Dwarf 2 info always uses byte addresses. On such machines,
488 Dwarf 2 addresses need to be larger than the architecture's
490 #define DWARF2_ADDR_SIZE 4
493 /* Miscellaneous Parameters. */
495 #define CASE_VECTOR_MODE SImode
497 #define WORD_REGISTER_OPERATIONS
499 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
503 #define SHIFT_COUNT_TRUNCATED 1
505 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
509 #define FUNCTION_MODE HImode
511 #define NO_IMPLICIT_EXTERN_C