1 ;; Copyright (C) 2006 Free Software Foundation, Inc.
3 ;; This file is free software; you can redistribute it and/or modify it under
4 ;; the terms of the GNU General Public License as published by the Free
5 ;; Software Foundation; either version 2 of the License, or (at your option)
8 ;; This file is distributed in the hope that it will be useful, but WITHOUT
9 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 ;; You should have received a copy of the GNU General Public License
14 ;; along with this file; see the file COPYING. If not, write to the Free
15 ;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
19 ;; This includes expands for all the intrinsics.
20 ;; spu_expand_builtin looks at the mode of match_operand.
25 (define_expand "spu_lqd"
26 [(set (match_operand:TI 0 "spu_reg_operand" "")
27 (mem:TI (and:SI (plus:SI (match_operand:SI 1 "spu_reg_operand" "")
28 (match_operand:SI 2 "spu_nonmem_operand" ""))
32 if (GET_CODE (operands[2]) == CONST_INT
33 && (INTVAL (operands[2]) & 15) != 0)
34 operands[2] = GEN_INT (INTVAL (operands[2]) & -16);
35 if (GET_CODE (operands[2]) != CONST_INT)
37 rtx op2 = operands[2];
38 operands[2] = force_reg (Pmode, operands[2]);
39 if (!ALIGNED_SYMBOL_REF_P (op2))
40 emit_insn (gen_andsi3 (operands[2], operands[2], GEN_INT (-16)));
44 (define_expand "spu_lqx"
45 [(set (match_operand:TI 0 "spu_reg_operand" "")
46 (mem:TI (and:SI (plus:SI (match_operand:SI 1 "spu_reg_operand" "")
47 (match_operand:SI 2 "spu_reg_operand" ""))
52 (define_expand "spu_lqa"
53 [(set (match_operand:TI 0 "spu_reg_operand" "")
54 (mem:TI (and:SI (match_operand:SI 1 "immediate_operand" "")
58 if (GET_CODE (operands[1]) == CONST_INT
59 && (INTVAL (operands[1]) & 15) != 0)
60 operands[1] = GEN_INT (INTVAL (operands[1]) & -16);
63 (define_expand "spu_lqr"
64 [(set (match_operand:TI 0 "spu_reg_operand" "")
65 (mem:TI (and:SI (match_operand:SI 1 "address_operand" "")
70 (define_expand "spu_stqd"
71 [(set (mem:TI (and:SI (plus:SI (match_operand:SI 1 "spu_reg_operand" "")
72 (match_operand:SI 2 "spu_nonmem_operand" ""))
74 (match_operand:TI 0 "spu_reg_operand" "r,r"))]
77 if (GET_CODE (operands[2]) == CONST_INT
78 && (INTVAL (operands[2]) & 15) != 0)
79 operands[2] = GEN_INT (INTVAL (operands[2]) & -16);
80 if (GET_CODE (operands[2]) != CONST_INT)
82 rtx op2 = operands[2];
83 operands[2] = force_reg (Pmode, operands[2]);
84 if (!ALIGNED_SYMBOL_REF_P (op2))
85 emit_insn (gen_andsi3 (operands[2], operands[2], GEN_INT (-16)));
89 (define_expand "spu_stqx"
90 [(set (mem:TI (and:SI (plus:SI (match_operand:SI 1 "spu_reg_operand" "")
91 (match_operand:SI 2 "spu_reg_operand" ""))
93 (match_operand:TI 0 "spu_reg_operand" "r"))]
97 (define_expand "spu_stqa"
98 [(set (mem:TI (and:SI (match_operand:SI 1 "immediate_operand" "")
100 (match_operand:TI 0 "spu_reg_operand" "r"))]
103 if (GET_CODE (operands[1]) == CONST_INT
104 && (INTVAL (operands[1]) & 15) != 0)
105 operands[1] = GEN_INT (INTVAL (operands[1]) & -16);
108 (define_expand "spu_stqr"
109 [(set (mem:TI (and:SI (match_operand:SI 1 "address_operand" "")
111 (match_operand:TI 0 "spu_reg_operand" ""))]
116 ;; generate control word
118 (define_expand "spu_cbx"
119 [(set (match_operand:TI 0 "spu_reg_operand" "")
120 (unspec:TI [(match_operand:SI 1 "spu_reg_operand" "")
121 (match_operand:SI 2 "spu_nonmem_operand" "")
122 (const_int 1)] UNSPEC_CPAT))]
126 (define_expand "spu_chx"
127 [(set (match_operand:TI 0 "spu_reg_operand" "")
128 (unspec:TI [(match_operand:SI 1 "spu_reg_operand" "")
129 (match_operand:SI 2 "spu_nonmem_operand" "")
130 (const_int 2)] UNSPEC_CPAT))]
134 (define_expand "spu_cwx"
135 [(set (match_operand:TI 0 "spu_reg_operand" "")
136 (unspec:TI [(match_operand:SI 1 "spu_reg_operand" "")
137 (match_operand:SI 2 "spu_nonmem_operand" "")
138 (const_int 4)] UNSPEC_CPAT))]
142 (define_expand "spu_cdx"
143 [(set (match_operand:TI 0 "spu_reg_operand" "")
144 (unspec:TI [(match_operand:SI 1 "spu_reg_operand" "")
145 (match_operand:SI 2 "spu_nonmem_operand" "")
146 (const_int 8)] UNSPEC_CPAT))]
152 ;; Constant formation
154 (define_expand "spu_ilhu"
155 [(set (match_operand:V4SI 0 "spu_reg_operand" "")
156 (const_vector:V4SI [(match_operand:SI 1 "immediate_operand" "")]))]
158 "{ emit_insn(gen_movv4si(operands[0], spu_const(V4SImode, (INTVAL(operands[1]) << 16))));
164 (define_expand "spu_sfh"
165 [(set (match_operand:V8HI 0 "spu_reg_operand" "")
166 (minus:V8HI (match_operand:V8HI 2 "spu_nonmem_operand" "")
167 (match_operand:V8HI 1 "spu_reg_operand" "")))]
171 (define_expand "spu_sf"
172 [(set (match_operand:V4SI 0 "spu_reg_operand" "")
173 (minus:V4SI (match_operand:V4SI 2 "spu_nonmem_operand" "")
174 (match_operand:V4SI 1 "spu_reg_operand" "")))]
178 (define_expand "spu_sfx"
179 [(set (match_operand:V4SI 0 "spu_reg_operand" "")
180 (unspec:V4SI [(match_operand:V4SI 2 "spu_reg_operand" "")
181 (match_operand:V4SI 1 "spu_reg_operand" "")
182 (match_operand:V4SI 3 "spu_reg_operand" "")] UNSPEC_SFX))]
186 (define_expand "spu_bg"
187 [(set (match_operand:V4SI 0 "spu_reg_operand" "")
188 (unspec:V4SI [(match_operand:V4SI 2 "spu_reg_operand" "")
189 (match_operand:V4SI 1 "spu_reg_operand" "")] UNSPEC_BG))]
193 (define_expand "spu_bgx"
194 [(set (match_operand:V4SI 0 "spu_reg_operand" "")
195 (unspec:V4SI [(match_operand:V4SI 2 "spu_reg_operand" "")
196 (match_operand:V4SI 1 "spu_reg_operand" "")
197 (match_operand:V4SI 3 "spu_reg_operand" "")] UNSPEC_BGX))]
202 (define_insn "spu_mpy"
203 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r,r")
207 (match_operand:V8HI 1 "spu_reg_operand" "r,r")
208 (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)])))
211 (match_operand:V8HI 2 "spu_arith_operand" "r,B")
212 (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)])))))]
217 [(set_attr "type" "fp7")])
219 (define_insn "spu_mpyu"
220 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r,r")
224 (match_operand:V8HI 1 "spu_reg_operand" "r,r")
225 (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)])))
228 (match_operand:V8HI 2 "spu_arith_operand" "r,B")
229 (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)])))))]
234 [(set_attr "type" "fp7")])
236 (define_insn "spu_mpya"
237 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
242 (match_operand:V8HI 1 "spu_reg_operand" "r")
243 (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)])))
246 (match_operand:V8HI 2 "spu_reg_operand" "r")
247 (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)]))))
248 (match_operand:V4SI 3 "spu_reg_operand" "r")))]
251 [(set_attr "type" "fp7")])
253 (define_insn "spu_mpyh"
254 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
259 (match_operand:V8HI 1 "spu_reg_operand" "r")
260 (parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)])))
263 (match_operand:V8HI 2 "spu_reg_operand" "r")
264 (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)]))))
265 (const_vector:V4SI [(const_int 16)(const_int 16)(const_int 16)(const_int 16)])))]
268 [(set_attr "type" "fp7")])
270 (define_insn "spu_mpys"
271 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
276 (match_operand:V8HI 1 "spu_reg_operand" "r")
277 (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)])))
280 (match_operand:V8HI 2 "spu_reg_operand" "r")
281 (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)]))))
282 (const_vector:V4SI [(const_int 16)(const_int 16)(const_int 16)(const_int 16)])))]
285 [(set_attr "type" "fp7")])
287 (define_insn "spu_mpyhhu"
288 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
292 (match_operand:V8HI 1 "spu_reg_operand" "r")
293 (parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)])))
296 (match_operand:V8HI 2 "spu_reg_operand" "r")
297 (parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)])))))]
300 [(set_attr "type" "fp7")])
302 (define_insn "spu_mpyhh"
303 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
307 (match_operand:V8HI 1 "spu_reg_operand" "r")
308 (parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)])))
311 (match_operand:V8HI 2 "spu_reg_operand" "r")
312 (parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)])))))]
315 [(set_attr "type" "fp7")])
317 (define_insn "spu_mpyhhau"
318 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
323 (match_operand:V8HI 1 "spu_reg_operand" "r")
324 (parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)])))
327 (match_operand:V8HI 2 "spu_reg_operand" "r")
328 (parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)]))))
329 (match_operand:V4SI 3 "spu_reg_operand" "0")))]
332 [(set_attr "type" "fp7")])
334 (define_insn "spu_mpyhha"
335 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
340 (match_operand:V8HI 1 "spu_reg_operand" "r")
341 (parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)])))
344 (match_operand:V8HI 2 "spu_reg_operand" "r")
345 (parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)]))))
346 (match_operand:V4SI 3 "spu_reg_operand" "0")))]
349 [(set_attr "type" "fp7")])
352 (define_insn "spu_fsmb"
353 [(set (match_operand:V16QI 0 "spu_reg_operand" "=r,r")
354 (unspec:V16QI [(match_operand:SI 1 "spu_nonmem_operand" "r,MN")] UNSPEC_FSMB))]
359 [(set_attr "type" "shuf")])
361 (define_insn "spu_fsmh"
362 [(set (match_operand:V8HI 0 "spu_reg_operand" "=r")
363 (unspec:V8HI [(match_operand:SI 1 "spu_reg_operand" "r")] UNSPEC_FSMH))]
366 [(set_attr "type" "shuf")])
368 (define_insn "spu_fsm"
369 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
370 (unspec:V4SI [(match_operand:SI 1 "spu_reg_operand" "r")] UNSPEC_FSM))]
373 [(set_attr "type" "shuf")])
377 (define_insn "spu_gbb"
378 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
379 (unspec:V4SI [(match_operand:V16QI 1 "spu_reg_operand" "r")] UNSPEC_GBB))]
382 [(set_attr "type" "shuf")])
384 (define_insn "spu_gbh"
385 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
386 (unspec:V4SI [(match_operand:V8HI 1 "spu_reg_operand" "r")] UNSPEC_GBH))]
389 [(set_attr "type" "shuf")])
391 (define_insn "spu_gb"
392 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
393 (unspec:V4SI [(match_operand:V4SI 1 "spu_reg_operand" "r")] UNSPEC_GB))]
396 [(set_attr "type" "shuf")])
398 ;; misc byte operations
399 (define_insn "spu_avgb"
400 [(set (match_operand:V16QI 0 "spu_reg_operand" "=r")
401 (unspec:V16QI [(match_operand:V16QI 1 "spu_reg_operand" "r")
402 (match_operand:V16QI 2 "spu_reg_operand" "r")] UNSPEC_AVGB))]
405 [(set_attr "type" "fxb")])
407 (define_insn "spu_absdb"
408 [(set (match_operand:V16QI 0 "spu_reg_operand" "=r")
409 (unspec:V16QI [(match_operand:V16QI 1 "spu_reg_operand" "r")
410 (match_operand:V16QI 2 "spu_reg_operand" "r")] UNSPEC_ABSDB))]
413 [(set_attr "type" "fxb")])
415 (define_insn "spu_sumb"
416 [(set (match_operand:V8HI 0 "spu_reg_operand" "=r")
417 (unspec:V8HI [(match_operand:V16QI 1 "spu_reg_operand" "r")
418 (match_operand:V16QI 2 "spu_reg_operand" "r")] UNSPEC_SUMB))]
421 [(set_attr "type" "fxb")])
424 (define_insn "spu_xsbh"
425 [(set (match_operand:V8HI 0 "spu_reg_operand" "=r")
428 (match_operand:V16QI 1 "spu_reg_operand" "r")
429 (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)
430 (const_int 9)(const_int 11)(const_int 13)(const_int 15)]))))]
434 (define_insn "spu_xshw"
435 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
438 (match_operand:V8HI 1 "spu_reg_operand" "r")
439 (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)]))))]
443 (define_insn "spu_xswd"
444 [(set (match_operand:V2DI 0 "spu_reg_operand" "=r")
447 (match_operand:V4SI 1 "spu_reg_operand" "r")
448 (parallel [(const_int 1)(const_int 3)]))))]
454 (define_insn "spu_orx"
455 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
456 (unspec:V4SI [(match_operand:V4SI 1 "spu_reg_operand" "r")] UNSPEC_ORX))]
462 (define_insn "spu_heq"
463 [(unspec_volatile [(match_operand:SI 0 "spu_reg_operand" "r,r")
464 (match_operand:SI 1 "spu_nonmem_operand" "r,K")] UNSPEC_HEQ)]
470 (define_insn "spu_hgt"
471 [(unspec_volatile [(match_operand:SI 0 "spu_reg_operand" "r,r")
472 (match_operand:SI 1 "spu_nonmem_operand" "r,K")] UNSPEC_HGT)]
478 (define_insn "spu_hlgt"
479 [(unspec_volatile [(match_operand:SI 0 "spu_reg_operand" "r,r")
480 (match_operand:SI 1 "spu_nonmem_operand" "r,K")] UNSPEC_HLGT)]
488 ;; The description below hides the fact that bisled conditionally
489 ;; executes the call depending on the value in channel 0. This was
490 ;; done so that the description would conform to the format of a call
491 ;; insn. Otherwise (if this were not part of call insn), the link
492 ;; register, $lr, would not be saved/restored in the prologue/epilogue.
494 (define_insn "spu_bisled"
496 [(call (mem:QI (match_operand:SI 0 "spu_reg_operand" "r"))
499 (clobber (reg:SI 130))
500 (use (match_operand:SI 1 "address_operand" ""))
501 (use (const_int 0))])]
504 [(set_attr "type" "br")])
506 (define_insn "spu_bisledd"
508 [(call (mem:QI (match_operand:SI 0 "spu_reg_operand" "r"))
511 (clobber (reg:SI 130))
512 (use (match_operand:SI 1 "address_operand" ""))
513 (use (const_int 1))])]
516 [(set_attr "type" "br")])
518 (define_insn "spu_bislede"
520 [(call (mem:QI (match_operand:SI 0 "spu_reg_operand" "r"))
523 (clobber (reg:SI 130))
524 (use (match_operand:SI 1 "address_operand" ""))
525 (use (const_int 2))])]
528 [(set_attr "type" "br")])
531 (define_insn "spu_csflt"
532 [(set (match_operand:V4SF 0 "spu_reg_operand" "=r")
533 (unspec:V4SF [(match_operand:V4SI 1 "spu_reg_operand" "r")
534 (match_operand:SI 2 "immediate_operand" "K")] UNSPEC_CSFLT ))]
537 [(set_attr "type" "fp7")])
539 (define_insn "spu_cflts"
540 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
541 (unspec:V4SI [(match_operand:V4SF 1 "spu_reg_operand" "r")
542 (match_operand:SI 2 "immediate_operand" "J")] UNSPEC_CFLTS ))]
545 [(set_attr "type" "fp7")])
547 (define_insn "spu_cuflt"
548 [(set (match_operand:V4SF 0 "spu_reg_operand" "=r")
549 (unspec:V4SF [(match_operand:V4SI 1 "spu_reg_operand" "r")
550 (match_operand:SI 2 "immediate_operand" "K")] UNSPEC_CUFLT ))]
553 [(set_attr "type" "fp7")])
555 (define_insn "spu_cfltu"
556 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
557 (unspec:V4SI [(match_operand:V4SF 1 "spu_reg_operand" "r")
558 (match_operand:SI 2 "immediate_operand" "J")] UNSPEC_CFLTU ))]
561 [(set_attr "type" "fp7")])
563 (define_expand "spu_frds"
564 [(set (match_operand:V4SF 0 "spu_reg_operand" "")
567 (float_truncate:V2SF (match_operand:V2DF 1 "spu_reg_operand" ""))
569 (parallel [(const_int 0)(const_int 2)(const_int 1)(const_int 3)])))]
571 "operands[2] = spu_const(V2SFmode, 0);")
574 [(set (match_operand:V4SF 0 "spu_reg_operand" "=r")
577 (float_truncate:V2SF (match_operand:V2DF 1 "spu_reg_operand" "r"))
578 (match_operand:V2SF 2 "vec_imm_operand" "i"))
579 (parallel [(const_int 0)(const_int 2)(const_int 1)(const_int 3)])))]
582 [(set_attr "type" "fpd")])
584 (define_insn "spu_fesd"
585 [(set (match_operand:V2DF 0 "spu_reg_operand" "=r")
588 (match_operand:V4SF 1 "spu_reg_operand" "r")
589 (parallel [(const_int 0)(const_int 2)]))))]
592 [(set_attr "type" "fpd")])
595 (define_insn "spu_stop"
596 [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "M")] UNSPEC_STOP)]
599 [(set_attr "type" "br")])
601 (define_insn "spu_stopd"
602 [(unspec_volatile [(match_operand:SI 0 "spu_reg_operand" "r")
603 (match_operand:SI 1 "spu_reg_operand" "r")
604 (match_operand:SI 2 "spu_reg_operand" "r")] UNSPEC_STOPD)]
607 [(set_attr "type" "br")])
609 ;; interrupt disable/enable
610 (define_expand "spu_idisable"
612 [(unspec_volatile [(const_int 0)] UNSPEC_SET_INTR)
613 (clobber (match_dup:SI 0))
614 (clobber (mem:BLK (scratch)))])]
616 "operands[0] = gen_reg_rtx (SImode);")
618 (define_expand "spu_ienable"
620 [(unspec_volatile [(const_int 1)] UNSPEC_SET_INTR)
621 (clobber (match_dup:SI 0))
622 (clobber (mem:BLK (scratch)))])]
624 "operands[0] = gen_reg_rtx (SImode);")
626 (define_insn "set_intr"
627 [(unspec_volatile [(match_operand 1 "const_int_operand" "i")] UNSPEC_SET_INTR)
628 (clobber (match_operand:SI 0 "spu_reg_operand" "=&r"))
629 (clobber (mem:BLK (scratch)))]
631 "ila\t%0,.+8\;bi%I1\t%0"
632 [(set_attr "length" "8")
633 (set_attr "type" "multi0")])
635 (define_insn "set_intr_pic"
636 [(unspec_volatile [(match_operand 1 "const_int_operand" "i")] UNSPEC_SET_INTR)
637 (clobber (match_operand:SI 0 "spu_reg_operand" "=&r"))
638 (clobber (mem:BLK (scratch)))]
640 "brsl\t%0,.+4\;ai\t%0,%0,8\;bi%I1\t%0"
641 [(set_attr "length" "12")
642 (set_attr "type" "multi1")])
644 (define_insn "set_intr_cc"
645 [(cond_exec (match_operator 1 "branch_comparison_operator"
646 [(match_operand 2 "spu_reg_operand" "r")
648 (parallel [(unspec_volatile [(match_operand:SI 3 "const_int_operand" "i")] UNSPEC_SET_INTR)
649 (clobber (match_operand:SI 0 "spu_reg_operand" "=&r"))
650 (clobber (mem:BLK (scratch)))]))]
652 "ila\t%0,.+8\;bi%b2%b1z%I3\t%2,%0"
653 [(set_attr "length" "8")
654 (set_attr "type" "multi0")])
656 (define_insn "set_intr_cc_pic"
657 [(cond_exec (match_operator 1 "branch_comparison_operator"
658 [(match_operand 2 "spu_reg_operand" "r")
660 (parallel [(unspec_volatile [(match_operand:SI 3 "const_int_operand" "i")] UNSPEC_SET_INTR)
661 (clobber (match_operand:SI 0 "spu_reg_operand" "=&r"))
662 (clobber (mem:BLK (scratch)))]))]
664 "brsl\t%0,.+4\;ai\t%0,%0,8\;bi%b2%b1z%I3\t%2,%0"
665 [(set_attr "length" "12")
666 (set_attr "type" "multi1")])
668 (define_insn "set_intr_return"
669 [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "i")] UNSPEC_SET_INTR)
673 [(set_attr "type" "br")])
677 [(unspec_volatile [(match_operand:SI 0 "const_int_operand")] UNSPEC_SET_INTR)
678 (clobber (match_operand:SI 1 "spu_reg_operand"))
679 (clobber (mem:BLK (scratch)))])
685 [(unspec_volatile [(match_dup:SI 0)] UNSPEC_SET_INTR)
689 ;; special purpose registers
690 (define_insn "spu_fscrrd"
691 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
692 (unspec_volatile:V4SI [(const_int 6)] UNSPEC_FSCRRD))]
695 [(set_attr "type" "spr")])
697 (define_insn "spu_fscrwr"
698 [(unspec_volatile [(match_operand:V4SI 0 "spu_reg_operand" "r")] UNSPEC_FSCRWR)]
701 [(set_attr "type" "spr")])
703 (define_insn "spu_mfspr"
704 [(set (match_operand:SI 0 "spu_reg_operand" "=r")
705 (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "J")] UNSPEC_MFSPR))]
708 [(set_attr "type" "spr")])
710 (define_insn "spu_mtspr"
711 [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "J")
712 (match_operand:SI 1 "spu_reg_operand" "r")] UNSPEC_MTSPR)]
715 [(set_attr "type" "spr")])
718 (define_expand "spu_rdch"
719 [(set (match_operand:V4SI 0 "spu_reg_operand" "")
720 (unspec_volatile:V4SI [(match_operand:SI 1 "immediate_operand" "")] UNSPEC_RDCH))]
723 if (spu_safe_dma (INTVAL (operands[1])))
725 emit_insn (gen_spu_rdch_clobber (operands[0], operands[1]));
730 (define_expand "spu_rchcnt"
731 [(set (match_operand:SI 0 "spu_reg_operand" "")
732 (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "")] UNSPEC_RCHCNT))]
735 if (spu_safe_dma (INTVAL (operands[1])))
737 emit_insn (gen_spu_rchcnt_clobber (operands[0], operands[1]));
742 (define_expand "spu_wrch"
743 [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "")
744 (match_operand:V4SI 1 "spu_reg_operand" "")] UNSPEC_WRCH)]
747 if (spu_safe_dma (INTVAL (operands[0])))
749 emit_insn (gen_spu_wrch_clobber (operands[0], operands[1]));
754 (define_insn "spu_rdch_noclobber"
755 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
756 (unspec_volatile:V4SI [(match_operand:SI 1 "immediate_operand" "J")] UNSPEC_RDCH))]
759 [(set_attr "type" "spr")])
761 (define_insn "spu_rchcnt_noclobber"
762 [(set (match_operand:SI 0 "spu_reg_operand" "=r")
763 (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "J")] UNSPEC_RCHCNT))]
766 [(set_attr "type" "spr")])
768 (define_insn "spu_wrch_noclobber"
769 [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "J")
770 (match_operand:V4SI 1 "spu_reg_operand" "r")] UNSPEC_WRCH)]
773 [(set_attr "type" "spr")])
775 (define_insn "spu_rdch_clobber"
776 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
777 (unspec_volatile:V4SI [(match_operand:SI 1 "immediate_operand" "J")] UNSPEC_RDCH))
778 (clobber (mem:BLK (scratch)))]
781 [(set_attr "type" "spr")])
783 (define_insn "spu_rchcnt_clobber"
784 [(set (match_operand:SI 0 "spu_reg_operand" "=r")
785 (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "J")] UNSPEC_RCHCNT))
786 (clobber (mem:BLK (scratch)))]
789 [(set_attr "type" "spr")])
791 (define_insn "spu_wrch_clobber"
792 [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "J")
793 (match_operand:V4SI 1 "spu_reg_operand" "r")] UNSPEC_WRCH)
794 (clobber (mem:BLK (scratch)))]
797 [(set_attr "type" "spr")])
799 (define_expand "spu_splats"
800 [(set (match_operand 0 "spu_reg_operand" "")
801 (vec_duplicate (match_operand 1 "spu_nonmem_operand" "")))]
804 spu_builtin_splats(operands);
808 (define_expand "spu_extract"
809 [(set (match_operand 0 "spu_reg_operand" "")
810 (unspec [(match_operand 1 "spu_reg_operand" "")
811 (match_operand 2 "spu_nonmem_operand" "")] 0))]
814 spu_builtin_extract (operands);
818 (define_expand "spu_insert"
819 [(set (match_operand 0 "spu_reg_operand" "")
820 (unspec [(match_operand 1 "spu_reg_operand" "")
821 (match_operand 2 "spu_reg_operand" "")
822 (match_operand:SI 3 "spu_nonmem_operand" "")] 0))]
825 spu_builtin_insert(operands);
829 (define_expand "spu_promote"
830 [(set (match_operand 0 "spu_reg_operand" "")
831 (unspec [(match_operand 1 "spu_reg_operand" "")
832 (match_operand:SI 2 "immediate_operand" "")] 0))]
835 spu_builtin_promote(operands);
839 ;; Currently doing nothing with this but expanding its args.
840 (define_expand "spu_align_hint"
841 [(unspec [(match_operand:SI 0 "address_operand" "")
842 (match_operand:SI 1 "immediate_operand" "")
843 (match_operand:SI 2 "immediate_operand" "")] 0)]