1 ;; Machine description for SPARC chip for GCC
2 ;; Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
4 ;; Contributed by Michael Tiemann (tiemann@cygnus.com)
5 ;; 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 2, or (at your option)
15 ;; GCC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING. If not, write to
22 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
23 ;; Boston, MA 02111-1307, USA.
25 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 (UNSPEC_UPDATE_RETURN 1)
31 (UNSPEC_MOVE_PIC_LABEL 5)
37 (UNSPEC_EMB_TEXTUHI 13)
38 (UNSPEC_EMB_TEXTHI 14)
39 (UNSPEC_EMB_TEXTULO 15)
47 (UNSPEC_TLSLD_BASE 35)
59 ;; The upper 32 fp regs on the v9 can't hold SFmode values. To deal with this
60 ;; a second register class, EXTRA_FP_REGS, exists for the v9 chip. The name
61 ;; is a bit of a misnomer as it covers all 64 fp regs. The corresponding
62 ;; constraint letter is 'e'. To avoid any confusion, 'e' is used instead of
63 ;; 'f' for all DF/TFmode values, including those that are specific to the v8.
65 ;; Attribute for cpu type.
66 ;; These must match the values for enum processor_type in sparc.h.
73 hypersparc,sparclite86x,
78 (const (symbol_ref "sparc_cpu_attr")))
80 ;; Attribute for the instruction set.
81 ;; At present we only need to distinguish v9/!v9, but for clarity we
82 ;; test TARGET_V8 too.
83 (define_attr "isa" "v6,v8,v9,sparclet"
85 (cond [(symbol_ref "TARGET_V9") (const_string "v9")
86 (symbol_ref "TARGET_V8") (const_string "v8")
87 (symbol_ref "TARGET_SPARCLET") (const_string "sparclet")]
88 (const_string "v6"))))
91 (define_attr "arch" "arch32bit,arch64bit"
93 (cond [(symbol_ref "TARGET_ARCH64") (const_string "arch64bit")]
94 (const_string "arch32bit"))))
101 uncond_branch,branch,call,sibcall,call_no_delay_slot,
109 fga,fgm_pack,fgm_mul,fgm_pdist,fgm_cmp,
112 multi,flushw,iflush,trap"
113 (const_string "ialu"))
115 ;; true if branch/call has empty delay slot and will emit a nop in it
116 (define_attr "empty_delay_slot" "false,true"
117 (symbol_ref "empty_delay_slot (insn)"))
119 (define_attr "branch_type" "none,icc,fcc,reg" (const_string "none"))
121 (define_attr "pic" "false,true"
122 (symbol_ref "flag_pic != 0"))
124 (define_attr "current_function_calls_alloca" "false,true"
125 (symbol_ref "current_function_calls_alloca != 0"))
127 (define_attr "flat" "false,true"
128 (symbol_ref "TARGET_FLAT != 0"))
130 ;; Length (in # of insns).
131 (define_attr "length" ""
132 (cond [(eq_attr "type" "uncond_branch,call,sibcall")
133 (if_then_else (eq_attr "empty_delay_slot" "true")
136 (eq_attr "branch_type" "icc")
137 (if_then_else (match_operand 0 "noov_compare64_op" "")
138 (if_then_else (lt (pc) (match_dup 1))
139 (if_then_else (lt (minus (match_dup 1) (pc)) (const_int 260000))
140 (if_then_else (eq_attr "empty_delay_slot" "true")
143 (if_then_else (eq_attr "empty_delay_slot" "true")
146 (if_then_else (lt (minus (pc) (match_dup 1)) (const_int 260000))
147 (if_then_else (eq_attr "empty_delay_slot" "true")
150 (if_then_else (eq_attr "empty_delay_slot" "true")
153 (if_then_else (eq_attr "empty_delay_slot" "true")
156 (eq_attr "branch_type" "fcc")
157 (if_then_else (match_operand 0 "fcc0_reg_operand" "")
158 (if_then_else (eq_attr "empty_delay_slot" "true")
159 (if_then_else (eq (symbol_ref "TARGET_V9") (const_int 0))
162 (if_then_else (eq (symbol_ref "TARGET_V9") (const_int 0))
165 (if_then_else (lt (pc) (match_dup 2))
166 (if_then_else (lt (minus (match_dup 2) (pc)) (const_int 260000))
167 (if_then_else (eq_attr "empty_delay_slot" "true")
170 (if_then_else (eq_attr "empty_delay_slot" "true")
173 (if_then_else (lt (minus (pc) (match_dup 2)) (const_int 260000))
174 (if_then_else (eq_attr "empty_delay_slot" "true")
177 (if_then_else (eq_attr "empty_delay_slot" "true")
180 (eq_attr "branch_type" "reg")
181 (if_then_else (lt (pc) (match_dup 2))
182 (if_then_else (lt (minus (match_dup 2) (pc)) (const_int 32000))
183 (if_then_else (eq_attr "empty_delay_slot" "true")
186 (if_then_else (eq_attr "empty_delay_slot" "true")
189 (if_then_else (lt (minus (pc) (match_dup 2)) (const_int 32000))
190 (if_then_else (eq_attr "empty_delay_slot" "true")
193 (if_then_else (eq_attr "empty_delay_slot" "true")
199 (define_attr "fptype" "single,double" (const_string "single"))
201 ;; UltraSPARC-III integer load type.
202 (define_attr "us3load_type" "2cycle,3cycle" (const_string "2cycle"))
204 (define_asm_attributes
205 [(set_attr "length" "2")
206 (set_attr "type" "multi")])
208 ;; Attributes for instruction and branch scheduling
210 (define_attr "tls_call_delay" "false,true"
211 (symbol_ref "tls_call_delay (insn)"))
213 (define_attr "in_call_delay" "false,true"
214 (cond [(eq_attr "type" "uncond_branch,branch,call,sibcall,call_no_delay_slot,multi")
215 (const_string "false")
216 (eq_attr "type" "load,fpload,store,fpstore")
217 (if_then_else (eq_attr "length" "1")
218 (const_string "true")
219 (const_string "false"))]
220 (if_then_else (and (eq_attr "length" "1")
221 (eq_attr "tls_call_delay" "true"))
222 (const_string "true")
223 (const_string "false"))))
225 (define_delay (eq_attr "type" "call")
226 [(eq_attr "in_call_delay" "true") (nil) (nil)])
228 (define_attr "eligible_for_sibcall_delay" "false,true"
229 (symbol_ref "eligible_for_sibcall_delay (insn)"))
231 (define_delay (eq_attr "type" "sibcall")
232 [(eq_attr "eligible_for_sibcall_delay" "true") (nil) (nil)])
234 (define_attr "leaf_function" "false,true"
235 (const (symbol_ref "current_function_uses_only_leaf_regs")))
237 ;; ??? Should implement the notion of predelay slots for floating point
238 ;; branches. This would allow us to remove the nop always inserted before
239 ;; a floating point branch.
241 ;; ??? It is OK for fill_simple_delay_slots to put load/store instructions
242 ;; in a delay slot, but it is not OK for fill_eager_delay_slots to do so.
243 ;; This is because doing so will add several pipeline stalls to the path
244 ;; that the load/store did not come from. Unfortunately, there is no way
245 ;; to prevent fill_eager_delay_slots from using load/store without completely
246 ;; disabling them. For the SPEC benchmark set, this is a serious lose,
247 ;; because it prevents us from moving back the final store of inner loops.
249 (define_attr "in_branch_delay" "false,true"
250 (if_then_else (and (eq_attr "type" "!uncond_branch,branch,call,sibcall,call_no_delay_slot,multi")
251 (eq_attr "length" "1"))
252 (const_string "true")
253 (const_string "false")))
255 (define_attr "in_uncond_branch_delay" "false,true"
256 (if_then_else (and (eq_attr "type" "!uncond_branch,branch,call,sibcall,call_no_delay_slot,multi")
257 (eq_attr "length" "1"))
258 (const_string "true")
259 (const_string "false")))
261 (define_attr "in_annul_branch_delay" "false,true"
262 (if_then_else (and (eq_attr "type" "!uncond_branch,branch,call,sibcall,call_no_delay_slot,multi")
263 (eq_attr "length" "1"))
264 (const_string "true")
265 (const_string "false")))
267 (define_delay (eq_attr "type" "branch")
268 [(eq_attr "in_branch_delay" "true")
269 (nil) (eq_attr "in_annul_branch_delay" "true")])
271 (define_delay (eq_attr "type" "uncond_branch")
272 [(eq_attr "in_uncond_branch_delay" "true")
275 ;; Include SPARC DFA schedulers
277 (include "cypress.md")
278 (include "supersparc.md")
279 (include "hypersparc.md")
280 (include "sparclet.md")
281 (include "ultra1_2.md")
282 (include "ultra3.md")
285 ;; Compare instructions.
286 ;; This controls RTL generation and register allocation.
288 ;; We generate RTL for comparisons and branches by having the cmpxx
289 ;; patterns store away the operands. Then, the scc and bcc patterns
290 ;; emit RTL for both the compare and the branch.
292 ;; We do this because we want to generate different code for an sne and
293 ;; seq insn. In those cases, if the second operand of the compare is not
294 ;; const0_rtx, we want to compute the xor of the two operands and test
297 ;; We start with the DEFINE_EXPANDs, then the DEFINE_INSNs to match
298 ;; the patterns. Finally, we have the DEFINE_SPLITs for some of the scc
299 ;; insns that actually require more than one machine instruction.
301 ;; Put cmpsi first among compare insns so it matches two CONST_INT operands.
303 (define_expand "cmpsi"
305 (compare:CC (match_operand:SI 0 "register_operand" "")
306 (match_operand:SI 1 "arith_operand" "")))]
309 sparc_compare_op0 = operands[0];
310 sparc_compare_op1 = operands[1];
314 (define_expand "cmpdi"
316 (compare:CCX (match_operand:DI 0 "register_operand" "")
317 (match_operand:DI 1 "arith_double_operand" "")))]
320 sparc_compare_op0 = operands[0];
321 sparc_compare_op1 = operands[1];
325 (define_expand "cmpsf"
326 ;; The 96 here isn't ever used by anyone.
328 (compare:CCFP (match_operand:SF 0 "register_operand" "")
329 (match_operand:SF 1 "register_operand" "")))]
332 sparc_compare_op0 = operands[0];
333 sparc_compare_op1 = operands[1];
337 (define_expand "cmpdf"
338 ;; The 96 here isn't ever used by anyone.
340 (compare:CCFP (match_operand:DF 0 "register_operand" "")
341 (match_operand:DF 1 "register_operand" "")))]
344 sparc_compare_op0 = operands[0];
345 sparc_compare_op1 = operands[1];
349 (define_expand "cmptf"
350 ;; The 96 here isn't ever used by anyone.
352 (compare:CCFP (match_operand:TF 0 "register_operand" "")
353 (match_operand:TF 1 "register_operand" "")))]
356 sparc_compare_op0 = operands[0];
357 sparc_compare_op1 = operands[1];
361 ;; Now the compare DEFINE_INSNs.
363 (define_insn "*cmpsi_insn"
365 (compare:CC (match_operand:SI 0 "register_operand" "r")
366 (match_operand:SI 1 "arith_operand" "rI")))]
369 [(set_attr "type" "compare")])
371 (define_insn "*cmpdi_sp64"
373 (compare:CCX (match_operand:DI 0 "register_operand" "r")
374 (match_operand:DI 1 "arith_double_operand" "rHI")))]
377 [(set_attr "type" "compare")])
379 (define_insn "*cmpsf_fpe"
380 [(set (match_operand:CCFPE 0 "fcc_reg_operand" "=c")
381 (compare:CCFPE (match_operand:SF 1 "register_operand" "f")
382 (match_operand:SF 2 "register_operand" "f")))]
386 return "fcmpes\t%0, %1, %2";
387 return "fcmpes\t%1, %2";
389 [(set_attr "type" "fpcmp")])
391 (define_insn "*cmpdf_fpe"
392 [(set (match_operand:CCFPE 0 "fcc_reg_operand" "=c")
393 (compare:CCFPE (match_operand:DF 1 "register_operand" "e")
394 (match_operand:DF 2 "register_operand" "e")))]
398 return "fcmped\t%0, %1, %2";
399 return "fcmped\t%1, %2";
401 [(set_attr "type" "fpcmp")
402 (set_attr "fptype" "double")])
404 (define_insn "*cmptf_fpe"
405 [(set (match_operand:CCFPE 0 "fcc_reg_operand" "=c")
406 (compare:CCFPE (match_operand:TF 1 "register_operand" "e")
407 (match_operand:TF 2 "register_operand" "e")))]
408 "TARGET_FPU && TARGET_HARD_QUAD"
411 return "fcmpeq\t%0, %1, %2";
412 return "fcmpeq\t%1, %2";
414 [(set_attr "type" "fpcmp")])
416 (define_insn "*cmpsf_fp"
417 [(set (match_operand:CCFP 0 "fcc_reg_operand" "=c")
418 (compare:CCFP (match_operand:SF 1 "register_operand" "f")
419 (match_operand:SF 2 "register_operand" "f")))]
423 return "fcmps\t%0, %1, %2";
424 return "fcmps\t%1, %2";
426 [(set_attr "type" "fpcmp")])
428 (define_insn "*cmpdf_fp"
429 [(set (match_operand:CCFP 0 "fcc_reg_operand" "=c")
430 (compare:CCFP (match_operand:DF 1 "register_operand" "e")
431 (match_operand:DF 2 "register_operand" "e")))]
435 return "fcmpd\t%0, %1, %2";
436 return "fcmpd\t%1, %2";
438 [(set_attr "type" "fpcmp")
439 (set_attr "fptype" "double")])
441 (define_insn "*cmptf_fp"
442 [(set (match_operand:CCFP 0 "fcc_reg_operand" "=c")
443 (compare:CCFP (match_operand:TF 1 "register_operand" "e")
444 (match_operand:TF 2 "register_operand" "e")))]
445 "TARGET_FPU && TARGET_HARD_QUAD"
448 return "fcmpq\t%0, %1, %2";
449 return "fcmpq\t%1, %2";
451 [(set_attr "type" "fpcmp")])
453 ;; Next come the scc insns. For seq, sne, sgeu, and sltu, we can do this
454 ;; without jumps using the addx/subx instructions. For seq/sne on v9 we use
455 ;; the same code as v8 (the addx/subx method has more applications). The
456 ;; exception to this is "reg != 0" which can be done in one instruction on v9
457 ;; (so we do it). For the rest, on v9 we use conditional moves; on v8, we do
460 ;; Seq_special[_xxx] and sne_special[_xxx] clobber the CC reg, because they
461 ;; generate addcc/subcc instructions.
463 (define_expand "seqsi_special"
465 (xor:SI (match_operand:SI 1 "register_operand" "")
466 (match_operand:SI 2 "register_operand" "")))
467 (parallel [(set (match_operand:SI 0 "register_operand" "")
468 (eq:SI (match_dup 3) (const_int 0)))
469 (clobber (reg:CC 100))])]
471 { operands[3] = gen_reg_rtx (SImode); })
473 (define_expand "seqdi_special"
475 (xor:DI (match_operand:DI 1 "register_operand" "")
476 (match_operand:DI 2 "register_operand" "")))
477 (set (match_operand:DI 0 "register_operand" "")
478 (eq:DI (match_dup 3) (const_int 0)))]
480 { operands[3] = gen_reg_rtx (DImode); })
482 (define_expand "snesi_special"
484 (xor:SI (match_operand:SI 1 "register_operand" "")
485 (match_operand:SI 2 "register_operand" "")))
486 (parallel [(set (match_operand:SI 0 "register_operand" "")
487 (ne:SI (match_dup 3) (const_int 0)))
488 (clobber (reg:CC 100))])]
490 { operands[3] = gen_reg_rtx (SImode); })
492 (define_expand "snedi_special"
494 (xor:DI (match_operand:DI 1 "register_operand" "")
495 (match_operand:DI 2 "register_operand" "")))
496 (set (match_operand:DI 0 "register_operand" "")
497 (ne:DI (match_dup 3) (const_int 0)))]
499 { operands[3] = gen_reg_rtx (DImode); })
501 (define_expand "seqdi_special_trunc"
503 (xor:DI (match_operand:DI 1 "register_operand" "")
504 (match_operand:DI 2 "register_operand" "")))
505 (set (match_operand:SI 0 "register_operand" "")
506 (eq:SI (match_dup 3) (const_int 0)))]
508 { operands[3] = gen_reg_rtx (DImode); })
510 (define_expand "snedi_special_trunc"
512 (xor:DI (match_operand:DI 1 "register_operand" "")
513 (match_operand:DI 2 "register_operand" "")))
514 (set (match_operand:SI 0 "register_operand" "")
515 (ne:SI (match_dup 3) (const_int 0)))]
517 { operands[3] = gen_reg_rtx (DImode); })
519 (define_expand "seqsi_special_extend"
521 (xor:SI (match_operand:SI 1 "register_operand" "")
522 (match_operand:SI 2 "register_operand" "")))
523 (parallel [(set (match_operand:DI 0 "register_operand" "")
524 (eq:DI (match_dup 3) (const_int 0)))
525 (clobber (reg:CC 100))])]
527 { operands[3] = gen_reg_rtx (SImode); })
529 (define_expand "snesi_special_extend"
531 (xor:SI (match_operand:SI 1 "register_operand" "")
532 (match_operand:SI 2 "register_operand" "")))
533 (parallel [(set (match_operand:DI 0 "register_operand" "")
534 (ne:DI (match_dup 3) (const_int 0)))
535 (clobber (reg:CC 100))])]
537 { operands[3] = gen_reg_rtx (SImode); })
539 ;; ??? v9: Operand 0 needs a mode, so SImode was chosen.
540 ;; However, the code handles both SImode and DImode.
542 [(set (match_operand:SI 0 "intreg_operand" "")
543 (eq:SI (match_dup 1) (const_int 0)))]
546 if (GET_MODE (sparc_compare_op0) == SImode)
550 if (GET_MODE (operands[0]) == SImode)
551 pat = gen_seqsi_special (operands[0], sparc_compare_op0,
553 else if (! TARGET_ARCH64)
556 pat = gen_seqsi_special_extend (operands[0], sparc_compare_op0,
561 else if (GET_MODE (sparc_compare_op0) == DImode)
567 else if (GET_MODE (operands[0]) == SImode)
568 pat = gen_seqdi_special_trunc (operands[0], sparc_compare_op0,
571 pat = gen_seqdi_special (operands[0], sparc_compare_op0,
576 else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
578 sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, EQ);
579 emit_jump_insn (gen_sne (operands[0]));
584 if (gen_v9_scc (EQ, operands))
591 ;; ??? v9: Operand 0 needs a mode, so SImode was chosen.
592 ;; However, the code handles both SImode and DImode.
594 [(set (match_operand:SI 0 "intreg_operand" "")
595 (ne:SI (match_dup 1) (const_int 0)))]
598 if (GET_MODE (sparc_compare_op0) == SImode)
602 if (GET_MODE (operands[0]) == SImode)
603 pat = gen_snesi_special (operands[0], sparc_compare_op0,
605 else if (! TARGET_ARCH64)
608 pat = gen_snesi_special_extend (operands[0], sparc_compare_op0,
613 else if (GET_MODE (sparc_compare_op0) == DImode)
619 else if (GET_MODE (operands[0]) == SImode)
620 pat = gen_snedi_special_trunc (operands[0], sparc_compare_op0,
623 pat = gen_snedi_special (operands[0], sparc_compare_op0,
628 else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
630 sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, NE);
631 emit_jump_insn (gen_sne (operands[0]));
636 if (gen_v9_scc (NE, operands))
644 [(set (match_operand:SI 0 "intreg_operand" "")
645 (gt:SI (match_dup 1) (const_int 0)))]
648 if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
650 sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, GT);
651 emit_jump_insn (gen_sne (operands[0]));
656 if (gen_v9_scc (GT, operands))
664 [(set (match_operand:SI 0 "intreg_operand" "")
665 (lt:SI (match_dup 1) (const_int 0)))]
668 if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
670 sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, LT);
671 emit_jump_insn (gen_sne (operands[0]));
676 if (gen_v9_scc (LT, operands))
684 [(set (match_operand:SI 0 "intreg_operand" "")
685 (ge:SI (match_dup 1) (const_int 0)))]
688 if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
690 sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, GE);
691 emit_jump_insn (gen_sne (operands[0]));
696 if (gen_v9_scc (GE, operands))
704 [(set (match_operand:SI 0 "intreg_operand" "")
705 (le:SI (match_dup 1) (const_int 0)))]
708 if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
710 sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, LE);
711 emit_jump_insn (gen_sne (operands[0]));
716 if (gen_v9_scc (LE, operands))
723 (define_expand "sgtu"
724 [(set (match_operand:SI 0 "intreg_operand" "")
725 (gtu:SI (match_dup 1) (const_int 0)))]
732 /* We can do ltu easily, so if both operands are registers, swap them and
734 if ((GET_CODE (sparc_compare_op0) == REG
735 || GET_CODE (sparc_compare_op0) == SUBREG)
736 && (GET_CODE (sparc_compare_op1) == REG
737 || GET_CODE (sparc_compare_op1) == SUBREG))
739 tem = sparc_compare_op0;
740 sparc_compare_op0 = sparc_compare_op1;
741 sparc_compare_op1 = tem;
742 pat = gen_sltu (operands[0]);
751 if (gen_v9_scc (GTU, operands))
757 (define_expand "sltu"
758 [(set (match_operand:SI 0 "intreg_operand" "")
759 (ltu:SI (match_dup 1) (const_int 0)))]
764 if (gen_v9_scc (LTU, operands))
767 operands[1] = gen_compare_reg (LTU, sparc_compare_op0, sparc_compare_op1);
770 (define_expand "sgeu"
771 [(set (match_operand:SI 0 "intreg_operand" "")
772 (geu:SI (match_dup 1) (const_int 0)))]
777 if (gen_v9_scc (GEU, operands))
780 operands[1] = gen_compare_reg (GEU, sparc_compare_op0, sparc_compare_op1);
783 (define_expand "sleu"
784 [(set (match_operand:SI 0 "intreg_operand" "")
785 (leu:SI (match_dup 1) (const_int 0)))]
792 /* We can do geu easily, so if both operands are registers, swap them and
794 if ((GET_CODE (sparc_compare_op0) == REG
795 || GET_CODE (sparc_compare_op0) == SUBREG)
796 && (GET_CODE (sparc_compare_op1) == REG
797 || GET_CODE (sparc_compare_op1) == SUBREG))
799 tem = sparc_compare_op0;
800 sparc_compare_op0 = sparc_compare_op1;
801 sparc_compare_op1 = tem;
802 pat = gen_sgeu (operands[0]);
811 if (gen_v9_scc (LEU, operands))
817 ;; Now the DEFINE_INSNs for the scc cases.
819 ;; The SEQ and SNE patterns are special because they can be done
820 ;; without any branching and do not involve a COMPARE. We want
821 ;; them to always use the splitz below so the results can be
824 (define_insn_and_split "*snesi_zero"
825 [(set (match_operand:SI 0 "register_operand" "=r")
826 (ne:SI (match_operand:SI 1 "register_operand" "r")
828 (clobber (reg:CC 100))]
832 [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
834 (set (match_dup 0) (ltu:SI (reg:CC 100) (const_int 0)))]
836 [(set_attr "length" "2")])
838 (define_insn_and_split "*neg_snesi_zero"
839 [(set (match_operand:SI 0 "register_operand" "=r")
840 (neg:SI (ne:SI (match_operand:SI 1 "register_operand" "r")
842 (clobber (reg:CC 100))]
846 [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
848 (set (match_dup 0) (neg:SI (ltu:SI (reg:CC 100) (const_int 0))))]
850 [(set_attr "length" "2")])
852 (define_insn_and_split "*snesi_zero_extend"
853 [(set (match_operand:DI 0 "register_operand" "=r")
854 (ne:DI (match_operand:SI 1 "register_operand" "r")
856 (clobber (reg:CC 100))]
860 [(set (reg:CC_NOOV 100) (compare:CC_NOOV (minus:SI (const_int 0)
863 (set (match_dup 0) (zero_extend:DI (plus:SI (plus:SI (const_int 0)
865 (ltu:SI (reg:CC_NOOV 100)
868 [(set_attr "length" "2")])
870 (define_insn_and_split "*snedi_zero"
871 [(set (match_operand:DI 0 "register_operand" "=&r")
872 (ne:DI (match_operand:DI 1 "register_operand" "r")
876 "&& ! reg_overlap_mentioned_p (operands[1], operands[0])"
877 [(set (match_dup 0) (const_int 0))
878 (set (match_dup 0) (if_then_else:DI (ne:DI (match_dup 1)
883 [(set_attr "length" "2")])
885 (define_insn_and_split "*neg_snedi_zero"
886 [(set (match_operand:DI 0 "register_operand" "=&r")
887 (neg:DI (ne:DI (match_operand:DI 1 "register_operand" "r")
891 "&& ! reg_overlap_mentioned_p (operands[1], operands[0])"
892 [(set (match_dup 0) (const_int 0))
893 (set (match_dup 0) (if_then_else:DI (ne:DI (match_dup 1)
898 [(set_attr "length" "2")])
900 (define_insn_and_split "*snedi_zero_trunc"
901 [(set (match_operand:SI 0 "register_operand" "=&r")
902 (ne:SI (match_operand:DI 1 "register_operand" "r")
906 "&& ! reg_overlap_mentioned_p (operands[1], operands[0])"
907 [(set (match_dup 0) (const_int 0))
908 (set (match_dup 0) (if_then_else:SI (ne:DI (match_dup 1)
913 [(set_attr "length" "2")])
915 (define_insn_and_split "*seqsi_zero"
916 [(set (match_operand:SI 0 "register_operand" "=r")
917 (eq:SI (match_operand:SI 1 "register_operand" "r")
919 (clobber (reg:CC 100))]
923 [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
925 (set (match_dup 0) (geu:SI (reg:CC 100) (const_int 0)))]
927 [(set_attr "length" "2")])
929 (define_insn_and_split "*neg_seqsi_zero"
930 [(set (match_operand:SI 0 "register_operand" "=r")
931 (neg:SI (eq:SI (match_operand:SI 1 "register_operand" "r")
933 (clobber (reg:CC 100))]
937 [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
939 (set (match_dup 0) (neg:SI (geu:SI (reg:CC 100) (const_int 0))))]
941 [(set_attr "length" "2")])
943 (define_insn_and_split "*seqsi_zero_extend"
944 [(set (match_operand:DI 0 "register_operand" "=r")
945 (eq:DI (match_operand:SI 1 "register_operand" "r")
947 (clobber (reg:CC 100))]
951 [(set (reg:CC_NOOV 100) (compare:CC_NOOV (minus:SI (const_int 0)
954 (set (match_dup 0) (zero_extend:DI (minus:SI (minus:SI (const_int 0)
956 (ltu:SI (reg:CC_NOOV 100)
959 [(set_attr "length" "2")])
961 (define_insn_and_split "*seqdi_zero"
962 [(set (match_operand:DI 0 "register_operand" "=&r")
963 (eq:DI (match_operand:DI 1 "register_operand" "r")
967 "&& ! reg_overlap_mentioned_p (operands[1], operands[0])"
968 [(set (match_dup 0) (const_int 0))
969 (set (match_dup 0) (if_then_else:DI (eq:DI (match_dup 1)
974 [(set_attr "length" "2")])
976 (define_insn_and_split "*neg_seqdi_zero"
977 [(set (match_operand:DI 0 "register_operand" "=&r")
978 (neg:DI (eq:DI (match_operand:DI 1 "register_operand" "r")
982 "&& ! reg_overlap_mentioned_p (operands[1], operands[0])"
983 [(set (match_dup 0) (const_int 0))
984 (set (match_dup 0) (if_then_else:DI (eq:DI (match_dup 1)
989 [(set_attr "length" "2")])
991 (define_insn_and_split "*seqdi_zero_trunc"
992 [(set (match_operand:SI 0 "register_operand" "=&r")
993 (eq:SI (match_operand:DI 1 "register_operand" "r")
997 "&& ! reg_overlap_mentioned_p (operands[1], operands[0])"
998 [(set (match_dup 0) (const_int 0))
999 (set (match_dup 0) (if_then_else:SI (eq:DI (match_dup 1)
1004 [(set_attr "length" "2")])
1006 ;; We can also do (x + (i == 0)) and related, so put them in.
1007 ;; ??? The addx/subx insns use the 32 bit carry flag so there are no DImode
1010 (define_insn_and_split "*x_plus_i_ne_0"
1011 [(set (match_operand:SI 0 "register_operand" "=r")
1012 (plus:SI (ne:SI (match_operand:SI 1 "register_operand" "r")
1014 (match_operand:SI 2 "register_operand" "r")))
1015 (clobber (reg:CC 100))]
1019 [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
1021 (set (match_dup 0) (plus:SI (ltu:SI (reg:CC 100) (const_int 0))
1024 [(set_attr "length" "2")])
1026 (define_insn_and_split "*x_minus_i_ne_0"
1027 [(set (match_operand:SI 0 "register_operand" "=r")
1028 (minus:SI (match_operand:SI 2 "register_operand" "r")
1029 (ne:SI (match_operand:SI 1 "register_operand" "r")
1031 (clobber (reg:CC 100))]
1035 [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
1037 (set (match_dup 0) (minus:SI (match_dup 2)
1038 (ltu:SI (reg:CC 100) (const_int 0))))]
1040 [(set_attr "length" "2")])
1042 (define_insn_and_split "*x_plus_i_eq_0"
1043 [(set (match_operand:SI 0 "register_operand" "=r")
1044 (plus:SI (eq:SI (match_operand:SI 1 "register_operand" "r")
1046 (match_operand:SI 2 "register_operand" "r")))
1047 (clobber (reg:CC 100))]
1051 [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
1053 (set (match_dup 0) (plus:SI (geu:SI (reg:CC 100) (const_int 0))
1056 [(set_attr "length" "2")])
1058 (define_insn_and_split "*x_minus_i_eq_0"
1059 [(set (match_operand:SI 0 "register_operand" "=r")
1060 (minus:SI (match_operand:SI 2 "register_operand" "r")
1061 (eq:SI (match_operand:SI 1 "register_operand" "r")
1063 (clobber (reg:CC 100))]
1067 [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
1069 (set (match_dup 0) (minus:SI (match_dup 2)
1070 (geu:SI (reg:CC 100) (const_int 0))))]
1072 [(set_attr "length" "2")])
1074 ;; We can also do GEU and LTU directly, but these operate after a compare.
1075 ;; ??? The addx/subx insns use the 32 bit carry flag so there are no DImode
1078 (define_insn "*sltu_insn"
1079 [(set (match_operand:SI 0 "register_operand" "=r")
1080 (ltu:SI (reg:CC 100) (const_int 0)))]
1083 [(set_attr "type" "ialuX")])
1085 (define_insn "*neg_sltu_insn"
1086 [(set (match_operand:SI 0 "register_operand" "=r")
1087 (neg:SI (ltu:SI (reg:CC 100) (const_int 0))))]
1090 [(set_attr "type" "ialuX")])
1092 ;; ??? Combine should canonicalize these next two to the same pattern.
1093 (define_insn "*neg_sltu_minus_x"
1094 [(set (match_operand:SI 0 "register_operand" "=r")
1095 (minus:SI (neg:SI (ltu:SI (reg:CC 100) (const_int 0)))
1096 (match_operand:SI 1 "arith_operand" "rI")))]
1098 "subx\t%%g0, %1, %0"
1099 [(set_attr "type" "ialuX")])
1101 (define_insn "*neg_sltu_plus_x"
1102 [(set (match_operand:SI 0 "register_operand" "=r")
1103 (neg:SI (plus:SI (ltu:SI (reg:CC 100) (const_int 0))
1104 (match_operand:SI 1 "arith_operand" "rI"))))]
1106 "subx\t%%g0, %1, %0"
1107 [(set_attr "type" "ialuX")])
1109 (define_insn "*sgeu_insn"
1110 [(set (match_operand:SI 0 "register_operand" "=r")
1111 (geu:SI (reg:CC 100) (const_int 0)))]
1113 "subx\t%%g0, -1, %0"
1114 [(set_attr "type" "ialuX")])
1116 (define_insn "*neg_sgeu_insn"
1117 [(set (match_operand:SI 0 "register_operand" "=r")
1118 (neg:SI (geu:SI (reg:CC 100) (const_int 0))))]
1120 "addx\t%%g0, -1, %0"
1121 [(set_attr "type" "ialuX")])
1123 ;; We can also do (x + ((unsigned) i >= 0)) and related, so put them in.
1124 ;; ??? The addx/subx insns use the 32 bit carry flag so there are no DImode
1127 (define_insn "*sltu_plus_x"
1128 [(set (match_operand:SI 0 "register_operand" "=r")
1129 (plus:SI (ltu:SI (reg:CC 100) (const_int 0))
1130 (match_operand:SI 1 "arith_operand" "rI")))]
1132 "addx\t%%g0, %1, %0"
1133 [(set_attr "type" "ialuX")])
1135 (define_insn "*sltu_plus_x_plus_y"
1136 [(set (match_operand:SI 0 "register_operand" "=r")
1137 (plus:SI (ltu:SI (reg:CC 100) (const_int 0))
1138 (plus:SI (match_operand:SI 1 "arith_operand" "%r")
1139 (match_operand:SI 2 "arith_operand" "rI"))))]
1142 [(set_attr "type" "ialuX")])
1144 (define_insn "*x_minus_sltu"
1145 [(set (match_operand:SI 0 "register_operand" "=r")
1146 (minus:SI (match_operand:SI 1 "register_operand" "r")
1147 (ltu:SI (reg:CC 100) (const_int 0))))]
1150 [(set_attr "type" "ialuX")])
1152 ;; ??? Combine should canonicalize these next two to the same pattern.
1153 (define_insn "*x_minus_y_minus_sltu"
1154 [(set (match_operand:SI 0 "register_operand" "=r")
1155 (minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
1156 (match_operand:SI 2 "arith_operand" "rI"))
1157 (ltu:SI (reg:CC 100) (const_int 0))))]
1160 [(set_attr "type" "ialuX")])
1162 (define_insn "*x_minus_sltu_plus_y"
1163 [(set (match_operand:SI 0 "register_operand" "=r")
1164 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
1165 (plus:SI (ltu:SI (reg:CC 100) (const_int 0))
1166 (match_operand:SI 2 "arith_operand" "rI"))))]
1169 [(set_attr "type" "ialuX")])
1171 (define_insn "*sgeu_plus_x"
1172 [(set (match_operand:SI 0 "register_operand" "=r")
1173 (plus:SI (geu:SI (reg:CC 100) (const_int 0))
1174 (match_operand:SI 1 "register_operand" "r")))]
1177 [(set_attr "type" "ialuX")])
1179 (define_insn "*x_minus_sgeu"
1180 [(set (match_operand:SI 0 "register_operand" "=r")
1181 (minus:SI (match_operand:SI 1 "register_operand" "r")
1182 (geu:SI (reg:CC 100) (const_int 0))))]
1185 [(set_attr "type" "ialuX")])
1188 [(set (match_operand:SI 0 "register_operand" "")
1189 (match_operator:SI 2 "noov_compare_op"
1190 [(match_operand 1 "icc_or_fcc_reg_operand" "")
1192 ;; 32 bit LTU/GEU are better implemented using addx/subx
1193 "TARGET_V9 && REGNO (operands[1]) == SPARC_ICC_REG
1194 && (GET_MODE (operands[1]) == CCXmode
1195 || (GET_CODE (operands[2]) != LTU && GET_CODE (operands[2]) != GEU))"
1196 [(set (match_dup 0) (const_int 0))
1198 (if_then_else:SI (match_op_dup:SI 2 [(match_dup 1) (const_int 0)])
1204 ;; These control RTL generation for conditional jump insns
1206 ;; The quad-word fp compare library routines all return nonzero to indicate
1207 ;; true, which is different from the equivalent libgcc routines, so we must
1208 ;; handle them specially here.
1210 (define_expand "beq"
1212 (if_then_else (eq (match_dup 1) (const_int 0))
1213 (label_ref (match_operand 0 "" ""))
1217 if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx
1218 && GET_CODE (sparc_compare_op0) == REG
1219 && GET_MODE (sparc_compare_op0) == DImode)
1221 emit_v9_brxx_insn (EQ, sparc_compare_op0, operands[0]);
1224 else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
1226 sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, EQ);
1227 emit_jump_insn (gen_bne (operands[0]));
1230 operands[1] = gen_compare_reg (EQ, sparc_compare_op0, sparc_compare_op1);
1233 (define_expand "bne"
1235 (if_then_else (ne (match_dup 1) (const_int 0))
1236 (label_ref (match_operand 0 "" ""))
1240 if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx
1241 && GET_CODE (sparc_compare_op0) == REG
1242 && GET_MODE (sparc_compare_op0) == DImode)
1244 emit_v9_brxx_insn (NE, sparc_compare_op0, operands[0]);
1247 else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
1249 sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, NE);
1250 emit_jump_insn (gen_bne (operands[0]));
1253 operands[1] = gen_compare_reg (NE, sparc_compare_op0, sparc_compare_op1);
1256 (define_expand "bgt"
1258 (if_then_else (gt (match_dup 1) (const_int 0))
1259 (label_ref (match_operand 0 "" ""))
1263 if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx
1264 && GET_CODE (sparc_compare_op0) == REG
1265 && GET_MODE (sparc_compare_op0) == DImode)
1267 emit_v9_brxx_insn (GT, sparc_compare_op0, operands[0]);
1270 else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
1272 sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, GT);
1273 emit_jump_insn (gen_bne (operands[0]));
1276 operands[1] = gen_compare_reg (GT, sparc_compare_op0, sparc_compare_op1);
1279 (define_expand "bgtu"
1281 (if_then_else (gtu (match_dup 1) (const_int 0))
1282 (label_ref (match_operand 0 "" ""))
1286 operands[1] = gen_compare_reg (GTU, sparc_compare_op0, sparc_compare_op1);
1289 (define_expand "blt"
1291 (if_then_else (lt (match_dup 1) (const_int 0))
1292 (label_ref (match_operand 0 "" ""))
1296 if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx
1297 && GET_CODE (sparc_compare_op0) == REG
1298 && GET_MODE (sparc_compare_op0) == DImode)
1300 emit_v9_brxx_insn (LT, sparc_compare_op0, operands[0]);
1303 else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
1305 sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, LT);
1306 emit_jump_insn (gen_bne (operands[0]));
1309 operands[1] = gen_compare_reg (LT, sparc_compare_op0, sparc_compare_op1);
1312 (define_expand "bltu"
1314 (if_then_else (ltu (match_dup 1) (const_int 0))
1315 (label_ref (match_operand 0 "" ""))
1319 operands[1] = gen_compare_reg (LTU, sparc_compare_op0, sparc_compare_op1);
1322 (define_expand "bge"
1324 (if_then_else (ge (match_dup 1) (const_int 0))
1325 (label_ref (match_operand 0 "" ""))
1329 if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx
1330 && GET_CODE (sparc_compare_op0) == REG
1331 && GET_MODE (sparc_compare_op0) == DImode)
1333 emit_v9_brxx_insn (GE, sparc_compare_op0, operands[0]);
1336 else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
1338 sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, GE);
1339 emit_jump_insn (gen_bne (operands[0]));
1342 operands[1] = gen_compare_reg (GE, sparc_compare_op0, sparc_compare_op1);
1345 (define_expand "bgeu"
1347 (if_then_else (geu (match_dup 1) (const_int 0))
1348 (label_ref (match_operand 0 "" ""))
1352 operands[1] = gen_compare_reg (GEU, sparc_compare_op0, sparc_compare_op1);
1355 (define_expand "ble"
1357 (if_then_else (le (match_dup 1) (const_int 0))
1358 (label_ref (match_operand 0 "" ""))
1362 if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx
1363 && GET_CODE (sparc_compare_op0) == REG
1364 && GET_MODE (sparc_compare_op0) == DImode)
1366 emit_v9_brxx_insn (LE, sparc_compare_op0, operands[0]);
1369 else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
1371 sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, LE);
1372 emit_jump_insn (gen_bne (operands[0]));
1375 operands[1] = gen_compare_reg (LE, sparc_compare_op0, sparc_compare_op1);
1378 (define_expand "bleu"
1380 (if_then_else (leu (match_dup 1) (const_int 0))
1381 (label_ref (match_operand 0 "" ""))
1385 operands[1] = gen_compare_reg (LEU, sparc_compare_op0, sparc_compare_op1);
1388 (define_expand "bunordered"
1390 (if_then_else (unordered (match_dup 1) (const_int 0))
1391 (label_ref (match_operand 0 "" ""))
1395 if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
1397 sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1,
1399 emit_jump_insn (gen_beq (operands[0]));
1402 operands[1] = gen_compare_reg (UNORDERED, sparc_compare_op0,
1406 (define_expand "bordered"
1408 (if_then_else (ordered (match_dup 1) (const_int 0))
1409 (label_ref (match_operand 0 "" ""))
1413 if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
1415 sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, ORDERED);
1416 emit_jump_insn (gen_bne (operands[0]));
1419 operands[1] = gen_compare_reg (ORDERED, sparc_compare_op0,
1423 (define_expand "bungt"
1425 (if_then_else (ungt (match_dup 1) (const_int 0))
1426 (label_ref (match_operand 0 "" ""))
1430 if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
1432 sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, UNGT);
1433 emit_jump_insn (gen_bgt (operands[0]));
1436 operands[1] = gen_compare_reg (UNGT, sparc_compare_op0, sparc_compare_op1);
1439 (define_expand "bunlt"
1441 (if_then_else (unlt (match_dup 1) (const_int 0))
1442 (label_ref (match_operand 0 "" ""))
1446 if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
1448 sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, UNLT);
1449 emit_jump_insn (gen_bne (operands[0]));
1452 operands[1] = gen_compare_reg (UNLT, sparc_compare_op0, sparc_compare_op1);
1455 (define_expand "buneq"
1457 (if_then_else (uneq (match_dup 1) (const_int 0))
1458 (label_ref (match_operand 0 "" ""))
1462 if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
1464 sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, UNEQ);
1465 emit_jump_insn (gen_beq (operands[0]));
1468 operands[1] = gen_compare_reg (UNEQ, sparc_compare_op0, sparc_compare_op1);
1471 (define_expand "bunge"
1473 (if_then_else (unge (match_dup 1) (const_int 0))
1474 (label_ref (match_operand 0 "" ""))
1478 if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
1480 sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, UNGE);
1481 emit_jump_insn (gen_bne (operands[0]));
1484 operands[1] = gen_compare_reg (UNGE, sparc_compare_op0, sparc_compare_op1);
1487 (define_expand "bunle"
1489 (if_then_else (unle (match_dup 1) (const_int 0))
1490 (label_ref (match_operand 0 "" ""))
1494 if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
1496 sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, UNLE);
1497 emit_jump_insn (gen_bne (operands[0]));
1500 operands[1] = gen_compare_reg (UNLE, sparc_compare_op0, sparc_compare_op1);
1503 (define_expand "bltgt"
1505 (if_then_else (ltgt (match_dup 1) (const_int 0))
1506 (label_ref (match_operand 0 "" ""))
1510 if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
1512 sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, LTGT);
1513 emit_jump_insn (gen_bne (operands[0]));
1516 operands[1] = gen_compare_reg (LTGT, sparc_compare_op0, sparc_compare_op1);
1519 ;; Now match both normal and inverted jump.
1521 ;; XXX fpcmp nop braindamage
1522 (define_insn "*normal_branch"
1524 (if_then_else (match_operator 0 "noov_compare_op"
1525 [(reg 100) (const_int 0)])
1526 (label_ref (match_operand 1 "" ""))
1530 return output_cbranch (operands[0], operands[1], 1, 0,
1531 final_sequence && INSN_ANNULLED_BRANCH_P (insn),
1532 ! final_sequence, insn);
1534 [(set_attr "type" "branch")
1535 (set_attr "branch_type" "icc")])
1537 ;; XXX fpcmp nop braindamage
1538 (define_insn "*inverted_branch"
1540 (if_then_else (match_operator 0 "noov_compare_op"
1541 [(reg 100) (const_int 0)])
1543 (label_ref (match_operand 1 "" ""))))]
1546 return output_cbranch (operands[0], operands[1], 1, 1,
1547 final_sequence && INSN_ANNULLED_BRANCH_P (insn),
1548 ! final_sequence, insn);
1550 [(set_attr "type" "branch")
1551 (set_attr "branch_type" "icc")])
1553 ;; XXX fpcmp nop braindamage
1554 (define_insn "*normal_fp_branch"
1556 (if_then_else (match_operator 1 "comparison_operator"
1557 [(match_operand:CCFP 0 "fcc_reg_operand" "c")
1559 (label_ref (match_operand 2 "" ""))
1563 return output_cbranch (operands[1], operands[2], 2, 0,
1564 final_sequence && INSN_ANNULLED_BRANCH_P (insn),
1565 ! final_sequence, insn);
1567 [(set_attr "type" "branch")
1568 (set_attr "branch_type" "fcc")])
1570 ;; XXX fpcmp nop braindamage
1571 (define_insn "*inverted_fp_branch"
1573 (if_then_else (match_operator 1 "comparison_operator"
1574 [(match_operand:CCFP 0 "fcc_reg_operand" "c")
1577 (label_ref (match_operand 2 "" ""))))]
1580 return output_cbranch (operands[1], operands[2], 2, 1,
1581 final_sequence && INSN_ANNULLED_BRANCH_P (insn),
1582 ! final_sequence, insn);
1584 [(set_attr "type" "branch")
1585 (set_attr "branch_type" "fcc")])
1587 ;; XXX fpcmp nop braindamage
1588 (define_insn "*normal_fpe_branch"
1590 (if_then_else (match_operator 1 "comparison_operator"
1591 [(match_operand:CCFPE 0 "fcc_reg_operand" "c")
1593 (label_ref (match_operand 2 "" ""))
1597 return output_cbranch (operands[1], operands[2], 2, 0,
1598 final_sequence && INSN_ANNULLED_BRANCH_P (insn),
1599 ! final_sequence, insn);
1601 [(set_attr "type" "branch")
1602 (set_attr "branch_type" "fcc")])
1604 ;; XXX fpcmp nop braindamage
1605 (define_insn "*inverted_fpe_branch"
1607 (if_then_else (match_operator 1 "comparison_operator"
1608 [(match_operand:CCFPE 0 "fcc_reg_operand" "c")
1611 (label_ref (match_operand 2 "" ""))))]
1614 return output_cbranch (operands[1], operands[2], 2, 1,
1615 final_sequence && INSN_ANNULLED_BRANCH_P (insn),
1616 ! final_sequence, insn);
1618 [(set_attr "type" "branch")
1619 (set_attr "branch_type" "fcc")])
1621 ;; SPARC V9-specific jump insns. None of these are guaranteed to be
1622 ;; in the architecture.
1624 ;; There are no 32 bit brreg insns.
1627 (define_insn "*normal_int_branch_sp64"
1629 (if_then_else (match_operator 0 "v9_regcmp_op"
1630 [(match_operand:DI 1 "register_operand" "r")
1632 (label_ref (match_operand 2 "" ""))
1636 return output_v9branch (operands[0], operands[2], 1, 2, 0,
1637 final_sequence && INSN_ANNULLED_BRANCH_P (insn),
1638 ! final_sequence, insn);
1640 [(set_attr "type" "branch")
1641 (set_attr "branch_type" "reg")])
1644 (define_insn "*inverted_int_branch_sp64"
1646 (if_then_else (match_operator 0 "v9_regcmp_op"
1647 [(match_operand:DI 1 "register_operand" "r")
1650 (label_ref (match_operand 2 "" ""))))]
1653 return output_v9branch (operands[0], operands[2], 1, 2, 1,
1654 final_sequence && INSN_ANNULLED_BRANCH_P (insn),
1655 ! final_sequence, insn);
1657 [(set_attr "type" "branch")
1658 (set_attr "branch_type" "reg")])
1660 ;; Load program counter insns.
1662 (define_insn "get_pc"
1663 [(clobber (reg:SI 15))
1664 (set (match_operand 0 "register_operand" "=r")
1665 (unspec [(match_operand 1 "" "") (match_operand 2 "" "")] UNSPEC_GET_PC))]
1666 "flag_pic && REGNO (operands[0]) == 23"
1667 "sethi\t%%hi(%a1-4), %0\n\tcall\t%a2\n\tadd\t%0, %%lo(%a1+4), %0"
1668 [(set_attr "type" "multi")
1669 (set_attr "length" "3")])
1672 ;; Move instructions
1674 (define_expand "movqi"
1675 [(set (match_operand:QI 0 "general_operand" "")
1676 (match_operand:QI 1 "general_operand" ""))]
1679 /* Working with CONST_INTs is easier, so convert
1680 a double if needed. */
1681 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1683 operands[1] = GEN_INT (trunc_int_for_mode
1684 (CONST_DOUBLE_LOW (operands[1]), QImode));
1687 /* Handle sets of MEM first. */
1688 if (GET_CODE (operands[0]) == MEM)
1690 if (reg_or_0_operand (operands[1], QImode))
1693 if (! reload_in_progress)
1695 operands[0] = validize_mem (operands[0]);
1696 operands[1] = force_reg (QImode, operands[1]);
1700 /* Fixup TLS cases. */
1701 if (tls_symbolic_operand (operands [1]))
1702 operands[1] = legitimize_tls_address (operands[1]);
1704 /* Fixup PIC cases. */
1707 if (CONSTANT_P (operands[1])
1708 && pic_address_needs_scratch (operands[1]))
1709 operands[1] = legitimize_pic_address (operands[1], QImode, 0);
1711 if (symbolic_operand (operands[1], QImode))
1713 operands[1] = legitimize_pic_address (operands[1],
1715 (reload_in_progress ?
1722 /* All QI constants require only one insn, so proceed. */
1728 (define_insn "*movqi_insn"
1729 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m")
1730 (match_operand:QI 1 "input_operand" "rI,m,rJ"))]
1731 "(register_operand (operands[0], QImode)
1732 || reg_or_0_operand (operands[1], QImode))"
1737 [(set_attr "type" "*,load,store")
1738 (set_attr "us3load_type" "*,3cycle,*")])
1740 (define_expand "movhi"
1741 [(set (match_operand:HI 0 "general_operand" "")
1742 (match_operand:HI 1 "general_operand" ""))]
1745 /* Working with CONST_INTs is easier, so convert
1746 a double if needed. */
1747 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1748 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
1750 /* Handle sets of MEM first. */
1751 if (GET_CODE (operands[0]) == MEM)
1753 if (reg_or_0_operand (operands[1], HImode))
1756 if (! reload_in_progress)
1758 operands[0] = validize_mem (operands[0]);
1759 operands[1] = force_reg (HImode, operands[1]);
1763 /* Fixup TLS cases. */
1764 if (tls_symbolic_operand (operands [1]))
1765 operands[1] = legitimize_tls_address (operands[1]);
1767 /* Fixup PIC cases. */
1770 if (CONSTANT_P (operands[1])
1771 && pic_address_needs_scratch (operands[1]))
1772 operands[1] = legitimize_pic_address (operands[1], HImode, 0);
1774 if (symbolic_operand (operands[1], HImode))
1776 operands[1] = legitimize_pic_address (operands[1],
1778 (reload_in_progress ?
1785 /* This makes sure we will not get rematched due to splittage. */
1786 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], HImode))
1788 else if (CONSTANT_P (operands[1])
1789 && GET_CODE (operands[1]) != HIGH
1790 && GET_CODE (operands[1]) != LO_SUM)
1792 sparc_emit_set_const32 (operands[0], operands[1]);
1799 (define_insn "*movhi_const64_special"
1800 [(set (match_operand:HI 0 "register_operand" "=r")
1801 (match_operand:HI 1 "const64_high_operand" ""))]
1803 "sethi\t%%hi(%a1), %0")
1805 (define_insn "*movhi_insn"
1806 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
1807 (match_operand:HI 1 "input_operand" "rI,K,m,rJ"))]
1808 "(register_operand (operands[0], HImode)
1809 || reg_or_0_operand (operands[1], HImode))"
1812 sethi\t%%hi(%a1), %0
1815 [(set_attr "type" "*,*,load,store")
1816 (set_attr "us3load_type" "*,*,3cycle,*")])
1818 ;; We always work with constants here.
1819 (define_insn "*movhi_lo_sum"
1820 [(set (match_operand:HI 0 "register_operand" "=r")
1821 (ior:HI (match_operand:HI 1 "arith_operand" "%r")
1822 (match_operand:HI 2 "arith_operand" "I")))]
1826 (define_expand "movsi"
1827 [(set (match_operand:SI 0 "general_operand" "")
1828 (match_operand:SI 1 "general_operand" ""))]
1831 /* Working with CONST_INTs is easier, so convert
1832 a double if needed. */
1833 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1834 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
1836 /* Handle sets of MEM first. */
1837 if (GET_CODE (operands[0]) == MEM)
1839 if (reg_or_0_operand (operands[1], SImode))
1842 if (! reload_in_progress)
1844 operands[0] = validize_mem (operands[0]);
1845 operands[1] = force_reg (SImode, operands[1]);
1849 /* Fixup TLS cases. */
1850 if (tls_symbolic_operand (operands [1]))
1851 operands[1] = legitimize_tls_address (operands[1]);
1853 /* Fixup PIC cases. */
1856 if (CONSTANT_P (operands[1])
1857 && pic_address_needs_scratch (operands[1]))
1858 operands[1] = legitimize_pic_address (operands[1], SImode, 0);
1860 if (GET_CODE (operands[1]) == LABEL_REF)
1863 emit_insn (gen_movsi_pic_label_ref (operands[0], operands[1]));
1867 if (symbolic_operand (operands[1], SImode))
1869 operands[1] = legitimize_pic_address (operands[1],
1871 (reload_in_progress ?
1878 /* If we are trying to toss an integer constant into the
1879 FPU registers, force it into memory. */
1880 if (GET_CODE (operands[0]) == REG
1881 && REGNO (operands[0]) >= SPARC_FIRST_FP_REG
1882 && REGNO (operands[0]) <= SPARC_LAST_V9_FP_REG
1883 && CONSTANT_P (operands[1]))
1884 operands[1] = validize_mem (force_const_mem (GET_MODE (operands[0]),
1887 /* This makes sure we will not get rematched due to splittage. */
1888 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], SImode))
1890 else if (CONSTANT_P (operands[1])
1891 && GET_CODE (operands[1]) != HIGH
1892 && GET_CODE (operands[1]) != LO_SUM)
1894 sparc_emit_set_const32 (operands[0], operands[1]);
1901 ;; This is needed to show CSE exactly which bits are set
1902 ;; in a 64-bit register by sethi instructions.
1903 (define_insn "*movsi_const64_special"
1904 [(set (match_operand:SI 0 "register_operand" "=r")
1905 (match_operand:SI 1 "const64_high_operand" ""))]
1907 "sethi\t%%hi(%a1), %0")
1909 (define_insn "*movsi_insn"
1910 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,f,r,r,r,f,m,m,d")
1911 (match_operand:SI 1 "input_operand" "rI,!f,K,J,m,!m,rJ,!f,J"))]
1912 "(register_operand (operands[0], SImode)
1913 || reg_or_0_operand (operands[1], SImode))"
1917 sethi\t%%hi(%a1), %0
1924 [(set_attr "type" "*,fpmove,*,*,load,fpload,store,fpstore,fga")])
1926 (define_insn "*movsi_lo_sum"
1927 [(set (match_operand:SI 0 "register_operand" "=r")
1928 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
1929 (match_operand:SI 2 "immediate_operand" "in")))]
1931 "or\t%1, %%lo(%a2), %0")
1933 (define_insn "*movsi_high"
1934 [(set (match_operand:SI 0 "register_operand" "=r")
1935 (high:SI (match_operand:SI 1 "immediate_operand" "in")))]
1937 "sethi\t%%hi(%a1), %0")
1939 ;; The next two patterns must wrap the SYMBOL_REF in an UNSPEC
1940 ;; so that CSE won't optimize the address computation away.
1941 (define_insn "movsi_lo_sum_pic"
1942 [(set (match_operand:SI 0 "register_operand" "=r")
1943 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
1944 (unspec:SI [(match_operand:SI 2 "immediate_operand" "in")] UNSPEC_MOVE_PIC)))]
1946 "or\t%1, %%lo(%a2), %0")
1948 (define_insn "movsi_high_pic"
1949 [(set (match_operand:SI 0 "register_operand" "=r")
1950 (high:SI (unspec:SI [(match_operand 1 "" "")] UNSPEC_MOVE_PIC)))]
1951 "flag_pic && check_pic (1)"
1952 "sethi\t%%hi(%a1), %0")
1954 (define_expand "movsi_pic_label_ref"
1955 [(set (match_dup 3) (high:SI
1956 (unspec:SI [(match_operand:SI 1 "label_ref_operand" "")
1957 (match_dup 2)] UNSPEC_MOVE_PIC_LABEL)))
1958 (set (match_dup 4) (lo_sum:SI (match_dup 3)
1959 (unspec:SI [(match_dup 1) (match_dup 2)] UNSPEC_MOVE_PIC_LABEL)))
1960 (set (match_operand:SI 0 "register_operand" "=r")
1961 (minus:SI (match_dup 5) (match_dup 4)))]
1964 current_function_uses_pic_offset_table = 1;
1965 operands[2] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
1968 operands[3] = operands[0];
1969 operands[4] = operands[0];
1973 operands[3] = gen_reg_rtx (SImode);
1974 operands[4] = gen_reg_rtx (SImode);
1976 operands[5] = pic_offset_table_rtx;
1979 (define_insn "*movsi_high_pic_label_ref"
1980 [(set (match_operand:SI 0 "register_operand" "=r")
1982 (unspec:SI [(match_operand:SI 1 "label_ref_operand" "")
1983 (match_operand:SI 2 "" "")] UNSPEC_MOVE_PIC_LABEL)))]
1985 "sethi\t%%hi(%a2-(%a1-.)), %0")
1987 (define_insn "*movsi_lo_sum_pic_label_ref"
1988 [(set (match_operand:SI 0 "register_operand" "=r")
1989 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
1990 (unspec:SI [(match_operand:SI 2 "label_ref_operand" "")
1991 (match_operand:SI 3 "" "")] UNSPEC_MOVE_PIC_LABEL)))]
1993 "or\t%1, %%lo(%a3-(%a2-.)), %0")
1995 (define_expand "movdi"
1996 [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" "")
1997 (match_operand:DI 1 "general_operand" ""))]
2000 /* Where possible, convert CONST_DOUBLE into a CONST_INT. */
2001 if (GET_CODE (operands[1]) == CONST_DOUBLE
2002 #if HOST_BITS_PER_WIDE_INT == 32
2003 && ((CONST_DOUBLE_HIGH (operands[1]) == 0
2004 && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) == 0)
2005 || (CONST_DOUBLE_HIGH (operands[1]) == (HOST_WIDE_INT) 0xffffffff
2006 && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) != 0))
2009 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
2011 /* Handle MEM cases first. */
2012 if (GET_CODE (operands[0]) == MEM)
2014 /* If it's a REG, we can always do it.
2015 The const zero case is more complex, on v9
2016 we can always perform it. */
2017 if (register_operand (operands[1], DImode)
2019 && (operands[1] == const0_rtx)))
2022 if (! reload_in_progress)
2024 operands[0] = validize_mem (operands[0]);
2025 operands[1] = force_reg (DImode, operands[1]);
2029 /* Fixup TLS cases. */
2030 if (tls_symbolic_operand (operands [1]))
2031 operands[1] = legitimize_tls_address (operands[1]);
2035 if (CONSTANT_P (operands[1])
2036 && pic_address_needs_scratch (operands[1]))
2037 operands[1] = legitimize_pic_address (operands[1], DImode, 0);
2039 if (GET_CODE (operands[1]) == LABEL_REF)
2041 if (! TARGET_ARCH64)
2043 emit_insn (gen_movdi_pic_label_ref (operands[0], operands[1]));
2047 if (symbolic_operand (operands[1], DImode))
2049 operands[1] = legitimize_pic_address (operands[1],
2051 (reload_in_progress ?
2058 /* If we are trying to toss an integer constant into the
2059 FPU registers, force it into memory. */
2060 if (GET_CODE (operands[0]) == REG
2061 && REGNO (operands[0]) >= SPARC_FIRST_FP_REG
2062 && REGNO (operands[0]) <= SPARC_LAST_V9_FP_REG
2063 && CONSTANT_P (operands[1]))
2064 operands[1] = validize_mem (force_const_mem (GET_MODE (operands[0]),
2067 /* This makes sure we will not get rematched due to splittage. */
2068 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], DImode))
2070 else if (TARGET_ARCH64
2071 && CONSTANT_P (operands[1])
2072 && GET_CODE (operands[1]) != HIGH
2073 && GET_CODE (operands[1]) != LO_SUM)
2075 sparc_emit_set_const64 (operands[0], operands[1]);
2083 ;; Be careful, fmovd does not exist when !v9.
2084 ;; We match MEM moves directly when we have correct even
2085 ;; numbered registers, but fall into splits otherwise.
2086 ;; The constraint ordering here is really important to
2087 ;; avoid insane problems in reload, especially for patterns
2090 ;; (set (mem:DI (plus:SI (reg:SI 30 %fp)
2091 ;; (const_int -5016)))
2095 (define_insn "*movdi_insn_sp32_v9"
2096 [(set (match_operand:DI 0 "nonimmediate_operand"
2097 "=T,o,T,U,o,r,r,r,?T,?f,?f,?o,?e,?e,?W")
2098 (match_operand:DI 1 "input_operand"
2099 " J,J,U,T,r,o,i,r, f, T, o, f, e, W, e"))]
2100 "! TARGET_ARCH64 && TARGET_V9
2101 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
2118 [(set_attr "type" "store,store,store,load,*,*,*,*,fpstore,fpload,*,*,fpmove,fpload,fpstore")
2119 (set_attr "length" "*,2,*,*,2,2,2,2,*,*,2,2,*,*,*")
2120 (set_attr "fptype" "*,*,*,*,*,*,*,*,*,*,*,*,double,*,*")])
2122 (define_insn "*movdi_insn_sp32"
2123 [(set (match_operand:DI 0 "nonimmediate_operand"
2124 "=o,T,U,o,r,r,r,?T,?f,?f,?o,?f")
2125 (match_operand:DI 1 "input_operand"
2126 " J,U,T,r,o,i,r, f, T, o, f, f"))]
2128 && (register_operand (operands[0], DImode)
2129 || register_operand (operands[1], DImode))"
2143 [(set_attr "type" "store,store,load,*,*,*,*,fpstore,fpload,*,*,*")
2144 (set_attr "length" "2,*,*,2,2,2,2,*,*,2,2,2")])
2146 ;; The following are generated by sparc_emit_set_const64
2147 (define_insn "*movdi_sp64_dbl"
2148 [(set (match_operand:DI 0 "register_operand" "=r")
2149 (match_operand:DI 1 "const64_operand" ""))]
2151 && HOST_BITS_PER_WIDE_INT != 64)"
2154 ;; This is needed to show CSE exactly which bits are set
2155 ;; in a 64-bit register by sethi instructions.
2156 (define_insn "*movdi_const64_special"
2157 [(set (match_operand:DI 0 "register_operand" "=r")
2158 (match_operand:DI 1 "const64_high_operand" ""))]
2160 "sethi\t%%hi(%a1), %0")
2162 (define_insn "*movdi_insn_sp64_novis"
2163 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,m,?e,?e,?W")
2164 (match_operand:DI 1 "input_operand" "rI,N,J,m,rJ,e,W,e"))]
2165 "TARGET_ARCH64 && ! TARGET_VIS
2166 && (register_operand (operands[0], DImode)
2167 || reg_or_0_operand (operands[1], DImode))"
2170 sethi\t%%hi(%a1), %0
2177 [(set_attr "type" "*,*,*,load,store,fpmove,fpload,fpstore")
2178 (set_attr "fptype" "*,*,*,*,*,double,*,*")])
2180 (define_insn "*movdi_insn_sp64_vis"
2181 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,m,?e,?e,?W,b")
2182 (match_operand:DI 1 "input_operand" "rI,N,J,m,rJ,e,W,e,J"))]
2183 "TARGET_ARCH64 && TARGET_VIS &&
2184 (register_operand (operands[0], DImode)
2185 || reg_or_0_operand (operands[1], DImode))"
2188 sethi\t%%hi(%a1), %0
2196 [(set_attr "type" "*,*,*,load,store,fpmove,fpload,fpstore,fga")
2197 (set_attr "fptype" "*,*,*,*,*,double,*,*,double")])
2199 (define_expand "movdi_pic_label_ref"
2200 [(set (match_dup 3) (high:DI
2201 (unspec:DI [(match_operand:DI 1 "label_ref_operand" "")
2202 (match_dup 2)] UNSPEC_MOVE_PIC_LABEL)))
2203 (set (match_dup 4) (lo_sum:DI (match_dup 3)
2204 (unspec:DI [(match_dup 1) (match_dup 2)] UNSPEC_MOVE_PIC_LABEL)))
2205 (set (match_operand:DI 0 "register_operand" "=r")
2206 (minus:DI (match_dup 5) (match_dup 4)))]
2207 "TARGET_ARCH64 && flag_pic"
2209 current_function_uses_pic_offset_table = 1;
2210 operands[2] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2213 operands[3] = operands[0];
2214 operands[4] = operands[0];
2218 operands[3] = gen_reg_rtx (DImode);
2219 operands[4] = gen_reg_rtx (DImode);
2221 operands[5] = pic_offset_table_rtx;
2224 (define_insn "*movdi_high_pic_label_ref"
2225 [(set (match_operand:DI 0 "register_operand" "=r")
2227 (unspec:DI [(match_operand:DI 1 "label_ref_operand" "")
2228 (match_operand:DI 2 "" "")] UNSPEC_MOVE_PIC_LABEL)))]
2229 "TARGET_ARCH64 && flag_pic"
2230 "sethi\t%%hi(%a2-(%a1-.)), %0")
2232 (define_insn "*movdi_lo_sum_pic_label_ref"
2233 [(set (match_operand:DI 0 "register_operand" "=r")
2234 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2235 (unspec:DI [(match_operand:DI 2 "label_ref_operand" "")
2236 (match_operand:DI 3 "" "")] UNSPEC_MOVE_PIC_LABEL)))]
2237 "TARGET_ARCH64 && flag_pic"
2238 "or\t%1, %%lo(%a3-(%a2-.)), %0")
2240 ;; SPARC-v9 code model support insns. See sparc_emit_set_symbolic_const64
2241 ;; in sparc.c to see what is going on here... PIC stuff comes first.
2243 (define_insn "movdi_lo_sum_pic"
2244 [(set (match_operand:DI 0 "register_operand" "=r")
2245 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2246 (unspec:DI [(match_operand:DI 2 "immediate_operand" "in")] UNSPEC_MOVE_PIC)))]
2247 "TARGET_ARCH64 && flag_pic"
2248 "or\t%1, %%lo(%a2), %0")
2250 (define_insn "movdi_high_pic"
2251 [(set (match_operand:DI 0 "register_operand" "=r")
2252 (high:DI (unspec:DI [(match_operand 1 "" "")] UNSPEC_MOVE_PIC)))]
2253 "TARGET_ARCH64 && flag_pic && check_pic (1)"
2254 "sethi\t%%hi(%a1), %0")
2256 (define_insn "*sethi_di_medlow_embmedany_pic"
2257 [(set (match_operand:DI 0 "register_operand" "=r")
2258 (high:DI (match_operand:DI 1 "sp64_medium_pic_operand" "")))]
2259 "(TARGET_CM_MEDLOW || TARGET_CM_EMBMEDANY) && check_pic (1)"
2260 "sethi\t%%hi(%a1), %0")
2262 (define_insn "*sethi_di_medlow"
2263 [(set (match_operand:DI 0 "register_operand" "=r")
2264 (high:DI (match_operand:DI 1 "symbolic_operand" "")))]
2265 "TARGET_CM_MEDLOW && check_pic (1)"
2266 "sethi\t%%hi(%a1), %0")
2268 (define_insn "*losum_di_medlow"
2269 [(set (match_operand:DI 0 "register_operand" "=r")
2270 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2271 (match_operand:DI 2 "symbolic_operand" "")))]
2273 "or\t%1, %%lo(%a2), %0")
2275 (define_insn "seth44"
2276 [(set (match_operand:DI 0 "register_operand" "=r")
2277 (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] UNSPEC_SETH44)))]
2279 "sethi\t%%h44(%a1), %0")
2281 (define_insn "setm44"
2282 [(set (match_operand:DI 0 "register_operand" "=r")
2283 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2284 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] UNSPEC_SETM44)))]
2286 "or\t%1, %%m44(%a2), %0")
2288 (define_insn "setl44"
2289 [(set (match_operand:DI 0 "register_operand" "=r")
2290 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2291 (match_operand:DI 2 "symbolic_operand" "")))]
2293 "or\t%1, %%l44(%a2), %0")
2295 (define_insn "sethh"
2296 [(set (match_operand:DI 0 "register_operand" "=r")
2297 (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] UNSPEC_SETHH)))]
2299 "sethi\t%%hh(%a1), %0")
2301 (define_insn "setlm"
2302 [(set (match_operand:DI 0 "register_operand" "=r")
2303 (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] UNSPEC_SETLM)))]
2305 "sethi\t%%lm(%a1), %0")
2307 (define_insn "sethm"
2308 [(set (match_operand:DI 0 "register_operand" "=r")
2309 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2310 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] UNSPEC_EMB_SETHM)))]
2312 "or\t%1, %%hm(%a2), %0")
2314 (define_insn "setlo"
2315 [(set (match_operand:DI 0 "register_operand" "=r")
2316 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2317 (match_operand:DI 2 "symbolic_operand" "")))]
2319 "or\t%1, %%lo(%a2), %0")
2321 (define_insn "embmedany_sethi"
2322 [(set (match_operand:DI 0 "register_operand" "=r")
2323 (high:DI (unspec:DI [(match_operand:DI 1 "data_segment_operand" "")] UNSPEC_EMB_HISUM)))]
2324 "TARGET_CM_EMBMEDANY && check_pic (1)"
2325 "sethi\t%%hi(%a1), %0")
2327 (define_insn "embmedany_losum"
2328 [(set (match_operand:DI 0 "register_operand" "=r")
2329 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2330 (match_operand:DI 2 "data_segment_operand" "")))]
2331 "TARGET_CM_EMBMEDANY"
2332 "add\t%1, %%lo(%a2), %0")
2334 (define_insn "embmedany_brsum"
2335 [(set (match_operand:DI 0 "register_operand" "=r")
2336 (unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_EMB_HISUM))]
2337 "TARGET_CM_EMBMEDANY"
2340 (define_insn "embmedany_textuhi"
2341 [(set (match_operand:DI 0 "register_operand" "=r")
2342 (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] UNSPEC_EMB_TEXTUHI)))]
2343 "TARGET_CM_EMBMEDANY && check_pic (1)"
2344 "sethi\t%%uhi(%a1), %0")
2346 (define_insn "embmedany_texthi"
2347 [(set (match_operand:DI 0 "register_operand" "=r")
2348 (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] UNSPEC_EMB_TEXTHI)))]
2349 "TARGET_CM_EMBMEDANY && check_pic (1)"
2350 "sethi\t%%hi(%a1), %0")
2352 (define_insn "embmedany_textulo"
2353 [(set (match_operand:DI 0 "register_operand" "=r")
2354 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2355 (unspec:DI [(match_operand:DI 2 "text_segment_operand" "")] UNSPEC_EMB_TEXTULO)))]
2356 "TARGET_CM_EMBMEDANY"
2357 "or\t%1, %%ulo(%a2), %0")
2359 (define_insn "embmedany_textlo"
2360 [(set (match_operand:DI 0 "register_operand" "=r")
2361 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2362 (match_operand:DI 2 "text_segment_operand" "")))]
2363 "TARGET_CM_EMBMEDANY"
2364 "or\t%1, %%lo(%a2), %0")
2366 ;; Now some patterns to help reload out a bit.
2367 (define_expand "reload_indi"
2368 [(parallel [(match_operand:DI 0 "register_operand" "=r")
2369 (match_operand:DI 1 "immediate_operand" "")
2370 (match_operand:TI 2 "register_operand" "=&r")])]
2372 || TARGET_CM_EMBMEDANY)
2375 sparc_emit_set_symbolic_const64 (operands[0], operands[1], operands[2]);
2379 (define_expand "reload_outdi"
2380 [(parallel [(match_operand:DI 0 "register_operand" "=r")
2381 (match_operand:DI 1 "immediate_operand" "")
2382 (match_operand:TI 2 "register_operand" "=&r")])]
2384 || TARGET_CM_EMBMEDANY)
2387 sparc_emit_set_symbolic_const64 (operands[0], operands[1], operands[2]);
2391 ;; Split up putting CONSTs and REGs into DI regs when !arch64
2393 [(set (match_operand:DI 0 "register_operand" "")
2394 (match_operand:DI 1 "const_int_operand" ""))]
2395 "! TARGET_ARCH64 && reload_completed"
2396 [(clobber (const_int 0))]
2398 #if HOST_BITS_PER_WIDE_INT == 32
2399 emit_insn (gen_movsi (gen_highpart (SImode, operands[0]),
2400 (INTVAL (operands[1]) < 0) ?
2403 emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]),
2406 unsigned int low, high;
2408 low = trunc_int_for_mode (INTVAL (operands[1]), SImode);
2409 high = trunc_int_for_mode (INTVAL (operands[1]) >> 32, SImode);
2410 emit_insn (gen_movsi (gen_highpart (SImode, operands[0]), GEN_INT (high)));
2412 /* Slick... but this trick loses if this subreg constant part
2413 can be done in one insn. */
2414 if (low == high && (low & 0x3ff) != 0 && low + 0x1000 >= 0x2000)
2415 emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]),
2416 gen_highpart (SImode, operands[0])));
2418 emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]), GEN_INT (low)));
2424 [(set (match_operand:DI 0 "register_operand" "")
2425 (match_operand:DI 1 "const_double_operand" ""))]
2429 && ((GET_CODE (operands[0]) == REG
2430 && REGNO (operands[0]) < 32)
2431 || (GET_CODE (operands[0]) == SUBREG
2432 && GET_CODE (SUBREG_REG (operands[0])) == REG
2433 && REGNO (SUBREG_REG (operands[0])) < 32))))"
2434 [(clobber (const_int 0))]
2436 emit_insn (gen_movsi (gen_highpart (SImode, operands[0]),
2437 GEN_INT (CONST_DOUBLE_HIGH (operands[1]))));
2439 /* Slick... but this trick loses if this subreg constant part
2440 can be done in one insn. */
2441 if (CONST_DOUBLE_LOW (operands[1]) == CONST_DOUBLE_HIGH (operands[1])
2442 && !(SPARC_SETHI32_P (CONST_DOUBLE_HIGH (operands[1]))
2443 || SPARC_SIMM13_P (CONST_DOUBLE_HIGH (operands[1]))))
2445 emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]),
2446 gen_highpart (SImode, operands[0])));
2450 emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]),
2451 GEN_INT (CONST_DOUBLE_LOW (operands[1]))));
2457 [(set (match_operand:DI 0 "register_operand" "")
2458 (match_operand:DI 1 "register_operand" ""))]
2462 && ((GET_CODE (operands[0]) == REG
2463 && REGNO (operands[0]) < 32)
2464 || (GET_CODE (operands[0]) == SUBREG
2465 && GET_CODE (SUBREG_REG (operands[0])) == REG
2466 && REGNO (SUBREG_REG (operands[0])) < 32))))"
2467 [(clobber (const_int 0))]
2469 rtx set_dest = operands[0];
2470 rtx set_src = operands[1];
2474 dest1 = gen_highpart (SImode, set_dest);
2475 dest2 = gen_lowpart (SImode, set_dest);
2476 src1 = gen_highpart (SImode, set_src);
2477 src2 = gen_lowpart (SImode, set_src);
2479 /* Now emit using the real source and destination we found, swapping
2480 the order if we detect overlap. */
2481 if (reg_overlap_mentioned_p (dest1, src2))
2483 emit_insn (gen_movsi (dest2, src2));
2484 emit_insn (gen_movsi (dest1, src1));
2488 emit_insn (gen_movsi (dest1, src1));
2489 emit_insn (gen_movsi (dest2, src2));
2494 ;; Now handle the cases of memory moves from/to non-even
2495 ;; DI mode register pairs.
2497 [(set (match_operand:DI 0 "register_operand" "")
2498 (match_operand:DI 1 "memory_operand" ""))]
2501 && sparc_splitdi_legitimate (operands[0], operands[1]))"
2502 [(clobber (const_int 0))]
2504 rtx word0 = adjust_address (operands[1], SImode, 0);
2505 rtx word1 = adjust_address (operands[1], SImode, 4);
2506 rtx high_part = gen_highpart (SImode, operands[0]);
2507 rtx low_part = gen_lowpart (SImode, operands[0]);
2509 if (reg_overlap_mentioned_p (high_part, word1))
2511 emit_insn (gen_movsi (low_part, word1));
2512 emit_insn (gen_movsi (high_part, word0));
2516 emit_insn (gen_movsi (high_part, word0));
2517 emit_insn (gen_movsi (low_part, word1));
2523 [(set (match_operand:DI 0 "memory_operand" "")
2524 (match_operand:DI 1 "register_operand" ""))]
2527 && sparc_splitdi_legitimate (operands[1], operands[0]))"
2528 [(clobber (const_int 0))]
2530 emit_insn (gen_movsi (adjust_address (operands[0], SImode, 0),
2531 gen_highpart (SImode, operands[1])));
2532 emit_insn (gen_movsi (adjust_address (operands[0], SImode, 4),
2533 gen_lowpart (SImode, operands[1])));
2538 [(set (match_operand:DI 0 "memory_operand" "")
2543 && ! mem_min_alignment (operands[0], 8)))
2544 && offsettable_memref_p (operands[0])"
2545 [(clobber (const_int 0))]
2547 emit_insn (gen_movsi (adjust_address (operands[0], SImode, 0), const0_rtx));
2548 emit_insn (gen_movsi (adjust_address (operands[0], SImode, 4), const0_rtx));
2552 ;; Floating point move insns
2554 (define_insn "*movsf_insn_novis"
2555 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,*r,*r,*r,*r,*r,f,m,m")
2556 (match_operand:SF 1 "input_operand" "f,G,Q,*rR,S,m,m,f,*rG"))]
2557 "(TARGET_FPU && ! TARGET_VIS)
2558 && (register_operand (operands[0], SFmode)
2559 || register_operand (operands[1], SFmode)
2560 || fp_zero_operand (operands[1], SFmode))"
2562 if (GET_CODE (operands[1]) == CONST_DOUBLE
2563 && (which_alternative == 2
2564 || which_alternative == 3
2565 || which_alternative == 4))
2570 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
2571 REAL_VALUE_TO_TARGET_SINGLE (r, i);
2572 operands[1] = GEN_INT (i);
2575 switch (which_alternative)
2578 return "fmovs\t%1, %0";
2582 return "sethi\t%%hi(%a1), %0";
2584 return "mov\t%1, %0";
2589 return "ld\t%1, %0";
2592 return "st\t%r1, %0";
2597 [(set_attr "type" "fpmove,*,*,*,*,load,fpload,fpstore,store")])
2599 (define_insn "*movsf_insn_vis"
2600 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,*r,*r,*r,f,m,m")
2601 (match_operand:SF 1 "input_operand" "f,G,G,Q,*rR,S,m,m,f,*rG"))]
2602 "(TARGET_FPU && TARGET_VIS)
2603 && (register_operand (operands[0], SFmode)
2604 || register_operand (operands[1], SFmode)
2605 || fp_zero_operand (operands[1], SFmode))"
2607 if (GET_CODE (operands[1]) == CONST_DOUBLE
2608 && (which_alternative == 3
2609 || which_alternative == 4
2610 || which_alternative == 5))
2615 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
2616 REAL_VALUE_TO_TARGET_SINGLE (r, i);
2617 operands[1] = GEN_INT (i);
2620 switch (which_alternative)
2623 return "fmovs\t%1, %0";
2625 return "fzeros\t%0";
2629 return "sethi\t%%hi(%a1), %0";
2631 return "mov\t%1, %0";
2636 return "ld\t%1, %0";
2639 return "st\t%r1, %0";
2644 [(set_attr "type" "fpmove,fga,*,*,*,*,load,fpload,fpstore,store")])
2646 ;; Exactly the same as above, except that all `f' cases are deleted.
2647 ;; This is necessary to prevent reload from ever trying to use a `f' reg
2650 (define_insn "*movsf_no_f_insn"
2651 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,r,r,r,m")
2652 (match_operand:SF 1 "input_operand" "G,Q,rR,S,m,rG"))]
2654 && (register_operand (operands[0], SFmode)
2655 || register_operand (operands[1], SFmode)
2656 || fp_zero_operand (operands[1], SFmode))"
2658 if (GET_CODE (operands[1]) == CONST_DOUBLE
2659 && (which_alternative == 1
2660 || which_alternative == 2
2661 || which_alternative == 3))
2666 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
2667 REAL_VALUE_TO_TARGET_SINGLE (r, i);
2668 operands[1] = GEN_INT (i);
2671 switch (which_alternative)
2676 return "sethi\t%%hi(%a1), %0";
2678 return "mov\t%1, %0";
2682 return "ld\t%1, %0";
2684 return "st\t%r1, %0";
2689 [(set_attr "type" "*,*,*,*,load,store")])
2691 (define_insn "*movsf_lo_sum"
2692 [(set (match_operand:SF 0 "register_operand" "=r")
2693 (lo_sum:SF (match_operand:SF 1 "register_operand" "r")
2694 (match_operand:SF 2 "const_double_operand" "S")))]
2695 "fp_high_losum_p (operands[2])"
2700 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[2]);
2701 REAL_VALUE_TO_TARGET_SINGLE (r, i);
2702 operands[2] = GEN_INT (i);
2703 return "or\t%1, %%lo(%a2), %0";
2706 (define_insn "*movsf_high"
2707 [(set (match_operand:SF 0 "register_operand" "=r")
2708 (high:SF (match_operand:SF 1 "const_double_operand" "S")))]
2709 "fp_high_losum_p (operands[1])"
2714 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
2715 REAL_VALUE_TO_TARGET_SINGLE (r, i);
2716 operands[1] = GEN_INT (i);
2717 return "sethi\t%%hi(%1), %0";
2721 [(set (match_operand:SF 0 "register_operand" "")
2722 (match_operand:SF 1 "const_double_operand" ""))]
2723 "fp_high_losum_p (operands[1])
2724 && (GET_CODE (operands[0]) == REG
2725 && REGNO (operands[0]) < 32)"
2726 [(set (match_dup 0) (high:SF (match_dup 1)))
2727 (set (match_dup 0) (lo_sum:SF (match_dup 0) (match_dup 1)))])
2729 (define_expand "movsf"
2730 [(set (match_operand:SF 0 "general_operand" "")
2731 (match_operand:SF 1 "general_operand" ""))]
2734 /* Force SFmode constants into memory. */
2735 if (GET_CODE (operands[0]) == REG
2736 && CONSTANT_P (operands[1]))
2738 /* emit_group_store will send such bogosity to us when it is
2739 not storing directly into memory. So fix this up to avoid
2740 crashes in output_constant_pool. */
2741 if (operands [1] == const0_rtx)
2742 operands[1] = CONST0_RTX (SFmode);
2744 if (TARGET_VIS && fp_zero_operand (operands[1], SFmode))
2747 /* We are able to build any SF constant in integer registers
2748 with at most 2 instructions. */
2749 if (REGNO (operands[0]) < 32)
2752 operands[1] = validize_mem (force_const_mem (GET_MODE (operands[0]),
2756 /* Handle sets of MEM first. */
2757 if (GET_CODE (operands[0]) == MEM)
2759 if (register_operand (operands[1], SFmode)
2760 || fp_zero_operand (operands[1], SFmode))
2763 if (! reload_in_progress)
2765 operands[0] = validize_mem (operands[0]);
2766 operands[1] = force_reg (SFmode, operands[1]);
2770 /* Fixup PIC cases. */
2773 if (CONSTANT_P (operands[1])
2774 && pic_address_needs_scratch (operands[1]))
2775 operands[1] = legitimize_pic_address (operands[1], SFmode, 0);
2777 if (symbolic_operand (operands[1], SFmode))
2779 operands[1] = legitimize_pic_address (operands[1],
2781 (reload_in_progress ?
2791 (define_expand "movdf"
2792 [(set (match_operand:DF 0 "general_operand" "")
2793 (match_operand:DF 1 "general_operand" ""))]
2796 /* Force DFmode constants into memory. */
2797 if (GET_CODE (operands[0]) == REG
2798 && CONSTANT_P (operands[1]))
2800 /* emit_group_store will send such bogosity to us when it is
2801 not storing directly into memory. So fix this up to avoid
2802 crashes in output_constant_pool. */
2803 if (operands [1] == const0_rtx)
2804 operands[1] = CONST0_RTX (DFmode);
2806 if ((TARGET_VIS || REGNO (operands[0]) < 32)
2807 && fp_zero_operand (operands[1], DFmode))
2810 /* We are able to build any DF constant in integer registers. */
2811 if (REGNO (operands[0]) < 32
2812 && (reload_completed || reload_in_progress))
2815 operands[1] = validize_mem (force_const_mem (GET_MODE (operands[0]),
2819 /* Handle MEM cases first. */
2820 if (GET_CODE (operands[0]) == MEM)
2822 if (register_operand (operands[1], DFmode)
2823 || fp_zero_operand (operands[1], DFmode))
2826 if (! reload_in_progress)
2828 operands[0] = validize_mem (operands[0]);
2829 operands[1] = force_reg (DFmode, operands[1]);
2833 /* Fixup PIC cases. */
2836 if (CONSTANT_P (operands[1])
2837 && pic_address_needs_scratch (operands[1]))
2838 operands[1] = legitimize_pic_address (operands[1], DFmode, 0);
2840 if (symbolic_operand (operands[1], DFmode))
2842 operands[1] = legitimize_pic_address (operands[1],
2844 (reload_in_progress ?
2854 ;; Be careful, fmovd does not exist when !v9.
2855 (define_insn "*movdf_insn_sp32"
2856 [(set (match_operand:DF 0 "nonimmediate_operand" "=e,W,U,T,o,e,*r,o,e,o")
2857 (match_operand:DF 1 "input_operand" "W#F,e,T,U,G,e,*rFo,*r,o#F,e"))]
2860 && (register_operand (operands[0], DFmode)
2861 || register_operand (operands[1], DFmode)
2862 || fp_zero_operand (operands[1], DFmode))"
2874 [(set_attr "type" "fpload,fpstore,load,store,*,*,*,*,*,*")
2875 (set_attr "length" "*,*,*,*,2,2,2,2,2,2")])
2877 (define_insn "*movdf_no_e_insn_sp32"
2878 [(set (match_operand:DF 0 "nonimmediate_operand" "=U,T,o,r,o")
2879 (match_operand:DF 1 "input_operand" "T,U,G,ro,r"))]
2883 && (register_operand (operands[0], DFmode)
2884 || register_operand (operands[1], DFmode)
2885 || fp_zero_operand (operands[1], DFmode))"
2892 [(set_attr "type" "load,store,*,*,*")
2893 (set_attr "length" "*,*,2,2,2")])
2895 (define_insn "*movdf_no_e_insn_v9_sp32"
2896 [(set (match_operand:DF 0 "nonimmediate_operand" "=U,T,T,r,o")
2897 (match_operand:DF 1 "input_operand" "T,U,G,ro,rG"))]
2901 && (register_operand (operands[0], DFmode)
2902 || register_operand (operands[1], DFmode)
2903 || fp_zero_operand (operands[1], DFmode))"
2910 [(set_attr "type" "load,store,store,*,*")
2911 (set_attr "length" "*,*,*,2,2")])
2913 ;; We have available v9 double floats but not 64-bit
2914 ;; integer registers and no VIS.
2915 (define_insn "*movdf_insn_v9only_novis"
2916 [(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,T,W,U,T,f,*r,o")
2917 (match_operand:DF 1 "input_operand" "e,W#F,G,e,T,U,o#F,*roF,*rGf"))]
2922 && (register_operand (operands[0], DFmode)
2923 || register_operand (operands[1], DFmode)
2924 || fp_zero_operand (operands[1], DFmode))"
2935 [(set_attr "type" "fpmove,load,store,store,load,store,*,*,*")
2936 (set_attr "length" "*,*,*,*,*,*,2,2,2")
2937 (set_attr "fptype" "double,*,*,*,*,*,*,*,*")])
2939 ;; We have available v9 double floats but not 64-bit
2940 ;; integer registers but we have VIS.
2941 (define_insn "*movdf_insn_v9only_vis"
2942 [(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,e,T,W,U,T,f,*r,o")
2943 (match_operand:DF 1 "input_operand" "G,e,W#F,G,e,T,U,o#F,*roGF,*rGf"))]
2947 && (register_operand (operands[0], DFmode)
2948 || register_operand (operands[1], DFmode)
2949 || fp_zero_operand (operands[1], DFmode))"
2961 [(set_attr "type" "fga,fpmove,load,store,store,load,store,*,*,*")
2962 (set_attr "length" "*,*,*,*,*,*,*,2,2,2")
2963 (set_attr "fptype" "double,double,*,*,*,*,*,*,*,*")])
2965 ;; We have available both v9 double floats and 64-bit
2966 ;; integer registers. No VIS though.
2967 (define_insn "*movdf_insn_sp64_novis"
2968 [(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,W,*r,*r,m,*r")
2969 (match_operand:DF 1 "input_operand" "e,W#F,e,*rG,m,*rG,F"))]
2973 && (register_operand (operands[0], DFmode)
2974 || register_operand (operands[1], DFmode)
2975 || fp_zero_operand (operands[1], DFmode))"
2984 [(set_attr "type" "fpmove,load,store,*,load,store,*")
2985 (set_attr "length" "*,*,*,*,*,*,2")
2986 (set_attr "fptype" "double,*,*,*,*,*,*")])
2988 ;; We have available both v9 double floats and 64-bit
2989 ;; integer registers. And we have VIS.
2990 (define_insn "*movdf_insn_sp64_vis"
2991 [(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,e,W,*r,*r,m,*r")
2992 (match_operand:DF 1 "input_operand" "G,e,W#F,e,*rG,m,*rG,F"))]
2996 && (register_operand (operands[0], DFmode)
2997 || register_operand (operands[1], DFmode)
2998 || fp_zero_operand (operands[1], DFmode))"
3008 [(set_attr "type" "fga,fpmove,load,store,*,load,store,*")
3009 (set_attr "length" "*,*,*,*,*,*,*,2")
3010 (set_attr "fptype" "double,double,*,*,*,*,*,*")])
3012 (define_insn "*movdf_no_e_insn_sp64"
3013 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
3014 (match_operand:DF 1 "input_operand" "r,m,rG"))]
3017 && (register_operand (operands[0], DFmode)
3018 || register_operand (operands[1], DFmode)
3019 || fp_zero_operand (operands[1], DFmode))"
3024 [(set_attr "type" "*,load,store")])
3027 [(set (match_operand:DF 0 "register_operand" "")
3028 (match_operand:DF 1 "const_double_operand" ""))]
3030 && (GET_CODE (operands[0]) == REG
3031 && REGNO (operands[0]) < 32)
3032 && ! fp_zero_operand(operands[1], DFmode)
3033 && reload_completed"
3034 [(clobber (const_int 0))]
3039 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
3040 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
3041 operands[0] = gen_rtx_raw_REG (DImode, REGNO (operands[0]));
3045 #if HOST_BITS_PER_WIDE_INT == 64
3048 val = ((HOST_WIDE_INT)(unsigned long)l[1] |
3049 ((HOST_WIDE_INT)(unsigned long)l[0] << 32));
3050 emit_insn (gen_movdi (operands[0], GEN_INT (val)));
3052 emit_insn (gen_movdi (operands[0],
3053 immed_double_const (l[1], l[0], DImode)));
3058 emit_insn (gen_movsi (gen_highpart (SImode, operands[0]),
3061 /* Slick... but this trick loses if this subreg constant part
3062 can be done in one insn. */
3064 && !(SPARC_SETHI32_P (l[0])
3065 || SPARC_SIMM13_P (l[0])))
3067 emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]),
3068 gen_highpart (SImode, operands[0])));
3072 emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]),
3079 ;; Ok, now the splits to handle all the multi insn and
3080 ;; mis-aligned memory address cases.
3081 ;; In these splits please take note that we must be
3082 ;; careful when V9 but not ARCH64 because the integer
3083 ;; register DFmode cases must be handled.
3085 [(set (match_operand:DF 0 "register_operand" "")
3086 (match_operand:DF 1 "register_operand" ""))]
3089 && ((GET_CODE (operands[0]) == REG
3090 && REGNO (operands[0]) < 32)
3091 || (GET_CODE (operands[0]) == SUBREG
3092 && GET_CODE (SUBREG_REG (operands[0])) == REG
3093 && REGNO (SUBREG_REG (operands[0])) < 32))))
3094 && reload_completed"
3095 [(clobber (const_int 0))]
3097 rtx set_dest = operands[0];
3098 rtx set_src = operands[1];
3102 dest1 = gen_highpart (SFmode, set_dest);
3103 dest2 = gen_lowpart (SFmode, set_dest);
3104 src1 = gen_highpart (SFmode, set_src);
3105 src2 = gen_lowpart (SFmode, set_src);
3107 /* Now emit using the real source and destination we found, swapping
3108 the order if we detect overlap. */
3109 if (reg_overlap_mentioned_p (dest1, src2))
3111 emit_insn (gen_movsf (dest2, src2));
3112 emit_insn (gen_movsf (dest1, src1));
3116 emit_insn (gen_movsf (dest1, src1));
3117 emit_insn (gen_movsf (dest2, src2));
3123 [(set (match_operand:DF 0 "register_operand" "")
3124 (match_operand:DF 1 "memory_operand" ""))]
3127 && (((REGNO (operands[0]) % 2) != 0)
3128 || ! mem_min_alignment (operands[1], 8))
3129 && offsettable_memref_p (operands[1])"
3130 [(clobber (const_int 0))]
3132 rtx word0 = adjust_address (operands[1], SFmode, 0);
3133 rtx word1 = adjust_address (operands[1], SFmode, 4);
3135 if (reg_overlap_mentioned_p (gen_highpart (SFmode, operands[0]), word1))
3137 emit_insn (gen_movsf (gen_lowpart (SFmode, operands[0]),
3139 emit_insn (gen_movsf (gen_highpart (SFmode, operands[0]),
3144 emit_insn (gen_movsf (gen_highpart (SFmode, operands[0]),
3146 emit_insn (gen_movsf (gen_lowpart (SFmode, operands[0]),
3153 [(set (match_operand:DF 0 "memory_operand" "")
3154 (match_operand:DF 1 "register_operand" ""))]
3157 && (((REGNO (operands[1]) % 2) != 0)
3158 || ! mem_min_alignment (operands[0], 8))
3159 && offsettable_memref_p (operands[0])"
3160 [(clobber (const_int 0))]
3162 rtx word0 = adjust_address (operands[0], SFmode, 0);
3163 rtx word1 = adjust_address (operands[0], SFmode, 4);
3165 emit_insn (gen_movsf (word0,
3166 gen_highpart (SFmode, operands[1])));
3167 emit_insn (gen_movsf (word1,
3168 gen_lowpart (SFmode, operands[1])));
3173 [(set (match_operand:DF 0 "memory_operand" "")
3174 (match_operand:DF 1 "fp_zero_operand" ""))]
3178 && ! mem_min_alignment (operands[0], 8)))
3179 && offsettable_memref_p (operands[0])"
3180 [(clobber (const_int 0))]
3184 dest1 = adjust_address (operands[0], SFmode, 0);
3185 dest2 = adjust_address (operands[0], SFmode, 4);
3187 emit_insn (gen_movsf (dest1, CONST0_RTX (SFmode)));
3188 emit_insn (gen_movsf (dest2, CONST0_RTX (SFmode)));
3193 [(set (match_operand:DF 0 "register_operand" "")
3194 (match_operand:DF 1 "fp_zero_operand" ""))]
3197 && ((GET_CODE (operands[0]) == REG
3198 && REGNO (operands[0]) < 32)
3199 || (GET_CODE (operands[0]) == SUBREG
3200 && GET_CODE (SUBREG_REG (operands[0])) == REG
3201 && REGNO (SUBREG_REG (operands[0])) < 32))"
3202 [(clobber (const_int 0))]
3204 rtx set_dest = operands[0];
3207 dest1 = gen_highpart (SFmode, set_dest);
3208 dest2 = gen_lowpart (SFmode, set_dest);
3209 emit_insn (gen_movsf (dest1, CONST0_RTX (SFmode)));
3210 emit_insn (gen_movsf (dest2, CONST0_RTX (SFmode)));
3214 (define_expand "movtf"
3215 [(set (match_operand:TF 0 "general_operand" "")
3216 (match_operand:TF 1 "general_operand" ""))]
3219 /* Force TFmode constants into memory. */
3220 if (GET_CODE (operands[0]) == REG
3221 && CONSTANT_P (operands[1]))
3223 /* emit_group_store will send such bogosity to us when it is
3224 not storing directly into memory. So fix this up to avoid
3225 crashes in output_constant_pool. */
3226 if (operands [1] == const0_rtx)
3227 operands[1] = CONST0_RTX (TFmode);
3229 if (TARGET_VIS && fp_zero_operand (operands[1], TFmode))
3232 operands[1] = validize_mem (force_const_mem (GET_MODE (operands[0]),
3236 /* Handle MEM cases first, note that only v9 guarantees
3237 full 16-byte alignment for quads. */
3238 if (GET_CODE (operands[0]) == MEM)
3240 if (register_operand (operands[1], TFmode)
3241 || fp_zero_operand (operands[1], TFmode))
3244 if (! reload_in_progress)
3246 operands[0] = validize_mem (operands[0]);
3247 operands[1] = force_reg (TFmode, operands[1]);
3251 /* Fixup PIC cases. */
3254 if (CONSTANT_P (operands[1])
3255 && pic_address_needs_scratch (operands[1]))
3256 operands[1] = legitimize_pic_address (operands[1], TFmode, 0);
3258 if (symbolic_operand (operands[1], TFmode))
3260 operands[1] = legitimize_pic_address (operands[1],
3262 (reload_in_progress ?
3272 ;; Be careful, fmovq and {st,ld}{x,q} do not exist when !arch64 so
3273 ;; we must split them all. :-(
3274 (define_insn "*movtf_insn_sp32"
3275 [(set (match_operand:TF 0 "nonimmediate_operand" "=e,o,U,r")
3276 (match_operand:TF 1 "input_operand" "oe,GeUr,o,roG"))]
3280 && (register_operand (operands[0], TFmode)
3281 || register_operand (operands[1], TFmode)
3282 || fp_zero_operand (operands[1], TFmode))"
3284 [(set_attr "length" "4")])
3286 (define_insn "*movtf_insn_vis_sp32"
3287 [(set (match_operand:TF 0 "nonimmediate_operand" "=e,o,U,r")
3288 (match_operand:TF 1 "input_operand" "Goe,GeUr,o,roG"))]
3292 && (register_operand (operands[0], TFmode)
3293 || register_operand (operands[1], TFmode)
3294 || fp_zero_operand (operands[1], TFmode))"
3296 [(set_attr "length" "4")])
3298 ;; Exactly the same as above, except that all `e' cases are deleted.
3299 ;; This is necessary to prevent reload from ever trying to use a `e' reg
3302 (define_insn "*movtf_no_e_insn_sp32"
3303 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,U,o,r,o")
3304 (match_operand:TF 1 "input_operand" "G,o,U,roG,r"))]
3307 && (register_operand (operands[0], TFmode)
3308 || register_operand (operands[1], TFmode)
3309 || fp_zero_operand (operands[1], TFmode))"
3311 [(set_attr "length" "4")])
3313 ;; Now handle the float reg cases directly when arch64,
3314 ;; hard_quad, and proper reg number alignment are all true.
3315 (define_insn "*movtf_insn_hq_sp64"
3316 [(set (match_operand:TF 0 "nonimmediate_operand" "=e,e,m,o,r")
3317 (match_operand:TF 1 "input_operand" "e,m,e,Gr,roG"))]
3322 && (register_operand (operands[0], TFmode)
3323 || register_operand (operands[1], TFmode)
3324 || fp_zero_operand (operands[1], TFmode))"
3331 [(set_attr "type" "fpmove,fpload,fpstore,*,*")
3332 (set_attr "length" "*,*,*,2,2")])
3334 (define_insn "*movtf_insn_hq_vis_sp64"
3335 [(set (match_operand:TF 0 "nonimmediate_operand" "=e,e,m,eo,r,o")
3336 (match_operand:TF 1 "input_operand" "e,m,e,G,roG,r"))]
3341 && (register_operand (operands[0], TFmode)
3342 || register_operand (operands[1], TFmode)
3343 || fp_zero_operand (operands[1], TFmode))"
3351 [(set_attr "type" "fpmove,fpload,fpstore,*,*,*")
3352 (set_attr "length" "*,*,*,2,2,2")])
3354 ;; Now we allow the integer register cases even when
3355 ;; only arch64 is true.
3356 (define_insn "*movtf_insn_sp64"
3357 [(set (match_operand:TF 0 "nonimmediate_operand" "=e,o,r")
3358 (match_operand:TF 1 "input_operand" "oe,Ger,orG"))]
3362 && ! TARGET_HARD_QUAD
3363 && (register_operand (operands[0], TFmode)
3364 || register_operand (operands[1], TFmode)
3365 || fp_zero_operand (operands[1], TFmode))"
3367 [(set_attr "length" "2")])
3369 (define_insn "*movtf_insn_vis_sp64"
3370 [(set (match_operand:TF 0 "nonimmediate_operand" "=e,o,r")
3371 (match_operand:TF 1 "input_operand" "Goe,Ger,orG"))]
3375 && ! TARGET_HARD_QUAD
3376 && (register_operand (operands[0], TFmode)
3377 || register_operand (operands[1], TFmode)
3378 || fp_zero_operand (operands[1], TFmode))"
3380 [(set_attr "length" "2")])
3382 (define_insn "*movtf_no_e_insn_sp64"
3383 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
3384 (match_operand:TF 1 "input_operand" "orG,rG"))]
3387 && (register_operand (operands[0], TFmode)
3388 || register_operand (operands[1], TFmode)
3389 || fp_zero_operand (operands[1], TFmode))"
3391 [(set_attr "length" "2")])
3393 ;; Now all the splits to handle multi-insn TF mode moves.
3395 [(set (match_operand:TF 0 "register_operand" "")
3396 (match_operand:TF 1 "register_operand" ""))]
3400 && ! TARGET_HARD_QUAD)
3401 || ! fp_register_operand (operands[0], TFmode))"
3402 [(clobber (const_int 0))]
3404 rtx set_dest = operands[0];
3405 rtx set_src = operands[1];
3409 dest1 = gen_df_reg (set_dest, 0);
3410 dest2 = gen_df_reg (set_dest, 1);
3411 src1 = gen_df_reg (set_src, 0);
3412 src2 = gen_df_reg (set_src, 1);
3414 /* Now emit using the real source and destination we found, swapping
3415 the order if we detect overlap. */
3416 if (reg_overlap_mentioned_p (dest1, src2))
3418 emit_insn (gen_movdf (dest2, src2));
3419 emit_insn (gen_movdf (dest1, src1));
3423 emit_insn (gen_movdf (dest1, src1));
3424 emit_insn (gen_movdf (dest2, src2));
3430 [(set (match_operand:TF 0 "nonimmediate_operand" "")
3431 (match_operand:TF 1 "fp_zero_operand" ""))]
3433 [(clobber (const_int 0))]
3435 rtx set_dest = operands[0];
3438 switch (GET_CODE (set_dest))
3441 dest1 = gen_df_reg (set_dest, 0);
3442 dest2 = gen_df_reg (set_dest, 1);
3445 dest1 = adjust_address (set_dest, DFmode, 0);
3446 dest2 = adjust_address (set_dest, DFmode, 8);
3452 emit_insn (gen_movdf (dest1, CONST0_RTX (DFmode)));
3453 emit_insn (gen_movdf (dest2, CONST0_RTX (DFmode)));
3458 [(set (match_operand:TF 0 "register_operand" "")
3459 (match_operand:TF 1 "memory_operand" ""))]
3461 && offsettable_memref_p (operands[1])
3463 || ! TARGET_HARD_QUAD
3464 || ! fp_register_operand (operands[0], TFmode)))"
3465 [(clobber (const_int 0))]
3467 rtx word0 = adjust_address (operands[1], DFmode, 0);
3468 rtx word1 = adjust_address (operands[1], DFmode, 8);
3469 rtx set_dest, dest1, dest2;
3471 set_dest = operands[0];
3473 dest1 = gen_df_reg (set_dest, 0);
3474 dest2 = gen_df_reg (set_dest, 1);
3476 /* Now output, ordering such that we don't clobber any registers
3477 mentioned in the address. */
3478 if (reg_overlap_mentioned_p (dest1, word1))
3481 emit_insn (gen_movdf (dest2, word1));
3482 emit_insn (gen_movdf (dest1, word0));
3486 emit_insn (gen_movdf (dest1, word0));
3487 emit_insn (gen_movdf (dest2, word1));
3493 [(set (match_operand:TF 0 "memory_operand" "")
3494 (match_operand:TF 1 "register_operand" ""))]
3496 && offsettable_memref_p (operands[0])
3498 || ! TARGET_HARD_QUAD
3499 || ! fp_register_operand (operands[1], TFmode)))"
3500 [(clobber (const_int 0))]
3502 rtx set_src = operands[1];
3504 emit_insn (gen_movdf (adjust_address (operands[0], DFmode, 0),
3505 gen_df_reg (set_src, 0)));
3506 emit_insn (gen_movdf (adjust_address (operands[0], DFmode, 8),
3507 gen_df_reg (set_src, 1)));
3511 ;; SPARC V9 conditional move instructions.
3513 ;; We can handle larger constants here for some flavors, but for now we keep
3514 ;; it simple and only allow those constants supported by all flavors.
3515 ;; Note that emit_conditional_move canonicalizes operands 2,3 so that operand
3516 ;; 3 contains the constant if one is present, but we handle either for
3517 ;; generality (sparc.c puts a constant in operand 2).
3519 (define_expand "movqicc"
3520 [(set (match_operand:QI 0 "register_operand" "")
3521 (if_then_else:QI (match_operand 1 "comparison_operator" "")
3522 (match_operand:QI 2 "arith10_operand" "")
3523 (match_operand:QI 3 "arith10_operand" "")))]
3526 enum rtx_code code = GET_CODE (operands[1]);
3528 if (GET_MODE (sparc_compare_op0) == DImode
3532 if (sparc_compare_op1 == const0_rtx
3533 && GET_CODE (sparc_compare_op0) == REG
3534 && GET_MODE (sparc_compare_op0) == DImode
3535 && v9_regcmp_p (code))
3537 operands[1] = gen_rtx_fmt_ee (code, DImode,
3538 sparc_compare_op0, sparc_compare_op1);
3542 rtx cc_reg = gen_compare_reg (code,
3543 sparc_compare_op0, sparc_compare_op1);
3544 operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx);
3548 (define_expand "movhicc"
3549 [(set (match_operand:HI 0 "register_operand" "")
3550 (if_then_else:HI (match_operand 1 "comparison_operator" "")
3551 (match_operand:HI 2 "arith10_operand" "")
3552 (match_operand:HI 3 "arith10_operand" "")))]
3555 enum rtx_code code = GET_CODE (operands[1]);
3557 if (GET_MODE (sparc_compare_op0) == DImode
3561 if (sparc_compare_op1 == const0_rtx
3562 && GET_CODE (sparc_compare_op0) == REG
3563 && GET_MODE (sparc_compare_op0) == DImode
3564 && v9_regcmp_p (code))
3566 operands[1] = gen_rtx_fmt_ee (code, DImode,
3567 sparc_compare_op0, sparc_compare_op1);
3571 rtx cc_reg = gen_compare_reg (code,
3572 sparc_compare_op0, sparc_compare_op1);
3573 operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx);
3577 (define_expand "movsicc"
3578 [(set (match_operand:SI 0 "register_operand" "")
3579 (if_then_else:SI (match_operand 1 "comparison_operator" "")
3580 (match_operand:SI 2 "arith10_operand" "")
3581 (match_operand:SI 3 "arith10_operand" "")))]
3584 enum rtx_code code = GET_CODE (operands[1]);
3585 enum machine_mode op0_mode = GET_MODE (sparc_compare_op0);
3587 if (sparc_compare_op1 == const0_rtx
3588 && GET_CODE (sparc_compare_op0) == REG
3589 && (TARGET_ARCH64 && op0_mode == DImode && v9_regcmp_p (code)))
3591 operands[1] = gen_rtx_fmt_ee (code, op0_mode,
3592 sparc_compare_op0, sparc_compare_op1);
3596 rtx cc_reg = gen_compare_reg (code,
3597 sparc_compare_op0, sparc_compare_op1);
3598 operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg),
3599 cc_reg, const0_rtx);
3603 (define_expand "movdicc"
3604 [(set (match_operand:DI 0 "register_operand" "")
3605 (if_then_else:DI (match_operand 1 "comparison_operator" "")
3606 (match_operand:DI 2 "arith10_double_operand" "")
3607 (match_operand:DI 3 "arith10_double_operand" "")))]
3610 enum rtx_code code = GET_CODE (operands[1]);
3612 if (sparc_compare_op1 == const0_rtx
3613 && GET_CODE (sparc_compare_op0) == REG
3614 && GET_MODE (sparc_compare_op0) == DImode
3615 && v9_regcmp_p (code))
3617 operands[1] = gen_rtx_fmt_ee (code, DImode,
3618 sparc_compare_op0, sparc_compare_op1);
3622 rtx cc_reg = gen_compare_reg (code,
3623 sparc_compare_op0, sparc_compare_op1);
3624 operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg),
3625 cc_reg, const0_rtx);
3629 (define_expand "movsfcc"
3630 [(set (match_operand:SF 0 "register_operand" "")
3631 (if_then_else:SF (match_operand 1 "comparison_operator" "")
3632 (match_operand:SF 2 "register_operand" "")
3633 (match_operand:SF 3 "register_operand" "")))]
3634 "TARGET_V9 && TARGET_FPU"
3636 enum rtx_code code = GET_CODE (operands[1]);
3638 if (GET_MODE (sparc_compare_op0) == DImode
3642 if (sparc_compare_op1 == const0_rtx
3643 && GET_CODE (sparc_compare_op0) == REG
3644 && GET_MODE (sparc_compare_op0) == DImode
3645 && v9_regcmp_p (code))
3647 operands[1] = gen_rtx_fmt_ee (code, DImode,
3648 sparc_compare_op0, sparc_compare_op1);
3652 rtx cc_reg = gen_compare_reg (code,
3653 sparc_compare_op0, sparc_compare_op1);
3654 operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx);
3658 (define_expand "movdfcc"
3659 [(set (match_operand:DF 0 "register_operand" "")
3660 (if_then_else:DF (match_operand 1 "comparison_operator" "")
3661 (match_operand:DF 2 "register_operand" "")
3662 (match_operand:DF 3 "register_operand" "")))]
3663 "TARGET_V9 && TARGET_FPU"
3665 enum rtx_code code = GET_CODE (operands[1]);
3667 if (GET_MODE (sparc_compare_op0) == DImode
3671 if (sparc_compare_op1 == const0_rtx
3672 && GET_CODE (sparc_compare_op0) == REG
3673 && GET_MODE (sparc_compare_op0) == DImode
3674 && v9_regcmp_p (code))
3676 operands[1] = gen_rtx_fmt_ee (code, DImode,
3677 sparc_compare_op0, sparc_compare_op1);
3681 rtx cc_reg = gen_compare_reg (code,
3682 sparc_compare_op0, sparc_compare_op1);
3683 operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx);
3687 (define_expand "movtfcc"
3688 [(set (match_operand:TF 0 "register_operand" "")
3689 (if_then_else:TF (match_operand 1 "comparison_operator" "")
3690 (match_operand:TF 2 "register_operand" "")
3691 (match_operand:TF 3 "register_operand" "")))]
3692 "TARGET_V9 && TARGET_FPU"
3694 enum rtx_code code = GET_CODE (operands[1]);
3696 if (GET_MODE (sparc_compare_op0) == DImode
3700 if (sparc_compare_op1 == const0_rtx
3701 && GET_CODE (sparc_compare_op0) == REG
3702 && GET_MODE (sparc_compare_op0) == DImode
3703 && v9_regcmp_p (code))
3705 operands[1] = gen_rtx_fmt_ee (code, DImode,
3706 sparc_compare_op0, sparc_compare_op1);
3710 rtx cc_reg = gen_compare_reg (code,
3711 sparc_compare_op0, sparc_compare_op1);
3712 operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx);
3716 ;; Conditional move define_insns.
3718 (define_insn "*movqi_cc_sp64"
3719 [(set (match_operand:QI 0 "register_operand" "=r,r")
3720 (if_then_else:QI (match_operator 1 "comparison_operator"
3721 [(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
3723 (match_operand:QI 3 "arith11_operand" "rL,0")
3724 (match_operand:QI 4 "arith11_operand" "0,rL")))]
3728 mov%c1\t%x2, %4, %0"
3729 [(set_attr "type" "cmove")])
3731 (define_insn "*movhi_cc_sp64"
3732 [(set (match_operand:HI 0 "register_operand" "=r,r")
3733 (if_then_else:HI (match_operator 1 "comparison_operator"
3734 [(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
3736 (match_operand:HI 3 "arith11_operand" "rL,0")
3737 (match_operand:HI 4 "arith11_operand" "0,rL")))]
3741 mov%c1\t%x2, %4, %0"
3742 [(set_attr "type" "cmove")])
3744 (define_insn "*movsi_cc_sp64"
3745 [(set (match_operand:SI 0 "register_operand" "=r,r")
3746 (if_then_else:SI (match_operator 1 "comparison_operator"
3747 [(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
3749 (match_operand:SI 3 "arith11_operand" "rL,0")
3750 (match_operand:SI 4 "arith11_operand" "0,rL")))]
3754 mov%c1\t%x2, %4, %0"
3755 [(set_attr "type" "cmove")])
3757 ;; ??? The constraints of operands 3,4 need work.
3758 (define_insn "*movdi_cc_sp64"
3759 [(set (match_operand:DI 0 "register_operand" "=r,r")
3760 (if_then_else:DI (match_operator 1 "comparison_operator"
3761 [(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
3763 (match_operand:DI 3 "arith11_double_operand" "rLH,0")
3764 (match_operand:DI 4 "arith11_double_operand" "0,rLH")))]
3768 mov%c1\t%x2, %4, %0"
3769 [(set_attr "type" "cmove")])
3771 (define_insn "*movdi_cc_sp64_trunc"
3772 [(set (match_operand:SI 0 "register_operand" "=r,r")
3773 (if_then_else:SI (match_operator 1 "comparison_operator"
3774 [(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
3776 (match_operand:SI 3 "arith11_double_operand" "rLH,0")
3777 (match_operand:SI 4 "arith11_double_operand" "0,rLH")))]
3781 mov%c1\t%x2, %4, %0"
3782 [(set_attr "type" "cmove")])
3784 (define_insn "*movsf_cc_sp64"
3785 [(set (match_operand:SF 0 "register_operand" "=f,f")
3786 (if_then_else:SF (match_operator 1 "comparison_operator"
3787 [(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
3789 (match_operand:SF 3 "register_operand" "f,0")
3790 (match_operand:SF 4 "register_operand" "0,f")))]
3791 "TARGET_V9 && TARGET_FPU"
3793 fmovs%C1\t%x2, %3, %0
3794 fmovs%c1\t%x2, %4, %0"
3795 [(set_attr "type" "fpcmove")])
3797 (define_insn "movdf_cc_sp64"
3798 [(set (match_operand:DF 0 "register_operand" "=e,e")
3799 (if_then_else:DF (match_operator 1 "comparison_operator"
3800 [(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
3802 (match_operand:DF 3 "register_operand" "e,0")
3803 (match_operand:DF 4 "register_operand" "0,e")))]
3804 "TARGET_V9 && TARGET_FPU"
3806 fmovd%C1\t%x2, %3, %0
3807 fmovd%c1\t%x2, %4, %0"
3808 [(set_attr "type" "fpcmove")
3809 (set_attr "fptype" "double")])
3811 (define_insn "*movtf_cc_hq_sp64"
3812 [(set (match_operand:TF 0 "register_operand" "=e,e")
3813 (if_then_else:TF (match_operator 1 "comparison_operator"
3814 [(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
3816 (match_operand:TF 3 "register_operand" "e,0")
3817 (match_operand:TF 4 "register_operand" "0,e")))]
3818 "TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD"
3820 fmovq%C1\t%x2, %3, %0
3821 fmovq%c1\t%x2, %4, %0"
3822 [(set_attr "type" "fpcmove")])
3824 (define_insn_and_split "*movtf_cc_sp64"
3825 [(set (match_operand:TF 0 "register_operand" "=e,e")
3826 (if_then_else:TF (match_operator 1 "comparison_operator"
3827 [(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
3829 (match_operand:TF 3 "register_operand" "e,0")
3830 (match_operand:TF 4 "register_operand" "0,e")))]
3831 "TARGET_V9 && TARGET_FPU && !TARGET_HARD_QUAD"
3833 "&& reload_completed"
3834 [(clobber (const_int 0))]
3836 rtx set_dest = operands[0];
3837 rtx set_srca = operands[3];
3838 rtx set_srcb = operands[4];
3839 int third = rtx_equal_p (set_dest, set_srca);
3841 rtx srca1, srca2, srcb1, srcb2;
3843 dest1 = gen_df_reg (set_dest, 0);
3844 dest2 = gen_df_reg (set_dest, 1);
3845 srca1 = gen_df_reg (set_srca, 0);
3846 srca2 = gen_df_reg (set_srca, 1);
3847 srcb1 = gen_df_reg (set_srcb, 0);
3848 srcb2 = gen_df_reg (set_srcb, 1);
3850 /* Now emit using the real source and destination we found, swapping
3851 the order if we detect overlap. */
3852 if ((third && reg_overlap_mentioned_p (dest1, srcb2))
3853 || (!third && reg_overlap_mentioned_p (dest1, srca2)))
3855 emit_insn (gen_movdf_cc_sp64 (dest2, operands[1], operands[2], srca2, srcb2));
3856 emit_insn (gen_movdf_cc_sp64 (dest1, operands[1], operands[2], srca1, srcb1));
3860 emit_insn (gen_movdf_cc_sp64 (dest1, operands[1], operands[2], srca1, srcb1));
3861 emit_insn (gen_movdf_cc_sp64 (dest2, operands[1], operands[2], srca2, srcb2));
3865 [(set_attr "length" "2")])
3867 (define_insn "*movqi_cc_reg_sp64"
3868 [(set (match_operand:QI 0 "register_operand" "=r,r")
3869 (if_then_else:QI (match_operator 1 "v9_regcmp_op"
3870 [(match_operand:DI 2 "register_operand" "r,r")
3872 (match_operand:QI 3 "arith10_operand" "rM,0")
3873 (match_operand:QI 4 "arith10_operand" "0,rM")))]
3876 movr%D1\t%2, %r3, %0
3877 movr%d1\t%2, %r4, %0"
3878 [(set_attr "type" "cmove")])
3880 (define_insn "*movhi_cc_reg_sp64"
3881 [(set (match_operand:HI 0 "register_operand" "=r,r")
3882 (if_then_else:HI (match_operator 1 "v9_regcmp_op"
3883 [(match_operand:DI 2 "register_operand" "r,r")
3885 (match_operand:HI 3 "arith10_operand" "rM,0")
3886 (match_operand:HI 4 "arith10_operand" "0,rM")))]
3889 movr%D1\t%2, %r3, %0
3890 movr%d1\t%2, %r4, %0"
3891 [(set_attr "type" "cmove")])
3893 (define_insn "*movsi_cc_reg_sp64"
3894 [(set (match_operand:SI 0 "register_operand" "=r,r")
3895 (if_then_else:SI (match_operator 1 "v9_regcmp_op"
3896 [(match_operand:DI 2 "register_operand" "r,r")
3898 (match_operand:SI 3 "arith10_operand" "rM,0")
3899 (match_operand:SI 4 "arith10_operand" "0,rM")))]
3902 movr%D1\t%2, %r3, %0
3903 movr%d1\t%2, %r4, %0"
3904 [(set_attr "type" "cmove")])
3906 ;; ??? The constraints of operands 3,4 need work.
3907 (define_insn "*movdi_cc_reg_sp64"
3908 [(set (match_operand:DI 0 "register_operand" "=r,r")
3909 (if_then_else:DI (match_operator 1 "v9_regcmp_op"
3910 [(match_operand:DI 2 "register_operand" "r,r")
3912 (match_operand:DI 3 "arith10_double_operand" "rMH,0")
3913 (match_operand:DI 4 "arith10_double_operand" "0,rMH")))]
3916 movr%D1\t%2, %r3, %0
3917 movr%d1\t%2, %r4, %0"
3918 [(set_attr "type" "cmove")])
3920 (define_insn "*movdi_cc_reg_sp64_trunc"
3921 [(set (match_operand:SI 0 "register_operand" "=r,r")
3922 (if_then_else:SI (match_operator 1 "v9_regcmp_op"
3923 [(match_operand:DI 2 "register_operand" "r,r")
3925 (match_operand:SI 3 "arith10_double_operand" "rMH,0")
3926 (match_operand:SI 4 "arith10_double_operand" "0,rMH")))]
3929 movr%D1\t%2, %r3, %0
3930 movr%d1\t%2, %r4, %0"
3931 [(set_attr "type" "cmove")])
3933 (define_insn "*movsf_cc_reg_sp64"
3934 [(set (match_operand:SF 0 "register_operand" "=f,f")
3935 (if_then_else:SF (match_operator 1 "v9_regcmp_op"
3936 [(match_operand:DI 2 "register_operand" "r,r")
3938 (match_operand:SF 3 "register_operand" "f,0")
3939 (match_operand:SF 4 "register_operand" "0,f")))]
3940 "TARGET_ARCH64 && TARGET_FPU"
3942 fmovrs%D1\t%2, %3, %0
3943 fmovrs%d1\t%2, %4, %0"
3944 [(set_attr "type" "fpcrmove")])
3946 (define_insn "movdf_cc_reg_sp64"
3947 [(set (match_operand:DF 0 "register_operand" "=e,e")
3948 (if_then_else:DF (match_operator 1 "v9_regcmp_op"
3949 [(match_operand:DI 2 "register_operand" "r,r")
3951 (match_operand:DF 3 "register_operand" "e,0")
3952 (match_operand:DF 4 "register_operand" "0,e")))]
3953 "TARGET_ARCH64 && TARGET_FPU"
3955 fmovrd%D1\t%2, %3, %0
3956 fmovrd%d1\t%2, %4, %0"
3957 [(set_attr "type" "fpcrmove")
3958 (set_attr "fptype" "double")])
3960 (define_insn "*movtf_cc_reg_hq_sp64"
3961 [(set (match_operand:TF 0 "register_operand" "=e,e")
3962 (if_then_else:TF (match_operator 1 "v9_regcmp_op"
3963 [(match_operand:DI 2 "register_operand" "r,r")
3965 (match_operand:TF 3 "register_operand" "e,0")
3966 (match_operand:TF 4 "register_operand" "0,e")))]
3967 "TARGET_ARCH64 && TARGET_FPU && TARGET_HARD_QUAD"
3969 fmovrq%D1\t%2, %3, %0
3970 fmovrq%d1\t%2, %4, %0"
3971 [(set_attr "type" "fpcrmove")])
3973 (define_insn_and_split "*movtf_cc_reg_sp64"
3974 [(set (match_operand:TF 0 "register_operand" "=e,e")
3975 (if_then_else:TF (match_operator 1 "v9_regcmp_op"
3976 [(match_operand:DI 2 "register_operand" "r,r")
3978 (match_operand:TF 3 "register_operand" "e,0")
3979 (match_operand:TF 4 "register_operand" "0,e")))]
3980 "TARGET_ARCH64 && TARGET_FPU && ! TARGET_HARD_QUAD"
3982 "&& reload_completed"
3983 [(clobber (const_int 0))]
3985 rtx set_dest = operands[0];
3986 rtx set_srca = operands[3];
3987 rtx set_srcb = operands[4];
3988 int third = rtx_equal_p (set_dest, set_srca);
3990 rtx srca1, srca2, srcb1, srcb2;
3992 dest1 = gen_df_reg (set_dest, 0);
3993 dest2 = gen_df_reg (set_dest, 1);
3994 srca1 = gen_df_reg (set_srca, 0);
3995 srca2 = gen_df_reg (set_srca, 1);
3996 srcb1 = gen_df_reg (set_srcb, 0);
3997 srcb2 = gen_df_reg (set_srcb, 1);
3999 /* Now emit using the real source and destination we found, swapping
4000 the order if we detect overlap. */
4001 if ((third && reg_overlap_mentioned_p (dest1, srcb2))
4002 || (!third && reg_overlap_mentioned_p (dest1, srca2)))
4004 emit_insn (gen_movdf_cc_reg_sp64 (dest2, operands[1], operands[2], srca2, srcb2));
4005 emit_insn (gen_movdf_cc_reg_sp64 (dest1, operands[1], operands[2], srca1, srcb1));
4009 emit_insn (gen_movdf_cc_reg_sp64 (dest1, operands[1], operands[2], srca1, srcb1));
4010 emit_insn (gen_movdf_cc_reg_sp64 (dest2, operands[1], operands[2], srca2, srcb2));
4014 [(set_attr "length" "2")])
4017 ;;- zero extension instructions
4019 ;; These patterns originally accepted general_operands, however, slightly
4020 ;; better code is generated by only accepting register_operands, and then
4021 ;; letting combine generate the ldu[hb] insns.
4023 (define_expand "zero_extendhisi2"
4024 [(set (match_operand:SI 0 "register_operand" "")
4025 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
4028 rtx temp = gen_reg_rtx (SImode);
4029 rtx shift_16 = GEN_INT (16);
4030 int op1_subbyte = 0;
4032 if (GET_CODE (operand1) == SUBREG)
4034 op1_subbyte = SUBREG_BYTE (operand1);
4035 op1_subbyte /= GET_MODE_SIZE (SImode);
4036 op1_subbyte *= GET_MODE_SIZE (SImode);
4037 operand1 = XEXP (operand1, 0);
4040 emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1, op1_subbyte),
4042 emit_insn (gen_lshrsi3 (operand0, temp, shift_16));
4046 (define_insn "*zero_extendhisi2_insn"
4047 [(set (match_operand:SI 0 "register_operand" "=r")
4048 (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
4051 [(set_attr "type" "load")
4052 (set_attr "us3load_type" "3cycle")])
4054 (define_expand "zero_extendqihi2"
4055 [(set (match_operand:HI 0 "register_operand" "")
4056 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
4060 (define_insn "*zero_extendqihi2_insn"
4061 [(set (match_operand:HI 0 "register_operand" "=r,r")
4062 (zero_extend:HI (match_operand:QI 1 "input_operand" "r,m")))]
4063 "GET_CODE (operands[1]) != CONST_INT"
4067 [(set_attr "type" "*,load")
4068 (set_attr "us3load_type" "*,3cycle")])
4070 (define_expand "zero_extendqisi2"
4071 [(set (match_operand:SI 0 "register_operand" "")
4072 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
4076 (define_insn "*zero_extendqisi2_insn"
4077 [(set (match_operand:SI 0 "register_operand" "=r,r")
4078 (zero_extend:SI (match_operand:QI 1 "input_operand" "r,m")))]
4079 "GET_CODE (operands[1]) != CONST_INT"
4083 [(set_attr "type" "*,load")
4084 (set_attr "us3load_type" "*,3cycle")])
4086 (define_expand "zero_extendqidi2"
4087 [(set (match_operand:DI 0 "register_operand" "")
4088 (zero_extend:DI (match_operand:QI 1 "register_operand" "")))]
4092 (define_insn "*zero_extendqidi2_insn"
4093 [(set (match_operand:DI 0 "register_operand" "=r,r")
4094 (zero_extend:DI (match_operand:QI 1 "input_operand" "r,m")))]
4095 "TARGET_ARCH64 && GET_CODE (operands[1]) != CONST_INT"
4099 [(set_attr "type" "*,load")
4100 (set_attr "us3load_type" "*,3cycle")])
4102 (define_expand "zero_extendhidi2"
4103 [(set (match_operand:DI 0 "register_operand" "")
4104 (zero_extend:DI (match_operand:HI 1 "register_operand" "")))]
4107 rtx temp = gen_reg_rtx (DImode);
4108 rtx shift_48 = GEN_INT (48);
4109 int op1_subbyte = 0;
4111 if (GET_CODE (operand1) == SUBREG)
4113 op1_subbyte = SUBREG_BYTE (operand1);
4114 op1_subbyte /= GET_MODE_SIZE (DImode);
4115 op1_subbyte *= GET_MODE_SIZE (DImode);
4116 operand1 = XEXP (operand1, 0);
4119 emit_insn (gen_ashldi3 (temp, gen_rtx_SUBREG (DImode, operand1, op1_subbyte),
4121 emit_insn (gen_lshrdi3 (operand0, temp, shift_48));
4125 (define_insn "*zero_extendhidi2_insn"
4126 [(set (match_operand:DI 0 "register_operand" "=r")
4127 (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
4130 [(set_attr "type" "load")
4131 (set_attr "us3load_type" "3cycle")])
4134 ;; ??? Write truncdisi pattern using sra?
4136 (define_expand "zero_extendsidi2"
4137 [(set (match_operand:DI 0 "register_operand" "")
4138 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))]
4142 (define_insn "*zero_extendsidi2_insn_sp64"
4143 [(set (match_operand:DI 0 "register_operand" "=r,r")
4144 (zero_extend:DI (match_operand:SI 1 "input_operand" "r,m")))]
4145 "TARGET_ARCH64 && GET_CODE (operands[1]) != CONST_INT"
4149 [(set_attr "type" "shift,load")])
4151 (define_insn_and_split "*zero_extendsidi2_insn_sp32"
4152 [(set (match_operand:DI 0 "register_operand" "=r")
4153 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
4156 "&& reload_completed"
4157 [(set (match_dup 2) (match_dup 3))
4158 (set (match_dup 4) (match_dup 5))]
4162 dest1 = gen_highpart (SImode, operands[0]);
4163 dest2 = gen_lowpart (SImode, operands[0]);
4165 /* Swap the order in case of overlap. */
4166 if (REGNO (dest1) == REGNO (operands[1]))
4168 operands[2] = dest2;
4169 operands[3] = operands[1];
4170 operands[4] = dest1;
4171 operands[5] = const0_rtx;
4175 operands[2] = dest1;
4176 operands[3] = const0_rtx;
4177 operands[4] = dest2;
4178 operands[5] = operands[1];
4181 [(set_attr "length" "2")])
4183 ;; Simplify comparisons of extended values.
4185 (define_insn "*cmp_zero_extendqisi2"
4187 (compare:CC (zero_extend:SI (match_operand:QI 0 "register_operand" "r"))
4190 "andcc\t%0, 0xff, %%g0"
4191 [(set_attr "type" "compare")])
4193 (define_insn "*cmp_zero_qi"
4195 (compare:CC (match_operand:QI 0 "register_operand" "r")
4198 "andcc\t%0, 0xff, %%g0"
4199 [(set_attr "type" "compare")])
4201 (define_insn "*cmp_zero_extendqisi2_set"
4203 (compare:CC (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
4205 (set (match_operand:SI 0 "register_operand" "=r")
4206 (zero_extend:SI (match_dup 1)))]
4208 "andcc\t%1, 0xff, %0"
4209 [(set_attr "type" "compare")])
4211 (define_insn "*cmp_zero_extendqisi2_andcc_set"
4213 (compare:CC (and:SI (match_operand:SI 1 "register_operand" "r")
4216 (set (match_operand:SI 0 "register_operand" "=r")
4217 (zero_extend:SI (subreg:QI (match_dup 1) 0)))]
4219 "andcc\t%1, 0xff, %0"
4220 [(set_attr "type" "compare")])
4222 (define_insn "*cmp_zero_extendqidi2"
4224 (compare:CCX (zero_extend:DI (match_operand:QI 0 "register_operand" "r"))
4227 "andcc\t%0, 0xff, %%g0"
4228 [(set_attr "type" "compare")])
4230 (define_insn "*cmp_zero_qi_sp64"
4232 (compare:CCX (match_operand:QI 0 "register_operand" "r")
4235 "andcc\t%0, 0xff, %%g0"
4236 [(set_attr "type" "compare")])
4238 (define_insn "*cmp_zero_extendqidi2_set"
4240 (compare:CCX (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
4242 (set (match_operand:DI 0 "register_operand" "=r")
4243 (zero_extend:DI (match_dup 1)))]
4245 "andcc\t%1, 0xff, %0"
4246 [(set_attr "type" "compare")])
4248 (define_insn "*cmp_zero_extendqidi2_andcc_set"
4250 (compare:CCX (and:DI (match_operand:DI 1 "register_operand" "r")
4253 (set (match_operand:DI 0 "register_operand" "=r")
4254 (zero_extend:DI (subreg:QI (match_dup 1) 0)))]
4256 "andcc\t%1, 0xff, %0"
4257 [(set_attr "type" "compare")])
4259 ;; Similarly, handle {SI,DI}->QI mode truncation followed by a compare.
4261 (define_insn "*cmp_siqi_trunc"
4263 (compare:CC (subreg:QI (match_operand:SI 0 "register_operand" "r") 3)
4266 "andcc\t%0, 0xff, %%g0"
4267 [(set_attr "type" "compare")])
4269 (define_insn "*cmp_siqi_trunc_set"
4271 (compare:CC (subreg:QI (match_operand:SI 1 "register_operand" "r") 3)
4273 (set (match_operand:QI 0 "register_operand" "=r")
4274 (subreg:QI (match_dup 1) 3))]
4276 "andcc\t%1, 0xff, %0"
4277 [(set_attr "type" "compare")])
4279 (define_insn "*cmp_diqi_trunc"
4281 (compare:CC (subreg:QI (match_operand:DI 0 "register_operand" "r") 7)
4284 "andcc\t%0, 0xff, %%g0"
4285 [(set_attr "type" "compare")])
4287 (define_insn "*cmp_diqi_trunc_set"
4289 (compare:CC (subreg:QI (match_operand:DI 1 "register_operand" "r") 7)
4291 (set (match_operand:QI 0 "register_operand" "=r")
4292 (subreg:QI (match_dup 1) 7))]
4294 "andcc\t%1, 0xff, %0"
4295 [(set_attr "type" "compare")])
4297 ;;- sign extension instructions
4299 ;; These patterns originally accepted general_operands, however, slightly
4300 ;; better code is generated by only accepting register_operands, and then
4301 ;; letting combine generate the lds[hb] insns.
4303 (define_expand "extendhisi2"
4304 [(set (match_operand:SI 0 "register_operand" "")
4305 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
4308 rtx temp = gen_reg_rtx (SImode);
4309 rtx shift_16 = GEN_INT (16);
4310 int op1_subbyte = 0;
4312 if (GET_CODE (operand1) == SUBREG)
4314 op1_subbyte = SUBREG_BYTE (operand1);
4315 op1_subbyte /= GET_MODE_SIZE (SImode);
4316 op1_subbyte *= GET_MODE_SIZE (SImode);
4317 operand1 = XEXP (operand1, 0);
4320 emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1, op1_subbyte),
4322 emit_insn (gen_ashrsi3 (operand0, temp, shift_16));
4326 (define_insn "*sign_extendhisi2_insn"
4327 [(set (match_operand:SI 0 "register_operand" "=r")
4328 (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
4331 [(set_attr "type" "sload")
4332 (set_attr "us3load_type" "3cycle")])
4334 (define_expand "extendqihi2"
4335 [(set (match_operand:HI 0 "register_operand" "")
4336 (sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
4339 rtx temp = gen_reg_rtx (SImode);
4340 rtx shift_24 = GEN_INT (24);
4341 int op1_subbyte = 0;
4342 int op0_subbyte = 0;
4344 if (GET_CODE (operand1) == SUBREG)
4346 op1_subbyte = SUBREG_BYTE (operand1);
4347 op1_subbyte /= GET_MODE_SIZE (SImode);
4348 op1_subbyte *= GET_MODE_SIZE (SImode);
4349 operand1 = XEXP (operand1, 0);
4351 if (GET_CODE (operand0) == SUBREG)
4353 op0_subbyte = SUBREG_BYTE (operand0);
4354 op0_subbyte /= GET_MODE_SIZE (SImode);
4355 op0_subbyte *= GET_MODE_SIZE (SImode);
4356 operand0 = XEXP (operand0, 0);
4358 emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1, op1_subbyte),
4360 if (GET_MODE (operand0) != SImode)
4361 operand0 = gen_rtx_SUBREG (SImode, operand0, op0_subbyte);
4362 emit_insn (gen_ashrsi3 (operand0, temp, shift_24));
4366 (define_insn "*sign_extendqihi2_insn"
4367 [(set (match_operand:HI 0 "register_operand" "=r")
4368 (sign_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
4371 [(set_attr "type" "sload")
4372 (set_attr "us3load_type" "3cycle")])
4374 (define_expand "extendqisi2"
4375 [(set (match_operand:SI 0 "register_operand" "")
4376 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
4379 rtx temp = gen_reg_rtx (SImode);
4380 rtx shift_24 = GEN_INT (24);
4381 int op1_subbyte = 0;
4383 if (GET_CODE (operand1) == SUBREG)
4385 op1_subbyte = SUBREG_BYTE (operand1);
4386 op1_subbyte /= GET_MODE_SIZE (SImode);
4387 op1_subbyte *= GET_MODE_SIZE (SImode);
4388 operand1 = XEXP (operand1, 0);
4391 emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1, op1_subbyte),
4393 emit_insn (gen_ashrsi3 (operand0, temp, shift_24));
4397 (define_insn "*sign_extendqisi2_insn"
4398 [(set (match_operand:SI 0 "register_operand" "=r")
4399 (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
4402 [(set_attr "type" "sload")
4403 (set_attr "us3load_type" "3cycle")])
4405 (define_expand "extendqidi2"
4406 [(set (match_operand:DI 0 "register_operand" "")
4407 (sign_extend:DI (match_operand:QI 1 "register_operand" "")))]
4410 rtx temp = gen_reg_rtx (DImode);
4411 rtx shift_56 = GEN_INT (56);
4412 int op1_subbyte = 0;
4414 if (GET_CODE (operand1) == SUBREG)
4416 op1_subbyte = SUBREG_BYTE (operand1);
4417 op1_subbyte /= GET_MODE_SIZE (DImode);
4418 op1_subbyte *= GET_MODE_SIZE (DImode);
4419 operand1 = XEXP (operand1, 0);
4422 emit_insn (gen_ashldi3 (temp, gen_rtx_SUBREG (DImode, operand1, op1_subbyte),
4424 emit_insn (gen_ashrdi3 (operand0, temp, shift_56));
4428 (define_insn "*sign_extendqidi2_insn"
4429 [(set (match_operand:DI 0 "register_operand" "=r")
4430 (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
4433 [(set_attr "type" "sload")
4434 (set_attr "us3load_type" "3cycle")])
4436 (define_expand "extendhidi2"
4437 [(set (match_operand:DI 0 "register_operand" "")
4438 (sign_extend:DI (match_operand:HI 1 "register_operand" "")))]
4441 rtx temp = gen_reg_rtx (DImode);
4442 rtx shift_48 = GEN_INT (48);
4443 int op1_subbyte = 0;
4445 if (GET_CODE (operand1) == SUBREG)
4447 op1_subbyte = SUBREG_BYTE (operand1);
4448 op1_subbyte /= GET_MODE_SIZE (DImode);
4449 op1_subbyte *= GET_MODE_SIZE (DImode);
4450 operand1 = XEXP (operand1, 0);
4453 emit_insn (gen_ashldi3 (temp, gen_rtx_SUBREG (DImode, operand1, op1_subbyte),
4455 emit_insn (gen_ashrdi3 (operand0, temp, shift_48));
4459 (define_insn "*sign_extendhidi2_insn"
4460 [(set (match_operand:DI 0 "register_operand" "=r")
4461 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
4464 [(set_attr "type" "sload")
4465 (set_attr "us3load_type" "3cycle")])
4467 (define_expand "extendsidi2"
4468 [(set (match_operand:DI 0 "register_operand" "")
4469 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))]
4473 (define_insn "*sign_extendsidi2_insn"
4474 [(set (match_operand:DI 0 "register_operand" "=r,r")
4475 (sign_extend:DI (match_operand:SI 1 "input_operand" "r,m")))]
4480 [(set_attr "type" "shift,sload")
4481 (set_attr "us3load_type" "*,3cycle")])
4483 ;; Special pattern for optimizing bit-field compares. This is needed
4484 ;; because combine uses this as a canonical form.
4486 (define_insn "*cmp_zero_extract"
4489 (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
4490 (match_operand:SI 1 "small_int_or_double" "n")
4491 (match_operand:SI 2 "small_int_or_double" "n"))
4493 "(GET_CODE (operands[2]) == CONST_INT
4494 && INTVAL (operands[2]) > 19)
4495 || (GET_CODE (operands[2]) == CONST_DOUBLE
4496 && CONST_DOUBLE_LOW (operands[2]) > 19)"
4498 int len = (GET_CODE (operands[1]) == CONST_INT
4499 ? INTVAL (operands[1])
4500 : CONST_DOUBLE_LOW (operands[1]));
4502 (GET_CODE (operands[2]) == CONST_INT
4503 ? INTVAL (operands[2])
4504 : CONST_DOUBLE_LOW (operands[2])) - len;
4505 HOST_WIDE_INT mask = ((1 << len) - 1) << pos;
4507 operands[1] = GEN_INT (mask);
4508 return "andcc\t%0, %1, %%g0";
4510 [(set_attr "type" "compare")])
4512 (define_insn "*cmp_zero_extract_sp64"
4515 (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
4516 (match_operand:SI 1 "small_int_or_double" "n")
4517 (match_operand:SI 2 "small_int_or_double" "n"))
4520 && ((GET_CODE (operands[2]) == CONST_INT
4521 && INTVAL (operands[2]) > 51)
4522 || (GET_CODE (operands[2]) == CONST_DOUBLE
4523 && CONST_DOUBLE_LOW (operands[2]) > 51))"
4525 int len = (GET_CODE (operands[1]) == CONST_INT
4526 ? INTVAL (operands[1])
4527 : CONST_DOUBLE_LOW (operands[1]));
4529 (GET_CODE (operands[2]) == CONST_INT
4530 ? INTVAL (operands[2])
4531 : CONST_DOUBLE_LOW (operands[2])) - len;
4532 HOST_WIDE_INT mask = (((unsigned HOST_WIDE_INT) 1 << len) - 1) << pos;
4534 operands[1] = GEN_INT (mask);
4535 return "andcc\t%0, %1, %%g0";
4537 [(set_attr "type" "compare")])
4539 ;; Conversions between float, double and long double.
4541 (define_insn "extendsfdf2"
4542 [(set (match_operand:DF 0 "register_operand" "=e")
4544 (match_operand:SF 1 "register_operand" "f")))]
4547 [(set_attr "type" "fp")
4548 (set_attr "fptype" "double")])
4550 (define_expand "extendsftf2"
4551 [(set (match_operand:TF 0 "nonimmediate_operand" "")
4553 (match_operand:SF 1 "register_operand" "")))]
4554 "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
4555 "emit_tfmode_cvt (FLOAT_EXTEND, operands); DONE;")
4557 (define_insn "*extendsftf2_hq"
4558 [(set (match_operand:TF 0 "register_operand" "=e")
4560 (match_operand:SF 1 "register_operand" "f")))]
4561 "TARGET_FPU && TARGET_HARD_QUAD"
4563 [(set_attr "type" "fp")])
4565 (define_expand "extenddftf2"
4566 [(set (match_operand:TF 0 "nonimmediate_operand" "")
4568 (match_operand:DF 1 "register_operand" "")))]
4569 "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
4570 "emit_tfmode_cvt (FLOAT_EXTEND, operands); DONE;")
4572 (define_insn "*extenddftf2_hq"
4573 [(set (match_operand:TF 0 "register_operand" "=e")
4575 (match_operand:DF 1 "register_operand" "e")))]
4576 "TARGET_FPU && TARGET_HARD_QUAD"
4578 [(set_attr "type" "fp")])
4580 (define_insn "truncdfsf2"
4581 [(set (match_operand:SF 0 "register_operand" "=f")
4583 (match_operand:DF 1 "register_operand" "e")))]
4586 [(set_attr "type" "fp")
4587 (set_attr "fptype" "double")])
4589 (define_expand "trunctfsf2"
4590 [(set (match_operand:SF 0 "register_operand" "")
4592 (match_operand:TF 1 "general_operand" "")))]
4593 "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
4594 "emit_tfmode_cvt (FLOAT_TRUNCATE, operands); DONE;")
4596 (define_insn "*trunctfsf2_hq"
4597 [(set (match_operand:SF 0 "register_operand" "=f")
4599 (match_operand:TF 1 "register_operand" "e")))]
4600 "TARGET_FPU && TARGET_HARD_QUAD"
4602 [(set_attr "type" "fp")])
4604 (define_expand "trunctfdf2"
4605 [(set (match_operand:DF 0 "register_operand" "")
4607 (match_operand:TF 1 "general_operand" "")))]
4608 "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
4609 "emit_tfmode_cvt (FLOAT_TRUNCATE, operands); DONE;")
4611 (define_insn "*trunctfdf2_hq"
4612 [(set (match_operand:DF 0 "register_operand" "=e")
4614 (match_operand:TF 1 "register_operand" "e")))]
4615 "TARGET_FPU && TARGET_HARD_QUAD"
4617 [(set_attr "type" "fp")])
4619 ;; Conversion between fixed point and floating point.
4621 (define_insn "floatsisf2"
4622 [(set (match_operand:SF 0 "register_operand" "=f")
4623 (float:SF (match_operand:SI 1 "register_operand" "f")))]
4626 [(set_attr "type" "fp")
4627 (set_attr "fptype" "double")])
4629 (define_insn "floatsidf2"
4630 [(set (match_operand:DF 0 "register_operand" "=e")
4631 (float:DF (match_operand:SI 1 "register_operand" "f")))]
4634 [(set_attr "type" "fp")
4635 (set_attr "fptype" "double")])
4637 (define_expand "floatsitf2"
4638 [(set (match_operand:TF 0 "nonimmediate_operand" "")
4639 (float:TF (match_operand:SI 1 "register_operand" "")))]
4640 "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
4641 "emit_tfmode_cvt (FLOAT, operands); DONE;")
4643 (define_insn "*floatsitf2_hq"
4644 [(set (match_operand:TF 0 "register_operand" "=e")
4645 (float:TF (match_operand:SI 1 "register_operand" "f")))]
4646 "TARGET_FPU && TARGET_HARD_QUAD"
4648 [(set_attr "type" "fp")])
4650 (define_expand "floatunssitf2"
4651 [(set (match_operand:TF 0 "nonimmediate_operand" "")
4652 (unsigned_float:TF (match_operand:SI 1 "register_operand" "")))]
4653 "TARGET_FPU && TARGET_ARCH64 && ! TARGET_HARD_QUAD"
4654 "emit_tfmode_cvt (UNSIGNED_FLOAT, operands); DONE;")
4656 ;; Now the same for 64 bit sources.
4658 (define_insn "floatdisf2"
4659 [(set (match_operand:SF 0 "register_operand" "=f")
4660 (float:SF (match_operand:DI 1 "register_operand" "e")))]
4661 "TARGET_V9 && TARGET_FPU"
4663 [(set_attr "type" "fp")
4664 (set_attr "fptype" "double")])
4666 (define_expand "floatunsdisf2"
4667 [(use (match_operand:SF 0 "register_operand" ""))
4668 (use (match_operand:DI 1 "register_operand" ""))]
4669 "TARGET_ARCH64 && TARGET_FPU"
4670 "sparc_emit_floatunsdi (operands); DONE;")
4672 (define_insn "floatdidf2"
4673 [(set (match_operand:DF 0 "register_operand" "=e")
4674 (float:DF (match_operand:DI 1 "register_operand" "e")))]
4675 "TARGET_V9 && TARGET_FPU"
4677 [(set_attr "type" "fp")
4678 (set_attr "fptype" "double")])
4680 (define_expand "floatunsdidf2"
4681 [(use (match_operand:DF 0 "register_operand" ""))
4682 (use (match_operand:DI 1 "register_operand" ""))]
4683 "TARGET_ARCH64 && TARGET_FPU"
4684 "sparc_emit_floatunsdi (operands); DONE;")
4686 (define_expand "floatditf2"
4687 [(set (match_operand:TF 0 "nonimmediate_operand" "")
4688 (float:TF (match_operand:DI 1 "register_operand" "")))]
4689 "TARGET_FPU && TARGET_V9 && (TARGET_HARD_QUAD || TARGET_ARCH64)"
4690 "emit_tfmode_cvt (FLOAT, operands); DONE;")
4692 (define_insn "*floatditf2_hq"
4693 [(set (match_operand:TF 0 "register_operand" "=e")
4694 (float:TF (match_operand:DI 1 "register_operand" "e")))]
4695 "TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD"
4697 [(set_attr "type" "fp")])
4699 (define_expand "floatunsditf2"
4700 [(set (match_operand:TF 0 "nonimmediate_operand" "")
4701 (unsigned_float:TF (match_operand:DI 1 "register_operand" "")))]
4702 "TARGET_FPU && TARGET_ARCH64 && ! TARGET_HARD_QUAD"
4703 "emit_tfmode_cvt (UNSIGNED_FLOAT, operands); DONE;")
4705 ;; Convert a float to an actual integer.
4706 ;; Truncation is performed as part of the conversion.
4708 (define_insn "fix_truncsfsi2"
4709 [(set (match_operand:SI 0 "register_operand" "=f")
4710 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4713 [(set_attr "type" "fp")
4714 (set_attr "fptype" "double")])
4716 (define_insn "fix_truncdfsi2"
4717 [(set (match_operand:SI 0 "register_operand" "=f")
4718 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "e"))))]
4721 [(set_attr "type" "fp")
4722 (set_attr "fptype" "double")])
4724 (define_expand "fix_trunctfsi2"
4725 [(set (match_operand:SI 0 "register_operand" "")
4726 (fix:SI (match_operand:TF 1 "general_operand" "")))]
4727 "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
4728 "emit_tfmode_cvt (FIX, operands); DONE;")
4730 (define_insn "*fix_trunctfsi2_hq"
4731 [(set (match_operand:SI 0 "register_operand" "=f")
4732 (fix:SI (match_operand:TF 1 "register_operand" "e")))]
4733 "TARGET_FPU && TARGET_HARD_QUAD"
4735 [(set_attr "type" "fp")])
4737 (define_expand "fixuns_trunctfsi2"
4738 [(set (match_operand:SI 0 "register_operand" "")
4739 (unsigned_fix:SI (match_operand:TF 1 "general_operand" "")))]
4740 "TARGET_FPU && TARGET_ARCH64 && ! TARGET_HARD_QUAD"
4741 "emit_tfmode_cvt (UNSIGNED_FIX, operands); DONE;")
4743 ;; Now the same, for V9 targets
4745 (define_insn "fix_truncsfdi2"
4746 [(set (match_operand:DI 0 "register_operand" "=e")
4747 (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4748 "TARGET_V9 && TARGET_FPU"
4750 [(set_attr "type" "fp")
4751 (set_attr "fptype" "double")])
4753 (define_insn "fix_truncdfdi2"
4754 [(set (match_operand:DI 0 "register_operand" "=e")
4755 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "e"))))]
4756 "TARGET_V9 && TARGET_FPU"
4758 [(set_attr "type" "fp")
4759 (set_attr "fptype" "double")])
4761 (define_expand "fix_trunctfdi2"
4762 [(set (match_operand:DI 0 "register_operand" "")
4763 (fix:DI (match_operand:TF 1 "general_operand" "")))]
4764 "TARGET_V9 && TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
4765 "emit_tfmode_cvt (FIX, operands); DONE;")
4767 (define_insn "*fix_trunctfdi2_hq"
4768 [(set (match_operand:DI 0 "register_operand" "=e")
4769 (fix:DI (match_operand:TF 1 "register_operand" "e")))]
4770 "TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD"
4772 [(set_attr "type" "fp")])
4774 (define_expand "fixuns_trunctfdi2"
4775 [(set (match_operand:DI 0 "register_operand" "")
4776 (unsigned_fix:DI (match_operand:TF 1 "general_operand" "")))]
4777 "TARGET_FPU && TARGET_ARCH64 && ! TARGET_HARD_QUAD"
4778 "emit_tfmode_cvt (UNSIGNED_FIX, operands); DONE;")
4780 ;;- arithmetic instructions
4782 (define_expand "adddi3"
4783 [(set (match_operand:DI 0 "register_operand" "")
4784 (plus:DI (match_operand:DI 1 "register_operand" "")
4785 (match_operand:DI 2 "arith_double_add_operand" "")))]
4788 if (! TARGET_ARCH64)
4790 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
4791 gen_rtx_SET (VOIDmode, operands[0],
4792 gen_rtx_PLUS (DImode, operands[1],
4794 gen_rtx_CLOBBER (VOIDmode,
4795 gen_rtx_REG (CCmode, SPARC_ICC_REG)))));
4800 (define_insn_and_split "adddi3_insn_sp32"
4801 [(set (match_operand:DI 0 "register_operand" "=r")
4802 (plus:DI (match_operand:DI 1 "arith_double_operand" "%r")
4803 (match_operand:DI 2 "arith_double_operand" "rHI")))
4804 (clobber (reg:CC 100))]
4807 "&& reload_completed"
4808 [(parallel [(set (reg:CC_NOOV 100)
4809 (compare:CC_NOOV (plus:SI (match_dup 4)
4813 (plus:SI (match_dup 4) (match_dup 5)))])
4815 (plus:SI (plus:SI (match_dup 7)
4817 (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
4819 operands[3] = gen_lowpart (SImode, operands[0]);
4820 operands[4] = gen_lowpart (SImode, operands[1]);
4821 operands[5] = gen_lowpart (SImode, operands[2]);
4822 operands[6] = gen_highpart (SImode, operands[0]);
4823 operands[7] = gen_highpart_mode (SImode, DImode, operands[1]);
4824 #if HOST_BITS_PER_WIDE_INT == 32
4825 if (GET_CODE (operands[2]) == CONST_INT)
4827 if (INTVAL (operands[2]) < 0)
4828 operands[8] = constm1_rtx;
4830 operands[8] = const0_rtx;
4834 operands[8] = gen_highpart_mode (SImode, DImode, operands[2]);
4836 [(set_attr "length" "2")])
4839 [(set (match_operand:DI 0 "register_operand" "")
4840 (minus:DI (match_operand:DI 1 "arith_double_operand" "")
4841 (match_operand:DI 2 "arith_double_operand" "")))
4842 (clobber (reg:CC 100))]
4843 "! TARGET_ARCH64 && reload_completed"
4844 [(parallel [(set (reg:CC_NOOV 100)
4845 (compare:CC_NOOV (minus:SI (match_dup 4)
4849 (minus:SI (match_dup 4) (match_dup 5)))])
4851 (minus:SI (minus:SI (match_dup 7)
4853 (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
4855 operands[3] = gen_lowpart (SImode, operands[0]);
4856 operands[4] = gen_lowpart (SImode, operands[1]);
4857 operands[5] = gen_lowpart (SImode, operands[2]);
4858 operands[6] = gen_highpart (SImode, operands[0]);
4859 operands[7] = gen_highpart (SImode, operands[1]);
4860 #if HOST_BITS_PER_WIDE_INT == 32
4861 if (GET_CODE (operands[2]) == CONST_INT)
4863 if (INTVAL (operands[2]) < 0)
4864 operands[8] = constm1_rtx;
4866 operands[8] = const0_rtx;
4870 operands[8] = gen_highpart_mode (SImode, DImode, operands[2]);
4873 ;; LTU here means "carry set"
4875 [(set (match_operand:SI 0 "register_operand" "=r")
4876 (plus:SI (plus:SI (match_operand:SI 1 "arith_operand" "%r")
4877 (match_operand:SI 2 "arith_operand" "rI"))
4878 (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
4881 [(set_attr "type" "ialuX")])
4883 (define_insn_and_split "*addx_extend_sp32"
4884 [(set (match_operand:DI 0 "register_operand" "=r")
4885 (zero_extend:DI (plus:SI (plus:SI
4886 (match_operand:SI 1 "reg_or_0_operand" "%rJ")
4887 (match_operand:SI 2 "arith_operand" "rI"))
4888 (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))]
4891 "&& reload_completed"
4892 [(set (match_dup 3) (plus:SI (plus:SI (match_dup 1) (match_dup 2))
4893 (ltu:SI (reg:CC_NOOV 100) (const_int 0))))
4894 (set (match_dup 4) (const_int 0))]
4895 "operands[3] = gen_lowpart (SImode, operands[0]);
4896 operands[4] = gen_highpart_mode (SImode, DImode, operands[1]);"
4897 [(set_attr "length" "2")])
4899 (define_insn "*addx_extend_sp64"
4900 [(set (match_operand:DI 0 "register_operand" "=r")
4901 (zero_extend:DI (plus:SI (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
4902 (match_operand:SI 2 "arith_operand" "rI"))
4903 (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))]
4906 [(set_attr "type" "ialuX")])
4909 [(set (match_operand:SI 0 "register_operand" "=r")
4910 (minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
4911 (match_operand:SI 2 "arith_operand" "rI"))
4912 (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
4915 [(set_attr "type" "ialuX")])
4917 (define_insn "*subx_extend_sp64"
4918 [(set (match_operand:DI 0 "register_operand" "=r")
4919 (zero_extend:DI (minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
4920 (match_operand:SI 2 "arith_operand" "rI"))
4921 (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))]
4924 [(set_attr "type" "ialuX")])
4926 (define_insn_and_split "*subx_extend"
4927 [(set (match_operand:DI 0 "register_operand" "=r")
4928 (zero_extend:DI (minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
4929 (match_operand:SI 2 "arith_operand" "rI"))
4930 (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))]
4933 "&& reload_completed"
4934 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 1) (match_dup 2))
4935 (ltu:SI (reg:CC_NOOV 100) (const_int 0))))
4936 (set (match_dup 4) (const_int 0))]
4937 "operands[3] = gen_lowpart (SImode, operands[0]);
4938 operands[4] = gen_highpart (SImode, operands[0]);"
4939 [(set_attr "length" "2")])
4941 (define_insn_and_split ""
4942 [(set (match_operand:DI 0 "register_operand" "=r")
4943 (plus:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
4944 (match_operand:DI 2 "register_operand" "r")))
4945 (clobber (reg:CC 100))]
4948 "&& reload_completed"
4949 [(parallel [(set (reg:CC_NOOV 100)
4950 (compare:CC_NOOV (plus:SI (match_dup 3) (match_dup 1))
4952 (set (match_dup 5) (plus:SI (match_dup 3) (match_dup 1)))])
4954 (plus:SI (plus:SI (match_dup 4) (const_int 0))
4955 (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
4956 "operands[3] = gen_lowpart (SImode, operands[2]);
4957 operands[4] = gen_highpart (SImode, operands[2]);
4958 operands[5] = gen_lowpart (SImode, operands[0]);
4959 operands[6] = gen_highpart (SImode, operands[0]);"
4960 [(set_attr "length" "2")])
4962 (define_insn "*adddi3_sp64"
4963 [(set (match_operand:DI 0 "register_operand" "=r,r")
4964 (plus:DI (match_operand:DI 1 "register_operand" "%r,r")
4965 (match_operand:DI 2 "arith_double_add_operand" "rHI,O")))]
4971 (define_insn "addsi3"
4972 [(set (match_operand:SI 0 "register_operand" "=r,r,d")
4973 (plus:SI (match_operand:SI 1 "register_operand" "%r,r,d")
4974 (match_operand:SI 2 "arith_add_operand" "rI,O,d")))]
4979 fpadd32s\t%1, %2, %0"
4980 [(set_attr "type" "*,*,fga")])
4982 (define_insn "*cmp_cc_plus"
4983 [(set (reg:CC_NOOV 100)
4984 (compare:CC_NOOV (plus:SI (match_operand:SI 0 "arith_operand" "%r")
4985 (match_operand:SI 1 "arith_operand" "rI"))
4988 "addcc\t%0, %1, %%g0"
4989 [(set_attr "type" "compare")])
4991 (define_insn "*cmp_ccx_plus"
4992 [(set (reg:CCX_NOOV 100)
4993 (compare:CCX_NOOV (plus:DI (match_operand:DI 0 "arith_double_operand" "%r")
4994 (match_operand:DI 1 "arith_double_operand" "rHI"))
4997 "addcc\t%0, %1, %%g0"
4998 [(set_attr "type" "compare")])
5000 (define_insn "*cmp_cc_plus_set"
5001 [(set (reg:CC_NOOV 100)
5002 (compare:CC_NOOV (plus:SI (match_operand:SI 1 "arith_operand" "%r")
5003 (match_operand:SI 2 "arith_operand" "rI"))
5005 (set (match_operand:SI 0 "register_operand" "=r")
5006 (plus:SI (match_dup 1) (match_dup 2)))]
5009 [(set_attr "type" "compare")])
5011 (define_insn "*cmp_ccx_plus_set"
5012 [(set (reg:CCX_NOOV 100)
5013 (compare:CCX_NOOV (plus:DI (match_operand:DI 1 "arith_double_operand" "%r")
5014 (match_operand:DI 2 "arith_double_operand" "rHI"))
5016 (set (match_operand:DI 0 "register_operand" "=r")
5017 (plus:DI (match_dup 1) (match_dup 2)))]
5020 [(set_attr "type" "compare")])
5022 (define_expand "subdi3"
5023 [(set (match_operand:DI 0 "register_operand" "")
5024 (minus:DI (match_operand:DI 1 "register_operand" "")
5025 (match_operand:DI 2 "arith_double_add_operand" "")))]
5028 if (! TARGET_ARCH64)
5030 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
5031 gen_rtx_SET (VOIDmode, operands[0],
5032 gen_rtx_MINUS (DImode, operands[1],
5034 gen_rtx_CLOBBER (VOIDmode,
5035 gen_rtx_REG (CCmode, SPARC_ICC_REG)))));
5040 (define_insn_and_split "*subdi3_sp32"
5041 [(set (match_operand:DI 0 "register_operand" "=r")
5042 (minus:DI (match_operand:DI 1 "register_operand" "r")
5043 (match_operand:DI 2 "arith_double_operand" "rHI")))
5044 (clobber (reg:CC 100))]
5047 "&& reload_completed
5048 && (GET_CODE (operands[2]) == CONST_INT
5049 || GET_CODE (operands[2]) == CONST_DOUBLE)"
5050 [(clobber (const_int 0))]
5054 highp = gen_highpart_mode (SImode, DImode, operands[2]);
5055 lowp = gen_lowpart (SImode, operands[2]);
5056 if ((lowp == const0_rtx)
5057 && (operands[0] == operands[1]))
5059 emit_insn (gen_rtx_SET (VOIDmode,
5060 gen_highpart (SImode, operands[0]),
5061 gen_rtx_MINUS (SImode,
5062 gen_highpart_mode (SImode, DImode,
5068 emit_insn (gen_cmp_minus_cc_set (gen_lowpart (SImode, operands[0]),
5069 gen_lowpart (SImode, operands[1]),
5071 emit_insn (gen_subx (gen_highpart (SImode, operands[0]),
5072 gen_highpart_mode (SImode, DImode, operands[1]),
5077 [(set_attr "length" "2")])
5080 [(set (match_operand:DI 0 "register_operand" "")
5081 (minus:DI (match_operand:DI 1 "register_operand" "")
5082 (match_operand:DI 2 "register_operand" "")))
5083 (clobber (reg:CC 100))]
5085 && reload_completed"
5086 [(clobber (const_int 0))]
5088 emit_insn (gen_cmp_minus_cc_set (gen_lowpart (SImode, operands[0]),
5089 gen_lowpart (SImode, operands[1]),
5090 gen_lowpart (SImode, operands[2])));
5091 emit_insn (gen_subx (gen_highpart (SImode, operands[0]),
5092 gen_highpart (SImode, operands[1]),
5093 gen_highpart (SImode, operands[2])));
5097 (define_insn_and_split ""
5098 [(set (match_operand:DI 0 "register_operand" "=r")
5099 (minus:DI (match_operand:DI 1 "register_operand" "r")
5100 (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))
5101 (clobber (reg:CC 100))]
5104 "&& reload_completed"
5105 [(parallel [(set (reg:CC_NOOV 100)
5106 (compare:CC_NOOV (minus:SI (match_dup 3) (match_dup 2))
5108 (set (match_dup 5) (minus:SI (match_dup 3) (match_dup 2)))])
5110 (minus:SI (minus:SI (match_dup 4) (const_int 0))
5111 (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
5112 "operands[3] = gen_lowpart (SImode, operands[1]);
5113 operands[4] = gen_highpart (SImode, operands[1]);
5114 operands[5] = gen_lowpart (SImode, operands[0]);
5115 operands[6] = gen_highpart (SImode, operands[0]);"
5116 [(set_attr "length" "2")])
5118 (define_insn "*subdi3_sp64"
5119 [(set (match_operand:DI 0 "register_operand" "=r,r")
5120 (minus:DI (match_operand:DI 1 "register_operand" "r,r")
5121 (match_operand:DI 2 "arith_double_add_operand" "rHI,O")))]
5127 (define_insn "subsi3"
5128 [(set (match_operand:SI 0 "register_operand" "=r,r,d")
5129 (minus:SI (match_operand:SI 1 "register_operand" "r,r,d")
5130 (match_operand:SI 2 "arith_add_operand" "rI,O,d")))]
5135 fpsub32s\t%1, %2, %0"
5136 [(set_attr "type" "*,*,fga")])
5138 (define_insn "*cmp_minus_cc"
5139 [(set (reg:CC_NOOV 100)
5140 (compare:CC_NOOV (minus:SI (match_operand:SI 0 "reg_or_0_operand" "rJ")
5141 (match_operand:SI 1 "arith_operand" "rI"))
5144 "subcc\t%r0, %1, %%g0"
5145 [(set_attr "type" "compare")])
5147 (define_insn "*cmp_minus_ccx"
5148 [(set (reg:CCX_NOOV 100)
5149 (compare:CCX_NOOV (minus:DI (match_operand:DI 0 "register_operand" "r")
5150 (match_operand:DI 1 "arith_double_operand" "rHI"))
5153 "subcc\t%0, %1, %%g0"
5154 [(set_attr "type" "compare")])
5156 (define_insn "cmp_minus_cc_set"
5157 [(set (reg:CC_NOOV 100)
5158 (compare:CC_NOOV (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
5159 (match_operand:SI 2 "arith_operand" "rI"))
5161 (set (match_operand:SI 0 "register_operand" "=r")
5162 (minus:SI (match_dup 1) (match_dup 2)))]
5164 "subcc\t%r1, %2, %0"
5165 [(set_attr "type" "compare")])
5167 (define_insn "*cmp_minus_ccx_set"
5168 [(set (reg:CCX_NOOV 100)
5169 (compare:CCX_NOOV (minus:DI (match_operand:DI 1 "register_operand" "r")
5170 (match_operand:DI 2 "arith_double_operand" "rHI"))
5172 (set (match_operand:DI 0 "register_operand" "=r")
5173 (minus:DI (match_dup 1) (match_dup 2)))]
5176 [(set_attr "type" "compare")])
5178 ;; Integer Multiply/Divide.
5180 ;; The 32 bit multiply/divide instructions are deprecated on v9, but at
5181 ;; least in UltraSPARC I, II and IIi it is a win tick-wise.
5183 (define_insn "mulsi3"
5184 [(set (match_operand:SI 0 "register_operand" "=r")
5185 (mult:SI (match_operand:SI 1 "arith_operand" "%r")
5186 (match_operand:SI 2 "arith_operand" "rI")))]
5189 [(set_attr "type" "imul")])
5191 (define_expand "muldi3"
5192 [(set (match_operand:DI 0 "register_operand" "=r")
5193 (mult:DI (match_operand:DI 1 "arith_double_operand" "%r")
5194 (match_operand:DI 2 "arith_double_operand" "rHI")))]
5195 "TARGET_ARCH64 || TARGET_V8PLUS"
5199 emit_insn (gen_muldi3_v8plus (operands[0], operands[1], operands[2]));
5204 (define_insn "*muldi3_sp64"
5205 [(set (match_operand:DI 0 "register_operand" "=r")
5206 (mult:DI (match_operand:DI 1 "arith_double_operand" "%r")
5207 (match_operand:DI 2 "arith_double_operand" "rHI")))]
5210 [(set_attr "type" "imul")])
5212 ;; V8plus wide multiply.
5214 (define_insn "muldi3_v8plus"
5215 [(set (match_operand:DI 0 "register_operand" "=r,h")
5216 (mult:DI (match_operand:DI 1 "arith_double_operand" "%r,0")
5217 (match_operand:DI 2 "arith_double_operand" "rI,rI")))
5218 (clobber (match_scratch:SI 3 "=&h,X"))
5219 (clobber (match_scratch:SI 4 "=&h,X"))]
5222 if (sparc_check_64 (operands[1], insn) <= 0)
5223 output_asm_insn ("srl\t%L1, 0, %L1", operands);
5224 if (which_alternative == 1)
5225 output_asm_insn ("sllx\t%H1, 32, %H1", operands);
5226 if (GET_CODE (operands[2]) == CONST_INT)
5228 if (which_alternative == 1)
5229 return "or\t%L1, %H1, %H1\n\tmulx\t%H1, %2, %L0\;srlx\t%L0, 32, %H0";
5231 return "sllx\t%H1, 32, %3\n\tor\t%L1, %3, %3\n\tmulx\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0";
5233 else if (rtx_equal_p (operands[1], operands[2]))
5235 if (which_alternative == 1)
5236 return "or\t%L1, %H1, %H1\n\tmulx\t%H1, %H1, %L0\;srlx\t%L0, 32, %H0";
5238 return "sllx\t%H1, 32, %3\n\tor\t%L1, %3, %3\n\tmulx\t%3, %3, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0";
5240 if (sparc_check_64 (operands[2], insn) <= 0)
5241 output_asm_insn ("srl\t%L2, 0, %L2", operands);
5242 if (which_alternative == 1)
5243 return "or\t%L1, %H1, %H1\n\tsllx\t%H2, 32, %L1\n\tor\t%L2, %L1, %L1\n\tmulx\t%H1, %L1, %L0\;srlx\t%L0, 32, %H0";
5245 return "sllx\t%H1, 32, %3\n\tsllx\t%H2, 32, %4\n\tor\t%L1, %3, %3\n\tor\t%L2, %4, %4\n\tmulx\t%3, %4, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0";
5247 [(set_attr "type" "multi")
5248 (set_attr "length" "9,8")])
5250 (define_insn "*cmp_mul_set"
5252 (compare:CC (mult:SI (match_operand:SI 1 "arith_operand" "%r")
5253 (match_operand:SI 2 "arith_operand" "rI"))
5255 (set (match_operand:SI 0 "register_operand" "=r")
5256 (mult:SI (match_dup 1) (match_dup 2)))]
5257 "TARGET_V8 || TARGET_SPARCLITE || TARGET_DEPRECATED_V8_INSNS"
5258 "smulcc\t%1, %2, %0"
5259 [(set_attr "type" "imul")])
5261 (define_expand "mulsidi3"
5262 [(set (match_operand:DI 0 "register_operand" "")
5263 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
5264 (sign_extend:DI (match_operand:SI 2 "arith_operand" ""))))]
5267 if (CONSTANT_P (operands[2]))
5270 emit_insn (gen_const_mulsidi3_v8plus (operands[0], operands[1],
5272 else if (TARGET_ARCH32)
5273 emit_insn (gen_const_mulsidi3_sp32 (operands[0], operands[1],
5276 emit_insn (gen_const_mulsidi3_sp64 (operands[0], operands[1],
5282 emit_insn (gen_mulsidi3_v8plus (operands[0], operands[1], operands[2]));
5287 ;; V9 puts the 64 bit product in a 64 bit register. Only out or global
5288 ;; registers can hold 64 bit values in the V8plus environment.
5290 (define_insn "mulsidi3_v8plus"
5291 [(set (match_operand:DI 0 "register_operand" "=h,r")
5292 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
5293 (sign_extend:DI (match_operand:SI 2 "register_operand" "r,r"))))
5294 (clobber (match_scratch:SI 3 "=X,&h"))]
5297 smul\t%1, %2, %L0\n\tsrlx\t%L0, 32, %H0
5298 smul\t%1, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0"
5299 [(set_attr "type" "multi")
5300 (set_attr "length" "2,3")])
5303 (define_insn "const_mulsidi3_v8plus"
5304 [(set (match_operand:DI 0 "register_operand" "=h,r")
5305 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
5306 (match_operand:DI 2 "small_int" "I,I")))
5307 (clobber (match_scratch:SI 3 "=X,&h"))]
5310 smul\t%1, %2, %L0\n\tsrlx\t%L0, 32, %H0
5311 smul\t%1, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0"
5312 [(set_attr "type" "multi")
5313 (set_attr "length" "2,3")])
5316 (define_insn "*mulsidi3_sp32"
5317 [(set (match_operand:DI 0 "register_operand" "=r")
5318 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
5319 (sign_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
5322 return TARGET_SPARCLET
5323 ? "smuld\t%1, %2, %L0"
5324 : "smul\t%1, %2, %L0\n\trd\t%%y, %H0";
5327 (if_then_else (eq_attr "isa" "sparclet")
5328 (const_string "imul") (const_string "multi")))
5329 (set (attr "length")
5330 (if_then_else (eq_attr "isa" "sparclet")
5331 (const_int 1) (const_int 2)))])
5333 (define_insn "*mulsidi3_sp64"
5334 [(set (match_operand:DI 0 "register_operand" "=r")
5335 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
5336 (sign_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
5337 "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
5339 [(set_attr "type" "imul")])
5341 ;; Extra pattern, because sign_extend of a constant isn't valid.
5344 (define_insn "const_mulsidi3_sp32"
5345 [(set (match_operand:DI 0 "register_operand" "=r")
5346 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
5347 (match_operand:DI 2 "small_int" "I")))]
5350 return TARGET_SPARCLET
5351 ? "smuld\t%1, %2, %L0"
5352 : "smul\t%1, %2, %L0\n\trd\t%%y, %H0";
5355 (if_then_else (eq_attr "isa" "sparclet")
5356 (const_string "imul") (const_string "multi")))
5357 (set (attr "length")
5358 (if_then_else (eq_attr "isa" "sparclet")
5359 (const_int 1) (const_int 2)))])
5361 (define_insn "const_mulsidi3_sp64"
5362 [(set (match_operand:DI 0 "register_operand" "=r")
5363 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
5364 (match_operand:DI 2 "small_int" "I")))]
5365 "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
5367 [(set_attr "type" "imul")])
5369 (define_expand "smulsi3_highpart"
5370 [(set (match_operand:SI 0 "register_operand" "")
5372 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
5373 (sign_extend:DI (match_operand:SI 2 "arith_operand" "")))
5375 "TARGET_HARD_MUL && TARGET_ARCH32"
5377 if (CONSTANT_P (operands[2]))
5381 emit_insn (gen_const_smulsi3_highpart_v8plus (operands[0],
5387 emit_insn (gen_const_smulsi3_highpart (operands[0], operands[1], operands[2]));
5392 emit_insn (gen_smulsi3_highpart_v8plus (operands[0], operands[1],
5393 operands[2], GEN_INT (32)));
5399 (define_insn "smulsi3_highpart_v8plus"
5400 [(set (match_operand:SI 0 "register_operand" "=h,r")
5402 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
5403 (sign_extend:DI (match_operand:SI 2 "register_operand" "r,r")))
5404 (match_operand:SI 3 "const_int_operand" "i,i"))))
5405 (clobber (match_scratch:SI 4 "=X,&h"))]
5408 smul\t%1, %2, %0\;srlx\t%0, %3, %0
5409 smul\t%1, %2, %4\;srlx\t%4, %3, %0"
5410 [(set_attr "type" "multi")
5411 (set_attr "length" "2")])
5413 ;; The combiner changes TRUNCATE in the previous pattern to SUBREG.
5416 [(set (match_operand:SI 0 "register_operand" "=h,r")
5419 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
5420 (sign_extend:DI (match_operand:SI 2 "register_operand" "r,r")))
5421 (match_operand:SI 3 "const_int_operand" "i,i"))
5423 (clobber (match_scratch:SI 4 "=X,&h"))]
5426 smul\t%1, %2, %0\n\tsrlx\t%0, %3, %0
5427 smul\t%1, %2, %4\n\tsrlx\t%4, %3, %0"
5428 [(set_attr "type" "multi")
5429 (set_attr "length" "2")])
5432 (define_insn "const_smulsi3_highpart_v8plus"
5433 [(set (match_operand:SI 0 "register_operand" "=h,r")
5435 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
5436 (match_operand:DI 2 "small_int" "i,i"))
5437 (match_operand:SI 3 "const_int_operand" "i,i"))))
5438 (clobber (match_scratch:SI 4 "=X,&h"))]
5441 smul\t%1, %2, %0\n\tsrlx\t%0, %3, %0
5442 smul\t%1, %2, %4\n\tsrlx\t%4, %3, %0"
5443 [(set_attr "type" "multi")
5444 (set_attr "length" "2")])
5447 (define_insn "*smulsi3_highpart_sp32"
5448 [(set (match_operand:SI 0 "register_operand" "=r")
5450 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
5451 (sign_extend:DI (match_operand:SI 2 "register_operand" "r")))
5454 "smul\t%1, %2, %%g0\n\trd\t%%y, %0"
5455 [(set_attr "type" "multi")
5456 (set_attr "length" "2")])
5459 (define_insn "const_smulsi3_highpart"
5460 [(set (match_operand:SI 0 "register_operand" "=r")
5462 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
5463 (match_operand:DI 2 "small_int" "i"))
5466 "smul\t%1, %2, %%g0\n\trd\t%%y, %0"
5467 [(set_attr "type" "multi")
5468 (set_attr "length" "2")])
5470 (define_expand "umulsidi3"
5471 [(set (match_operand:DI 0 "register_operand" "")
5472 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
5473 (zero_extend:DI (match_operand:SI 2 "uns_arith_operand" ""))))]
5476 if (CONSTANT_P (operands[2]))
5479 emit_insn (gen_const_umulsidi3_v8plus (operands[0], operands[1],
5481 else if (TARGET_ARCH32)
5482 emit_insn (gen_const_umulsidi3_sp32 (operands[0], operands[1],
5485 emit_insn (gen_const_umulsidi3_sp64 (operands[0], operands[1],
5491 emit_insn (gen_umulsidi3_v8plus (operands[0], operands[1], operands[2]));
5497 (define_insn "umulsidi3_v8plus"
5498 [(set (match_operand:DI 0 "register_operand" "=h,r")
5499 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
5500 (zero_extend:DI (match_operand:SI 2 "register_operand" "r,r"))))
5501 (clobber (match_scratch:SI 3 "=X,&h"))]
5504 umul\t%1, %2, %L0\n\tsrlx\t%L0, 32, %H0
5505 umul\t%1, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0"
5506 [(set_attr "type" "multi")
5507 (set_attr "length" "2,3")])
5510 (define_insn "*umulsidi3_sp32"
5511 [(set (match_operand:DI 0 "register_operand" "=r")
5512 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
5513 (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
5516 return TARGET_SPARCLET
5517 ? "umuld\t%1, %2, %L0"
5518 : "umul\t%1, %2, %L0\n\trd\t%%y, %H0";
5521 (if_then_else (eq_attr "isa" "sparclet")
5522 (const_string "imul") (const_string "multi")))
5523 (set (attr "length")
5524 (if_then_else (eq_attr "isa" "sparclet")
5525 (const_int 1) (const_int 2)))])
5527 (define_insn "*umulsidi3_sp64"
5528 [(set (match_operand:DI 0 "register_operand" "=r")
5529 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
5530 (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
5531 "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
5533 [(set_attr "type" "imul")])
5535 ;; Extra pattern, because sign_extend of a constant isn't valid.
5538 (define_insn "const_umulsidi3_sp32"
5539 [(set (match_operand:DI 0 "register_operand" "=r")
5540 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
5541 (match_operand:DI 2 "uns_small_int" "")))]
5544 return TARGET_SPARCLET
5545 ? "umuld\t%1, %s2, %L0"
5546 : "umul\t%1, %s2, %L0\n\trd\t%%y, %H0";
5549 (if_then_else (eq_attr "isa" "sparclet")
5550 (const_string "imul") (const_string "multi")))
5551 (set (attr "length")
5552 (if_then_else (eq_attr "isa" "sparclet")
5553 (const_int 1) (const_int 2)))])
5555 (define_insn "const_umulsidi3_sp64"
5556 [(set (match_operand:DI 0 "register_operand" "=r")
5557 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
5558 (match_operand:DI 2 "uns_small_int" "")))]
5559 "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
5561 [(set_attr "type" "imul")])
5564 (define_insn "const_umulsidi3_v8plus"
5565 [(set (match_operand:DI 0 "register_operand" "=h,r")
5566 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
5567 (match_operand:DI 2 "uns_small_int" "")))
5568 (clobber (match_scratch:SI 3 "=X,h"))]
5571 umul\t%1, %s2, %L0\n\tsrlx\t%L0, 32, %H0
5572 umul\t%1, %s2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0"
5573 [(set_attr "type" "multi")
5574 (set_attr "length" "2,3")])
5576 (define_expand "umulsi3_highpart"
5577 [(set (match_operand:SI 0 "register_operand" "")
5579 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
5580 (zero_extend:DI (match_operand:SI 2 "uns_arith_operand" "")))
5582 "TARGET_HARD_MUL && TARGET_ARCH32"
5584 if (CONSTANT_P (operands[2]))
5588 emit_insn (gen_const_umulsi3_highpart_v8plus (operands[0],
5594 emit_insn (gen_const_umulsi3_highpart (operands[0], operands[1], operands[2]));
5599 emit_insn (gen_umulsi3_highpart_v8plus (operands[0], operands[1],
5600 operands[2], GEN_INT (32)));
5606 (define_insn "umulsi3_highpart_v8plus"
5607 [(set (match_operand:SI 0 "register_operand" "=h,r")
5609 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
5610 (zero_extend:DI (match_operand:SI 2 "register_operand" "r,r")))
5611 (match_operand:SI 3 "const_int_operand" "i,i"))))
5612 (clobber (match_scratch:SI 4 "=X,h"))]
5615 umul\t%1, %2, %0\n\tsrlx\t%0, %3, %0
5616 umul\t%1, %2, %4\n\tsrlx\t%4, %3, %0"
5617 [(set_attr "type" "multi")
5618 (set_attr "length" "2")])
5621 (define_insn "const_umulsi3_highpart_v8plus"
5622 [(set (match_operand:SI 0 "register_operand" "=h,r")
5624 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
5625 (match_operand:DI 2 "uns_small_int" ""))
5626 (match_operand:SI 3 "const_int_operand" "i,i"))))
5627 (clobber (match_scratch:SI 4 "=X,h"))]
5630 umul\t%1, %s2, %0\n\tsrlx\t%0, %3, %0
5631 umul\t%1, %s2, %4\n\tsrlx\t%4, %3, %0"
5632 [(set_attr "type" "multi")
5633 (set_attr "length" "2")])
5636 (define_insn "*umulsi3_highpart_sp32"
5637 [(set (match_operand:SI 0 "register_operand" "=r")
5639 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
5640 (zero_extend:DI (match_operand:SI 2 "register_operand" "r")))
5643 "umul\t%1, %2, %%g0\n\trd\t%%y, %0"
5644 [(set_attr "type" "multi")
5645 (set_attr "length" "2")])
5648 (define_insn "const_umulsi3_highpart"
5649 [(set (match_operand:SI 0 "register_operand" "=r")
5651 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
5652 (match_operand:DI 2 "uns_small_int" ""))
5655 "umul\t%1, %s2, %%g0\n\trd\t%%y, %0"
5656 [(set_attr "type" "multi")
5657 (set_attr "length" "2")])
5659 ;; The v8 architecture specifies that there must be 3 instructions between
5660 ;; a y register write and a use of it for correct results.
5662 (define_expand "divsi3"
5663 [(parallel [(set (match_operand:SI 0 "register_operand" "=r,r")
5664 (div:SI (match_operand:SI 1 "register_operand" "r,r")
5665 (match_operand:SI 2 "input_operand" "rI,m")))
5666 (clobber (match_scratch:SI 3 "=&r,&r"))])]
5667 "TARGET_V8 || TARGET_DEPRECATED_V8_INSNS"
5671 operands[3] = gen_reg_rtx(SImode);
5672 emit_insn (gen_ashrsi3 (operands[3], operands[1], GEN_INT (31)));
5673 emit_insn (gen_divsi3_sp64 (operands[0], operands[1], operands[2],
5679 (define_insn "divsi3_sp32"
5680 [(set (match_operand:SI 0 "register_operand" "=r,r")
5681 (div:SI (match_operand:SI 1 "register_operand" "r,r")
5682 (match_operand:SI 2 "input_operand" "rI,m")))
5683 (clobber (match_scratch:SI 3 "=&r,&r"))]
5684 "(TARGET_V8 || TARGET_DEPRECATED_V8_INSNS)
5687 if (which_alternative == 0)
5689 return "sra\t%1, 31, %3\n\twr\t%3, 0, %%y\n\tsdiv\t%1, %2, %0";
5691 return "sra\t%1, 31, %3\n\twr\t%3, 0, %%y\n\tnop\n\tnop\n\tnop\n\tsdiv\t%1, %2, %0";
5694 return "sra\t%1, 31, %3\n\twr\t%3, 0, %%y\n\tld\t%2, %3\n\tsdiv\t%1, %3, %0";
5696 return "sra\t%1, 31, %3\n\twr\t%3, 0, %%y\n\tld\t%2, %3\n\tnop\n\tnop\n\tsdiv\t%1, %3, %0";
5698 [(set_attr "type" "multi")
5699 (set (attr "length")
5700 (if_then_else (eq_attr "isa" "v9")
5701 (const_int 4) (const_int 6)))])
5703 (define_insn "divsi3_sp64"
5704 [(set (match_operand:SI 0 "register_operand" "=r")
5705 (div:SI (match_operand:SI 1 "register_operand" "r")
5706 (match_operand:SI 2 "input_operand" "rI")))
5707 (use (match_operand:SI 3 "register_operand" "r"))]
5708 "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
5709 "wr\t%%g0, %3, %%y\n\tsdiv\t%1, %2, %0"
5710 [(set_attr "type" "multi")
5711 (set_attr "length" "2")])
5713 (define_insn "divdi3"
5714 [(set (match_operand:DI 0 "register_operand" "=r")
5715 (div:DI (match_operand:DI 1 "register_operand" "r")
5716 (match_operand:DI 2 "arith_double_operand" "rHI")))]
5719 [(set_attr "type" "idiv")])
5721 (define_insn "*cmp_sdiv_cc_set"
5723 (compare:CC (div:SI (match_operand:SI 1 "register_operand" "r")
5724 (match_operand:SI 2 "arith_operand" "rI"))
5726 (set (match_operand:SI 0 "register_operand" "=r")
5727 (div:SI (match_dup 1) (match_dup 2)))
5728 (clobber (match_scratch:SI 3 "=&r"))]
5729 "TARGET_V8 || TARGET_DEPRECATED_V8_INSNS"
5732 return "sra\t%1, 31, %3\n\twr\t%3, 0, %%y\n\tsdivcc\t%1, %2, %0";
5734 return "sra\t%1, 31, %3\n\twr\t%3, 0, %%y\n\tnop\n\tnop\n\tnop\n\tsdivcc\t%1, %2, %0";
5736 [(set_attr "type" "multi")
5737 (set (attr "length")
5738 (if_then_else (eq_attr "isa" "v9")
5739 (const_int 3) (const_int 6)))])
5742 (define_expand "udivsi3"
5743 [(set (match_operand:SI 0 "register_operand" "")
5744 (udiv:SI (match_operand:SI 1 "reg_or_nonsymb_mem_operand" "")
5745 (match_operand:SI 2 "input_operand" "")))]
5746 "TARGET_V8 || TARGET_DEPRECATED_V8_INSNS"
5749 (define_insn "udivsi3_sp32"
5750 [(set (match_operand:SI 0 "register_operand" "=r,&r,&r")
5751 (udiv:SI (match_operand:SI 1 "reg_or_nonsymb_mem_operand" "r,r,m")
5752 (match_operand:SI 2 "input_operand" "rI,m,r")))]
5754 || TARGET_DEPRECATED_V8_INSNS)
5757 output_asm_insn ("wr\t%%g0, %%g0, %%y", operands);
5758 switch (which_alternative)
5761 return "nop\n\tnop\n\tnop\n\tudiv\t%1, %2, %0";
5763 return "ld\t%2, %0\n\tnop\n\tnop\n\tudiv\t%1, %0, %0";
5765 return "ld\t%1, %0\n\tnop\n\tnop\n\tudiv\t%0, %2, %0";
5768 [(set_attr "type" "multi")
5769 (set_attr "length" "5")])
5771 (define_insn "udivsi3_sp64"
5772 [(set (match_operand:SI 0 "register_operand" "=r")
5773 (udiv:SI (match_operand:SI 1 "reg_or_nonsymb_mem_operand" "r")
5774 (match_operand:SI 2 "input_operand" "rI")))]
5775 "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
5776 "wr\t%%g0, 0, %%y\n\tudiv\t%1, %2, %0"
5777 [(set_attr "type" "multi")
5778 (set_attr "length" "2")])
5780 (define_insn "udivdi3"
5781 [(set (match_operand:DI 0 "register_operand" "=r")
5782 (udiv:DI (match_operand:DI 1 "register_operand" "r")
5783 (match_operand:DI 2 "arith_double_operand" "rHI")))]
5786 [(set_attr "type" "idiv")])
5788 (define_insn "*cmp_udiv_cc_set"
5790 (compare:CC (udiv:SI (match_operand:SI 1 "register_operand" "r")
5791 (match_operand:SI 2 "arith_operand" "rI"))
5793 (set (match_operand:SI 0 "register_operand" "=r")
5794 (udiv:SI (match_dup 1) (match_dup 2)))]
5796 || TARGET_DEPRECATED_V8_INSNS"
5799 return "wr\t%%g0, %%g0, %%y\n\tudivcc\t%1, %2, %0";
5801 return "wr\t%%g0, %%g0, %%y\n\tnop\n\tnop\n\tnop\n\tudivcc\t%1, %2, %0";
5803 [(set_attr "type" "multi")
5804 (set (attr "length")
5805 (if_then_else (eq_attr "isa" "v9")
5806 (const_int 2) (const_int 5)))])
5808 ; sparclet multiply/accumulate insns
5810 (define_insn "*smacsi"
5811 [(set (match_operand:SI 0 "register_operand" "=r")
5812 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "%r")
5813 (match_operand:SI 2 "arith_operand" "rI"))
5814 (match_operand:SI 3 "register_operand" "0")))]
5817 [(set_attr "type" "imul")])
5819 (define_insn "*smacdi"
5820 [(set (match_operand:DI 0 "register_operand" "=r")
5821 (plus:DI (mult:DI (sign_extend:DI
5822 (match_operand:SI 1 "register_operand" "%r"))
5824 (match_operand:SI 2 "register_operand" "r")))
5825 (match_operand:DI 3 "register_operand" "0")))]
5827 "smacd\t%1, %2, %L0"
5828 [(set_attr "type" "imul")])
5830 (define_insn "*umacdi"
5831 [(set (match_operand:DI 0 "register_operand" "=r")
5832 (plus:DI (mult:DI (zero_extend:DI
5833 (match_operand:SI 1 "register_operand" "%r"))
5835 (match_operand:SI 2 "register_operand" "r")))
5836 (match_operand:DI 3 "register_operand" "0")))]
5838 "umacd\t%1, %2, %L0"
5839 [(set_attr "type" "imul")])
5841 ;;- Boolean instructions
5842 ;; We define DImode `and' so with DImode `not' we can get
5843 ;; DImode `andn'. Other combinations are possible.
5845 (define_expand "anddi3"
5846 [(set (match_operand:DI 0 "register_operand" "")
5847 (and:DI (match_operand:DI 1 "arith_double_operand" "")
5848 (match_operand:DI 2 "arith_double_operand" "")))]
5852 (define_insn "*anddi3_sp32"
5853 [(set (match_operand:DI 0 "register_operand" "=r,b")
5854 (and:DI (match_operand:DI 1 "arith_double_operand" "%r,b")
5855 (match_operand:DI 2 "arith_double_operand" "rHI,b")))]
5860 [(set_attr "type" "*,fga")
5861 (set_attr "length" "2,*")
5862 (set_attr "fptype" "double")])
5864 (define_insn "*anddi3_sp64"
5865 [(set (match_operand:DI 0 "register_operand" "=r,b")
5866 (and:DI (match_operand:DI 1 "arith_double_operand" "%r,b")
5867 (match_operand:DI 2 "arith_double_operand" "rHI,b")))]
5872 [(set_attr "type" "*,fga")
5873 (set_attr "fptype" "double")])
5875 (define_insn "andsi3"
5876 [(set (match_operand:SI 0 "register_operand" "=r,d")
5877 (and:SI (match_operand:SI 1 "arith_operand" "%r,d")
5878 (match_operand:SI 2 "arith_operand" "rI,d")))]
5883 [(set_attr "type" "*,fga")])
5886 [(set (match_operand:SI 0 "register_operand" "")
5887 (and:SI (match_operand:SI 1 "register_operand" "")
5888 (match_operand:SI 2 "" "")))
5889 (clobber (match_operand:SI 3 "register_operand" ""))]
5890 "GET_CODE (operands[2]) == CONST_INT
5891 && !SMALL_INT32 (operands[2])
5892 && (INTVAL (operands[2]) & 0x3ff) == 0x3ff"
5893 [(set (match_dup 3) (match_dup 4))
5894 (set (match_dup 0) (and:SI (not:SI (match_dup 3)) (match_dup 1)))]
5896 operands[4] = GEN_INT (~INTVAL (operands[2]));
5899 ;; Split DImode logical operations requiring two instructions.
5901 [(set (match_operand:DI 0 "register_operand" "")
5902 (match_operator:DI 1 "cc_arithop" ; AND, IOR, XOR
5903 [(match_operand:DI 2 "register_operand" "")
5904 (match_operand:DI 3 "arith_double_operand" "")]))]
5907 && ((GET_CODE (operands[0]) == REG
5908 && REGNO (operands[0]) < 32)
5909 || (GET_CODE (operands[0]) == SUBREG
5910 && GET_CODE (SUBREG_REG (operands[0])) == REG
5911 && REGNO (SUBREG_REG (operands[0])) < 32))"
5912 [(set (match_dup 4) (match_op_dup:SI 1 [(match_dup 6) (match_dup 8)]))
5913 (set (match_dup 5) (match_op_dup:SI 1 [(match_dup 7) (match_dup 9)]))]
5915 operands[4] = gen_highpart (SImode, operands[0]);
5916 operands[5] = gen_lowpart (SImode, operands[0]);
5917 operands[6] = gen_highpart (SImode, operands[2]);
5918 operands[7] = gen_lowpart (SImode, operands[2]);
5919 #if HOST_BITS_PER_WIDE_INT == 32
5920 if (GET_CODE (operands[3]) == CONST_INT)
5922 if (INTVAL (operands[3]) < 0)
5923 operands[8] = constm1_rtx;
5925 operands[8] = const0_rtx;
5929 operands[8] = gen_highpart_mode (SImode, DImode, operands[3]);
5930 operands[9] = gen_lowpart (SImode, operands[3]);
5933 (define_insn_and_split "*and_not_di_sp32"
5934 [(set (match_operand:DI 0 "register_operand" "=r,b")
5935 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r,b"))
5936 (match_operand:DI 2 "register_operand" "r,b")))]
5940 fandnot1\t%1, %2, %0"
5941 "&& reload_completed
5942 && ((GET_CODE (operands[0]) == REG
5943 && REGNO (operands[0]) < 32)
5944 || (GET_CODE (operands[0]) == SUBREG
5945 && GET_CODE (SUBREG_REG (operands[0])) == REG
5946 && REGNO (SUBREG_REG (operands[0])) < 32))"
5947 [(set (match_dup 3) (and:SI (not:SI (match_dup 4)) (match_dup 5)))
5948 (set (match_dup 6) (and:SI (not:SI (match_dup 7)) (match_dup 8)))]
5949 "operands[3] = gen_highpart (SImode, operands[0]);
5950 operands[4] = gen_highpart (SImode, operands[1]);
5951 operands[5] = gen_highpart (SImode, operands[2]);
5952 operands[6] = gen_lowpart (SImode, operands[0]);
5953 operands[7] = gen_lowpart (SImode, operands[1]);
5954 operands[8] = gen_lowpart (SImode, operands[2]);"
5955 [(set_attr "type" "*,fga")
5956 (set_attr "length" "2,*")
5957 (set_attr "fptype" "double")])
5959 (define_insn "*and_not_di_sp64"
5960 [(set (match_operand:DI 0 "register_operand" "=r,b")
5961 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r,b"))
5962 (match_operand:DI 2 "register_operand" "r,b")))]
5966 fandnot1\t%1, %2, %0"
5967 [(set_attr "type" "*,fga")
5968 (set_attr "fptype" "double")])
5970 (define_insn "*and_not_si"
5971 [(set (match_operand:SI 0 "register_operand" "=r,d")
5972 (and:SI (not:SI (match_operand:SI 1 "register_operand" "r,d"))
5973 (match_operand:SI 2 "register_operand" "r,d")))]
5977 fandnot1s\t%1, %2, %0"
5978 [(set_attr "type" "*,fga")])
5980 (define_expand "iordi3"
5981 [(set (match_operand:DI 0 "register_operand" "")
5982 (ior:DI (match_operand:DI 1 "arith_double_operand" "")
5983 (match_operand:DI 2 "arith_double_operand" "")))]
5987 (define_insn "*iordi3_sp32"
5988 [(set (match_operand:DI 0 "register_operand" "=r,b")
5989 (ior:DI (match_operand:DI 1 "arith_double_operand" "%r,b")
5990 (match_operand:DI 2 "arith_double_operand" "rHI,b")))]
5995 [(set_attr "type" "*,fga")
5996 (set_attr "length" "2,*")
5997 (set_attr "fptype" "double")])
5999 (define_insn "*iordi3_sp64"
6000 [(set (match_operand:DI 0 "register_operand" "=r,b")
6001 (ior:DI (match_operand:DI 1 "arith_double_operand" "%r,b")
6002 (match_operand:DI 2 "arith_double_operand" "rHI,b")))]
6007 [(set_attr "type" "*,fga")
6008 (set_attr "fptype" "double")])
6010 (define_insn "iorsi3"
6011 [(set (match_operand:SI 0 "register_operand" "=r,d")
6012 (ior:SI (match_operand:SI 1 "arith_operand" "%r,d")
6013 (match_operand:SI 2 "arith_operand" "rI,d")))]
6018 [(set_attr "type" "*,fga")])
6021 [(set (match_operand:SI 0 "register_operand" "")
6022 (ior:SI (match_operand:SI 1 "register_operand" "")
6023 (match_operand:SI 2 "" "")))
6024 (clobber (match_operand:SI 3 "register_operand" ""))]
6025 "GET_CODE (operands[2]) == CONST_INT
6026 && !SMALL_INT32 (operands[2])
6027 && (INTVAL (operands[2]) & 0x3ff) == 0x3ff"
6028 [(set (match_dup 3) (match_dup 4))
6029 (set (match_dup 0) (ior:SI (not:SI (match_dup 3)) (match_dup 1)))]
6031 operands[4] = GEN_INT (~INTVAL (operands[2]));
6034 (define_insn_and_split "*or_not_di_sp32"
6035 [(set (match_operand:DI 0 "register_operand" "=r,b")
6036 (ior:DI (not:DI (match_operand:DI 1 "register_operand" "r,b"))
6037 (match_operand:DI 2 "register_operand" "r,b")))]
6041 fornot1\t%1, %2, %0"
6042 "&& reload_completed
6043 && ((GET_CODE (operands[0]) == REG
6044 && REGNO (operands[0]) < 32)
6045 || (GET_CODE (operands[0]) == SUBREG
6046 && GET_CODE (SUBREG_REG (operands[0])) == REG
6047 && REGNO (SUBREG_REG (operands[0])) < 32))"
6048 [(set (match_dup 3) (ior:SI (not:SI (match_dup 4)) (match_dup 5)))
6049 (set (match_dup 6) (ior:SI (not:SI (match_dup 7)) (match_dup 8)))]
6050 "operands[3] = gen_highpart (SImode, operands[0]);
6051 operands[4] = gen_highpart (SImode, operands[1]);
6052 operands[5] = gen_highpart (SImode, operands[2]);
6053 operands[6] = gen_lowpart (SImode, operands[0]);
6054 operands[7] = gen_lowpart (SImode, operands[1]);
6055 operands[8] = gen_lowpart (SImode, operands[2]);"
6056 [(set_attr "type" "*,fga")
6057 (set_attr "length" "2,*")
6058 (set_attr "fptype" "double")])
6060 (define_insn "*or_not_di_sp64"
6061 [(set (match_operand:DI 0 "register_operand" "=r,b")
6062 (ior:DI (not:DI (match_operand:DI 1 "register_operand" "r,b"))
6063 (match_operand:DI 2 "register_operand" "r,b")))]
6067 fornot1\t%1, %2, %0"
6068 [(set_attr "type" "*,fga")
6069 (set_attr "fptype" "double")])
6071 (define_insn "*or_not_si"
6072 [(set (match_operand:SI 0 "register_operand" "=r,d")
6073 (ior:SI (not:SI (match_operand:SI 1 "register_operand" "r,d"))
6074 (match_operand:SI 2 "register_operand" "r,d")))]
6078 fornot1s\t%1, %2, %0"
6079 [(set_attr "type" "*,fga")])
6081 (define_expand "xordi3"
6082 [(set (match_operand:DI 0 "register_operand" "")
6083 (xor:DI (match_operand:DI 1 "arith_double_operand" "")
6084 (match_operand:DI 2 "arith_double_operand" "")))]
6088 (define_insn "*xordi3_sp32"
6089 [(set (match_operand:DI 0 "register_operand" "=r,b")
6090 (xor:DI (match_operand:DI 1 "arith_double_operand" "%r,b")
6091 (match_operand:DI 2 "arith_double_operand" "rHI,b")))]
6096 [(set_attr "type" "*,fga")
6097 (set_attr "length" "2,*")
6098 (set_attr "fptype" "double")])
6100 (define_insn "*xordi3_sp64"
6101 [(set (match_operand:DI 0 "register_operand" "=r,b")
6102 (xor:DI (match_operand:DI 1 "arith_double_operand" "%rJ,b")
6103 (match_operand:DI 2 "arith_double_operand" "rHI,b")))]
6108 [(set_attr "type" "*,fga")
6109 (set_attr "fptype" "double")])
6111 (define_insn "*xordi3_sp64_dbl"
6112 [(set (match_operand:DI 0 "register_operand" "=r")
6113 (xor:DI (match_operand:DI 1 "register_operand" "r")
6114 (match_operand:DI 2 "const64_operand" "")))]
6116 && HOST_BITS_PER_WIDE_INT != 64)"
6119 (define_insn "xorsi3"
6120 [(set (match_operand:SI 0 "register_operand" "=r,d")
6121 (xor:SI (match_operand:SI 1 "arith_operand" "%rJ,d")
6122 (match_operand:SI 2 "arith_operand" "rI,d")))]
6127 [(set_attr "type" "*,fga")])
6130 [(set (match_operand:SI 0 "register_operand" "")
6131 (xor:SI (match_operand:SI 1 "register_operand" "")
6132 (match_operand:SI 2 "" "")))
6133 (clobber (match_operand:SI 3 "register_operand" ""))]
6134 "GET_CODE (operands[2]) == CONST_INT
6135 && !SMALL_INT32 (operands[2])
6136 && (INTVAL (operands[2]) & 0x3ff) == 0x3ff"
6137 [(set (match_dup 3) (match_dup 4))
6138 (set (match_dup 0) (not:SI (xor:SI (match_dup 3) (match_dup 1))))]
6140 operands[4] = GEN_INT (~INTVAL (operands[2]));
6144 [(set (match_operand:SI 0 "register_operand" "")
6145 (not:SI (xor:SI (match_operand:SI 1 "register_operand" "")
6146 (match_operand:SI 2 "" ""))))
6147 (clobber (match_operand:SI 3 "register_operand" ""))]
6148 "GET_CODE (operands[2]) == CONST_INT
6149 && !SMALL_INT32 (operands[2])
6150 && (INTVAL (operands[2]) & 0x3ff) == 0x3ff"
6151 [(set (match_dup 3) (match_dup 4))
6152 (set (match_dup 0) (xor:SI (match_dup 3) (match_dup 1)))]
6154 operands[4] = GEN_INT (~INTVAL (operands[2]));
6157 ;; xnor patterns. Note that (a ^ ~b) == (~a ^ b) == ~(a ^ b).
6158 ;; Combine now canonicalizes to the rightmost expression.
6159 (define_insn_and_split "*xor_not_di_sp32"
6160 [(set (match_operand:DI 0 "register_operand" "=r,b")
6161 (not:DI (xor:DI (match_operand:DI 1 "register_operand" "r,b")
6162 (match_operand:DI 2 "register_operand" "r,b"))))]
6167 "&& reload_completed
6168 && ((GET_CODE (operands[0]) == REG
6169 && REGNO (operands[0]) < 32)
6170 || (GET_CODE (operands[0]) == SUBREG
6171 && GET_CODE (SUBREG_REG (operands[0])) == REG
6172 && REGNO (SUBREG_REG (operands[0])) < 32))"
6173 [(set (match_dup 3) (not:SI (xor:SI (match_dup 4) (match_dup 5))))
6174 (set (match_dup 6) (not:SI (xor:SI (match_dup 7) (match_dup 8))))]
6175 "operands[3] = gen_highpart (SImode, operands[0]);
6176 operands[4] = gen_highpart (SImode, operands[1]);
6177 operands[5] = gen_highpart (SImode, operands[2]);
6178 operands[6] = gen_lowpart (SImode, operands[0]);
6179 operands[7] = gen_lowpart (SImode, operands[1]);
6180 operands[8] = gen_lowpart (SImode, operands[2]);"
6181 [(set_attr "type" "*,fga")
6182 (set_attr "length" "2,*")
6183 (set_attr "fptype" "double")])
6185 (define_insn "*xor_not_di_sp64"
6186 [(set (match_operand:DI 0 "register_operand" "=r,b")
6187 (not:DI (xor:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,b")
6188 (match_operand:DI 2 "arith_double_operand" "rHI,b"))))]
6193 [(set_attr "type" "*,fga")
6194 (set_attr "fptype" "double")])
6196 (define_insn "*xor_not_si"
6197 [(set (match_operand:SI 0 "register_operand" "=r,d")
6198 (not:SI (xor:SI (match_operand:SI 1 "reg_or_0_operand" "rJ,d")
6199 (match_operand:SI 2 "arith_operand" "rI,d"))))]
6204 [(set_attr "type" "*,fga")])
6206 ;; These correspond to the above in the case where we also (or only)
6207 ;; want to set the condition code.
6209 (define_insn "*cmp_cc_arith_op"
6212 (match_operator:SI 2 "cc_arithop"
6213 [(match_operand:SI 0 "arith_operand" "%r")
6214 (match_operand:SI 1 "arith_operand" "rI")])
6217 "%A2cc\t%0, %1, %%g0"
6218 [(set_attr "type" "compare")])
6220 (define_insn "*cmp_ccx_arith_op"
6223 (match_operator:DI 2 "cc_arithop"
6224 [(match_operand:DI 0 "arith_double_operand" "%r")
6225 (match_operand:DI 1 "arith_double_operand" "rHI")])
6228 "%A2cc\t%0, %1, %%g0"
6229 [(set_attr "type" "compare")])
6231 (define_insn "*cmp_cc_arith_op_set"
6234 (match_operator:SI 3 "cc_arithop"
6235 [(match_operand:SI 1 "arith_operand" "%r")
6236 (match_operand:SI 2 "arith_operand" "rI")])
6238 (set (match_operand:SI 0 "register_operand" "=r")
6239 (match_operator:SI 4 "cc_arithop" [(match_dup 1) (match_dup 2)]))]
6240 "GET_CODE (operands[3]) == GET_CODE (operands[4])"
6242 [(set_attr "type" "compare")])
6244 (define_insn "*cmp_ccx_arith_op_set"
6247 (match_operator:DI 3 "cc_arithop"
6248 [(match_operand:DI 1 "arith_double_operand" "%r")
6249 (match_operand:DI 2 "arith_double_operand" "rHI")])
6251 (set (match_operand:DI 0 "register_operand" "=r")
6252 (match_operator:DI 4 "cc_arithop" [(match_dup 1) (match_dup 2)]))]
6253 "TARGET_ARCH64 && GET_CODE (operands[3]) == GET_CODE (operands[4])"
6255 [(set_attr "type" "compare")])
6257 (define_insn "*cmp_cc_xor_not"
6260 (not:SI (xor:SI (match_operand:SI 0 "reg_or_0_operand" "%rJ")
6261 (match_operand:SI 1 "arith_operand" "rI")))
6264 "xnorcc\t%r0, %1, %%g0"
6265 [(set_attr "type" "compare")])
6267 (define_insn "*cmp_ccx_xor_not"
6270 (not:DI (xor:DI (match_operand:DI 0 "reg_or_0_operand" "%rJ")
6271 (match_operand:DI 1 "arith_double_operand" "rHI")))
6274 "xnorcc\t%r0, %1, %%g0"
6275 [(set_attr "type" "compare")])
6277 (define_insn "*cmp_cc_xor_not_set"
6280 (not:SI (xor:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
6281 (match_operand:SI 2 "arith_operand" "rI")))
6283 (set (match_operand:SI 0 "register_operand" "=r")
6284 (not:SI (xor:SI (match_dup 1) (match_dup 2))))]
6286 "xnorcc\t%r1, %2, %0"
6287 [(set_attr "type" "compare")])
6289 (define_insn "*cmp_ccx_xor_not_set"
6292 (not:DI (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
6293 (match_operand:DI 2 "arith_double_operand" "rHI")))
6295 (set (match_operand:DI 0 "register_operand" "=r")
6296 (not:DI (xor:DI (match_dup 1) (match_dup 2))))]
6298 "xnorcc\t%r1, %2, %0"
6299 [(set_attr "type" "compare")])
6301 (define_insn "*cmp_cc_arith_op_not"
6304 (match_operator:SI 2 "cc_arithopn"
6305 [(not:SI (match_operand:SI 0 "arith_operand" "rI"))
6306 (match_operand:SI 1 "reg_or_0_operand" "rJ")])
6309 "%B2cc\t%r1, %0, %%g0"
6310 [(set_attr "type" "compare")])
6312 (define_insn "*cmp_ccx_arith_op_not"
6315 (match_operator:DI 2 "cc_arithopn"
6316 [(not:DI (match_operand:DI 0 "arith_double_operand" "rHI"))
6317 (match_operand:DI 1 "reg_or_0_operand" "rJ")])
6320 "%B2cc\t%r1, %0, %%g0"
6321 [(set_attr "type" "compare")])
6323 (define_insn "*cmp_cc_arith_op_not_set"
6326 (match_operator:SI 3 "cc_arithopn"
6327 [(not:SI (match_operand:SI 1 "arith_operand" "rI"))
6328 (match_operand:SI 2 "reg_or_0_operand" "rJ")])
6330 (set (match_operand:SI 0 "register_operand" "=r")
6331 (match_operator:SI 4 "cc_arithopn"
6332 [(not:SI (match_dup 1)) (match_dup 2)]))]
6333 "GET_CODE (operands[3]) == GET_CODE (operands[4])"
6334 "%B3cc\t%r2, %1, %0"
6335 [(set_attr "type" "compare")])
6337 (define_insn "*cmp_ccx_arith_op_not_set"
6340 (match_operator:DI 3 "cc_arithopn"
6341 [(not:DI (match_operand:DI 1 "arith_double_operand" "rHI"))
6342 (match_operand:DI 2 "reg_or_0_operand" "rJ")])
6344 (set (match_operand:DI 0 "register_operand" "=r")
6345 (match_operator:DI 4 "cc_arithopn"
6346 [(not:DI (match_dup 1)) (match_dup 2)]))]
6347 "TARGET_ARCH64 && GET_CODE (operands[3]) == GET_CODE (operands[4])"
6348 "%B3cc\t%r2, %1, %0"
6349 [(set_attr "type" "compare")])
6351 ;; We cannot use the "neg" pseudo insn because the Sun assembler
6352 ;; does not know how to make it work for constants.
6354 (define_expand "negdi2"
6355 [(set (match_operand:DI 0 "register_operand" "=r")
6356 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
6359 if (! TARGET_ARCH64)
6361 emit_insn (gen_rtx_PARALLEL
6364 gen_rtx_SET (VOIDmode, operand0,
6365 gen_rtx_NEG (DImode, operand1)),
6366 gen_rtx_CLOBBER (VOIDmode,
6367 gen_rtx_REG (CCmode,
6373 (define_insn_and_split "*negdi2_sp32"
6374 [(set (match_operand:DI 0 "register_operand" "=r")
6375 (neg:DI (match_operand:DI 1 "register_operand" "r")))
6376 (clobber (reg:CC 100))]
6379 "&& reload_completed"
6380 [(parallel [(set (reg:CC_NOOV 100)
6381 (compare:CC_NOOV (minus:SI (const_int 0) (match_dup 5))
6383 (set (match_dup 4) (minus:SI (const_int 0) (match_dup 5)))])
6384 (set (match_dup 2) (minus:SI (minus:SI (const_int 0) (match_dup 3))
6385 (ltu:SI (reg:CC 100) (const_int 0))))]
6386 "operands[2] = gen_highpart (SImode, operands[0]);
6387 operands[3] = gen_highpart (SImode, operands[1]);
6388 operands[4] = gen_lowpart (SImode, operands[0]);
6389 operands[5] = gen_lowpart (SImode, operands[1]);"
6390 [(set_attr "length" "2")])
6392 (define_insn "*negdi2_sp64"
6393 [(set (match_operand:DI 0 "register_operand" "=r")
6394 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
6396 "sub\t%%g0, %1, %0")
6398 (define_insn "negsi2"
6399 [(set (match_operand:SI 0 "register_operand" "=r")
6400 (neg:SI (match_operand:SI 1 "arith_operand" "rI")))]
6402 "sub\t%%g0, %1, %0")
6404 (define_insn "*cmp_cc_neg"
6405 [(set (reg:CC_NOOV 100)
6406 (compare:CC_NOOV (neg:SI (match_operand:SI 0 "arith_operand" "rI"))
6409 "subcc\t%%g0, %0, %%g0"
6410 [(set_attr "type" "compare")])
6412 (define_insn "*cmp_ccx_neg"
6413 [(set (reg:CCX_NOOV 100)
6414 (compare:CCX_NOOV (neg:DI (match_operand:DI 0 "arith_double_operand" "rHI"))
6417 "subcc\t%%g0, %0, %%g0"
6418 [(set_attr "type" "compare")])
6420 (define_insn "*cmp_cc_set_neg"
6421 [(set (reg:CC_NOOV 100)
6422 (compare:CC_NOOV (neg:SI (match_operand:SI 1 "arith_operand" "rI"))
6424 (set (match_operand:SI 0 "register_operand" "=r")
6425 (neg:SI (match_dup 1)))]
6427 "subcc\t%%g0, %1, %0"
6428 [(set_attr "type" "compare")])
6430 (define_insn "*cmp_ccx_set_neg"
6431 [(set (reg:CCX_NOOV 100)
6432 (compare:CCX_NOOV (neg:DI (match_operand:DI 1 "arith_double_operand" "rHI"))
6434 (set (match_operand:DI 0 "register_operand" "=r")
6435 (neg:DI (match_dup 1)))]
6437 "subcc\t%%g0, %1, %0"
6438 [(set_attr "type" "compare")])
6440 ;; We cannot use the "not" pseudo insn because the Sun assembler
6441 ;; does not know how to make it work for constants.
6442 (define_expand "one_cmpldi2"
6443 [(set (match_operand:DI 0 "register_operand" "")
6444 (not:DI (match_operand:DI 1 "register_operand" "")))]
6448 (define_insn_and_split "*one_cmpldi2_sp32"
6449 [(set (match_operand:DI 0 "register_operand" "=r,b")
6450 (not:DI (match_operand:DI 1 "register_operand" "r,b")))]
6455 "&& reload_completed
6456 && ((GET_CODE (operands[0]) == REG
6457 && REGNO (operands[0]) < 32)
6458 || (GET_CODE (operands[0]) == SUBREG
6459 && GET_CODE (SUBREG_REG (operands[0])) == REG
6460 && REGNO (SUBREG_REG (operands[0])) < 32))"
6461 [(set (match_dup 2) (not:SI (xor:SI (match_dup 3) (const_int 0))))
6462 (set (match_dup 4) (not:SI (xor:SI (match_dup 5) (const_int 0))))]
6463 "operands[2] = gen_highpart (SImode, operands[0]);
6464 operands[3] = gen_highpart (SImode, operands[1]);
6465 operands[4] = gen_lowpart (SImode, operands[0]);
6466 operands[5] = gen_lowpart (SImode, operands[1]);"
6467 [(set_attr "type" "*,fga")
6468 (set_attr "length" "2,*")
6469 (set_attr "fptype" "double")])
6471 (define_insn "*one_cmpldi2_sp64"
6472 [(set (match_operand:DI 0 "register_operand" "=r,b")
6473 (not:DI (match_operand:DI 1 "arith_double_operand" "rHI,b")))]
6478 [(set_attr "type" "*,fga")
6479 (set_attr "fptype" "double")])
6481 (define_insn "one_cmplsi2"
6482 [(set (match_operand:SI 0 "register_operand" "=r,d")
6483 (not:SI (match_operand:SI 1 "arith_operand" "rI,d")))]
6488 [(set_attr "type" "*,fga")])
6490 (define_insn "*cmp_cc_not"
6492 (compare:CC (not:SI (match_operand:SI 0 "arith_operand" "rI"))
6495 "xnorcc\t%%g0, %0, %%g0"
6496 [(set_attr "type" "compare")])
6498 (define_insn "*cmp_ccx_not"
6500 (compare:CCX (not:DI (match_operand:DI 0 "arith_double_operand" "rHI"))
6503 "xnorcc\t%%g0, %0, %%g0"
6504 [(set_attr "type" "compare")])
6506 (define_insn "*cmp_cc_set_not"
6508 (compare:CC (not:SI (match_operand:SI 1 "arith_operand" "rI"))
6510 (set (match_operand:SI 0 "register_operand" "=r")
6511 (not:SI (match_dup 1)))]
6513 "xnorcc\t%%g0, %1, %0"
6514 [(set_attr "type" "compare")])
6516 (define_insn "*cmp_ccx_set_not"
6518 (compare:CCX (not:DI (match_operand:DI 1 "arith_double_operand" "rHI"))
6520 (set (match_operand:DI 0 "register_operand" "=r")
6521 (not:DI (match_dup 1)))]
6523 "xnorcc\t%%g0, %1, %0"
6524 [(set_attr "type" "compare")])
6526 (define_insn "*cmp_cc_set"
6527 [(set (match_operand:SI 0 "register_operand" "=r")
6528 (match_operand:SI 1 "register_operand" "r"))
6530 (compare:CC (match_dup 1)
6534 [(set_attr "type" "compare")])
6536 (define_insn "*cmp_ccx_set64"
6537 [(set (match_operand:DI 0 "register_operand" "=r")
6538 (match_operand:DI 1 "register_operand" "r"))
6540 (compare:CCX (match_dup 1)
6544 [(set_attr "type" "compare")])
6546 ;; Floating point arithmetic instructions.
6548 (define_expand "addtf3"
6549 [(set (match_operand:TF 0 "nonimmediate_operand" "")
6550 (plus:TF (match_operand:TF 1 "general_operand" "")
6551 (match_operand:TF 2 "general_operand" "")))]
6552 "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
6553 "emit_tfmode_binop (PLUS, operands); DONE;")
6555 (define_insn "*addtf3_hq"
6556 [(set (match_operand:TF 0 "register_operand" "=e")
6557 (plus:TF (match_operand:TF 1 "register_operand" "e")
6558 (match_operand:TF 2 "register_operand" "e")))]
6559 "TARGET_FPU && TARGET_HARD_QUAD"
6561 [(set_attr "type" "fp")])
6563 (define_insn "adddf3"
6564 [(set (match_operand:DF 0 "register_operand" "=e")
6565 (plus:DF (match_operand:DF 1 "register_operand" "e")
6566 (match_operand:DF 2 "register_operand" "e")))]
6569 [(set_attr "type" "fp")
6570 (set_attr "fptype" "double")])
6572 (define_insn "addsf3"
6573 [(set (match_operand:SF 0 "register_operand" "=f")
6574 (plus:SF (match_operand:SF 1 "register_operand" "f")
6575 (match_operand:SF 2 "register_operand" "f")))]
6578 [(set_attr "type" "fp")])
6580 (define_expand "subtf3"
6581 [(set (match_operand:TF 0 "nonimmediate_operand" "")
6582 (minus:TF (match_operand:TF 1 "general_operand" "")
6583 (match_operand:TF 2 "general_operand" "")))]
6584 "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
6585 "emit_tfmode_binop (MINUS, operands); DONE;")
6587 (define_insn "*subtf3_hq"
6588 [(set (match_operand:TF 0 "register_operand" "=e")
6589 (minus:TF (match_operand:TF 1 "register_operand" "e")
6590 (match_operand:TF 2 "register_operand" "e")))]
6591 "TARGET_FPU && TARGET_HARD_QUAD"
6593 [(set_attr "type" "fp")])
6595 (define_insn "subdf3"
6596 [(set (match_operand:DF 0 "register_operand" "=e")
6597 (minus:DF (match_operand:DF 1 "register_operand" "e")
6598 (match_operand:DF 2 "register_operand" "e")))]
6601 [(set_attr "type" "fp")
6602 (set_attr "fptype" "double")])
6604 (define_insn "subsf3"
6605 [(set (match_operand:SF 0 "register_operand" "=f")
6606 (minus:SF (match_operand:SF 1 "register_operand" "f")
6607 (match_operand:SF 2 "register_operand" "f")))]
6610 [(set_attr "type" "fp")])
6612 (define_expand "multf3"
6613 [(set (match_operand:TF 0 "nonimmediate_operand" "")
6614 (mult:TF (match_operand:TF 1 "general_operand" "")
6615 (match_operand:TF 2 "general_operand" "")))]
6616 "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
6617 "emit_tfmode_binop (MULT, operands); DONE;")
6619 (define_insn "*multf3_hq"
6620 [(set (match_operand:TF 0 "register_operand" "=e")
6621 (mult:TF (match_operand:TF 1 "register_operand" "e")
6622 (match_operand:TF 2 "register_operand" "e")))]
6623 "TARGET_FPU && TARGET_HARD_QUAD"
6625 [(set_attr "type" "fpmul")])
6627 (define_insn "muldf3"
6628 [(set (match_operand:DF 0 "register_operand" "=e")
6629 (mult:DF (match_operand:DF 1 "register_operand" "e")
6630 (match_operand:DF 2 "register_operand" "e")))]
6633 [(set_attr "type" "fpmul")
6634 (set_attr "fptype" "double")])
6636 (define_insn "mulsf3"
6637 [(set (match_operand:SF 0 "register_operand" "=f")
6638 (mult:SF (match_operand:SF 1 "register_operand" "f")
6639 (match_operand:SF 2 "register_operand" "f")))]
6642 [(set_attr "type" "fpmul")])
6644 (define_insn "*muldf3_extend"
6645 [(set (match_operand:DF 0 "register_operand" "=e")
6646 (mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "f"))
6647 (float_extend:DF (match_operand:SF 2 "register_operand" "f"))))]
6648 "(TARGET_V8 || TARGET_V9) && TARGET_FPU"
6649 "fsmuld\t%1, %2, %0"
6650 [(set_attr "type" "fpmul")
6651 (set_attr "fptype" "double")])
6653 (define_insn "*multf3_extend"
6654 [(set (match_operand:TF 0 "register_operand" "=e")
6655 (mult:TF (float_extend:TF (match_operand:DF 1 "register_operand" "e"))
6656 (float_extend:TF (match_operand:DF 2 "register_operand" "e"))))]
6657 "(TARGET_V8 || TARGET_V9) && TARGET_FPU && TARGET_HARD_QUAD"
6658 "fdmulq\t%1, %2, %0"
6659 [(set_attr "type" "fpmul")])
6661 (define_expand "divtf3"
6662 [(set (match_operand:TF 0 "nonimmediate_operand" "")
6663 (div:TF (match_operand:TF 1 "general_operand" "")
6664 (match_operand:TF 2 "general_operand" "")))]
6665 "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
6666 "emit_tfmode_binop (DIV, operands); DONE;")
6668 ;; don't have timing for quad-prec. divide.
6669 (define_insn "*divtf3_hq"
6670 [(set (match_operand:TF 0 "register_operand" "=e")
6671 (div:TF (match_operand:TF 1 "register_operand" "e")
6672 (match_operand:TF 2 "register_operand" "e")))]
6673 "TARGET_FPU && TARGET_HARD_QUAD"
6675 [(set_attr "type" "fpdivd")])
6677 (define_insn "divdf3"
6678 [(set (match_operand:DF 0 "register_operand" "=e")
6679 (div:DF (match_operand:DF 1 "register_operand" "e")
6680 (match_operand:DF 2 "register_operand" "e")))]
6683 [(set_attr "type" "fpdivd")
6684 (set_attr "fptype" "double")])
6686 (define_insn "divsf3"
6687 [(set (match_operand:SF 0 "register_operand" "=f")
6688 (div:SF (match_operand:SF 1 "register_operand" "f")
6689 (match_operand:SF 2 "register_operand" "f")))]
6692 [(set_attr "type" "fpdivs")])
6694 (define_expand "negtf2"
6695 [(set (match_operand:TF 0 "register_operand" "=e,e")
6696 (neg:TF (match_operand:TF 1 "register_operand" "0,e")))]
6700 (define_insn_and_split "*negtf2_notv9"
6701 [(set (match_operand:TF 0 "register_operand" "=e,e")
6702 (neg:TF (match_operand:TF 1 "register_operand" "0,e")))]
6703 ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD.
6709 "&& reload_completed
6710 && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
6711 [(set (match_dup 2) (neg:SF (match_dup 3)))
6712 (set (match_dup 4) (match_dup 5))
6713 (set (match_dup 6) (match_dup 7))]
6714 "operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
6715 operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
6716 operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
6717 operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);
6718 operands[6] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2);
6719 operands[7] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);"
6720 [(set_attr "type" "fpmove,*")
6721 (set_attr "length" "*,2")])
6723 (define_insn_and_split "*negtf2_v9"
6724 [(set (match_operand:TF 0 "register_operand" "=e,e")
6725 (neg:TF (match_operand:TF 1 "register_operand" "0,e")))]
6726 ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD.
6727 "TARGET_FPU && TARGET_V9"
6731 "&& reload_completed
6732 && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
6733 [(set (match_dup 2) (neg:DF (match_dup 3)))
6734 (set (match_dup 4) (match_dup 5))]
6735 "operands[2] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]));
6736 operands[3] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]));
6737 operands[4] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2);
6738 operands[5] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);"
6739 [(set_attr "type" "fpmove,*")
6740 (set_attr "length" "*,2")
6741 (set_attr "fptype" "double")])
6743 (define_expand "negdf2"
6744 [(set (match_operand:DF 0 "register_operand" "")
6745 (neg:DF (match_operand:DF 1 "register_operand" "")))]
6749 (define_insn_and_split "*negdf2_notv9"
6750 [(set (match_operand:DF 0 "register_operand" "=e,e")
6751 (neg:DF (match_operand:DF 1 "register_operand" "0,e")))]
6752 "TARGET_FPU && ! TARGET_V9"
6756 "&& reload_completed
6757 && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
6758 [(set (match_dup 2) (neg:SF (match_dup 3)))
6759 (set (match_dup 4) (match_dup 5))]
6760 "operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
6761 operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
6762 operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
6763 operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);"
6764 [(set_attr "type" "fpmove,*")
6765 (set_attr "length" "*,2")])
6767 (define_insn "*negdf2_v9"
6768 [(set (match_operand:DF 0 "register_operand" "=e")
6769 (neg:DF (match_operand:DF 1 "register_operand" "e")))]
6770 "TARGET_FPU && TARGET_V9"
6772 [(set_attr "type" "fpmove")
6773 (set_attr "fptype" "double")])
6775 (define_insn "negsf2"
6776 [(set (match_operand:SF 0 "register_operand" "=f")
6777 (neg:SF (match_operand:SF 1 "register_operand" "f")))]
6780 [(set_attr "type" "fpmove")])
6782 (define_expand "abstf2"
6783 [(set (match_operand:TF 0 "register_operand" "")
6784 (abs:TF (match_operand:TF 1 "register_operand" "")))]
6788 (define_insn_and_split "*abstf2_notv9"
6789 [(set (match_operand:TF 0 "register_operand" "=e,e")
6790 (abs:TF (match_operand:TF 1 "register_operand" "0,e")))]
6791 ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD.
6792 "TARGET_FPU && ! TARGET_V9"
6796 "&& reload_completed
6797 && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
6798 [(set (match_dup 2) (abs:SF (match_dup 3)))
6799 (set (match_dup 4) (match_dup 5))
6800 (set (match_dup 6) (match_dup 7))]
6801 "operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
6802 operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
6803 operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
6804 operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);
6805 operands[6] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2);
6806 operands[7] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);"
6807 [(set_attr "type" "fpmove,*")
6808 (set_attr "length" "*,2")])
6810 (define_insn "*abstf2_hq_v9"
6811 [(set (match_operand:TF 0 "register_operand" "=e,e")
6812 (abs:TF (match_operand:TF 1 "register_operand" "0,e")))]
6813 "TARGET_FPU && TARGET_V9 && TARGET_HARD_QUAD"
6817 [(set_attr "type" "fpmove")
6818 (set_attr "fptype" "double,*")])
6820 (define_insn_and_split "*abstf2_v9"
6821 [(set (match_operand:TF 0 "register_operand" "=e,e")
6822 (abs:TF (match_operand:TF 1 "register_operand" "0,e")))]
6823 "TARGET_FPU && TARGET_V9 && !TARGET_HARD_QUAD"
6827 "&& reload_completed
6828 && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
6829 [(set (match_dup 2) (abs:DF (match_dup 3)))
6830 (set (match_dup 4) (match_dup 5))]
6831 "operands[2] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]));
6832 operands[3] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]));
6833 operands[4] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2);
6834 operands[5] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);"
6835 [(set_attr "type" "fpmove,*")
6836 (set_attr "length" "*,2")
6837 (set_attr "fptype" "double,*")])
6839 (define_expand "absdf2"
6840 [(set (match_operand:DF 0 "register_operand" "")
6841 (abs:DF (match_operand:DF 1 "register_operand" "")))]
6845 (define_insn_and_split "*absdf2_notv9"
6846 [(set (match_operand:DF 0 "register_operand" "=e,e")
6847 (abs:DF (match_operand:DF 1 "register_operand" "0,e")))]
6848 "TARGET_FPU && ! TARGET_V9"
6852 "&& reload_completed
6853 && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
6854 [(set (match_dup 2) (abs:SF (match_dup 3)))
6855 (set (match_dup 4) (match_dup 5))]
6856 "operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
6857 operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
6858 operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
6859 operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);"
6860 [(set_attr "type" "fpmove,*")
6861 (set_attr "length" "*,2")])
6863 (define_insn "*absdf2_v9"
6864 [(set (match_operand:DF 0 "register_operand" "=e")
6865 (abs:DF (match_operand:DF 1 "register_operand" "e")))]
6866 "TARGET_FPU && TARGET_V9"
6868 [(set_attr "type" "fpmove")
6869 (set_attr "fptype" "double")])
6871 (define_insn "abssf2"
6872 [(set (match_operand:SF 0 "register_operand" "=f")
6873 (abs:SF (match_operand:SF 1 "register_operand" "f")))]
6876 [(set_attr "type" "fpmove")])
6878 (define_expand "sqrttf2"
6879 [(set (match_operand:TF 0 "nonimmediate_operand" "")
6880 (sqrt:TF (match_operand:TF 1 "general_operand" "")))]
6881 "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
6882 "emit_tfmode_unop (SQRT, operands); DONE;")
6884 (define_insn "*sqrttf2_hq"
6885 [(set (match_operand:TF 0 "register_operand" "=e")
6886 (sqrt:TF (match_operand:TF 1 "register_operand" "e")))]
6887 "TARGET_FPU && TARGET_HARD_QUAD"
6889 [(set_attr "type" "fpsqrtd")])
6891 (define_insn "sqrtdf2"
6892 [(set (match_operand:DF 0 "register_operand" "=e")
6893 (sqrt:DF (match_operand:DF 1 "register_operand" "e")))]
6896 [(set_attr "type" "fpsqrtd")
6897 (set_attr "fptype" "double")])
6899 (define_insn "sqrtsf2"
6900 [(set (match_operand:SF 0 "register_operand" "=f")
6901 (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
6904 [(set_attr "type" "fpsqrts")])
6906 ;;- arithmetic shift instructions
6908 (define_insn "ashlsi3"
6909 [(set (match_operand:SI 0 "register_operand" "=r")
6910 (ashift:SI (match_operand:SI 1 "register_operand" "r")
6911 (match_operand:SI 2 "arith_operand" "rI")))]
6914 if (operands[2] == const1_rtx)
6915 return "add\t%1, %1, %0";
6916 if (GET_CODE (operands[2]) == CONST_INT)
6917 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
6918 return "sll\t%1, %2, %0";
6921 (if_then_else (match_operand 2 "const1_operand" "")
6922 (const_string "ialu") (const_string "shift")))])
6924 (define_expand "ashldi3"
6925 [(set (match_operand:DI 0 "register_operand" "=r")
6926 (ashift:DI (match_operand:DI 1 "register_operand" "r")
6927 (match_operand:SI 2 "arith_operand" "rI")))]
6928 "TARGET_ARCH64 || TARGET_V8PLUS"
6930 if (! TARGET_ARCH64)
6932 if (GET_CODE (operands[2]) == CONST_INT)
6934 emit_insn (gen_ashldi3_v8plus (operands[0], operands[1], operands[2]));
6939 (define_insn "*ashldi3_sp64"
6940 [(set (match_operand:DI 0 "register_operand" "=r")
6941 (ashift:DI (match_operand:DI 1 "register_operand" "r")
6942 (match_operand:SI 2 "arith_operand" "rI")))]
6945 if (operands[2] == const1_rtx)
6946 return "add\t%1, %1, %0";
6947 if (GET_CODE (operands[2]) == CONST_INT)
6948 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
6949 return "sllx\t%1, %2, %0";
6952 (if_then_else (match_operand 2 "const1_operand" "")
6953 (const_string "ialu") (const_string "shift")))])
6956 (define_insn "ashldi3_v8plus"
6957 [(set (match_operand:DI 0 "register_operand" "=&h,&h,r")
6958 (ashift:DI (match_operand:DI 1 "arith_operand" "rI,0,rI")
6959 (match_operand:SI 2 "arith_operand" "rI,rI,rI")))
6960 (clobber (match_scratch:SI 3 "=X,X,&h"))]
6962 { return sparc_v8plus_shift (operands, insn, "sllx"); }
6963 [(set_attr "type" "multi")
6964 (set_attr "length" "5,5,6")])
6966 ;; Optimize (1LL<<x)-1
6967 ;; XXX this also needs to be fixed to handle equal subregs
6968 ;; XXX first before we could re-enable it.
6970 ; [(set (match_operand:DI 0 "register_operand" "=h")
6971 ; (plus:DI (ashift:DI (const_int 1)
6972 ; (match_operand:SI 1 "arith_operand" "rI"))
6974 ; "0 && TARGET_V8PLUS"
6976 ; if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == REGNO (operands[0]))
6977 ; return "mov\t1, %L0\;sllx\t%L0, %1, %L0\;sub\t%L0, 1, %L0\;srlx\t%L0, 32, %H0";
6978 ; return "mov\t1, %H0\;sllx\t%H0, %1, %L0\;sub\t%L0, 1, %L0\;srlx\t%L0, 32, %H0";
6980 ; [(set_attr "type" "multi")
6981 ; (set_attr "length" "4")])
6983 (define_insn "*cmp_cc_ashift_1"
6984 [(set (reg:CC_NOOV 100)
6985 (compare:CC_NOOV (ashift:SI (match_operand:SI 0 "register_operand" "r")
6989 "addcc\t%0, %0, %%g0"
6990 [(set_attr "type" "compare")])
6992 (define_insn "*cmp_cc_set_ashift_1"
6993 [(set (reg:CC_NOOV 100)
6994 (compare:CC_NOOV (ashift:SI (match_operand:SI 1 "register_operand" "r")
6997 (set (match_operand:SI 0 "register_operand" "=r")
6998 (ashift:SI (match_dup 1) (const_int 1)))]
7001 [(set_attr "type" "compare")])
7003 (define_insn "ashrsi3"
7004 [(set (match_operand:SI 0 "register_operand" "=r")
7005 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
7006 (match_operand:SI 2 "arith_operand" "rI")))]
7009 if (GET_CODE (operands[2]) == CONST_INT)
7010 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
7011 return "sra\t%1, %2, %0";
7013 [(set_attr "type" "shift")])
7015 (define_insn "*ashrsi3_extend"
7016 [(set (match_operand:DI 0 "register_operand" "=r")
7017 (sign_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
7018 (match_operand:SI 2 "arith_operand" "r"))))]
7021 [(set_attr "type" "shift")])
7023 ;; This handles the case as above, but with constant shift instead of
7024 ;; register. Combiner "simplifies" it for us a little bit though.
7025 (define_insn "*ashrsi3_extend2"
7026 [(set (match_operand:DI 0 "register_operand" "=r")
7027 (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 1 "register_operand" "r") 0)
7029 (match_operand:SI 2 "small_int_or_double" "n")))]
7031 && ((GET_CODE (operands[2]) == CONST_INT
7032 && INTVAL (operands[2]) >= 32 && INTVAL (operands[2]) < 64)
7033 || (GET_CODE (operands[2]) == CONST_DOUBLE
7034 && !CONST_DOUBLE_HIGH (operands[2])
7035 && CONST_DOUBLE_LOW (operands[2]) >= 32
7036 && CONST_DOUBLE_LOW (operands[2]) < 64))"
7038 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
7040 return "sra\t%1, %2, %0";
7042 [(set_attr "type" "shift")])
7044 (define_expand "ashrdi3"
7045 [(set (match_operand:DI 0 "register_operand" "=r")
7046 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
7047 (match_operand:SI 2 "arith_operand" "rI")))]
7048 "TARGET_ARCH64 || TARGET_V8PLUS"
7050 if (! TARGET_ARCH64)
7052 if (GET_CODE (operands[2]) == CONST_INT)
7053 FAIL; /* prefer generic code in this case */
7054 emit_insn (gen_ashrdi3_v8plus (operands[0], operands[1], operands[2]));
7059 (define_insn "*ashrdi3_sp64"
7060 [(set (match_operand:DI 0 "register_operand" "=r")
7061 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
7062 (match_operand:SI 2 "arith_operand" "rI")))]
7066 if (GET_CODE (operands[2]) == CONST_INT)
7067 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
7068 return "srax\t%1, %2, %0";
7070 [(set_attr "type" "shift")])
7073 (define_insn "ashrdi3_v8plus"
7074 [(set (match_operand:DI 0 "register_operand" "=&h,&h,r")
7075 (ashiftrt:DI (match_operand:DI 1 "arith_operand" "rI,0,rI")
7076 (match_operand:SI 2 "arith_operand" "rI,rI,rI")))
7077 (clobber (match_scratch:SI 3 "=X,X,&h"))]
7079 { return sparc_v8plus_shift (operands, insn, "srax"); }
7080 [(set_attr "type" "multi")
7081 (set_attr "length" "5,5,6")])
7083 (define_insn "lshrsi3"
7084 [(set (match_operand:SI 0 "register_operand" "=r")
7085 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
7086 (match_operand:SI 2 "arith_operand" "rI")))]
7089 if (GET_CODE (operands[2]) == CONST_INT)
7090 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
7091 return "srl\t%1, %2, %0";
7093 [(set_attr "type" "shift")])
7095 ;; This handles the case where
7096 ;; (zero_extend:DI (lshiftrt:SI (match_operand:SI) (match_operand:SI))),
7097 ;; but combiner "simplifies" it for us.
7098 (define_insn "*lshrsi3_extend"
7099 [(set (match_operand:DI 0 "register_operand" "=r")
7100 (and:DI (subreg:DI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
7101 (match_operand:SI 2 "arith_operand" "r")) 0)
7102 (match_operand 3 "" "")))]
7104 && ((GET_CODE (operands[3]) == CONST_DOUBLE
7105 && CONST_DOUBLE_HIGH (operands[3]) == 0
7106 && CONST_DOUBLE_LOW (operands[3]) == 0xffffffff)
7107 || (HOST_BITS_PER_WIDE_INT >= 64
7108 && GET_CODE (operands[3]) == CONST_INT
7109 && (unsigned HOST_WIDE_INT) INTVAL (operands[3]) == 0xffffffff))"
7111 [(set_attr "type" "shift")])
7113 ;; This handles the case where
7114 ;; (lshiftrt:DI (zero_extend:DI (match_operand:SI)) (const_int >=0 < 32))
7115 ;; but combiner "simplifies" it for us.
7116 (define_insn "*lshrsi3_extend2"
7117 [(set (match_operand:DI 0 "register_operand" "=r")
7118 (zero_extract:DI (subreg:DI (match_operand:SI 1 "register_operand" "r") 0)
7119 (match_operand 2 "small_int_or_double" "n")
7122 && ((GET_CODE (operands[2]) == CONST_INT
7123 && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 32)
7124 || (GET_CODE (operands[2]) == CONST_DOUBLE
7125 && CONST_DOUBLE_HIGH (operands[2]) == 0
7126 && (unsigned HOST_WIDE_INT) CONST_DOUBLE_LOW (operands[2]) < 32))"
7128 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
7130 return "srl\t%1, %2, %0";
7132 [(set_attr "type" "shift")])
7134 (define_expand "lshrdi3"
7135 [(set (match_operand:DI 0 "register_operand" "=r")
7136 (lshiftrt:DI (match_operand:DI 1 "register_operand" "r")
7137 (match_operand:SI 2 "arith_operand" "rI")))]
7138 "TARGET_ARCH64 || TARGET_V8PLUS"
7140 if (! TARGET_ARCH64)
7142 if (GET_CODE (operands[2]) == CONST_INT)
7144 emit_insn (gen_lshrdi3_v8plus (operands[0], operands[1], operands[2]));
7149 (define_insn "*lshrdi3_sp64"
7150 [(set (match_operand:DI 0 "register_operand" "=r")
7151 (lshiftrt:DI (match_operand:DI 1 "register_operand" "r")
7152 (match_operand:SI 2 "arith_operand" "rI")))]
7155 if (GET_CODE (operands[2]) == CONST_INT)
7156 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
7157 return "srlx\t%1, %2, %0";
7159 [(set_attr "type" "shift")])
7162 (define_insn "lshrdi3_v8plus"
7163 [(set (match_operand:DI 0 "register_operand" "=&h,&h,r")
7164 (lshiftrt:DI (match_operand:DI 1 "arith_operand" "rI,0,rI")
7165 (match_operand:SI 2 "arith_operand" "rI,rI,rI")))
7166 (clobber (match_scratch:SI 3 "=X,X,&h"))]
7168 { return sparc_v8plus_shift (operands, insn, "srlx"); }
7169 [(set_attr "type" "multi")
7170 (set_attr "length" "5,5,6")])
7173 [(set (match_operand:SI 0 "register_operand" "=r")
7174 (ashiftrt:SI (subreg:SI (lshiftrt:DI (match_operand:DI 1 "register_operand" "r")
7176 (match_operand:SI 2 "small_int_or_double" "n")))]
7178 && ((GET_CODE (operands[2]) == CONST_INT
7179 && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 32)
7180 || (GET_CODE (operands[2]) == CONST_DOUBLE
7181 && !CONST_DOUBLE_HIGH (operands[2])
7182 && (unsigned HOST_WIDE_INT) CONST_DOUBLE_LOW (operands[2]) < 32))"
7184 operands[2] = GEN_INT (INTVAL (operands[2]) + 32);
7186 return "srax\t%1, %2, %0";
7188 [(set_attr "type" "shift")])
7191 [(set (match_operand:SI 0 "register_operand" "=r")
7192 (lshiftrt:SI (subreg:SI (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
7194 (match_operand:SI 2 "small_int_or_double" "n")))]
7196 && ((GET_CODE (operands[2]) == CONST_INT
7197 && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 32)
7198 || (GET_CODE (operands[2]) == CONST_DOUBLE
7199 && !CONST_DOUBLE_HIGH (operands[2])
7200 && (unsigned HOST_WIDE_INT) CONST_DOUBLE_LOW (operands[2]) < 32))"
7202 operands[2] = GEN_INT (INTVAL (operands[2]) + 32);
7204 return "srlx\t%1, %2, %0";
7206 [(set_attr "type" "shift")])
7209 [(set (match_operand:SI 0 "register_operand" "=r")
7210 (ashiftrt:SI (subreg:SI (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
7211 (match_operand:SI 2 "small_int_or_double" "n")) 4)
7212 (match_operand:SI 3 "small_int_or_double" "n")))]
7214 && GET_CODE (operands[2]) == CONST_INT && GET_CODE (operands[3]) == CONST_INT
7215 && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) >= 32
7216 && (unsigned HOST_WIDE_INT) INTVAL (operands[3]) < 32
7217 && (unsigned HOST_WIDE_INT) (INTVAL (operands[2]) + INTVAL (operands[3])) < 64"
7219 operands[2] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[3]));
7221 return "srax\t%1, %2, %0";
7223 [(set_attr "type" "shift")])
7226 [(set (match_operand:SI 0 "register_operand" "=r")
7227 (lshiftrt:SI (subreg:SI (lshiftrt:DI (match_operand:DI 1 "register_operand" "r")
7228 (match_operand:SI 2 "small_int_or_double" "n")) 4)
7229 (match_operand:SI 3 "small_int_or_double" "n")))]
7231 && GET_CODE (operands[2]) == CONST_INT && GET_CODE (operands[3]) == CONST_INT
7232 && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) >= 32
7233 && (unsigned HOST_WIDE_INT) INTVAL (operands[3]) < 32
7234 && (unsigned HOST_WIDE_INT) (INTVAL (operands[2]) + INTVAL (operands[3])) < 64"
7236 operands[2] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[3]));
7238 return "srlx\t%1, %2, %0";
7240 [(set_attr "type" "shift")])
7242 ;; Unconditional and other jump instructions
7243 ;; On the SPARC, by setting the annul bit on an unconditional branch, the
7244 ;; following insn is never executed. This saves us a nop. Dbx does not
7245 ;; handle such branches though, so we only use them when optimizing.
7247 [(set (pc) (label_ref (match_operand 0 "" "")))]
7250 /* TurboSPARC is reported to have problems with
7253 i.e. an empty loop with the annul bit set. The workaround is to use
7257 if (! TARGET_V9 && flag_delayed_branch
7258 && (INSN_ADDRESSES (INSN_UID (operands[0]))
7259 == INSN_ADDRESSES (INSN_UID (insn))))
7262 return TARGET_V9 ? "ba%*,pt\t%%xcc, %l0%(" : "b%*\t%l0%(";
7264 [(set_attr "type" "uncond_branch")])
7266 (define_expand "tablejump"
7267 [(parallel [(set (pc) (match_operand 0 "register_operand" "r"))
7268 (use (label_ref (match_operand 1 "" "")))])]
7271 if (GET_MODE (operands[0]) != CASE_VECTOR_MODE)
7274 /* In pic mode, our address differences are against the base of the
7275 table. Add that base value back in; CSE ought to be able to combine
7276 the two address loads. */
7280 tmp = gen_rtx_LABEL_REF (Pmode, operands[1]);
7282 if (CASE_VECTOR_MODE != Pmode)
7283 tmp2 = gen_rtx_SIGN_EXTEND (Pmode, tmp2);
7284 tmp = gen_rtx_PLUS (Pmode, tmp2, tmp);
7285 operands[0] = memory_address (Pmode, tmp);
7289 (define_insn "*tablejump_sp32"
7290 [(set (pc) (match_operand:SI 0 "address_operand" "p"))
7291 (use (label_ref (match_operand 1 "" "")))]
7294 [(set_attr "type" "uncond_branch")])
7296 (define_insn "*tablejump_sp64"
7297 [(set (pc) (match_operand:DI 0 "address_operand" "p"))
7298 (use (label_ref (match_operand 1 "" "")))]
7301 [(set_attr "type" "uncond_branch")])
7303 ;; This pattern recognizes the "instruction" that appears in
7304 ;; a function call that wants a structure value,
7305 ;; to inform the called function if compiled with Sun CC.
7306 ;(define_insn "*unimp_insn"
7307 ; [(match_operand:SI 0 "immediate_operand" "")]
7308 ; "GET_CODE (operands[0]) == CONST_INT && INTVAL (operands[0]) > 0"
7310 ; [(set_attr "type" "marker")])
7312 ;;- jump to subroutine
7313 (define_expand "call"
7314 ;; Note that this expression is not used for generating RTL.
7315 ;; All the RTL is generated explicitly below.
7316 [(call (match_operand 0 "call_operand" "")
7317 (match_operand 3 "" "i"))]
7318 ;; operands[2] is next_arg_register
7319 ;; operands[3] is struct_value_size_rtx.
7322 rtx fn_rtx, nregs_rtx;
7324 if (GET_MODE (operands[0]) != FUNCTION_MODE)
7327 if (GET_CODE (XEXP (operands[0], 0)) == LABEL_REF)
7329 /* This is really a PIC sequence. We want to represent
7330 it as a funny jump so its delay slots can be filled.
7332 ??? But if this really *is* a CALL, will not it clobber the
7333 call-clobbered registers? We lose this if it is a JUMP_INSN.
7334 Why cannot we have delay slots filled if it were a CALL? */
7336 if (! TARGET_ARCH64 && INTVAL (operands[3]) != 0)
7341 gen_rtx_SET (VOIDmode, pc_rtx, XEXP (operands[0], 0)),
7343 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 15)))));
7349 gen_rtx_SET (VOIDmode, pc_rtx, XEXP (operands[0], 0)),
7350 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 15)))));
7354 fn_rtx = operands[0];
7356 /* Count the number of parameter registers being used by this call.
7357 if that argument is NULL, it means we are using them all, which
7358 means 6 on the sparc. */
7361 nregs_rtx = GEN_INT (REGNO (operands[2]) - 8);
7363 nregs_rtx = GEN_INT (6);
7365 nregs_rtx = const0_rtx;
7368 if (! TARGET_ARCH64 && INTVAL (operands[3]) != 0)
7372 gen_rtvec (3, gen_rtx_CALL (VOIDmode, fn_rtx, nregs_rtx),
7374 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 15)))));
7379 gen_rtvec (2, gen_rtx_CALL (VOIDmode, fn_rtx, nregs_rtx),
7380 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 15)))));
7384 /* If this call wants a structure value,
7385 emit an unimp insn to let the called function know about this. */
7386 if (! TARGET_ARCH64 && INTVAL (operands[3]) > 0)
7388 rtx insn = emit_insn (operands[3]);
7389 SCHED_GROUP_P (insn) = 1;
7396 ;; We can't use the same pattern for these two insns, because then registers
7397 ;; in the address may not be properly reloaded.
7399 (define_insn "*call_address_sp32"
7400 [(call (mem:SI (match_operand:SI 0 "address_operand" "p"))
7401 (match_operand 1 "" ""))
7402 (clobber (reg:SI 15))]
7403 ;;- Do not use operand 1 for most machines.
7406 [(set_attr "type" "call")])
7408 (define_insn "*call_symbolic_sp32"
7409 [(call (mem:SI (match_operand:SI 0 "symbolic_operand" "s"))
7410 (match_operand 1 "" ""))
7411 (clobber (reg:SI 15))]
7412 ;;- Do not use operand 1 for most machines.
7415 [(set_attr "type" "call")])
7417 (define_insn "*call_address_sp64"
7418 [(call (mem:DI (match_operand:DI 0 "address_operand" "p"))
7419 (match_operand 1 "" ""))
7420 (clobber (reg:DI 15))]
7421 ;;- Do not use operand 1 for most machines.
7424 [(set_attr "type" "call")])
7426 (define_insn "*call_symbolic_sp64"
7427 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "s"))
7428 (match_operand 1 "" ""))
7429 (clobber (reg:DI 15))]
7430 ;;- Do not use operand 1 for most machines.
7433 [(set_attr "type" "call")])
7435 ;; This is a call that wants a structure value.
7436 ;; There is no such critter for v9 (??? we may need one anyway).
7437 (define_insn "*call_address_struct_value_sp32"
7438 [(call (mem:SI (match_operand:SI 0 "address_operand" "p"))
7439 (match_operand 1 "" ""))
7440 (match_operand 2 "immediate_operand" "")
7441 (clobber (reg:SI 15))]
7442 ;;- Do not use operand 1 for most machines.
7443 "! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 0"
7444 "call\t%a0, %1\n\tnop\n\tunimp\t%2"
7445 [(set_attr "type" "call_no_delay_slot")
7446 (set_attr "length" "3")])
7448 ;; This is a call that wants a structure value.
7449 ;; There is no such critter for v9 (??? we may need one anyway).
7450 (define_insn "*call_symbolic_struct_value_sp32"
7451 [(call (mem:SI (match_operand:SI 0 "symbolic_operand" "s"))
7452 (match_operand 1 "" ""))
7453 (match_operand 2 "immediate_operand" "")
7454 (clobber (reg:SI 15))]
7455 ;;- Do not use operand 1 for most machines.
7456 "! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 0"
7457 "call\t%a0, %1\n\tnop\n\tunimp\t%2"
7458 [(set_attr "type" "call_no_delay_slot")
7459 (set_attr "length" "3")])
7461 ;; This is a call that may want a structure value. This is used for
7463 (define_insn "*call_address_untyped_struct_value_sp32"
7464 [(call (mem:SI (match_operand:SI 0 "address_operand" "p"))
7465 (match_operand 1 "" ""))
7466 (match_operand 2 "immediate_operand" "")
7467 (clobber (reg:SI 15))]
7468 ;;- Do not use operand 1 for most machines.
7469 "! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0"
7470 "call\t%a0, %1\n\tnop\n\tnop"
7471 [(set_attr "type" "call_no_delay_slot")
7472 (set_attr "length" "3")])
7474 ;; This is a call that wants a structure value.
7475 (define_insn "*call_symbolic_untyped_struct_value_sp32"
7476 [(call (mem:SI (match_operand:SI 0 "symbolic_operand" "s"))
7477 (match_operand 1 "" ""))
7478 (match_operand 2 "immediate_operand" "")
7479 (clobber (reg:SI 15))]
7480 ;;- Do not use operand 1 for most machines.
7481 "! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0"
7482 "call\t%a0, %1\n\tnop\n\tnop"
7483 [(set_attr "type" "call_no_delay_slot")
7484 (set_attr "length" "3")])
7486 (define_expand "call_value"
7487 ;; Note that this expression is not used for generating RTL.
7488 ;; All the RTL is generated explicitly below.
7489 [(set (match_operand 0 "register_operand" "=rf")
7490 (call (match_operand 1 "" "")
7491 (match_operand 4 "" "")))]
7492 ;; operand 2 is stack_size_rtx
7493 ;; operand 3 is next_arg_register
7496 rtx fn_rtx, nregs_rtx;
7499 if (GET_MODE (operands[1]) != FUNCTION_MODE)
7502 fn_rtx = operands[1];
7506 nregs_rtx = GEN_INT (REGNO (operands[3]) - 8);
7508 nregs_rtx = GEN_INT (6);
7510 nregs_rtx = const0_rtx;
7514 gen_rtx_SET (VOIDmode, operands[0],
7515 gen_rtx_CALL (VOIDmode, fn_rtx, nregs_rtx)),
7516 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 15)));
7518 emit_call_insn (gen_rtx_PARALLEL (VOIDmode, vec));
7523 (define_insn "*call_value_address_sp32"
7524 [(set (match_operand 0 "" "=rf")
7525 (call (mem:SI (match_operand:SI 1 "address_operand" "p"))
7526 (match_operand 2 "" "")))
7527 (clobber (reg:SI 15))]
7528 ;;- Do not use operand 2 for most machines.
7531 [(set_attr "type" "call")])
7533 (define_insn "*call_value_symbolic_sp32"
7534 [(set (match_operand 0 "" "=rf")
7535 (call (mem:SI (match_operand:SI 1 "symbolic_operand" "s"))
7536 (match_operand 2 "" "")))
7537 (clobber (reg:SI 15))]
7538 ;;- Do not use operand 2 for most machines.
7541 [(set_attr "type" "call")])
7543 (define_insn "*call_value_address_sp64"
7544 [(set (match_operand 0 "" "")
7545 (call (mem:DI (match_operand:DI 1 "address_operand" "p"))
7546 (match_operand 2 "" "")))
7547 (clobber (reg:DI 15))]
7548 ;;- Do not use operand 2 for most machines.
7551 [(set_attr "type" "call")])
7553 (define_insn "*call_value_symbolic_sp64"
7554 [(set (match_operand 0 "" "")
7555 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "s"))
7556 (match_operand 2 "" "")))
7557 (clobber (reg:DI 15))]
7558 ;;- Do not use operand 2 for most machines.
7561 [(set_attr "type" "call")])
7563 (define_expand "untyped_call"
7564 [(parallel [(call (match_operand 0 "" "")
7566 (match_operand 1 "" "")
7567 (match_operand 2 "" "")])]
7572 /* Pass constm1 to indicate that it may expect a structure value, but
7573 we don't know what size it is. */
7574 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, constm1_rtx));
7576 for (i = 0; i < XVECLEN (operands[2], 0); i++)
7578 rtx set = XVECEXP (operands[2], 0, i);
7579 emit_move_insn (SET_DEST (set), SET_SRC (set));
7582 /* The optimizer does not know that the call sets the function value
7583 registers we stored in the result block. We avoid problems by
7584 claiming that all hard registers are used and clobbered at this
7586 emit_insn (gen_blockage ());
7592 (define_expand "sibcall"
7593 [(parallel [(call (match_operand 0 "call_operand" "") (const_int 0))
7598 (define_insn "*sibcall_symbolic_sp32"
7599 [(call (mem:SI (match_operand:SI 0 "symbolic_operand" "s"))
7600 (match_operand 1 "" ""))
7603 "* return output_sibcall(insn, operands[0]);"
7604 [(set_attr "type" "sibcall")])
7606 (define_insn "*sibcall_symbolic_sp64"
7607 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "s"))
7608 (match_operand 1 "" ""))
7611 "* return output_sibcall(insn, operands[0]);"
7612 [(set_attr "type" "sibcall")])
7614 (define_expand "sibcall_value"
7615 [(parallel [(set (match_operand 0 "register_operand" "=rf")
7616 (call (match_operand 1 "" "") (const_int 0)))
7621 (define_insn "*sibcall_value_symbolic_sp32"
7622 [(set (match_operand 0 "" "=rf")
7623 (call (mem:SI (match_operand:SI 1 "symbolic_operand" "s"))
7624 (match_operand 2 "" "")))
7627 "* return output_sibcall(insn, operands[1]);"
7628 [(set_attr "type" "sibcall")])
7630 (define_insn "*sibcall_value_symbolic_sp64"
7631 [(set (match_operand 0 "" "")
7632 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "s"))
7633 (match_operand 2 "" "")))
7636 "* return output_sibcall(insn, operands[1]);"
7637 [(set_attr "type" "sibcall")])
7639 (define_expand "sibcall_epilogue"
7644 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
7645 ;; all of memory. This blocks insns from being moved across this point.
7647 (define_insn "blockage"
7648 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
7651 [(set_attr "length" "0")])
7653 ;; Prepare to return any type including a structure value.
7655 (define_expand "untyped_return"
7656 [(match_operand:BLK 0 "memory_operand" "")
7657 (match_operand 1 "" "")]
7660 rtx valreg1 = gen_rtx_REG (DImode, 24);
7661 rtx valreg2 = gen_rtx_REG (TARGET_ARCH64 ? TFmode : DFmode, 32);
7662 rtx result = operands[0];
7664 if (! TARGET_ARCH64)
7666 rtx rtnreg = gen_rtx_REG (SImode, (current_function_uses_only_leaf_regs
7668 rtx value = gen_reg_rtx (SImode);
7670 /* Fetch the instruction where we will return to and see if it's an unimp
7671 instruction (the most significant 10 bits will be zero). If so,
7672 update the return address to skip the unimp instruction. */
7673 emit_move_insn (value,
7674 gen_rtx_MEM (SImode, plus_constant (rtnreg, 8)));
7675 emit_insn (gen_lshrsi3 (value, value, GEN_INT (22)));
7676 emit_insn (gen_update_return (rtnreg, value));
7679 /* Reload the function value registers. */
7680 emit_move_insn (valreg1, adjust_address (result, DImode, 0));
7681 emit_move_insn (valreg2,
7682 adjust_address (result, TARGET_ARCH64 ? TFmode : DFmode, 8));
7684 /* Put USE insns before the return. */
7685 emit_insn (gen_rtx_USE (VOIDmode, valreg1));
7686 emit_insn (gen_rtx_USE (VOIDmode, valreg2));
7688 /* Construct the return. */
7689 expand_naked_return ();
7694 ;; This is a bit of a hack. We're incrementing a fixed register (%i7),
7695 ;; and parts of the compiler don't want to believe that the add is needed.
7697 (define_insn "update_return"
7698 [(unspec:SI [(match_operand:SI 0 "register_operand" "r")
7699 (match_operand:SI 1 "register_operand" "r")] UNSPEC_UPDATE_RETURN)]
7701 "cmp\t%1, 0\;be,a\t.+8\;add\t%0, 4, %0"
7702 [(set_attr "type" "multi")
7703 (set_attr "length" "3")])
7710 (define_expand "indirect_jump"
7711 [(set (pc) (match_operand 0 "address_operand" "p"))]
7715 (define_insn "*branch_sp32"
7716 [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
7719 [(set_attr "type" "uncond_branch")])
7721 (define_insn "*branch_sp64"
7722 [(set (pc) (match_operand:DI 0 "address_operand" "p"))]
7725 [(set_attr "type" "uncond_branch")])
7727 ;; ??? Doesn't work with -mflat.
7728 (define_expand "nonlocal_goto"
7729 [(match_operand:SI 0 "general_operand" "")
7730 (match_operand:SI 1 "general_operand" "")
7731 (match_operand:SI 2 "general_operand" "")
7732 (match_operand:SI 3 "" "")]
7736 rtx chain = operands[0];
7738 rtx lab = operands[1];
7739 rtx stack = operands[2];
7740 rtx fp = operands[3];
7743 /* Trap instruction to flush all the register windows. */
7744 emit_insn (gen_flush_register_windows ());
7746 /* Load the fp value for the containing fn into %fp. This is needed
7747 because STACK refers to %fp. Note that virtual register instantiation
7748 fails if the virtual %fp isn't set from a register. */
7749 if (GET_CODE (fp) != REG)
7750 fp = force_reg (Pmode, fp);
7751 emit_move_insn (virtual_stack_vars_rtx, fp);
7753 /* Find the containing function's current nonlocal goto handler,
7754 which will do any cleanups and then jump to the label. */
7755 labreg = gen_rtx_REG (Pmode, 8);
7756 emit_move_insn (labreg, lab);
7758 /* Restore %fp from stack pointer value for containing function.
7759 The restore insn that follows will move this to %sp,
7760 and reload the appropriate value into %fp. */
7761 emit_move_insn (hard_frame_pointer_rtx, stack);
7763 /* USE of frame_pointer_rtx added for consistency; not clear if
7765 /*emit_insn (gen_rtx_USE (VOIDmode, frame_pointer_rtx));*/
7766 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
7769 /* Return, restoring reg window and jumping to goto handler. */
7770 if (TARGET_V9 && GET_CODE (chain) == CONST_INT
7771 && ! (INTVAL (chain) & ~(HOST_WIDE_INT)0xffffffff))
7773 emit_jump_insn (gen_goto_handler_and_restore_v9 (labreg,
7779 /* Put in the static chain register the nonlocal label address. */
7780 emit_move_insn (static_chain_rtx, chain);
7783 emit_insn (gen_rtx_USE (VOIDmode, static_chain_rtx));
7784 emit_jump_insn (gen_goto_handler_and_restore (labreg));
7789 ;; Special trap insn to flush register windows.
7790 (define_insn "flush_register_windows"
7791 [(unspec_volatile [(const_int 0)] UNSPECV_FLUSHW)]
7793 { return TARGET_V9 ? "flushw" : "ta\t3"; }
7794 [(set_attr "type" "flushw")])
7796 (define_insn "goto_handler_and_restore"
7797 [(unspec_volatile [(match_operand 0 "register_operand" "=r")] UNSPECV_GOTO)]
7798 "GET_MODE (operands[0]) == Pmode"
7799 "jmp\t%0+0\n\trestore"
7800 [(set_attr "type" "multi")
7801 (set_attr "length" "2")])
7803 ;;(define_insn "goto_handler_and_restore_v9"
7804 ;; [(unspec_volatile [(match_operand:SI 0 "register_operand" "=r,r")
7805 ;; (match_operand:SI 1 "register_operand" "=r,r")
7806 ;; (match_operand:SI 2 "const_int_operand" "I,n")] UNSPECV_GOTO_V9)]
7807 ;; "TARGET_V9 && ! TARGET_ARCH64"
7809 ;; return\t%0+0\n\tmov\t%2, %Y1
7810 ;; sethi\t%%hi(%2), %1\n\treturn\t%0+0\n\tor\t%Y1, %%lo(%2), %Y1"
7811 ;; [(set_attr "type" "multi")
7812 ;; (set_attr "length" "2,3")])
7814 ;;(define_insn "*goto_handler_and_restore_v9_sp64"
7815 ;; [(unspec_volatile [(match_operand:DI 0 "register_operand" "=r,r")
7816 ;; (match_operand:DI 1 "register_operand" "=r,r")
7817 ;; (match_operand:SI 2 "const_int_operand" "I,n")] UNSPECV_GOTO_V9)]
7818 ;; "TARGET_V9 && TARGET_ARCH64"
7820 ;; return\t%0+0\n\tmov\t%2, %Y1
7821 ;; sethi\t%%hi(%2), %1\n\treturn\t%0+0\n\tor\t%Y1, %%lo(%2), %Y1"
7822 ;; [(set_attr "type" "multi")
7823 ;; (set_attr "length" "2,3")])
7825 ;; For __builtin_setjmp we need to flush register windows iff the function
7826 ;; calls alloca as well, because otherwise the register window might be
7827 ;; saved after %sp adjustment and thus setjmp would crash
7828 (define_expand "builtin_setjmp_setup"
7829 [(match_operand 0 "register_operand" "r")]
7832 emit_insn (gen_do_builtin_setjmp_setup ());
7836 (define_insn "do_builtin_setjmp_setup"
7837 [(unspec_volatile [(const_int 0)] UNSPECV_SETJMP)]
7840 if (! current_function_calls_alloca)
7842 if (! TARGET_V9 || TARGET_FLAT)
7844 fputs ("\tflushw\n", asm_out_file);
7846 fprintf (asm_out_file, "\tst%c\t%%l7, [%%sp+%d]\n",
7847 TARGET_ARCH64 ? 'x' : 'w',
7848 SPARC_STACK_BIAS + 7 * UNITS_PER_WORD);
7849 fprintf (asm_out_file, "\tst%c\t%%fp, [%%sp+%d]\n",
7850 TARGET_ARCH64 ? 'x' : 'w',
7851 SPARC_STACK_BIAS + 14 * UNITS_PER_WORD);
7852 fprintf (asm_out_file, "\tst%c\t%%i7, [%%sp+%d]\n",
7853 TARGET_ARCH64 ? 'x' : 'w',
7854 SPARC_STACK_BIAS + 15 * UNITS_PER_WORD);
7857 [(set_attr "type" "multi")
7858 (set (attr "length")
7859 (cond [(eq_attr "current_function_calls_alloca" "false")
7861 (eq_attr "flat" "true")
7863 (eq_attr "isa" "!v9")
7865 (eq_attr "pic" "true")
7866 (const_int 4)] (const_int 3)))])
7868 ;; Pattern for use after a setjmp to store FP and the return register
7869 ;; into the stack area.
7871 (define_expand "setjmp"
7876 emit_insn (gen_setjmp_64 ());
7878 emit_insn (gen_setjmp_32 ());
7882 (define_expand "setjmp_32"
7883 [(set (mem:SI (plus:SI (reg:SI 14) (const_int 56))) (match_dup 0))
7884 (set (mem:SI (plus:SI (reg:SI 14) (const_int 60))) (reg:SI 31))]
7886 { operands[0] = frame_pointer_rtx; })
7888 (define_expand "setjmp_64"
7889 [(set (mem:DI (plus:DI (reg:DI 14) (const_int 112))) (match_dup 0))
7890 (set (mem:DI (plus:DI (reg:DI 14) (const_int 120))) (reg:DI 31))]
7892 { operands[0] = frame_pointer_rtx; })
7894 ;; Special pattern for the FLUSH instruction.
7896 ; We do SImode and DImode versions of this to quiet down genrecog's complaints
7897 ; of the define_insn otherwise missing a mode. We make "flush", aka
7898 ; gen_flush, the default one since sparc_initialize_trampoline uses
7899 ; it on SImode mem values.
7901 (define_insn "flush"
7902 [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")] UNSPECV_FLUSH)]
7904 { return TARGET_V9 ? "flush\t%f0" : "iflush\t%f0"; }
7905 [(set_attr "type" "iflush")])
7907 (define_insn "flushdi"
7908 [(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")] UNSPECV_FLUSH)]
7910 { return TARGET_V9 ? "flush\t%f0" : "iflush\t%f0"; }
7911 [(set_attr "type" "iflush")])
7916 ;; The scan instruction searches from the most significant bit while ffs
7917 ;; searches from the least significant bit. The bit index and treatment of
7918 ;; zero also differ. It takes at least 7 instructions to get the proper
7919 ;; result. Here is an obvious 8 instruction sequence.
7922 (define_insn "ffssi2"
7923 [(set (match_operand:SI 0 "register_operand" "=&r")
7924 (ffs:SI (match_operand:SI 1 "register_operand" "r")))
7925 (clobber (match_scratch:SI 2 "=&r"))]
7926 "TARGET_SPARCLITE || TARGET_SPARCLET"
7928 return "sub\t%%g0, %1, %0\;and\t%0, %1, %0\;scan\t%0, 0, %0\;mov\t32, %2\;sub\t%2, %0, %0\;sra\t%0, 31, %2\;and\t%2, 31, %2\;add\t%2, %0, %0";
7930 [(set_attr "type" "multi")
7931 (set_attr "length" "8")])
7933 ;; ??? This should be a define expand, so that the extra instruction have
7934 ;; a chance of being optimized away.
7936 ;; Disabled because none of the UltraSPARCs implement popc. The HAL R1
7937 ;; does, but no one uses that and we don't have a switch for it.
7939 ;(define_insn "ffsdi2"
7940 ; [(set (match_operand:DI 0 "register_operand" "=&r")
7941 ; (ffs:DI (match_operand:DI 1 "register_operand" "r")))
7942 ; (clobber (match_scratch:DI 2 "=&r"))]
7944 ; "neg\t%1, %2\;xnor\t%1, %2, %2\;popc\t%2, %0\;movzr\t%1, 0, %0"
7945 ; [(set_attr "type" "multi")
7946 ; (set_attr "length" "4")])
7950 ;; Peepholes go at the end.
7952 ;; Optimize consecutive loads or stores into ldd and std when possible.
7953 ;; The conditions in which we do this are very restricted and are
7954 ;; explained in the code for {registers,memory}_ok_for_ldd functions.
7957 [(set (match_operand:SI 0 "memory_operand" "")
7959 (set (match_operand:SI 1 "memory_operand" "")
7962 && mems_ok_for_ldd_peep (operands[0], operands[1], NULL_RTX)"
7965 "operands[0] = widen_memory_access (operands[0], DImode, 0);")
7968 [(set (match_operand:SI 0 "memory_operand" "")
7970 (set (match_operand:SI 1 "memory_operand" "")
7973 && mems_ok_for_ldd_peep (operands[1], operands[0], NULL_RTX)"
7976 "operands[1] = widen_memory_access (operands[1], DImode, 0);")
7979 [(set (match_operand:SI 0 "register_operand" "")
7980 (match_operand:SI 1 "memory_operand" ""))
7981 (set (match_operand:SI 2 "register_operand" "")
7982 (match_operand:SI 3 "memory_operand" ""))]
7983 "registers_ok_for_ldd_peep (operands[0], operands[2])
7984 && mems_ok_for_ldd_peep (operands[1], operands[3], operands[0])"
7987 "operands[1] = widen_memory_access (operands[1], DImode, 0);
7988 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));")
7991 [(set (match_operand:SI 0 "memory_operand" "")
7992 (match_operand:SI 1 "register_operand" ""))
7993 (set (match_operand:SI 2 "memory_operand" "")
7994 (match_operand:SI 3 "register_operand" ""))]
7995 "registers_ok_for_ldd_peep (operands[1], operands[3])
7996 && mems_ok_for_ldd_peep (operands[0], operands[2], NULL_RTX)"
7999 "operands[0] = widen_memory_access (operands[0], DImode, 0);
8000 operands[1] = gen_rtx_REG (DImode, REGNO (operands[1]));")
8003 [(set (match_operand:SF 0 "register_operand" "")
8004 (match_operand:SF 1 "memory_operand" ""))
8005 (set (match_operand:SF 2 "register_operand" "")
8006 (match_operand:SF 3 "memory_operand" ""))]
8007 "registers_ok_for_ldd_peep (operands[0], operands[2])
8008 && mems_ok_for_ldd_peep (operands[1], operands[3], operands[0])"
8011 "operands[1] = widen_memory_access (operands[1], DFmode, 0);
8012 operands[0] = gen_rtx_REG (DFmode, REGNO (operands[0]));")
8015 [(set (match_operand:SF 0 "memory_operand" "")
8016 (match_operand:SF 1 "register_operand" ""))
8017 (set (match_operand:SF 2 "memory_operand" "")
8018 (match_operand:SF 3 "register_operand" ""))]
8019 "registers_ok_for_ldd_peep (operands[1], operands[3])
8020 && mems_ok_for_ldd_peep (operands[0], operands[2], NULL_RTX)"
8023 "operands[0] = widen_memory_access (operands[0], DFmode, 0);
8024 operands[1] = gen_rtx_REG (DFmode, REGNO (operands[1]));")
8027 [(set (match_operand:SI 0 "register_operand" "")
8028 (match_operand:SI 1 "memory_operand" ""))
8029 (set (match_operand:SI 2 "register_operand" "")
8030 (match_operand:SI 3 "memory_operand" ""))]
8031 "registers_ok_for_ldd_peep (operands[2], operands[0])
8032 && mems_ok_for_ldd_peep (operands[3], operands[1], operands[0])"
8035 "operands[3] = widen_memory_access (operands[3], DImode, 0);
8036 operands[2] = gen_rtx_REG (DImode, REGNO (operands[2]));")
8039 [(set (match_operand:SI 0 "memory_operand" "")
8040 (match_operand:SI 1 "register_operand" ""))
8041 (set (match_operand:SI 2 "memory_operand" "")
8042 (match_operand:SI 3 "register_operand" ""))]
8043 "registers_ok_for_ldd_peep (operands[3], operands[1])
8044 && mems_ok_for_ldd_peep (operands[2], operands[0], NULL_RTX)"
8047 "operands[2] = widen_memory_access (operands[2], DImode, 0);
8048 operands[3] = gen_rtx_REG (DImode, REGNO (operands[3]));
8052 [(set (match_operand:SF 0 "register_operand" "")
8053 (match_operand:SF 1 "memory_operand" ""))
8054 (set (match_operand:SF 2 "register_operand" "")
8055 (match_operand:SF 3 "memory_operand" ""))]
8056 "registers_ok_for_ldd_peep (operands[2], operands[0])
8057 && mems_ok_for_ldd_peep (operands[3], operands[1], operands[0])"
8060 "operands[3] = widen_memory_access (operands[3], DFmode, 0);
8061 operands[2] = gen_rtx_REG (DFmode, REGNO (operands[2]));")
8064 [(set (match_operand:SF 0 "memory_operand" "")
8065 (match_operand:SF 1 "register_operand" ""))
8066 (set (match_operand:SF 2 "memory_operand" "")
8067 (match_operand:SF 3 "register_operand" ""))]
8068 "registers_ok_for_ldd_peep (operands[3], operands[1])
8069 && mems_ok_for_ldd_peep (operands[2], operands[0], NULL_RTX)"
8072 "operands[2] = widen_memory_access (operands[2], DFmode, 0);
8073 operands[3] = gen_rtx_REG (DFmode, REGNO (operands[3]));")
8075 ;; Optimize the case of following a reg-reg move with a test
8076 ;; of reg just moved. Don't allow floating point regs for operand 0 or 1.
8077 ;; This can result from a float to fix conversion.
8080 [(set (match_operand:SI 0 "register_operand" "")
8081 (match_operand:SI 1 "register_operand" ""))
8083 (compare:CC (match_operand:SI 2 "register_operand" "")
8085 "(rtx_equal_p (operands[2], operands[0])
8086 || rtx_equal_p (operands[2], operands[1]))
8087 && ! SPARC_FP_REG_P (REGNO (operands[0]))
8088 && ! SPARC_FP_REG_P (REGNO (operands[1]))"
8089 [(parallel [(set (match_dup 0) (match_dup 1))
8091 (compare:CC (match_dup 1) (const_int 0)))])]
8095 [(set (match_operand:DI 0 "register_operand" "")
8096 (match_operand:DI 1 "register_operand" ""))
8098 (compare:CCX (match_operand:DI 2 "register_operand" "")
8101 && (rtx_equal_p (operands[2], operands[0])
8102 || rtx_equal_p (operands[2], operands[1]))
8103 && ! SPARC_FP_REG_P (REGNO (operands[0]))
8104 && ! SPARC_FP_REG_P (REGNO (operands[1]))"
8105 [(parallel [(set (match_dup 0) (match_dup 1))
8107 (compare:CCX (match_dup 1) (const_int 0)))])]
8110 ;; Return peepholes. These are generated by sparc_nonflat_function_epilogue
8111 ;; who then immediately calls final_scan_insn.
8113 (define_insn "*return_qi"
8114 [(set (match_operand:QI 0 "restore_operand" "")
8115 (match_operand:QI 1 "arith_operand" "rI"))
8117 "sparc_emitting_epilogue"
8119 if (! TARGET_ARCH64 && current_function_returns_struct)
8120 return "jmp\t%%i7+12\n\trestore %%g0, %1, %Y0";
8121 else if (TARGET_V9 && (GET_CODE (operands[1]) == CONST_INT
8122 || IN_OR_GLOBAL_P (operands[1])))
8123 return "return\t%%i7+8\n\tmov\t%Y1, %Y0";
8125 return "ret\n\trestore %%g0, %1, %Y0";
8127 [(set_attr "type" "multi")
8128 (set_attr "length" "2")])
8130 (define_insn "*return_hi"
8131 [(set (match_operand:HI 0 "restore_operand" "")
8132 (match_operand:HI 1 "arith_operand" "rI"))
8134 "sparc_emitting_epilogue"
8136 if (! TARGET_ARCH64 && current_function_returns_struct)
8137 return "jmp\t%%i7+12\n\trestore %%g0, %1, %Y0";
8138 else if (TARGET_V9 && (GET_CODE (operands[1]) == CONST_INT
8139 || IN_OR_GLOBAL_P (operands[1])))
8140 return "return\t%%i7+8\n\tmov\t%Y1, %Y0";
8142 return "ret\;restore %%g0, %1, %Y0";
8144 [(set_attr "type" "multi")
8145 (set_attr "length" "2")])
8147 (define_insn "*return_si"
8148 [(set (match_operand:SI 0 "restore_operand" "")
8149 (match_operand:SI 1 "arith_operand" "rI"))
8151 "sparc_emitting_epilogue"
8153 if (! TARGET_ARCH64 && current_function_returns_struct)
8154 return "jmp\t%%i7+12\n\trestore %%g0, %1, %Y0";
8155 else if (TARGET_V9 && (GET_CODE (operands[1]) == CONST_INT
8156 || IN_OR_GLOBAL_P (operands[1])))
8157 return "return\t%%i7+8\n\tmov\t%Y1, %Y0";
8159 return "ret\;restore %%g0, %1, %Y0";
8161 [(set_attr "type" "multi")
8162 (set_attr "length" "2")])
8164 (define_insn "*return_sf_no_fpu"
8165 [(set (match_operand:SF 0 "restore_operand" "=r")
8166 (match_operand:SF 1 "register_operand" "r"))
8168 "sparc_emitting_epilogue"
8170 if (! TARGET_ARCH64 && current_function_returns_struct)
8171 return "jmp\t%%i7+12\n\trestore %%g0, %1, %Y0";
8172 else if (TARGET_V9 && IN_OR_GLOBAL_P (operands[1]))
8173 return "return\t%%i7+8\n\tmov\t%Y1, %Y0";
8175 return "ret\;restore %%g0, %1, %Y0";
8177 [(set_attr "type" "multi")
8178 (set_attr "length" "2")])
8180 (define_insn "*return_df_no_fpu"
8181 [(set (match_operand:DF 0 "restore_operand" "=r")
8182 (match_operand:DF 1 "register_operand" "r"))
8184 "sparc_emitting_epilogue && TARGET_ARCH64"
8186 if (IN_OR_GLOBAL_P (operands[1]))
8187 return "return\t%%i7+8\n\tmov\t%Y1, %Y0";
8189 return "ret\;restore %%g0, %1, %Y0";
8191 [(set_attr "type" "multi")
8192 (set_attr "length" "2")])
8194 (define_insn "*return_addsi"
8195 [(set (match_operand:SI 0 "restore_operand" "")
8196 (plus:SI (match_operand:SI 1 "register_operand" "r")
8197 (match_operand:SI 2 "arith_operand" "rI")))
8199 "sparc_emitting_epilogue"
8201 if (! TARGET_ARCH64 && current_function_returns_struct)
8202 return "jmp\t%%i7+12\n\trestore %r1, %2, %Y0";
8203 /* If operands are global or in registers, can use return */
8204 else if (TARGET_V9 && IN_OR_GLOBAL_P (operands[1])
8205 && (GET_CODE (operands[2]) == CONST_INT
8206 || IN_OR_GLOBAL_P (operands[2])))
8207 return "return\t%%i7+8\n\tadd\t%Y1, %Y2, %Y0";
8209 return "ret\;restore %r1, %2, %Y0";
8211 [(set_attr "type" "multi")
8212 (set_attr "length" "2")])
8214 (define_insn "*return_losum_si"
8215 [(set (match_operand:SI 0 "restore_operand" "")
8216 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
8217 (match_operand:SI 2 "immediate_operand" "in")))
8219 "sparc_emitting_epilogue && ! TARGET_CM_MEDMID"
8221 if (! TARGET_ARCH64 && current_function_returns_struct)
8222 return "jmp\t%%i7+12\n\trestore %r1, %%lo(%a2), %Y0";
8223 /* If operands are global or in registers, can use return */
8224 else if (TARGET_V9 && IN_OR_GLOBAL_P (operands[1]))
8225 return "return\t%%i7+8\n\tor\t%Y1, %%lo(%a2), %Y0";
8227 return "ret\;restore %r1, %%lo(%a2), %Y0";
8229 [(set_attr "type" "multi")
8230 (set_attr "length" "2")])
8232 (define_insn "*return_di"
8233 [(set (match_operand:DI 0 "restore_operand" "")
8234 (match_operand:DI 1 "arith_double_operand" "rHI"))
8236 "sparc_emitting_epilogue && TARGET_ARCH64"
8237 "ret\;restore %%g0, %1, %Y0"
8238 [(set_attr "type" "multi")
8239 (set_attr "length" "2")])
8241 (define_insn "*return_adddi"
8242 [(set (match_operand:DI 0 "restore_operand" "")
8243 (plus:DI (match_operand:DI 1 "arith_operand" "%r")
8244 (match_operand:DI 2 "arith_double_operand" "rHI")))
8246 "sparc_emitting_epilogue && TARGET_ARCH64"
8247 "ret\;restore %r1, %2, %Y0"
8248 [(set_attr "type" "multi")
8249 (set_attr "length" "2")])
8251 (define_insn "*return_losum_di"
8252 [(set (match_operand:DI 0 "restore_operand" "")
8253 (lo_sum:DI (match_operand:DI 1 "arith_operand" "%r")
8254 (match_operand:DI 2 "immediate_operand" "in")))
8256 "sparc_emitting_epilogue && TARGET_ARCH64 && ! TARGET_CM_MEDMID"
8257 "ret\;restore %r1, %%lo(%a2), %Y0"
8258 [(set_attr "type" "multi")
8259 (set_attr "length" "2")])
8261 (define_insn "*return_sf"
8263 (match_operand:SF 0 "register_operand" "f"))
8265 "sparc_emitting_epilogue"
8266 "ret\;fmovs\t%0, %%f0"
8267 [(set_attr "type" "multi")
8268 (set_attr "length" "2")])
8270 ;; Now peepholes to do a call followed by a jump.
8273 [(parallel [(set (match_operand 0 "" "")
8274 (call (mem:SI (match_operand:SI 1 "call_operand_address" "ps"))
8275 (match_operand 2 "" "")))
8276 (clobber (reg:SI 15))])
8277 (set (pc) (label_ref (match_operand 3 "" "")))]
8278 "short_branch (INSN_UID (insn), INSN_UID (operands[3]))
8279 && (USING_SJLJ_EXCEPTIONS || ! can_throw_internal (ins1))
8280 && sparc_cpu != PROCESSOR_ULTRASPARC
8281 && sparc_cpu != PROCESSOR_ULTRASPARC3"
8282 "call\t%a1, %2\n\tadd\t%%o7, (%l3-.-4), %%o7")
8285 [(parallel [(call (mem:SI (match_operand:SI 0 "call_operand_address" "ps"))
8286 (match_operand 1 "" ""))
8287 (clobber (reg:SI 15))])
8288 (set (pc) (label_ref (match_operand 2 "" "")))]
8289 "short_branch (INSN_UID (insn), INSN_UID (operands[2]))
8290 && (USING_SJLJ_EXCEPTIONS || ! can_throw_internal (ins1))
8291 && sparc_cpu != PROCESSOR_ULTRASPARC
8292 && sparc_cpu != PROCESSOR_ULTRASPARC3"
8293 "call\t%a0, %1\n\tadd\t%%o7, (%l2-.-4), %%o7")
8295 ;; ??? UltraSPARC-III note: A memory operation loading into the floating point register
8296 ;; ??? file, if it hits the prefetch cache, has a chance to dual-issue with other memory
8297 ;; ??? operations. With DFA we might be able to model this, but it requires a lot of
8299 (define_expand "prefetch"
8300 [(match_operand 0 "address_operand" "")
8301 (match_operand 1 "const_int_operand" "")
8302 (match_operand 2 "const_int_operand" "")]
8306 emit_insn (gen_prefetch_64 (operands[0], operands[1], operands[2]));
8308 emit_insn (gen_prefetch_32 (operands[0], operands[1], operands[2]));
8312 (define_insn "prefetch_64"
8313 [(prefetch (match_operand:DI 0 "address_operand" "p")
8314 (match_operand:DI 1 "const_int_operand" "n")
8315 (match_operand:DI 2 "const_int_operand" "n"))]
8318 static const char * const prefetch_instr[2][2] = {
8320 "prefetch\t[%a0], 1", /* no locality: prefetch for one read */
8321 "prefetch\t[%a0], 0", /* medium to high locality: prefetch for several reads */
8324 "prefetch\t[%a0], 3", /* no locality: prefetch for one write */
8325 "prefetch\t[%a0], 2", /* medium to high locality: prefetch for several writes */
8328 int read_or_write = INTVAL (operands[1]);
8329 int locality = INTVAL (operands[2]);
8331 if (read_or_write != 0 && read_or_write != 1)
8333 if (locality < 0 || locality > 3)
8335 return prefetch_instr [read_or_write][locality == 0 ? 0 : 1];
8337 [(set_attr "type" "load")])
8339 (define_insn "prefetch_32"
8340 [(prefetch (match_operand:SI 0 "address_operand" "p")
8341 (match_operand:SI 1 "const_int_operand" "n")
8342 (match_operand:SI 2 "const_int_operand" "n"))]
8345 static const char * const prefetch_instr[2][2] = {
8347 "prefetch\t[%a0], 1", /* no locality: prefetch for one read */
8348 "prefetch\t[%a0], 0", /* medium to high locality: prefetch for several reads */
8351 "prefetch\t[%a0], 3", /* no locality: prefetch for one write */
8352 "prefetch\t[%a0], 2", /* medium to high locality: prefetch for several writes */
8355 int read_or_write = INTVAL (operands[1]);
8356 int locality = INTVAL (operands[2]);
8358 if (read_or_write != 0 && read_or_write != 1)
8360 if (locality < 0 || locality > 3)
8362 return prefetch_instr [read_or_write][locality == 0 ? 0 : 1];
8364 [(set_attr "type" "load")])
8366 (define_expand "prologue"
8368 "flag_pic && current_function_uses_pic_offset_table"
8370 load_pic_register ();
8374 ;; We need to reload %l7 for -mflat -fpic,
8375 ;; otherwise %l7 should be preserved simply
8376 ;; by loading the function's register window
8377 (define_expand "exception_receiver"
8379 "TARGET_FLAT && flag_pic"
8381 load_pic_register ();
8386 (define_expand "builtin_setjmp_receiver"
8387 [(label_ref (match_operand 0 "" ""))]
8388 "TARGET_FLAT && flag_pic"
8390 load_pic_register ();
8395 [(trap_if (const_int 1) (const_int 5))]
8398 [(set_attr "type" "trap")])
8400 (define_expand "conditional_trap"
8401 [(trap_if (match_operator 0 "noov_compare_op"
8402 [(match_dup 2) (match_dup 3)])
8403 (match_operand:SI 1 "arith_operand" ""))]
8405 "operands[2] = gen_compare_reg (GET_CODE (operands[0]),
8406 sparc_compare_op0, sparc_compare_op1);
8407 operands[3] = const0_rtx;")
8410 [(trap_if (match_operator 0 "noov_compare_op" [(reg:CC 100) (const_int 0)])
8411 (match_operand:SI 1 "arith_operand" "rM"))]
8414 [(set_attr "type" "trap")])
8417 [(trap_if (match_operator 0 "noov_compare_op" [(reg:CCX 100) (const_int 0)])
8418 (match_operand:SI 1 "arith_operand" "rM"))]
8421 [(set_attr "type" "trap")])
8424 (define_insn "tgd_hi22"
8425 [(set (match_operand:SI 0 "register_operand" "=r")
8426 (high:SI (unspec:SI [(match_operand 1 "tgd_symbolic_operand" "")]
8429 "sethi\\t%%tgd_hi22(%a1), %0")
8431 (define_insn "tgd_lo10"
8432 [(set (match_operand:SI 0 "register_operand" "=r")
8433 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
8434 (unspec:SI [(match_operand 2 "tgd_symbolic_operand" "")]
8437 "add\\t%1, %%tgd_lo10(%a2), %0")
8439 (define_insn "tgd_add32"
8440 [(set (match_operand:SI 0 "register_operand" "=r")
8441 (plus:SI (match_operand:SI 1 "register_operand" "r")
8442 (unspec:SI [(match_operand:SI 2 "register_operand" "r")
8443 (match_operand 3 "tgd_symbolic_operand" "")]
8445 "TARGET_TLS && TARGET_ARCH32"
8446 "add\\t%1, %2, %0, %%tgd_add(%a3)")
8448 (define_insn "tgd_add64"
8449 [(set (match_operand:DI 0 "register_operand" "=r")
8450 (plus:DI (match_operand:DI 1 "register_operand" "r")
8451 (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8452 (match_operand 3 "tgd_symbolic_operand" "")]
8454 "TARGET_TLS && TARGET_ARCH64"
8455 "add\\t%1, %2, %0, %%tgd_add(%a3)")
8457 (define_insn "tgd_call32"
8458 [(set (match_operand 0 "register_operand" "=r")
8459 (call (mem:SI (unspec:SI [(match_operand:SI 1 "symbolic_operand" "s")
8460 (match_operand 2 "tgd_symbolic_operand" "")]
8462 (match_operand 3 "" "")))
8463 (clobber (reg:SI 15))]
8464 "TARGET_TLS && TARGET_ARCH32"
8465 "call\t%a1, %%tgd_call(%a2)%#"
8466 [(set_attr "type" "call")])
8468 (define_insn "tgd_call64"
8469 [(set (match_operand 0 "register_operand" "=r")
8470 (call (mem:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "s")
8471 (match_operand 2 "tgd_symbolic_operand" "")]
8473 (match_operand 3 "" "")))
8474 (clobber (reg:DI 15))]
8475 "TARGET_TLS && TARGET_ARCH64"
8476 "call\t%a1, %%tgd_call(%a2)%#"
8477 [(set_attr "type" "call")])
8479 (define_insn "tldm_hi22"
8480 [(set (match_operand:SI 0 "register_operand" "=r")
8481 (high:SI (unspec:SI [(const_int 0)] UNSPEC_TLSLDM)))]
8483 "sethi\\t%%tldm_hi22(%&), %0")
8485 (define_insn "tldm_lo10"
8486 [(set (match_operand:SI 0 "register_operand" "=r")
8487 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
8488 (unspec:SI [(const_int 0)] UNSPEC_TLSLDM)))]
8490 "add\\t%1, %%tldm_lo10(%&), %0")
8492 (define_insn "tldm_add32"
8493 [(set (match_operand:SI 0 "register_operand" "=r")
8494 (plus:SI (match_operand:SI 1 "register_operand" "r")
8495 (unspec:SI [(match_operand:SI 2 "register_operand" "r")]
8497 "TARGET_TLS && TARGET_ARCH32"
8498 "add\\t%1, %2, %0, %%tldm_add(%&)")
8500 (define_insn "tldm_add64"
8501 [(set (match_operand:DI 0 "register_operand" "=r")
8502 (plus:DI (match_operand:DI 1 "register_operand" "r")
8503 (unspec:DI [(match_operand:SI 2 "register_operand" "r")]
8505 "TARGET_TLS && TARGET_ARCH64"
8506 "add\\t%1, %2, %0, %%tldm_add(%&)")
8508 (define_insn "tldm_call32"
8509 [(set (match_operand 0 "register_operand" "=r")
8510 (call (mem:SI (unspec:SI [(match_operand:SI 1 "symbolic_operand" "s")]
8512 (match_operand 2 "" "")))
8513 (clobber (reg:SI 15))]
8514 "TARGET_TLS && TARGET_ARCH32"
8515 "call\t%a1, %%tldm_call(%&)%#"
8516 [(set_attr "type" "call")])
8518 (define_insn "tldm_call64"
8519 [(set (match_operand 0 "register_operand" "=r")
8520 (call (mem:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "s")]
8522 (match_operand 2 "" "")))
8523 (clobber (reg:DI 15))]
8524 "TARGET_TLS && TARGET_ARCH64"
8525 "call\t%a1, %%tldm_call(%&)%#"
8526 [(set_attr "type" "call")])
8528 (define_insn "tldo_hix22"
8529 [(set (match_operand:SI 0 "register_operand" "=r")
8530 (high:SI (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")]
8533 "sethi\\t%%tldo_hix22(%a1), %0")
8535 (define_insn "tldo_lox10"
8536 [(set (match_operand:SI 0 "register_operand" "=r")
8537 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
8538 (unspec:SI [(match_operand 2 "tld_symbolic_operand" "")]
8541 "xor\\t%1, %%tldo_lox10(%a2), %0")
8543 (define_insn "tldo_add32"
8544 [(set (match_operand:SI 0 "register_operand" "=r")
8545 (plus:SI (match_operand:SI 1 "register_operand" "r")
8546 (unspec:SI [(match_operand:SI 2 "register_operand" "r")
8547 (match_operand 3 "tld_symbolic_operand" "")]
8549 "TARGET_TLS && TARGET_ARCH32"
8550 "add\\t%1, %2, %0, %%tldo_add(%a3)")
8552 (define_insn "tldo_add64"
8553 [(set (match_operand:DI 0 "register_operand" "=r")
8554 (plus:DI (match_operand:DI 1 "register_operand" "r")
8555 (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8556 (match_operand 3 "tld_symbolic_operand" "")]
8558 "TARGET_TLS && TARGET_ARCH64"
8559 "add\\t%1, %2, %0, %%tldo_add(%a3)")
8561 (define_insn "tie_hi22"
8562 [(set (match_operand:SI 0 "register_operand" "=r")
8563 (high:SI (unspec:SI [(match_operand 1 "tie_symbolic_operand" "")]
8566 "sethi\\t%%tie_hi22(%a1), %0")
8568 (define_insn "tie_lo10"
8569 [(set (match_operand:SI 0 "register_operand" "=r")
8570 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
8571 (unspec:SI [(match_operand 2 "tie_symbolic_operand" "")]
8574 "add\\t%1, %%tie_lo10(%a2), %0")
8576 (define_insn "tie_ld32"
8577 [(set (match_operand:SI 0 "register_operand" "=r")
8578 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
8579 (match_operand:SI 2 "register_operand" "r")
8580 (match_operand 3 "tie_symbolic_operand" "")]
8582 "TARGET_TLS && TARGET_ARCH32"
8583 "ld\\t[%1 + %2], %0, %%tie_ld(%a3)"
8584 [(set_attr "type" "load")])
8586 (define_insn "tie_ld64"
8587 [(set (match_operand:DI 0 "register_operand" "=r")
8588 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
8589 (match_operand:SI 2 "register_operand" "r")
8590 (match_operand 3 "tie_symbolic_operand" "")]
8592 "TARGET_TLS && TARGET_ARCH64"
8593 "ldx\\t[%1 + %2], %0, %%tie_ldx(%a3)"
8594 [(set_attr "type" "load")])
8596 (define_insn "tie_add32"
8597 [(set (match_operand:SI 0 "register_operand" "=r")
8598 (plus:SI (match_operand:SI 1 "register_operand" "r")
8599 (unspec:SI [(match_operand:SI 2 "register_operand" "r")
8600 (match_operand 3 "tld_symbolic_operand" "")]
8602 "TARGET_SUN_TLS && TARGET_ARCH32"
8603 "add\\t%1, %2, %0, %%tie_add(%a3)")
8605 (define_insn "tie_add64"
8606 [(set (match_operand:DI 0 "register_operand" "=r")
8607 (plus:DI (match_operand:DI 1 "register_operand" "r")
8608 (unspec:DI [(match_operand:DI 2 "register_operand" "r")
8609 (match_operand 3 "tld_symbolic_operand" "")]
8611 "TARGET_SUN_TLS && TARGET_ARCH64"
8612 "add\\t%1, %2, %0, %%tie_add(%a3)")
8614 (define_insn "tle_hix22_sp32"
8615 [(set (match_operand:SI 0 "register_operand" "=r")
8616 (high:SI (unspec:SI [(match_operand 1 "tle_symbolic_operand" "")]
8618 "TARGET_TLS && TARGET_ARCH32"
8619 "sethi\\t%%tle_hix22(%a1), %0")
8621 (define_insn "tle_lox10_sp32"
8622 [(set (match_operand:SI 0 "register_operand" "=r")
8623 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
8624 (unspec:SI [(match_operand 2 "tle_symbolic_operand" "")]
8626 "TARGET_TLS && TARGET_ARCH32"
8627 "xor\\t%1, %%tle_lox10(%a2), %0")
8629 (define_insn "tle_hix22_sp64"
8630 [(set (match_operand:DI 0 "register_operand" "=r")
8631 (high:DI (unspec:DI [(match_operand 1 "tle_symbolic_operand" "")]
8633 "TARGET_TLS && TARGET_ARCH64"
8634 "sethi\\t%%tle_hix22(%a1), %0")
8636 (define_insn "tle_lox10_sp64"
8637 [(set (match_operand:DI 0 "register_operand" "=r")
8638 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
8639 (unspec:DI [(match_operand 2 "tle_symbolic_operand" "")]
8641 "TARGET_TLS && TARGET_ARCH64"
8642 "xor\\t%1, %%tle_lox10(%a2), %0")
8644 ;; Now patterns combining tldo_add{32,64} with some integer loads or stores
8645 (define_insn "*tldo_ldub_sp32"
8646 [(set (match_operand:QI 0 "register_operand" "=r")
8647 (mem:QI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
8648 (match_operand 3 "tld_symbolic_operand" "")]
8650 (match_operand:SI 1 "register_operand" "r"))))]
8651 "TARGET_TLS && TARGET_ARCH32"
8652 "ldub\t[%1 + %2], %0, %%tldo_add(%3)"
8653 [(set_attr "type" "load")
8654 (set_attr "us3load_type" "3cycle")])
8656 (define_insn "*tldo_ldub1_sp32"
8657 [(set (match_operand:HI 0 "register_operand" "=r")
8658 (zero_extend:HI (mem:QI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
8659 (match_operand 3 "tld_symbolic_operand" "")]
8661 (match_operand:SI 1 "register_operand" "r")))))]
8662 "TARGET_TLS && TARGET_ARCH32"
8663 "ldub\t[%1 + %2], %0, %%tldo_add(%3)"
8664 [(set_attr "type" "load")
8665 (set_attr "us3load_type" "3cycle")])
8667 (define_insn "*tldo_ldub2_sp32"
8668 [(set (match_operand:SI 0 "register_operand" "=r")
8669 (zero_extend:SI (mem:QI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
8670 (match_operand 3 "tld_symbolic_operand" "")]
8672 (match_operand:SI 1 "register_operand" "r")))))]
8673 "TARGET_TLS && TARGET_ARCH32"
8674 "ldub\t[%1 + %2], %0, %%tldo_add(%3)"
8675 [(set_attr "type" "load")
8676 (set_attr "us3load_type" "3cycle")])
8678 (define_insn "*tldo_ldsb1_sp32"
8679 [(set (match_operand:HI 0 "register_operand" "=r")
8680 (sign_extend:HI (mem:QI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
8681 (match_operand 3 "tld_symbolic_operand" "")]
8683 (match_operand:SI 1 "register_operand" "r")))))]
8684 "TARGET_TLS && TARGET_ARCH32"
8685 "ldsb\t[%1 + %2], %0, %%tldo_add(%3)"
8686 [(set_attr "type" "sload")
8687 (set_attr "us3load_type" "3cycle")])
8689 (define_insn "*tldo_ldsb2_sp32"
8690 [(set (match_operand:SI 0 "register_operand" "=r")
8691 (sign_extend:SI (mem:QI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
8692 (match_operand 3 "tld_symbolic_operand" "")]
8694 (match_operand:SI 1 "register_operand" "r")))))]
8695 "TARGET_TLS && TARGET_ARCH32"
8696 "ldsb\t[%1 + %2], %0, %%tldo_add(%3)"
8697 [(set_attr "type" "sload")
8698 (set_attr "us3load_type" "3cycle")])
8700 (define_insn "*tldo_ldub_sp64"
8701 [(set (match_operand:QI 0 "register_operand" "=r")
8702 (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8703 (match_operand 3 "tld_symbolic_operand" "")]
8705 (match_operand:DI 1 "register_operand" "r"))))]
8706 "TARGET_TLS && TARGET_ARCH64"
8707 "ldub\t[%1 + %2], %0, %%tldo_add(%3)"
8708 [(set_attr "type" "load")
8709 (set_attr "us3load_type" "3cycle")])
8711 (define_insn "*tldo_ldub1_sp64"
8712 [(set (match_operand:HI 0 "register_operand" "=r")
8713 (zero_extend:HI (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8714 (match_operand 3 "tld_symbolic_operand" "")]
8716 (match_operand:DI 1 "register_operand" "r")))))]
8717 "TARGET_TLS && TARGET_ARCH64"
8718 "ldub\t[%1 + %2], %0, %%tldo_add(%3)"
8719 [(set_attr "type" "load")
8720 (set_attr "us3load_type" "3cycle")])
8722 (define_insn "*tldo_ldub2_sp64"
8723 [(set (match_operand:SI 0 "register_operand" "=r")
8724 (zero_extend:SI (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8725 (match_operand 3 "tld_symbolic_operand" "")]
8727 (match_operand:DI 1 "register_operand" "r")))))]
8728 "TARGET_TLS && TARGET_ARCH64"
8729 "ldub\t[%1 + %2], %0, %%tldo_add(%3)"
8730 [(set_attr "type" "load")
8731 (set_attr "us3load_type" "3cycle")])
8733 (define_insn "*tldo_ldub3_sp64"
8734 [(set (match_operand:DI 0 "register_operand" "=r")
8735 (zero_extend:DI (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8736 (match_operand 3 "tld_symbolic_operand" "")]
8738 (match_operand:DI 1 "register_operand" "r")))))]
8739 "TARGET_TLS && TARGET_ARCH64"
8740 "ldub\t[%1 + %2], %0, %%tldo_add(%3)"
8741 [(set_attr "type" "load")
8742 (set_attr "us3load_type" "3cycle")])
8744 (define_insn "*tldo_ldsb1_sp64"
8745 [(set (match_operand:HI 0 "register_operand" "=r")
8746 (sign_extend:HI (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8747 (match_operand 3 "tld_symbolic_operand" "")]
8749 (match_operand:DI 1 "register_operand" "r")))))]
8750 "TARGET_TLS && TARGET_ARCH64"
8751 "ldsb\t[%1 + %2], %0, %%tldo_add(%3)"
8752 [(set_attr "type" "sload")
8753 (set_attr "us3load_type" "3cycle")])
8755 (define_insn "*tldo_ldsb2_sp64"
8756 [(set (match_operand:SI 0 "register_operand" "=r")
8757 (sign_extend:SI (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8758 (match_operand 3 "tld_symbolic_operand" "")]
8760 (match_operand:DI 1 "register_operand" "r")))))]
8761 "TARGET_TLS && TARGET_ARCH64"
8762 "ldsb\t[%1 + %2], %0, %%tldo_add(%3)"
8763 [(set_attr "type" "sload")
8764 (set_attr "us3load_type" "3cycle")])
8766 (define_insn "*tldo_ldsb3_sp64"
8767 [(set (match_operand:DI 0 "register_operand" "=r")
8768 (sign_extend:DI (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8769 (match_operand 3 "tld_symbolic_operand" "")]
8771 (match_operand:DI 1 "register_operand" "r")))))]
8772 "TARGET_TLS && TARGET_ARCH64"
8773 "ldsb\t[%1 + %2], %0, %%tldo_add(%3)"
8774 [(set_attr "type" "sload")
8775 (set_attr "us3load_type" "3cycle")])
8777 (define_insn "*tldo_lduh_sp32"
8778 [(set (match_operand:HI 0 "register_operand" "=r")
8779 (mem:HI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
8780 (match_operand 3 "tld_symbolic_operand" "")]
8782 (match_operand:SI 1 "register_operand" "r"))))]
8783 "TARGET_TLS && TARGET_ARCH32"
8784 "lduh\t[%1 + %2], %0, %%tldo_add(%3)"
8785 [(set_attr "type" "load")
8786 (set_attr "us3load_type" "3cycle")])
8788 (define_insn "*tldo_lduh1_sp32"
8789 [(set (match_operand:SI 0 "register_operand" "=r")
8790 (zero_extend:SI (mem:HI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
8791 (match_operand 3 "tld_symbolic_operand" "")]
8793 (match_operand:SI 1 "register_operand" "r")))))]
8794 "TARGET_TLS && TARGET_ARCH32"
8795 "lduh\t[%1 + %2], %0, %%tldo_add(%3)"
8796 [(set_attr "type" "load")
8797 (set_attr "us3load_type" "3cycle")])
8799 (define_insn "*tldo_ldsh1_sp32"
8800 [(set (match_operand:SI 0 "register_operand" "=r")
8801 (sign_extend:SI (mem:HI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
8802 (match_operand 3 "tld_symbolic_operand" "")]
8804 (match_operand:SI 1 "register_operand" "r")))))]
8805 "TARGET_TLS && TARGET_ARCH32"
8806 "ldsh\t[%1 + %2], %0, %%tldo_add(%3)"
8807 [(set_attr "type" "sload")
8808 (set_attr "us3load_type" "3cycle")])
8810 (define_insn "*tldo_lduh_sp64"
8811 [(set (match_operand:HI 0 "register_operand" "=r")
8812 (mem:HI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8813 (match_operand 3 "tld_symbolic_operand" "")]
8815 (match_operand:DI 1 "register_operand" "r"))))]
8816 "TARGET_TLS && TARGET_ARCH64"
8817 "lduh\t[%1 + %2], %0, %%tldo_add(%3)"
8818 [(set_attr "type" "load")
8819 (set_attr "us3load_type" "3cycle")])
8821 (define_insn "*tldo_lduh1_sp64"
8822 [(set (match_operand:SI 0 "register_operand" "=r")
8823 (zero_extend:SI (mem:HI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8824 (match_operand 3 "tld_symbolic_operand" "")]
8826 (match_operand:DI 1 "register_operand" "r")))))]
8827 "TARGET_TLS && TARGET_ARCH64"
8828 "lduh\t[%1 + %2], %0, %%tldo_add(%3)"
8829 [(set_attr "type" "load")
8830 (set_attr "us3load_type" "3cycle")])
8832 (define_insn "*tldo_lduh2_sp64"
8833 [(set (match_operand:DI 0 "register_operand" "=r")
8834 (zero_extend:DI (mem:HI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8835 (match_operand 3 "tld_symbolic_operand" "")]
8837 (match_operand:DI 1 "register_operand" "r")))))]
8838 "TARGET_TLS && TARGET_ARCH64"
8839 "lduh\t[%1 + %2], %0, %%tldo_add(%3)"
8840 [(set_attr "type" "load")
8841 (set_attr "us3load_type" "3cycle")])
8843 (define_insn "*tldo_ldsh1_sp64"
8844 [(set (match_operand:SI 0 "register_operand" "=r")
8845 (sign_extend:SI (mem:HI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8846 (match_operand 3 "tld_symbolic_operand" "")]
8848 (match_operand:DI 1 "register_operand" "r")))))]
8849 "TARGET_TLS && TARGET_ARCH64"
8850 "ldsh\t[%1 + %2], %0, %%tldo_add(%3)"
8851 [(set_attr "type" "sload")
8852 (set_attr "us3load_type" "3cycle")])
8854 (define_insn "*tldo_ldsh2_sp64"
8855 [(set (match_operand:DI 0 "register_operand" "=r")
8856 (sign_extend:DI (mem:HI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8857 (match_operand 3 "tld_symbolic_operand" "")]
8859 (match_operand:DI 1 "register_operand" "r")))))]
8860 "TARGET_TLS && TARGET_ARCH64"
8861 "ldsh\t[%1 + %2], %0, %%tldo_add(%3)"
8862 [(set_attr "type" "sload")
8863 (set_attr "us3load_type" "3cycle")])
8865 (define_insn "*tldo_lduw_sp32"
8866 [(set (match_operand:SI 0 "register_operand" "=r")
8867 (mem:SI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
8868 (match_operand 3 "tld_symbolic_operand" "")]
8870 (match_operand:SI 1 "register_operand" "r"))))]
8871 "TARGET_TLS && TARGET_ARCH32"
8872 "ld\t[%1 + %2], %0, %%tldo_add(%3)"
8873 [(set_attr "type" "load")])
8875 (define_insn "*tldo_lduw_sp64"
8876 [(set (match_operand:SI 0 "register_operand" "=r")
8877 (mem:SI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8878 (match_operand 3 "tld_symbolic_operand" "")]
8880 (match_operand:DI 1 "register_operand" "r"))))]
8881 "TARGET_TLS && TARGET_ARCH64"
8882 "lduw\t[%1 + %2], %0, %%tldo_add(%3)"
8883 [(set_attr "type" "load")])
8885 (define_insn "*tldo_lduw1_sp64"
8886 [(set (match_operand:DI 0 "register_operand" "=r")
8887 (zero_extend:DI (mem:SI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8888 (match_operand 3 "tld_symbolic_operand" "")]
8890 (match_operand:DI 1 "register_operand" "r")))))]
8891 "TARGET_TLS && TARGET_ARCH64"
8892 "lduw\t[%1 + %2], %0, %%tldo_add(%3)"
8893 [(set_attr "type" "load")])
8895 (define_insn "*tldo_ldsw1_sp64"
8896 [(set (match_operand:DI 0 "register_operand" "=r")
8897 (sign_extend:DI (mem:SI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8898 (match_operand 3 "tld_symbolic_operand" "")]
8900 (match_operand:DI 1 "register_operand" "r")))))]
8901 "TARGET_TLS && TARGET_ARCH64"
8902 "ldsw\t[%1 + %2], %0, %%tldo_add(%3)"
8903 [(set_attr "type" "sload")
8904 (set_attr "us3load_type" "3cycle")])
8906 (define_insn "*tldo_ldx_sp64"
8907 [(set (match_operand:DI 0 "register_operand" "=r")
8908 (mem:DI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8909 (match_operand 3 "tld_symbolic_operand" "")]
8911 (match_operand:DI 1 "register_operand" "r"))))]
8912 "TARGET_TLS && TARGET_ARCH64"
8913 "ldx\t[%1 + %2], %0, %%tldo_add(%3)"
8914 [(set_attr "type" "load")])
8916 (define_insn "*tldo_stb_sp32"
8917 [(set (mem:QI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
8918 (match_operand 3 "tld_symbolic_operand" "")]
8920 (match_operand:SI 1 "register_operand" "r")))
8921 (match_operand:QI 0 "register_operand" "=r"))]
8922 "TARGET_TLS && TARGET_ARCH32"
8923 "stb\t%0, [%1 + %2], %%tldo_add(%3)"
8924 [(set_attr "type" "store")])
8926 (define_insn "*tldo_stb_sp64"
8927 [(set (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8928 (match_operand 3 "tld_symbolic_operand" "")]
8930 (match_operand:DI 1 "register_operand" "r")))
8931 (match_operand:QI 0 "register_operand" "=r"))]
8932 "TARGET_TLS && TARGET_ARCH64"
8933 "stb\t%0, [%1 + %2], %%tldo_add(%3)"
8934 [(set_attr "type" "store")])
8936 (define_insn "*tldo_sth_sp32"
8937 [(set (mem:HI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
8938 (match_operand 3 "tld_symbolic_operand" "")]
8940 (match_operand:SI 1 "register_operand" "r")))
8941 (match_operand:HI 0 "register_operand" "=r"))]
8942 "TARGET_TLS && TARGET_ARCH32"
8943 "sth\t%0, [%1 + %2], %%tldo_add(%3)"
8944 [(set_attr "type" "store")])
8946 (define_insn "*tldo_sth_sp64"
8947 [(set (mem:HI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8948 (match_operand 3 "tld_symbolic_operand" "")]
8950 (match_operand:DI 1 "register_operand" "r")))
8951 (match_operand:HI 0 "register_operand" "=r"))]
8952 "TARGET_TLS && TARGET_ARCH64"
8953 "sth\t%0, [%1 + %2], %%tldo_add(%3)"
8954 [(set_attr "type" "store")])
8956 (define_insn "*tldo_stw_sp32"
8957 [(set (mem:SI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
8958 (match_operand 3 "tld_symbolic_operand" "")]
8960 (match_operand:SI 1 "register_operand" "r")))
8961 (match_operand:SI 0 "register_operand" "=r"))]
8962 "TARGET_TLS && TARGET_ARCH32"
8963 "st\t%0, [%1 + %2], %%tldo_add(%3)"
8964 [(set_attr "type" "store")])
8966 (define_insn "*tldo_stw_sp64"
8967 [(set (mem:SI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8968 (match_operand 3 "tld_symbolic_operand" "")]
8970 (match_operand:DI 1 "register_operand" "r")))
8971 (match_operand:SI 0 "register_operand" "=r"))]
8972 "TARGET_TLS && TARGET_ARCH64"
8973 "stw\t%0, [%1 + %2], %%tldo_add(%3)"
8974 [(set_attr "type" "store")])
8976 (define_insn "*tldo_stx_sp64"
8977 [(set (mem:DI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8978 (match_operand 3 "tld_symbolic_operand" "")]
8980 (match_operand:DI 1 "register_operand" "r")))
8981 (match_operand:DI 0 "register_operand" "=r"))]
8982 "TARGET_TLS && TARGET_ARCH64"
8983 "stx\t%0, [%1 + %2], %%tldo_add(%3)"
8984 [(set_attr "type" "store")])