1 ;; Machine description for SPARC chip for GCC
2 ;; Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by Michael Tiemann (tiemann@cygnus.com)
6 ;; 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
9 ;; This file is part of GCC.
11 ;; GCC is free software; you can redistribute it and/or modify
12 ;; it under the terms of the GNU General Public License as published by
13 ;; the Free Software Foundation; either version 3, or (at your option)
16 ;; GCC is distributed in the hope that it will be useful,
17 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
18 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 ;; GNU General Public License for more details.
21 ;; You should have received a copy of the GNU General Public License
22 ;; along with GCC; see the file COPYING3. If not see
23 ;; <http://www.gnu.org/licenses/>.
25 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 (UNSPEC_UPDATE_RETURN 1)
30 (UNSPEC_LOAD_PCREL_SYM 2)
31 (UNSPEC_MOVE_PIC_LABEL 5)
37 (UNSPEC_EMB_TEXTUHI 13)
38 (UNSPEC_EMB_TEXTHI 14)
39 (UNSPEC_EMB_TEXTULO 15)
49 (UNSPEC_TLSLD_BASE 35)
79 ;; The upper 32 fp regs on the v9 can't hold SFmode values. To deal with this
80 ;; a second register class, EXTRA_FP_REGS, exists for the v9 chip. The name
81 ;; is a bit of a misnomer as it covers all 64 fp regs. The corresponding
82 ;; constraint letter is 'e'. To avoid any confusion, 'e' is used instead of
83 ;; 'f' for all DF/TFmode values, including those that are specific to the v8.
86 ;; Attribute for cpu type.
87 ;; These must match the values for enum processor_type in sparc.h.
94 hypersparc,sparclite86x,
101 (const (symbol_ref "sparc_cpu_attr")))
103 ;; Attribute for the instruction set.
104 ;; At present we only need to distinguish v9/!v9, but for clarity we
105 ;; test TARGET_V8 too.
106 (define_attr "isa" "v7,v8,v9,sparclet"
108 (cond [(symbol_ref "TARGET_V9") (const_string "v9")
109 (symbol_ref "TARGET_V8") (const_string "v8")
110 (symbol_ref "TARGET_SPARCLET") (const_string "sparclet")]
111 (const_string "v7"))))
117 uncond_branch,branch,call,sibcall,call_no_delay_slot,return,
125 fga,fgm_pack,fgm_mul,fgm_pdist,fgm_cmp,
128 multi,savew,flushw,iflush,trap"
129 (const_string "ialu"))
131 ;; True if branch/call has empty delay slot and will emit a nop in it
132 (define_attr "empty_delay_slot" "false,true"
133 (symbol_ref "empty_delay_slot (insn)"))
135 (define_attr "branch_type" "none,icc,fcc,reg"
136 (const_string "none"))
138 (define_attr "pic" "false,true"
139 (symbol_ref "flag_pic != 0"))
141 (define_attr "calls_alloca" "false,true"
142 (symbol_ref "cfun->calls_alloca != 0"))
144 (define_attr "calls_eh_return" "false,true"
145 (symbol_ref "crtl->calls_eh_return !=0 "))
147 (define_attr "leaf_function" "false,true"
148 (symbol_ref "current_function_uses_only_leaf_regs != 0"))
150 (define_attr "delayed_branch" "false,true"
151 (symbol_ref "flag_delayed_branch != 0"))
153 ;; Length (in # of insns).
154 ;; Beware that setting a length greater or equal to 3 for conditional branches
155 ;; has a side-effect (see output_cbranch and output_v9branch).
156 (define_attr "length" ""
157 (cond [(eq_attr "type" "uncond_branch,call")
158 (if_then_else (eq_attr "empty_delay_slot" "true")
161 (eq_attr "type" "sibcall")
162 (if_then_else (eq_attr "leaf_function" "true")
163 (if_then_else (eq_attr "empty_delay_slot" "true")
166 (if_then_else (eq_attr "empty_delay_slot" "true")
169 (eq_attr "branch_type" "icc")
170 (if_then_else (match_operand 0 "noov_compare64_operator" "")
171 (if_then_else (lt (pc) (match_dup 1))
172 (if_then_else (lt (minus (match_dup 1) (pc)) (const_int 260000))
173 (if_then_else (eq_attr "empty_delay_slot" "true")
176 (if_then_else (eq_attr "empty_delay_slot" "true")
179 (if_then_else (lt (minus (pc) (match_dup 1)) (const_int 260000))
180 (if_then_else (eq_attr "empty_delay_slot" "true")
183 (if_then_else (eq_attr "empty_delay_slot" "true")
186 (if_then_else (eq_attr "empty_delay_slot" "true")
189 (eq_attr "branch_type" "fcc")
190 (if_then_else (match_operand 0 "fcc0_register_operand" "")
191 (if_then_else (eq_attr "empty_delay_slot" "true")
192 (if_then_else (eq (symbol_ref "TARGET_V9") (const_int 0))
195 (if_then_else (eq (symbol_ref "TARGET_V9") (const_int 0))
198 (if_then_else (lt (pc) (match_dup 2))
199 (if_then_else (lt (minus (match_dup 2) (pc)) (const_int 260000))
200 (if_then_else (eq_attr "empty_delay_slot" "true")
203 (if_then_else (eq_attr "empty_delay_slot" "true")
206 (if_then_else (lt (minus (pc) (match_dup 2)) (const_int 260000))
207 (if_then_else (eq_attr "empty_delay_slot" "true")
210 (if_then_else (eq_attr "empty_delay_slot" "true")
213 (eq_attr "branch_type" "reg")
214 (if_then_else (lt (pc) (match_dup 2))
215 (if_then_else (lt (minus (match_dup 2) (pc)) (const_int 32000))
216 (if_then_else (eq_attr "empty_delay_slot" "true")
219 (if_then_else (eq_attr "empty_delay_slot" "true")
222 (if_then_else (lt (minus (pc) (match_dup 2)) (const_int 32000))
223 (if_then_else (eq_attr "empty_delay_slot" "true")
226 (if_then_else (eq_attr "empty_delay_slot" "true")
232 (define_attr "fptype" "single,double"
233 (const_string "single"))
235 ;; UltraSPARC-III integer load type.
236 (define_attr "us3load_type" "2cycle,3cycle"
237 (const_string "2cycle"))
239 (define_asm_attributes
240 [(set_attr "length" "2")
241 (set_attr "type" "multi")])
243 ;; Attributes for instruction and branch scheduling
244 (define_attr "tls_call_delay" "false,true"
245 (symbol_ref "tls_call_delay (insn)"))
247 (define_attr "in_call_delay" "false,true"
248 (cond [(eq_attr "type" "uncond_branch,branch,call,sibcall,call_no_delay_slot,multi")
249 (const_string "false")
250 (eq_attr "type" "load,fpload,store,fpstore")
251 (if_then_else (eq_attr "length" "1")
252 (const_string "true")
253 (const_string "false"))]
254 (if_then_else (and (eq_attr "length" "1")
255 (eq_attr "tls_call_delay" "true"))
256 (const_string "true")
257 (const_string "false"))))
259 (define_attr "eligible_for_sibcall_delay" "false,true"
260 (symbol_ref "eligible_for_sibcall_delay (insn)"))
262 (define_attr "eligible_for_return_delay" "false,true"
263 (symbol_ref "eligible_for_return_delay (insn)"))
265 ;; ??? !v9: Should implement the notion of predelay slots for floating-point
266 ;; branches. This would allow us to remove the nop always inserted before
267 ;; a floating point branch.
269 ;; ??? It is OK for fill_simple_delay_slots to put load/store instructions
270 ;; in a delay slot, but it is not OK for fill_eager_delay_slots to do so.
271 ;; This is because doing so will add several pipeline stalls to the path
272 ;; that the load/store did not come from. Unfortunately, there is no way
273 ;; to prevent fill_eager_delay_slots from using load/store without completely
274 ;; disabling them. For the SPEC benchmark set, this is a serious lose,
275 ;; because it prevents us from moving back the final store of inner loops.
277 (define_attr "in_branch_delay" "false,true"
278 (if_then_else (and (eq_attr "type" "!uncond_branch,branch,call,sibcall,call_no_delay_slot,multi")
279 (eq_attr "length" "1"))
280 (const_string "true")
281 (const_string "false")))
283 (define_attr "in_uncond_branch_delay" "false,true"
284 (if_then_else (and (eq_attr "type" "!uncond_branch,branch,call,sibcall,call_no_delay_slot,multi")
285 (eq_attr "length" "1"))
286 (const_string "true")
287 (const_string "false")))
289 (define_attr "in_annul_branch_delay" "false,true"
290 (if_then_else (and (eq_attr "type" "!uncond_branch,branch,call,sibcall,call_no_delay_slot,multi")
291 (eq_attr "length" "1"))
292 (const_string "true")
293 (const_string "false")))
295 (define_delay (eq_attr "type" "call")
296 [(eq_attr "in_call_delay" "true") (nil) (nil)])
298 (define_delay (eq_attr "type" "sibcall")
299 [(eq_attr "eligible_for_sibcall_delay" "true") (nil) (nil)])
301 (define_delay (eq_attr "type" "branch")
302 [(eq_attr "in_branch_delay" "true")
303 (nil) (eq_attr "in_annul_branch_delay" "true")])
305 (define_delay (eq_attr "type" "uncond_branch")
306 [(eq_attr "in_uncond_branch_delay" "true")
309 (define_delay (eq_attr "type" "return")
310 [(eq_attr "eligible_for_return_delay" "true") (nil) (nil)])
313 ;; Include SPARC DFA schedulers
315 (include "cypress.md")
316 (include "supersparc.md")
317 (include "hypersparc.md")
318 (include "sparclet.md")
319 (include "ultra1_2.md")
320 (include "ultra3.md")
321 (include "niagara.md")
322 (include "niagara2.md")
325 ;; Operand and operator predicates and constraints
327 (include "predicates.md")
328 (include "constraints.md")
331 ;; Compare instructions.
333 ;; We generate RTL for comparisons and branches by having the cmpxx
334 ;; patterns store away the operands. Then, the scc and bcc patterns
335 ;; emit RTL for both the compare and the branch.
337 ;; We do this because we want to generate different code for an sne and
338 ;; seq insn. In those cases, if the second operand of the compare is not
339 ;; const0_rtx, we want to compute the xor of the two operands and test
342 ;; We start with the DEFINE_EXPANDs, then the DEFINE_INSNs to match
343 ;; the patterns. Finally, we have the DEFINE_SPLITs for some of the scc
344 ;; insns that actually require more than one machine instruction.
346 (define_expand "cmpsi"
348 (compare:CC (match_operand:SI 0 "compare_operand" "")
349 (match_operand:SI 1 "arith_operand" "")))]
352 if (GET_CODE (operands[0]) == ZERO_EXTRACT && operands[1] != const0_rtx)
353 operands[0] = force_reg (SImode, operands[0]);
355 sparc_compare_op0 = operands[0];
356 sparc_compare_op1 = operands[1];
360 (define_expand "cmpdi"
362 (compare:CCX (match_operand:DI 0 "compare_operand" "")
363 (match_operand:DI 1 "arith_operand" "")))]
366 if (GET_CODE (operands[0]) == ZERO_EXTRACT && operands[1] != const0_rtx)
367 operands[0] = force_reg (DImode, operands[0]);
369 sparc_compare_op0 = operands[0];
370 sparc_compare_op1 = operands[1];
374 (define_expand "cmpsf"
375 ;; The 96 here isn't ever used by anyone.
377 (compare:CCFP (match_operand:SF 0 "register_operand" "")
378 (match_operand:SF 1 "register_operand" "")))]
381 sparc_compare_op0 = operands[0];
382 sparc_compare_op1 = operands[1];
386 (define_expand "cmpdf"
387 ;; The 96 here isn't ever used by anyone.
389 (compare:CCFP (match_operand:DF 0 "register_operand" "")
390 (match_operand:DF 1 "register_operand" "")))]
393 sparc_compare_op0 = operands[0];
394 sparc_compare_op1 = operands[1];
398 (define_expand "cmptf"
399 ;; The 96 here isn't ever used by anyone.
401 (compare:CCFP (match_operand:TF 0 "register_operand" "")
402 (match_operand:TF 1 "register_operand" "")))]
405 sparc_compare_op0 = operands[0];
406 sparc_compare_op1 = operands[1];
410 ;; Now the compare DEFINE_INSNs.
412 (define_insn "*cmpsi_insn"
414 (compare:CC (match_operand:SI 0 "register_operand" "r")
415 (match_operand:SI 1 "arith_operand" "rI")))]
418 [(set_attr "type" "compare")])
420 (define_insn "*cmpdi_sp64"
422 (compare:CCX (match_operand:DI 0 "register_operand" "r")
423 (match_operand:DI 1 "arith_operand" "rI")))]
426 [(set_attr "type" "compare")])
428 (define_insn "*cmpsf_fpe"
429 [(set (match_operand:CCFPE 0 "fcc_register_operand" "=c")
430 (compare:CCFPE (match_operand:SF 1 "register_operand" "f")
431 (match_operand:SF 2 "register_operand" "f")))]
435 return "fcmpes\t%0, %1, %2";
436 return "fcmpes\t%1, %2";
438 [(set_attr "type" "fpcmp")])
440 (define_insn "*cmpdf_fpe"
441 [(set (match_operand:CCFPE 0 "fcc_register_operand" "=c")
442 (compare:CCFPE (match_operand:DF 1 "register_operand" "e")
443 (match_operand:DF 2 "register_operand" "e")))]
447 return "fcmped\t%0, %1, %2";
448 return "fcmped\t%1, %2";
450 [(set_attr "type" "fpcmp")
451 (set_attr "fptype" "double")])
453 (define_insn "*cmptf_fpe"
454 [(set (match_operand:CCFPE 0 "fcc_register_operand" "=c")
455 (compare:CCFPE (match_operand:TF 1 "register_operand" "e")
456 (match_operand:TF 2 "register_operand" "e")))]
457 "TARGET_FPU && TARGET_HARD_QUAD"
460 return "fcmpeq\t%0, %1, %2";
461 return "fcmpeq\t%1, %2";
463 [(set_attr "type" "fpcmp")])
465 (define_insn "*cmpsf_fp"
466 [(set (match_operand:CCFP 0 "fcc_register_operand" "=c")
467 (compare:CCFP (match_operand:SF 1 "register_operand" "f")
468 (match_operand:SF 2 "register_operand" "f")))]
472 return "fcmps\t%0, %1, %2";
473 return "fcmps\t%1, %2";
475 [(set_attr "type" "fpcmp")])
477 (define_insn "*cmpdf_fp"
478 [(set (match_operand:CCFP 0 "fcc_register_operand" "=c")
479 (compare:CCFP (match_operand:DF 1 "register_operand" "e")
480 (match_operand:DF 2 "register_operand" "e")))]
484 return "fcmpd\t%0, %1, %2";
485 return "fcmpd\t%1, %2";
487 [(set_attr "type" "fpcmp")
488 (set_attr "fptype" "double")])
490 (define_insn "*cmptf_fp"
491 [(set (match_operand:CCFP 0 "fcc_register_operand" "=c")
492 (compare:CCFP (match_operand:TF 1 "register_operand" "e")
493 (match_operand:TF 2 "register_operand" "e")))]
494 "TARGET_FPU && TARGET_HARD_QUAD"
497 return "fcmpq\t%0, %1, %2";
498 return "fcmpq\t%1, %2";
500 [(set_attr "type" "fpcmp")])
502 ;; Next come the scc insns. For seq, sne, sgeu, and sltu, we can do this
503 ;; without jumps using the addx/subx instructions. For seq/sne on v9 we use
504 ;; the same code as v8 (the addx/subx method has more applications). The
505 ;; exception to this is "reg != 0" which can be done in one instruction on v9
506 ;; (so we do it). For the rest, on v9 we use conditional moves; on v8, we do
509 ;; Seq_special[_xxx] and sne_special[_xxx] clobber the CC reg, because they
510 ;; generate addcc/subcc instructions.
512 (define_expand "seqsi_special"
514 (xor:SI (match_operand:SI 1 "register_operand" "")
515 (match_operand:SI 2 "register_operand" "")))
516 (parallel [(set (match_operand:SI 0 "register_operand" "")
517 (eq:SI (match_dup 3) (const_int 0)))
518 (clobber (reg:CC 100))])]
520 { operands[3] = gen_reg_rtx (SImode); })
522 (define_expand "seqdi_special"
524 (xor:DI (match_operand:DI 1 "register_operand" "")
525 (match_operand:DI 2 "register_operand" "")))
526 (set (match_operand:DI 0 "register_operand" "")
527 (eq:DI (match_dup 3) (const_int 0)))]
529 { operands[3] = gen_reg_rtx (DImode); })
531 (define_expand "snesi_special"
533 (xor:SI (match_operand:SI 1 "register_operand" "")
534 (match_operand:SI 2 "register_operand" "")))
535 (parallel [(set (match_operand:SI 0 "register_operand" "")
536 (ne:SI (match_dup 3) (const_int 0)))
537 (clobber (reg:CC 100))])]
539 { operands[3] = gen_reg_rtx (SImode); })
541 (define_expand "snedi_special"
543 (xor:DI (match_operand:DI 1 "register_operand" "")
544 (match_operand:DI 2 "register_operand" "")))
545 (set (match_operand:DI 0 "register_operand" "")
546 (ne:DI (match_dup 3) (const_int 0)))]
548 { operands[3] = gen_reg_rtx (DImode); })
550 (define_expand "seqdi_special_trunc"
552 (xor:DI (match_operand:DI 1 "register_operand" "")
553 (match_operand:DI 2 "register_operand" "")))
554 (set (match_operand:SI 0 "register_operand" "")
555 (eq:SI (match_dup 3) (const_int 0)))]
557 { operands[3] = gen_reg_rtx (DImode); })
559 (define_expand "snedi_special_trunc"
561 (xor:DI (match_operand:DI 1 "register_operand" "")
562 (match_operand:DI 2 "register_operand" "")))
563 (set (match_operand:SI 0 "register_operand" "")
564 (ne:SI (match_dup 3) (const_int 0)))]
566 { operands[3] = gen_reg_rtx (DImode); })
568 (define_expand "seqsi_special_extend"
570 (xor:SI (match_operand:SI 1 "register_operand" "")
571 (match_operand:SI 2 "register_operand" "")))
572 (parallel [(set (match_operand:DI 0 "register_operand" "")
573 (eq:DI (match_dup 3) (const_int 0)))
574 (clobber (reg:CC 100))])]
576 { operands[3] = gen_reg_rtx (SImode); })
578 (define_expand "snesi_special_extend"
580 (xor:SI (match_operand:SI 1 "register_operand" "")
581 (match_operand:SI 2 "register_operand" "")))
582 (parallel [(set (match_operand:DI 0 "register_operand" "")
583 (ne:DI (match_dup 3) (const_int 0)))
584 (clobber (reg:CC 100))])]
586 { operands[3] = gen_reg_rtx (SImode); })
588 ;; ??? v9: Operand 0 needs a mode, so SImode was chosen.
589 ;; However, the code handles both SImode and DImode.
591 [(set (match_operand:SI 0 "int_register_operand" "")
592 (eq:SI (match_dup 1) (const_int 0)))]
595 if (GET_MODE (sparc_compare_op0) == SImode)
599 if (GET_MODE (operands[0]) == SImode)
600 pat = gen_seqsi_special (operands[0], sparc_compare_op0,
602 else if (! TARGET_ARCH64)
605 pat = gen_seqsi_special_extend (operands[0], sparc_compare_op0,
610 else if (GET_MODE (sparc_compare_op0) == DImode)
616 else if (GET_MODE (operands[0]) == SImode)
617 pat = gen_seqdi_special_trunc (operands[0], sparc_compare_op0,
620 pat = gen_seqdi_special (operands[0], sparc_compare_op0,
625 else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
628 = sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, EQ);
629 gcc_assert (code == NE);
630 emit_insn (gen_sne (operands[0]));
635 if (gen_v9_scc (EQ, operands))
642 ;; ??? v9: Operand 0 needs a mode, so SImode was chosen.
643 ;; However, the code handles both SImode and DImode.
645 [(set (match_operand:SI 0 "int_register_operand" "")
646 (ne:SI (match_dup 1) (const_int 0)))]
649 if (GET_MODE (sparc_compare_op0) == SImode)
653 if (GET_MODE (operands[0]) == SImode)
654 pat = gen_snesi_special (operands[0], sparc_compare_op0,
656 else if (! TARGET_ARCH64)
659 pat = gen_snesi_special_extend (operands[0], sparc_compare_op0,
664 else if (GET_MODE (sparc_compare_op0) == DImode)
670 else if (GET_MODE (operands[0]) == SImode)
671 pat = gen_snedi_special_trunc (operands[0], sparc_compare_op0,
674 pat = gen_snedi_special (operands[0], sparc_compare_op0,
679 else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
682 = sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, NE);
683 gcc_assert (code == NE);
684 emit_insn (gen_sne (operands[0]));
689 if (gen_v9_scc (NE, operands))
697 [(set (match_operand:SI 0 "int_register_operand" "")
698 (gt:SI (match_dup 1) (const_int 0)))]
701 if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
704 = sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, GT);
705 gcc_assert (code == NE);
706 emit_insn (gen_sne (operands[0]));
711 if (gen_v9_scc (GT, operands))
719 [(set (match_operand:SI 0 "int_register_operand" "")
720 (lt:SI (match_dup 1) (const_int 0)))]
723 if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
726 = sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, LT);
727 gcc_assert (code == NE);
728 emit_insn (gen_sne (operands[0]));
733 if (gen_v9_scc (LT, operands))
741 [(set (match_operand:SI 0 "int_register_operand" "")
742 (ge:SI (match_dup 1) (const_int 0)))]
745 if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
748 = sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, GE);
749 gcc_assert (code == NE);
750 emit_insn (gen_sne (operands[0]));
755 if (gen_v9_scc (GE, operands))
763 [(set (match_operand:SI 0 "int_register_operand" "")
764 (le:SI (match_dup 1) (const_int 0)))]
767 if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
770 = sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, LE);
771 gcc_assert (code == NE);
772 emit_insn (gen_sne (operands[0]));
777 if (gen_v9_scc (LE, operands))
784 (define_expand "sgtu"
785 [(set (match_operand:SI 0 "int_register_operand" "")
786 (gtu:SI (match_dup 1) (const_int 0)))]
793 /* We can do ltu easily, so if both operands are registers, swap them and
795 if ((GET_CODE (sparc_compare_op0) == REG
796 || GET_CODE (sparc_compare_op0) == SUBREG)
797 && (GET_CODE (sparc_compare_op1) == REG
798 || GET_CODE (sparc_compare_op1) == SUBREG))
800 tem = sparc_compare_op0;
801 sparc_compare_op0 = sparc_compare_op1;
802 sparc_compare_op1 = tem;
803 pat = gen_sltu (operands[0]);
812 if (gen_v9_scc (GTU, operands))
818 (define_expand "sltu"
819 [(set (match_operand:SI 0 "int_register_operand" "")
820 (ltu:SI (match_dup 1) (const_int 0)))]
825 if (gen_v9_scc (LTU, operands))
828 operands[1] = gen_compare_reg (LTU);
831 (define_expand "sgeu"
832 [(set (match_operand:SI 0 "int_register_operand" "")
833 (geu:SI (match_dup 1) (const_int 0)))]
838 if (gen_v9_scc (GEU, operands))
841 operands[1] = gen_compare_reg (GEU);
844 (define_expand "sleu"
845 [(set (match_operand:SI 0 "int_register_operand" "")
846 (leu:SI (match_dup 1) (const_int 0)))]
853 /* We can do geu easily, so if both operands are registers, swap them and
855 if ((GET_CODE (sparc_compare_op0) == REG
856 || GET_CODE (sparc_compare_op0) == SUBREG)
857 && (GET_CODE (sparc_compare_op1) == REG
858 || GET_CODE (sparc_compare_op1) == SUBREG))
860 tem = sparc_compare_op0;
861 sparc_compare_op0 = sparc_compare_op1;
862 sparc_compare_op1 = tem;
863 pat = gen_sgeu (operands[0]);
872 if (gen_v9_scc (LEU, operands))
878 ;; Now the DEFINE_INSNs for the scc cases.
880 ;; The SEQ and SNE patterns are special because they can be done
881 ;; without any branching and do not involve a COMPARE. We want
882 ;; them to always use the splits below so the results can be
885 (define_insn_and_split "*snesi_zero"
886 [(set (match_operand:SI 0 "register_operand" "=r")
887 (ne:SI (match_operand:SI 1 "register_operand" "r")
889 (clobber (reg:CC 100))]
893 [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
895 (set (match_dup 0) (ltu:SI (reg:CC 100) (const_int 0)))]
897 [(set_attr "length" "2")])
899 (define_insn_and_split "*neg_snesi_zero"
900 [(set (match_operand:SI 0 "register_operand" "=r")
901 (neg:SI (ne:SI (match_operand:SI 1 "register_operand" "r")
903 (clobber (reg:CC 100))]
907 [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
909 (set (match_dup 0) (neg:SI (ltu:SI (reg:CC 100) (const_int 0))))]
911 [(set_attr "length" "2")])
913 (define_insn_and_split "*snesi_zero_extend"
914 [(set (match_operand:DI 0 "register_operand" "=r")
915 (ne:DI (match_operand:SI 1 "register_operand" "r")
917 (clobber (reg:CC 100))]
921 [(set (reg:CC_NOOV 100) (compare:CC_NOOV (minus:SI (const_int 0)
924 (set (match_dup 0) (zero_extend:DI (plus:SI (plus:SI (const_int 0)
926 (ltu:SI (reg:CC_NOOV 100)
929 [(set_attr "length" "2")])
931 (define_insn_and_split "*snedi_zero"
932 [(set (match_operand:DI 0 "register_operand" "=&r")
933 (ne:DI (match_operand:DI 1 "register_operand" "r")
937 "&& ! reg_overlap_mentioned_p (operands[1], operands[0])"
938 [(set (match_dup 0) (const_int 0))
939 (set (match_dup 0) (if_then_else:DI (ne:DI (match_dup 1)
944 [(set_attr "length" "2")])
946 (define_insn_and_split "*neg_snedi_zero"
947 [(set (match_operand:DI 0 "register_operand" "=&r")
948 (neg:DI (ne:DI (match_operand:DI 1 "register_operand" "r")
952 "&& ! reg_overlap_mentioned_p (operands[1], operands[0])"
953 [(set (match_dup 0) (const_int 0))
954 (set (match_dup 0) (if_then_else:DI (ne:DI (match_dup 1)
959 [(set_attr "length" "2")])
961 (define_insn_and_split "*snedi_zero_trunc"
962 [(set (match_operand:SI 0 "register_operand" "=&r")
963 (ne:SI (match_operand:DI 1 "register_operand" "r")
967 "&& ! reg_overlap_mentioned_p (operands[1], operands[0])"
968 [(set (match_dup 0) (const_int 0))
969 (set (match_dup 0) (if_then_else:SI (ne:DI (match_dup 1)
974 [(set_attr "length" "2")])
976 (define_insn_and_split "*seqsi_zero"
977 [(set (match_operand:SI 0 "register_operand" "=r")
978 (eq:SI (match_operand:SI 1 "register_operand" "r")
980 (clobber (reg:CC 100))]
984 [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
986 (set (match_dup 0) (geu:SI (reg:CC 100) (const_int 0)))]
988 [(set_attr "length" "2")])
990 (define_insn_and_split "*neg_seqsi_zero"
991 [(set (match_operand:SI 0 "register_operand" "=r")
992 (neg:SI (eq:SI (match_operand:SI 1 "register_operand" "r")
994 (clobber (reg:CC 100))]
998 [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
1000 (set (match_dup 0) (neg:SI (geu:SI (reg:CC 100) (const_int 0))))]
1002 [(set_attr "length" "2")])
1004 (define_insn_and_split "*seqsi_zero_extend"
1005 [(set (match_operand:DI 0 "register_operand" "=r")
1006 (eq:DI (match_operand:SI 1 "register_operand" "r")
1008 (clobber (reg:CC 100))]
1012 [(set (reg:CC_NOOV 100) (compare:CC_NOOV (minus:SI (const_int 0)
1015 (set (match_dup 0) (zero_extend:DI (minus:SI (minus:SI (const_int 0)
1017 (ltu:SI (reg:CC_NOOV 100)
1020 [(set_attr "length" "2")])
1022 (define_insn_and_split "*seqdi_zero"
1023 [(set (match_operand:DI 0 "register_operand" "=&r")
1024 (eq:DI (match_operand:DI 1 "register_operand" "r")
1028 "&& ! reg_overlap_mentioned_p (operands[1], operands[0])"
1029 [(set (match_dup 0) (const_int 0))
1030 (set (match_dup 0) (if_then_else:DI (eq:DI (match_dup 1)
1035 [(set_attr "length" "2")])
1037 (define_insn_and_split "*neg_seqdi_zero"
1038 [(set (match_operand:DI 0 "register_operand" "=&r")
1039 (neg:DI (eq:DI (match_operand:DI 1 "register_operand" "r")
1043 "&& ! reg_overlap_mentioned_p (operands[1], operands[0])"
1044 [(set (match_dup 0) (const_int 0))
1045 (set (match_dup 0) (if_then_else:DI (eq:DI (match_dup 1)
1050 [(set_attr "length" "2")])
1052 (define_insn_and_split "*seqdi_zero_trunc"
1053 [(set (match_operand:SI 0 "register_operand" "=&r")
1054 (eq:SI (match_operand:DI 1 "register_operand" "r")
1058 "&& ! reg_overlap_mentioned_p (operands[1], operands[0])"
1059 [(set (match_dup 0) (const_int 0))
1060 (set (match_dup 0) (if_then_else:SI (eq:DI (match_dup 1)
1065 [(set_attr "length" "2")])
1067 ;; We can also do (x + (i == 0)) and related, so put them in.
1068 ;; ??? The addx/subx insns use the 32 bit carry flag so there are no DImode
1071 (define_insn_and_split "*x_plus_i_ne_0"
1072 [(set (match_operand:SI 0 "register_operand" "=r")
1073 (plus:SI (ne:SI (match_operand:SI 1 "register_operand" "r")
1075 (match_operand:SI 2 "register_operand" "r")))
1076 (clobber (reg:CC 100))]
1080 [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
1082 (set (match_dup 0) (plus:SI (ltu:SI (reg:CC 100) (const_int 0))
1085 [(set_attr "length" "2")])
1087 (define_insn_and_split "*x_minus_i_ne_0"
1088 [(set (match_operand:SI 0 "register_operand" "=r")
1089 (minus:SI (match_operand:SI 2 "register_operand" "r")
1090 (ne:SI (match_operand:SI 1 "register_operand" "r")
1092 (clobber (reg:CC 100))]
1096 [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
1098 (set (match_dup 0) (minus:SI (match_dup 2)
1099 (ltu:SI (reg:CC 100) (const_int 0))))]
1101 [(set_attr "length" "2")])
1103 (define_insn_and_split "*x_plus_i_eq_0"
1104 [(set (match_operand:SI 0 "register_operand" "=r")
1105 (plus:SI (eq:SI (match_operand:SI 1 "register_operand" "r")
1107 (match_operand:SI 2 "register_operand" "r")))
1108 (clobber (reg:CC 100))]
1112 [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
1114 (set (match_dup 0) (plus:SI (geu:SI (reg:CC 100) (const_int 0))
1117 [(set_attr "length" "2")])
1119 (define_insn_and_split "*x_minus_i_eq_0"
1120 [(set (match_operand:SI 0 "register_operand" "=r")
1121 (minus:SI (match_operand:SI 2 "register_operand" "r")
1122 (eq:SI (match_operand:SI 1 "register_operand" "r")
1124 (clobber (reg:CC 100))]
1128 [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
1130 (set (match_dup 0) (minus:SI (match_dup 2)
1131 (geu:SI (reg:CC 100) (const_int 0))))]
1133 [(set_attr "length" "2")])
1135 ;; We can also do GEU and LTU directly, but these operate after a compare.
1136 ;; ??? The addx/subx insns use the 32 bit carry flag so there are no DImode
1139 (define_insn "*sltu_insn"
1140 [(set (match_operand:SI 0 "register_operand" "=r")
1141 (ltu:SI (reg:CC 100) (const_int 0)))]
1144 [(set_attr "type" "ialuX")])
1146 (define_insn "*neg_sltu_insn"
1147 [(set (match_operand:SI 0 "register_operand" "=r")
1148 (neg:SI (ltu:SI (reg:CC 100) (const_int 0))))]
1151 [(set_attr "type" "ialuX")])
1153 ;; ??? Combine should canonicalize these next two to the same pattern.
1154 (define_insn "*neg_sltu_minus_x"
1155 [(set (match_operand:SI 0 "register_operand" "=r")
1156 (minus:SI (neg:SI (ltu:SI (reg:CC 100) (const_int 0)))
1157 (match_operand:SI 1 "arith_operand" "rI")))]
1159 "subx\t%%g0, %1, %0"
1160 [(set_attr "type" "ialuX")])
1162 (define_insn "*neg_sltu_plus_x"
1163 [(set (match_operand:SI 0 "register_operand" "=r")
1164 (neg:SI (plus:SI (ltu:SI (reg:CC 100) (const_int 0))
1165 (match_operand:SI 1 "arith_operand" "rI"))))]
1167 "subx\t%%g0, %1, %0"
1168 [(set_attr "type" "ialuX")])
1170 (define_insn "*sgeu_insn"
1171 [(set (match_operand:SI 0 "register_operand" "=r")
1172 (geu:SI (reg:CC 100) (const_int 0)))]
1174 "subx\t%%g0, -1, %0"
1175 [(set_attr "type" "ialuX")])
1177 (define_insn "*neg_sgeu_insn"
1178 [(set (match_operand:SI 0 "register_operand" "=r")
1179 (neg:SI (geu:SI (reg:CC 100) (const_int 0))))]
1181 "addx\t%%g0, -1, %0"
1182 [(set_attr "type" "ialuX")])
1184 ;; We can also do (x + ((unsigned) i >= 0)) and related, so put them in.
1185 ;; ??? The addx/subx insns use the 32 bit carry flag so there are no DImode
1188 (define_insn "*sltu_plus_x"
1189 [(set (match_operand:SI 0 "register_operand" "=r")
1190 (plus:SI (ltu:SI (reg:CC 100) (const_int 0))
1191 (match_operand:SI 1 "arith_operand" "rI")))]
1193 "addx\t%%g0, %1, %0"
1194 [(set_attr "type" "ialuX")])
1196 (define_insn "*sltu_plus_x_plus_y"
1197 [(set (match_operand:SI 0 "register_operand" "=r")
1198 (plus:SI (ltu:SI (reg:CC 100) (const_int 0))
1199 (plus:SI (match_operand:SI 1 "arith_operand" "%r")
1200 (match_operand:SI 2 "arith_operand" "rI"))))]
1203 [(set_attr "type" "ialuX")])
1205 (define_insn "*x_minus_sltu"
1206 [(set (match_operand:SI 0 "register_operand" "=r")
1207 (minus:SI (match_operand:SI 1 "register_operand" "r")
1208 (ltu:SI (reg:CC 100) (const_int 0))))]
1211 [(set_attr "type" "ialuX")])
1213 ;; ??? Combine should canonicalize these next two to the same pattern.
1214 (define_insn "*x_minus_y_minus_sltu"
1215 [(set (match_operand:SI 0 "register_operand" "=r")
1216 (minus:SI (minus:SI (match_operand:SI 1 "register_or_zero_operand" "rJ")
1217 (match_operand:SI 2 "arith_operand" "rI"))
1218 (ltu:SI (reg:CC 100) (const_int 0))))]
1221 [(set_attr "type" "ialuX")])
1223 (define_insn "*x_minus_sltu_plus_y"
1224 [(set (match_operand:SI 0 "register_operand" "=r")
1225 (minus:SI (match_operand:SI 1 "register_or_zero_operand" "rJ")
1226 (plus:SI (ltu:SI (reg:CC 100) (const_int 0))
1227 (match_operand:SI 2 "arith_operand" "rI"))))]
1230 [(set_attr "type" "ialuX")])
1232 (define_insn "*sgeu_plus_x"
1233 [(set (match_operand:SI 0 "register_operand" "=r")
1234 (plus:SI (geu:SI (reg:CC 100) (const_int 0))
1235 (match_operand:SI 1 "register_operand" "r")))]
1238 [(set_attr "type" "ialuX")])
1240 (define_insn "*x_minus_sgeu"
1241 [(set (match_operand:SI 0 "register_operand" "=r")
1242 (minus:SI (match_operand:SI 1 "register_operand" "r")
1243 (geu:SI (reg:CC 100) (const_int 0))))]
1246 [(set_attr "type" "ialuX")])
1249 [(set (match_operand:SI 0 "register_operand" "")
1250 (match_operator:SI 2 "noov_compare_operator"
1251 [(match_operand 1 "icc_or_fcc_register_operand" "")
1254 && REGNO (operands[1]) == SPARC_ICC_REG
1255 && (GET_MODE (operands[1]) == CCXmode
1256 /* 32-bit LTU/GEU are better implemented using addx/subx. */
1257 || (GET_CODE (operands[2]) != LTU && GET_CODE (operands[2]) != GEU))"
1258 [(set (match_dup 0) (const_int 0))
1260 (if_then_else:SI (match_op_dup:SI 2 [(match_dup 1) (const_int 0)])
1266 ;; These control RTL generation for conditional jump insns
1268 ;; The quad-word fp compare library routines all return nonzero to indicate
1269 ;; true, which is different from the equivalent libgcc routines, so we must
1270 ;; handle them specially here.
1272 (define_expand "beq"
1274 (if_then_else (eq (match_dup 1) (const_int 0))
1275 (label_ref (match_operand 0 "" ""))
1279 if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx
1280 && GET_CODE (sparc_compare_op0) == REG
1281 && GET_MODE (sparc_compare_op0) == DImode)
1283 emit_v9_brxx_insn (EQ, sparc_compare_op0, operands[0]);
1286 else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
1289 = sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, EQ);
1290 gcc_assert (code == NE);
1291 emit_jump_insn (gen_bne (operands[0]));
1294 operands[1] = gen_compare_reg (EQ);
1297 (define_expand "bne"
1299 (if_then_else (ne (match_dup 1) (const_int 0))
1300 (label_ref (match_operand 0 "" ""))
1304 if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx
1305 && GET_CODE (sparc_compare_op0) == REG
1306 && GET_MODE (sparc_compare_op0) == DImode)
1308 emit_v9_brxx_insn (NE, sparc_compare_op0, operands[0]);
1311 else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
1314 = sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, NE);
1315 gcc_assert (code == NE);
1316 emit_jump_insn (gen_bne (operands[0]));
1319 operands[1] = gen_compare_reg (NE);
1322 (define_expand "bgt"
1324 (if_then_else (gt (match_dup 1) (const_int 0))
1325 (label_ref (match_operand 0 "" ""))
1329 if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx
1330 && GET_CODE (sparc_compare_op0) == REG
1331 && GET_MODE (sparc_compare_op0) == DImode)
1333 emit_v9_brxx_insn (GT, sparc_compare_op0, operands[0]);
1336 else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
1339 = sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, GT);
1340 gcc_assert (code == NE);
1341 emit_jump_insn (gen_bne (operands[0]));
1344 operands[1] = gen_compare_reg (GT);
1347 (define_expand "bgtu"
1349 (if_then_else (gtu (match_dup 1) (const_int 0))
1350 (label_ref (match_operand 0 "" ""))
1354 operands[1] = gen_compare_reg (GTU);
1357 (define_expand "blt"
1359 (if_then_else (lt (match_dup 1) (const_int 0))
1360 (label_ref (match_operand 0 "" ""))
1364 if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx
1365 && GET_CODE (sparc_compare_op0) == REG
1366 && GET_MODE (sparc_compare_op0) == DImode)
1368 emit_v9_brxx_insn (LT, sparc_compare_op0, operands[0]);
1371 else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
1374 = sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, LT);
1375 gcc_assert (code == NE);
1376 emit_jump_insn (gen_bne (operands[0]));
1379 operands[1] = gen_compare_reg (LT);
1382 (define_expand "bltu"
1384 (if_then_else (ltu (match_dup 1) (const_int 0))
1385 (label_ref (match_operand 0 "" ""))
1389 operands[1] = gen_compare_reg (LTU);
1392 (define_expand "bge"
1394 (if_then_else (ge (match_dup 1) (const_int 0))
1395 (label_ref (match_operand 0 "" ""))
1399 if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx
1400 && GET_CODE (sparc_compare_op0) == REG
1401 && GET_MODE (sparc_compare_op0) == DImode)
1403 emit_v9_brxx_insn (GE, sparc_compare_op0, operands[0]);
1406 else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
1409 = sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, GE);
1410 gcc_assert (code == NE);
1411 emit_jump_insn (gen_bne (operands[0]));
1414 operands[1] = gen_compare_reg (GE);
1417 (define_expand "bgeu"
1419 (if_then_else (geu (match_dup 1) (const_int 0))
1420 (label_ref (match_operand 0 "" ""))
1424 operands[1] = gen_compare_reg (GEU);
1427 (define_expand "ble"
1429 (if_then_else (le (match_dup 1) (const_int 0))
1430 (label_ref (match_operand 0 "" ""))
1434 if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx
1435 && GET_CODE (sparc_compare_op0) == REG
1436 && GET_MODE (sparc_compare_op0) == DImode)
1438 emit_v9_brxx_insn (LE, sparc_compare_op0, operands[0]);
1441 else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
1444 = sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, LE);
1445 gcc_assert (code == NE);
1446 emit_jump_insn (gen_bne (operands[0]));
1449 operands[1] = gen_compare_reg (LE);
1452 (define_expand "bleu"
1454 (if_then_else (leu (match_dup 1) (const_int 0))
1455 (label_ref (match_operand 0 "" ""))
1459 operands[1] = gen_compare_reg (LEU);
1462 (define_expand "bunordered"
1464 (if_then_else (unordered (match_dup 1) (const_int 0))
1465 (label_ref (match_operand 0 "" ""))
1469 if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
1472 = sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, UNORDERED);
1473 gcc_assert (code == EQ);
1474 emit_jump_insn (gen_beq (operands[0]));
1477 operands[1] = gen_compare_reg (UNORDERED);
1480 (define_expand "bordered"
1482 (if_then_else (ordered (match_dup 1) (const_int 0))
1483 (label_ref (match_operand 0 "" ""))
1487 if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
1490 = sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, ORDERED);
1491 gcc_assert (code == NE);
1492 emit_jump_insn (gen_bne (operands[0]));
1495 operands[1] = gen_compare_reg (ORDERED);
1498 (define_expand "bungt"
1500 (if_then_else (ungt (match_dup 1) (const_int 0))
1501 (label_ref (match_operand 0 "" ""))
1505 if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
1508 = sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, UNGT);
1509 gcc_assert (code == GT);
1510 emit_jump_insn (gen_bgt (operands[0]));
1513 operands[1] = gen_compare_reg (UNGT);
1516 (define_expand "bunlt"
1518 (if_then_else (unlt (match_dup 1) (const_int 0))
1519 (label_ref (match_operand 0 "" ""))
1523 if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
1526 = sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, UNLT);
1527 gcc_assert (code == NE);
1528 emit_jump_insn (gen_bne (operands[0]));
1531 operands[1] = gen_compare_reg (UNLT);
1534 (define_expand "buneq"
1536 (if_then_else (uneq (match_dup 1) (const_int 0))
1537 (label_ref (match_operand 0 "" ""))
1541 if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
1544 = sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, UNEQ);
1545 gcc_assert (code == EQ);
1546 emit_jump_insn (gen_beq (operands[0]));
1549 operands[1] = gen_compare_reg (UNEQ);
1552 (define_expand "bunge"
1554 (if_then_else (unge (match_dup 1) (const_int 0))
1555 (label_ref (match_operand 0 "" ""))
1559 if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
1562 = sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, UNGE);
1563 gcc_assert (code == NE);
1564 emit_jump_insn (gen_bne (operands[0]));
1567 operands[1] = gen_compare_reg (UNGE);
1570 (define_expand "bunle"
1572 (if_then_else (unle (match_dup 1) (const_int 0))
1573 (label_ref (match_operand 0 "" ""))
1577 if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
1580 = sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, UNLE);
1581 gcc_assert (code == NE);
1582 emit_jump_insn (gen_bne (operands[0]));
1585 operands[1] = gen_compare_reg (UNLE);
1588 (define_expand "bltgt"
1590 (if_then_else (ltgt (match_dup 1) (const_int 0))
1591 (label_ref (match_operand 0 "" ""))
1595 if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
1598 = sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, LTGT);
1599 gcc_assert (code == NE);
1600 emit_jump_insn (gen_bne (operands[0]));
1603 operands[1] = gen_compare_reg (LTGT);
1606 ;; Now match both normal and inverted jump.
1608 ;; XXX fpcmp nop braindamage
1609 (define_insn "*normal_branch"
1611 (if_then_else (match_operator 0 "noov_compare_operator"
1612 [(reg 100) (const_int 0)])
1613 (label_ref (match_operand 1 "" ""))
1617 return output_cbranch (operands[0], operands[1], 1, 0,
1618 final_sequence && INSN_ANNULLED_BRANCH_P (insn),
1621 [(set_attr "type" "branch")
1622 (set_attr "branch_type" "icc")])
1624 ;; XXX fpcmp nop braindamage
1625 (define_insn "*inverted_branch"
1627 (if_then_else (match_operator 0 "noov_compare_operator"
1628 [(reg 100) (const_int 0)])
1630 (label_ref (match_operand 1 "" ""))))]
1633 return output_cbranch (operands[0], operands[1], 1, 1,
1634 final_sequence && INSN_ANNULLED_BRANCH_P (insn),
1637 [(set_attr "type" "branch")
1638 (set_attr "branch_type" "icc")])
1640 ;; XXX fpcmp nop braindamage
1641 (define_insn "*normal_fp_branch"
1643 (if_then_else (match_operator 1 "comparison_operator"
1644 [(match_operand:CCFP 0 "fcc_register_operand" "c")
1646 (label_ref (match_operand 2 "" ""))
1650 return output_cbranch (operands[1], operands[2], 2, 0,
1651 final_sequence && INSN_ANNULLED_BRANCH_P (insn),
1654 [(set_attr "type" "branch")
1655 (set_attr "branch_type" "fcc")])
1657 ;; XXX fpcmp nop braindamage
1658 (define_insn "*inverted_fp_branch"
1660 (if_then_else (match_operator 1 "comparison_operator"
1661 [(match_operand:CCFP 0 "fcc_register_operand" "c")
1664 (label_ref (match_operand 2 "" ""))))]
1667 return output_cbranch (operands[1], operands[2], 2, 1,
1668 final_sequence && INSN_ANNULLED_BRANCH_P (insn),
1671 [(set_attr "type" "branch")
1672 (set_attr "branch_type" "fcc")])
1674 ;; XXX fpcmp nop braindamage
1675 (define_insn "*normal_fpe_branch"
1677 (if_then_else (match_operator 1 "comparison_operator"
1678 [(match_operand:CCFPE 0 "fcc_register_operand" "c")
1680 (label_ref (match_operand 2 "" ""))
1684 return output_cbranch (operands[1], operands[2], 2, 0,
1685 final_sequence && INSN_ANNULLED_BRANCH_P (insn),
1688 [(set_attr "type" "branch")
1689 (set_attr "branch_type" "fcc")])
1691 ;; XXX fpcmp nop braindamage
1692 (define_insn "*inverted_fpe_branch"
1694 (if_then_else (match_operator 1 "comparison_operator"
1695 [(match_operand:CCFPE 0 "fcc_register_operand" "c")
1698 (label_ref (match_operand 2 "" ""))))]
1701 return output_cbranch (operands[1], operands[2], 2, 1,
1702 final_sequence && INSN_ANNULLED_BRANCH_P (insn),
1705 [(set_attr "type" "branch")
1706 (set_attr "branch_type" "fcc")])
1708 ;; SPARC V9-specific jump insns. None of these are guaranteed to be
1709 ;; in the architecture.
1711 ;; There are no 32 bit brreg insns.
1714 (define_insn "*normal_int_branch_sp64"
1716 (if_then_else (match_operator 0 "v9_register_compare_operator"
1717 [(match_operand:DI 1 "register_operand" "r")
1719 (label_ref (match_operand 2 "" ""))
1723 return output_v9branch (operands[0], operands[2], 1, 2, 0,
1724 final_sequence && INSN_ANNULLED_BRANCH_P (insn),
1727 [(set_attr "type" "branch")
1728 (set_attr "branch_type" "reg")])
1731 (define_insn "*inverted_int_branch_sp64"
1733 (if_then_else (match_operator 0 "v9_register_compare_operator"
1734 [(match_operand:DI 1 "register_operand" "r")
1737 (label_ref (match_operand 2 "" ""))))]
1740 return output_v9branch (operands[0], operands[2], 1, 2, 1,
1741 final_sequence && INSN_ANNULLED_BRANCH_P (insn),
1744 [(set_attr "type" "branch")
1745 (set_attr "branch_type" "reg")])
1748 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
1750 ;; Load in operand 0 the (absolute) address of operand 1, which is a symbolic
1751 ;; value subject to a PC-relative relocation. Operand 2 is a helper function
1752 ;; that adds the PC value at the call point to operand 0.
1754 (define_insn "load_pcrel_sym<P:mode>"
1755 [(set (match_operand:P 0 "register_operand" "=r")
1756 (unspec:P [(match_operand:P 1 "symbolic_operand" "")
1757 (match_operand:P 2 "call_address_operand" "")] UNSPEC_LOAD_PCREL_SYM))
1758 (clobber (reg:P 15))]
1761 if (flag_delayed_branch)
1762 return "sethi\t%%hi(%a1-4), %0\n\tcall\t%a2\n\t add\t%0, %%lo(%a1+4), %0";
1764 return "sethi\t%%hi(%a1-8), %0\n\tadd\t%0, %%lo(%a1-4), %0\n\tcall\t%a2\n\t nop";
1766 [(set (attr "type") (const_string "multi"))
1767 (set (attr "length")
1768 (if_then_else (eq_attr "delayed_branch" "true")
1773 ;; Integer move instructions
1775 (define_expand "movqi"
1776 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1777 (match_operand:QI 1 "general_operand" ""))]
1780 if (sparc_expand_move (QImode, operands))
1784 (define_insn "*movqi_insn"
1785 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m")
1786 (match_operand:QI 1 "input_operand" "rI,m,rJ"))]
1787 "(register_operand (operands[0], QImode)
1788 || register_or_zero_operand (operands[1], QImode))"
1793 [(set_attr "type" "*,load,store")
1794 (set_attr "us3load_type" "*,3cycle,*")])
1796 (define_expand "movhi"
1797 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1798 (match_operand:HI 1 "general_operand" ""))]
1801 if (sparc_expand_move (HImode, operands))
1805 (define_insn "*movhi_insn"
1806 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
1807 (match_operand:HI 1 "input_operand" "rI,K,m,rJ"))]
1808 "(register_operand (operands[0], HImode)
1809 || register_or_zero_operand (operands[1], HImode))"
1812 sethi\t%%hi(%a1), %0
1815 [(set_attr "type" "*,*,load,store")
1816 (set_attr "us3load_type" "*,*,3cycle,*")])
1818 ;; We always work with constants here.
1819 (define_insn "*movhi_lo_sum"
1820 [(set (match_operand:HI 0 "register_operand" "=r")
1821 (ior:HI (match_operand:HI 1 "register_operand" "%r")
1822 (match_operand:HI 2 "small_int_operand" "I")))]
1826 (define_expand "movsi"
1827 [(set (match_operand:SI 0 "nonimmediate_operand" "")
1828 (match_operand:SI 1 "general_operand" ""))]
1831 if (sparc_expand_move (SImode, operands))
1835 (define_insn "*movsi_insn"
1836 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,!f,!f,!m,d")
1837 (match_operand:SI 1 "input_operand" "rI,K,m,rJ,f,m,f,J"))]
1838 "(register_operand (operands[0], SImode)
1839 || register_or_zero_operand (operands[1], SImode))"
1842 sethi\t%%hi(%a1), %0
1849 [(set_attr "type" "*,*,load,store,fpmove,fpload,fpstore,fga")])
1851 (define_insn "*movsi_lo_sum"
1852 [(set (match_operand:SI 0 "register_operand" "=r")
1853 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
1854 (match_operand:SI 2 "immediate_operand" "in")))]
1856 "or\t%1, %%lo(%a2), %0")
1858 (define_insn "*movsi_high"
1859 [(set (match_operand:SI 0 "register_operand" "=r")
1860 (high:SI (match_operand:SI 1 "immediate_operand" "in")))]
1862 "sethi\t%%hi(%a1), %0")
1864 ;; The next two patterns must wrap the SYMBOL_REF in an UNSPEC
1865 ;; so that CSE won't optimize the address computation away.
1866 (define_insn "movsi_lo_sum_pic"
1867 [(set (match_operand:SI 0 "register_operand" "=r")
1868 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
1869 (unspec:SI [(match_operand:SI 2 "immediate_operand" "in")] UNSPEC_MOVE_PIC)))]
1871 "or\t%1, %%lo(%a2), %0")
1873 (define_insn "movsi_high_pic"
1874 [(set (match_operand:SI 0 "register_operand" "=r")
1875 (high:SI (unspec:SI [(match_operand 1 "" "")] UNSPEC_MOVE_PIC)))]
1876 "flag_pic && check_pic (1)"
1877 "sethi\t%%hi(%a1), %0")
1879 (define_expand "movsi_pic_label_ref"
1880 [(set (match_dup 3) (high:SI
1881 (unspec:SI [(match_operand:SI 1 "label_ref_operand" "")
1882 (match_dup 2)] UNSPEC_MOVE_PIC_LABEL)))
1883 (set (match_dup 4) (lo_sum:SI (match_dup 3)
1884 (unspec:SI [(match_dup 1) (match_dup 2)] UNSPEC_MOVE_PIC_LABEL)))
1885 (set (match_operand:SI 0 "register_operand" "=r")
1886 (minus:SI (match_dup 5) (match_dup 4)))]
1889 crtl->uses_pic_offset_table = 1;
1890 operands[2] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
1891 if (!can_create_pseudo_p ())
1893 operands[3] = operands[0];
1894 operands[4] = operands[0];
1898 operands[3] = gen_reg_rtx (SImode);
1899 operands[4] = gen_reg_rtx (SImode);
1901 operands[5] = pic_offset_table_rtx;
1904 (define_insn "*movsi_high_pic_label_ref"
1905 [(set (match_operand:SI 0 "register_operand" "=r")
1907 (unspec:SI [(match_operand:SI 1 "label_ref_operand" "")
1908 (match_operand:SI 2 "" "")] UNSPEC_MOVE_PIC_LABEL)))]
1910 "sethi\t%%hi(%a2-(%a1-.)), %0")
1912 (define_insn "*movsi_lo_sum_pic_label_ref"
1913 [(set (match_operand:SI 0 "register_operand" "=r")
1914 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
1915 (unspec:SI [(match_operand:SI 2 "label_ref_operand" "")
1916 (match_operand:SI 3 "" "")] UNSPEC_MOVE_PIC_LABEL)))]
1918 "or\t%1, %%lo(%a3-(%a2-.)), %0")
1920 ;; Set up the PIC register for VxWorks.
1922 (define_expand "vxworks_load_got"
1924 (high:SI (match_dup 1)))
1926 (mem:SI (lo_sum:SI (match_dup 0) (match_dup 1))))
1928 (mem:SI (lo_sum:SI (match_dup 0) (match_dup 2))))]
1929 "TARGET_VXWORKS_RTP"
1931 operands[0] = pic_offset_table_rtx;
1932 operands[1] = gen_rtx_SYMBOL_REF (SImode, VXWORKS_GOTT_BASE);
1933 operands[2] = gen_rtx_SYMBOL_REF (SImode, VXWORKS_GOTT_INDEX);
1936 (define_expand "movdi"
1937 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1938 (match_operand:DI 1 "general_operand" ""))]
1941 if (sparc_expand_move (DImode, operands))
1945 ;; Be careful, fmovd does not exist when !v9.
1946 ;; We match MEM moves directly when we have correct even
1947 ;; numbered registers, but fall into splits otherwise.
1948 ;; The constraint ordering here is really important to
1949 ;; avoid insane problems in reload, especially for patterns
1952 ;; (set (mem:DI (plus:SI (reg:SI 30 %fp)
1953 ;; (const_int -5016)))
1957 (define_insn "*movdi_insn_sp32"
1958 [(set (match_operand:DI 0 "nonimmediate_operand"
1959 "=o,T,U,o,r,r,r,?T,?f,?f,?o,?f")
1960 (match_operand:DI 1 "input_operand"
1961 " J,U,T,r,o,i,r, f, T, o, f, f"))]
1963 && (register_operand (operands[0], DImode)
1964 || register_or_zero_operand (operands[1], DImode))"
1978 [(set_attr "type" "store,store,load,*,*,*,*,fpstore,fpload,*,*,*")
1979 (set_attr "length" "2,*,*,2,2,2,2,*,*,2,2,2")])
1981 (define_insn "*movdi_insn_sp32_v9"
1982 [(set (match_operand:DI 0 "nonimmediate_operand"
1983 "=T,o,T,U,o,r,r,r,?T,?f,?f,?o,?e,?e,?W")
1984 (match_operand:DI 1 "input_operand"
1985 " J,J,U,T,r,o,i,r, f, T, o, f, e, W, e"))]
1988 && (register_operand (operands[0], DImode)
1989 || register_or_zero_operand (operands[1], DImode))"
2006 [(set_attr "type" "store,store,store,load,*,*,*,*,fpstore,fpload,*,*,fpmove,fpload,fpstore")
2007 (set_attr "length" "*,2,*,*,2,2,2,2,*,*,2,2,*,*,*")
2008 (set_attr "fptype" "*,*,*,*,*,*,*,*,*,*,*,*,double,*,*")])
2010 (define_insn "*movdi_insn_sp64"
2011 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,m,?e,?e,?W,b")
2012 (match_operand:DI 1 "input_operand" "rI,N,m,rJ,e,W,e,J"))]
2014 && (register_operand (operands[0], DImode)
2015 || register_or_zero_operand (operands[1], DImode))"
2018 sethi\t%%hi(%a1), %0
2025 [(set_attr "type" "*,*,load,store,fpmove,fpload,fpstore,fga")
2026 (set_attr "fptype" "*,*,*,*,double,*,*,double")])
2028 (define_expand "movdi_pic_label_ref"
2029 [(set (match_dup 3) (high:DI
2030 (unspec:DI [(match_operand:DI 1 "label_ref_operand" "")
2031 (match_dup 2)] UNSPEC_MOVE_PIC_LABEL)))
2032 (set (match_dup 4) (lo_sum:DI (match_dup 3)
2033 (unspec:DI [(match_dup 1) (match_dup 2)] UNSPEC_MOVE_PIC_LABEL)))
2034 (set (match_operand:DI 0 "register_operand" "=r")
2035 (minus:DI (match_dup 5) (match_dup 4)))]
2036 "TARGET_ARCH64 && flag_pic"
2038 crtl->uses_pic_offset_table = 1;
2039 operands[2] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2040 if (!can_create_pseudo_p ())
2042 operands[3] = operands[0];
2043 operands[4] = operands[0];
2047 operands[3] = gen_reg_rtx (DImode);
2048 operands[4] = gen_reg_rtx (DImode);
2050 operands[5] = pic_offset_table_rtx;
2053 (define_insn "*movdi_high_pic_label_ref"
2054 [(set (match_operand:DI 0 "register_operand" "=r")
2056 (unspec:DI [(match_operand:DI 1 "label_ref_operand" "")
2057 (match_operand:DI 2 "" "")] UNSPEC_MOVE_PIC_LABEL)))]
2058 "TARGET_ARCH64 && flag_pic"
2059 "sethi\t%%hi(%a2-(%a1-.)), %0")
2061 (define_insn "*movdi_lo_sum_pic_label_ref"
2062 [(set (match_operand:DI 0 "register_operand" "=r")
2063 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2064 (unspec:DI [(match_operand:DI 2 "label_ref_operand" "")
2065 (match_operand:DI 3 "" "")] UNSPEC_MOVE_PIC_LABEL)))]
2066 "TARGET_ARCH64 && flag_pic"
2067 "or\t%1, %%lo(%a3-(%a2-.)), %0")
2069 ;; SPARC-v9 code model support insns. See sparc_emit_set_symbolic_const64
2070 ;; in sparc.c to see what is going on here... PIC stuff comes first.
2072 (define_insn "movdi_lo_sum_pic"
2073 [(set (match_operand:DI 0 "register_operand" "=r")
2074 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2075 (unspec:DI [(match_operand:DI 2 "immediate_operand" "in")] UNSPEC_MOVE_PIC)))]
2076 "TARGET_ARCH64 && flag_pic"
2077 "or\t%1, %%lo(%a2), %0")
2079 (define_insn "movdi_high_pic"
2080 [(set (match_operand:DI 0 "register_operand" "=r")
2081 (high:DI (unspec:DI [(match_operand 1 "" "")] UNSPEC_MOVE_PIC)))]
2082 "TARGET_ARCH64 && flag_pic && check_pic (1)"
2083 "sethi\t%%hi(%a1), %0")
2085 (define_insn "*sethi_di_medlow_embmedany_pic"
2086 [(set (match_operand:DI 0 "register_operand" "=r")
2087 (high:DI (match_operand:DI 1 "medium_pic_operand" "")))]
2088 "(TARGET_CM_MEDLOW || TARGET_CM_EMBMEDANY) && check_pic (1)"
2089 "sethi\t%%hi(%a1), %0")
2091 (define_insn "*sethi_di_medlow"
2092 [(set (match_operand:DI 0 "register_operand" "=r")
2093 (high:DI (match_operand:DI 1 "symbolic_operand" "")))]
2094 "TARGET_CM_MEDLOW && check_pic (1)"
2095 "sethi\t%%hi(%a1), %0")
2097 (define_insn "*losum_di_medlow"
2098 [(set (match_operand:DI 0 "register_operand" "=r")
2099 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2100 (match_operand:DI 2 "symbolic_operand" "")))]
2102 "or\t%1, %%lo(%a2), %0")
2104 (define_insn "seth44"
2105 [(set (match_operand:DI 0 "register_operand" "=r")
2106 (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] UNSPEC_SETH44)))]
2108 "sethi\t%%h44(%a1), %0")
2110 (define_insn "setm44"
2111 [(set (match_operand:DI 0 "register_operand" "=r")
2112 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2113 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] UNSPEC_SETM44)))]
2115 "or\t%1, %%m44(%a2), %0")
2117 (define_insn "setl44"
2118 [(set (match_operand:DI 0 "register_operand" "=r")
2119 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2120 (match_operand:DI 2 "symbolic_operand" "")))]
2122 "or\t%1, %%l44(%a2), %0")
2124 (define_insn "sethh"
2125 [(set (match_operand:DI 0 "register_operand" "=r")
2126 (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] UNSPEC_SETHH)))]
2128 "sethi\t%%hh(%a1), %0")
2130 (define_insn "setlm"
2131 [(set (match_operand:DI 0 "register_operand" "=r")
2132 (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] UNSPEC_SETLM)))]
2134 "sethi\t%%lm(%a1), %0")
2136 (define_insn "sethm"
2137 [(set (match_operand:DI 0 "register_operand" "=r")
2138 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2139 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] UNSPEC_EMB_SETHM)))]
2141 "or\t%1, %%hm(%a2), %0")
2143 (define_insn "setlo"
2144 [(set (match_operand:DI 0 "register_operand" "=r")
2145 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2146 (match_operand:DI 2 "symbolic_operand" "")))]
2148 "or\t%1, %%lo(%a2), %0")
2150 (define_insn "embmedany_sethi"
2151 [(set (match_operand:DI 0 "register_operand" "=r")
2152 (high:DI (unspec:DI [(match_operand:DI 1 "data_segment_operand" "")] UNSPEC_EMB_HISUM)))]
2153 "TARGET_CM_EMBMEDANY && check_pic (1)"
2154 "sethi\t%%hi(%a1), %0")
2156 (define_insn "embmedany_losum"
2157 [(set (match_operand:DI 0 "register_operand" "=r")
2158 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2159 (match_operand:DI 2 "data_segment_operand" "")))]
2160 "TARGET_CM_EMBMEDANY"
2161 "add\t%1, %%lo(%a2), %0")
2163 (define_insn "embmedany_brsum"
2164 [(set (match_operand:DI 0 "register_operand" "=r")
2165 (unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_EMB_HISUM))]
2166 "TARGET_CM_EMBMEDANY"
2169 (define_insn "embmedany_textuhi"
2170 [(set (match_operand:DI 0 "register_operand" "=r")
2171 (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] UNSPEC_EMB_TEXTUHI)))]
2172 "TARGET_CM_EMBMEDANY && check_pic (1)"
2173 "sethi\t%%uhi(%a1), %0")
2175 (define_insn "embmedany_texthi"
2176 [(set (match_operand:DI 0 "register_operand" "=r")
2177 (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] UNSPEC_EMB_TEXTHI)))]
2178 "TARGET_CM_EMBMEDANY && check_pic (1)"
2179 "sethi\t%%hi(%a1), %0")
2181 (define_insn "embmedany_textulo"
2182 [(set (match_operand:DI 0 "register_operand" "=r")
2183 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2184 (unspec:DI [(match_operand:DI 2 "text_segment_operand" "")] UNSPEC_EMB_TEXTULO)))]
2185 "TARGET_CM_EMBMEDANY"
2186 "or\t%1, %%ulo(%a2), %0")
2188 (define_insn "embmedany_textlo"
2189 [(set (match_operand:DI 0 "register_operand" "=r")
2190 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2191 (match_operand:DI 2 "text_segment_operand" "")))]
2192 "TARGET_CM_EMBMEDANY"
2193 "or\t%1, %%lo(%a2), %0")
2195 ;; Now some patterns to help reload out a bit.
2196 (define_expand "reload_indi"
2197 [(parallel [(match_operand:DI 0 "register_operand" "=r")
2198 (match_operand:DI 1 "immediate_operand" "")
2199 (match_operand:TI 2 "register_operand" "=&r")])]
2201 || TARGET_CM_EMBMEDANY)
2204 sparc_emit_set_symbolic_const64 (operands[0], operands[1], operands[2]);
2208 (define_expand "reload_outdi"
2209 [(parallel [(match_operand:DI 0 "register_operand" "=r")
2210 (match_operand:DI 1 "immediate_operand" "")
2211 (match_operand:TI 2 "register_operand" "=&r")])]
2213 || TARGET_CM_EMBMEDANY)
2216 sparc_emit_set_symbolic_const64 (operands[0], operands[1], operands[2]);
2220 ;; Split up putting CONSTs and REGs into DI regs when !arch64
2222 [(set (match_operand:DI 0 "register_operand" "")
2223 (match_operand:DI 1 "const_int_operand" ""))]
2224 "! TARGET_ARCH64 && reload_completed"
2225 [(clobber (const_int 0))]
2227 #if HOST_BITS_PER_WIDE_INT == 32
2228 emit_insn (gen_movsi (gen_highpart (SImode, operands[0]),
2229 (INTVAL (operands[1]) < 0) ?
2232 emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]),
2235 unsigned int low, high;
2237 low = trunc_int_for_mode (INTVAL (operands[1]), SImode);
2238 high = trunc_int_for_mode (INTVAL (operands[1]) >> 32, SImode);
2239 emit_insn (gen_movsi (gen_highpart (SImode, operands[0]), GEN_INT (high)));
2241 /* Slick... but this trick loses if this subreg constant part
2242 can be done in one insn. */
2244 && ! SPARC_SETHI32_P (high)
2245 && ! SPARC_SIMM13_P (high))
2246 emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]),
2247 gen_highpart (SImode, operands[0])));
2249 emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]), GEN_INT (low)));
2255 [(set (match_operand:DI 0 "register_operand" "")
2256 (match_operand:DI 1 "const_double_operand" ""))]
2260 && ((GET_CODE (operands[0]) == REG
2261 && REGNO (operands[0]) < 32)
2262 || (GET_CODE (operands[0]) == SUBREG
2263 && GET_CODE (SUBREG_REG (operands[0])) == REG
2264 && REGNO (SUBREG_REG (operands[0])) < 32))))"
2265 [(clobber (const_int 0))]
2267 emit_insn (gen_movsi (gen_highpart (SImode, operands[0]),
2268 GEN_INT (CONST_DOUBLE_HIGH (operands[1]))));
2270 /* Slick... but this trick loses if this subreg constant part
2271 can be done in one insn. */
2272 if (CONST_DOUBLE_LOW (operands[1]) == CONST_DOUBLE_HIGH (operands[1])
2273 && ! SPARC_SETHI32_P (CONST_DOUBLE_HIGH (operands[1]))
2274 && ! SPARC_SIMM13_P (CONST_DOUBLE_HIGH (operands[1])))
2276 emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]),
2277 gen_highpart (SImode, operands[0])));
2281 emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]),
2282 GEN_INT (CONST_DOUBLE_LOW (operands[1]))));
2288 [(set (match_operand:DI 0 "register_operand" "")
2289 (match_operand:DI 1 "register_operand" ""))]
2293 && ((GET_CODE (operands[0]) == REG
2294 && REGNO (operands[0]) < 32)
2295 || (GET_CODE (operands[0]) == SUBREG
2296 && GET_CODE (SUBREG_REG (operands[0])) == REG
2297 && REGNO (SUBREG_REG (operands[0])) < 32))))"
2298 [(clobber (const_int 0))]
2300 rtx set_dest = operands[0];
2301 rtx set_src = operands[1];
2305 dest1 = gen_highpart (SImode, set_dest);
2306 dest2 = gen_lowpart (SImode, set_dest);
2307 src1 = gen_highpart (SImode, set_src);
2308 src2 = gen_lowpart (SImode, set_src);
2310 /* Now emit using the real source and destination we found, swapping
2311 the order if we detect overlap. */
2312 if (reg_overlap_mentioned_p (dest1, src2))
2314 emit_insn (gen_movsi (dest2, src2));
2315 emit_insn (gen_movsi (dest1, src1));
2319 emit_insn (gen_movsi (dest1, src1));
2320 emit_insn (gen_movsi (dest2, src2));
2325 ;; Now handle the cases of memory moves from/to non-even
2326 ;; DI mode register pairs.
2328 [(set (match_operand:DI 0 "register_operand" "")
2329 (match_operand:DI 1 "memory_operand" ""))]
2332 && sparc_splitdi_legitimate (operands[0], operands[1]))"
2333 [(clobber (const_int 0))]
2335 rtx word0 = adjust_address (operands[1], SImode, 0);
2336 rtx word1 = adjust_address (operands[1], SImode, 4);
2337 rtx high_part = gen_highpart (SImode, operands[0]);
2338 rtx low_part = gen_lowpart (SImode, operands[0]);
2340 if (reg_overlap_mentioned_p (high_part, word1))
2342 emit_insn (gen_movsi (low_part, word1));
2343 emit_insn (gen_movsi (high_part, word0));
2347 emit_insn (gen_movsi (high_part, word0));
2348 emit_insn (gen_movsi (low_part, word1));
2354 [(set (match_operand:DI 0 "memory_operand" "")
2355 (match_operand:DI 1 "register_operand" ""))]
2358 && sparc_splitdi_legitimate (operands[1], operands[0]))"
2359 [(clobber (const_int 0))]
2361 emit_insn (gen_movsi (adjust_address (operands[0], SImode, 0),
2362 gen_highpart (SImode, operands[1])));
2363 emit_insn (gen_movsi (adjust_address (operands[0], SImode, 4),
2364 gen_lowpart (SImode, operands[1])));
2369 [(set (match_operand:DI 0 "memory_operand" "")
2370 (match_operand:DI 1 "const_zero_operand" ""))]
2374 && ! mem_min_alignment (operands[0], 8)))
2375 && offsettable_memref_p (operands[0])"
2376 [(clobber (const_int 0))]
2378 emit_insn (gen_movsi (adjust_address (operands[0], SImode, 0), const0_rtx));
2379 emit_insn (gen_movsi (adjust_address (operands[0], SImode, 4), const0_rtx));
2384 ;; Floating point and vector move instructions
2386 ;; We don't define V1SI because SI should work just fine.
2387 (define_mode_iterator V32 [SF V2HI V4QI])
2389 ;; Yes, you guessed it right, the former movsf expander.
2390 (define_expand "mov<V32:mode>"
2391 [(set (match_operand:V32 0 "nonimmediate_operand" "")
2392 (match_operand:V32 1 "general_operand" ""))]
2393 "<V32:MODE>mode == SFmode || TARGET_VIS"
2395 if (sparc_expand_move (<V32:MODE>mode, operands))
2399 (define_insn "*movsf_insn"
2400 [(set (match_operand:V32 0 "nonimmediate_operand" "=d,f,*r,*r,*r,f,*r,m,m")
2401 (match_operand:V32 1 "input_operand" "GY,f,*rRY,Q,S,m,m,f,*rGY"))]
2403 && (register_operand (operands[0], <V32:MODE>mode)
2404 || register_or_zero_operand (operands[1], <V32:MODE>mode))"
2406 if (GET_CODE (operands[1]) == CONST_DOUBLE
2407 && (which_alternative == 2
2408 || which_alternative == 3
2409 || which_alternative == 4))
2414 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
2415 REAL_VALUE_TO_TARGET_SINGLE (r, i);
2416 operands[1] = GEN_INT (i);
2419 switch (which_alternative)
2422 return "fzeros\t%0";
2424 return "fmovs\t%1, %0";
2426 return "mov\t%1, %0";
2428 return "sethi\t%%hi(%a1), %0";
2433 return "ld\t%1, %0";
2436 return "st\t%r1, %0";
2441 [(set_attr "type" "fga,fpmove,*,*,*,fpload,load,fpstore,store")])
2443 ;; Exactly the same as above, except that all `f' cases are deleted.
2444 ;; This is necessary to prevent reload from ever trying to use a `f' reg
2447 (define_insn "*movsf_insn_no_fpu"
2448 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,r,r,m")
2449 (match_operand:SF 1 "input_operand" "rR,Q,S,m,rG"))]
2451 && (register_operand (operands[0], SFmode)
2452 || register_or_zero_operand (operands[1], SFmode))"
2454 if (GET_CODE (operands[1]) == CONST_DOUBLE
2455 && (which_alternative == 0
2456 || which_alternative == 1
2457 || which_alternative == 2))
2462 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
2463 REAL_VALUE_TO_TARGET_SINGLE (r, i);
2464 operands[1] = GEN_INT (i);
2467 switch (which_alternative)
2470 return "mov\t%1, %0";
2472 return "sethi\t%%hi(%a1), %0";
2476 return "ld\t%1, %0";
2478 return "st\t%r1, %0";
2483 [(set_attr "type" "*,*,*,load,store")])
2485 ;; The following 3 patterns build SFmode constants in integer registers.
2487 (define_insn "*movsf_lo_sum"
2488 [(set (match_operand:SF 0 "register_operand" "=r")
2489 (lo_sum:SF (match_operand:SF 1 "register_operand" "r")
2490 (match_operand:SF 2 "fp_const_high_losum_operand" "S")))]
2496 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[2]);
2497 REAL_VALUE_TO_TARGET_SINGLE (r, i);
2498 operands[2] = GEN_INT (i);
2499 return "or\t%1, %%lo(%a2), %0";
2502 (define_insn "*movsf_high"
2503 [(set (match_operand:SF 0 "register_operand" "=r")
2504 (high:SF (match_operand:SF 1 "fp_const_high_losum_operand" "S")))]
2510 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
2511 REAL_VALUE_TO_TARGET_SINGLE (r, i);
2512 operands[1] = GEN_INT (i);
2513 return "sethi\t%%hi(%1), %0";
2517 [(set (match_operand:SF 0 "register_operand" "")
2518 (match_operand:SF 1 "fp_const_high_losum_operand" ""))]
2519 "REG_P (operands[0]) && REGNO (operands[0]) < 32"
2520 [(set (match_dup 0) (high:SF (match_dup 1)))
2521 (set (match_dup 0) (lo_sum:SF (match_dup 0) (match_dup 1)))])
2523 (define_mode_iterator V64 [DF V2SI V4HI V8QI])
2525 ;; Yes, you again guessed it right, the former movdf expander.
2526 (define_expand "mov<V64:mode>"
2527 [(set (match_operand:V64 0 "nonimmediate_operand" "")
2528 (match_operand:V64 1 "general_operand" ""))]
2529 "<V64:MODE>mode == DFmode || TARGET_VIS"
2531 if (sparc_expand_move (<V64:MODE>mode, operands))
2535 ;; Be careful, fmovd does not exist when !v9.
2536 (define_insn "*movdf_insn_sp32"
2537 [(set (match_operand:DF 0 "nonimmediate_operand" "=e,W,U,T,o,e,*r,o,e,o")
2538 (match_operand:DF 1 "input_operand" "W#F,e,T,U,G,e,*rFo,*r,o#F,e"))]
2541 && (register_operand (operands[0], DFmode)
2542 || register_or_zero_operand (operands[1], DFmode))"
2554 [(set_attr "type" "fpload,fpstore,load,store,*,*,*,*,*,*")
2555 (set_attr "length" "*,*,*,*,2,2,2,2,2,2")])
2557 (define_insn "*movdf_insn_sp32_no_fpu"
2558 [(set (match_operand:DF 0 "nonimmediate_operand" "=U,T,o,r,o")
2559 (match_operand:DF 1 "input_operand" "T,U,G,ro,r"))]
2562 && (register_operand (operands[0], DFmode)
2563 || register_or_zero_operand (operands[1], DFmode))"
2570 [(set_attr "type" "load,store,*,*,*")
2571 (set_attr "length" "*,*,2,2,2")])
2573 ;; We have available v9 double floats but not 64-bit integer registers.
2574 (define_insn "*movdf_insn_sp32_v9"
2575 [(set (match_operand:V64 0 "nonimmediate_operand" "=b,e,e,T,W,U,T,f,*r,o")
2576 (match_operand:V64 1 "input_operand" "GY,e,W#F,GY,e,T,U,o#F,*roGYDF,*rGYf"))]
2580 && (register_operand (operands[0], <V64:MODE>mode)
2581 || register_or_zero_operand (operands[1], <V64:MODE>mode))"
2593 [(set_attr "type" "fga,fpmove,load,store,store,load,store,*,*,*")
2594 (set_attr "length" "*,*,*,*,*,*,*,2,2,2")
2595 (set_attr "fptype" "double,double,*,*,*,*,*,*,*,*")])
2597 (define_insn "*movdf_insn_sp32_v9_no_fpu"
2598 [(set (match_operand:DF 0 "nonimmediate_operand" "=U,T,T,r,o")
2599 (match_operand:DF 1 "input_operand" "T,U,G,ro,rG"))]
2603 && (register_operand (operands[0], DFmode)
2604 || register_or_zero_operand (operands[1], DFmode))"
2611 [(set_attr "type" "load,store,store,*,*")
2612 (set_attr "length" "*,*,*,2,2")])
2614 ;; We have available both v9 double floats and 64-bit integer registers.
2615 (define_insn "*movdf_insn_sp64"
2616 [(set (match_operand:V64 0 "nonimmediate_operand" "=b,e,e,W,*r,*r,m,*r")
2617 (match_operand:V64 1 "input_operand" "GY,e,W#F,e,*rGY,m,*rGY,DF"))]
2620 && (register_operand (operands[0], <V64:MODE>mode)
2621 || register_or_zero_operand (operands[1], <V64:MODE>mode))"
2631 [(set_attr "type" "fga,fpmove,load,store,*,load,store,*")
2632 (set_attr "length" "*,*,*,*,*,*,*,2")
2633 (set_attr "fptype" "double,double,*,*,*,*,*,*")])
2635 (define_insn "*movdf_insn_sp64_no_fpu"
2636 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
2637 (match_operand:DF 1 "input_operand" "r,m,rG"))]
2640 && (register_operand (operands[0], DFmode)
2641 || register_or_zero_operand (operands[1], DFmode))"
2646 [(set_attr "type" "*,load,store")])
2648 ;; This pattern builds V64mode constants in integer registers.
2650 [(set (match_operand:V64 0 "register_operand" "")
2651 (match_operand:V64 1 "const_double_or_vector_operand" ""))]
2653 && (GET_CODE (operands[0]) == REG
2654 && REGNO (operands[0]) < 32)
2655 && ! const_zero_operand (operands[1], GET_MODE (operands[0]))
2656 && reload_completed"
2657 [(clobber (const_int 0))]
2659 operands[0] = gen_rtx_raw_REG (DImode, REGNO (operands[0]));
2663 #if HOST_BITS_PER_WIDE_INT == 32
2666 enum machine_mode mode = GET_MODE (operands[1]);
2667 rtx tem = simplify_subreg (DImode, operands[1], mode, 0);
2668 emit_insn (gen_movdi (operands[0], tem));
2673 enum machine_mode mode = GET_MODE (operands[1]);
2674 rtx hi = simplify_subreg (SImode, operands[1], mode, 0);
2675 rtx lo = simplify_subreg (SImode, operands[1], mode, 4);
2677 gcc_assert (GET_CODE (hi) == CONST_INT);
2678 gcc_assert (GET_CODE (lo) == CONST_INT);
2680 emit_insn (gen_movsi (gen_highpart (SImode, operands[0]), hi));
2682 /* Slick... but this trick loses if this subreg constant part
2683 can be done in one insn. */
2685 && ! SPARC_SETHI32_P (INTVAL (hi))
2686 && ! SPARC_SIMM13_P (INTVAL (hi)))
2688 emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]),
2689 gen_highpart (SImode, operands[0])));
2693 emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]), lo));
2699 ;; Ok, now the splits to handle all the multi insn and
2700 ;; mis-aligned memory address cases.
2701 ;; In these splits please take note that we must be
2702 ;; careful when V9 but not ARCH64 because the integer
2703 ;; register DFmode cases must be handled.
2705 [(set (match_operand:V64 0 "register_operand" "")
2706 (match_operand:V64 1 "register_operand" ""))]
2709 && ((GET_CODE (operands[0]) == REG
2710 && REGNO (operands[0]) < 32)
2711 || (GET_CODE (operands[0]) == SUBREG
2712 && GET_CODE (SUBREG_REG (operands[0])) == REG
2713 && REGNO (SUBREG_REG (operands[0])) < 32))))
2714 && reload_completed"
2715 [(clobber (const_int 0))]
2717 rtx set_dest = operands[0];
2718 rtx set_src = operands[1];
2721 enum machine_mode half_mode;
2723 /* We can be expanded for DFmode or integral vector modes. */
2724 if (<V64:MODE>mode == DFmode)
2729 dest1 = gen_highpart (half_mode, set_dest);
2730 dest2 = gen_lowpart (half_mode, set_dest);
2731 src1 = gen_highpart (half_mode, set_src);
2732 src2 = gen_lowpart (half_mode, set_src);
2734 /* Now emit using the real source and destination we found, swapping
2735 the order if we detect overlap. */
2736 if (reg_overlap_mentioned_p (dest1, src2))
2738 emit_move_insn_1 (dest2, src2);
2739 emit_move_insn_1 (dest1, src1);
2743 emit_move_insn_1 (dest1, src1);
2744 emit_move_insn_1 (dest2, src2);
2750 [(set (match_operand:V64 0 "register_operand" "")
2751 (match_operand:V64 1 "memory_operand" ""))]
2754 && (((REGNO (operands[0]) % 2) != 0)
2755 || ! mem_min_alignment (operands[1], 8))
2756 && offsettable_memref_p (operands[1])"
2757 [(clobber (const_int 0))]
2759 enum machine_mode half_mode;
2762 /* We can be expanded for DFmode or integral vector modes. */
2763 if (<V64:MODE>mode == DFmode)
2768 word0 = adjust_address (operands[1], half_mode, 0);
2769 word1 = adjust_address (operands[1], half_mode, 4);
2771 if (reg_overlap_mentioned_p (gen_highpart (half_mode, operands[0]), word1))
2773 emit_move_insn_1 (gen_lowpart (half_mode, operands[0]), word1);
2774 emit_move_insn_1 (gen_highpart (half_mode, operands[0]), word0);
2778 emit_move_insn_1 (gen_highpart (half_mode, operands[0]), word0);
2779 emit_move_insn_1 (gen_lowpart (half_mode, operands[0]), word1);
2785 [(set (match_operand:V64 0 "memory_operand" "")
2786 (match_operand:V64 1 "register_operand" ""))]
2789 && (((REGNO (operands[1]) % 2) != 0)
2790 || ! mem_min_alignment (operands[0], 8))
2791 && offsettable_memref_p (operands[0])"
2792 [(clobber (const_int 0))]
2794 enum machine_mode half_mode;
2797 /* We can be expanded for DFmode or integral vector modes. */
2798 if (<V64:MODE>mode == DFmode)
2803 word0 = adjust_address (operands[0], half_mode, 0);
2804 word1 = adjust_address (operands[0], half_mode, 4);
2806 emit_move_insn_1 (word0, gen_highpart (half_mode, operands[1]));
2807 emit_move_insn_1 (word1, gen_lowpart (half_mode, operands[1]));
2812 [(set (match_operand:V64 0 "memory_operand" "")
2813 (match_operand:V64 1 "const_zero_operand" ""))]
2817 && ! mem_min_alignment (operands[0], 8)))
2818 && offsettable_memref_p (operands[0])"
2819 [(clobber (const_int 0))]
2821 enum machine_mode half_mode;
2824 /* We can be expanded for DFmode or integral vector modes. */
2825 if (<V64:MODE>mode == DFmode)
2830 dest1 = adjust_address (operands[0], half_mode, 0);
2831 dest2 = adjust_address (operands[0], half_mode, 4);
2833 emit_move_insn_1 (dest1, CONST0_RTX (half_mode));
2834 emit_move_insn_1 (dest2, CONST0_RTX (half_mode));
2839 [(set (match_operand:V64 0 "register_operand" "")
2840 (match_operand:V64 1 "const_zero_operand" ""))]
2843 && ((GET_CODE (operands[0]) == REG
2844 && REGNO (operands[0]) < 32)
2845 || (GET_CODE (operands[0]) == SUBREG
2846 && GET_CODE (SUBREG_REG (operands[0])) == REG
2847 && REGNO (SUBREG_REG (operands[0])) < 32))"
2848 [(clobber (const_int 0))]
2850 enum machine_mode half_mode;
2851 rtx set_dest = operands[0];
2854 /* We can be expanded for DFmode or integral vector modes. */
2855 if (<V64:MODE>mode == DFmode)
2860 dest1 = gen_highpart (half_mode, set_dest);
2861 dest2 = gen_lowpart (half_mode, set_dest);
2862 emit_move_insn_1 (dest1, CONST0_RTX (half_mode));
2863 emit_move_insn_1 (dest2, CONST0_RTX (half_mode));
2867 (define_expand "movtf"
2868 [(set (match_operand:TF 0 "nonimmediate_operand" "")
2869 (match_operand:TF 1 "general_operand" ""))]
2872 if (sparc_expand_move (TFmode, operands))
2876 (define_insn "*movtf_insn_sp32"
2877 [(set (match_operand:TF 0 "nonimmediate_operand" "=b,e,o,U,r")
2878 (match_operand:TF 1 "input_operand" "G,oe,GeUr,o,roG"))]
2881 && (register_operand (operands[0], TFmode)
2882 || register_or_zero_operand (operands[1], TFmode))"
2884 [(set_attr "length" "4")])
2886 ;; Exactly the same as above, except that all `e' cases are deleted.
2887 ;; This is necessary to prevent reload from ever trying to use a `e' reg
2890 (define_insn "*movtf_insn_sp32_no_fpu"
2891 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,U,o,r,o")
2892 (match_operand:TF 1 "input_operand" "G,o,U,roG,r"))]
2895 && (register_operand (operands[0], TFmode)
2896 || register_or_zero_operand (operands[1], TFmode))"
2898 [(set_attr "length" "4")])
2900 (define_insn "*movtf_insn_sp64"
2901 [(set (match_operand:TF 0 "nonimmediate_operand" "=b,e,o,r")
2902 (match_operand:TF 1 "input_operand" "G,oe,Ger,roG"))]
2905 && ! TARGET_HARD_QUAD
2906 && (register_operand (operands[0], TFmode)
2907 || register_or_zero_operand (operands[1], TFmode))"
2909 [(set_attr "length" "2")])
2911 (define_insn "*movtf_insn_sp64_hq"
2912 [(set (match_operand:TF 0 "nonimmediate_operand" "=b,e,e,m,o,r")
2913 (match_operand:TF 1 "input_operand" "G,e,m,e,rG,roG"))]
2917 && (register_operand (operands[0], TFmode)
2918 || register_or_zero_operand (operands[1], TFmode))"
2926 [(set_attr "type" "*,fpmove,fpload,fpstore,*,*")
2927 (set_attr "length" "2,*,*,*,2,2")])
2929 (define_insn "*movtf_insn_sp64_no_fpu"
2930 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
2931 (match_operand:TF 1 "input_operand" "orG,rG"))]
2934 && (register_operand (operands[0], TFmode)
2935 || register_or_zero_operand (operands[1], TFmode))"
2937 [(set_attr "length" "2")])
2939 ;; Now all the splits to handle multi-insn TF mode moves.
2941 [(set (match_operand:TF 0 "register_operand" "")
2942 (match_operand:TF 1 "register_operand" ""))]
2946 && ! TARGET_HARD_QUAD)
2947 || ! fp_register_operand (operands[0], TFmode))"
2948 [(clobber (const_int 0))]
2950 rtx set_dest = operands[0];
2951 rtx set_src = operands[1];
2955 dest1 = gen_df_reg (set_dest, 0);
2956 dest2 = gen_df_reg (set_dest, 1);
2957 src1 = gen_df_reg (set_src, 0);
2958 src2 = gen_df_reg (set_src, 1);
2960 /* Now emit using the real source and destination we found, swapping
2961 the order if we detect overlap. */
2962 if (reg_overlap_mentioned_p (dest1, src2))
2964 emit_insn (gen_movdf (dest2, src2));
2965 emit_insn (gen_movdf (dest1, src1));
2969 emit_insn (gen_movdf (dest1, src1));
2970 emit_insn (gen_movdf (dest2, src2));
2976 [(set (match_operand:TF 0 "nonimmediate_operand" "")
2977 (match_operand:TF 1 "const_zero_operand" ""))]
2979 [(clobber (const_int 0))]
2981 rtx set_dest = operands[0];
2984 switch (GET_CODE (set_dest))
2987 dest1 = gen_df_reg (set_dest, 0);
2988 dest2 = gen_df_reg (set_dest, 1);
2991 dest1 = adjust_address (set_dest, DFmode, 0);
2992 dest2 = adjust_address (set_dest, DFmode, 8);
2998 emit_insn (gen_movdf (dest1, CONST0_RTX (DFmode)));
2999 emit_insn (gen_movdf (dest2, CONST0_RTX (DFmode)));
3004 [(set (match_operand:TF 0 "register_operand" "")
3005 (match_operand:TF 1 "memory_operand" ""))]
3007 && offsettable_memref_p (operands[1])
3009 || ! TARGET_HARD_QUAD
3010 || ! fp_register_operand (operands[0], TFmode)))"
3011 [(clobber (const_int 0))]
3013 rtx word0 = adjust_address (operands[1], DFmode, 0);
3014 rtx word1 = adjust_address (operands[1], DFmode, 8);
3015 rtx set_dest, dest1, dest2;
3017 set_dest = operands[0];
3019 dest1 = gen_df_reg (set_dest, 0);
3020 dest2 = gen_df_reg (set_dest, 1);
3022 /* Now output, ordering such that we don't clobber any registers
3023 mentioned in the address. */
3024 if (reg_overlap_mentioned_p (dest1, word1))
3027 emit_insn (gen_movdf (dest2, word1));
3028 emit_insn (gen_movdf (dest1, word0));
3032 emit_insn (gen_movdf (dest1, word0));
3033 emit_insn (gen_movdf (dest2, word1));
3039 [(set (match_operand:TF 0 "memory_operand" "")
3040 (match_operand:TF 1 "register_operand" ""))]
3042 && offsettable_memref_p (operands[0])
3044 || ! TARGET_HARD_QUAD
3045 || ! fp_register_operand (operands[1], TFmode)))"
3046 [(clobber (const_int 0))]
3048 rtx set_src = operands[1];
3050 emit_insn (gen_movdf (adjust_address (operands[0], DFmode, 0),
3051 gen_df_reg (set_src, 0)));
3052 emit_insn (gen_movdf (adjust_address (operands[0], DFmode, 8),
3053 gen_df_reg (set_src, 1)));
3058 ;; SPARC-V9 conditional move instructions
3060 ;; We can handle larger constants here for some flavors, but for now we keep
3061 ;; it simple and only allow those constants supported by all flavors.
3062 ;; Note that emit_conditional_move canonicalizes operands 2,3 so that operand
3063 ;; 3 contains the constant if one is present, but we handle either for
3064 ;; generality (sparc.c puts a constant in operand 2).
3066 (define_mode_iterator I [QI HI SI DI])
3068 (define_expand "mov<I:mode>cc"
3069 [(set (match_operand:I 0 "register_operand" "")
3070 (if_then_else:I (match_operand 1 "comparison_operator" "")
3071 (match_operand:I 2 "arith10_operand" "")
3072 (match_operand:I 3 "arith10_operand" "")))]
3073 "TARGET_V9 && !(<I:MODE>mode == DImode && TARGET_ARCH32)"
3075 enum rtx_code code = GET_CODE (operands[1]);
3077 if (GET_MODE (sparc_compare_op0) == DImode
3081 if (sparc_compare_op1 == const0_rtx
3082 && GET_CODE (sparc_compare_op0) == REG
3083 && GET_MODE (sparc_compare_op0) == DImode
3084 && v9_regcmp_p (code))
3085 operands[1] = gen_rtx_fmt_ee (code, DImode, sparc_compare_op0, const0_rtx);
3087 operands[1] = gen_compare_operator (code);
3090 (define_mode_iterator F [SF DF TF])
3092 (define_expand "mov<F:mode>cc"
3093 [(set (match_operand:F 0 "register_operand" "")
3094 (if_then_else:F (match_operand 1 "comparison_operator" "")
3095 (match_operand:F 2 "register_operand" "")
3096 (match_operand:F 3 "register_operand" "")))]
3097 "TARGET_V9 && TARGET_FPU"
3099 enum rtx_code code = GET_CODE (operands[1]);
3101 if (GET_MODE (sparc_compare_op0) == DImode
3105 if (sparc_compare_op1 == const0_rtx
3106 && GET_CODE (sparc_compare_op0) == REG
3107 && GET_MODE (sparc_compare_op0) == DImode
3108 && v9_regcmp_p (code))
3109 operands[1] = gen_rtx_fmt_ee (code, DImode, sparc_compare_op0, const0_rtx);
3111 operands[1] = gen_compare_operator (code);
3114 ;; Conditional move define_insns
3116 (define_insn "*mov<I:mode>_cc_v9"
3117 [(set (match_operand:I 0 "register_operand" "=r,r")
3118 (if_then_else:I (match_operator 1 "comparison_operator"
3119 [(match_operand 2 "icc_or_fcc_register_operand" "X,X")
3121 (match_operand:I 3 "arith11_operand" "rL,0")
3122 (match_operand:I 4 "arith11_operand" "0,rL")))]
3123 "TARGET_V9 && !(<I:MODE>mode == DImode && TARGET_ARCH32)"
3126 mov%c1\t%x2, %4, %0"
3127 [(set_attr "type" "cmove")])
3129 (define_insn "*mov<I:mode>_cc_reg_sp64"
3130 [(set (match_operand:I 0 "register_operand" "=r,r")
3131 (if_then_else:I (match_operator 1 "v9_register_compare_operator"
3132 [(match_operand:DI 2 "register_operand" "r,r")
3134 (match_operand:I 3 "arith10_operand" "rM,0")
3135 (match_operand:I 4 "arith10_operand" "0,rM")))]
3138 movr%D1\t%2, %r3, %0
3139 movr%d1\t%2, %r4, %0"
3140 [(set_attr "type" "cmove")])
3142 (define_insn "*movsf_cc_v9"
3143 [(set (match_operand:SF 0 "register_operand" "=f,f")
3144 (if_then_else:SF (match_operator 1 "comparison_operator"
3145 [(match_operand 2 "icc_or_fcc_register_operand" "X,X")
3147 (match_operand:SF 3 "register_operand" "f,0")
3148 (match_operand:SF 4 "register_operand" "0,f")))]
3149 "TARGET_V9 && TARGET_FPU"
3151 fmovs%C1\t%x2, %3, %0
3152 fmovs%c1\t%x2, %4, %0"
3153 [(set_attr "type" "fpcmove")])
3155 (define_insn "*movsf_cc_reg_sp64"
3156 [(set (match_operand:SF 0 "register_operand" "=f,f")
3157 (if_then_else:SF (match_operator 1 "v9_register_compare_operator"
3158 [(match_operand:DI 2 "register_operand" "r,r")
3160 (match_operand:SF 3 "register_operand" "f,0")
3161 (match_operand:SF 4 "register_operand" "0,f")))]
3162 "TARGET_ARCH64 && TARGET_FPU"
3164 fmovrs%D1\t%2, %3, %0
3165 fmovrs%d1\t%2, %4, %0"
3166 [(set_attr "type" "fpcrmove")])
3168 ;; Named because invoked by movtf_cc_v9
3169 (define_insn "movdf_cc_v9"
3170 [(set (match_operand:DF 0 "register_operand" "=e,e")
3171 (if_then_else:DF (match_operator 1 "comparison_operator"
3172 [(match_operand 2 "icc_or_fcc_register_operand" "X,X")
3174 (match_operand:DF 3 "register_operand" "e,0")
3175 (match_operand:DF 4 "register_operand" "0,e")))]
3176 "TARGET_V9 && TARGET_FPU"
3178 fmovd%C1\t%x2, %3, %0
3179 fmovd%c1\t%x2, %4, %0"
3180 [(set_attr "type" "fpcmove")
3181 (set_attr "fptype" "double")])
3183 ;; Named because invoked by movtf_cc_reg_sp64
3184 (define_insn "movdf_cc_reg_sp64"
3185 [(set (match_operand:DF 0 "register_operand" "=e,e")
3186 (if_then_else:DF (match_operator 1 "v9_register_compare_operator"
3187 [(match_operand:DI 2 "register_operand" "r,r")
3189 (match_operand:DF 3 "register_operand" "e,0")
3190 (match_operand:DF 4 "register_operand" "0,e")))]
3191 "TARGET_ARCH64 && TARGET_FPU"
3193 fmovrd%D1\t%2, %3, %0
3194 fmovrd%d1\t%2, %4, %0"
3195 [(set_attr "type" "fpcrmove")
3196 (set_attr "fptype" "double")])
3198 (define_insn "*movtf_cc_hq_v9"
3199 [(set (match_operand:TF 0 "register_operand" "=e,e")
3200 (if_then_else:TF (match_operator 1 "comparison_operator"
3201 [(match_operand 2 "icc_or_fcc_register_operand" "X,X")
3203 (match_operand:TF 3 "register_operand" "e,0")
3204 (match_operand:TF 4 "register_operand" "0,e")))]
3205 "TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD"
3207 fmovq%C1\t%x2, %3, %0
3208 fmovq%c1\t%x2, %4, %0"
3209 [(set_attr "type" "fpcmove")])
3211 (define_insn "*movtf_cc_reg_hq_sp64"
3212 [(set (match_operand:TF 0 "register_operand" "=e,e")
3213 (if_then_else:TF (match_operator 1 "v9_register_compare_operator"
3214 [(match_operand:DI 2 "register_operand" "r,r")
3216 (match_operand:TF 3 "register_operand" "e,0")
3217 (match_operand:TF 4 "register_operand" "0,e")))]
3218 "TARGET_ARCH64 && TARGET_FPU && TARGET_HARD_QUAD"
3220 fmovrq%D1\t%2, %3, %0
3221 fmovrq%d1\t%2, %4, %0"
3222 [(set_attr "type" "fpcrmove")])
3224 (define_insn_and_split "*movtf_cc_v9"
3225 [(set (match_operand:TF 0 "register_operand" "=e,e")
3226 (if_then_else:TF (match_operator 1 "comparison_operator"
3227 [(match_operand 2 "icc_or_fcc_register_operand" "X,X")
3229 (match_operand:TF 3 "register_operand" "e,0")
3230 (match_operand:TF 4 "register_operand" "0,e")))]
3231 "TARGET_V9 && TARGET_FPU && !TARGET_HARD_QUAD"
3233 "&& reload_completed"
3234 [(clobber (const_int 0))]
3236 rtx set_dest = operands[0];
3237 rtx set_srca = operands[3];
3238 rtx set_srcb = operands[4];
3239 int third = rtx_equal_p (set_dest, set_srca);
3241 rtx srca1, srca2, srcb1, srcb2;
3243 dest1 = gen_df_reg (set_dest, 0);
3244 dest2 = gen_df_reg (set_dest, 1);
3245 srca1 = gen_df_reg (set_srca, 0);
3246 srca2 = gen_df_reg (set_srca, 1);
3247 srcb1 = gen_df_reg (set_srcb, 0);
3248 srcb2 = gen_df_reg (set_srcb, 1);
3250 /* Now emit using the real source and destination we found, swapping
3251 the order if we detect overlap. */
3252 if ((third && reg_overlap_mentioned_p (dest1, srcb2))
3253 || (!third && reg_overlap_mentioned_p (dest1, srca2)))
3255 emit_insn (gen_movdf_cc_v9 (dest2, operands[1], operands[2], srca2, srcb2));
3256 emit_insn (gen_movdf_cc_v9 (dest1, operands[1], operands[2], srca1, srcb1));
3260 emit_insn (gen_movdf_cc_v9 (dest1, operands[1], operands[2], srca1, srcb1));
3261 emit_insn (gen_movdf_cc_v9 (dest2, operands[1], operands[2], srca2, srcb2));
3265 [(set_attr "length" "2")])
3267 (define_insn_and_split "*movtf_cc_reg_sp64"
3268 [(set (match_operand:TF 0 "register_operand" "=e,e")
3269 (if_then_else:TF (match_operator 1 "v9_register_compare_operator"
3270 [(match_operand:DI 2 "register_operand" "r,r")
3272 (match_operand:TF 3 "register_operand" "e,0")
3273 (match_operand:TF 4 "register_operand" "0,e")))]
3274 "TARGET_ARCH64 && TARGET_FPU && ! TARGET_HARD_QUAD"
3276 "&& reload_completed"
3277 [(clobber (const_int 0))]
3279 rtx set_dest = operands[0];
3280 rtx set_srca = operands[3];
3281 rtx set_srcb = operands[4];
3282 int third = rtx_equal_p (set_dest, set_srca);
3284 rtx srca1, srca2, srcb1, srcb2;
3286 dest1 = gen_df_reg (set_dest, 0);
3287 dest2 = gen_df_reg (set_dest, 1);
3288 srca1 = gen_df_reg (set_srca, 0);
3289 srca2 = gen_df_reg (set_srca, 1);
3290 srcb1 = gen_df_reg (set_srcb, 0);
3291 srcb2 = gen_df_reg (set_srcb, 1);
3293 /* Now emit using the real source and destination we found, swapping
3294 the order if we detect overlap. */
3295 if ((third && reg_overlap_mentioned_p (dest1, srcb2))
3296 || (!third && reg_overlap_mentioned_p (dest1, srca2)))
3298 emit_insn (gen_movdf_cc_reg_sp64 (dest2, operands[1], operands[2], srca2, srcb2));
3299 emit_insn (gen_movdf_cc_reg_sp64 (dest1, operands[1], operands[2], srca1, srcb1));
3303 emit_insn (gen_movdf_cc_reg_sp64 (dest1, operands[1], operands[2], srca1, srcb1));
3304 emit_insn (gen_movdf_cc_reg_sp64 (dest2, operands[1], operands[2], srca2, srcb2));
3308 [(set_attr "length" "2")])
3311 ;; Zero-extension instructions
3313 ;; These patterns originally accepted general_operands, however, slightly
3314 ;; better code is generated by only accepting register_operands, and then
3315 ;; letting combine generate the ldu[hb] insns.
3317 (define_expand "zero_extendhisi2"
3318 [(set (match_operand:SI 0 "register_operand" "")
3319 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
3322 rtx temp = gen_reg_rtx (SImode);
3323 rtx shift_16 = GEN_INT (16);
3324 int op1_subbyte = 0;
3326 if (GET_CODE (operand1) == SUBREG)
3328 op1_subbyte = SUBREG_BYTE (operand1);
3329 op1_subbyte /= GET_MODE_SIZE (SImode);
3330 op1_subbyte *= GET_MODE_SIZE (SImode);
3331 operand1 = XEXP (operand1, 0);
3334 emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1, op1_subbyte),
3336 emit_insn (gen_lshrsi3 (operand0, temp, shift_16));
3340 (define_insn "*zero_extendhisi2_insn"
3341 [(set (match_operand:SI 0 "register_operand" "=r")
3342 (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
3345 [(set_attr "type" "load")
3346 (set_attr "us3load_type" "3cycle")])
3348 (define_expand "zero_extendqihi2"
3349 [(set (match_operand:HI 0 "register_operand" "")
3350 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
3354 (define_insn "*zero_extendqihi2_insn"
3355 [(set (match_operand:HI 0 "register_operand" "=r,r")
3356 (zero_extend:HI (match_operand:QI 1 "input_operand" "r,m")))]
3357 "GET_CODE (operands[1]) != CONST_INT"
3361 [(set_attr "type" "*,load")
3362 (set_attr "us3load_type" "*,3cycle")])
3364 (define_expand "zero_extendqisi2"
3365 [(set (match_operand:SI 0 "register_operand" "")
3366 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
3370 (define_insn "*zero_extendqisi2_insn"
3371 [(set (match_operand:SI 0 "register_operand" "=r,r")
3372 (zero_extend:SI (match_operand:QI 1 "input_operand" "r,m")))]
3373 "GET_CODE (operands[1]) != CONST_INT"
3377 [(set_attr "type" "*,load")
3378 (set_attr "us3load_type" "*,3cycle")])
3380 (define_expand "zero_extendqidi2"
3381 [(set (match_operand:DI 0 "register_operand" "")
3382 (zero_extend:DI (match_operand:QI 1 "register_operand" "")))]
3386 (define_insn "*zero_extendqidi2_insn"
3387 [(set (match_operand:DI 0 "register_operand" "=r,r")
3388 (zero_extend:DI (match_operand:QI 1 "input_operand" "r,m")))]
3389 "TARGET_ARCH64 && GET_CODE (operands[1]) != CONST_INT"
3393 [(set_attr "type" "*,load")
3394 (set_attr "us3load_type" "*,3cycle")])
3396 (define_expand "zero_extendhidi2"
3397 [(set (match_operand:DI 0 "register_operand" "")
3398 (zero_extend:DI (match_operand:HI 1 "register_operand" "")))]
3401 rtx temp = gen_reg_rtx (DImode);
3402 rtx shift_48 = GEN_INT (48);
3403 int op1_subbyte = 0;
3405 if (GET_CODE (operand1) == SUBREG)
3407 op1_subbyte = SUBREG_BYTE (operand1);
3408 op1_subbyte /= GET_MODE_SIZE (DImode);
3409 op1_subbyte *= GET_MODE_SIZE (DImode);
3410 operand1 = XEXP (operand1, 0);
3413 emit_insn (gen_ashldi3 (temp, gen_rtx_SUBREG (DImode, operand1, op1_subbyte),
3415 emit_insn (gen_lshrdi3 (operand0, temp, shift_48));
3419 (define_insn "*zero_extendhidi2_insn"
3420 [(set (match_operand:DI 0 "register_operand" "=r")
3421 (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
3424 [(set_attr "type" "load")
3425 (set_attr "us3load_type" "3cycle")])
3427 ;; ??? Write truncdisi pattern using sra?
3429 (define_expand "zero_extendsidi2"
3430 [(set (match_operand:DI 0 "register_operand" "")
3431 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))]
3435 (define_insn "*zero_extendsidi2_insn_sp64"
3436 [(set (match_operand:DI 0 "register_operand" "=r,r")
3437 (zero_extend:DI (match_operand:SI 1 "input_operand" "r,m")))]
3438 "TARGET_ARCH64 && GET_CODE (operands[1]) != CONST_INT"
3442 [(set_attr "type" "shift,load")])
3444 (define_insn_and_split "*zero_extendsidi2_insn_sp32"
3445 [(set (match_operand:DI 0 "register_operand" "=r")
3446 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
3449 "&& reload_completed"
3450 [(set (match_dup 2) (match_dup 3))
3451 (set (match_dup 4) (match_dup 5))]
3455 dest1 = gen_highpart (SImode, operands[0]);
3456 dest2 = gen_lowpart (SImode, operands[0]);
3458 /* Swap the order in case of overlap. */
3459 if (REGNO (dest1) == REGNO (operands[1]))
3461 operands[2] = dest2;
3462 operands[3] = operands[1];
3463 operands[4] = dest1;
3464 operands[5] = const0_rtx;
3468 operands[2] = dest1;
3469 operands[3] = const0_rtx;
3470 operands[4] = dest2;
3471 operands[5] = operands[1];
3474 [(set_attr "length" "2")])
3476 ;; Simplify comparisons of extended values.
3478 (define_insn "*cmp_zero_extendqisi2"
3480 (compare:CC (zero_extend:SI (match_operand:QI 0 "register_operand" "r"))
3483 "andcc\t%0, 0xff, %%g0"
3484 [(set_attr "type" "compare")])
3486 (define_insn "*cmp_zero_qi"
3488 (compare:CC (match_operand:QI 0 "register_operand" "r")
3491 "andcc\t%0, 0xff, %%g0"
3492 [(set_attr "type" "compare")])
3494 (define_insn "*cmp_zero_extendqisi2_set"
3496 (compare:CC (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
3498 (set (match_operand:SI 0 "register_operand" "=r")
3499 (zero_extend:SI (match_dup 1)))]
3501 "andcc\t%1, 0xff, %0"
3502 [(set_attr "type" "compare")])
3504 (define_insn "*cmp_zero_extendqisi2_andcc_set"
3506 (compare:CC (and:SI (match_operand:SI 1 "register_operand" "r")
3509 (set (match_operand:SI 0 "register_operand" "=r")
3510 (zero_extend:SI (subreg:QI (match_dup 1) 0)))]
3512 "andcc\t%1, 0xff, %0"
3513 [(set_attr "type" "compare")])
3515 (define_insn "*cmp_zero_extendqidi2"
3517 (compare:CCX (zero_extend:DI (match_operand:QI 0 "register_operand" "r"))
3520 "andcc\t%0, 0xff, %%g0"
3521 [(set_attr "type" "compare")])
3523 (define_insn "*cmp_zero_qi_sp64"
3525 (compare:CCX (match_operand:QI 0 "register_operand" "r")
3528 "andcc\t%0, 0xff, %%g0"
3529 [(set_attr "type" "compare")])
3531 (define_insn "*cmp_zero_extendqidi2_set"
3533 (compare:CCX (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
3535 (set (match_operand:DI 0 "register_operand" "=r")
3536 (zero_extend:DI (match_dup 1)))]
3538 "andcc\t%1, 0xff, %0"
3539 [(set_attr "type" "compare")])
3541 (define_insn "*cmp_zero_extendqidi2_andcc_set"
3543 (compare:CCX (and:DI (match_operand:DI 1 "register_operand" "r")
3546 (set (match_operand:DI 0 "register_operand" "=r")
3547 (zero_extend:DI (subreg:QI (match_dup 1) 0)))]
3549 "andcc\t%1, 0xff, %0"
3550 [(set_attr "type" "compare")])
3552 ;; Similarly, handle {SI,DI}->QI mode truncation followed by a compare.
3554 (define_insn "*cmp_siqi_trunc"
3556 (compare:CC (subreg:QI (match_operand:SI 0 "register_operand" "r") 3)
3559 "andcc\t%0, 0xff, %%g0"
3560 [(set_attr "type" "compare")])
3562 (define_insn "*cmp_siqi_trunc_set"
3564 (compare:CC (subreg:QI (match_operand:SI 1 "register_operand" "r") 3)
3566 (set (match_operand:QI 0 "register_operand" "=r")
3567 (subreg:QI (match_dup 1) 3))]
3569 "andcc\t%1, 0xff, %0"
3570 [(set_attr "type" "compare")])
3572 (define_insn "*cmp_diqi_trunc"
3574 (compare:CC (subreg:QI (match_operand:DI 0 "register_operand" "r") 7)
3577 "andcc\t%0, 0xff, %%g0"
3578 [(set_attr "type" "compare")])
3580 (define_insn "*cmp_diqi_trunc_set"
3582 (compare:CC (subreg:QI (match_operand:DI 1 "register_operand" "r") 7)
3584 (set (match_operand:QI 0 "register_operand" "=r")
3585 (subreg:QI (match_dup 1) 7))]
3587 "andcc\t%1, 0xff, %0"
3588 [(set_attr "type" "compare")])
3591 ;; Sign-extension instructions
3593 ;; These patterns originally accepted general_operands, however, slightly
3594 ;; better code is generated by only accepting register_operands, and then
3595 ;; letting combine generate the lds[hb] insns.
3597 (define_expand "extendhisi2"
3598 [(set (match_operand:SI 0 "register_operand" "")
3599 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
3602 rtx temp = gen_reg_rtx (SImode);
3603 rtx shift_16 = GEN_INT (16);
3604 int op1_subbyte = 0;
3606 if (GET_CODE (operand1) == SUBREG)
3608 op1_subbyte = SUBREG_BYTE (operand1);
3609 op1_subbyte /= GET_MODE_SIZE (SImode);
3610 op1_subbyte *= GET_MODE_SIZE (SImode);
3611 operand1 = XEXP (operand1, 0);
3614 emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1, op1_subbyte),
3616 emit_insn (gen_ashrsi3 (operand0, temp, shift_16));
3620 (define_insn "*sign_extendhisi2_insn"
3621 [(set (match_operand:SI 0 "register_operand" "=r")
3622 (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
3625 [(set_attr "type" "sload")
3626 (set_attr "us3load_type" "3cycle")])
3628 (define_expand "extendqihi2"
3629 [(set (match_operand:HI 0 "register_operand" "")
3630 (sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
3633 rtx temp = gen_reg_rtx (SImode);
3634 rtx shift_24 = GEN_INT (24);
3635 int op1_subbyte = 0;
3636 int op0_subbyte = 0;
3638 if (GET_CODE (operand1) == SUBREG)
3640 op1_subbyte = SUBREG_BYTE (operand1);
3641 op1_subbyte /= GET_MODE_SIZE (SImode);
3642 op1_subbyte *= GET_MODE_SIZE (SImode);
3643 operand1 = XEXP (operand1, 0);
3645 if (GET_CODE (operand0) == SUBREG)
3647 op0_subbyte = SUBREG_BYTE (operand0);
3648 op0_subbyte /= GET_MODE_SIZE (SImode);
3649 op0_subbyte *= GET_MODE_SIZE (SImode);
3650 operand0 = XEXP (operand0, 0);
3652 emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1, op1_subbyte),
3654 if (GET_MODE (operand0) != SImode)
3655 operand0 = gen_rtx_SUBREG (SImode, operand0, op0_subbyte);
3656 emit_insn (gen_ashrsi3 (operand0, temp, shift_24));
3660 (define_insn "*sign_extendqihi2_insn"
3661 [(set (match_operand:HI 0 "register_operand" "=r")
3662 (sign_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
3665 [(set_attr "type" "sload")
3666 (set_attr "us3load_type" "3cycle")])
3668 (define_expand "extendqisi2"
3669 [(set (match_operand:SI 0 "register_operand" "")
3670 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
3673 rtx temp = gen_reg_rtx (SImode);
3674 rtx shift_24 = GEN_INT (24);
3675 int op1_subbyte = 0;
3677 if (GET_CODE (operand1) == SUBREG)
3679 op1_subbyte = SUBREG_BYTE (operand1);
3680 op1_subbyte /= GET_MODE_SIZE (SImode);
3681 op1_subbyte *= GET_MODE_SIZE (SImode);
3682 operand1 = XEXP (operand1, 0);
3685 emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1, op1_subbyte),
3687 emit_insn (gen_ashrsi3 (operand0, temp, shift_24));
3691 (define_insn "*sign_extendqisi2_insn"
3692 [(set (match_operand:SI 0 "register_operand" "=r")
3693 (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
3696 [(set_attr "type" "sload")
3697 (set_attr "us3load_type" "3cycle")])
3699 (define_expand "extendqidi2"
3700 [(set (match_operand:DI 0 "register_operand" "")
3701 (sign_extend:DI (match_operand:QI 1 "register_operand" "")))]
3704 rtx temp = gen_reg_rtx (DImode);
3705 rtx shift_56 = GEN_INT (56);
3706 int op1_subbyte = 0;
3708 if (GET_CODE (operand1) == SUBREG)
3710 op1_subbyte = SUBREG_BYTE (operand1);
3711 op1_subbyte /= GET_MODE_SIZE (DImode);
3712 op1_subbyte *= GET_MODE_SIZE (DImode);
3713 operand1 = XEXP (operand1, 0);
3716 emit_insn (gen_ashldi3 (temp, gen_rtx_SUBREG (DImode, operand1, op1_subbyte),
3718 emit_insn (gen_ashrdi3 (operand0, temp, shift_56));
3722 (define_insn "*sign_extendqidi2_insn"
3723 [(set (match_operand:DI 0 "register_operand" "=r")
3724 (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
3727 [(set_attr "type" "sload")
3728 (set_attr "us3load_type" "3cycle")])
3730 (define_expand "extendhidi2"
3731 [(set (match_operand:DI 0 "register_operand" "")
3732 (sign_extend:DI (match_operand:HI 1 "register_operand" "")))]
3735 rtx temp = gen_reg_rtx (DImode);
3736 rtx shift_48 = GEN_INT (48);
3737 int op1_subbyte = 0;
3739 if (GET_CODE (operand1) == SUBREG)
3741 op1_subbyte = SUBREG_BYTE (operand1);
3742 op1_subbyte /= GET_MODE_SIZE (DImode);
3743 op1_subbyte *= GET_MODE_SIZE (DImode);
3744 operand1 = XEXP (operand1, 0);
3747 emit_insn (gen_ashldi3 (temp, gen_rtx_SUBREG (DImode, operand1, op1_subbyte),
3749 emit_insn (gen_ashrdi3 (operand0, temp, shift_48));
3753 (define_insn "*sign_extendhidi2_insn"
3754 [(set (match_operand:DI 0 "register_operand" "=r")
3755 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
3758 [(set_attr "type" "sload")
3759 (set_attr "us3load_type" "3cycle")])
3761 (define_expand "extendsidi2"
3762 [(set (match_operand:DI 0 "register_operand" "")
3763 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))]
3767 (define_insn "*sign_extendsidi2_insn"
3768 [(set (match_operand:DI 0 "register_operand" "=r,r")
3769 (sign_extend:DI (match_operand:SI 1 "input_operand" "r,m")))]
3774 [(set_attr "type" "shift,sload")
3775 (set_attr "us3load_type" "*,3cycle")])
3778 ;; Special pattern for optimizing bit-field compares. This is needed
3779 ;; because combine uses this as a canonical form.
3781 (define_insn "*cmp_zero_extract"
3784 (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
3785 (match_operand:SI 1 "small_int_operand" "I")
3786 (match_operand:SI 2 "small_int_operand" "I"))
3788 "INTVAL (operands[2]) > 19"
3790 int len = INTVAL (operands[1]);
3791 int pos = 32 - INTVAL (operands[2]) - len;
3792 HOST_WIDE_INT mask = ((1 << len) - 1) << pos;
3793 operands[1] = GEN_INT (mask);
3794 return "andcc\t%0, %1, %%g0";
3796 [(set_attr "type" "compare")])
3798 (define_insn "*cmp_zero_extract_sp64"
3801 (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
3802 (match_operand:SI 1 "small_int_operand" "I")
3803 (match_operand:SI 2 "small_int_operand" "I"))
3805 "TARGET_ARCH64 && INTVAL (operands[2]) > 51"
3807 int len = INTVAL (operands[1]);
3808 int pos = 64 - INTVAL (operands[2]) - len;
3809 HOST_WIDE_INT mask = (((unsigned HOST_WIDE_INT) 1 << len) - 1) << pos;
3810 operands[1] = GEN_INT (mask);
3811 return "andcc\t%0, %1, %%g0";
3813 [(set_attr "type" "compare")])
3816 ;; Conversions between float, double and long double.
3818 (define_insn "extendsfdf2"
3819 [(set (match_operand:DF 0 "register_operand" "=e")
3821 (match_operand:SF 1 "register_operand" "f")))]
3824 [(set_attr "type" "fp")
3825 (set_attr "fptype" "double")])
3827 (define_expand "extendsftf2"
3828 [(set (match_operand:TF 0 "nonimmediate_operand" "")
3830 (match_operand:SF 1 "register_operand" "")))]
3831 "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
3832 "emit_tfmode_cvt (FLOAT_EXTEND, operands); DONE;")
3834 (define_insn "*extendsftf2_hq"
3835 [(set (match_operand:TF 0 "register_operand" "=e")
3837 (match_operand:SF 1 "register_operand" "f")))]
3838 "TARGET_FPU && TARGET_HARD_QUAD"
3840 [(set_attr "type" "fp")])
3842 (define_expand "extenddftf2"
3843 [(set (match_operand:TF 0 "nonimmediate_operand" "")
3845 (match_operand:DF 1 "register_operand" "")))]
3846 "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
3847 "emit_tfmode_cvt (FLOAT_EXTEND, operands); DONE;")
3849 (define_insn "*extenddftf2_hq"
3850 [(set (match_operand:TF 0 "register_operand" "=e")
3852 (match_operand:DF 1 "register_operand" "e")))]
3853 "TARGET_FPU && TARGET_HARD_QUAD"
3855 [(set_attr "type" "fp")])
3857 (define_insn "truncdfsf2"
3858 [(set (match_operand:SF 0 "register_operand" "=f")
3860 (match_operand:DF 1 "register_operand" "e")))]
3863 [(set_attr "type" "fp")
3864 (set_attr "fptype" "double")])
3866 (define_expand "trunctfsf2"
3867 [(set (match_operand:SF 0 "register_operand" "")
3869 (match_operand:TF 1 "general_operand" "")))]
3870 "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
3871 "emit_tfmode_cvt (FLOAT_TRUNCATE, operands); DONE;")
3873 (define_insn "*trunctfsf2_hq"
3874 [(set (match_operand:SF 0 "register_operand" "=f")
3876 (match_operand:TF 1 "register_operand" "e")))]
3877 "TARGET_FPU && TARGET_HARD_QUAD"
3879 [(set_attr "type" "fp")])
3881 (define_expand "trunctfdf2"
3882 [(set (match_operand:DF 0 "register_operand" "")
3884 (match_operand:TF 1 "general_operand" "")))]
3885 "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
3886 "emit_tfmode_cvt (FLOAT_TRUNCATE, operands); DONE;")
3888 (define_insn "*trunctfdf2_hq"
3889 [(set (match_operand:DF 0 "register_operand" "=e")
3891 (match_operand:TF 1 "register_operand" "e")))]
3892 "TARGET_FPU && TARGET_HARD_QUAD"
3894 [(set_attr "type" "fp")])
3897 ;; Conversion between fixed point and floating point.
3899 (define_insn "floatsisf2"
3900 [(set (match_operand:SF 0 "register_operand" "=f")
3901 (float:SF (match_operand:SI 1 "register_operand" "f")))]
3904 [(set_attr "type" "fp")
3905 (set_attr "fptype" "double")])
3907 (define_insn "floatsidf2"
3908 [(set (match_operand:DF 0 "register_operand" "=e")
3909 (float:DF (match_operand:SI 1 "register_operand" "f")))]
3912 [(set_attr "type" "fp")
3913 (set_attr "fptype" "double")])
3915 (define_expand "floatsitf2"
3916 [(set (match_operand:TF 0 "nonimmediate_operand" "")
3917 (float:TF (match_operand:SI 1 "register_operand" "")))]
3918 "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
3919 "emit_tfmode_cvt (FLOAT, operands); DONE;")
3921 (define_insn "*floatsitf2_hq"
3922 [(set (match_operand:TF 0 "register_operand" "=e")
3923 (float:TF (match_operand:SI 1 "register_operand" "f")))]
3924 "TARGET_FPU && TARGET_HARD_QUAD"
3926 [(set_attr "type" "fp")])
3928 (define_expand "floatunssitf2"
3929 [(set (match_operand:TF 0 "nonimmediate_operand" "")
3930 (unsigned_float:TF (match_operand:SI 1 "register_operand" "")))]
3931 "TARGET_FPU && TARGET_ARCH64 && ! TARGET_HARD_QUAD"
3932 "emit_tfmode_cvt (UNSIGNED_FLOAT, operands); DONE;")
3934 ;; Now the same for 64 bit sources.
3936 (define_insn "floatdisf2"
3937 [(set (match_operand:SF 0 "register_operand" "=f")
3938 (float:SF (match_operand:DI 1 "register_operand" "e")))]
3939 "TARGET_V9 && TARGET_FPU"
3941 [(set_attr "type" "fp")
3942 (set_attr "fptype" "double")])
3944 (define_expand "floatunsdisf2"
3945 [(use (match_operand:SF 0 "register_operand" ""))
3946 (use (match_operand:DI 1 "general_operand" ""))]
3947 "TARGET_ARCH64 && TARGET_FPU"
3948 "sparc_emit_floatunsdi (operands, SFmode); DONE;")
3950 (define_insn "floatdidf2"
3951 [(set (match_operand:DF 0 "register_operand" "=e")
3952 (float:DF (match_operand:DI 1 "register_operand" "e")))]
3953 "TARGET_V9 && TARGET_FPU"
3955 [(set_attr "type" "fp")
3956 (set_attr "fptype" "double")])
3958 (define_expand "floatunsdidf2"
3959 [(use (match_operand:DF 0 "register_operand" ""))
3960 (use (match_operand:DI 1 "general_operand" ""))]
3961 "TARGET_ARCH64 && TARGET_FPU"
3962 "sparc_emit_floatunsdi (operands, DFmode); DONE;")
3964 (define_expand "floatditf2"
3965 [(set (match_operand:TF 0 "nonimmediate_operand" "")
3966 (float:TF (match_operand:DI 1 "register_operand" "")))]
3967 "TARGET_FPU && TARGET_V9 && (TARGET_HARD_QUAD || TARGET_ARCH64)"
3968 "emit_tfmode_cvt (FLOAT, operands); DONE;")
3970 (define_insn "*floatditf2_hq"
3971 [(set (match_operand:TF 0 "register_operand" "=e")
3972 (float:TF (match_operand:DI 1 "register_operand" "e")))]
3973 "TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD"
3975 [(set_attr "type" "fp")])
3977 (define_expand "floatunsditf2"
3978 [(set (match_operand:TF 0 "nonimmediate_operand" "")
3979 (unsigned_float:TF (match_operand:DI 1 "register_operand" "")))]
3980 "TARGET_FPU && TARGET_ARCH64 && ! TARGET_HARD_QUAD"
3981 "emit_tfmode_cvt (UNSIGNED_FLOAT, operands); DONE;")
3983 ;; Convert a float to an actual integer.
3984 ;; Truncation is performed as part of the conversion.
3986 (define_insn "fix_truncsfsi2"
3987 [(set (match_operand:SI 0 "register_operand" "=f")
3988 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
3991 [(set_attr "type" "fp")
3992 (set_attr "fptype" "double")])
3994 (define_insn "fix_truncdfsi2"
3995 [(set (match_operand:SI 0 "register_operand" "=f")
3996 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "e"))))]
3999 [(set_attr "type" "fp")
4000 (set_attr "fptype" "double")])
4002 (define_expand "fix_trunctfsi2"
4003 [(set (match_operand:SI 0 "register_operand" "")
4004 (fix:SI (match_operand:TF 1 "general_operand" "")))]
4005 "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
4006 "emit_tfmode_cvt (FIX, operands); DONE;")
4008 (define_insn "*fix_trunctfsi2_hq"
4009 [(set (match_operand:SI 0 "register_operand" "=f")
4010 (fix:SI (match_operand:TF 1 "register_operand" "e")))]
4011 "TARGET_FPU && TARGET_HARD_QUAD"
4013 [(set_attr "type" "fp")])
4015 (define_expand "fixuns_trunctfsi2"
4016 [(set (match_operand:SI 0 "register_operand" "")
4017 (unsigned_fix:SI (match_operand:TF 1 "general_operand" "")))]
4018 "TARGET_FPU && TARGET_ARCH64 && ! TARGET_HARD_QUAD"
4019 "emit_tfmode_cvt (UNSIGNED_FIX, operands); DONE;")
4021 ;; Now the same, for V9 targets
4023 (define_insn "fix_truncsfdi2"
4024 [(set (match_operand:DI 0 "register_operand" "=e")
4025 (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4026 "TARGET_V9 && TARGET_FPU"
4028 [(set_attr "type" "fp")
4029 (set_attr "fptype" "double")])
4031 (define_expand "fixuns_truncsfdi2"
4032 [(use (match_operand:DI 0 "register_operand" ""))
4033 (use (match_operand:SF 1 "general_operand" ""))]
4034 "TARGET_ARCH64 && TARGET_FPU"
4035 "sparc_emit_fixunsdi (operands, SFmode); DONE;")
4037 (define_insn "fix_truncdfdi2"
4038 [(set (match_operand:DI 0 "register_operand" "=e")
4039 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "e"))))]
4040 "TARGET_V9 && TARGET_FPU"
4042 [(set_attr "type" "fp")
4043 (set_attr "fptype" "double")])
4045 (define_expand "fixuns_truncdfdi2"
4046 [(use (match_operand:DI 0 "register_operand" ""))
4047 (use (match_operand:DF 1 "general_operand" ""))]
4048 "TARGET_ARCH64 && TARGET_FPU"
4049 "sparc_emit_fixunsdi (operands, DFmode); DONE;")
4051 (define_expand "fix_trunctfdi2"
4052 [(set (match_operand:DI 0 "register_operand" "")
4053 (fix:DI (match_operand:TF 1 "general_operand" "")))]
4054 "TARGET_V9 && TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
4055 "emit_tfmode_cvt (FIX, operands); DONE;")
4057 (define_insn "*fix_trunctfdi2_hq"
4058 [(set (match_operand:DI 0 "register_operand" "=e")
4059 (fix:DI (match_operand:TF 1 "register_operand" "e")))]
4060 "TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD"
4062 [(set_attr "type" "fp")])
4064 (define_expand "fixuns_trunctfdi2"
4065 [(set (match_operand:DI 0 "register_operand" "")
4066 (unsigned_fix:DI (match_operand:TF 1 "general_operand" "")))]
4067 "TARGET_FPU && TARGET_ARCH64 && ! TARGET_HARD_QUAD"
4068 "emit_tfmode_cvt (UNSIGNED_FIX, operands); DONE;")
4071 ;; Integer addition/subtraction instructions.
4073 (define_expand "adddi3"
4074 [(set (match_operand:DI 0 "register_operand" "")
4075 (plus:DI (match_operand:DI 1 "register_operand" "")
4076 (match_operand:DI 2 "arith_double_add_operand" "")))]
4079 if (! TARGET_ARCH64)
4081 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
4082 gen_rtx_SET (VOIDmode, operands[0],
4083 gen_rtx_PLUS (DImode, operands[1],
4085 gen_rtx_CLOBBER (VOIDmode,
4086 gen_rtx_REG (CCmode, SPARC_ICC_REG)))));
4091 (define_insn_and_split "adddi3_insn_sp32"
4092 [(set (match_operand:DI 0 "register_operand" "=r")
4093 (plus:DI (match_operand:DI 1 "arith_double_operand" "%r")
4094 (match_operand:DI 2 "arith_double_operand" "rHI")))
4095 (clobber (reg:CC 100))]
4098 "&& reload_completed"
4099 [(parallel [(set (reg:CC_NOOV 100)
4100 (compare:CC_NOOV (plus:SI (match_dup 4)
4104 (plus:SI (match_dup 4) (match_dup 5)))])
4106 (plus:SI (plus:SI (match_dup 7)
4108 (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
4110 operands[3] = gen_lowpart (SImode, operands[0]);
4111 operands[4] = gen_lowpart (SImode, operands[1]);
4112 operands[5] = gen_lowpart (SImode, operands[2]);
4113 operands[6] = gen_highpart (SImode, operands[0]);
4114 operands[7] = gen_highpart_mode (SImode, DImode, operands[1]);
4115 #if HOST_BITS_PER_WIDE_INT == 32
4116 if (GET_CODE (operands[2]) == CONST_INT)
4118 if (INTVAL (operands[2]) < 0)
4119 operands[8] = constm1_rtx;
4121 operands[8] = const0_rtx;
4125 operands[8] = gen_highpart_mode (SImode, DImode, operands[2]);
4127 [(set_attr "length" "2")])
4129 ;; LTU here means "carry set"
4131 [(set (match_operand:SI 0 "register_operand" "=r")
4132 (plus:SI (plus:SI (match_operand:SI 1 "arith_operand" "%r")
4133 (match_operand:SI 2 "arith_operand" "rI"))
4134 (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
4137 [(set_attr "type" "ialuX")])
4139 (define_insn_and_split "*addx_extend_sp32"
4140 [(set (match_operand:DI 0 "register_operand" "=r")
4141 (zero_extend:DI (plus:SI (plus:SI
4142 (match_operand:SI 1 "register_or_zero_operand" "%rJ")
4143 (match_operand:SI 2 "arith_operand" "rI"))
4144 (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))]
4147 "&& reload_completed"
4148 [(set (match_dup 3) (plus:SI (plus:SI (match_dup 1) (match_dup 2))
4149 (ltu:SI (reg:CC_NOOV 100) (const_int 0))))
4150 (set (match_dup 4) (const_int 0))]
4151 "operands[3] = gen_lowpart (SImode, operands[0]);
4152 operands[4] = gen_highpart_mode (SImode, DImode, operands[1]);"
4153 [(set_attr "length" "2")])
4155 (define_insn "*addx_extend_sp64"
4156 [(set (match_operand:DI 0 "register_operand" "=r")
4157 (zero_extend:DI (plus:SI (plus:SI (match_operand:SI 1 "register_or_zero_operand" "%rJ")
4158 (match_operand:SI 2 "arith_operand" "rI"))
4159 (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))]
4162 [(set_attr "type" "ialuX")])
4164 (define_insn_and_split ""
4165 [(set (match_operand:DI 0 "register_operand" "=r")
4166 (plus:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
4167 (match_operand:DI 2 "register_operand" "r")))
4168 (clobber (reg:CC 100))]
4171 "&& reload_completed"
4172 [(parallel [(set (reg:CC_NOOV 100)
4173 (compare:CC_NOOV (plus:SI (match_dup 3) (match_dup 1))
4175 (set (match_dup 5) (plus:SI (match_dup 3) (match_dup 1)))])
4177 (plus:SI (plus:SI (match_dup 4) (const_int 0))
4178 (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
4179 "operands[3] = gen_lowpart (SImode, operands[2]);
4180 operands[4] = gen_highpart (SImode, operands[2]);
4181 operands[5] = gen_lowpart (SImode, operands[0]);
4182 operands[6] = gen_highpart (SImode, operands[0]);"
4183 [(set_attr "length" "2")])
4185 (define_insn "*adddi3_sp64"
4186 [(set (match_operand:DI 0 "register_operand" "=r,r")
4187 (plus:DI (match_operand:DI 1 "register_operand" "%r,r")
4188 (match_operand:DI 2 "arith_add_operand" "rI,O")))]
4194 (define_insn "addsi3"
4195 [(set (match_operand:SI 0 "register_operand" "=r,r,d")
4196 (plus:SI (match_operand:SI 1 "register_operand" "%r,r,d")
4197 (match_operand:SI 2 "arith_add_operand" "rI,O,d")))]
4202 fpadd32s\t%1, %2, %0"
4203 [(set_attr "type" "*,*,fga")
4204 (set_attr "fptype" "*,*,single")])
4206 (define_insn "*cmp_cc_plus"
4207 [(set (reg:CC_NOOV 100)
4208 (compare:CC_NOOV (plus:SI (match_operand:SI 0 "arith_operand" "%r")
4209 (match_operand:SI 1 "arith_operand" "rI"))
4212 "addcc\t%0, %1, %%g0"
4213 [(set_attr "type" "compare")])
4215 (define_insn "*cmp_ccx_plus"
4216 [(set (reg:CCX_NOOV 100)
4217 (compare:CCX_NOOV (plus:DI (match_operand:DI 0 "arith_operand" "%r")
4218 (match_operand:DI 1 "arith_operand" "rI"))
4221 "addcc\t%0, %1, %%g0"
4222 [(set_attr "type" "compare")])
4224 (define_insn "*cmp_cc_plus_set"
4225 [(set (reg:CC_NOOV 100)
4226 (compare:CC_NOOV (plus:SI (match_operand:SI 1 "arith_operand" "%r")
4227 (match_operand:SI 2 "arith_operand" "rI"))
4229 (set (match_operand:SI 0 "register_operand" "=r")
4230 (plus:SI (match_dup 1) (match_dup 2)))]
4233 [(set_attr "type" "compare")])
4235 (define_insn "*cmp_ccx_plus_set"
4236 [(set (reg:CCX_NOOV 100)
4237 (compare:CCX_NOOV (plus:DI (match_operand:DI 1 "arith_operand" "%r")
4238 (match_operand:DI 2 "arith_operand" "rI"))
4240 (set (match_operand:DI 0 "register_operand" "=r")
4241 (plus:DI (match_dup 1) (match_dup 2)))]
4244 [(set_attr "type" "compare")])
4246 (define_expand "subdi3"
4247 [(set (match_operand:DI 0 "register_operand" "")
4248 (minus:DI (match_operand:DI 1 "register_operand" "")
4249 (match_operand:DI 2 "arith_double_add_operand" "")))]
4252 if (! TARGET_ARCH64)
4254 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
4255 gen_rtx_SET (VOIDmode, operands[0],
4256 gen_rtx_MINUS (DImode, operands[1],
4258 gen_rtx_CLOBBER (VOIDmode,
4259 gen_rtx_REG (CCmode, SPARC_ICC_REG)))));
4264 (define_insn_and_split "subdi3_insn_sp32"
4265 [(set (match_operand:DI 0 "register_operand" "=r")
4266 (minus:DI (match_operand:DI 1 "register_operand" "r")
4267 (match_operand:DI 2 "arith_double_operand" "rHI")))
4268 (clobber (reg:CC 100))]
4271 "&& reload_completed"
4272 [(parallel [(set (reg:CC_NOOV 100)
4273 (compare:CC_NOOV (minus:SI (match_dup 4)
4277 (minus:SI (match_dup 4) (match_dup 5)))])
4279 (minus:SI (minus:SI (match_dup 7)
4281 (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
4283 operands[3] = gen_lowpart (SImode, operands[0]);
4284 operands[4] = gen_lowpart (SImode, operands[1]);
4285 operands[5] = gen_lowpart (SImode, operands[2]);
4286 operands[6] = gen_highpart (SImode, operands[0]);
4287 operands[7] = gen_highpart (SImode, operands[1]);
4288 #if HOST_BITS_PER_WIDE_INT == 32
4289 if (GET_CODE (operands[2]) == CONST_INT)
4291 if (INTVAL (operands[2]) < 0)
4292 operands[8] = constm1_rtx;
4294 operands[8] = const0_rtx;
4298 operands[8] = gen_highpart_mode (SImode, DImode, operands[2]);
4300 [(set_attr "length" "2")])
4302 ;; LTU here means "carry set"
4304 [(set (match_operand:SI 0 "register_operand" "=r")
4305 (minus:SI (minus:SI (match_operand:SI 1 "register_or_zero_operand" "rJ")
4306 (match_operand:SI 2 "arith_operand" "rI"))
4307 (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
4310 [(set_attr "type" "ialuX")])
4312 (define_insn "*subx_extend_sp64"
4313 [(set (match_operand:DI 0 "register_operand" "=r")
4314 (zero_extend:DI (minus:SI (minus:SI (match_operand:SI 1 "register_or_zero_operand" "rJ")
4315 (match_operand:SI 2 "arith_operand" "rI"))
4316 (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))]
4319 [(set_attr "type" "ialuX")])
4321 (define_insn_and_split "*subx_extend"
4322 [(set (match_operand:DI 0 "register_operand" "=r")
4323 (zero_extend:DI (minus:SI (minus:SI (match_operand:SI 1 "register_or_zero_operand" "rJ")
4324 (match_operand:SI 2 "arith_operand" "rI"))
4325 (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))]
4328 "&& reload_completed"
4329 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 1) (match_dup 2))
4330 (ltu:SI (reg:CC_NOOV 100) (const_int 0))))
4331 (set (match_dup 4) (const_int 0))]
4332 "operands[3] = gen_lowpart (SImode, operands[0]);
4333 operands[4] = gen_highpart (SImode, operands[0]);"
4334 [(set_attr "length" "2")])
4336 (define_insn_and_split ""
4337 [(set (match_operand:DI 0 "register_operand" "=r")
4338 (minus:DI (match_operand:DI 1 "register_operand" "r")
4339 (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))
4340 (clobber (reg:CC 100))]
4343 "&& reload_completed"
4344 [(parallel [(set (reg:CC_NOOV 100)
4345 (compare:CC_NOOV (minus:SI (match_dup 3) (match_dup 2))
4347 (set (match_dup 5) (minus:SI (match_dup 3) (match_dup 2)))])
4349 (minus:SI (minus:SI (match_dup 4) (const_int 0))
4350 (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
4351 "operands[3] = gen_lowpart (SImode, operands[1]);
4352 operands[4] = gen_highpart (SImode, operands[1]);
4353 operands[5] = gen_lowpart (SImode, operands[0]);
4354 operands[6] = gen_highpart (SImode, operands[0]);"
4355 [(set_attr "length" "2")])
4357 (define_insn "*subdi3_sp64"
4358 [(set (match_operand:DI 0 "register_operand" "=r,r")
4359 (minus:DI (match_operand:DI 1 "register_operand" "r,r")
4360 (match_operand:DI 2 "arith_add_operand" "rI,O")))]
4366 (define_insn "subsi3"
4367 [(set (match_operand:SI 0 "register_operand" "=r,r,d")
4368 (minus:SI (match_operand:SI 1 "register_operand" "r,r,d")
4369 (match_operand:SI 2 "arith_add_operand" "rI,O,d")))]
4374 fpsub32s\t%1, %2, %0"
4375 [(set_attr "type" "*,*,fga")
4376 (set_attr "fptype" "*,*,single")])
4378 (define_insn "*cmp_minus_cc"
4379 [(set (reg:CC_NOOV 100)
4380 (compare:CC_NOOV (minus:SI (match_operand:SI 0 "register_or_zero_operand" "rJ")
4381 (match_operand:SI 1 "arith_operand" "rI"))
4384 "subcc\t%r0, %1, %%g0"
4385 [(set_attr "type" "compare")])
4387 (define_insn "*cmp_minus_ccx"
4388 [(set (reg:CCX_NOOV 100)
4389 (compare:CCX_NOOV (minus:DI (match_operand:DI 0 "register_operand" "r")
4390 (match_operand:DI 1 "arith_operand" "rI"))
4393 "subcc\t%0, %1, %%g0"
4394 [(set_attr "type" "compare")])
4396 (define_insn "cmp_minus_cc_set"
4397 [(set (reg:CC_NOOV 100)
4398 (compare:CC_NOOV (minus:SI (match_operand:SI 1 "register_or_zero_operand" "rJ")
4399 (match_operand:SI 2 "arith_operand" "rI"))
4401 (set (match_operand:SI 0 "register_operand" "=r")
4402 (minus:SI (match_dup 1) (match_dup 2)))]
4404 "subcc\t%r1, %2, %0"
4405 [(set_attr "type" "compare")])
4407 (define_insn "*cmp_minus_ccx_set"
4408 [(set (reg:CCX_NOOV 100)
4409 (compare:CCX_NOOV (minus:DI (match_operand:DI 1 "register_operand" "r")
4410 (match_operand:DI 2 "arith_operand" "rI"))
4412 (set (match_operand:DI 0 "register_operand" "=r")
4413 (minus:DI (match_dup 1) (match_dup 2)))]
4416 [(set_attr "type" "compare")])
4419 ;; Integer multiply/divide instructions.
4421 ;; The 32-bit multiply/divide instructions are deprecated on v9, but at
4422 ;; least in UltraSPARC I, II and IIi it is a win tick-wise.
4424 (define_insn "mulsi3"
4425 [(set (match_operand:SI 0 "register_operand" "=r")
4426 (mult:SI (match_operand:SI 1 "arith_operand" "%r")
4427 (match_operand:SI 2 "arith_operand" "rI")))]
4430 [(set_attr "type" "imul")])
4432 (define_expand "muldi3"
4433 [(set (match_operand:DI 0 "register_operand" "")
4434 (mult:DI (match_operand:DI 1 "arith_operand" "")
4435 (match_operand:DI 2 "arith_operand" "")))]
4436 "TARGET_ARCH64 || TARGET_V8PLUS"
4440 emit_insn (gen_muldi3_v8plus (operands[0], operands[1], operands[2]));
4445 (define_insn "*muldi3_sp64"
4446 [(set (match_operand:DI 0 "register_operand" "=r")
4447 (mult:DI (match_operand:DI 1 "arith_operand" "%r")
4448 (match_operand:DI 2 "arith_operand" "rI")))]
4451 [(set_attr "type" "imul")])
4453 ;; V8plus wide multiply.
4455 (define_insn "muldi3_v8plus"
4456 [(set (match_operand:DI 0 "register_operand" "=r,h")
4457 (mult:DI (match_operand:DI 1 "arith_operand" "%r,0")
4458 (match_operand:DI 2 "arith_operand" "rI,rI")))
4459 (clobber (match_scratch:SI 3 "=&h,X"))
4460 (clobber (match_scratch:SI 4 "=&h,X"))]
4463 if (sparc_check_64 (operands[1], insn) <= 0)
4464 output_asm_insn ("srl\t%L1, 0, %L1", operands);
4465 if (which_alternative == 1)
4466 output_asm_insn ("sllx\t%H1, 32, %H1", operands);
4467 if (GET_CODE (operands[2]) == CONST_INT)
4469 if (which_alternative == 1)
4470 return "or\t%L1, %H1, %H1\n\tmulx\t%H1, %2, %L0\;srlx\t%L0, 32, %H0";
4472 return "sllx\t%H1, 32, %3\n\tor\t%L1, %3, %3\n\tmulx\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0";
4474 else if (rtx_equal_p (operands[1], operands[2]))
4476 if (which_alternative == 1)
4477 return "or\t%L1, %H1, %H1\n\tmulx\t%H1, %H1, %L0\;srlx\t%L0, 32, %H0";
4479 return "sllx\t%H1, 32, %3\n\tor\t%L1, %3, %3\n\tmulx\t%3, %3, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0";
4481 if (sparc_check_64 (operands[2], insn) <= 0)
4482 output_asm_insn ("srl\t%L2, 0, %L2", operands);
4483 if (which_alternative == 1)
4484 return "or\t%L1, %H1, %H1\n\tsllx\t%H2, 32, %L1\n\tor\t%L2, %L1, %L1\n\tmulx\t%H1, %L1, %L0\;srlx\t%L0, 32, %H0";
4486 return "sllx\t%H1, 32, %3\n\tsllx\t%H2, 32, %4\n\tor\t%L1, %3, %3\n\tor\t%L2, %4, %4\n\tmulx\t%3, %4, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0";
4488 [(set_attr "type" "multi")
4489 (set_attr "length" "9,8")])
4491 (define_insn "*cmp_mul_set"
4493 (compare:CC (mult:SI (match_operand:SI 1 "arith_operand" "%r")
4494 (match_operand:SI 2 "arith_operand" "rI"))
4496 (set (match_operand:SI 0 "register_operand" "=r")
4497 (mult:SI (match_dup 1) (match_dup 2)))]
4498 "TARGET_V8 || TARGET_SPARCLITE || TARGET_DEPRECATED_V8_INSNS"
4499 "smulcc\t%1, %2, %0"
4500 [(set_attr "type" "imul")])
4502 (define_expand "mulsidi3"
4503 [(set (match_operand:DI 0 "register_operand" "")
4504 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
4505 (sign_extend:DI (match_operand:SI 2 "arith_operand" ""))))]
4508 if (CONSTANT_P (operands[2]))
4511 emit_insn (gen_const_mulsidi3_v8plus (operands[0], operands[1],
4513 else if (TARGET_ARCH32)
4514 emit_insn (gen_const_mulsidi3_sp32 (operands[0], operands[1],
4517 emit_insn (gen_const_mulsidi3_sp64 (operands[0], operands[1],
4523 emit_insn (gen_mulsidi3_v8plus (operands[0], operands[1], operands[2]));
4528 ;; V9 puts the 64-bit product in a 64-bit register. Only out or global
4529 ;; registers can hold 64-bit values in the V8plus environment.
4531 (define_insn "mulsidi3_v8plus"
4532 [(set (match_operand:DI 0 "register_operand" "=h,r")
4533 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
4534 (sign_extend:DI (match_operand:SI 2 "register_operand" "r,r"))))
4535 (clobber (match_scratch:SI 3 "=X,&h"))]
4538 smul\t%1, %2, %L0\n\tsrlx\t%L0, 32, %H0
4539 smul\t%1, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0"
4540 [(set_attr "type" "multi")
4541 (set_attr "length" "2,3")])
4544 (define_insn "const_mulsidi3_v8plus"
4545 [(set (match_operand:DI 0 "register_operand" "=h,r")
4546 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
4547 (match_operand:DI 2 "small_int_operand" "I,I")))
4548 (clobber (match_scratch:SI 3 "=X,&h"))]
4551 smul\t%1, %2, %L0\n\tsrlx\t%L0, 32, %H0
4552 smul\t%1, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0"
4553 [(set_attr "type" "multi")
4554 (set_attr "length" "2,3")])
4557 (define_insn "*mulsidi3_sp32"
4558 [(set (match_operand:DI 0 "register_operand" "=r")
4559 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
4560 (sign_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
4563 return TARGET_SPARCLET
4564 ? "smuld\t%1, %2, %L0"
4565 : "smul\t%1, %2, %L0\n\trd\t%%y, %H0";
4568 (if_then_else (eq_attr "isa" "sparclet")
4569 (const_string "imul") (const_string "multi")))
4570 (set (attr "length")
4571 (if_then_else (eq_attr "isa" "sparclet")
4572 (const_int 1) (const_int 2)))])
4574 (define_insn "*mulsidi3_sp64"
4575 [(set (match_operand:DI 0 "register_operand" "=r")
4576 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
4577 (sign_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
4578 "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
4580 [(set_attr "type" "imul")])
4582 ;; Extra pattern, because sign_extend of a constant isn't valid.
4585 (define_insn "const_mulsidi3_sp32"
4586 [(set (match_operand:DI 0 "register_operand" "=r")
4587 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
4588 (match_operand:DI 2 "small_int_operand" "I")))]
4591 return TARGET_SPARCLET
4592 ? "smuld\t%1, %2, %L0"
4593 : "smul\t%1, %2, %L0\n\trd\t%%y, %H0";
4596 (if_then_else (eq_attr "isa" "sparclet")
4597 (const_string "imul") (const_string "multi")))
4598 (set (attr "length")
4599 (if_then_else (eq_attr "isa" "sparclet")
4600 (const_int 1) (const_int 2)))])
4602 (define_insn "const_mulsidi3_sp64"
4603 [(set (match_operand:DI 0 "register_operand" "=r")
4604 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
4605 (match_operand:DI 2 "small_int_operand" "I")))]
4606 "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
4608 [(set_attr "type" "imul")])
4610 (define_expand "smulsi3_highpart"
4611 [(set (match_operand:SI 0 "register_operand" "")
4613 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
4614 (sign_extend:DI (match_operand:SI 2 "arith_operand" "")))
4616 "TARGET_HARD_MUL && TARGET_ARCH32"
4618 if (CONSTANT_P (operands[2]))
4622 emit_insn (gen_const_smulsi3_highpart_v8plus (operands[0],
4628 emit_insn (gen_const_smulsi3_highpart (operands[0], operands[1], operands[2]));
4633 emit_insn (gen_smulsi3_highpart_v8plus (operands[0], operands[1],
4634 operands[2], GEN_INT (32)));
4640 (define_insn "smulsi3_highpart_v8plus"
4641 [(set (match_operand:SI 0 "register_operand" "=h,r")
4643 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
4644 (sign_extend:DI (match_operand:SI 2 "register_operand" "r,r")))
4645 (match_operand:SI 3 "small_int_operand" "I,I"))))
4646 (clobber (match_scratch:SI 4 "=X,&h"))]
4649 smul\t%1, %2, %0\;srlx\t%0, %3, %0
4650 smul\t%1, %2, %4\;srlx\t%4, %3, %0"
4651 [(set_attr "type" "multi")
4652 (set_attr "length" "2")])
4654 ;; The combiner changes TRUNCATE in the previous pattern to SUBREG.
4657 [(set (match_operand:SI 0 "register_operand" "=h,r")
4660 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
4661 (sign_extend:DI (match_operand:SI 2 "register_operand" "r,r")))
4662 (match_operand:SI 3 "small_int_operand" "I,I"))
4664 (clobber (match_scratch:SI 4 "=X,&h"))]
4667 smul\t%1, %2, %0\n\tsrlx\t%0, %3, %0
4668 smul\t%1, %2, %4\n\tsrlx\t%4, %3, %0"
4669 [(set_attr "type" "multi")
4670 (set_attr "length" "2")])
4673 (define_insn "const_smulsi3_highpart_v8plus"
4674 [(set (match_operand:SI 0 "register_operand" "=h,r")
4676 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
4677 (match_operand:DI 2 "small_int_operand" "I,I"))
4678 (match_operand:SI 3 "small_int_operand" "I,I"))))
4679 (clobber (match_scratch:SI 4 "=X,&h"))]
4682 smul\t%1, %2, %0\n\tsrlx\t%0, %3, %0
4683 smul\t%1, %2, %4\n\tsrlx\t%4, %3, %0"
4684 [(set_attr "type" "multi")
4685 (set_attr "length" "2")])
4688 (define_insn "*smulsi3_highpart_sp32"
4689 [(set (match_operand:SI 0 "register_operand" "=r")
4691 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
4692 (sign_extend:DI (match_operand:SI 2 "register_operand" "r")))
4695 "smul\t%1, %2, %%g0\n\trd\t%%y, %0"
4696 [(set_attr "type" "multi")
4697 (set_attr "length" "2")])
4700 (define_insn "const_smulsi3_highpart"
4701 [(set (match_operand:SI 0 "register_operand" "=r")
4703 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
4704 (match_operand:DI 2 "small_int_operand" "i"))
4707 "smul\t%1, %2, %%g0\n\trd\t%%y, %0"
4708 [(set_attr "type" "multi")
4709 (set_attr "length" "2")])
4711 (define_expand "umulsidi3"
4712 [(set (match_operand:DI 0 "register_operand" "")
4713 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
4714 (zero_extend:DI (match_operand:SI 2 "uns_arith_operand" ""))))]
4717 if (CONSTANT_P (operands[2]))
4720 emit_insn (gen_const_umulsidi3_v8plus (operands[0], operands[1],
4722 else if (TARGET_ARCH32)
4723 emit_insn (gen_const_umulsidi3_sp32 (operands[0], operands[1],
4726 emit_insn (gen_const_umulsidi3_sp64 (operands[0], operands[1],
4732 emit_insn (gen_umulsidi3_v8plus (operands[0], operands[1], operands[2]));
4738 (define_insn "umulsidi3_v8plus"
4739 [(set (match_operand:DI 0 "register_operand" "=h,r")
4740 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
4741 (zero_extend:DI (match_operand:SI 2 "register_operand" "r,r"))))
4742 (clobber (match_scratch:SI 3 "=X,&h"))]
4745 umul\t%1, %2, %L0\n\tsrlx\t%L0, 32, %H0
4746 umul\t%1, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0"
4747 [(set_attr "type" "multi")
4748 (set_attr "length" "2,3")])
4751 (define_insn "*umulsidi3_sp32"
4752 [(set (match_operand:DI 0 "register_operand" "=r")
4753 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
4754 (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
4757 return TARGET_SPARCLET
4758 ? "umuld\t%1, %2, %L0"
4759 : "umul\t%1, %2, %L0\n\trd\t%%y, %H0";
4762 (if_then_else (eq_attr "isa" "sparclet")
4763 (const_string "imul") (const_string "multi")))
4764 (set (attr "length")
4765 (if_then_else (eq_attr "isa" "sparclet")
4766 (const_int 1) (const_int 2)))])
4768 (define_insn "*umulsidi3_sp64"
4769 [(set (match_operand:DI 0 "register_operand" "=r")
4770 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
4771 (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
4772 "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
4774 [(set_attr "type" "imul")])
4776 ;; Extra pattern, because sign_extend of a constant isn't valid.
4779 (define_insn "const_umulsidi3_sp32"
4780 [(set (match_operand:DI 0 "register_operand" "=r")
4781 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
4782 (match_operand:DI 2 "uns_small_int_operand" "")))]
4785 return TARGET_SPARCLET
4786 ? "umuld\t%1, %s2, %L0"
4787 : "umul\t%1, %s2, %L0\n\trd\t%%y, %H0";
4790 (if_then_else (eq_attr "isa" "sparclet")
4791 (const_string "imul") (const_string "multi")))
4792 (set (attr "length")
4793 (if_then_else (eq_attr "isa" "sparclet")
4794 (const_int 1) (const_int 2)))])
4796 (define_insn "const_umulsidi3_sp64"
4797 [(set (match_operand:DI 0 "register_operand" "=r")
4798 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
4799 (match_operand:DI 2 "uns_small_int_operand" "")))]
4800 "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
4802 [(set_attr "type" "imul")])
4805 (define_insn "const_umulsidi3_v8plus"
4806 [(set (match_operand:DI 0 "register_operand" "=h,r")
4807 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
4808 (match_operand:DI 2 "uns_small_int_operand" "")))
4809 (clobber (match_scratch:SI 3 "=X,h"))]
4812 umul\t%1, %s2, %L0\n\tsrlx\t%L0, 32, %H0
4813 umul\t%1, %s2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0"
4814 [(set_attr "type" "multi")
4815 (set_attr "length" "2,3")])
4817 (define_expand "umulsi3_highpart"
4818 [(set (match_operand:SI 0 "register_operand" "")
4820 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
4821 (zero_extend:DI (match_operand:SI 2 "uns_arith_operand" "")))
4823 "TARGET_HARD_MUL && TARGET_ARCH32"
4825 if (CONSTANT_P (operands[2]))
4829 emit_insn (gen_const_umulsi3_highpart_v8plus (operands[0],
4835 emit_insn (gen_const_umulsi3_highpart (operands[0], operands[1], operands[2]));
4840 emit_insn (gen_umulsi3_highpart_v8plus (operands[0], operands[1],
4841 operands[2], GEN_INT (32)));
4847 (define_insn "umulsi3_highpart_v8plus"
4848 [(set (match_operand:SI 0 "register_operand" "=h,r")
4850 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
4851 (zero_extend:DI (match_operand:SI 2 "register_operand" "r,r")))
4852 (match_operand:SI 3 "small_int_operand" "I,I"))))
4853 (clobber (match_scratch:SI 4 "=X,h"))]
4856 umul\t%1, %2, %0\n\tsrlx\t%0, %3, %0
4857 umul\t%1, %2, %4\n\tsrlx\t%4, %3, %0"
4858 [(set_attr "type" "multi")
4859 (set_attr "length" "2")])
4862 (define_insn "const_umulsi3_highpart_v8plus"
4863 [(set (match_operand:SI 0 "register_operand" "=h,r")
4865 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
4866 (match_operand:DI 2 "uns_small_int_operand" ""))
4867 (match_operand:SI 3 "small_int_operand" "I,I"))))
4868 (clobber (match_scratch:SI 4 "=X,h"))]
4871 umul\t%1, %s2, %0\n\tsrlx\t%0, %3, %0
4872 umul\t%1, %s2, %4\n\tsrlx\t%4, %3, %0"
4873 [(set_attr "type" "multi")
4874 (set_attr "length" "2")])
4877 (define_insn "*umulsi3_highpart_sp32"
4878 [(set (match_operand:SI 0 "register_operand" "=r")
4880 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
4881 (zero_extend:DI (match_operand:SI 2 "register_operand" "r")))
4884 "umul\t%1, %2, %%g0\n\trd\t%%y, %0"
4885 [(set_attr "type" "multi")
4886 (set_attr "length" "2")])
4889 (define_insn "const_umulsi3_highpart"
4890 [(set (match_operand:SI 0 "register_operand" "=r")
4892 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
4893 (match_operand:DI 2 "uns_small_int_operand" ""))
4896 "umul\t%1, %s2, %%g0\n\trd\t%%y, %0"
4897 [(set_attr "type" "multi")
4898 (set_attr "length" "2")])
4900 (define_expand "divsi3"
4901 [(parallel [(set (match_operand:SI 0 "register_operand" "")
4902 (div:SI (match_operand:SI 1 "register_operand" "")
4903 (match_operand:SI 2 "input_operand" "")))
4904 (clobber (match_scratch:SI 3 ""))])]
4905 "TARGET_V8 || TARGET_DEPRECATED_V8_INSNS"
4909 operands[3] = gen_reg_rtx(SImode);
4910 emit_insn (gen_ashrsi3 (operands[3], operands[1], GEN_INT (31)));
4911 emit_insn (gen_divsi3_sp64 (operands[0], operands[1], operands[2],
4917 ;; The V8 architecture specifies that there must be at least 3 instructions
4918 ;; between a write to the Y register and a use of it for correct results.
4919 ;; We try to fill one of them with a simple constant or a memory load.
4921 (define_insn "divsi3_sp32"
4922 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
4923 (div:SI (match_operand:SI 1 "register_operand" "r,r,r")
4924 (match_operand:SI 2 "input_operand" "rI,K,m")))
4925 (clobber (match_scratch:SI 3 "=&r,&r,&r"))]
4926 "(TARGET_V8 || TARGET_DEPRECATED_V8_INSNS) && TARGET_ARCH32"
4928 output_asm_insn ("sra\t%1, 31, %3", operands);
4929 output_asm_insn ("wr\t%3, 0, %%y", operands);
4931 switch (which_alternative)
4935 return "sdiv\t%1, %2, %0";
4937 return "nop\n\tnop\n\tnop\n\tsdiv\t%1, %2, %0";
4940 return "sethi\t%%hi(%a2), %3\n\tsdiv\t%1, %3, %0";
4942 return "sethi\t%%hi(%a2), %3\n\tnop\n\tnop\n\tsdiv\t%1, %3, %0";
4945 return "ld\t%2, %3\n\tsdiv\t%1, %3, %0";
4947 return "ld\t%2, %3\n\tnop\n\tnop\n\tsdiv\t%1, %3, %0";
4952 [(set_attr "type" "multi")
4953 (set (attr "length")
4954 (if_then_else (eq_attr "isa" "v9")
4955 (const_int 4) (const_int 6)))])
4957 (define_insn "divsi3_sp64"
4958 [(set (match_operand:SI 0 "register_operand" "=r")
4959 (div:SI (match_operand:SI 1 "register_operand" "r")
4960 (match_operand:SI 2 "input_operand" "rI")))
4961 (use (match_operand:SI 3 "register_operand" "r"))]
4962 "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
4963 "wr\t%%g0, %3, %%y\n\tsdiv\t%1, %2, %0"
4964 [(set_attr "type" "multi")
4965 (set_attr "length" "2")])
4967 (define_insn "divdi3"
4968 [(set (match_operand:DI 0 "register_operand" "=r")
4969 (div:DI (match_operand:DI 1 "register_operand" "r")
4970 (match_operand:DI 2 "arith_operand" "rI")))]
4973 [(set_attr "type" "idiv")])
4975 (define_insn "*cmp_sdiv_cc_set"
4977 (compare:CC (div:SI (match_operand:SI 1 "register_operand" "r")
4978 (match_operand:SI 2 "arith_operand" "rI"))
4980 (set (match_operand:SI 0 "register_operand" "=r")
4981 (div:SI (match_dup 1) (match_dup 2)))
4982 (clobber (match_scratch:SI 3 "=&r"))]
4983 "TARGET_V8 || TARGET_DEPRECATED_V8_INSNS"
4985 output_asm_insn ("sra\t%1, 31, %3", operands);
4986 output_asm_insn ("wr\t%3, 0, %%y", operands);
4989 return "sdivcc\t%1, %2, %0";
4991 return "nop\n\tnop\n\tnop\n\tsdivcc\t%1, %2, %0";
4993 [(set_attr "type" "multi")
4994 (set (attr "length")
4995 (if_then_else (eq_attr "isa" "v9")
4996 (const_int 3) (const_int 6)))])
4999 (define_expand "udivsi3"
5000 [(set (match_operand:SI 0 "register_operand" "")
5001 (udiv:SI (match_operand:SI 1 "nonimmediate_operand" "")
5002 (match_operand:SI 2 "input_operand" "")))]
5003 "TARGET_V8 || TARGET_DEPRECATED_V8_INSNS"
5006 ;; The V8 architecture specifies that there must be at least 3 instructions
5007 ;; between a write to the Y register and a use of it for correct results.
5008 ;; We try to fill one of them with a simple constant or a memory load.
5010 (define_insn "udivsi3_sp32"
5011 [(set (match_operand:SI 0 "register_operand" "=r,&r,&r,&r")
5012 (udiv:SI (match_operand:SI 1 "nonimmediate_operand" "r,r,r,m")
5013 (match_operand:SI 2 "input_operand" "rI,K,m,r")))]
5014 "(TARGET_V8 || TARGET_DEPRECATED_V8_INSNS) && TARGET_ARCH32"
5016 output_asm_insn ("wr\t%%g0, 0, %%y", operands);
5018 switch (which_alternative)
5022 return "udiv\t%1, %2, %0";
5024 return "nop\n\tnop\n\tnop\n\tudiv\t%1, %2, %0";
5027 return "sethi\t%%hi(%a2), %0\n\tudiv\t%1, %0, %0";
5029 return "sethi\t%%hi(%a2), %0\n\tnop\n\tnop\n\tudiv\t%1, %0, %0";
5032 return "ld\t%2, %0\n\tudiv\t%1, %0, %0";
5034 return "ld\t%2, %0\n\tnop\n\tnop\n\tudiv\t%1, %0, %0";
5037 return "ld\t%1, %0\n\tudiv\t%0, %2, %0";
5039 return "ld\t%1, %0\n\tnop\n\tnop\n\tudiv\t%0, %2, %0";
5044 [(set_attr "type" "multi")
5045 (set (attr "length")
5046 (if_then_else (eq_attr "isa" "v9")
5047 (const_int 3) (const_int 5)))])
5049 (define_insn "udivsi3_sp64"
5050 [(set (match_operand:SI 0 "register_operand" "=r")
5051 (udiv:SI (match_operand:SI 1 "nonimmediate_operand" "r")
5052 (match_operand:SI 2 "input_operand" "rI")))]
5053 "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
5054 "wr\t%%g0, 0, %%y\n\tudiv\t%1, %2, %0"
5055 [(set_attr "type" "multi")
5056 (set_attr "length" "2")])
5058 (define_insn "udivdi3"
5059 [(set (match_operand:DI 0 "register_operand" "=r")
5060 (udiv:DI (match_operand:DI 1 "register_operand" "r")
5061 (match_operand:DI 2 "arith_operand" "rI")))]
5064 [(set_attr "type" "idiv")])
5066 (define_insn "*cmp_udiv_cc_set"
5068 (compare:CC (udiv:SI (match_operand:SI 1 "register_operand" "r")
5069 (match_operand:SI 2 "arith_operand" "rI"))
5071 (set (match_operand:SI 0 "register_operand" "=r")
5072 (udiv:SI (match_dup 1) (match_dup 2)))]
5073 "TARGET_V8 || TARGET_DEPRECATED_V8_INSNS"
5075 output_asm_insn ("wr\t%%g0, 0, %%y", operands);
5078 return "udivcc\t%1, %2, %0";
5080 return "nop\n\tnop\n\tnop\n\tudivcc\t%1, %2, %0";
5082 [(set_attr "type" "multi")
5083 (set (attr "length")
5084 (if_then_else (eq_attr "isa" "v9")
5085 (const_int 2) (const_int 5)))])
5087 ; sparclet multiply/accumulate insns
5089 (define_insn "*smacsi"
5090 [(set (match_operand:SI 0 "register_operand" "=r")
5091 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "%r")
5092 (match_operand:SI 2 "arith_operand" "rI"))
5093 (match_operand:SI 3 "register_operand" "0")))]
5096 [(set_attr "type" "imul")])
5098 (define_insn "*smacdi"
5099 [(set (match_operand:DI 0 "register_operand" "=r")
5100 (plus:DI (mult:DI (sign_extend:DI
5101 (match_operand:SI 1 "register_operand" "%r"))
5103 (match_operand:SI 2 "register_operand" "r")))
5104 (match_operand:DI 3 "register_operand" "0")))]
5106 "smacd\t%1, %2, %L0"
5107 [(set_attr "type" "imul")])
5109 (define_insn "*umacdi"
5110 [(set (match_operand:DI 0 "register_operand" "=r")
5111 (plus:DI (mult:DI (zero_extend:DI
5112 (match_operand:SI 1 "register_operand" "%r"))
5114 (match_operand:SI 2 "register_operand" "r")))
5115 (match_operand:DI 3 "register_operand" "0")))]
5117 "umacd\t%1, %2, %L0"
5118 [(set_attr "type" "imul")])
5121 ;; Boolean instructions.
5123 ;; We define DImode `and' so with DImode `not' we can get
5124 ;; DImode `andn'. Other combinations are possible.
5126 (define_mode_iterator V64I [DI V2SI V4HI V8QI])
5127 (define_mode_iterator V32I [SI V2HI V4QI])
5129 (define_expand "and<V64I:mode>3"
5130 [(set (match_operand:V64I 0 "register_operand" "")
5131 (and:V64I (match_operand:V64I 1 "arith_double_operand" "")
5132 (match_operand:V64I 2 "arith_double_operand" "")))]
5136 (define_insn "*and<V64I:mode>3_sp32"
5137 [(set (match_operand:V64I 0 "register_operand" "=r,b")
5138 (and:V64I (match_operand:V64I 1 "arith_double_operand" "%r,b")
5139 (match_operand:V64I 2 "arith_double_operand" "rHI,b")))]
5144 [(set_attr "type" "*,fga")
5145 (set_attr "length" "2,*")
5146 (set_attr "fptype" "*,double")])
5148 (define_insn "*and<V64I:mode>3_sp64"
5149 [(set (match_operand:V64I 0 "register_operand" "=r,b")
5150 (and:V64I (match_operand:V64I 1 "arith_operand" "%r,b")
5151 (match_operand:V64I 2 "arith_operand" "rI,b")))]
5156 [(set_attr "type" "*,fga")
5157 (set_attr "fptype" "*,double")])
5159 (define_insn "and<V32I:mode>3"
5160 [(set (match_operand:V32I 0 "register_operand" "=r,d")
5161 (and:V32I (match_operand:V32I 1 "arith_operand" "%r,d")
5162 (match_operand:V32I 2 "arith_operand" "rI,d")))]
5167 [(set_attr "type" "*,fga")
5168 (set_attr "fptype" "*,single")])
5171 [(set (match_operand:SI 0 "register_operand" "")
5172 (and:SI (match_operand:SI 1 "register_operand" "")
5173 (match_operand:SI 2 "const_compl_high_operand" "")))
5174 (clobber (match_operand:SI 3 "register_operand" ""))]
5176 [(set (match_dup 3) (match_dup 4))
5177 (set (match_dup 0) (and:SI (not:SI (match_dup 3)) (match_dup 1)))]
5179 operands[4] = GEN_INT (~INTVAL (operands[2]));
5182 (define_insn_and_split "*and_not_<V64I:mode>_sp32"
5183 [(set (match_operand:V64I 0 "register_operand" "=r,b")
5184 (and:V64I (not:V64I (match_operand:V64I 1 "register_operand" "%r,b"))
5185 (match_operand:V64I 2 "register_operand" "r,b")))]
5189 fandnot1\t%1, %2, %0"
5190 "&& reload_completed
5191 && ((GET_CODE (operands[0]) == REG
5192 && REGNO (operands[0]) < 32)
5193 || (GET_CODE (operands[0]) == SUBREG
5194 && GET_CODE (SUBREG_REG (operands[0])) == REG
5195 && REGNO (SUBREG_REG (operands[0])) < 32))"
5196 [(set (match_dup 3) (and:SI (not:SI (match_dup 4)) (match_dup 5)))
5197 (set (match_dup 6) (and:SI (not:SI (match_dup 7)) (match_dup 8)))]
5198 "operands[3] = gen_highpart (SImode, operands[0]);
5199 operands[4] = gen_highpart (SImode, operands[1]);
5200 operands[5] = gen_highpart (SImode, operands[2]);
5201 operands[6] = gen_lowpart (SImode, operands[0]);
5202 operands[7] = gen_lowpart (SImode, operands[1]);
5203 operands[8] = gen_lowpart (SImode, operands[2]);"
5204 [(set_attr "type" "*,fga")
5205 (set_attr "length" "2,*")
5206 (set_attr "fptype" "*,double")])
5208 (define_insn "*and_not_<V64I:mode>_sp64"
5209 [(set (match_operand:V64I 0 "register_operand" "=r,b")
5210 (and:V64I (not:V64I (match_operand:V64I 1 "register_operand" "%r,b"))
5211 (match_operand:V64I 2 "register_operand" "r,b")))]
5215 fandnot1\t%1, %2, %0"
5216 [(set_attr "type" "*,fga")
5217 (set_attr "fptype" "*,double")])
5219 (define_insn "*and_not_<V32I:mode>"
5220 [(set (match_operand:V32I 0 "register_operand" "=r,d")
5221 (and:V32I (not:V32I (match_operand:V32I 1 "register_operand" "%r,d"))
5222 (match_operand:V32I 2 "register_operand" "r,d")))]
5226 fandnot1s\t%1, %2, %0"
5227 [(set_attr "type" "*,fga")
5228 (set_attr "fptype" "*,single")])
5230 (define_expand "ior<V64I:mode>3"
5231 [(set (match_operand:V64I 0 "register_operand" "")
5232 (ior:V64I (match_operand:V64I 1 "arith_double_operand" "")
5233 (match_operand:V64I 2 "arith_double_operand" "")))]
5237 (define_insn "*ior<V64I:mode>3_sp32"
5238 [(set (match_operand:V64I 0 "register_operand" "=r,b")
5239 (ior:V64I (match_operand:V64I 1 "arith_double_operand" "%r,b")
5240 (match_operand:V64I 2 "arith_double_operand" "rHI,b")))]
5245 [(set_attr "type" "*,fga")
5246 (set_attr "length" "2,*")
5247 (set_attr "fptype" "*,double")])
5249 (define_insn "*ior<V64I:mode>3_sp64"
5250 [(set (match_operand:V64I 0 "register_operand" "=r,b")
5251 (ior:V64I (match_operand:V64I 1 "arith_operand" "%r,b")
5252 (match_operand:V64I 2 "arith_operand" "rI,b")))]
5257 [(set_attr "type" "*,fga")
5258 (set_attr "fptype" "*,double")])
5260 (define_insn "ior<V32I:mode>3"
5261 [(set (match_operand:V32I 0 "register_operand" "=r,d")
5262 (ior:V32I (match_operand:V32I 1 "arith_operand" "%r,d")
5263 (match_operand:V32I 2 "arith_operand" "rI,d")))]
5268 [(set_attr "type" "*,fga")
5269 (set_attr "fptype" "*,single")])
5272 [(set (match_operand:SI 0 "register_operand" "")
5273 (ior:SI (match_operand:SI 1 "register_operand" "")
5274 (match_operand:SI 2 "const_compl_high_operand" "")))
5275 (clobber (match_operand:SI 3 "register_operand" ""))]
5277 [(set (match_dup 3) (match_dup 4))
5278 (set (match_dup 0) (ior:SI (not:SI (match_dup 3)) (match_dup 1)))]
5280 operands[4] = GEN_INT (~INTVAL (operands[2]));
5283 (define_insn_and_split "*or_not_<V64I:mode>_sp32"
5284 [(set (match_operand:V64I 0 "register_operand" "=r,b")
5285 (ior:V64I (not:V64I (match_operand:V64I 1 "register_operand" "r,b"))
5286 (match_operand:V64I 2 "register_operand" "r,b")))]
5290 fornot1\t%1, %2, %0"
5291 "&& reload_completed
5292 && ((GET_CODE (operands[0]) == REG
5293 && REGNO (operands[0]) < 32)
5294 || (GET_CODE (operands[0]) == SUBREG
5295 && GET_CODE (SUBREG_REG (operands[0])) == REG
5296 && REGNO (SUBREG_REG (operands[0])) < 32))"
5297 [(set (match_dup 3) (ior:SI (not:SI (match_dup 4)) (match_dup 5)))
5298 (set (match_dup 6) (ior:SI (not:SI (match_dup 7)) (match_dup 8)))]
5299 "operands[3] = gen_highpart (SImode, operands[0]);
5300 operands[4] = gen_highpart (SImode, operands[1]);
5301 operands[5] = gen_highpart (SImode, operands[2]);
5302 operands[6] = gen_lowpart (SImode, operands[0]);
5303 operands[7] = gen_lowpart (SImode, operands[1]);
5304 operands[8] = gen_lowpart (SImode, operands[2]);"
5305 [(set_attr "type" "*,fga")
5306 (set_attr "length" "2,*")
5307 (set_attr "fptype" "*,double")])
5309 (define_insn "*or_not_<V64I:mode>_sp64"
5310 [(set (match_operand:V64I 0 "register_operand" "=r,b")
5311 (ior:V64I (not:V64I (match_operand:V64I 1 "register_operand" "r,b"))
5312 (match_operand:V64I 2 "register_operand" "r,b")))]
5316 fornot1\t%1, %2, %0"
5317 [(set_attr "type" "*,fga")
5318 (set_attr "fptype" "*,double")])
5320 (define_insn "*or_not_<V32I:mode>"
5321 [(set (match_operand:V32I 0 "register_operand" "=r,d")
5322 (ior:V32I (not:V32I (match_operand:V32I 1 "register_operand" "r,d"))
5323 (match_operand:V32I 2 "register_operand" "r,d")))]
5327 fornot1s\t%1, %2, %0"
5328 [(set_attr "type" "*,fga")
5329 (set_attr "fptype" "*,single")])
5331 (define_expand "xor<V64I:mode>3"
5332 [(set (match_operand:V64I 0 "register_operand" "")
5333 (xor:V64I (match_operand:V64I 1 "arith_double_operand" "")
5334 (match_operand:V64I 2 "arith_double_operand" "")))]
5338 (define_insn "*xor<V64I:mode>3_sp32"
5339 [(set (match_operand:V64I 0 "register_operand" "=r,b")
5340 (xor:V64I (match_operand:V64I 1 "arith_double_operand" "%r,b")
5341 (match_operand:V64I 2 "arith_double_operand" "rHI,b")))]
5346 [(set_attr "type" "*,fga")
5347 (set_attr "length" "2,*")
5348 (set_attr "fptype" "*,double")])
5350 (define_insn "*xor<V64I:mode>3_sp64"
5351 [(set (match_operand:V64I 0 "register_operand" "=r,b")
5352 (xor:V64I (match_operand:V64I 1 "arith_operand" "%rJ,b")
5353 (match_operand:V64I 2 "arith_operand" "rI,b")))]
5358 [(set_attr "type" "*,fga")
5359 (set_attr "fptype" "*,double")])
5361 (define_insn "xor<V32I:mode>3"
5362 [(set (match_operand:V32I 0 "register_operand" "=r,d")
5363 (xor:V32I (match_operand:V32I 1 "arith_operand" "%rJ,d")
5364 (match_operand:V32I 2 "arith_operand" "rI,d")))]
5369 [(set_attr "type" "*,fga")
5370 (set_attr "fptype" "*,single")])
5373 [(set (match_operand:SI 0 "register_operand" "")
5374 (xor:SI (match_operand:SI 1 "register_operand" "")
5375 (match_operand:SI 2 "const_compl_high_operand" "")))
5376 (clobber (match_operand:SI 3 "register_operand" ""))]
5378 [(set (match_dup 3) (match_dup 4))
5379 (set (match_dup 0) (not:SI (xor:SI (match_dup 3) (match_dup 1))))]
5381 operands[4] = GEN_INT (~INTVAL (operands[2]));
5385 [(set (match_operand:SI 0 "register_operand" "")
5386 (not:SI (xor:SI (match_operand:SI 1 "register_operand" "")
5387 (match_operand:SI 2 "const_compl_high_operand" ""))))
5388 (clobber (match_operand:SI 3 "register_operand" ""))]
5390 [(set (match_dup 3) (match_dup 4))
5391 (set (match_dup 0) (xor:SI (match_dup 3) (match_dup 1)))]
5393 operands[4] = GEN_INT (~INTVAL (operands[2]));
5396 ;; Split DImode logical operations requiring two instructions.
5398 [(set (match_operand:V64I 0 "register_operand" "")
5399 (match_operator:V64I 1 "cc_arith_operator" ; AND, IOR, XOR
5400 [(match_operand:V64I 2 "register_operand" "")
5401 (match_operand:V64I 3 "arith_double_operand" "")]))]
5404 && ((GET_CODE (operands[0]) == REG
5405 && REGNO (operands[0]) < 32)
5406 || (GET_CODE (operands[0]) == SUBREG
5407 && GET_CODE (SUBREG_REG (operands[0])) == REG
5408 && REGNO (SUBREG_REG (operands[0])) < 32))"
5409 [(set (match_dup 4) (match_op_dup:SI 1 [(match_dup 6) (match_dup 8)]))
5410 (set (match_dup 5) (match_op_dup:SI 1 [(match_dup 7) (match_dup 9)]))]
5412 operands[4] = gen_highpart (SImode, operands[0]);
5413 operands[5] = gen_lowpart (SImode, operands[0]);
5414 operands[6] = gen_highpart (SImode, operands[2]);
5415 operands[7] = gen_lowpart (SImode, operands[2]);
5416 #if HOST_BITS_PER_WIDE_INT == 32
5417 if (GET_CODE (operands[3]) == CONST_INT && <V64I:MODE>mode == DImode)
5419 if (INTVAL (operands[3]) < 0)
5420 operands[8] = constm1_rtx;
5422 operands[8] = const0_rtx;
5426 operands[8] = gen_highpart_mode (SImode, <V64I:MODE>mode, operands[3]);
5427 operands[9] = gen_lowpart (SImode, operands[3]);
5430 ;; xnor patterns. Note that (a ^ ~b) == (~a ^ b) == ~(a ^ b).
5431 ;; Combine now canonicalizes to the rightmost expression.
5432 (define_insn_and_split "*xor_not_<V64I:mode>_sp32"
5433 [(set (match_operand:V64I 0 "register_operand" "=r,b")
5434 (not:V64I (xor:V64I (match_operand:V64I 1 "register_operand" "r,b")
5435 (match_operand:V64I 2 "register_operand" "r,b"))))]
5440 "&& reload_completed
5441 && ((GET_CODE (operands[0]) == REG
5442 && REGNO (operands[0]) < 32)
5443 || (GET_CODE (operands[0]) == SUBREG
5444 && GET_CODE (SUBREG_REG (operands[0])) == REG
5445 && REGNO (SUBREG_REG (operands[0])) < 32))"
5446 [(set (match_dup 3) (not:SI (xor:SI (match_dup 4) (match_dup 5))))
5447 (set (match_dup 6) (not:SI (xor:SI (match_dup 7) (match_dup 8))))]
5448 "operands[3] = gen_highpart (SImode, operands[0]);
5449 operands[4] = gen_highpart (SImode, operands[1]);
5450 operands[5] = gen_highpart (SImode, operands[2]);
5451 operands[6] = gen_lowpart (SImode, operands[0]);
5452 operands[7] = gen_lowpart (SImode, operands[1]);
5453 operands[8] = gen_lowpart (SImode, operands[2]);"
5454 [(set_attr "type" "*,fga")
5455 (set_attr "length" "2,*")
5456 (set_attr "fptype" "*,double")])
5458 (define_insn "*xor_not_<V64I:mode>_sp64"
5459 [(set (match_operand:V64I 0 "register_operand" "=r,b")
5460 (not:V64I (xor:V64I (match_operand:V64I 1 "register_or_zero_operand" "rJ,b")
5461 (match_operand:V64I 2 "arith_operand" "rI,b"))))]
5466 [(set_attr "type" "*,fga")
5467 (set_attr "fptype" "*,double")])
5469 (define_insn "*xor_not_<V32I:mode>"
5470 [(set (match_operand:V32I 0 "register_operand" "=r,d")
5471 (not:V32I (xor:V32I (match_operand:V32I 1 "register_or_zero_operand" "rJ,d")
5472 (match_operand:V32I 2 "arith_operand" "rI,d"))))]
5477 [(set_attr "type" "*,fga")
5478 (set_attr "fptype" "*,single")])
5480 ;; These correspond to the above in the case where we also (or only)
5481 ;; want to set the condition code.
5483 (define_insn "*cmp_cc_arith_op"
5486 (match_operator:SI 2 "cc_arith_operator"
5487 [(match_operand:SI 0 "arith_operand" "%r")
5488 (match_operand:SI 1 "arith_operand" "rI")])
5491 "%A2cc\t%0, %1, %%g0"
5492 [(set_attr "type" "compare")])
5494 (define_insn "*cmp_ccx_arith_op"
5497 (match_operator:DI 2 "cc_arith_operator"
5498 [(match_operand:DI 0 "arith_operand" "%r")
5499 (match_operand:DI 1 "arith_operand" "rI")])
5502 "%A2cc\t%0, %1, %%g0"
5503 [(set_attr "type" "compare")])
5505 (define_insn "*cmp_cc_arith_op_set"
5508 (match_operator:SI 3 "cc_arith_operator"
5509 [(match_operand:SI 1 "arith_operand" "%r")
5510 (match_operand:SI 2 "arith_operand" "rI")])
5512 (set (match_operand:SI 0 "register_operand" "=r")
5513 (match_operator:SI 4 "cc_arith_operator" [(match_dup 1) (match_dup 2)]))]
5514 "GET_CODE (operands[3]) == GET_CODE (operands[4])"
5516 [(set_attr "type" "compare")])
5518 (define_insn "*cmp_ccx_arith_op_set"
5521 (match_operator:DI 3 "cc_arith_operator"
5522 [(match_operand:DI 1 "arith_operand" "%r")
5523 (match_operand:DI 2 "arith_operand" "rI")])
5525 (set (match_operand:DI 0 "register_operand" "=r")
5526 (match_operator:DI 4 "cc_arith_operator" [(match_dup 1) (match_dup 2)]))]
5527 "TARGET_ARCH64 && GET_CODE (operands[3]) == GET_CODE (operands[4])"
5529 [(set_attr "type" "compare")])
5531 (define_insn "*cmp_cc_xor_not"
5534 (not:SI (xor:SI (match_operand:SI 0 "register_or_zero_operand" "%rJ")
5535 (match_operand:SI 1 "arith_operand" "rI")))
5538 "xnorcc\t%r0, %1, %%g0"
5539 [(set_attr "type" "compare")])
5541 (define_insn "*cmp_ccx_xor_not"
5544 (not:DI (xor:DI (match_operand:DI 0 "register_or_zero_operand" "%rJ")
5545 (match_operand:DI 1 "arith_operand" "rI")))
5548 "xnorcc\t%r0, %1, %%g0"
5549 [(set_attr "type" "compare")])
5551 (define_insn "*cmp_cc_xor_not_set"
5554 (not:SI (xor:SI (match_operand:SI 1 "register_or_zero_operand" "%rJ")
5555 (match_operand:SI 2 "arith_operand" "rI")))
5557 (set (match_operand:SI 0 "register_operand" "=r")
5558 (not:SI (xor:SI (match_dup 1) (match_dup 2))))]
5560 "xnorcc\t%r1, %2, %0"
5561 [(set_attr "type" "compare")])
5563 (define_insn "*cmp_ccx_xor_not_set"
5566 (not:DI (xor:DI (match_operand:DI 1 "register_or_zero_operand" "%rJ")
5567 (match_operand:DI 2 "arith_operand" "rI")))
5569 (set (match_operand:DI 0 "register_operand" "=r")
5570 (not:DI (xor:DI (match_dup 1) (match_dup 2))))]
5572 "xnorcc\t%r1, %2, %0"
5573 [(set_attr "type" "compare")])
5575 (define_insn "*cmp_cc_arith_op_not"
5578 (match_operator:SI 2 "cc_arith_not_operator"
5579 [(not:SI (match_operand:SI 0 "arith_operand" "rI"))
5580 (match_operand:SI 1 "register_or_zero_operand" "rJ")])
5583 "%B2cc\t%r1, %0, %%g0"
5584 [(set_attr "type" "compare")])
5586 (define_insn "*cmp_ccx_arith_op_not"
5589 (match_operator:DI 2 "cc_arith_not_operator"
5590 [(not:DI (match_operand:DI 0 "arith_operand" "rI"))
5591 (match_operand:DI 1 "register_or_zero_operand" "rJ")])
5594 "%B2cc\t%r1, %0, %%g0"
5595 [(set_attr "type" "compare")])
5597 (define_insn "*cmp_cc_arith_op_not_set"
5600 (match_operator:SI 3 "cc_arith_not_operator"
5601 [(not:SI (match_operand:SI 1 "arith_operand" "rI"))
5602 (match_operand:SI 2 "register_or_zero_operand" "rJ")])
5604 (set (match_operand:SI 0 "register_operand" "=r")
5605 (match_operator:SI 4 "cc_arith_not_operator"
5606 [(not:SI (match_dup 1)) (match_dup 2)]))]
5607 "GET_CODE (operands[3]) == GET_CODE (operands[4])"
5608 "%B3cc\t%r2, %1, %0"
5609 [(set_attr "type" "compare")])
5611 (define_insn "*cmp_ccx_arith_op_not_set"
5614 (match_operator:DI 3 "cc_arith_not_operator"
5615 [(not:DI (match_operand:DI 1 "arith_operand" "rI"))
5616 (match_operand:DI 2 "register_or_zero_operand" "rJ")])
5618 (set (match_operand:DI 0 "register_operand" "=r")
5619 (match_operator:DI 4 "cc_arith_not_operator"
5620 [(not:DI (match_dup 1)) (match_dup 2)]))]
5621 "TARGET_ARCH64 && GET_CODE (operands[3]) == GET_CODE (operands[4])"
5622 "%B3cc\t%r2, %1, %0"
5623 [(set_attr "type" "compare")])
5625 ;; We cannot use the "neg" pseudo insn because the Sun assembler
5626 ;; does not know how to make it work for constants.
5628 (define_expand "negdi2"
5629 [(set (match_operand:DI 0 "register_operand" "=r")
5630 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
5633 if (! TARGET_ARCH64)
5635 emit_insn (gen_rtx_PARALLEL
5638 gen_rtx_SET (VOIDmode, operand0,
5639 gen_rtx_NEG (DImode, operand1)),
5640 gen_rtx_CLOBBER (VOIDmode,
5641 gen_rtx_REG (CCmode,
5647 (define_insn_and_split "*negdi2_sp32"
5648 [(set (match_operand:DI 0 "register_operand" "=r")
5649 (neg:DI (match_operand:DI 1 "register_operand" "r")))
5650 (clobber (reg:CC 100))]
5653 "&& reload_completed"
5654 [(parallel [(set (reg:CC_NOOV 100)
5655 (compare:CC_NOOV (minus:SI (const_int 0) (match_dup 5))
5657 (set (match_dup 4) (minus:SI (const_int 0) (match_dup 5)))])
5658 (set (match_dup 2) (minus:SI (minus:SI (const_int 0) (match_dup 3))
5659 (ltu:SI (reg:CC 100) (const_int 0))))]
5660 "operands[2] = gen_highpart (SImode, operands[0]);
5661 operands[3] = gen_highpart (SImode, operands[1]);
5662 operands[4] = gen_lowpart (SImode, operands[0]);
5663 operands[5] = gen_lowpart (SImode, operands[1]);"
5664 [(set_attr "length" "2")])
5666 (define_insn "*negdi2_sp64"
5667 [(set (match_operand:DI 0 "register_operand" "=r")
5668 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
5670 "sub\t%%g0, %1, %0")
5672 (define_insn "negsi2"
5673 [(set (match_operand:SI 0 "register_operand" "=r")
5674 (neg:SI (match_operand:SI 1 "arith_operand" "rI")))]
5676 "sub\t%%g0, %1, %0")
5678 (define_insn "*cmp_cc_neg"
5679 [(set (reg:CC_NOOV 100)
5680 (compare:CC_NOOV (neg:SI (match_operand:SI 0 "arith_operand" "rI"))
5683 "subcc\t%%g0, %0, %%g0"
5684 [(set_attr "type" "compare")])
5686 (define_insn "*cmp_ccx_neg"
5687 [(set (reg:CCX_NOOV 100)
5688 (compare:CCX_NOOV (neg:DI (match_operand:DI 0 "arith_operand" "rI"))
5691 "subcc\t%%g0, %0, %%g0"
5692 [(set_attr "type" "compare")])
5694 (define_insn "*cmp_cc_set_neg"
5695 [(set (reg:CC_NOOV 100)
5696 (compare:CC_NOOV (neg:SI (match_operand:SI 1 "arith_operand" "rI"))
5698 (set (match_operand:SI 0 "register_operand" "=r")
5699 (neg:SI (match_dup 1)))]
5701 "subcc\t%%g0, %1, %0"
5702 [(set_attr "type" "compare")])
5704 (define_insn "*cmp_ccx_set_neg"
5705 [(set (reg:CCX_NOOV 100)
5706 (compare:CCX_NOOV (neg:DI (match_operand:DI 1 "arith_operand" "rI"))
5708 (set (match_operand:DI 0 "register_operand" "=r")
5709 (neg:DI (match_dup 1)))]
5711 "subcc\t%%g0, %1, %0"
5712 [(set_attr "type" "compare")])
5714 ;; We cannot use the "not" pseudo insn because the Sun assembler
5715 ;; does not know how to make it work for constants.
5716 (define_expand "one_cmpl<V64I:mode>2"
5717 [(set (match_operand:V64I 0 "register_operand" "")
5718 (not:V64I (match_operand:V64I 1 "register_operand" "")))]
5722 (define_insn_and_split "*one_cmpl<V64I:mode>2_sp32"
5723 [(set (match_operand:V64I 0 "register_operand" "=r,b")
5724 (not:V64I (match_operand:V64I 1 "register_operand" "r,b")))]
5729 "&& reload_completed
5730 && ((GET_CODE (operands[0]) == REG
5731 && REGNO (operands[0]) < 32)
5732 || (GET_CODE (operands[0]) == SUBREG
5733 && GET_CODE (SUBREG_REG (operands[0])) == REG
5734 && REGNO (SUBREG_REG (operands[0])) < 32))"
5735 [(set (match_dup 2) (not:SI (xor:SI (match_dup 3) (const_int 0))))
5736 (set (match_dup 4) (not:SI (xor:SI (match_dup 5) (const_int 0))))]
5737 "operands[2] = gen_highpart (SImode, operands[0]);
5738 operands[3] = gen_highpart (SImode, operands[1]);
5739 operands[4] = gen_lowpart (SImode, operands[0]);
5740 operands[5] = gen_lowpart (SImode, operands[1]);"
5741 [(set_attr "type" "*,fga")
5742 (set_attr "length" "2,*")
5743 (set_attr "fptype" "*,double")])
5745 (define_insn "*one_cmpl<V64I:mode>2_sp64"
5746 [(set (match_operand:V64I 0 "register_operand" "=r,b")
5747 (not:V64I (match_operand:V64I 1 "arith_operand" "rI,b")))]
5752 [(set_attr "type" "*,fga")
5753 (set_attr "fptype" "*,double")])
5755 (define_insn "one_cmpl<V32I:mode>2"
5756 [(set (match_operand:V32I 0 "register_operand" "=r,d")
5757 (not:V32I (match_operand:V32I 1 "arith_operand" "rI,d")))]
5762 [(set_attr "type" "*,fga")
5763 (set_attr "fptype" "*,single")])
5765 (define_insn "*cmp_cc_not"
5767 (compare:CC (not:SI (match_operand:SI 0 "arith_operand" "rI"))
5770 "xnorcc\t%%g0, %0, %%g0"
5771 [(set_attr "type" "compare")])
5773 (define_insn "*cmp_ccx_not"
5775 (compare:CCX (not:DI (match_operand:DI 0 "arith_operand" "rI"))
5778 "xnorcc\t%%g0, %0, %%g0"
5779 [(set_attr "type" "compare")])
5781 (define_insn "*cmp_cc_set_not"
5783 (compare:CC (not:SI (match_operand:SI 1 "arith_operand" "rI"))
5785 (set (match_operand:SI 0 "register_operand" "=r")
5786 (not:SI (match_dup 1)))]
5788 "xnorcc\t%%g0, %1, %0"
5789 [(set_attr "type" "compare")])
5791 (define_insn "*cmp_ccx_set_not"
5793 (compare:CCX (not:DI (match_operand:DI 1 "arith_operand" "rI"))
5795 (set (match_operand:DI 0 "register_operand" "=r")
5796 (not:DI (match_dup 1)))]
5798 "xnorcc\t%%g0, %1, %0"
5799 [(set_attr "type" "compare")])
5801 (define_insn "*cmp_cc_set"
5802 [(set (match_operand:SI 0 "register_operand" "=r")
5803 (match_operand:SI 1 "register_operand" "r"))
5805 (compare:CC (match_dup 1)
5809 [(set_attr "type" "compare")])
5811 (define_insn "*cmp_ccx_set64"
5812 [(set (match_operand:DI 0 "register_operand" "=r")
5813 (match_operand:DI 1 "register_operand" "r"))
5815 (compare:CCX (match_dup 1)
5819 [(set_attr "type" "compare")])
5822 ;; Floating point arithmetic instructions.
5824 (define_expand "addtf3"
5825 [(set (match_operand:TF 0 "nonimmediate_operand" "")
5826 (plus:TF (match_operand:TF 1 "general_operand" "")
5827 (match_operand:TF 2 "general_operand" "")))]
5828 "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
5829 "emit_tfmode_binop (PLUS, operands); DONE;")
5831 (define_insn "*addtf3_hq"
5832 [(set (match_operand:TF 0 "register_operand" "=e")
5833 (plus:TF (match_operand:TF 1 "register_operand" "e")
5834 (match_operand:TF 2 "register_operand" "e")))]
5835 "TARGET_FPU && TARGET_HARD_QUAD"
5837 [(set_attr "type" "fp")])
5839 (define_insn "adddf3"
5840 [(set (match_operand:DF 0 "register_operand" "=e")
5841 (plus:DF (match_operand:DF 1 "register_operand" "e")
5842 (match_operand:DF 2 "register_operand" "e")))]
5845 [(set_attr "type" "fp")
5846 (set_attr "fptype" "double")])
5848 (define_insn "addsf3"
5849 [(set (match_operand:SF 0 "register_operand" "=f")
5850 (plus:SF (match_operand:SF 1 "register_operand" "f")
5851 (match_operand:SF 2 "register_operand" "f")))]
5854 [(set_attr "type" "fp")])
5856 (define_expand "subtf3"
5857 [(set (match_operand:TF 0 "nonimmediate_operand" "")
5858 (minus:TF (match_operand:TF 1 "general_operand" "")
5859 (match_operand:TF 2 "general_operand" "")))]
5860 "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
5861 "emit_tfmode_binop (MINUS, operands); DONE;")
5863 (define_insn "*subtf3_hq"
5864 [(set (match_operand:TF 0 "register_operand" "=e")
5865 (minus:TF (match_operand:TF 1 "register_operand" "e")
5866 (match_operand:TF 2 "register_operand" "e")))]
5867 "TARGET_FPU && TARGET_HARD_QUAD"
5869 [(set_attr "type" "fp")])
5871 (define_insn "subdf3"
5872 [(set (match_operand:DF 0 "register_operand" "=e")
5873 (minus:DF (match_operand:DF 1 "register_operand" "e")
5874 (match_operand:DF 2 "register_operand" "e")))]
5877 [(set_attr "type" "fp")
5878 (set_attr "fptype" "double")])
5880 (define_insn "subsf3"
5881 [(set (match_operand:SF 0 "register_operand" "=f")
5882 (minus:SF (match_operand:SF 1 "register_operand" "f")
5883 (match_operand:SF 2 "register_operand" "f")))]
5886 [(set_attr "type" "fp")])
5888 (define_expand "multf3"
5889 [(set (match_operand:TF 0 "nonimmediate_operand" "")
5890 (mult:TF (match_operand:TF 1 "general_operand" "")
5891 (match_operand:TF 2 "general_operand" "")))]
5892 "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
5893 "emit_tfmode_binop (MULT, operands); DONE;")
5895 (define_insn "*multf3_hq"
5896 [(set (match_operand:TF 0 "register_operand" "=e")
5897 (mult:TF (match_operand:TF 1 "register_operand" "e")
5898 (match_operand:TF 2 "register_operand" "e")))]
5899 "TARGET_FPU && TARGET_HARD_QUAD"
5901 [(set_attr "type" "fpmul")])
5903 (define_insn "muldf3"
5904 [(set (match_operand:DF 0 "register_operand" "=e")
5905 (mult:DF (match_operand:DF 1 "register_operand" "e")
5906 (match_operand:DF 2 "register_operand" "e")))]
5909 [(set_attr "type" "fpmul")
5910 (set_attr "fptype" "double")])
5912 (define_insn "mulsf3"
5913 [(set (match_operand:SF 0 "register_operand" "=f")
5914 (mult:SF (match_operand:SF 1 "register_operand" "f")
5915 (match_operand:SF 2 "register_operand" "f")))]
5918 [(set_attr "type" "fpmul")])
5920 (define_insn "*muldf3_extend"
5921 [(set (match_operand:DF 0 "register_operand" "=e")
5922 (mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "f"))
5923 (float_extend:DF (match_operand:SF 2 "register_operand" "f"))))]
5924 "(TARGET_V8 || TARGET_V9) && TARGET_FPU"
5925 "fsmuld\t%1, %2, %0"
5926 [(set_attr "type" "fpmul")
5927 (set_attr "fptype" "double")])
5929 (define_insn "*multf3_extend"
5930 [(set (match_operand:TF 0 "register_operand" "=e")
5931 (mult:TF (float_extend:TF (match_operand:DF 1 "register_operand" "e"))
5932 (float_extend:TF (match_operand:DF 2 "register_operand" "e"))))]
5933 "(TARGET_V8 || TARGET_V9) && TARGET_FPU && TARGET_HARD_QUAD"
5934 "fdmulq\t%1, %2, %0"
5935 [(set_attr "type" "fpmul")])
5937 (define_expand "divtf3"
5938 [(set (match_operand:TF 0 "nonimmediate_operand" "")
5939 (div:TF (match_operand:TF 1 "general_operand" "")
5940 (match_operand:TF 2 "general_operand" "")))]
5941 "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
5942 "emit_tfmode_binop (DIV, operands); DONE;")
5944 ;; don't have timing for quad-prec. divide.
5945 (define_insn "*divtf3_hq"
5946 [(set (match_operand:TF 0 "register_operand" "=e")
5947 (div:TF (match_operand:TF 1 "register_operand" "e")
5948 (match_operand:TF 2 "register_operand" "e")))]
5949 "TARGET_FPU && TARGET_HARD_QUAD"
5951 [(set_attr "type" "fpdivd")])
5953 (define_insn "divdf3"
5954 [(set (match_operand:DF 0 "register_operand" "=e")
5955 (div:DF (match_operand:DF 1 "register_operand" "e")
5956 (match_operand:DF 2 "register_operand" "e")))]
5959 [(set_attr "type" "fpdivd")
5960 (set_attr "fptype" "double")])
5962 (define_insn "divsf3"
5963 [(set (match_operand:SF 0 "register_operand" "=f")
5964 (div:SF (match_operand:SF 1 "register_operand" "f")
5965 (match_operand:SF 2 "register_operand" "f")))]
5968 [(set_attr "type" "fpdivs")])
5970 (define_expand "negtf2"
5971 [(set (match_operand:TF 0 "register_operand" "=e,e")
5972 (neg:TF (match_operand:TF 1 "register_operand" "0,e")))]
5976 (define_insn_and_split "*negtf2_notv9"
5977 [(set (match_operand:TF 0 "register_operand" "=e,e")
5978 (neg:TF (match_operand:TF 1 "register_operand" "0,e")))]
5979 ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD.
5985 "&& reload_completed
5986 && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
5987 [(set (match_dup 2) (neg:SF (match_dup 3)))
5988 (set (match_dup 4) (match_dup 5))
5989 (set (match_dup 6) (match_dup 7))]
5990 "operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
5991 operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
5992 operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
5993 operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);
5994 operands[6] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2);
5995 operands[7] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);"
5996 [(set_attr "type" "fpmove,*")
5997 (set_attr "length" "*,2")])
5999 (define_insn_and_split "*negtf2_v9"
6000 [(set (match_operand:TF 0 "register_operand" "=e,e")
6001 (neg:TF (match_operand:TF 1 "register_operand" "0,e")))]
6002 ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD.
6003 "TARGET_FPU && TARGET_V9"
6007 "&& reload_completed
6008 && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
6009 [(set (match_dup 2) (neg:DF (match_dup 3)))
6010 (set (match_dup 4) (match_dup 5))]
6011 "operands[2] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]));
6012 operands[3] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]));
6013 operands[4] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2);
6014 operands[5] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);"
6015 [(set_attr "type" "fpmove,*")
6016 (set_attr "length" "*,2")
6017 (set_attr "fptype" "double")])
6019 (define_expand "negdf2"
6020 [(set (match_operand:DF 0 "register_operand" "")
6021 (neg:DF (match_operand:DF 1 "register_operand" "")))]
6025 (define_insn_and_split "*negdf2_notv9"
6026 [(set (match_operand:DF 0 "register_operand" "=e,e")
6027 (neg:DF (match_operand:DF 1 "register_operand" "0,e")))]
6028 "TARGET_FPU && ! TARGET_V9"
6032 "&& reload_completed
6033 && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
6034 [(set (match_dup 2) (neg:SF (match_dup 3)))
6035 (set (match_dup 4) (match_dup 5))]
6036 "operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
6037 operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
6038 operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
6039 operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);"
6040 [(set_attr "type" "fpmove,*")
6041 (set_attr "length" "*,2")])
6043 (define_insn "*negdf2_v9"
6044 [(set (match_operand:DF 0 "register_operand" "=e")
6045 (neg:DF (match_operand:DF 1 "register_operand" "e")))]
6046 "TARGET_FPU && TARGET_V9"
6048 [(set_attr "type" "fpmove")
6049 (set_attr "fptype" "double")])
6051 (define_insn "negsf2"
6052 [(set (match_operand:SF 0 "register_operand" "=f")
6053 (neg:SF (match_operand:SF 1 "register_operand" "f")))]
6056 [(set_attr "type" "fpmove")])
6058 (define_expand "abstf2"
6059 [(set (match_operand:TF 0 "register_operand" "")
6060 (abs:TF (match_operand:TF 1 "register_operand" "")))]
6064 (define_insn_and_split "*abstf2_notv9"
6065 [(set (match_operand:TF 0 "register_operand" "=e,e")
6066 (abs:TF (match_operand:TF 1 "register_operand" "0,e")))]
6067 ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD.
6068 "TARGET_FPU && ! TARGET_V9"
6072 "&& reload_completed
6073 && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
6074 [(set (match_dup 2) (abs:SF (match_dup 3)))
6075 (set (match_dup 4) (match_dup 5))
6076 (set (match_dup 6) (match_dup 7))]
6077 "operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
6078 operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
6079 operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
6080 operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);
6081 operands[6] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2);
6082 operands[7] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);"
6083 [(set_attr "type" "fpmove,*")
6084 (set_attr "length" "*,2")])
6086 (define_insn "*abstf2_hq_v9"
6087 [(set (match_operand:TF 0 "register_operand" "=e,e")
6088 (abs:TF (match_operand:TF 1 "register_operand" "0,e")))]
6089 "TARGET_FPU && TARGET_V9 && TARGET_HARD_QUAD"
6093 [(set_attr "type" "fpmove")
6094 (set_attr "fptype" "double,*")])
6096 (define_insn_and_split "*abstf2_v9"
6097 [(set (match_operand:TF 0 "register_operand" "=e,e")
6098 (abs:TF (match_operand:TF 1 "register_operand" "0,e")))]
6099 "TARGET_FPU && TARGET_V9 && !TARGET_HARD_QUAD"
6103 "&& reload_completed
6104 && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
6105 [(set (match_dup 2) (abs:DF (match_dup 3)))
6106 (set (match_dup 4) (match_dup 5))]
6107 "operands[2] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]));
6108 operands[3] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]));
6109 operands[4] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2);
6110 operands[5] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);"
6111 [(set_attr "type" "fpmove,*")
6112 (set_attr "length" "*,2")
6113 (set_attr "fptype" "double,*")])
6115 (define_expand "absdf2"
6116 [(set (match_operand:DF 0 "register_operand" "")
6117 (abs:DF (match_operand:DF 1 "register_operand" "")))]
6121 (define_insn_and_split "*absdf2_notv9"
6122 [(set (match_operand:DF 0 "register_operand" "=e,e")
6123 (abs:DF (match_operand:DF 1 "register_operand" "0,e")))]
6124 "TARGET_FPU && ! TARGET_V9"
6128 "&& reload_completed
6129 && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
6130 [(set (match_dup 2) (abs:SF (match_dup 3)))
6131 (set (match_dup 4) (match_dup 5))]
6132 "operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
6133 operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
6134 operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
6135 operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);"
6136 [(set_attr "type" "fpmove,*")
6137 (set_attr "length" "*,2")])
6139 (define_insn "*absdf2_v9"
6140 [(set (match_operand:DF 0 "register_operand" "=e")
6141 (abs:DF (match_operand:DF 1 "register_operand" "e")))]
6142 "TARGET_FPU && TARGET_V9"
6144 [(set_attr "type" "fpmove")
6145 (set_attr "fptype" "double")])
6147 (define_insn "abssf2"
6148 [(set (match_operand:SF 0 "register_operand" "=f")
6149 (abs:SF (match_operand:SF 1 "register_operand" "f")))]
6152 [(set_attr "type" "fpmove")])
6154 (define_expand "sqrttf2"
6155 [(set (match_operand:TF 0 "nonimmediate_operand" "")
6156 (sqrt:TF (match_operand:TF 1 "general_operand" "")))]
6157 "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
6158 "emit_tfmode_unop (SQRT, operands); DONE;")
6160 (define_insn "*sqrttf2_hq"
6161 [(set (match_operand:TF 0 "register_operand" "=e")
6162 (sqrt:TF (match_operand:TF 1 "register_operand" "e")))]
6163 "TARGET_FPU && TARGET_HARD_QUAD"
6165 [(set_attr "type" "fpsqrtd")])
6167 (define_insn "sqrtdf2"
6168 [(set (match_operand:DF 0 "register_operand" "=e")
6169 (sqrt:DF (match_operand:DF 1 "register_operand" "e")))]
6172 [(set_attr "type" "fpsqrtd")
6173 (set_attr "fptype" "double")])
6175 (define_insn "sqrtsf2"
6176 [(set (match_operand:SF 0 "register_operand" "=f")
6177 (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
6180 [(set_attr "type" "fpsqrts")])
6183 ;; Arithmetic shift instructions.
6185 (define_insn "ashlsi3"
6186 [(set (match_operand:SI 0 "register_operand" "=r")
6187 (ashift:SI (match_operand:SI 1 "register_operand" "r")
6188 (match_operand:SI 2 "arith_operand" "rI")))]
6191 if (GET_CODE (operands[2]) == CONST_INT)
6192 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
6193 return "sll\t%1, %2, %0";
6196 (if_then_else (match_operand 2 "const_one_operand" "")
6197 (const_string "ialu") (const_string "shift")))])
6199 (define_expand "ashldi3"
6200 [(set (match_operand:DI 0 "register_operand" "=r")
6201 (ashift:DI (match_operand:DI 1 "register_operand" "r")
6202 (match_operand:SI 2 "arith_operand" "rI")))]
6203 "TARGET_ARCH64 || TARGET_V8PLUS"
6205 if (! TARGET_ARCH64)
6207 if (GET_CODE (operands[2]) == CONST_INT)
6209 emit_insn (gen_ashldi3_v8plus (operands[0], operands[1], operands[2]));
6214 (define_insn "*ashldi3_sp64"
6215 [(set (match_operand:DI 0 "register_operand" "=r")
6216 (ashift:DI (match_operand:DI 1 "register_operand" "r")
6217 (match_operand:SI 2 "arith_operand" "rI")))]
6220 if (GET_CODE (operands[2]) == CONST_INT)
6221 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
6222 return "sllx\t%1, %2, %0";
6225 (if_then_else (match_operand 2 "const_one_operand" "")
6226 (const_string "ialu") (const_string "shift")))])
6229 (define_insn "ashldi3_v8plus"
6230 [(set (match_operand:DI 0 "register_operand" "=&h,&h,r")
6231 (ashift:DI (match_operand:DI 1 "arith_operand" "rI,0,rI")
6232 (match_operand:SI 2 "arith_operand" "rI,rI,rI")))
6233 (clobber (match_scratch:SI 3 "=X,X,&h"))]
6235 "* return output_v8plus_shift (operands, insn, \"sllx\");"
6236 [(set_attr "type" "multi")
6237 (set_attr "length" "5,5,6")])
6239 ;; Optimize (1LL<<x)-1
6240 ;; XXX this also needs to be fixed to handle equal subregs
6241 ;; XXX first before we could re-enable it.
6243 ; [(set (match_operand:DI 0 "register_operand" "=h")
6244 ; (plus:DI (ashift:DI (const_int 1)
6245 ; (match_operand:SI 1 "arith_operand" "rI"))
6247 ; "0 && TARGET_V8PLUS"
6249 ; if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == REGNO (operands[0]))
6250 ; return "mov\t1, %L0\;sllx\t%L0, %1, %L0\;sub\t%L0, 1, %L0\;srlx\t%L0, 32, %H0";
6251 ; return "mov\t1, %H0\;sllx\t%H0, %1, %L0\;sub\t%L0, 1, %L0\;srlx\t%L0, 32, %H0";
6253 ; [(set_attr "type" "multi")
6254 ; (set_attr "length" "4")])
6256 (define_insn "*cmp_cc_ashift_1"
6257 [(set (reg:CC_NOOV 100)
6258 (compare:CC_NOOV (ashift:SI (match_operand:SI 0 "register_operand" "r")
6262 "addcc\t%0, %0, %%g0"
6263 [(set_attr "type" "compare")])
6265 (define_insn "*cmp_cc_set_ashift_1"
6266 [(set (reg:CC_NOOV 100)
6267 (compare:CC_NOOV (ashift:SI (match_operand:SI 1 "register_operand" "r")
6270 (set (match_operand:SI 0 "register_operand" "=r")
6271 (ashift:SI (match_dup 1) (const_int 1)))]
6274 [(set_attr "type" "compare")])
6276 (define_insn "ashrsi3"
6277 [(set (match_operand:SI 0 "register_operand" "=r")
6278 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
6279 (match_operand:SI 2 "arith_operand" "rI")))]
6282 if (GET_CODE (operands[2]) == CONST_INT)
6283 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
6284 return "sra\t%1, %2, %0";
6286 [(set_attr "type" "shift")])
6288 (define_insn "*ashrsi3_extend"
6289 [(set (match_operand:DI 0 "register_operand" "=r")
6290 (sign_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
6291 (match_operand:SI 2 "arith_operand" "r"))))]
6294 [(set_attr "type" "shift")])
6296 ;; This handles the case as above, but with constant shift instead of
6297 ;; register. Combiner "simplifies" it for us a little bit though.
6298 (define_insn "*ashrsi3_extend2"
6299 [(set (match_operand:DI 0 "register_operand" "=r")
6300 (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 1 "register_operand" "r") 0)
6302 (match_operand:SI 2 "small_int_operand" "I")))]
6303 "TARGET_ARCH64 && INTVAL (operands[2]) >= 32 && INTVAL (operands[2]) < 64"
6305 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
6306 return "sra\t%1, %2, %0";
6308 [(set_attr "type" "shift")])
6310 (define_expand "ashrdi3"
6311 [(set (match_operand:DI 0 "register_operand" "=r")
6312 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
6313 (match_operand:SI 2 "arith_operand" "rI")))]
6314 "TARGET_ARCH64 || TARGET_V8PLUS"
6316 if (! TARGET_ARCH64)
6318 if (GET_CODE (operands[2]) == CONST_INT)
6319 FAIL; /* prefer generic code in this case */
6320 emit_insn (gen_ashrdi3_v8plus (operands[0], operands[1], operands[2]));
6325 (define_insn "*ashrdi3_sp64"
6326 [(set (match_operand:DI 0 "register_operand" "=r")
6327 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
6328 (match_operand:SI 2 "arith_operand" "rI")))]
6332 if (GET_CODE (operands[2]) == CONST_INT)
6333 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
6334 return "srax\t%1, %2, %0";
6336 [(set_attr "type" "shift")])
6339 (define_insn "ashrdi3_v8plus"
6340 [(set (match_operand:DI 0 "register_operand" "=&h,&h,r")
6341 (ashiftrt:DI (match_operand:DI 1 "arith_operand" "rI,0,rI")
6342 (match_operand:SI 2 "arith_operand" "rI,rI,rI")))
6343 (clobber (match_scratch:SI 3 "=X,X,&h"))]
6345 "* return output_v8plus_shift (operands, insn, \"srax\");"
6346 [(set_attr "type" "multi")
6347 (set_attr "length" "5,5,6")])
6349 (define_insn "lshrsi3"
6350 [(set (match_operand:SI 0 "register_operand" "=r")
6351 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
6352 (match_operand:SI 2 "arith_operand" "rI")))]
6355 if (GET_CODE (operands[2]) == CONST_INT)
6356 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
6357 return "srl\t%1, %2, %0";
6359 [(set_attr "type" "shift")])
6361 ;; This handles the case where
6362 ;; (zero_extend:DI (lshiftrt:SI (match_operand:SI) (match_operand:SI))),
6363 ;; but combiner "simplifies" it for us.
6364 (define_insn "*lshrsi3_extend"
6365 [(set (match_operand:DI 0 "register_operand" "=r")
6366 (and:DI (subreg:DI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
6367 (match_operand:SI 2 "arith_operand" "r")) 0)
6368 (match_operand 3 "const_int_operand" "")))]
6369 "TARGET_ARCH64 && (unsigned HOST_WIDE_INT) INTVAL (operands[3]) == 0xffffffff"
6371 [(set_attr "type" "shift")])
6373 ;; This handles the case where
6374 ;; (lshiftrt:DI (zero_extend:DI (match_operand:SI)) (const_int >=0 < 32))
6375 ;; but combiner "simplifies" it for us.
6376 (define_insn "*lshrsi3_extend2"
6377 [(set (match_operand:DI 0 "register_operand" "=r")
6378 (zero_extract:DI (subreg:DI (match_operand:SI 1 "register_operand" "r") 0)
6379 (match_operand 2 "small_int_operand" "I")
6381 "TARGET_ARCH64 && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 32"
6383 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
6384 return "srl\t%1, %2, %0";
6386 [(set_attr "type" "shift")])
6388 (define_expand "lshrdi3"
6389 [(set (match_operand:DI 0 "register_operand" "=r")
6390 (lshiftrt:DI (match_operand:DI 1 "register_operand" "r")
6391 (match_operand:SI 2 "arith_operand" "rI")))]
6392 "TARGET_ARCH64 || TARGET_V8PLUS"
6394 if (! TARGET_ARCH64)
6396 if (GET_CODE (operands[2]) == CONST_INT)
6398 emit_insn (gen_lshrdi3_v8plus (operands[0], operands[1], operands[2]));
6403 (define_insn "*lshrdi3_sp64"
6404 [(set (match_operand:DI 0 "register_operand" "=r")
6405 (lshiftrt:DI (match_operand:DI 1 "register_operand" "r")
6406 (match_operand:SI 2 "arith_operand" "rI")))]
6409 if (GET_CODE (operands[2]) == CONST_INT)
6410 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
6411 return "srlx\t%1, %2, %0";
6413 [(set_attr "type" "shift")])
6416 (define_insn "lshrdi3_v8plus"
6417 [(set (match_operand:DI 0 "register_operand" "=&h,&h,r")
6418 (lshiftrt:DI (match_operand:DI 1 "arith_operand" "rI,0,rI")
6419 (match_operand:SI 2 "arith_operand" "rI,rI,rI")))
6420 (clobber (match_scratch:SI 3 "=X,X,&h"))]
6422 "* return output_v8plus_shift (operands, insn, \"srlx\");"
6423 [(set_attr "type" "multi")
6424 (set_attr "length" "5,5,6")])
6427 [(set (match_operand:SI 0 "register_operand" "=r")
6428 (ashiftrt:SI (subreg:SI (lshiftrt:DI (match_operand:DI 1 "register_operand" "r")
6430 (match_operand:SI 2 "small_int_operand" "I")))]
6431 "TARGET_ARCH64 && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 32"
6433 operands[2] = GEN_INT (INTVAL (operands[2]) + 32);
6434 return "srax\t%1, %2, %0";
6436 [(set_attr "type" "shift")])
6439 [(set (match_operand:SI 0 "register_operand" "=r")
6440 (lshiftrt:SI (subreg:SI (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
6442 (match_operand:SI 2 "small_int_operand" "I")))]
6443 "TARGET_ARCH64 && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 32"
6445 operands[2] = GEN_INT (INTVAL (operands[2]) + 32);
6446 return "srlx\t%1, %2, %0";
6448 [(set_attr "type" "shift")])
6451 [(set (match_operand:SI 0 "register_operand" "=r")
6452 (ashiftrt:SI (subreg:SI (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
6453 (match_operand:SI 2 "small_int_operand" "I")) 4)
6454 (match_operand:SI 3 "small_int_operand" "I")))]
6456 && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) >= 32
6457 && (unsigned HOST_WIDE_INT) INTVAL (operands[3]) < 32
6458 && (unsigned HOST_WIDE_INT) (INTVAL (operands[2]) + INTVAL (operands[3])) < 64"
6460 operands[2] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[3]));
6462 return "srax\t%1, %2, %0";
6464 [(set_attr "type" "shift")])
6467 [(set (match_operand:SI 0 "register_operand" "=r")
6468 (lshiftrt:SI (subreg:SI (lshiftrt:DI (match_operand:DI 1 "register_operand" "r")
6469 (match_operand:SI 2 "small_int_operand" "I")) 4)
6470 (match_operand:SI 3 "small_int_operand" "I")))]
6472 && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) >= 32
6473 && (unsigned HOST_WIDE_INT) INTVAL (operands[3]) < 32
6474 && (unsigned HOST_WIDE_INT) (INTVAL (operands[2]) + INTVAL (operands[3])) < 64"
6476 operands[2] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[3]));
6478 return "srlx\t%1, %2, %0";
6480 [(set_attr "type" "shift")])
6483 ;; Unconditional and other jump instructions.
6486 [(set (pc) (label_ref (match_operand 0 "" "")))]
6488 "* return output_ubranch (operands[0], 0, insn);"
6489 [(set_attr "type" "uncond_branch")])
6491 (define_expand "tablejump"
6492 [(parallel [(set (pc) (match_operand 0 "register_operand" "r"))
6493 (use (label_ref (match_operand 1 "" "")))])]
6496 gcc_assert (GET_MODE (operands[0]) == CASE_VECTOR_MODE);
6498 /* In pic mode, our address differences are against the base of the
6499 table. Add that base value back in; CSE ought to be able to combine
6500 the two address loads. */
6504 tmp = gen_rtx_LABEL_REF (Pmode, operands[1]);
6506 if (CASE_VECTOR_MODE != Pmode)
6507 tmp2 = gen_rtx_SIGN_EXTEND (Pmode, tmp2);
6508 tmp = gen_rtx_PLUS (Pmode, tmp2, tmp);
6509 operands[0] = memory_address (Pmode, tmp);
6513 (define_insn "*tablejump_sp32"
6514 [(set (pc) (match_operand:SI 0 "address_operand" "p"))
6515 (use (label_ref (match_operand 1 "" "")))]
6518 [(set_attr "type" "uncond_branch")])
6520 (define_insn "*tablejump_sp64"
6521 [(set (pc) (match_operand:DI 0 "address_operand" "p"))
6522 (use (label_ref (match_operand 1 "" "")))]
6525 [(set_attr "type" "uncond_branch")])
6528 ;; Jump to subroutine instructions.
6530 (define_expand "call"
6531 ;; Note that this expression is not used for generating RTL.
6532 ;; All the RTL is generated explicitly below.
6533 [(call (match_operand 0 "call_operand" "")
6534 (match_operand 3 "" "i"))]
6535 ;; operands[2] is next_arg_register
6536 ;; operands[3] is struct_value_size_rtx.
6541 gcc_assert (MEM_P (operands[0]) && GET_MODE (operands[0]) == FUNCTION_MODE);
6543 gcc_assert (GET_CODE (operands[3]) == CONST_INT);
6545 if (GET_CODE (XEXP (operands[0], 0)) == LABEL_REF)
6547 /* This is really a PIC sequence. We want to represent
6548 it as a funny jump so its delay slots can be filled.
6550 ??? But if this really *is* a CALL, will not it clobber the
6551 call-clobbered registers? We lose this if it is a JUMP_INSN.
6552 Why cannot we have delay slots filled if it were a CALL? */
6554 /* We accept negative sizes for untyped calls. */
6555 if (! TARGET_ARCH64 && INTVAL (operands[3]) != 0)
6560 gen_rtx_SET (VOIDmode, pc_rtx, XEXP (operands[0], 0)),
6562 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 15)))));
6568 gen_rtx_SET (VOIDmode, pc_rtx, XEXP (operands[0], 0)),
6569 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 15)))));
6573 fn_rtx = operands[0];
6575 /* We accept negative sizes for untyped calls. */
6576 if (! TARGET_ARCH64 && INTVAL (operands[3]) != 0)
6577 sparc_emit_call_insn
6580 gen_rtvec (3, gen_rtx_CALL (VOIDmode, fn_rtx, const0_rtx),
6582 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 15)))),
6585 sparc_emit_call_insn
6588 gen_rtvec (2, gen_rtx_CALL (VOIDmode, fn_rtx, const0_rtx),
6589 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 15)))),
6597 ;; We can't use the same pattern for these two insns, because then registers
6598 ;; in the address may not be properly reloaded.
6600 (define_insn "*call_address_sp32"
6601 [(call (mem:SI (match_operand:SI 0 "address_operand" "p"))
6602 (match_operand 1 "" ""))
6603 (clobber (reg:SI 15))]
6604 ;;- Do not use operand 1 for most machines.
6607 [(set_attr "type" "call")])
6609 (define_insn "*call_symbolic_sp32"
6610 [(call (mem:SI (match_operand:SI 0 "symbolic_operand" "s"))
6611 (match_operand 1 "" ""))
6612 (clobber (reg:SI 15))]
6613 ;;- Do not use operand 1 for most machines.
6616 [(set_attr "type" "call")])
6618 (define_insn "*call_address_sp64"
6619 [(call (mem:DI (match_operand:DI 0 "address_operand" "p"))
6620 (match_operand 1 "" ""))
6621 (clobber (reg:DI 15))]
6622 ;;- Do not use operand 1 for most machines.
6625 [(set_attr "type" "call")])
6627 (define_insn "*call_symbolic_sp64"
6628 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "s"))
6629 (match_operand 1 "" ""))
6630 (clobber (reg:DI 15))]
6631 ;;- Do not use operand 1 for most machines.
6634 [(set_attr "type" "call")])
6636 ;; This is a call that wants a structure value.
6637 ;; There is no such critter for v9 (??? we may need one anyway).
6638 (define_insn "*call_address_struct_value_sp32"
6639 [(call (mem:SI (match_operand:SI 0 "address_operand" "p"))
6640 (match_operand 1 "" ""))
6641 (match_operand 2 "immediate_operand" "")
6642 (clobber (reg:SI 15))]
6643 ;;- Do not use operand 1 for most machines.
6644 "! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) > 0"
6646 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xfff);
6647 return "call\t%a0, %1\n\t nop\n\tunimp\t%2";
6649 [(set_attr "type" "call_no_delay_slot")
6650 (set_attr "length" "3")])
6652 ;; This is a call that wants a structure value.
6653 ;; There is no such critter for v9 (??? we may need one anyway).
6654 (define_insn "*call_symbolic_struct_value_sp32"
6655 [(call (mem:SI (match_operand:SI 0 "symbolic_operand" "s"))
6656 (match_operand 1 "" ""))
6657 (match_operand 2 "immediate_operand" "")
6658 (clobber (reg:SI 15))]
6659 ;;- Do not use operand 1 for most machines.
6660 "! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) > 0"
6662 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xfff);
6663 return "call\t%a0, %1\n\t nop\n\tunimp\t%2";
6665 [(set_attr "type" "call_no_delay_slot")
6666 (set_attr "length" "3")])
6668 ;; This is a call that may want a structure value. This is used for
6670 (define_insn "*call_address_untyped_struct_value_sp32"
6671 [(call (mem:SI (match_operand:SI 0 "address_operand" "p"))
6672 (match_operand 1 "" ""))
6673 (match_operand 2 "immediate_operand" "")
6674 (clobber (reg:SI 15))]
6675 ;;- Do not use operand 1 for most machines.
6676 "! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0"
6677 "call\t%a0, %1\n\t nop\n\tnop"
6678 [(set_attr "type" "call_no_delay_slot")
6679 (set_attr "length" "3")])
6681 ;; This is a call that may want a structure value. This is used for
6683 (define_insn "*call_symbolic_untyped_struct_value_sp32"
6684 [(call (mem:SI (match_operand:SI 0 "symbolic_operand" "s"))
6685 (match_operand 1 "" ""))
6686 (match_operand 2 "immediate_operand" "")
6687 (clobber (reg:SI 15))]
6688 ;;- Do not use operand 1 for most machines.
6689 "! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0"
6690 "call\t%a0, %1\n\t nop\n\tnop"
6691 [(set_attr "type" "call_no_delay_slot")
6692 (set_attr "length" "3")])
6694 (define_expand "call_value"
6695 ;; Note that this expression is not used for generating RTL.
6696 ;; All the RTL is generated explicitly below.
6697 [(set (match_operand 0 "register_operand" "=rf")
6698 (call (match_operand 1 "" "")
6699 (match_operand 4 "" "")))]
6700 ;; operand 2 is stack_size_rtx
6701 ;; operand 3 is next_arg_register
6707 gcc_assert (MEM_P (operands[1]) && GET_MODE (operands[1]) == FUNCTION_MODE);
6709 fn_rtx = operands[1];
6712 gen_rtx_SET (VOIDmode, operands[0],
6713 gen_rtx_CALL (VOIDmode, fn_rtx, const0_rtx)),
6714 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 15)));
6716 sparc_emit_call_insn (gen_rtx_PARALLEL (VOIDmode, vec), XEXP (fn_rtx, 0));
6721 (define_insn "*call_value_address_sp32"
6722 [(set (match_operand 0 "" "=rf")
6723 (call (mem:SI (match_operand:SI 1 "address_operand" "p"))
6724 (match_operand 2 "" "")))
6725 (clobber (reg:SI 15))]
6726 ;;- Do not use operand 2 for most machines.
6729 [(set_attr "type" "call")])
6731 (define_insn "*call_value_symbolic_sp32"
6732 [(set (match_operand 0 "" "=rf")
6733 (call (mem:SI (match_operand:SI 1 "symbolic_operand" "s"))
6734 (match_operand 2 "" "")))
6735 (clobber (reg:SI 15))]
6736 ;;- Do not use operand 2 for most machines.
6739 [(set_attr "type" "call")])
6741 (define_insn "*call_value_address_sp64"
6742 [(set (match_operand 0 "" "")
6743 (call (mem:DI (match_operand:DI 1 "address_operand" "p"))
6744 (match_operand 2 "" "")))
6745 (clobber (reg:DI 15))]
6746 ;;- Do not use operand 2 for most machines.
6749 [(set_attr "type" "call")])
6751 (define_insn "*call_value_symbolic_sp64"
6752 [(set (match_operand 0 "" "")
6753 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "s"))
6754 (match_operand 2 "" "")))
6755 (clobber (reg:DI 15))]
6756 ;;- Do not use operand 2 for most machines.
6759 [(set_attr "type" "call")])
6761 (define_expand "untyped_call"
6762 [(parallel [(call (match_operand 0 "" "")
6764 (match_operand:BLK 1 "memory_operand" "")
6765 (match_operand 2 "" "")])]
6768 rtx valreg1 = gen_rtx_REG (DImode, 8);
6769 rtx valreg2 = gen_rtx_REG (TARGET_ARCH64 ? TFmode : DFmode, 32);
6770 rtx result = operands[1];
6772 /* Pass constm1 to indicate that it may expect a structure value, but
6773 we don't know what size it is. */
6774 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, constm1_rtx));
6776 /* Save the function value registers. */
6777 emit_move_insn (adjust_address (result, DImode, 0), valreg1);
6778 emit_move_insn (adjust_address (result, TARGET_ARCH64 ? TFmode : DFmode, 8),
6781 /* The optimizer does not know that the call sets the function value
6782 registers we stored in the result block. We avoid problems by
6783 claiming that all hard registers are used and clobbered at this
6785 emit_insn (gen_blockage ());
6790 ;; Tail call instructions.
6792 (define_expand "sibcall"
6793 [(parallel [(call (match_operand 0 "call_operand" "") (const_int 0))
6798 (define_insn "*sibcall_symbolic_sp32"
6799 [(call (mem:SI (match_operand:SI 0 "symbolic_operand" "s"))
6800 (match_operand 1 "" ""))
6803 "* return output_sibcall(insn, operands[0]);"
6804 [(set_attr "type" "sibcall")])
6806 (define_insn "*sibcall_symbolic_sp64"
6807 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "s"))
6808 (match_operand 1 "" ""))
6811 "* return output_sibcall(insn, operands[0]);"
6812 [(set_attr "type" "sibcall")])
6814 (define_expand "sibcall_value"
6815 [(parallel [(set (match_operand 0 "register_operand" "=rf")
6816 (call (match_operand 1 "" "") (const_int 0)))
6821 (define_insn "*sibcall_value_symbolic_sp32"
6822 [(set (match_operand 0 "" "=rf")
6823 (call (mem:SI (match_operand:SI 1 "symbolic_operand" "s"))
6824 (match_operand 2 "" "")))
6827 "* return output_sibcall(insn, operands[1]);"
6828 [(set_attr "type" "sibcall")])
6830 (define_insn "*sibcall_value_symbolic_sp64"
6831 [(set (match_operand 0 "" "")
6832 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "s"))
6833 (match_operand 2 "" "")))
6836 "* return output_sibcall(insn, operands[1]);"
6837 [(set_attr "type" "sibcall")])
6840 ;; Special instructions.
6842 (define_expand "prologue"
6846 sparc_expand_prologue ();
6850 ;; The "save register window" insn is modelled as follows so that the DWARF-2
6851 ;; backend automatically emits the required call frame debugging information
6852 ;; while it is parsing it. Therefore, the pattern should not be modified
6853 ;; without first studying the impact of the changes on the debug info.
6854 ;; [(set (%fp) (%sp))
6855 ;; (set (%sp) (unspec_volatile [(%sp) (-frame_size)] UNSPECV_SAVEW))
6856 ;; (set (%i7) (%o7))]
6858 (define_insn "save_register_window<P:mode>"
6859 [(set (reg:P 30) (reg:P 14))
6860 (set (reg:P 14) (unspec_volatile:P [(reg:P 14)
6861 (match_operand:P 0 "arith_operand" "rI")] UNSPECV_SAVEW))
6862 (set (reg:P 31) (reg:P 15))]
6864 "save\t%%sp, %0, %%sp"
6865 [(set_attr "type" "savew")])
6867 (define_expand "epilogue"
6871 sparc_expand_epilogue ();
6874 (define_expand "sibcall_epilogue"
6878 sparc_expand_epilogue ();
6882 (define_expand "return"
6884 "sparc_can_use_return_insn_p ()"
6887 (define_insn "*return_internal"
6890 "* return output_return (insn);"
6891 [(set_attr "type" "return")
6892 (set (attr "length")
6893 (cond [(eq_attr "leaf_function" "true")
6894 (if_then_else (eq_attr "empty_delay_slot" "true")
6897 (eq_attr "calls_eh_return" "true")
6898 (if_then_else (eq_attr "delayed_branch" "true")
6899 (if_then_else (eq_attr "isa" "v9")
6902 (if_then_else (eq_attr "isa" "v9")
6905 (eq_attr "empty_delay_slot" "true")
6906 (if_then_else (eq_attr "delayed_branch" "true")
6911 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6912 ;; all of memory. This blocks insns from being moved across this point.
6914 (define_insn "blockage"
6915 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
6918 [(set_attr "length" "0")])
6920 ;; Prepare to return any type including a structure value.
6922 (define_expand "untyped_return"
6923 [(match_operand:BLK 0 "memory_operand" "")
6924 (match_operand 1 "" "")]
6927 rtx valreg1 = gen_rtx_REG (DImode, 24);
6928 rtx valreg2 = gen_rtx_REG (TARGET_ARCH64 ? TFmode : DFmode, 32);
6929 rtx result = operands[0];
6931 if (! TARGET_ARCH64)
6933 rtx rtnreg = gen_rtx_REG (SImode, (current_function_uses_only_leaf_regs
6935 rtx value = gen_reg_rtx (SImode);
6937 /* Fetch the instruction where we will return to and see if it's an unimp
6938 instruction (the most significant 10 bits will be zero). If so,
6939 update the return address to skip the unimp instruction. */
6940 emit_move_insn (value,
6941 gen_rtx_MEM (SImode, plus_constant (rtnreg, 8)));
6942 emit_insn (gen_lshrsi3 (value, value, GEN_INT (22)));
6943 emit_insn (gen_update_return (rtnreg, value));
6946 /* Reload the function value registers. */
6947 emit_move_insn (valreg1, adjust_address (result, DImode, 0));
6948 emit_move_insn (valreg2,
6949 adjust_address (result, TARGET_ARCH64 ? TFmode : DFmode, 8));
6951 /* Put USE insns before the return. */
6955 /* Construct the return. */
6956 expand_naked_return ();
6961 ;; Adjust the return address conditionally. If the value of op1 is equal
6962 ;; to all zero then adjust the return address i.e. op0 = op0 + 4.
6963 ;; This is technically *half* the check required by the 32-bit SPARC
6964 ;; psABI. This check only ensures that an "unimp" insn was written by
6965 ;; the caller, but doesn't check to see if the expected size matches
6966 ;; (this is encoded in the 12 lower bits). This check is obsolete and
6967 ;; only used by the above code "untyped_return".
6969 (define_insn "update_return"
6970 [(unspec:SI [(match_operand:SI 0 "register_operand" "r")
6971 (match_operand:SI 1 "register_operand" "r")] UNSPEC_UPDATE_RETURN)]
6974 if (flag_delayed_branch)
6975 return "cmp\t%1, 0\n\tbe,a\t.+8\n\t add\t%0, 4, %0";
6977 return "cmp\t%1, 0\n\tbne\t.+12\n\t nop\n\tadd\t%0, 4, %0";
6979 [(set (attr "type") (const_string "multi"))
6980 (set (attr "length")
6981 (if_then_else (eq_attr "delayed_branch" "true")
6990 (define_expand "indirect_jump"
6991 [(set (pc) (match_operand 0 "address_operand" "p"))]
6995 (define_insn "*branch_sp32"
6996 [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
6999 [(set_attr "type" "uncond_branch")])
7001 (define_insn "*branch_sp64"
7002 [(set (pc) (match_operand:DI 0 "address_operand" "p"))]
7005 [(set_attr "type" "uncond_branch")])
7007 (define_expand "nonlocal_goto"
7008 [(match_operand:SI 0 "general_operand" "")
7009 (match_operand:SI 1 "general_operand" "")
7010 (match_operand:SI 2 "general_operand" "")
7011 (match_operand:SI 3 "" "")]
7014 rtx lab = operands[1];
7015 rtx stack = operands[2];
7016 rtx fp = operands[3];
7019 /* Trap instruction to flush all the register windows. */
7020 emit_insn (gen_flush_register_windows ());
7022 /* Load the fp value for the containing fn into %fp. This is needed
7023 because STACK refers to %fp. Note that virtual register instantiation
7024 fails if the virtual %fp isn't set from a register. */
7025 if (GET_CODE (fp) != REG)
7026 fp = force_reg (Pmode, fp);
7027 emit_move_insn (virtual_stack_vars_rtx, fp);
7029 /* Find the containing function's current nonlocal goto handler,
7030 which will do any cleanups and then jump to the label. */
7031 labreg = gen_rtx_REG (Pmode, 8);
7032 emit_move_insn (labreg, lab);
7034 /* Restore %fp from stack pointer value for containing function.
7035 The restore insn that follows will move this to %sp,
7036 and reload the appropriate value into %fp. */
7037 emit_move_insn (hard_frame_pointer_rtx, stack);
7039 emit_use (stack_pointer_rtx);
7040 emit_use (static_chain_rtx);
7042 /* ??? The V9-specific version was disabled in rev 1.65. */
7043 emit_jump_insn (gen_goto_handler_and_restore (labreg));
7048 ;; Special trap insn to flush register windows.
7049 (define_insn "flush_register_windows"
7050 [(unspec_volatile [(const_int 0)] UNSPECV_FLUSHW)]
7052 { return TARGET_V9 ? "flushw" : "ta\t3"; }
7053 [(set_attr "type" "flushw")])
7055 (define_insn "goto_handler_and_restore"
7056 [(unspec_volatile [(match_operand 0 "register_operand" "=r")] UNSPECV_GOTO)]
7057 "GET_MODE (operands[0]) == Pmode"
7059 if (flag_delayed_branch)
7060 return "jmp\t%0\n\t restore";
7062 return "mov\t%0,%%g1\n\trestore\n\tjmp\t%%g1\n\t nop";
7064 [(set (attr "type") (const_string "multi"))
7065 (set (attr "length")
7066 (if_then_else (eq_attr "delayed_branch" "true")
7070 ;; For __builtin_setjmp we need to flush register windows iff the function
7071 ;; calls alloca as well, because otherwise the register window might be
7072 ;; saved after %sp adjustment and thus setjmp would crash
7073 (define_expand "builtin_setjmp_setup"
7074 [(match_operand 0 "register_operand" "r")]
7077 emit_insn (gen_do_builtin_setjmp_setup ());
7081 (define_insn "do_builtin_setjmp_setup"
7082 [(unspec_volatile [(const_int 0)] UNSPECV_SETJMP)]
7085 if (!cfun->calls_alloca)
7089 fputs ("\tflushw\n", asm_out_file);
7091 fprintf (asm_out_file, "\tst%c\t%%l7, [%%sp+%d]\n",
7092 TARGET_ARCH64 ? 'x' : 'w',
7093 SPARC_STACK_BIAS + 7 * UNITS_PER_WORD);
7094 fprintf (asm_out_file, "\tst%c\t%%fp, [%%sp+%d]\n",
7095 TARGET_ARCH64 ? 'x' : 'w',
7096 SPARC_STACK_BIAS + 14 * UNITS_PER_WORD);
7097 fprintf (asm_out_file, "\tst%c\t%%i7, [%%sp+%d]\n",
7098 TARGET_ARCH64 ? 'x' : 'w',
7099 SPARC_STACK_BIAS + 15 * UNITS_PER_WORD);
7102 [(set_attr "type" "multi")
7103 (set (attr "length")
7104 (cond [(eq_attr "calls_alloca" "false")
7106 (eq_attr "isa" "!v9")
7108 (eq_attr "pic" "true")
7109 (const_int 4)] (const_int 3)))])
7111 ;; Pattern for use after a setjmp to store FP and the return register
7112 ;; into the stack area.
7114 (define_expand "setjmp"
7120 mem = gen_rtx_MEM (Pmode,
7121 plus_constant (stack_pointer_rtx,
7122 SPARC_STACK_BIAS + 14 * UNITS_PER_WORD));
7123 emit_insn (gen_rtx_SET (VOIDmode, mem, frame_pointer_rtx));
7125 mem = gen_rtx_MEM (Pmode,
7126 plus_constant (stack_pointer_rtx,
7127 SPARC_STACK_BIAS + 15 * UNITS_PER_WORD));
7128 emit_insn (gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (Pmode, 31)));
7132 ;; Special pattern for the FLUSH instruction.
7134 ; We do SImode and DImode versions of this to quiet down genrecog's complaints
7135 ; of the define_insn otherwise missing a mode. We make "flush", aka
7136 ; gen_flush, the default one since sparc_initialize_trampoline uses
7137 ; it on SImode mem values.
7139 (define_insn "flush"
7140 [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")] UNSPECV_FLUSH)]
7142 { return TARGET_V9 ? "flush\t%f0" : "iflush\t%f0"; }
7143 [(set_attr "type" "iflush")])
7145 (define_insn "flushdi"
7146 [(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")] UNSPECV_FLUSH)]
7148 { return TARGET_V9 ? "flush\t%f0" : "iflush\t%f0"; }
7149 [(set_attr "type" "iflush")])
7152 ;; Find first set instructions.
7154 ;; The scan instruction searches from the most significant bit while ffs
7155 ;; searches from the least significant bit. The bit index and treatment of
7156 ;; zero also differ. It takes at least 7 instructions to get the proper
7157 ;; result. Here is an obvious 8 instruction sequence.
7160 (define_insn "ffssi2"
7161 [(set (match_operand:SI 0 "register_operand" "=&r")
7162 (ffs:SI (match_operand:SI 1 "register_operand" "r")))
7163 (clobber (match_scratch:SI 2 "=&r"))]
7164 "TARGET_SPARCLITE || TARGET_SPARCLET"
7166 return "sub\t%%g0, %1, %0\;and\t%0, %1, %0\;scan\t%0, 0, %0\;mov\t32, %2\;sub\t%2, %0, %0\;sra\t%0, 31, %2\;and\t%2, 31, %2\;add\t%2, %0, %0";
7168 [(set_attr "type" "multi")
7169 (set_attr "length" "8")])
7171 ;; ??? This should be a define expand, so that the extra instruction have
7172 ;; a chance of being optimized away.
7174 ;; Disabled because none of the UltraSPARCs implement popc. The HAL R1
7175 ;; does, but no one uses that and we don't have a switch for it.
7177 ;(define_insn "ffsdi2"
7178 ; [(set (match_operand:DI 0 "register_operand" "=&r")
7179 ; (ffs:DI (match_operand:DI 1 "register_operand" "r")))
7180 ; (clobber (match_scratch:DI 2 "=&r"))]
7182 ; "neg\t%1, %2\;xnor\t%1, %2, %2\;popc\t%2, %0\;movzr\t%1, 0, %0"
7183 ; [(set_attr "type" "multi")
7184 ; (set_attr "length" "4")])
7188 ;; Peepholes go at the end.
7190 ;; Optimize consecutive loads or stores into ldd and std when possible.
7191 ;; The conditions in which we do this are very restricted and are
7192 ;; explained in the code for {registers,memory}_ok_for_ldd functions.
7195 [(set (match_operand:SI 0 "memory_operand" "")
7197 (set (match_operand:SI 1 "memory_operand" "")
7200 && mems_ok_for_ldd_peep (operands[0], operands[1], NULL_RTX)"
7203 "operands[0] = widen_memory_access (operands[0], DImode, 0);")
7206 [(set (match_operand:SI 0 "memory_operand" "")
7208 (set (match_operand:SI 1 "memory_operand" "")
7211 && mems_ok_for_ldd_peep (operands[1], operands[0], NULL_RTX)"
7214 "operands[1] = widen_memory_access (operands[1], DImode, 0);")
7217 [(set (match_operand:SI 0 "register_operand" "")
7218 (match_operand:SI 1 "memory_operand" ""))
7219 (set (match_operand:SI 2 "register_operand" "")
7220 (match_operand:SI 3 "memory_operand" ""))]
7221 "registers_ok_for_ldd_peep (operands[0], operands[2])
7222 && mems_ok_for_ldd_peep (operands[1], operands[3], operands[0])"
7225 "operands[1] = widen_memory_access (operands[1], DImode, 0);
7226 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));")
7229 [(set (match_operand:SI 0 "memory_operand" "")
7230 (match_operand:SI 1 "register_operand" ""))
7231 (set (match_operand:SI 2 "memory_operand" "")
7232 (match_operand:SI 3 "register_operand" ""))]
7233 "registers_ok_for_ldd_peep (operands[1], operands[3])
7234 && mems_ok_for_ldd_peep (operands[0], operands[2], NULL_RTX)"
7237 "operands[0] = widen_memory_access (operands[0], DImode, 0);
7238 operands[1] = gen_rtx_REG (DImode, REGNO (operands[1]));")
7241 [(set (match_operand:SF 0 "register_operand" "")
7242 (match_operand:SF 1 "memory_operand" ""))
7243 (set (match_operand:SF 2 "register_operand" "")
7244 (match_operand:SF 3 "memory_operand" ""))]
7245 "registers_ok_for_ldd_peep (operands[0], operands[2])
7246 && mems_ok_for_ldd_peep (operands[1], operands[3], operands[0])"
7249 "operands[1] = widen_memory_access (operands[1], DFmode, 0);
7250 operands[0] = gen_rtx_REG (DFmode, REGNO (operands[0]));")
7253 [(set (match_operand:SF 0 "memory_operand" "")
7254 (match_operand:SF 1 "register_operand" ""))
7255 (set (match_operand:SF 2 "memory_operand" "")
7256 (match_operand:SF 3 "register_operand" ""))]
7257 "registers_ok_for_ldd_peep (operands[1], operands[3])
7258 && mems_ok_for_ldd_peep (operands[0], operands[2], NULL_RTX)"
7261 "operands[0] = widen_memory_access (operands[0], DFmode, 0);
7262 operands[1] = gen_rtx_REG (DFmode, REGNO (operands[1]));")
7265 [(set (match_operand:SI 0 "register_operand" "")
7266 (match_operand:SI 1 "memory_operand" ""))
7267 (set (match_operand:SI 2 "register_operand" "")
7268 (match_operand:SI 3 "memory_operand" ""))]
7269 "registers_ok_for_ldd_peep (operands[2], operands[0])
7270 && mems_ok_for_ldd_peep (operands[3], operands[1], operands[0])"
7273 "operands[3] = widen_memory_access (operands[3], DImode, 0);
7274 operands[2] = gen_rtx_REG (DImode, REGNO (operands[2]));")
7277 [(set (match_operand:SI 0 "memory_operand" "")
7278 (match_operand:SI 1 "register_operand" ""))
7279 (set (match_operand:SI 2 "memory_operand" "")
7280 (match_operand:SI 3 "register_operand" ""))]
7281 "registers_ok_for_ldd_peep (operands[3], operands[1])
7282 && mems_ok_for_ldd_peep (operands[2], operands[0], NULL_RTX)"
7285 "operands[2] = widen_memory_access (operands[2], DImode, 0);
7286 operands[3] = gen_rtx_REG (DImode, REGNO (operands[3]));
7290 [(set (match_operand:SF 0 "register_operand" "")
7291 (match_operand:SF 1 "memory_operand" ""))
7292 (set (match_operand:SF 2 "register_operand" "")
7293 (match_operand:SF 3 "memory_operand" ""))]
7294 "registers_ok_for_ldd_peep (operands[2], operands[0])
7295 && mems_ok_for_ldd_peep (operands[3], operands[1], operands[0])"
7298 "operands[3] = widen_memory_access (operands[3], DFmode, 0);
7299 operands[2] = gen_rtx_REG (DFmode, REGNO (operands[2]));")
7302 [(set (match_operand:SF 0 "memory_operand" "")
7303 (match_operand:SF 1 "register_operand" ""))
7304 (set (match_operand:SF 2 "memory_operand" "")
7305 (match_operand:SF 3 "register_operand" ""))]
7306 "registers_ok_for_ldd_peep (operands[3], operands[1])
7307 && mems_ok_for_ldd_peep (operands[2], operands[0], NULL_RTX)"
7310 "operands[2] = widen_memory_access (operands[2], DFmode, 0);
7311 operands[3] = gen_rtx_REG (DFmode, REGNO (operands[3]));")
7313 ;; Optimize the case of following a reg-reg move with a test
7314 ;; of reg just moved. Don't allow floating point regs for operand 0 or 1.
7315 ;; This can result from a float to fix conversion.
7318 [(set (match_operand:SI 0 "register_operand" "")
7319 (match_operand:SI 1 "register_operand" ""))
7321 (compare:CC (match_operand:SI 2 "register_operand" "")
7323 "(rtx_equal_p (operands[2], operands[0])
7324 || rtx_equal_p (operands[2], operands[1]))
7325 && ! SPARC_FP_REG_P (REGNO (operands[0]))
7326 && ! SPARC_FP_REG_P (REGNO (operands[1]))"
7327 [(parallel [(set (match_dup 0) (match_dup 1))
7329 (compare:CC (match_dup 1) (const_int 0)))])]
7333 [(set (match_operand:DI 0 "register_operand" "")
7334 (match_operand:DI 1 "register_operand" ""))
7336 (compare:CCX (match_operand:DI 2 "register_operand" "")
7339 && (rtx_equal_p (operands[2], operands[0])
7340 || rtx_equal_p (operands[2], operands[1]))
7341 && ! SPARC_FP_REG_P (REGNO (operands[0]))
7342 && ! SPARC_FP_REG_P (REGNO (operands[1]))"
7343 [(parallel [(set (match_dup 0) (match_dup 1))
7345 (compare:CCX (match_dup 1) (const_int 0)))])]
7349 ;; Prefetch instructions.
7351 ;; ??? UltraSPARC-III note: A memory operation loading into the floating point register
7352 ;; ??? file, if it hits the prefetch cache, has a chance to dual-issue with other memory
7353 ;; ??? operations. With DFA we might be able to model this, but it requires a lot of
7355 (define_expand "prefetch"
7356 [(match_operand 0 "address_operand" "")
7357 (match_operand 1 "const_int_operand" "")
7358 (match_operand 2 "const_int_operand" "")]
7362 emit_insn (gen_prefetch_64 (operands[0], operands[1], operands[2]));
7364 emit_insn (gen_prefetch_32 (operands[0], operands[1], operands[2]));
7368 (define_insn "prefetch_64"
7369 [(prefetch (match_operand:DI 0 "address_operand" "p")
7370 (match_operand:DI 1 "const_int_operand" "n")
7371 (match_operand:DI 2 "const_int_operand" "n"))]
7374 static const char * const prefetch_instr[2][2] = {
7376 "prefetch\t[%a0], 1", /* no locality: prefetch for one read */
7377 "prefetch\t[%a0], 0", /* medium to high locality: prefetch for several reads */
7380 "prefetch\t[%a0], 3", /* no locality: prefetch for one write */
7381 "prefetch\t[%a0], 2", /* medium to high locality: prefetch for several writes */
7384 int read_or_write = INTVAL (operands[1]);
7385 int locality = INTVAL (operands[2]);
7387 gcc_assert (read_or_write == 0 || read_or_write == 1);
7388 gcc_assert (locality >= 0 && locality < 4);
7389 return prefetch_instr [read_or_write][locality == 0 ? 0 : 1];
7391 [(set_attr "type" "load")])
7393 (define_insn "prefetch_32"
7394 [(prefetch (match_operand:SI 0 "address_operand" "p")
7395 (match_operand:SI 1 "const_int_operand" "n")
7396 (match_operand:SI 2 "const_int_operand" "n"))]
7399 static const char * const prefetch_instr[2][2] = {
7401 "prefetch\t[%a0], 1", /* no locality: prefetch for one read */
7402 "prefetch\t[%a0], 0", /* medium to high locality: prefetch for several reads */
7405 "prefetch\t[%a0], 3", /* no locality: prefetch for one write */
7406 "prefetch\t[%a0], 2", /* medium to high locality: prefetch for several writes */
7409 int read_or_write = INTVAL (operands[1]);
7410 int locality = INTVAL (operands[2]);
7412 gcc_assert (read_or_write == 0 || read_or_write == 1);
7413 gcc_assert (locality >= 0 && locality < 4);
7414 return prefetch_instr [read_or_write][locality == 0 ? 0 : 1];
7416 [(set_attr "type" "load")])
7419 ;; Trap instructions.
7422 [(trap_if (const_int 1) (const_int 5))]
7425 [(set_attr "type" "trap")])
7427 (define_expand "conditional_trap"
7428 [(trap_if (match_operator 0 "noov_compare_operator" [(match_dup 2) (match_dup 3)])
7429 (match_operand:SI 1 "arith_operand" ""))]
7431 "operands[2] = gen_compare_reg (GET_CODE (operands[0]));
7432 if (GET_MODE (operands[2]) != CCmode && GET_MODE (operands[2]) != CCXmode)
7434 operands[3] = const0_rtx;")
7437 [(trap_if (match_operator 0 "noov_compare_operator" [(reg:CC 100) (const_int 0)])
7438 (match_operand:SI 1 "arith_operand" "rM"))]
7442 return "t%C0\t%%icc, %1";
7446 [(set_attr "type" "trap")])
7449 [(trap_if (match_operator 0 "noov_compare_operator" [(reg:CCX 100) (const_int 0)])
7450 (match_operand:SI 1 "arith_operand" "rM"))]
7453 [(set_attr "type" "trap")])
7456 ;; TLS support instructions.
7458 (define_insn "tgd_hi22"
7459 [(set (match_operand:SI 0 "register_operand" "=r")
7460 (high:SI (unspec:SI [(match_operand 1 "tgd_symbolic_operand" "")]
7463 "sethi\\t%%tgd_hi22(%a1), %0")
7465 (define_insn "tgd_lo10"
7466 [(set (match_operand:SI 0 "register_operand" "=r")
7467 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
7468 (unspec:SI [(match_operand 2 "tgd_symbolic_operand" "")]
7471 "add\\t%1, %%tgd_lo10(%a2), %0")
7473 (define_insn "tgd_add32"
7474 [(set (match_operand:SI 0 "register_operand" "=r")
7475 (plus:SI (match_operand:SI 1 "register_operand" "r")
7476 (unspec:SI [(match_operand:SI 2 "register_operand" "r")
7477 (match_operand 3 "tgd_symbolic_operand" "")]
7479 "TARGET_TLS && TARGET_ARCH32"
7480 "add\\t%1, %2, %0, %%tgd_add(%a3)")
7482 (define_insn "tgd_add64"
7483 [(set (match_operand:DI 0 "register_operand" "=r")
7484 (plus:DI (match_operand:DI 1 "register_operand" "r")
7485 (unspec:DI [(match_operand:SI 2 "register_operand" "r")
7486 (match_operand 3 "tgd_symbolic_operand" "")]
7488 "TARGET_TLS && TARGET_ARCH64"
7489 "add\\t%1, %2, %0, %%tgd_add(%a3)")
7491 (define_insn "tgd_call32"
7492 [(set (match_operand 0 "register_operand" "=r")
7493 (call (mem:SI (unspec:SI [(match_operand:SI 1 "symbolic_operand" "s")
7494 (match_operand 2 "tgd_symbolic_operand" "")]
7496 (match_operand 3 "" "")))
7497 (clobber (reg:SI 15))]
7498 "TARGET_TLS && TARGET_ARCH32"
7499 "call\t%a1, %%tgd_call(%a2)%#"
7500 [(set_attr "type" "call")])
7502 (define_insn "tgd_call64"
7503 [(set (match_operand 0 "register_operand" "=r")
7504 (call (mem:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "s")
7505 (match_operand 2 "tgd_symbolic_operand" "")]
7507 (match_operand 3 "" "")))
7508 (clobber (reg:DI 15))]
7509 "TARGET_TLS && TARGET_ARCH64"
7510 "call\t%a1, %%tgd_call(%a2)%#"
7511 [(set_attr "type" "call")])
7513 (define_insn "tldm_hi22"
7514 [(set (match_operand:SI 0 "register_operand" "=r")
7515 (high:SI (unspec:SI [(const_int 0)] UNSPEC_TLSLDM)))]
7517 "sethi\\t%%tldm_hi22(%&), %0")
7519 (define_insn "tldm_lo10"
7520 [(set (match_operand:SI 0 "register_operand" "=r")
7521 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
7522 (unspec:SI [(const_int 0)] UNSPEC_TLSLDM)))]
7524 "add\\t%1, %%tldm_lo10(%&), %0")
7526 (define_insn "tldm_add32"
7527 [(set (match_operand:SI 0 "register_operand" "=r")
7528 (plus:SI (match_operand:SI 1 "register_operand" "r")
7529 (unspec:SI [(match_operand:SI 2 "register_operand" "r")]
7531 "TARGET_TLS && TARGET_ARCH32"
7532 "add\\t%1, %2, %0, %%tldm_add(%&)")
7534 (define_insn "tldm_add64"
7535 [(set (match_operand:DI 0 "register_operand" "=r")
7536 (plus:DI (match_operand:DI 1 "register_operand" "r")
7537 (unspec:DI [(match_operand:SI 2 "register_operand" "r")]
7539 "TARGET_TLS && TARGET_ARCH64"
7540 "add\\t%1, %2, %0, %%tldm_add(%&)")
7542 (define_insn "tldm_call32"
7543 [(set (match_operand 0 "register_operand" "=r")
7544 (call (mem:SI (unspec:SI [(match_operand:SI 1 "symbolic_operand" "s")]
7546 (match_operand 2 "" "")))
7547 (clobber (reg:SI 15))]
7548 "TARGET_TLS && TARGET_ARCH32"
7549 "call\t%a1, %%tldm_call(%&)%#"
7550 [(set_attr "type" "call")])
7552 (define_insn "tldm_call64"
7553 [(set (match_operand 0 "register_operand" "=r")
7554 (call (mem:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "s")]
7556 (match_operand 2 "" "")))
7557 (clobber (reg:DI 15))]
7558 "TARGET_TLS && TARGET_ARCH64"
7559 "call\t%a1, %%tldm_call(%&)%#"
7560 [(set_attr "type" "call")])
7562 (define_insn "tldo_hix22"
7563 [(set (match_operand:SI 0 "register_operand" "=r")
7564 (high:SI (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")]
7567 "sethi\\t%%tldo_hix22(%a1), %0")
7569 (define_insn "tldo_lox10"
7570 [(set (match_operand:SI 0 "register_operand" "=r")
7571 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
7572 (unspec:SI [(match_operand 2 "tld_symbolic_operand" "")]
7575 "xor\\t%1, %%tldo_lox10(%a2), %0")
7577 (define_insn "tldo_add32"
7578 [(set (match_operand:SI 0 "register_operand" "=r")
7579 (plus:SI (match_operand:SI 1 "register_operand" "r")
7580 (unspec:SI [(match_operand:SI 2 "register_operand" "r")
7581 (match_operand 3 "tld_symbolic_operand" "")]
7583 "TARGET_TLS && TARGET_ARCH32"
7584 "add\\t%1, %2, %0, %%tldo_add(%a3)")
7586 (define_insn "tldo_add64"
7587 [(set (match_operand:DI 0 "register_operand" "=r")
7588 (plus:DI (match_operand:DI 1 "register_operand" "r")
7589 (unspec:DI [(match_operand:SI 2 "register_operand" "r")
7590 (match_operand 3 "tld_symbolic_operand" "")]
7592 "TARGET_TLS && TARGET_ARCH64"
7593 "add\\t%1, %2, %0, %%tldo_add(%a3)")
7595 (define_insn "tie_hi22"
7596 [(set (match_operand:SI 0 "register_operand" "=r")
7597 (high:SI (unspec:SI [(match_operand 1 "tie_symbolic_operand" "")]
7600 "sethi\\t%%tie_hi22(%a1), %0")
7602 (define_insn "tie_lo10"
7603 [(set (match_operand:SI 0 "register_operand" "=r")
7604 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
7605 (unspec:SI [(match_operand 2 "tie_symbolic_operand" "")]
7608 "add\\t%1, %%tie_lo10(%a2), %0")
7610 (define_insn "tie_ld32"
7611 [(set (match_operand:SI 0 "register_operand" "=r")
7612 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
7613 (match_operand:SI 2 "register_operand" "r")
7614 (match_operand 3 "tie_symbolic_operand" "")]
7616 "TARGET_TLS && TARGET_ARCH32"
7617 "ld\\t[%1 + %2], %0, %%tie_ld(%a3)"
7618 [(set_attr "type" "load")])
7620 (define_insn "tie_ld64"
7621 [(set (match_operand:DI 0 "register_operand" "=r")
7622 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
7623 (match_operand:SI 2 "register_operand" "r")
7624 (match_operand 3 "tie_symbolic_operand" "")]
7626 "TARGET_TLS && TARGET_ARCH64"
7627 "ldx\\t[%1 + %2], %0, %%tie_ldx(%a3)"
7628 [(set_attr "type" "load")])
7630 (define_insn "tie_add32"
7631 [(set (match_operand:SI 0 "register_operand" "=r")
7632 (plus:SI (match_operand:SI 1 "register_operand" "r")
7633 (unspec:SI [(match_operand:SI 2 "register_operand" "r")
7634 (match_operand 3 "tie_symbolic_operand" "")]
7636 "TARGET_SUN_TLS && TARGET_ARCH32"
7637 "add\\t%1, %2, %0, %%tie_add(%a3)")
7639 (define_insn "tie_add64"
7640 [(set (match_operand:DI 0 "register_operand" "=r")
7641 (plus:DI (match_operand:DI 1 "register_operand" "r")
7642 (unspec:DI [(match_operand:DI 2 "register_operand" "r")
7643 (match_operand 3 "tie_symbolic_operand" "")]
7645 "TARGET_SUN_TLS && TARGET_ARCH64"
7646 "add\\t%1, %2, %0, %%tie_add(%a3)")
7648 (define_insn "tle_hix22_sp32"
7649 [(set (match_operand:SI 0 "register_operand" "=r")
7650 (high:SI (unspec:SI [(match_operand 1 "tle_symbolic_operand" "")]
7652 "TARGET_TLS && TARGET_ARCH32"
7653 "sethi\\t%%tle_hix22(%a1), %0")
7655 (define_insn "tle_lox10_sp32"
7656 [(set (match_operand:SI 0 "register_operand" "=r")
7657 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
7658 (unspec:SI [(match_operand 2 "tle_symbolic_operand" "")]
7660 "TARGET_TLS && TARGET_ARCH32"
7661 "xor\\t%1, %%tle_lox10(%a2), %0")
7663 (define_insn "tle_hix22_sp64"
7664 [(set (match_operand:DI 0 "register_operand" "=r")
7665 (high:DI (unspec:DI [(match_operand 1 "tle_symbolic_operand" "")]
7667 "TARGET_TLS && TARGET_ARCH64"
7668 "sethi\\t%%tle_hix22(%a1), %0")
7670 (define_insn "tle_lox10_sp64"
7671 [(set (match_operand:DI 0 "register_operand" "=r")
7672 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
7673 (unspec:DI [(match_operand 2 "tle_symbolic_operand" "")]
7675 "TARGET_TLS && TARGET_ARCH64"
7676 "xor\\t%1, %%tle_lox10(%a2), %0")
7678 ;; Now patterns combining tldo_add{32,64} with some integer loads or stores
7679 (define_insn "*tldo_ldub_sp32"
7680 [(set (match_operand:QI 0 "register_operand" "=r")
7681 (mem:QI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
7682 (match_operand 3 "tld_symbolic_operand" "")]
7684 (match_operand:SI 1 "register_operand" "r"))))]
7685 "TARGET_TLS && TARGET_ARCH32"
7686 "ldub\t[%1 + %2], %0, %%tldo_add(%3)"
7687 [(set_attr "type" "load")
7688 (set_attr "us3load_type" "3cycle")])
7690 (define_insn "*tldo_ldub1_sp32"
7691 [(set (match_operand:HI 0 "register_operand" "=r")
7692 (zero_extend:HI (mem:QI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
7693 (match_operand 3 "tld_symbolic_operand" "")]
7695 (match_operand:SI 1 "register_operand" "r")))))]
7696 "TARGET_TLS && TARGET_ARCH32"
7697 "ldub\t[%1 + %2], %0, %%tldo_add(%3)"
7698 [(set_attr "type" "load")
7699 (set_attr "us3load_type" "3cycle")])
7701 (define_insn "*tldo_ldub2_sp32"
7702 [(set (match_operand:SI 0 "register_operand" "=r")
7703 (zero_extend:SI (mem:QI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
7704 (match_operand 3 "tld_symbolic_operand" "")]
7706 (match_operand:SI 1 "register_operand" "r")))))]
7707 "TARGET_TLS && TARGET_ARCH32"
7708 "ldub\t[%1 + %2], %0, %%tldo_add(%3)"
7709 [(set_attr "type" "load")
7710 (set_attr "us3load_type" "3cycle")])
7712 (define_insn "*tldo_ldsb1_sp32"
7713 [(set (match_operand:HI 0 "register_operand" "=r")
7714 (sign_extend:HI (mem:QI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
7715 (match_operand 3 "tld_symbolic_operand" "")]
7717 (match_operand:SI 1 "register_operand" "r")))))]
7718 "TARGET_TLS && TARGET_ARCH32"
7719 "ldsb\t[%1 + %2], %0, %%tldo_add(%3)"
7720 [(set_attr "type" "sload")
7721 (set_attr "us3load_type" "3cycle")])
7723 (define_insn "*tldo_ldsb2_sp32"
7724 [(set (match_operand:SI 0 "register_operand" "=r")
7725 (sign_extend:SI (mem:QI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
7726 (match_operand 3 "tld_symbolic_operand" "")]
7728 (match_operand:SI 1 "register_operand" "r")))))]
7729 "TARGET_TLS && TARGET_ARCH32"
7730 "ldsb\t[%1 + %2], %0, %%tldo_add(%3)"
7731 [(set_attr "type" "sload")
7732 (set_attr "us3load_type" "3cycle")])
7734 (define_insn "*tldo_ldub_sp64"
7735 [(set (match_operand:QI 0 "register_operand" "=r")
7736 (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
7737 (match_operand 3 "tld_symbolic_operand" "")]
7739 (match_operand:DI 1 "register_operand" "r"))))]
7740 "TARGET_TLS && TARGET_ARCH64"
7741 "ldub\t[%1 + %2], %0, %%tldo_add(%3)"
7742 [(set_attr "type" "load")
7743 (set_attr "us3load_type" "3cycle")])
7745 (define_insn "*tldo_ldub1_sp64"
7746 [(set (match_operand:HI 0 "register_operand" "=r")
7747 (zero_extend:HI (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
7748 (match_operand 3 "tld_symbolic_operand" "")]
7750 (match_operand:DI 1 "register_operand" "r")))))]
7751 "TARGET_TLS && TARGET_ARCH64"
7752 "ldub\t[%1 + %2], %0, %%tldo_add(%3)"
7753 [(set_attr "type" "load")
7754 (set_attr "us3load_type" "3cycle")])
7756 (define_insn "*tldo_ldub2_sp64"
7757 [(set (match_operand:SI 0 "register_operand" "=r")
7758 (zero_extend:SI (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
7759 (match_operand 3 "tld_symbolic_operand" "")]
7761 (match_operand:DI 1 "register_operand" "r")))))]
7762 "TARGET_TLS && TARGET_ARCH64"
7763 "ldub\t[%1 + %2], %0, %%tldo_add(%3)"
7764 [(set_attr "type" "load")
7765 (set_attr "us3load_type" "3cycle")])
7767 (define_insn "*tldo_ldub3_sp64"
7768 [(set (match_operand:DI 0 "register_operand" "=r")
7769 (zero_extend:DI (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
7770 (match_operand 3 "tld_symbolic_operand" "")]
7772 (match_operand:DI 1 "register_operand" "r")))))]
7773 "TARGET_TLS && TARGET_ARCH64"
7774 "ldub\t[%1 + %2], %0, %%tldo_add(%3)"
7775 [(set_attr "type" "load")
7776 (set_attr "us3load_type" "3cycle")])
7778 (define_insn "*tldo_ldsb1_sp64"
7779 [(set (match_operand:HI 0 "register_operand" "=r")
7780 (sign_extend:HI (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
7781 (match_operand 3 "tld_symbolic_operand" "")]
7783 (match_operand:DI 1 "register_operand" "r")))))]
7784 "TARGET_TLS && TARGET_ARCH64"
7785 "ldsb\t[%1 + %2], %0, %%tldo_add(%3)"
7786 [(set_attr "type" "sload")
7787 (set_attr "us3load_type" "3cycle")])
7789 (define_insn "*tldo_ldsb2_sp64"
7790 [(set (match_operand:SI 0 "register_operand" "=r")
7791 (sign_extend:SI (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
7792 (match_operand 3 "tld_symbolic_operand" "")]
7794 (match_operand:DI 1 "register_operand" "r")))))]
7795 "TARGET_TLS && TARGET_ARCH64"
7796 "ldsb\t[%1 + %2], %0, %%tldo_add(%3)"
7797 [(set_attr "type" "sload")
7798 (set_attr "us3load_type" "3cycle")])
7800 (define_insn "*tldo_ldsb3_sp64"
7801 [(set (match_operand:DI 0 "register_operand" "=r")
7802 (sign_extend:DI (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
7803 (match_operand 3 "tld_symbolic_operand" "")]
7805 (match_operand:DI 1 "register_operand" "r")))))]
7806 "TARGET_TLS && TARGET_ARCH64"
7807 "ldsb\t[%1 + %2], %0, %%tldo_add(%3)"
7808 [(set_attr "type" "sload")
7809 (set_attr "us3load_type" "3cycle")])
7811 (define_insn "*tldo_lduh_sp32"
7812 [(set (match_operand:HI 0 "register_operand" "=r")
7813 (mem:HI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
7814 (match_operand 3 "tld_symbolic_operand" "")]
7816 (match_operand:SI 1 "register_operand" "r"))))]
7817 "TARGET_TLS && TARGET_ARCH32"
7818 "lduh\t[%1 + %2], %0, %%tldo_add(%3)"
7819 [(set_attr "type" "load")
7820 (set_attr "us3load_type" "3cycle")])
7822 (define_insn "*tldo_lduh1_sp32"
7823 [(set (match_operand:SI 0 "register_operand" "=r")
7824 (zero_extend:SI (mem:HI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
7825 (match_operand 3 "tld_symbolic_operand" "")]
7827 (match_operand:SI 1 "register_operand" "r")))))]
7828 "TARGET_TLS && TARGET_ARCH32"
7829 "lduh\t[%1 + %2], %0, %%tldo_add(%3)"
7830 [(set_attr "type" "load")
7831 (set_attr "us3load_type" "3cycle")])
7833 (define_insn "*tldo_ldsh1_sp32"
7834 [(set (match_operand:SI 0 "register_operand" "=r")
7835 (sign_extend:SI (mem:HI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
7836 (match_operand 3 "tld_symbolic_operand" "")]
7838 (match_operand:SI 1 "register_operand" "r")))))]
7839 "TARGET_TLS && TARGET_ARCH32"
7840 "ldsh\t[%1 + %2], %0, %%tldo_add(%3)"
7841 [(set_attr "type" "sload")
7842 (set_attr "us3load_type" "3cycle")])
7844 (define_insn "*tldo_lduh_sp64"
7845 [(set (match_operand:HI 0 "register_operand" "=r")
7846 (mem:HI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
7847 (match_operand 3 "tld_symbolic_operand" "")]
7849 (match_operand:DI 1 "register_operand" "r"))))]
7850 "TARGET_TLS && TARGET_ARCH64"
7851 "lduh\t[%1 + %2], %0, %%tldo_add(%3)"
7852 [(set_attr "type" "load")
7853 (set_attr "us3load_type" "3cycle")])
7855 (define_insn "*tldo_lduh1_sp64"
7856 [(set (match_operand:SI 0 "register_operand" "=r")
7857 (zero_extend:SI (mem:HI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
7858 (match_operand 3 "tld_symbolic_operand" "")]
7860 (match_operand:DI 1 "register_operand" "r")))))]
7861 "TARGET_TLS && TARGET_ARCH64"
7862 "lduh\t[%1 + %2], %0, %%tldo_add(%3)"
7863 [(set_attr "type" "load")
7864 (set_attr "us3load_type" "3cycle")])
7866 (define_insn "*tldo_lduh2_sp64"
7867 [(set (match_operand:DI 0 "register_operand" "=r")
7868 (zero_extend:DI (mem:HI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
7869 (match_operand 3 "tld_symbolic_operand" "")]
7871 (match_operand:DI 1 "register_operand" "r")))))]
7872 "TARGET_TLS && TARGET_ARCH64"
7873 "lduh\t[%1 + %2], %0, %%tldo_add(%3)"
7874 [(set_attr "type" "load")
7875 (set_attr "us3load_type" "3cycle")])
7877 (define_insn "*tldo_ldsh1_sp64"
7878 [(set (match_operand:SI 0 "register_operand" "=r")
7879 (sign_extend:SI (mem:HI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
7880 (match_operand 3 "tld_symbolic_operand" "")]
7882 (match_operand:DI 1 "register_operand" "r")))))]
7883 "TARGET_TLS && TARGET_ARCH64"
7884 "ldsh\t[%1 + %2], %0, %%tldo_add(%3)"
7885 [(set_attr "type" "sload")
7886 (set_attr "us3load_type" "3cycle")])
7888 (define_insn "*tldo_ldsh2_sp64"
7889 [(set (match_operand:DI 0 "register_operand" "=r")
7890 (sign_extend:DI (mem:HI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
7891 (match_operand 3 "tld_symbolic_operand" "")]
7893 (match_operand:DI 1 "register_operand" "r")))))]
7894 "TARGET_TLS && TARGET_ARCH64"
7895 "ldsh\t[%1 + %2], %0, %%tldo_add(%3)"
7896 [(set_attr "type" "sload")
7897 (set_attr "us3load_type" "3cycle")])
7899 (define_insn "*tldo_lduw_sp32"
7900 [(set (match_operand:SI 0 "register_operand" "=r")
7901 (mem:SI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
7902 (match_operand 3 "tld_symbolic_operand" "")]
7904 (match_operand:SI 1 "register_operand" "r"))))]
7905 "TARGET_TLS && TARGET_ARCH32"
7906 "ld\t[%1 + %2], %0, %%tldo_add(%3)"
7907 [(set_attr "type" "load")])
7909 (define_insn "*tldo_lduw_sp64"
7910 [(set (match_operand:SI 0 "register_operand" "=r")
7911 (mem:SI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
7912 (match_operand 3 "tld_symbolic_operand" "")]
7914 (match_operand:DI 1 "register_operand" "r"))))]
7915 "TARGET_TLS && TARGET_ARCH64"
7916 "lduw\t[%1 + %2], %0, %%tldo_add(%3)"
7917 [(set_attr "type" "load")])
7919 (define_insn "*tldo_lduw1_sp64"
7920 [(set (match_operand:DI 0 "register_operand" "=r")
7921 (zero_extend:DI (mem:SI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
7922 (match_operand 3 "tld_symbolic_operand" "")]
7924 (match_operand:DI 1 "register_operand" "r")))))]
7925 "TARGET_TLS && TARGET_ARCH64"
7926 "lduw\t[%1 + %2], %0, %%tldo_add(%3)"
7927 [(set_attr "type" "load")])
7929 (define_insn "*tldo_ldsw1_sp64"
7930 [(set (match_operand:DI 0 "register_operand" "=r")
7931 (sign_extend:DI (mem:SI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
7932 (match_operand 3 "tld_symbolic_operand" "")]
7934 (match_operand:DI 1 "register_operand" "r")))))]
7935 "TARGET_TLS && TARGET_ARCH64"
7936 "ldsw\t[%1 + %2], %0, %%tldo_add(%3)"
7937 [(set_attr "type" "sload")
7938 (set_attr "us3load_type" "3cycle")])
7940 (define_insn "*tldo_ldx_sp64"
7941 [(set (match_operand:DI 0 "register_operand" "=r")
7942 (mem:DI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
7943 (match_operand 3 "tld_symbolic_operand" "")]
7945 (match_operand:DI 1 "register_operand" "r"))))]
7946 "TARGET_TLS && TARGET_ARCH64"
7947 "ldx\t[%1 + %2], %0, %%tldo_add(%3)"
7948 [(set_attr "type" "load")])
7950 (define_insn "*tldo_stb_sp32"
7951 [(set (mem:QI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
7952 (match_operand 3 "tld_symbolic_operand" "")]
7954 (match_operand:SI 1 "register_operand" "r")))
7955 (match_operand:QI 0 "register_operand" "=r"))]
7956 "TARGET_TLS && TARGET_ARCH32"
7957 "stb\t%0, [%1 + %2], %%tldo_add(%3)"
7958 [(set_attr "type" "store")])
7960 (define_insn "*tldo_stb_sp64"
7961 [(set (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
7962 (match_operand 3 "tld_symbolic_operand" "")]
7964 (match_operand:DI 1 "register_operand" "r")))
7965 (match_operand:QI 0 "register_operand" "=r"))]
7966 "TARGET_TLS && TARGET_ARCH64"
7967 "stb\t%0, [%1 + %2], %%tldo_add(%3)"
7968 [(set_attr "type" "store")])
7970 (define_insn "*tldo_sth_sp32"
7971 [(set (mem:HI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
7972 (match_operand 3 "tld_symbolic_operand" "")]
7974 (match_operand:SI 1 "register_operand" "r")))
7975 (match_operand:HI 0 "register_operand" "=r"))]
7976 "TARGET_TLS && TARGET_ARCH32"
7977 "sth\t%0, [%1 + %2], %%tldo_add(%3)"
7978 [(set_attr "type" "store")])
7980 (define_insn "*tldo_sth_sp64"
7981 [(set (mem:HI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
7982 (match_operand 3 "tld_symbolic_operand" "")]
7984 (match_operand:DI 1 "register_operand" "r")))
7985 (match_operand:HI 0 "register_operand" "=r"))]
7986 "TARGET_TLS && TARGET_ARCH64"
7987 "sth\t%0, [%1 + %2], %%tldo_add(%3)"
7988 [(set_attr "type" "store")])
7990 (define_insn "*tldo_stw_sp32"
7991 [(set (mem:SI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
7992 (match_operand 3 "tld_symbolic_operand" "")]
7994 (match_operand:SI 1 "register_operand" "r")))
7995 (match_operand:SI 0 "register_operand" "=r"))]
7996 "TARGET_TLS && TARGET_ARCH32"
7997 "st\t%0, [%1 + %2], %%tldo_add(%3)"
7998 [(set_attr "type" "store")])
8000 (define_insn "*tldo_stw_sp64"
8001 [(set (mem:SI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8002 (match_operand 3 "tld_symbolic_operand" "")]
8004 (match_operand:DI 1 "register_operand" "r")))
8005 (match_operand:SI 0 "register_operand" "=r"))]
8006 "TARGET_TLS && TARGET_ARCH64"
8007 "stw\t%0, [%1 + %2], %%tldo_add(%3)"
8008 [(set_attr "type" "store")])
8010 (define_insn "*tldo_stx_sp64"
8011 [(set (mem:DI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8012 (match_operand 3 "tld_symbolic_operand" "")]
8014 (match_operand:DI 1 "register_operand" "r")))
8015 (match_operand:DI 0 "register_operand" "=r"))]
8016 "TARGET_TLS && TARGET_ARCH64"
8017 "stx\t%0, [%1 + %2], %%tldo_add(%3)"
8018 [(set_attr "type" "store")])
8021 ;; Stack protector instructions.
8023 (define_expand "stack_protect_set"
8024 [(match_operand 0 "memory_operand" "")
8025 (match_operand 1 "memory_operand" "")]
8028 #ifdef TARGET_THREAD_SSP_OFFSET
8029 rtx tlsreg = gen_rtx_REG (Pmode, 7);
8030 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
8031 operands[1] = gen_rtx_MEM (Pmode, addr);
8034 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
8036 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
8040 (define_insn "stack_protect_setsi"
8041 [(set (match_operand:SI 0 "memory_operand" "=m")
8042 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
8043 (set (match_scratch:SI 2 "=&r") (const_int 0))]
8045 "ld\t%1, %2\;st\t%2, %0\;mov\t0, %2"
8046 [(set_attr "type" "multi")
8047 (set_attr "length" "3")])
8049 (define_insn "stack_protect_setdi"
8050 [(set (match_operand:DI 0 "memory_operand" "=m")
8051 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
8052 (set (match_scratch:DI 2 "=&r") (const_int 0))]
8054 "ldx\t%1, %2\;stx\t%2, %0\;mov\t0, %2"
8055 [(set_attr "type" "multi")
8056 (set_attr "length" "3")])
8058 (define_expand "stack_protect_test"
8059 [(match_operand 0 "memory_operand" "")
8060 (match_operand 1 "memory_operand" "")
8061 (match_operand 2 "" "")]
8064 #ifdef TARGET_THREAD_SSP_OFFSET
8065 rtx tlsreg = gen_rtx_REG (Pmode, 7);
8066 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
8067 operands[1] = gen_rtx_MEM (Pmode, addr);
8071 rtx temp = gen_reg_rtx (Pmode);
8072 emit_insn (gen_stack_protect_testdi (temp, operands[0], operands[1]));
8073 sparc_compare_op0 = temp;
8074 sparc_compare_op1 = const0_rtx;
8078 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
8079 sparc_compare_op0 = operands[0];
8080 sparc_compare_op1 = operands[1];
8081 sparc_compare_emitted = gen_rtx_REG (CCmode, SPARC_ICC_REG);
8083 emit_jump_insn (gen_beq (operands[2]));
8087 (define_insn "stack_protect_testsi"
8089 (unspec:CC [(match_operand:SI 0 "memory_operand" "m")
8090 (match_operand:SI 1 "memory_operand" "m")]
8092 (set (match_scratch:SI 3 "=r") (const_int 0))
8093 (clobber (match_scratch:SI 2 "=&r"))]
8095 "ld\t%0, %2\;ld\t%1, %3\;xorcc\t%2, %3, %2\;mov\t0, %3"
8096 [(set_attr "type" "multi")
8097 (set_attr "length" "4")])
8099 (define_insn "stack_protect_testdi"
8100 [(set (match_operand:DI 0 "register_operand" "=&r")
8101 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
8102 (match_operand:DI 2 "memory_operand" "m")]
8104 (set (match_scratch:DI 3 "=r") (const_int 0))]
8106 "ldx\t%1, %0\;ldx\t%2, %3\;xor\t%0, %3, %0\;mov\t0, %3"
8107 [(set_attr "type" "multi")
8108 (set_attr "length" "4")])
8111 ;; Vector instructions.
8113 (define_insn "addv2si3"
8114 [(set (match_operand:V2SI 0 "register_operand" "=e")
8115 (plus:V2SI (match_operand:V2SI 1 "register_operand" "e")
8116 (match_operand:V2SI 2 "register_operand" "e")))]
8118 "fpadd32\t%1, %2, %0"
8119 [(set_attr "type" "fga")
8120 (set_attr "fptype" "double")])
8122 (define_insn "addv4hi3"
8123 [(set (match_operand:V4HI 0 "register_operand" "=e")
8124 (plus:V4HI (match_operand:V4HI 1 "register_operand" "e")
8125 (match_operand:V4HI 2 "register_operand" "e")))]
8127 "fpadd16\t%1, %2, %0"
8128 [(set_attr "type" "fga")
8129 (set_attr "fptype" "double")])
8131 ;; fpadd32s is emitted by the addsi3 pattern.
8133 (define_insn "addv2hi3"
8134 [(set (match_operand:V2HI 0 "register_operand" "=f")
8135 (plus:V2HI (match_operand:V2HI 1 "register_operand" "f")
8136 (match_operand:V2HI 2 "register_operand" "f")))]
8138 "fpadd16s\t%1, %2, %0"
8139 [(set_attr "type" "fga")
8140 (set_attr "fptype" "single")])
8142 (define_insn "subv2si3"
8143 [(set (match_operand:V2SI 0 "register_operand" "=e")
8144 (minus:V2SI (match_operand:V2SI 1 "register_operand" "e")
8145 (match_operand:V2SI 2 "register_operand" "e")))]
8147 "fpsub32\t%1, %2, %0"
8148 [(set_attr "type" "fga")
8149 (set_attr "fptype" "double")])
8151 (define_insn "subv4hi3"
8152 [(set (match_operand:V4HI 0 "register_operand" "=e")
8153 (minus:V4HI (match_operand:V4HI 1 "register_operand" "e")
8154 (match_operand:V4HI 2 "register_operand" "e")))]
8156 "fpsub16\t%1, %2, %0"
8157 [(set_attr "type" "fga")
8158 (set_attr "fptype" "double")])
8160 ;; fpsub32s is emitted by the subsi3 pattern.
8162 (define_insn "subv2hi3"
8163 [(set (match_operand:V2HI 0 "register_operand" "=f")
8164 (minus:V2HI (match_operand:V2HI 1 "register_operand" "f")
8165 (match_operand:V2HI 2 "register_operand" "f")))]
8167 "fpsub16s\t%1, %2, %0"
8168 [(set_attr "type" "fga")
8169 (set_attr "fptype" "single")])
8171 ;; All other logical instructions have integer equivalents so they
8172 ;; are defined together.
8174 ;; (ior (not (op1)) (not (op2))) is the canonical form of NAND.
8176 (define_insn "*nand<V64mode>_vis"
8177 [(set (match_operand:V64 0 "register_operand" "=e")
8178 (ior:V64 (not:V64 (match_operand:V64 1 "register_operand" "e"))
8179 (not:V64 (match_operand:V64 2 "register_operand" "e"))))]
8182 [(set_attr "type" "fga")
8183 (set_attr "fptype" "double")])
8185 (define_insn "*nand<V32mode>_vis"
8186 [(set (match_operand:V32 0 "register_operand" "=f")
8187 (ior:V32 (not:V32 (match_operand:V32 1 "register_operand" "f"))
8188 (not:V32 (match_operand:V32 2 "register_operand" "f"))))]
8190 "fnands\t%1, %2, %0"
8191 [(set_attr "type" "fga")
8192 (set_attr "fptype" "single")])
8194 ;; Hard to generate VIS instructions. We have builtins for these.
8196 (define_insn "fpack16_vis"
8197 [(set (match_operand:V4QI 0 "register_operand" "=f")
8198 (unspec:V4QI [(match_operand:V4HI 1 "register_operand" "e")]
8202 [(set_attr "type" "fga")
8203 (set_attr "fptype" "double")])
8205 (define_insn "fpackfix_vis"
8206 [(set (match_operand:V2HI 0 "register_operand" "=f")
8207 (unspec:V2HI [(match_operand:V2SI 1 "register_operand" "e")]
8211 [(set_attr "type" "fga")
8212 (set_attr "fptype" "double")])
8214 (define_insn "fpack32_vis"
8215 [(set (match_operand:V8QI 0 "register_operand" "=e")
8216 (unspec:V8QI [(match_operand:V2SI 1 "register_operand" "e")
8217 (match_operand:V8QI 2 "register_operand" "e")]
8220 "fpack32\t%1, %2, %0"
8221 [(set_attr "type" "fga")
8222 (set_attr "fptype" "double")])
8224 (define_insn "fexpand_vis"
8225 [(set (match_operand:V4HI 0 "register_operand" "=e")
8226 (unspec:V4HI [(match_operand:V4QI 1 "register_operand" "f")]
8230 [(set_attr "type" "fga")
8231 (set_attr "fptype" "double")])
8233 ;; It may be possible to describe this operation as (1 indexed):
8234 ;; (vec_select (vec_duplicate (vec_duplicate (vec_concat 1 2)))
8235 ;; 1,5,10,14,19,23,28,32)
8236 ;; Note that (vec_merge:V8QI [(V4QI) (V4QI)] (10101010 = 170) doesn't work
8237 ;; because vec_merge expects all the operands to be of the same type.
8238 (define_insn "fpmerge_vis"
8239 [(set (match_operand:V8QI 0 "register_operand" "=e")
8240 (unspec:V8QI [(match_operand:V4QI 1 "register_operand" "f")
8241 (match_operand:V4QI 2 "register_operand" "f")]
8244 "fpmerge\t%1, %2, %0"
8245 [(set_attr "type" "fga")
8246 (set_attr "fptype" "double")])
8248 ;; Partitioned multiply instructions
8249 (define_insn "fmul8x16_vis"
8250 [(set (match_operand:V4HI 0 "register_operand" "=e")
8251 (mult:V4HI (match_operand:V4QI 1 "register_operand" "f")
8252 (match_operand:V4HI 2 "register_operand" "e")))]
8254 "fmul8x16\t%1, %2, %0"
8255 [(set_attr "type" "fpmul")
8256 (set_attr "fptype" "double")])
8258 ;; Only one of the following two insns can be a multiply.
8259 (define_insn "fmul8x16au_vis"
8260 [(set (match_operand:V4HI 0 "register_operand" "=e")
8261 (mult:V4HI (match_operand:V4QI 1 "register_operand" "f")
8262 (match_operand:V2HI 2 "register_operand" "f")))]
8264 "fmul8x16au\t%1, %2, %0"
8265 [(set_attr "type" "fpmul")
8266 (set_attr "fptype" "double")])
8268 (define_insn "fmul8x16al_vis"
8269 [(set (match_operand:V4HI 0 "register_operand" "=e")
8270 (unspec:V4HI [(match_operand:V4QI 1 "register_operand" "f")
8271 (match_operand:V2HI 2 "register_operand" "f")]
8274 "fmul8x16al\t%1, %2, %0"
8275 [(set_attr "type" "fpmul")
8276 (set_attr "fptype" "double")])
8278 ;; Only one of the following two insns can be a multiply.
8279 (define_insn "fmul8sux16_vis"
8280 [(set (match_operand:V4HI 0 "register_operand" "=e")
8281 (mult:V4HI (match_operand:V8QI 1 "register_operand" "e")
8282 (match_operand:V4HI 2 "register_operand" "e")))]
8284 "fmul8sux16\t%1, %2, %0"
8285 [(set_attr "type" "fpmul")
8286 (set_attr "fptype" "double")])
8288 (define_insn "fmul8ulx16_vis"
8289 [(set (match_operand:V4HI 0 "register_operand" "=e")
8290 (unspec:V4HI [(match_operand:V8QI 1 "register_operand" "e")
8291 (match_operand:V4HI 2 "register_operand" "e")]
8294 "fmul8ulx16\t%1, %2, %0"
8295 [(set_attr "type" "fpmul")
8296 (set_attr "fptype" "double")])
8298 ;; Only one of the following two insns can be a multiply.
8299 (define_insn "fmuld8sux16_vis"
8300 [(set (match_operand:V2SI 0 "register_operand" "=e")
8301 (mult:V2SI (match_operand:V4QI 1 "register_operand" "f")
8302 (match_operand:V2HI 2 "register_operand" "f")))]
8304 "fmuld8sux16\t%1, %2, %0"
8305 [(set_attr "type" "fpmul")
8306 (set_attr "fptype" "double")])
8308 (define_insn "fmuld8ulx16_vis"
8309 [(set (match_operand:V2SI 0 "register_operand" "=e")
8310 (unspec:V2SI [(match_operand:V4QI 1 "register_operand" "f")
8311 (match_operand:V2HI 2 "register_operand" "f")]
8314 "fmuld8ulx16\t%1, %2, %0"
8315 [(set_attr "type" "fpmul")
8316 (set_attr "fptype" "double")])
8318 ;; Using faligndata only makes sense after an alignaddr since the choice of
8319 ;; bytes to take out of each operand is dependent on the results of the last
8321 (define_insn "faligndata<V64I:mode>_vis"
8322 [(set (match_operand:V64I 0 "register_operand" "=e")
8323 (unspec:V64I [(match_operand:V64I 1 "register_operand" "e")
8324 (match_operand:V64I 2 "register_operand" "e")]
8327 "faligndata\t%1, %2, %0"
8328 [(set_attr "type" "fga")
8329 (set_attr "fptype" "double")])
8331 (define_insn "alignaddr<P:mode>_vis"
8332 [(set (match_operand:P 0 "register_operand" "=r")
8333 (unspec:P [(match_operand:P 1 "register_or_zero_operand" "rJ")
8334 (match_operand:P 2 "register_or_zero_operand" "rJ")]
8337 "alignaddr\t%r1, %r2, %0")
8339 (define_insn "pdist_vis"
8340 [(set (match_operand:DI 0 "register_operand" "=e")
8341 (unspec:DI [(match_operand:V8QI 1 "register_operand" "e")
8342 (match_operand:V8QI 2 "register_operand" "e")
8343 (match_operand:DI 3 "register_operand" "0")]
8347 [(set_attr "type" "fga")
8348 (set_attr "fptype" "double")])