1 /* Definitions of target machine for GNU compiler, for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1994, 1995, 1996, 1997, 1998, 1999
3 2000, 2001, 2002 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com).
5 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 /* Note that some other tm.h files include this one and then override
26 whatever definitions are necessary. */
28 /* Specify this in a cover file to provide bi-architecture (32/64) support. */
29 /* #define SPARC_BI_ARCH */
31 /* Macro used later in this file to determine default architecture. */
32 #define DEFAULT_ARCH32_P ((TARGET_DEFAULT & MASK_64BIT) == 0)
34 /* TARGET_ARCH{32,64} are the main macros to decide which of the two
35 architectures to compile for. We allow targets to choose compile time or
38 #if defined(__sparcv9) || defined(__arch64__)
39 #define TARGET_ARCH32 0
41 #define TARGET_ARCH32 1
45 #define TARGET_ARCH32 (! TARGET_64BIT)
47 #define TARGET_ARCH32 (DEFAULT_ARCH32_P)
48 #endif /* SPARC_BI_ARCH */
49 #endif /* IN_LIBGCC2 */
50 #define TARGET_ARCH64 (! TARGET_ARCH32)
52 /* Code model selection.
53 -mcmodel is used to select the v9 code model.
54 Different code models aren't supported for v7/8 code.
56 TARGET_CM_32: 32 bit address space, top 32 bits = 0,
57 pointers are 32 bits. Note that this isn't intended
60 TARGET_CM_MEDLOW: 32 bit address space, top 32 bits = 0,
61 avoid generating %uhi and %ulo terms,
64 TARGET_CM_MEDMID: 64 bit address space.
65 The executable must be in the low 16 TB of memory.
66 This corresponds to the low 44 bits, and the %[hml]44
67 relocs are used. The text segment has a maximum size
70 TARGET_CM_MEDANY: 64 bit address space.
71 The text and data segments have a maximum size of 31
72 bits and may be located anywhere. The maximum offset
73 from any instruction to the label _GLOBAL_OFFSET_TABLE_
76 TARGET_CM_EMBMEDANY: 64 bit address space.
77 The text and data segments have a maximum size of 31 bits
78 and may be located anywhere. Register %g4 contains
79 the start address of the data segment.
90 /* Value of -mcmodel specified by user. */
91 extern const char *sparc_cmodel_string;
93 extern enum cmodel sparc_cmodel;
95 /* V9 code model selection. */
96 #define TARGET_CM_MEDLOW (sparc_cmodel == CM_MEDLOW)
97 #define TARGET_CM_MEDMID (sparc_cmodel == CM_MEDMID)
98 #define TARGET_CM_MEDANY (sparc_cmodel == CM_MEDANY)
99 #define TARGET_CM_EMBMEDANY (sparc_cmodel == CM_EMBMEDANY)
101 #define SPARC_DEFAULT_CMODEL CM_32
103 /* This is call-clobbered in the normal ABI, but is reserved in the
104 home grown (aka upward compatible) embedded ABI. */
105 #define EMBMEDANY_BASE_REG "%g4"
107 /* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile,
108 and specified by the user via --with-cpu=foo.
109 This specifies the cpu implementation, not the architecture size. */
110 /* Note that TARGET_CPU_v9 is assumed to start the list of 64-bit
112 #define TARGET_CPU_sparc 0
113 #define TARGET_CPU_v7 0 /* alias for previous */
114 #define TARGET_CPU_sparclet 1
115 #define TARGET_CPU_sparclite 2
116 #define TARGET_CPU_v8 3 /* generic v8 implementation */
117 #define TARGET_CPU_supersparc 4
118 #define TARGET_CPU_hypersparc 5
119 #define TARGET_CPU_sparc86x 6
120 #define TARGET_CPU_sparclite86x 6
121 #define TARGET_CPU_v9 7 /* generic v9 implementation */
122 #define TARGET_CPU_sparcv9 7 /* alias */
123 #define TARGET_CPU_sparc64 7 /* alias */
124 #define TARGET_CPU_ultrasparc 8
125 #define TARGET_CPU_ultrasparc3 9
127 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
128 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \
129 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3
131 #define CPP_CPU32_DEFAULT_SPEC ""
132 #define ASM_CPU32_DEFAULT_SPEC ""
134 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9
135 /* ??? What does Sun's CC pass? */
136 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
137 /* ??? It's not clear how other assemblers will handle this, so by default
138 use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case
139 is handled in sol2.h. */
140 #define ASM_CPU64_DEFAULT_SPEC "-Av9"
142 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc
143 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
144 #define ASM_CPU64_DEFAULT_SPEC "-Av9a"
146 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3
147 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
148 #define ASM_CPU64_DEFAULT_SPEC "-Av9b"
153 #define CPP_CPU64_DEFAULT_SPEC ""
154 #define ASM_CPU64_DEFAULT_SPEC ""
156 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc \
157 || TARGET_CPU_DEFAULT == TARGET_CPU_v8
158 #define CPP_CPU32_DEFAULT_SPEC ""
159 #define ASM_CPU32_DEFAULT_SPEC ""
162 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet
163 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclet__"
164 #define ASM_CPU32_DEFAULT_SPEC "-Asparclet"
167 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite
168 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite__"
169 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
172 #if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc
173 #define CPP_CPU32_DEFAULT_SPEC "-D__supersparc__ -D__sparc_v8__"
174 #define ASM_CPU32_DEFAULT_SPEC ""
177 #if TARGET_CPU_DEFAULT == TARGET_CPU_hypersparc
178 #define CPP_CPU32_DEFAULT_SPEC "-D__hypersparc__ -D__sparc_v8__"
179 #define ASM_CPU32_DEFAULT_SPEC ""
182 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite86x
183 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite86x__"
184 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
189 #if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC)
190 #error Unrecognized value in TARGET_CPU_DEFAULT.
195 #define CPP_CPU_DEFAULT_SPEC \
196 (DEFAULT_ARCH32_P ? "\
197 %{m64:" CPP_CPU64_DEFAULT_SPEC "} \
198 %{!m64:" CPP_CPU32_DEFAULT_SPEC "} \
200 %{m32:" CPP_CPU32_DEFAULT_SPEC "} \
201 %{!m32:" CPP_CPU64_DEFAULT_SPEC "} \
203 #define ASM_CPU_DEFAULT_SPEC \
204 (DEFAULT_ARCH32_P ? "\
205 %{m64:" ASM_CPU64_DEFAULT_SPEC "} \
206 %{!m64:" ASM_CPU32_DEFAULT_SPEC "} \
208 %{m32:" ASM_CPU32_DEFAULT_SPEC "} \
209 %{!m32:" ASM_CPU64_DEFAULT_SPEC "} \
212 #else /* !SPARC_BI_ARCH */
214 #define CPP_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? CPP_CPU32_DEFAULT_SPEC : CPP_CPU64_DEFAULT_SPEC)
215 #define ASM_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? ASM_CPU32_DEFAULT_SPEC : ASM_CPU64_DEFAULT_SPEC)
217 #endif /* !SPARC_BI_ARCH */
219 /* Define macros to distinguish architectures. */
221 /* Common CPP definitions used by CPP_SPEC amongst the various targets
222 for handling -mcpu=xxx switches. */
223 #define CPP_CPU_SPEC "\
224 %{msoft-float:-D_SOFT_FLOAT} \
226 %{msparclite:-D__sparclite__} \
227 %{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \
228 %{mv8:-D__sparc_v8__} \
229 %{msupersparc:-D__supersparc__ -D__sparc_v8__} \
230 %{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \
231 %{mcpu=sparclite:-D__sparclite__} \
232 %{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \
233 %{mcpu=v8:-D__sparc_v8__} \
234 %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \
235 %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \
236 %{mcpu=sparclite86x:-D__sparclite86x__} \
237 %{mcpu=v9:-D__sparc_v9__} \
238 %{mcpu=ultrasparc:-D__sparc_v9__} \
239 %{mcpu=ultrasparc3:-D__sparc_v9__} \
240 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \
243 /* ??? The GCC_NEW_VARARGS macro is now obsolete, because gcc always uses
244 the right varags.h file when bootstrapping. */
245 /* ??? It's not clear what value we want to use for -Acpu/machine for
246 sparc64 in 32 bit environments, so for now we only use `sparc64' in
247 64 bit environments. */
249 #define CPP_ARCH32_SPEC "-D__GCC_NEW_VARARGS__ -Acpu=sparc -Amachine=sparc"
250 #define CPP_ARCH64_SPEC "-D__arch64__ -Acpu=sparc64 -Amachine=sparc64"
252 #define CPP_ARCH_DEFAULT_SPEC \
253 (DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC)
255 #define CPP_ARCH_SPEC "\
256 %{m32:%(cpp_arch32)} \
257 %{m64:%(cpp_arch64)} \
258 %{!m32:%{!m64:%(cpp_arch_default)}} \
261 /* Macros to distinguish endianness. */
262 #define CPP_ENDIAN_SPEC "\
263 %{mlittle-endian:-D__LITTLE_ENDIAN__} \
264 %{mlittle-endian-data:-D__LITTLE_ENDIAN_DATA__}"
266 /* Macros to distinguish the particular subtarget. */
267 #define CPP_SUBTARGET_SPEC ""
269 #define CPP_SPEC "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_subtarget)"
271 /* Prevent error on `-sun4' and `-target sun4' options. */
272 /* This used to translate -dalign to -malign, but that is no good
273 because it can't turn off the usual meaning of making debugging dumps. */
274 /* Translate old style -m<cpu> into new style -mcpu=<cpu>.
275 ??? Delete support for -m<cpu> for 2.9. */
278 %{sun4:} %{target:} \
279 %{mcypress:-mcpu=cypress} \
280 %{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \
281 %{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \
284 /* Override in target specific files. */
285 #define ASM_CPU_SPEC "\
286 %{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \
287 %{msparclite:-Asparclite} \
288 %{mf930:-Asparclite} %{mf934:-Asparclite} \
289 %{mcpu=sparclite:-Asparclite} \
290 %{mcpu=sparclite86x:-Asparclite} \
291 %{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \
292 %{mv8plus:-Av8plus} \
294 %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \
295 %{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \
296 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_cpu_default)}}}}}}} \
299 /* Word size selection, among other things.
300 This is what GAS uses. Add %(asm_arch) to ASM_SPEC to enable. */
302 #define ASM_ARCH32_SPEC "-32"
303 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
304 #define ASM_ARCH64_SPEC "-64 -no-undeclared-regs"
306 #define ASM_ARCH64_SPEC "-64"
308 #define ASM_ARCH_DEFAULT_SPEC \
309 (DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC)
311 #define ASM_ARCH_SPEC "\
312 %{m32:%(asm_arch32)} \
313 %{m64:%(asm_arch64)} \
314 %{!m32:%{!m64:%(asm_arch_default)}} \
317 #ifdef HAVE_AS_RELAX_OPTION
318 #define ASM_RELAX_SPEC "%{!mno-relax:-relax}"
320 #define ASM_RELAX_SPEC ""
323 /* Special flags to the Sun-4 assembler when using pipe for input. */
326 %{R} %{!pg:%{!p:%{fpic:-k} %{fPIC:-k}}} %{keep-local-as-symbols:-L} \
327 %(asm_cpu) %(asm_relax)"
329 #define AS_NEEDS_DASH_FOR_PIPED_INPUT
331 /* This macro defines names of additional specifications to put in the specs
332 that can be used in various specifications like CC1_SPEC. Its definition
333 is an initializer with a subgrouping for each command option.
335 Each subgrouping contains a string constant, that defines the
336 specification name, and a string constant that used by the GNU CC driver
339 Do not define this macro if it does not need to do anything. */
341 #define EXTRA_SPECS \
342 { "cpp_cpu", CPP_CPU_SPEC }, \
343 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
344 { "cpp_arch32", CPP_ARCH32_SPEC }, \
345 { "cpp_arch64", CPP_ARCH64_SPEC }, \
346 { "cpp_arch_default", CPP_ARCH_DEFAULT_SPEC },\
347 { "cpp_arch", CPP_ARCH_SPEC }, \
348 { "cpp_endian", CPP_ENDIAN_SPEC }, \
349 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \
350 { "asm_cpu", ASM_CPU_SPEC }, \
351 { "asm_cpu_default", ASM_CPU_DEFAULT_SPEC }, \
352 { "asm_arch32", ASM_ARCH32_SPEC }, \
353 { "asm_arch64", ASM_ARCH64_SPEC }, \
354 { "asm_relax", ASM_RELAX_SPEC }, \
355 { "asm_arch_default", ASM_ARCH_DEFAULT_SPEC },\
356 { "asm_arch", ASM_ARCH_SPEC }, \
357 SUBTARGET_EXTRA_SPECS
359 #define SUBTARGET_EXTRA_SPECS
361 /* Because libgcc can generate references back to libc (via .umul etc.) we have
362 to list libc again after the second libgcc. */
363 #define LINK_GCC_C_SEQUENCE_SPEC "%G %L %G %L"
366 #define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int")
367 #define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int")
369 /* ??? This should be 32 bits for v9 but what can we do? */
370 #define WCHAR_TYPE "short unsigned int"
371 #define WCHAR_TYPE_SIZE 16
373 /* Show we can debug even without a frame pointer. */
374 #define CAN_DEBUG_WITHOUT_FP
376 #define OVERRIDE_OPTIONS sparc_override_options ()
378 /* Generate DBX debugging information. */
380 #define DBX_DEBUGGING_INFO 1
382 /* Run-time compilation parameters selecting different hardware subsets. */
384 extern int target_flags;
386 /* Nonzero if we should generate code to use the fpu. */
388 #define TARGET_FPU (target_flags & MASK_FPU)
390 /* Nonzero if we should assume that double pointers might be unaligned.
391 This can happen when linking gcc compiled code with other compilers,
392 because the ABI only guarantees 4 byte alignment. */
393 #define MASK_UNALIGNED_DOUBLES 4
394 #define TARGET_UNALIGNED_DOUBLES (target_flags & MASK_UNALIGNED_DOUBLES)
396 /* Nonzero means that we should generate code for a v8 sparc. */
398 #define TARGET_V8 (target_flags & MASK_V8)
400 /* Nonzero means that we should generate code for a sparclite.
401 This enables the sparclite specific instructions, but does not affect
402 whether FPU instructions are emitted. */
403 #define MASK_SPARCLITE 0x10
404 #define TARGET_SPARCLITE (target_flags & MASK_SPARCLITE)
406 /* Nonzero if we're compiling for the sparclet. */
407 #define MASK_SPARCLET 0x20
408 #define TARGET_SPARCLET (target_flags & MASK_SPARCLET)
410 /* Nonzero if we're compiling for v9 sparc.
411 Note that v9's can run in 32 bit mode so this doesn't necessarily mean
412 the word size is 64. */
414 #define TARGET_V9 (target_flags & MASK_V9)
416 /* Nonzero to generate code that uses the instructions deprecated in
417 the v9 architecture. This option only applies to v9 systems. */
418 /* ??? This isn't user selectable yet. It's used to enable such insns
419 on 32 bit v9 systems and for the moment they're permanently disabled
420 on 64 bit v9 systems. */
421 #define MASK_DEPRECATED_V8_INSNS 0x80
422 #define TARGET_DEPRECATED_V8_INSNS (target_flags & MASK_DEPRECATED_V8_INSNS)
424 /* Mask of all CPU selection flags. */
426 (MASK_V8 + MASK_SPARCLITE + MASK_SPARCLET + MASK_V9 + MASK_DEPRECATED_V8_INSNS)
428 /* Nonzero means don't pass `-assert pure-text' to the linker. */
429 #define MASK_IMPURE_TEXT 0x100
430 #define TARGET_IMPURE_TEXT (target_flags & MASK_IMPURE_TEXT)
432 /* Nonzero means that we should generate code using a flat register window
433 model, i.e. no save/restore instructions are generated, which is
434 compatible with normal sparc code.
435 The frame pointer is %i7 instead of %fp. */
436 #define MASK_FLAT 0x200
437 #define TARGET_FLAT (target_flags & MASK_FLAT)
439 /* Nonzero means use the registers that the SPARC ABI reserves for
440 application software. This must be the default to coincide with the
441 setting in FIXED_REGISTERS. */
442 #define MASK_APP_REGS 0x400
443 #define TARGET_APP_REGS (target_flags & MASK_APP_REGS)
445 /* Option to select how quad word floating point is implemented.
446 When TARGET_HARD_QUAD is true, we use the hardware quad instructions.
447 Otherwise, we use the SPARC ABI quad library functions. */
448 #define MASK_HARD_QUAD 0x800
449 #define TARGET_HARD_QUAD (target_flags & MASK_HARD_QUAD)
451 /* Nonzero on little-endian machines. */
452 /* ??? Little endian support currently only exists for sparclet-aout and
453 sparc64-elf configurations. May eventually want to expand the support
454 to all targets, but for now it's kept local to only those two. */
455 #define MASK_LITTLE_ENDIAN 0x1000
456 #define TARGET_LITTLE_ENDIAN (target_flags & MASK_LITTLE_ENDIAN)
458 /* 0x2000, 0x4000 are unused */
460 /* Nonzero if pointers are 64 bits. */
461 #define MASK_PTR64 0x8000
462 #define TARGET_PTR64 (target_flags & MASK_PTR64)
464 /* Nonzero if generating code to run in a 64 bit environment.
465 This is intended to only be used by TARGET_ARCH{32,64} as they are the
466 mechanism used to control compile time or run time selection. */
467 #define MASK_64BIT 0x10000
468 #define TARGET_64BIT (target_flags & MASK_64BIT)
470 /* 0x20000,0x40000 unused */
472 /* Nonzero means use a stack bias of 2047. Stack offsets are obtained by
473 adding 2047 to %sp. This option is for v9 only and is the default. */
474 #define MASK_STACK_BIAS 0x80000
475 #define TARGET_STACK_BIAS (target_flags & MASK_STACK_BIAS)
477 /* 0x100000,0x200000 unused */
479 /* Nonzero means -m{,no-}fpu was passed on the command line. */
480 #define MASK_FPU_SET 0x400000
481 #define TARGET_FPU_SET (target_flags & MASK_FPU_SET)
483 /* Use the UltraSPARC Visual Instruction Set extensions. */
484 #define MASK_VIS 0x1000000
485 #define TARGET_VIS (target_flags & MASK_VIS)
487 /* Compile for Solaris V8+. 32 bit Solaris preserves the high bits of
488 the current out and global registers and Linux 2.2+ as well. */
489 #define MASK_V8PLUS 0x2000000
490 #define TARGET_V8PLUS (target_flags & MASK_V8PLUS)
492 /* Force a the fastest alignment on structures to take advantage of
494 #define MASK_FASTER_STRUCTS 0x4000000
495 #define TARGET_FASTER_STRUCTS (target_flags & MASK_FASTER_STRUCTS)
497 /* Use IEEE quad long double. */
498 #define MASK_LONG_DOUBLE_128 0x8000000
499 #define TARGET_LONG_DOUBLE_128 (target_flags & MASK_LONG_DOUBLE_128)
501 /* TARGET_HARD_MUL: Use hardware multiply instructions but not %y.
502 TARGET_HARD_MUL32: Use hardware multiply instructions with rd %y
503 to get high 32 bits. False in V8+ or V9 because multiply stores
504 a 64 bit result in a register. */
506 #define TARGET_HARD_MUL32 \
507 ((TARGET_V8 || TARGET_SPARCLITE \
508 || TARGET_SPARCLET || TARGET_DEPRECATED_V8_INSNS) \
509 && ! TARGET_V8PLUS && TARGET_ARCH32)
511 #define TARGET_HARD_MUL \
512 (TARGET_V8 || TARGET_SPARCLITE || TARGET_SPARCLET \
513 || TARGET_DEPRECATED_V8_INSNS || TARGET_V8PLUS)
516 /* Macro to define tables used to set the flags.
517 This is a list in braces of pairs in braces,
518 each pair being { "NAME", VALUE }
519 where VALUE is the bits to set or minus the bits to clear.
520 An empty string NAME is used to identify the default VALUE. */
522 #define TARGET_SWITCHES \
523 { {"fpu", MASK_FPU | MASK_FPU_SET, \
524 N_("Use hardware fp") }, \
525 {"no-fpu", -MASK_FPU, \
526 N_("Do not use hardware fp") }, \
527 {"no-fpu", MASK_FPU_SET, NULL, }, \
528 {"hard-float", MASK_FPU | MASK_FPU_SET, \
529 N_("Use hardware fp") }, \
530 {"soft-float", -MASK_FPU, \
531 N_("Do not use hardware fp") }, \
532 {"soft-float", MASK_FPU_SET, NULL }, \
533 {"unaligned-doubles", MASK_UNALIGNED_DOUBLES, \
534 N_("Assume possible double misalignment") }, \
535 {"no-unaligned-doubles", -MASK_UNALIGNED_DOUBLES, \
536 N_("Assume all doubles are aligned") }, \
537 {"impure-text", MASK_IMPURE_TEXT, \
538 N_("Pass -assert pure-text to linker") }, \
539 {"no-impure-text", -MASK_IMPURE_TEXT, \
540 N_("Do not pass -assert pure-text to linker") }, \
541 {"flat", MASK_FLAT, \
542 N_("Use flat register window model") }, \
543 {"no-flat", -MASK_FLAT, \
544 N_("Do not use flat register window model") }, \
545 {"app-regs", MASK_APP_REGS, \
546 N_("Use ABI reserved registers") }, \
547 {"no-app-regs", -MASK_APP_REGS, \
548 N_("Do not use ABI reserved registers") }, \
549 {"hard-quad-float", MASK_HARD_QUAD, \
550 N_("Use hardware quad fp instructions") }, \
551 {"soft-quad-float", -MASK_HARD_QUAD, \
552 N_("Do not use hardware quad fp instructions") }, \
553 {"v8plus", MASK_V8PLUS, \
554 N_("Compile for v8plus ABI") }, \
555 {"no-v8plus", -MASK_V8PLUS, \
556 N_("Do not compile for v8plus ABI") }, \
558 N_("Utilize Visual Instruction Set") }, \
559 {"no-vis", -MASK_VIS, \
560 N_("Do not utilize Visual Instruction Set") }, \
561 /* ??? These are deprecated, coerced to -mcpu=. Delete in 2.9. */ \
563 N_("Optimize for Cypress processors") }, \
565 N_("Optimize for SPARCLite processors") }, \
567 N_("Optimize for F930 processors") }, \
569 N_("Optimize for F934 processors") }, \
571 N_("Use V8 SPARC ISA") }, \
573 N_("Optimize for SuperSPARC processors") }, \
574 /* End of deprecated options. */ \
575 {"ptr64", MASK_PTR64, \
576 N_("Pointers are 64-bit") }, \
577 {"ptr32", -MASK_PTR64, \
578 N_("Pointers are 32-bit") }, \
579 {"32", -MASK_64BIT, \
580 N_("Use 32-bit ABI") }, \
582 N_("Use 64-bit ABI") }, \
583 {"stack-bias", MASK_STACK_BIAS, \
584 N_("Use stack bias") }, \
585 {"no-stack-bias", -MASK_STACK_BIAS, \
586 N_("Do not use stack bias") }, \
587 {"faster-structs", MASK_FASTER_STRUCTS, \
588 N_("Use structs on stronger alignment for double-word copies") }, \
589 {"no-faster-structs", -MASK_FASTER_STRUCTS, \
590 N_("Do not use structs on stronger alignment for double-word copies") }, \
592 N_("Optimize tail call instructions in assembler and linker") }, \
594 N_("Do not optimize tail call instructions in assembler or linker") }, \
596 { "", TARGET_DEFAULT, ""}}
598 /* MASK_APP_REGS must always be the default because that's what
599 FIXED_REGISTERS is set to and -ffixed- is processed before
600 CONDITIONAL_REGISTER_USAGE is called (where we process -mno-app-regs). */
601 #define TARGET_DEFAULT (MASK_APP_REGS + MASK_FPU)
603 /* This is meant to be redefined in target specific files. */
604 #define SUBTARGET_SWITCHES
607 These must match the values for the cpu attribute in sparc.md. */
608 enum processor_type {
612 PROCESSOR_SUPERSPARC,
616 PROCESSOR_HYPERSPARC,
617 PROCESSOR_SPARCLITE86X,
621 PROCESSOR_ULTRASPARC,
622 PROCESSOR_ULTRASPARC3
625 /* This is set from -m{cpu,tune}=xxx. */
626 extern enum processor_type sparc_cpu;
628 /* Recast the cpu class to be the cpu attribute.
629 Every file includes us, but not every file includes insn-attr.h. */
630 #define sparc_cpu_attr ((enum attr_cpu) sparc_cpu)
632 #define TARGET_OPTIONS \
634 { "cpu=", &sparc_select[1].string, \
635 N_("Use features of and schedule code for given CPU") }, \
636 { "tune=", &sparc_select[2].string, \
637 N_("Schedule code for given CPU") }, \
638 { "cmodel=", &sparc_cmodel_string, \
639 N_("Use given SPARC code model") }, \
643 /* This is meant to be redefined in target specific files. */
644 #define SUBTARGET_OPTIONS
646 /* sparc_select[0] is reserved for the default cpu. */
647 struct sparc_cpu_select
650 const char *const name;
651 const int set_tune_p;
652 const int set_arch_p;
655 extern struct sparc_cpu_select sparc_select[];
657 /* target machine storage layout */
659 /* Define this if most significant bit is lowest numbered
660 in instructions that operate on numbered bit-fields. */
661 #define BITS_BIG_ENDIAN 1
663 /* Define this if most significant byte of a word is the lowest numbered. */
664 #define BYTES_BIG_ENDIAN 1
666 /* Define this if most significant word of a multiword number is the lowest
668 #define WORDS_BIG_ENDIAN 1
670 /* Define this to set the endianness to use in libgcc2.c, which can
671 not depend on target_flags. */
672 #if defined (__LITTLE_ENDIAN__) || defined(__LITTLE_ENDIAN_DATA__)
673 #define LIBGCC2_WORDS_BIG_ENDIAN 0
675 #define LIBGCC2_WORDS_BIG_ENDIAN 1
678 #define MAX_BITS_PER_WORD 64
680 /* Width of a word, in units (bytes). */
681 #define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4)
683 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
685 #define MIN_UNITS_PER_WORD 4
688 /* Now define the sizes of the C data types. */
690 #define SHORT_TYPE_SIZE 16
691 #define INT_TYPE_SIZE 32
692 #define LONG_TYPE_SIZE (TARGET_ARCH64 ? 64 : 32)
693 #define LONG_LONG_TYPE_SIZE 64
694 #define FLOAT_TYPE_SIZE 32
695 #define DOUBLE_TYPE_SIZE 64
698 #define MAX_LONG_TYPE_SIZE 64
702 /* ??? This does not work in SunOS 4.x, so it is not enabled here.
703 Instead, it is enabled in sol2.h, because it does work under Solaris. */
704 /* Define for support of TFmode long double.
705 SPARC ABI says that long double is 4 words. */
706 #define LONG_DOUBLE_TYPE_SIZE 128
709 /* Width in bits of a pointer.
710 See also the macro `Pmode' defined below. */
711 #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32)
713 /* If we have to extend pointers (only when TARGET_ARCH64 and not
714 TARGET_PTR64), we want to do it unsigned. This macro does nothing
715 if ptr_mode and Pmode are the same. */
716 #define POINTERS_EXTEND_UNSIGNED 1
718 /* A macro to update MODE and UNSIGNEDP when an object whose type
719 is TYPE and which has the specified mode and signedness is to be
720 stored in a register. This macro is only called when TYPE is a
722 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
724 && GET_MODE_CLASS (MODE) == MODE_INT \
725 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
728 /* Define this macro if the promotion described by PROMOTE_MODE
729 should also be done for outgoing function arguments. */
730 /* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op
731 for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test
733 #define PROMOTE_FUNCTION_ARGS
735 /* Define this macro if the promotion described by PROMOTE_MODE
736 should also be done for the return value of functions.
737 If this macro is defined, FUNCTION_VALUE must perform the same
738 promotions done by PROMOTE_MODE. */
739 /* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op
740 for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test
742 #define PROMOTE_FUNCTION_RETURN
744 /* Define this macro if the promotion described by PROMOTE_MODE
745 should _only_ be performed for outgoing function arguments or
746 function return values, as specified by PROMOTE_FUNCTION_ARGS
747 and PROMOTE_FUNCTION_RETURN, respectively. */
748 /* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op
749 for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test
750 for this value. For TARGET_ARCH64 we need it, as we don't have instructions
751 for arithmetic operations which do zero/sign extension at the same time,
752 so without this we end up with a srl/sra after every assignment to an
753 user variable, which means very very bad code. */
754 #define PROMOTE_FOR_CALL_ONLY
756 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
757 #define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
759 /* Boundary (in *bits*) on which stack pointer should be aligned. */
760 #define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64)
762 /* ALIGN FRAMES on double word boundaries */
764 #define SPARC_STACK_ALIGN(LOC) \
765 (TARGET_ARCH64 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7))
767 /* Allocation boundary (in *bits*) for the code of a function. */
768 #define FUNCTION_BOUNDARY 32
770 /* Alignment of field after `int : 0' in a structure. */
771 #define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
773 /* Every structure's size must be a multiple of this. */
774 #define STRUCTURE_SIZE_BOUNDARY 8
776 /* A bit-field declared as `int' forces `int' alignment for the struct. */
777 #define PCC_BITFIELD_TYPE_MATTERS 1
779 /* No data type wants to be aligned rounder than this. */
780 #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64)
782 /* The best alignment to use in cases where we have a choice. */
783 #define FASTEST_ALIGNMENT 64
785 /* Define this macro as an expression for the alignment of a structure
786 (given by STRUCT as a tree node) if the alignment computed in the
787 usual way is COMPUTED and the alignment explicitly specified was
790 The default is to use SPECIFIED if it is larger; otherwise, use
791 the smaller of COMPUTED and `BIGGEST_ALIGNMENT' */
792 #define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \
793 (TARGET_FASTER_STRUCTS ? \
794 ((TREE_CODE (STRUCT) == RECORD_TYPE \
795 || TREE_CODE (STRUCT) == UNION_TYPE \
796 || TREE_CODE (STRUCT) == QUAL_UNION_TYPE) \
797 && TYPE_FIELDS (STRUCT) != 0 \
798 ? MAX (MAX ((COMPUTED), (SPECIFIED)), BIGGEST_ALIGNMENT) \
799 : MAX ((COMPUTED), (SPECIFIED))) \
800 : MAX ((COMPUTED), (SPECIFIED)))
802 /* Make strings word-aligned so strcpy from constants will be faster. */
803 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
804 ((TREE_CODE (EXP) == STRING_CST \
805 && (ALIGN) < FASTEST_ALIGNMENT) \
806 ? FASTEST_ALIGNMENT : (ALIGN))
808 /* Make arrays of chars word-aligned for the same reasons. */
809 #define DATA_ALIGNMENT(TYPE, ALIGN) \
810 (TREE_CODE (TYPE) == ARRAY_TYPE \
811 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
812 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
814 /* Set this nonzero if move instructions will actually fail to work
815 when given unaligned data. */
816 #define STRICT_ALIGNMENT 1
818 /* Things that must be doubleword aligned cannot go in the text section,
819 because the linker fails to align the text section enough!
820 Put them in the data section. This macro is only used in this file. */
821 #define MAX_TEXT_ALIGN 32
823 /* This forces all variables and constants to the data section when PIC.
824 This is because the SunOS 4 shared library scheme thinks everything in
825 text is a function, and patches the address to point to a loader stub. */
826 /* This is defined to zero for every system which doesn't use the a.out object
828 #ifndef SUNOS4_SHARED_LIBRARIES
829 #define SUNOS4_SHARED_LIBRARIES 0
832 /* Standard register usage. */
834 /* Number of actual hardware registers.
835 The hardware registers are assigned numbers for the compiler
836 from 0 to just below FIRST_PSEUDO_REGISTER.
837 All registers that the compiler knows about must be given numbers,
838 even those that are not normally considered general registers.
840 SPARC has 32 integer registers and 32 floating point registers.
841 64 bit SPARC has 32 additional fp regs, but the odd numbered ones are not
842 accessible. We still account for them to simplify register computations
843 (eg: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so
845 Register 100 is used as the integer condition code register.
846 Register 101 is used as the soft frame pointer register. */
848 #define FIRST_PSEUDO_REGISTER 102
850 #define SPARC_FIRST_FP_REG 32
851 /* Additional V9 fp regs. */
852 #define SPARC_FIRST_V9_FP_REG 64
853 #define SPARC_LAST_V9_FP_REG 95
854 /* V9 %fcc[0123]. V8 uses (figuratively) %fcc0. */
855 #define SPARC_FIRST_V9_FCC_REG 96
856 #define SPARC_LAST_V9_FCC_REG 99
858 #define SPARC_FCC_REG 96
859 /* Integer CC reg. We don't distinguish %icc from %xcc. */
860 #define SPARC_ICC_REG 100
862 /* Nonzero if REGNO is an fp reg. */
863 #define SPARC_FP_REG_P(REGNO) \
864 ((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG)
866 /* Argument passing regs. */
867 #define SPARC_OUTGOING_INT_ARG_FIRST 8
868 #define SPARC_INCOMING_INT_ARG_FIRST (TARGET_FLAT ? 8 : 24)
869 #define SPARC_FP_ARG_FIRST 32
871 /* 1 for registers that have pervasive standard uses
872 and are not available for the register allocator.
875 g1 is free to use as temporary.
876 g2-g4 are reserved for applications. Gcc normally uses them as
877 temporaries, but this can be disabled via the -mno-app-regs option.
878 g5 through g7 are reserved for the operating system.
881 g1,g5 are free to use as temporaries, and are free to use between calls
882 if the call is to an external function via the PLT.
883 g4 is free to use as a temporary in the non-embedded case.
884 g4 is reserved in the embedded case.
885 g2-g3 are reserved for applications. Gcc normally uses them as
886 temporaries, but this can be disabled via the -mno-app-regs option.
887 g6-g7 are reserved for the operating system (or application in
889 ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must
890 currently be a fixed register until this pattern is rewritten.
891 Register 1 is also used when restoring call-preserved registers in large
894 Registers fixed in arch32 and not arch64 (or vice-versa) are marked in
895 CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-.
898 #define FIXED_REGISTERS \
899 {1, 0, 2, 2, 2, 2, 1, 1, \
900 0, 0, 0, 0, 0, 0, 1, 0, \
901 0, 0, 0, 0, 0, 0, 0, 0, \
902 0, 0, 0, 0, 0, 0, 1, 1, \
904 0, 0, 0, 0, 0, 0, 0, 0, \
905 0, 0, 0, 0, 0, 0, 0, 0, \
906 0, 0, 0, 0, 0, 0, 0, 0, \
907 0, 0, 0, 0, 0, 0, 0, 0, \
909 0, 0, 0, 0, 0, 0, 0, 0, \
910 0, 0, 0, 0, 0, 0, 0, 0, \
911 0, 0, 0, 0, 0, 0, 0, 0, \
912 0, 0, 0, 0, 0, 0, 0, 0, \
916 /* 1 for registers not available across function calls.
917 These must include the FIXED_REGISTERS and also any
918 registers that can be used without being saved.
919 The latter must include the registers where values are returned
920 and the register where structure-value addresses are passed.
921 Aside from that, you can include as many other registers as you like. */
923 #define CALL_USED_REGISTERS \
924 {1, 1, 1, 1, 1, 1, 1, 1, \
925 1, 1, 1, 1, 1, 1, 1, 1, \
926 0, 0, 0, 0, 0, 0, 0, 0, \
927 0, 0, 0, 0, 0, 0, 1, 1, \
929 1, 1, 1, 1, 1, 1, 1, 1, \
930 1, 1, 1, 1, 1, 1, 1, 1, \
931 1, 1, 1, 1, 1, 1, 1, 1, \
932 1, 1, 1, 1, 1, 1, 1, 1, \
934 1, 1, 1, 1, 1, 1, 1, 1, \
935 1, 1, 1, 1, 1, 1, 1, 1, \
936 1, 1, 1, 1, 1, 1, 1, 1, \
937 1, 1, 1, 1, 1, 1, 1, 1, \
941 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
942 they won't be allocated. */
944 #define CONDITIONAL_REGISTER_USAGE \
947 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
949 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
950 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
952 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */ \
953 /* then honor it. */ \
954 if (TARGET_ARCH32 && fixed_regs[5]) \
956 else if (TARGET_ARCH64 && fixed_regs[5] == 2) \
961 for (regno = SPARC_FIRST_V9_FP_REG; \
962 regno <= SPARC_LAST_V9_FP_REG; \
964 fixed_regs[regno] = 1; \
965 /* %fcc0 is used by v8 and v9. */ \
966 for (regno = SPARC_FIRST_V9_FCC_REG + 1; \
967 regno <= SPARC_LAST_V9_FCC_REG; \
969 fixed_regs[regno] = 1; \
974 for (regno = 32; regno < SPARC_LAST_V9_FCC_REG; regno++) \
975 fixed_regs[regno] = 1; \
977 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */ \
978 /* then honor it. Likewise with g3 and g4. */ \
979 if (fixed_regs[2] == 2) \
980 fixed_regs[2] = ! TARGET_APP_REGS; \
981 if (fixed_regs[3] == 2) \
982 fixed_regs[3] = ! TARGET_APP_REGS; \
983 if (TARGET_ARCH32 && fixed_regs[4] == 2) \
984 fixed_regs[4] = ! TARGET_APP_REGS; \
985 else if (TARGET_CM_EMBMEDANY) \
987 else if (fixed_regs[4] == 2) \
992 /* Let the compiler believe the frame pointer is still \
993 %fp, but output it as %i7. */ \
994 fixed_regs[31] = 1; \
995 reg_names[HARD_FRAME_POINTER_REGNUM] = "%i7"; \
996 /* Disable leaf functions */ \
997 memset (sparc_leaf_regs, 0, FIRST_PSEUDO_REGISTER); \
998 /* Make LEAF_REG_REMAP a noop. */ \
999 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
1000 leaf_reg_remap [regno] = regno; \
1005 /* Return number of consecutive hard regs needed starting at reg REGNO
1006 to hold something of mode MODE.
1007 This is ordinarily the length in words of a value of mode MODE
1008 but can be less for certain modes in special long registers.
1010 On SPARC, ordinary registers hold 32 bits worth;
1011 this means both integer and floating point registers.
1012 On v9, integer regs hold 64 bits worth; floating point regs hold
1013 32 bits worth (this includes the new fp regs as even the odd ones are
1014 included in the hard register count). */
1016 #define HARD_REGNO_NREGS(REGNO, MODE) \
1018 ? ((REGNO) < 32 || (REGNO) == FRAME_POINTER_REGNUM \
1019 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \
1020 : (GET_MODE_SIZE (MODE) + 3) / 4) \
1021 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1023 /* Due to the ARCH64 descrepancy above we must override this next
1025 #define REGMODE_NATURAL_SIZE(MODE) \
1026 ((TARGET_ARCH64 && FLOAT_MODE_P (MODE)) ? 4 : UNITS_PER_WORD)
1028 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
1029 See sparc.c for how we initialize this. */
1030 extern const int *hard_regno_mode_classes;
1031 extern int sparc_mode_class[];
1033 /* ??? Because of the funny way we pass parameters we should allow certain
1034 ??? types of float/complex values to be in integer registers during
1035 ??? RTL generation. This only matters on arch32. */
1036 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1037 ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0)
1039 /* Value is 1 if it is a good idea to tie two pseudo registers
1040 when one has mode MODE1 and one has mode MODE2.
1041 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1042 for any hard reg, then this must be 0 for correct output.
1044 For V9: SFmode can't be combined with other float modes, because they can't
1045 be allocated to the %d registers. Also, DFmode won't fit in odd %f
1046 registers, but SFmode will. */
1047 #define MODES_TIEABLE_P(MODE1, MODE2) \
1048 ((MODE1) == (MODE2) \
1049 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
1051 || (GET_MODE_CLASS (MODE1) != MODE_FLOAT \
1052 || (MODE1 != SFmode && MODE2 != SFmode)))))
1054 /* Specify the registers used for certain standard purposes.
1055 The values of these macros are register numbers. */
1057 /* SPARC pc isn't overloaded on a register that the compiler knows about. */
1058 /* #define PC_REGNUM */
1060 /* Register to use for pushing function arguments. */
1061 #define STACK_POINTER_REGNUM 14
1063 /* The stack bias (amount by which the hardware register is offset by). */
1064 #define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0)
1066 /* Actual top-of-stack address is 92/176 greater than the contents of the
1067 stack pointer register for !v9/v9. That is:
1068 - !v9: 64 bytes for the in and local registers, 4 bytes for structure return
1069 address, and 6*4 bytes for the 6 register parameters.
1070 - v9: 128 bytes for the in and local registers + 6*8 bytes for the integer
1072 #define STACK_POINTER_OFFSET (FIRST_PARM_OFFSET(0) + SPARC_STACK_BIAS)
1074 /* Base register for access to local variables of the function. */
1075 #define HARD_FRAME_POINTER_REGNUM 30
1077 /* The soft frame pointer does not have the stack bias applied. */
1078 #define FRAME_POINTER_REGNUM 101
1080 /* Given the stack bias, the stack pointer isn't actually aligned. */
1081 #define INIT_EXPANDERS \
1083 if (cfun && cfun->emit->regno_pointer_align && SPARC_STACK_BIAS) \
1085 REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = BITS_PER_UNIT; \
1086 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT; \
1090 /* Value should be nonzero if functions must have frame pointers.
1091 Zero means the frame pointer need not be set up (and parms
1092 may be accessed via the stack pointer) in functions that seem suitable.
1093 This is computed in `reload', in reload1.c.
1094 Used in flow.c, global.c, and reload1.c.
1096 Being a non-leaf function does not mean a frame pointer is needed in the
1097 flat window model. However, the debugger won't be able to backtrace through
1099 #define FRAME_POINTER_REQUIRED \
1101 ? (current_function_calls_alloca \
1102 || !leaf_function_p ()) \
1103 : ! (leaf_function_p () && only_leaf_regs_used ()))
1105 /* Base register for access to arguments of the function. */
1106 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM
1108 /* Register in which static-chain is passed to a function. This must
1109 not be a register used by the prologue. */
1110 #define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2)
1112 /* Register which holds offset table for position-independent
1115 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 23 : INVALID_REGNUM)
1117 /* Pick a default value we can notice from override_options:
1119 v9: Default is off. */
1121 #define DEFAULT_PCC_STRUCT_RETURN -1
1123 /* SPARC ABI says that quad-precision floats and all structures are returned
1125 For v9: unions <= 32 bytes in size are returned in int regs,
1126 structures up to 32 bytes are returned in int and fp regs. */
1128 #define RETURN_IN_MEMORY(TYPE) \
1130 ? (TYPE_MODE (TYPE) == BLKmode \
1131 || TYPE_MODE (TYPE) == TFmode \
1132 || TYPE_MODE (TYPE) == TCmode) \
1133 : (TYPE_MODE (TYPE) == BLKmode \
1134 && (unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) > 32))
1136 /* Functions which return large structures get the address
1137 to place the wanted value at offset 64 from the frame.
1138 Must reserve 64 bytes for the in and local registers.
1139 v9: Functions which return large structures get the address to place the
1140 wanted value from an invisible first argument. */
1141 /* Used only in other #defines in this file. */
1142 #define STRUCT_VALUE_OFFSET 64
1144 #define STRUCT_VALUE \
1147 : gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, \
1148 STRUCT_VALUE_OFFSET)))
1150 #define STRUCT_VALUE_INCOMING \
1153 : gen_rtx_MEM (Pmode, plus_constant (frame_pointer_rtx, \
1154 STRUCT_VALUE_OFFSET)))
1156 /* Define the classes of registers for register constraints in the
1157 machine description. Also define ranges of constants.
1159 One of the classes must always be named ALL_REGS and include all hard regs.
1160 If there is more than one class, another class must be named NO_REGS
1161 and contain no registers.
1163 The name GENERAL_REGS must be the name of a class (or an alias for
1164 another name such as ALL_REGS). This is the class of registers
1165 that is allowed by "g" or "r" in a register constraint.
1166 Also, registers outside this class are allocated only when
1167 instructions express preferences for them.
1169 The classes must be numbered in nondecreasing order; that is,
1170 a larger-numbered class must never be contained completely
1171 in a smaller-numbered class.
1173 For any two classes, it is very desirable that there be another
1174 class that represents their union. */
1176 /* The SPARC has various kinds of registers: general, floating point,
1177 and condition codes [well, it has others as well, but none that we
1178 care directly about].
1180 For v9 we must distinguish between the upper and lower floating point
1181 registers because the upper ones can't hold SFmode values.
1182 HARD_REGNO_MODE_OK won't help here because reload assumes that register(s)
1183 satisfying a group need for a class will also satisfy a single need for
1184 that class. EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp
1187 It is important that one class contains all the general and all the standard
1188 fp regs. Otherwise find_reg() won't properly allocate int regs for moves,
1189 because reg_class_record() will bias the selection in favor of fp regs,
1190 because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS,
1191 because FP_REGS > GENERAL_REGS.
1193 It is also important that one class contain all the general and all the
1194 fp regs. Otherwise when spilling a DFmode reg, it may be from EXTRA_FP_REGS
1195 but find_reloads() may use class GENERAL_OR_FP_REGS. This will cause
1196 allocate_reload_reg() to bypass it causing an abort because the compiler
1197 thinks it doesn't have a spill reg when in fact it does.
1199 v9 also has 4 floating point condition code registers. Since we don't
1200 have a class that is the union of FPCC_REGS with either of the others,
1201 it is important that it appear first. Otherwise the compiler will die
1202 trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its
1205 It is important that SPARC_ICC_REG have class NO_REGS. Otherwise combine
1206 may try to use it to hold an SImode value. See register_operand.
1207 ??? Should %fcc[0123] be handled similarly?
1210 enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS,
1211 EXTRA_FP_REGS, GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS,
1212 ALL_REGS, LIM_REG_CLASSES };
1214 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1216 /* Give names of register classes as strings for dump file. */
1218 #define REG_CLASS_NAMES \
1219 { "NO_REGS", "FPCC_REGS", "I64_REGS", "GENERAL_REGS", "FP_REGS", \
1220 "EXTRA_FP_REGS", "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", \
1223 /* Define which registers fit in which classes.
1224 This is an initializer for a vector of HARD_REG_SET
1225 of length N_REG_CLASSES. */
1227 #define REG_CLASS_CONTENTS \
1228 {{0, 0, 0, 0}, /* NO_REGS */ \
1229 {0, 0, 0, 0xf}, /* FPCC_REGS */ \
1230 {0xffff, 0, 0, 0}, /* I64_REGS */ \
1231 {-1, 0, 0, 0x20}, /* GENERAL_REGS */ \
1232 {0, -1, 0, 0}, /* FP_REGS */ \
1233 {0, -1, -1, 0}, /* EXTRA_FP_REGS */ \
1234 {-1, -1, 0, 0x20}, /* GENERAL_OR_FP_REGS */ \
1235 {-1, -1, -1, 0x20}, /* GENERAL_OR_EXTRA_FP_REGS */ \
1236 {-1, -1, -1, 0x3f}} /* ALL_REGS */
1238 /* The same information, inverted:
1239 Return the class number of the smallest class containing
1240 reg number REGNO. This could be a conditional expression
1241 or could index an array. */
1243 extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
1245 #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)]
1247 /* This is the order in which to allocate registers normally.
1249 We put %f0-%f7 last among the float registers, so as to make it more
1250 likely that a pseudo-register which dies in the float return register
1251 area will get allocated to the float return register, thus saving a move
1252 instruction at the end of the function.
1254 Similarly for integer return value registers.
1256 We know in this case that we will not end up with a leaf function.
1258 The register allocater is given the global and out registers first
1259 because these registers are call clobbered and thus less useful to
1260 global register allocation.
1262 Next we list the local and in registers. They are not call clobbered
1263 and thus very useful for global register allocation. We list the input
1264 registers before the locals so that it is more likely the incoming
1265 arguments received in those registers can just stay there and not be
1268 #define REG_ALLOC_ORDER \
1269 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \
1270 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \
1272 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \
1273 29, 28, 27, 26, 25, 24, 31, /* %i5-%i0,%i7 */\
1274 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \
1275 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \
1276 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \
1277 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \
1278 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \
1279 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \
1280 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \
1281 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \
1282 96, 97, 98, 99, /* %fcc0-3 */ \
1283 100, 0, 14, 30, 101} /* %icc, %g0, %o6, %i6, %sfp */
1285 /* This is the order in which to allocate registers for
1286 leaf functions. If all registers can fit in the global and
1287 output registers, then we have the possibility of having a leaf
1290 The macro actually mentioned the input registers first,
1291 because they get renumbered into the output registers once
1292 we know really do have a leaf function.
1294 To be more precise, this register allocation order is used
1295 when %o7 is found to not be clobbered right before register
1296 allocation. Normally, the reason %o7 would be clobbered is
1297 due to a call which could not be transformed into a sibling
1300 As a consequence, it is possible to use the leaf register
1301 allocation order and not end up with a leaf function. We will
1302 not get suboptimal register allocation in that case because by
1303 definition of being potentially leaf, there were no function
1304 calls. Therefore, allocation order within the local register
1305 window is not critical like it is when we do have function calls. */
1307 #define REG_LEAF_ALLOC_ORDER \
1308 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \
1309 29, 28, 27, 26, 25, 24, /* %i5-%i0 */ \
1311 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \
1312 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \
1313 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \
1314 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \
1315 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \
1316 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \
1317 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \
1318 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \
1319 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \
1320 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \
1321 96, 97, 98, 99, /* %fcc0-3 */ \
1322 100, 0, 14, 30, 31, 101} /* %icc, %g0, %o6, %i6, %i7, %sfp */
1324 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
1326 extern char sparc_leaf_regs[];
1327 #define LEAF_REGISTERS sparc_leaf_regs
1329 extern char leaf_reg_remap[];
1330 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO])
1332 /* The class value for index registers, and the one for base regs. */
1333 #define INDEX_REG_CLASS GENERAL_REGS
1334 #define BASE_REG_CLASS GENERAL_REGS
1336 /* Local macro to handle the two v9 classes of FP regs. */
1337 #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS)
1339 /* Get reg_class from a letter such as appears in the machine description.
1340 In the not-v9 case, coerce v9's 'e' class to 'f', so we can use 'e' in the
1341 .md file for v8 and v9.
1342 'd' and 'b' are used for single and double precision VIS operations,
1344 'h' is used for V8+ 64 bit global and out registers. */
1346 #define REG_CLASS_FROM_LETTER(C) \
1348 ? ((C) == 'f' ? FP_REGS \
1349 : (C) == 'e' ? EXTRA_FP_REGS \
1350 : (C) == 'c' ? FPCC_REGS \
1351 : ((C) == 'd' && TARGET_VIS) ? FP_REGS\
1352 : ((C) == 'b' && TARGET_VIS) ? EXTRA_FP_REGS\
1353 : ((C) == 'h' && TARGET_V8PLUS) ? I64_REGS\
1355 : ((C) == 'f' ? FP_REGS \
1356 : (C) == 'e' ? FP_REGS \
1357 : (C) == 'c' ? FPCC_REGS \
1360 /* The letters I, J, K, L and M in a register constraint string
1361 can be used to stand for particular ranges of immediate operands.
1362 This macro defines what the ranges are.
1363 C is the letter, and VALUE is a constant value.
1364 Return 1 if VALUE is in the range specified by C.
1366 `I' is used for the range of constants an insn can actually contain.
1367 `J' is used for the range which is just zero (since that is R0).
1368 `K' is used for constants which can be loaded with a single sethi insn.
1369 `L' is used for the range of constants supported by the movcc insns.
1370 `M' is used for the range of constants supported by the movrcc insns.
1371 `N' is like K, but for constants wider than 32 bits. */
1373 #define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400)
1374 #define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800)
1375 #define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000)
1376 /* 10 and 11 bit immediates are only used for a few specific insns.
1377 SMALL_INT is used throughout the port so we continue to use it. */
1378 #define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X)))
1379 /* 13 bit immediate, considering only the low 32 bits */
1380 #define SMALL_INT32(X) (SPARC_SIMM13_P (trunc_int_for_mode \
1381 (INTVAL (X), SImode)))
1382 #define SPARC_SETHI_P(X) \
1383 (((unsigned HOST_WIDE_INT) (X) \
1384 & ((unsigned HOST_WIDE_INT) 0x3ff - GET_MODE_MASK (SImode) - 1)) == 0)
1385 #define SPARC_SETHI32_P(X) \
1386 (SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode)))
1388 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1389 ((C) == 'I' ? SPARC_SIMM13_P (VALUE) \
1390 : (C) == 'J' ? (VALUE) == 0 \
1391 : (C) == 'K' ? SPARC_SETHI32_P (VALUE) \
1392 : (C) == 'L' ? SPARC_SIMM11_P (VALUE) \
1393 : (C) == 'M' ? SPARC_SIMM10_P (VALUE) \
1394 : (C) == 'N' ? SPARC_SETHI_P (VALUE) \
1397 /* Similar, but for floating constants, and defining letters G and H.
1398 Here VALUE is the CONST_DOUBLE rtx itself. */
1400 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1401 ((C) == 'G' ? fp_zero_operand (VALUE, GET_MODE (VALUE)) \
1402 : (C) == 'H' ? arith_double_operand (VALUE, DImode) \
1405 /* Given an rtx X being reloaded into a reg required to be
1406 in class CLASS, return the class of reg to actually use.
1407 In general this is just CLASS; but on some machines
1408 in some cases it is preferable to use a more restrictive class. */
1409 /* - We can't load constants into FP registers.
1410 - We can't load FP constants into integer registers when soft-float,
1411 because there is no soft-float pattern with a r/F constraint.
1412 - We can't load FP constants into integer registers for TFmode unless
1413 it is 0.0L, because there is no movtf pattern with a r/F constraint.
1414 - Try and reload integer constants (symbolic or otherwise) back into
1415 registers directly, rather than having them dumped to memory. */
1417 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1419 ? ((FP_REG_CLASS_P (CLASS) \
1420 || (CLASS) == GENERAL_OR_FP_REGS \
1421 || (CLASS) == GENERAL_OR_EXTRA_FP_REGS \
1422 || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1424 || (GET_MODE (X) == TFmode \
1425 && ! fp_zero_operand (X, TFmode))) \
1427 : (!FP_REG_CLASS_P (CLASS) \
1428 && GET_MODE_CLASS (GET_MODE (X)) == MODE_INT) \
1433 /* Return the register class of a scratch register needed to load IN into
1434 a register of class CLASS in MODE.
1436 We need a temporary when loading/storing a HImode/QImode value
1437 between memory and the FPU registers. This can happen when combine puts
1438 a paradoxical subreg in a float/fix conversion insn.
1440 We need a temporary when loading/storing a DFmode value between
1441 unaligned memory and the upper FPU registers. */
1443 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1444 ((FP_REG_CLASS_P (CLASS) \
1445 && ((MODE) == HImode || (MODE) == QImode) \
1446 && (GET_CODE (IN) == MEM \
1447 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1448 && true_regnum (IN) == -1))) \
1450 : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \
1451 && GET_CODE (IN) == MEM && TARGET_ARCH32 \
1452 && ! mem_min_alignment ((IN), 8)) \
1454 : (((TARGET_CM_MEDANY \
1455 && symbolic_operand ((IN), (MODE))) \
1456 || (TARGET_CM_EMBMEDANY \
1457 && text_segment_operand ((IN), (MODE)))) \
1462 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1463 ((FP_REG_CLASS_P (CLASS) \
1464 && ((MODE) == HImode || (MODE) == QImode) \
1465 && (GET_CODE (IN) == MEM \
1466 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1467 && true_regnum (IN) == -1))) \
1469 : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \
1470 && GET_CODE (IN) == MEM && TARGET_ARCH32 \
1471 && ! mem_min_alignment ((IN), 8)) \
1473 : (((TARGET_CM_MEDANY \
1474 && symbolic_operand ((IN), (MODE))) \
1475 || (TARGET_CM_EMBMEDANY \
1476 && text_segment_operand ((IN), (MODE)))) \
1481 /* On SPARC it is not possible to directly move data between
1482 GENERAL_REGS and FP_REGS. */
1483 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1484 (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2))
1486 /* Return the stack location to use for secondary memory needed reloads.
1487 We want to use the reserved location just below the frame pointer.
1488 However, we must ensure that there is a frame, so use assign_stack_local
1489 if the frame size is zero. */
1490 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
1491 (get_frame_size () == 0 \
1492 ? assign_stack_local (MODE, GET_MODE_SIZE (MODE), 0) \
1493 : gen_rtx_MEM (MODE, plus_constant (frame_pointer_rtx, \
1494 STARTING_FRAME_OFFSET)))
1496 /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9
1497 because the movsi and movsf patterns don't handle r/f moves.
1498 For v8 we copy the default definition. */
1499 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
1501 ? (GET_MODE_BITSIZE (MODE) < 32 \
1502 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
1504 : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \
1505 ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0) \
1508 /* Return the maximum number of consecutive registers
1509 needed to represent mode MODE in a register of class CLASS. */
1510 /* On SPARC, this is the size of MODE in words. */
1511 #define CLASS_MAX_NREGS(CLASS, MODE) \
1512 (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \
1513 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1515 /* Stack layout; function entry, exit and calling. */
1517 /* Define the number of register that can hold parameters.
1518 This macro is only used in other macro definitions below and in sparc.c.
1519 MODE is the mode of the argument.
1520 !v9: All args are passed in %o0-%o5.
1521 v9: %o0-%o5 and %f0-%f31 are cumulatively used to pass values.
1522 See the description in sparc.c. */
1523 #define NPARM_REGS(MODE) \
1525 ? (GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 6) \
1528 /* Define this if pushing a word on the stack
1529 makes the stack pointer a smaller address. */
1530 #define STACK_GROWS_DOWNWARD
1532 /* Define this if the nominal address of the stack frame
1533 is at the high-address end of the local variables;
1534 that is, each additional local variable allocated
1535 goes at a more negative offset in the frame. */
1536 #define FRAME_GROWS_DOWNWARD
1538 /* Offset within stack frame to start allocating local variables at.
1539 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1540 first local allocated. Otherwise, it is the offset to the BEGINNING
1541 of the first local allocated. */
1542 /* This allows space for one TFmode floating point value. */
1543 #define STARTING_FRAME_OFFSET \
1544 (TARGET_ARCH64 ? -16 \
1545 : (-SPARC_STACK_ALIGN (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)))
1547 /* If we generate an insn to push BYTES bytes,
1548 this says how many the stack pointer really advances by.
1549 On SPARC, don't define this because there are no push insns. */
1550 /* #define PUSH_ROUNDING(BYTES) */
1552 /* Offset of first parameter from the argument pointer register value.
1553 !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg
1554 even if this function isn't going to use it.
1555 v9: This is 128 for the ins and locals. */
1556 #define FIRST_PARM_OFFSET(FNDECL) \
1557 (TARGET_ARCH64 ? 16 * UNITS_PER_WORD : STRUCT_VALUE_OFFSET + UNITS_PER_WORD)
1559 /* Offset from the argument pointer register value to the CFA.
1560 This is different from FIRST_PARM_OFFSET because the register window
1561 comes between the CFA and the arguments. */
1562 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1564 /* When a parameter is passed in a register, stack space is still
1566 !v9: All 6 possible integer registers have backing store allocated.
1567 v9: Only space for the arguments passed is allocated. */
1568 /* ??? Ideally, we'd use zero here (as the minimum), but zero has special
1569 meaning to the backend. Further, we need to be able to detect if a
1570 varargs/unprototyped function is called, as they may want to spill more
1571 registers than we've provided space. Ugly, ugly. So for now we retain
1572 all 6 slots even for v9. */
1573 #define REG_PARM_STACK_SPACE(DECL) (6 * UNITS_PER_WORD)
1575 /* Definitions for register elimination. */
1576 /* ??? In TARGET_FLAT mode we needn't have a hard frame pointer. */
1578 #define ELIMINABLE_REGS \
1579 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1580 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM} }
1582 /* The way this is structured, we can't eliminate SFP in favor of SP
1583 if the frame pointer is required: we want to use the SFP->HFP elimination
1584 in that case. But the test in update_eliminables doesn't know we are
1585 assuming below that we only do the former elimination. */
1586 #define CAN_ELIMINATE(FROM, TO) \
1587 ((TO) == HARD_FRAME_POINTER_REGNUM || !FRAME_POINTER_REQUIRED)
1589 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1592 if ((TO) == STACK_POINTER_REGNUM) \
1594 /* Note, we always pretend that this is a leaf function \
1595 because if it's not, there's no point in trying to \
1596 eliminate the frame pointer. If it is a leaf \
1597 function, we guessed right! */ \
1600 sparc_flat_compute_frame_size (get_frame_size ()); \
1602 (OFFSET) = compute_frame_size (get_frame_size (), 1); \
1604 (OFFSET) += SPARC_STACK_BIAS; \
1607 /* Keep the stack pointer constant throughout the function.
1608 This is both an optimization and a necessity: longjmp
1609 doesn't behave itself when the stack pointer moves within
1611 #define ACCUMULATE_OUTGOING_ARGS 1
1613 /* Value is the number of bytes of arguments automatically
1614 popped when returning from a subroutine call.
1615 FUNDECL is the declaration node of the function (as a tree),
1616 FUNTYPE is the data type of the function (as a tree),
1617 or for a library call it is an identifier node for the subroutine name.
1618 SIZE is the number of bytes of arguments passed on the stack. */
1620 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1622 /* Some subroutine macros specific to this machine.
1623 When !TARGET_FPU, put float return values in the general registers,
1624 since we don't have any fp registers. */
1625 #define BASE_RETURN_VALUE_REG(MODE) \
1627 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 : 8) \
1628 : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 : 8))
1630 #define BASE_OUTGOING_VALUE_REG(MODE) \
1632 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 \
1633 : TARGET_FLAT ? 8 : 24) \
1634 : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 \
1635 : (TARGET_FLAT ? 8 : 24)))
1637 #define BASE_PASSING_ARG_REG(MODE) \
1639 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 : 8) \
1642 /* ??? FIXME -- seems wrong for v9 structure passing... */
1643 #define BASE_INCOMING_ARG_REG(MODE) \
1645 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 \
1646 : TARGET_FLAT ? 8 : 24) \
1647 : (TARGET_FLAT ? 8 : 24))
1649 /* Define this macro if the target machine has "register windows". This
1650 C expression returns the register number as seen by the called function
1651 corresponding to register number OUT as seen by the calling function.
1652 Return OUT if register number OUT is not an outbound register. */
1654 #define INCOMING_REGNO(OUT) \
1655 ((TARGET_FLAT || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16)
1657 /* Define this macro if the target machine has "register windows". This
1658 C expression returns the register number as seen by the calling function
1659 corresponding to register number IN as seen by the called function.
1660 Return IN if register number IN is not an inbound register. */
1662 #define OUTGOING_REGNO(IN) \
1663 ((TARGET_FLAT || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16)
1665 /* Define this macro if the target machine has register windows. This
1666 C expression returns true if the register is call-saved but is in the
1669 #define LOCAL_REGNO(REGNO) \
1670 (TARGET_FLAT ? 0 : (REGNO) >= 16 && (REGNO) <= 31)
1672 /* Define how to find the value returned by a function.
1673 VALTYPE is the data type of the value (as a tree).
1674 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1675 otherwise, FUNC is 0. */
1677 /* On SPARC the value is found in the first "output" register. */
1679 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1680 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 1)
1682 /* But the called function leaves it in the first "input" register. */
1684 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
1685 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 0)
1687 /* Define how to find the value returned by a library function
1688 assuming the value has mode MODE. */
1690 #define LIBCALL_VALUE(MODE) \
1691 function_value (NULL_TREE, (MODE), 1)
1693 /* 1 if N is a possible register number for a function value
1694 as seen by the caller.
1695 On SPARC, the first "output" reg is used for integer values,
1696 and the first floating point register is used for floating point values. */
1698 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32)
1700 /* Define the size of space to allocate for the return value of an
1703 #define APPLY_RESULT_SIZE 16
1705 /* 1 if N is a possible register number for function argument passing.
1706 On SPARC, these are the "output" registers. v9 also uses %f0-%f31. */
1708 #define FUNCTION_ARG_REGNO_P(N) \
1710 ? (((N) >= 8 && (N) <= 13) || ((N) >= 32 && (N) <= 63)) \
1711 : ((N) >= 8 && (N) <= 13))
1713 /* Define a data type for recording info about an argument list
1714 during the scan of that argument list. This data type should
1715 hold all necessary information about the function itself
1716 and about the args processed so far, enough to enable macros
1717 such as FUNCTION_ARG to determine where the next arg should go.
1719 On SPARC (!v9), this is a single integer, which is a number of words
1720 of arguments scanned so far (including the invisible argument,
1721 if any, which holds the structure-value-address).
1722 Thus 7 or more means all following args should go on the stack.
1724 For v9, we also need to know whether a prototype is present. */
1727 int words; /* number of words passed so far */
1728 int prototype_p; /* nonzero if a prototype is present */
1729 int libcall_p; /* nonzero if a library call */
1731 #define CUMULATIVE_ARGS struct sparc_args
1733 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1734 for a call to a function whose data type is FNTYPE.
1735 For a library call, FNTYPE is 0. */
1737 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1738 init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (INDIRECT));
1740 /* Update the data in CUM to advance over an argument
1741 of mode MODE and data type TYPE.
1742 TYPE is null for libcalls where that information may not be available. */
1744 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1745 function_arg_advance (& (CUM), (MODE), (TYPE), (NAMED))
1747 /* Nonzero if we do not know how to pass TYPE solely in registers. */
1749 #define MUST_PASS_IN_STACK(MODE,TYPE) \
1751 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1752 || TREE_ADDRESSABLE (TYPE)))
1754 /* Determine where to put an argument to a function.
1755 Value is zero to push the argument on the stack,
1756 or a hard register in which to store the argument.
1758 MODE is the argument's machine mode.
1759 TYPE is the data type of the argument (as a tree).
1760 This is null for libcalls where that information may
1762 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1763 the preceding args and about the function being called.
1764 NAMED is nonzero if this argument is a named parameter
1765 (otherwise it is an extra parameter matching an ellipsis). */
1767 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1768 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 0)
1770 /* Define where a function finds its arguments.
1771 This is different from FUNCTION_ARG because of register windows. */
1773 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
1774 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 1)
1776 /* For an arg passed partly in registers and partly in memory,
1777 this is the number of registers used.
1778 For args passed entirely in registers or entirely in memory, zero. */
1780 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1781 function_arg_partial_nregs (& (CUM), (MODE), (TYPE), (NAMED))
1783 /* A C expression that indicates when an argument must be passed by reference.
1784 If nonzero for an argument, a copy of that argument is made in memory and a
1785 pointer to the argument is passed instead of the argument itself.
1786 The pointer is passed in whatever way is appropriate for passing a pointer
1789 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1790 function_arg_pass_by_reference (& (CUM), (MODE), (TYPE), (NAMED))
1792 /* If defined, a C expression which determines whether, and in which direction,
1793 to pad out an argument with extra space. The value should be of type
1794 `enum direction': either `upward' to pad above the argument,
1795 `downward' to pad below, or `none' to inhibit padding. */
1797 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1798 function_arg_padding ((MODE), (TYPE))
1800 /* If defined, a C expression that gives the alignment boundary, in bits,
1801 of an argument with the specified mode and type. If it is not defined,
1802 PARM_BOUNDARY is used for all arguments.
1803 For sparc64, objects requiring 16 byte alignment are passed that way. */
1805 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1807 && (GET_MODE_ALIGNMENT (MODE) == 128 \
1808 || ((TYPE) && TYPE_ALIGN (TYPE) == 128))) \
1809 ? 128 : PARM_BOUNDARY)
1811 /* Define the information needed to generate branch and scc insns. This is
1812 stored from the compare operation. Note that we can't use "rtx" here
1813 since it hasn't been defined! */
1815 extern GTY(()) rtx sparc_compare_op0;
1816 extern GTY(()) rtx sparc_compare_op1;
1819 /* Generate the special assembly code needed to tell the assembler whatever
1820 it might need to know about the return value of a function.
1822 For SPARC assemblers, we need to output a .proc pseudo-op which conveys
1823 information to the assembler relating to peephole optimization (done in
1826 #define ASM_DECLARE_RESULT(FILE, RESULT) \
1827 fprintf ((FILE), "\t.proc\t0%lo\n", sparc_type_code (TREE_TYPE (RESULT)))
1829 /* Output the special assembly code needed to tell the assembler some
1830 register is used as global register variable.
1832 SPARC 64bit psABI declares registers %g2 and %g3 as application
1833 registers and %g6 and %g7 as OS registers. Any object using them
1834 should declare (for %g2/%g3 has to, for %g6/%g7 can) that it uses them
1835 and how they are used (scratch or some global variable).
1836 Linker will then refuse to link together objects which use those
1837 registers incompatibly.
1839 Unless the registers are used for scratch, two different global
1840 registers cannot be declared to the same name, so in the unlikely
1841 case of a global register variable occupying more than one register
1842 we prefix the second and following registers with .gnu.part1. etc. */
1844 extern char sparc_hard_reg_printed[8];
1846 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
1847 #define ASM_DECLARE_REGISTER_GLOBAL(FILE, DECL, REGNO, NAME) \
1849 if (TARGET_ARCH64) \
1851 int end = HARD_REGNO_NREGS ((REGNO), DECL_MODE (decl)) + (REGNO); \
1853 for (reg = (REGNO); reg < 8 && reg < end; reg++) \
1854 if ((reg & ~1) == 2 || (reg & ~1) == 6) \
1856 if (reg == (REGNO)) \
1857 fprintf ((FILE), "\t.register\t%%g%d, %s\n", reg, (NAME)); \
1859 fprintf ((FILE), "\t.register\t%%g%d, .gnu.part%d.%s\n", \
1860 reg, reg - (REGNO), (NAME)); \
1861 sparc_hard_reg_printed[reg] = 1; \
1868 /* Emit rtl for profiling. */
1869 #define PROFILE_HOOK(LABEL) sparc_profile_hook (LABEL)
1871 /* All the work done in PROFILE_HOOK, but still required. */
1872 #define FUNCTION_PROFILER(FILE, LABELNO) do { } while (0)
1874 /* Set the name of the mcount function for the system. */
1875 #define MCOUNT_FUNCTION "*mcount"
1877 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1878 the stack pointer does not matter. The value is tested only in
1879 functions that have frame pointers.
1880 No definition is equivalent to always zero. */
1882 #define EXIT_IGNORE_STACK \
1883 (get_frame_size () != 0 \
1884 || current_function_calls_alloca || current_function_outgoing_args_size)
1886 #define DELAY_SLOTS_FOR_EPILOGUE \
1887 (TARGET_FLAT ? sparc_flat_epilogue_delay_slots () : 1)
1888 #define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \
1889 (TARGET_FLAT ? sparc_flat_eligible_for_epilogue_delay (trial, slots_filled) \
1890 : eligible_for_epilogue_delay (trial, slots_filled))
1892 /* Define registers used by the epilogue and return instruction. */
1893 #define EPILOGUE_USES(REGNO) \
1894 (!TARGET_FLAT && REGNO == 31)
1896 /* Length in units of the trampoline for entering a nested function. */
1898 #define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 32 : 16)
1900 #define TRAMPOLINE_ALIGNMENT 128 /* 16 bytes */
1902 /* Emit RTL insns to initialize the variable parts of a trampoline.
1903 FNADDR is an RTX for the address of the function's pure code.
1904 CXT is an RTX for the static chain value for the function. */
1906 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1907 if (TARGET_ARCH64) \
1908 sparc64_initialize_trampoline (TRAMP, FNADDR, CXT); \
1910 sparc_initialize_trampoline (TRAMP, FNADDR, CXT)
1912 /* Generate necessary RTL for __builtin_saveregs(). */
1914 #define EXPAND_BUILTIN_SAVEREGS() sparc_builtin_saveregs ()
1916 /* Implement `va_start' for varargs and stdarg. */
1917 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
1918 sparc_va_start (valist, nextarg)
1920 /* Implement `va_arg'. */
1921 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1922 sparc_va_arg (valist, type)
1924 /* Define this macro if the location where a function argument is passed
1925 depends on whether or not it is a named argument.
1927 This macro controls how the NAMED argument to FUNCTION_ARG
1928 is set for varargs and stdarg functions. With this macro defined,
1929 the NAMED argument is always true for named arguments, and false for
1930 unnamed arguments. If this is not defined, but SETUP_INCOMING_VARARGS
1931 is defined, then all arguments are treated as named. Otherwise, all named
1932 arguments except the last are treated as named.
1933 For the v9 we want NAMED to mean what it says it means. */
1935 #define STRICT_ARGUMENT_NAMING TARGET_V9
1937 /* Generate RTL to flush the register windows so as to make arbitrary frames
1939 #define SETUP_FRAME_ADDRESSES() \
1940 emit_insn (gen_flush_register_windows ())
1942 /* Given an rtx for the address of a frame,
1943 return an rtx for the address of the word in the frame
1944 that holds the dynamic chain--the previous frame's address.
1945 ??? -mflat support? */
1946 #define DYNAMIC_CHAIN_ADDRESS(frame) \
1947 plus_constant (frame, 14 * UNITS_PER_WORD + SPARC_STACK_BIAS)
1949 /* The return address isn't on the stack, it is in a register, so we can't
1950 access it from the current frame pointer. We can access it from the
1951 previous frame pointer though by reading a value from the register window
1953 #define RETURN_ADDR_IN_PREVIOUS_FRAME
1955 /* This is the offset of the return address to the true next instruction to be
1956 executed for the current function. */
1957 #define RETURN_ADDR_OFFSET \
1958 (8 + 4 * (! TARGET_ARCH64 && current_function_returns_struct))
1960 /* The current return address is in %i7. The return address of anything
1961 farther back is in the register window save area at [%fp+60]. */
1962 /* ??? This ignores the fact that the actual return address is +8 for normal
1963 returns, and +12 for structure returns. */
1964 #define RETURN_ADDR_RTX(count, frame) \
1966 ? gen_rtx_REG (Pmode, 31) \
1967 : gen_rtx_MEM (Pmode, \
1968 memory_address (Pmode, plus_constant (frame, \
1969 15 * UNITS_PER_WORD \
1970 + SPARC_STACK_BIAS))))
1972 /* Before the prologue, the return address is %o7 + 8. OK, sometimes it's
1973 +12, but always using +8 is close enough for frame unwind purposes.
1974 Actually, just using %o7 is close enough for unwinding, but %o7+8
1975 is something you can return to. */
1976 #define INCOMING_RETURN_ADDR_RTX \
1977 plus_constant (gen_rtx_REG (word_mode, 15), 8)
1978 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (15)
1980 /* The offset from the incoming value of %sp to the top of the stack frame
1981 for the current function. On sparc64, we have to account for the stack
1983 #define INCOMING_FRAME_SP_OFFSET SPARC_STACK_BIAS
1985 /* Describe how we implement __builtin_eh_return. */
1986 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 24 : INVALID_REGNUM)
1987 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 1) /* %g1 */
1988 #define EH_RETURN_HANDLER_RTX gen_rtx_REG (Pmode, 31) /* %i7 */
1990 /* Select a format to encode pointers in exception handling data. CODE
1991 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
1992 true if the symbol may be affected by dynamic relocations.
1994 If assembler and linker properly support .uaword %r_disp32(foo),
1995 then use PC relative 32-bit relocations instead of absolute relocs
1996 for shared libraries. On sparc64, use pc relative 32-bit relocs even
1997 for binaries, to save memory.
1999 binutils 2.12 would emit a R_SPARC_DISP32 dynamic relocation if the
2000 symbol %r_disp32() is against was not local, but .hidden. In that
2001 case, we have to use DW_EH_PE_absptr for pic personality. */
2002 #ifdef HAVE_AS_SPARC_UA_PCREL
2003 #ifdef HAVE_AS_SPARC_UA_PCREL_HIDDEN
2004 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
2006 ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\
2007 : ((TARGET_ARCH64 && ! GLOBAL) \
2008 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \
2011 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
2013 ? (GLOBAL ? DW_EH_PE_absptr : (DW_EH_PE_pcrel | DW_EH_PE_sdata4)) \
2014 : ((TARGET_ARCH64 && ! GLOBAL) \
2015 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \
2019 /* Emit a PC-relative relocation. */
2020 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \
2022 fputs (integer_asm_op (SIZE, FALSE), FILE); \
2023 fprintf (FILE, "%%r_disp%d(", SIZE * 8); \
2024 assemble_name (FILE, LABEL); \
2025 fputc (')', FILE); \
2029 /* Addressing modes, and classification of registers for them. */
2031 /* Macros to check register numbers against specific register classes. */
2033 /* These assume that REGNO is a hard or pseudo reg number.
2034 They give nonzero only if REGNO is a hard reg of the suitable class
2035 or a pseudo reg currently allocated to a suitable hard reg.
2036 Since they use reg_renumber, they are safe only once reg_renumber
2037 has been allocated, which happens in local-alloc.c. */
2039 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2040 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < (unsigned)32 \
2041 || (REGNO) == FRAME_POINTER_REGNUM \
2042 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)
2044 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO)
2046 #define REGNO_OK_FOR_FP_P(REGNO) \
2047 (((unsigned) (REGNO) - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)) \
2048 || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)))
2049 #define REGNO_OK_FOR_CCFP_P(REGNO) \
2051 && (((unsigned) (REGNO) - 96 < (unsigned)4) \
2052 || ((unsigned) reg_renumber[REGNO] - 96 < (unsigned)4)))
2054 /* Now macros that check whether X is a register and also,
2055 strictly, whether it is in a specified class.
2057 These macros are specific to the SPARC, and may be used only
2058 in code for printing assembler insns and in conditions for
2059 define_optimization. */
2061 /* 1 if X is an fp register. */
2063 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
2065 /* Is X, a REG, an in or global register? i.e. is regno 0..7 or 24..31 */
2066 #define IN_OR_GLOBAL_P(X) (REGNO (X) < 8 || (REGNO (X) >= 24 && REGNO (X) <= 31))
2068 /* Maximum number of registers that can appear in a valid memory address. */
2070 #define MAX_REGS_PER_ADDRESS 2
2072 /* Recognize any constant value that is a valid address.
2073 When PIC, we do not accept an address that would require a scratch reg
2074 to load into a register. */
2076 #define CONSTANT_ADDRESS_P(X) \
2077 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2078 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
2079 || (GET_CODE (X) == CONST \
2080 && ! (flag_pic && pic_address_needs_scratch (X))))
2082 /* Define this, so that when PIC, reload won't try to reload invalid
2083 addresses which require two reload registers. */
2085 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
2087 /* Nonzero if the constant value X is a legitimate general operand.
2088 Anything can be made to work except floating point constants.
2089 If TARGET_VIS, 0.0 can be made to work as well. */
2091 #define LEGITIMATE_CONSTANT_P(X) \
2092 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode || \
2094 (GET_MODE (X) == SFmode || GET_MODE (X) == DFmode || \
2095 GET_MODE (X) == TFmode) && \
2096 fp_zero_operand (X, GET_MODE (X))))
2098 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2099 and check its validity for a certain class.
2100 We have two alternate definitions for each of them.
2101 The usual definition accepts all pseudo regs; the other rejects
2102 them unless they have been allocated suitable hard regs.
2103 The symbol REG_OK_STRICT causes the latter definition to be used.
2105 Most source files want to accept pseudo regs in the hope that
2106 they will get allocated to the class that the insn wants them to be in.
2107 Source files for reload pass need to be strict.
2108 After reload, it makes no difference, since pseudo regs have
2109 been eliminated by then. */
2111 /* Optional extra constraints for this machine.
2113 'Q' handles floating point constants which can be moved into
2114 an integer register with a single sethi instruction.
2116 'R' handles floating point constants which can be moved into
2117 an integer register with a single mov instruction.
2119 'S' handles floating point constants which can be moved into
2120 an integer register using a high/lo_sum sequence.
2122 'T' handles memory addresses where the alignment is known to
2123 be at least 8 bytes.
2125 `U' handles all pseudo registers or a hard even numbered
2126 integer register, needed for ldd/std instructions.
2128 'W' handles the memory operand when moving operands in/out
2129 of 'e' constraint floating point registers. */
2131 #ifndef REG_OK_STRICT
2133 /* Nonzero if X is a hard reg that can be used as an index
2134 or if it is a pseudo reg. */
2135 #define REG_OK_FOR_INDEX_P(X) \
2137 || REGNO (X) == FRAME_POINTER_REGNUM \
2138 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2140 /* Nonzero if X is a hard reg that can be used as a base reg
2141 or if it is a pseudo reg. */
2142 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_INDEX_P (X)
2144 /* 'T', 'U' are for aligned memory loads which aren't needed for arch64.
2145 'W' is like 'T' but is assumed true on arch64.
2147 Remember to accept pseudo-registers for memory constraints if reload is
2150 #define EXTRA_CONSTRAINT(OP, C) \
2151 sparc_extra_constraint_check(OP, C, 0)
2155 /* Nonzero if X is a hard reg that can be used as an index. */
2156 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
2157 /* Nonzero if X is a hard reg that can be used as a base reg. */
2158 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
2160 #define EXTRA_CONSTRAINT(OP, C) \
2161 sparc_extra_constraint_check(OP, C, 1)
2165 /* Should gcc use [%reg+%lo(xx)+offset] addresses? */
2167 #ifdef HAVE_AS_OFFSETABLE_LO10
2168 #define USE_AS_OFFSETABLE_LO10 1
2170 #define USE_AS_OFFSETABLE_LO10 0
2173 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2174 that is a valid memory address for an instruction.
2175 The MODE argument is the machine mode for the MEM expression
2176 that wants to use this address.
2178 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
2179 ordinarily. This changes a bit when generating PIC.
2181 If you change this, execute "rm explow.o recog.o reload.o". */
2183 #define RTX_OK_FOR_BASE_P(X) \
2184 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2185 || (GET_CODE (X) == SUBREG \
2186 && GET_CODE (SUBREG_REG (X)) == REG \
2187 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2189 #define RTX_OK_FOR_INDEX_P(X) \
2190 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2191 || (GET_CODE (X) == SUBREG \
2192 && GET_CODE (SUBREG_REG (X)) == REG \
2193 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
2195 #define RTX_OK_FOR_OFFSET_P(X) \
2196 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000 - 8)
2198 #define RTX_OK_FOR_OLO10_P(X) \
2199 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0xc00 - 8)
2201 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2202 { if (RTX_OK_FOR_BASE_P (X)) \
2204 else if (GET_CODE (X) == PLUS) \
2206 register rtx op0 = XEXP (X, 0); \
2207 register rtx op1 = XEXP (X, 1); \
2208 if (flag_pic && op0 == pic_offset_table_rtx) \
2210 if (RTX_OK_FOR_BASE_P (op1)) \
2212 else if (flag_pic == 1 \
2213 && GET_CODE (op1) != REG \
2214 && GET_CODE (op1) != LO_SUM \
2215 && GET_CODE (op1) != MEM \
2216 && (GET_CODE (op1) != CONST_INT \
2217 || SMALL_INT (op1))) \
2220 else if (RTX_OK_FOR_BASE_P (op0)) \
2222 if ((RTX_OK_FOR_INDEX_P (op1) \
2223 /* We prohibit REG + REG for TFmode when \
2224 there are no instructions which accept \
2225 REG+REG instructions. We do this \
2226 because REG+REG is not an offsetable \
2227 address. If we get the situation \
2228 in reload where source and destination \
2229 of a movtf pattern are both MEMs with \
2230 REG+REG address, then only one of them \
2231 gets converted to an offsetable \
2233 && (MODE != TFmode \
2234 || (TARGET_FPU && TARGET_ARCH64 \
2236 && TARGET_HARD_QUAD)) \
2237 /* We prohibit REG + REG on ARCH32 if \
2238 not optimizing for DFmode/DImode \
2239 because then mem_min_alignment is \
2240 likely to be zero after reload and the \
2241 forced split would lack a matching \
2242 splitter pattern. */ \
2243 && (TARGET_ARCH64 || optimize \
2244 || (MODE != DFmode \
2245 && MODE != DImode))) \
2246 || RTX_OK_FOR_OFFSET_P (op1)) \
2249 else if (RTX_OK_FOR_BASE_P (op1)) \
2251 if ((RTX_OK_FOR_INDEX_P (op0) \
2252 /* See the previous comment. */ \
2253 && (MODE != TFmode \
2254 || (TARGET_FPU && TARGET_ARCH64 \
2256 && TARGET_HARD_QUAD)) \
2257 && (TARGET_ARCH64 || optimize \
2258 || (MODE != DFmode \
2259 && MODE != DImode))) \
2260 || RTX_OK_FOR_OFFSET_P (op0)) \
2263 else if (USE_AS_OFFSETABLE_LO10 \
2264 && GET_CODE (op0) == LO_SUM \
2266 && ! TARGET_CM_MEDMID \
2267 && RTX_OK_FOR_OLO10_P (op1)) \
2269 register rtx op00 = XEXP (op0, 0); \
2270 register rtx op01 = XEXP (op0, 1); \
2271 if (RTX_OK_FOR_BASE_P (op00) \
2272 && CONSTANT_P (op01)) \
2275 else if (USE_AS_OFFSETABLE_LO10 \
2276 && GET_CODE (op1) == LO_SUM \
2278 && ! TARGET_CM_MEDMID \
2279 && RTX_OK_FOR_OLO10_P (op0)) \
2281 register rtx op10 = XEXP (op1, 0); \
2282 register rtx op11 = XEXP (op1, 1); \
2283 if (RTX_OK_FOR_BASE_P (op10) \
2284 && CONSTANT_P (op11)) \
2288 else if (GET_CODE (X) == LO_SUM) \
2290 register rtx op0 = XEXP (X, 0); \
2291 register rtx op1 = XEXP (X, 1); \
2292 if (RTX_OK_FOR_BASE_P (op0) \
2293 && CONSTANT_P (op1) \
2294 /* We can't allow TFmode, because an offset \
2295 greater than or equal to the alignment (8) \
2296 may cause the LO_SUM to overflow if !v9. */\
2297 && (MODE != TFmode || TARGET_V9)) \
2300 else if (GET_CODE (X) == CONST_INT && SMALL_INT (X)) \
2304 /* Try machine-dependent ways of modifying an illegitimate address
2305 to be legitimate. If we find one, return the new, valid address.
2306 This macro is used in only one place: `memory_address' in explow.c.
2308 OLDX is the address as it was before break_out_memory_refs was called.
2309 In some cases it is useful to look at this to decide what needs to be done.
2311 MODE and WIN are passed so that this macro can use
2312 GO_IF_LEGITIMATE_ADDRESS.
2314 It is always safe for this macro to do nothing. It exists to recognize
2315 opportunities to optimize the output. */
2317 /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
2318 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2319 { rtx sparc_x = (X); \
2320 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \
2321 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 1), \
2322 force_operand (XEXP (X, 0), NULL_RTX)); \
2323 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \
2324 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2325 force_operand (XEXP (X, 1), NULL_RTX)); \
2326 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \
2327 (X) = gen_rtx_PLUS (Pmode, force_operand (XEXP (X, 0), NULL_RTX),\
2329 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \
2330 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2331 force_operand (XEXP (X, 1), NULL_RTX)); \
2332 if (sparc_x != (X) && memory_address_p (MODE, X)) \
2334 if (flag_pic) (X) = legitimize_pic_address (X, MODE, 0); \
2335 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
2336 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2337 copy_to_mode_reg (Pmode, XEXP (X, 1))); \
2338 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0))) \
2339 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 1), \
2340 copy_to_mode_reg (Pmode, XEXP (X, 0))); \
2341 else if (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
2342 || GET_CODE (X) == LABEL_REF) \
2343 (X) = copy_to_suggested_reg (X, NULL_RTX, Pmode); \
2344 if (memory_address_p (MODE, X)) \
2347 /* Try a machine-dependent way of reloading an illegitimate address
2348 operand. If we find one, push the reload and jump to WIN. This
2349 macro is used in only one place: `find_reloads_address' in reload.c.
2351 For SPARC 32, we wish to handle addresses by splitting them into
2352 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
2353 This cuts the number of extra insns by one.
2355 Do nothing when generating PIC code and the address is a
2356 symbolic operand or requires a scratch register. */
2358 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2360 /* Decompose SImode constants into hi+lo_sum. We do have to \
2361 rerecognize what we produce, so be careful. */ \
2362 if (CONSTANT_P (X) \
2363 && (MODE != TFmode || TARGET_ARCH64) \
2364 && GET_MODE (X) == SImode \
2365 && GET_CODE (X) != LO_SUM && GET_CODE (X) != HIGH \
2367 && (symbolic_operand (X, Pmode) \
2368 || pic_address_needs_scratch (X))) \
2369 && sparc_cmodel <= CM_MEDLOW) \
2371 X = gen_rtx_LO_SUM (GET_MODE (X), \
2372 gen_rtx_HIGH (GET_MODE (X), X), X); \
2373 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
2374 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
2378 /* ??? 64-bit reloads. */ \
2381 /* Go to LABEL if ADDR (a legitimate address expression)
2382 has an effect that depends on the machine mode it is used for.
2383 On the SPARC this is never true. */
2385 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
2387 /* Specify the machine mode that this machine uses
2388 for the index in the tablejump instruction. */
2389 /* If we ever implement any of the full models (such as CM_FULLANY),
2390 this has to be DImode in that case */
2391 #ifdef HAVE_GAS_SUBSECTION_ORDERING
2392 #define CASE_VECTOR_MODE \
2393 (! TARGET_PTR64 ? SImode : flag_pic ? SImode : TARGET_CM_MEDLOW ? SImode : DImode)
2395 /* If assembler does not have working .subsection -1, we use DImode for pic, as otherwise
2396 we have to sign extend which slows things down. */
2397 #define CASE_VECTOR_MODE \
2398 (! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode)
2401 /* Define as C expression which evaluates to nonzero if the tablejump
2402 instruction expects the table to contain offsets from the address of the
2404 Do not define this if the table should contain absolute addresses. */
2405 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2407 /* Define this as 1 if `char' should by default be signed; else as 0. */
2408 #define DEFAULT_SIGNED_CHAR 1
2410 /* Max number of bytes we can move from memory to memory
2411 in one reasonably fast instruction. */
2414 #if 0 /* Sun 4 has matherr, so this is no good. */
2415 /* This is the value of the error code EDOM for this machine,
2416 used by the sqrt instruction. */
2417 #define TARGET_EDOM 33
2419 /* This is how to refer to the variable errno. */
2420 #define GEN_ERRNO_RTX \
2421 gen_rtx_MEM (SImode, gen_rtx_SYMBOL_REF (Pmode, "errno"))
2424 /* Define if operations between registers always perform the operation
2425 on the full register even if a narrower mode is specified. */
2426 #define WORD_REGISTER_OPERATIONS
2428 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2429 will either zero-extend or sign-extend. The value of this macro should
2430 be the code that says which one of the two operations is implicitly
2431 done, NIL if none. */
2432 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2434 /* Nonzero if access to memory by bytes is slow and undesirable.
2435 For RISC chips, it means that access to memory by bytes is no
2436 better than access by words when possible, so grab a whole word
2437 and maybe make use of that. */
2438 #define SLOW_BYTE_ACCESS 1
2440 /* We assume that the store-condition-codes instructions store 0 for false
2441 and some other value for true. This is the value stored for true. */
2443 #define STORE_FLAG_VALUE 1
2445 /* When a prototype says `char' or `short', really pass an `int'. */
2446 #define PROMOTE_PROTOTYPES (TARGET_ARCH32)
2448 /* Define this to be nonzero if shift instructions ignore all but the low-order
2450 #define SHIFT_COUNT_TRUNCATED 1
2452 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2453 is done just by pretending it is already truncated. */
2454 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2456 /* Specify the machine mode that pointers have.
2457 After generation of rtl, the compiler makes no further distinction
2458 between pointers and any other objects of this machine mode. */
2459 #define Pmode (TARGET_ARCH64 ? DImode : SImode)
2461 /* Generate calls to memcpy, memcmp and memset. */
2462 #define TARGET_MEM_FUNCTIONS
2464 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2465 return the mode to be used for the comparison. For floating-point,
2466 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2467 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2468 processing is needed. */
2469 #define SELECT_CC_MODE(OP,X,Y) select_cc_mode ((OP), (X), (Y))
2471 /* Return nonzero if MODE implies a floating point inequality can be
2472 reversed. For SPARC this is always true because we have a full
2473 compliment of ordered and unordered comparisons, but until generic
2474 code knows how to reverse it correctly we keep the old definition. */
2475 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode && (MODE) != CCFPmode)
2477 /* A function address in a call instruction for indexing purposes. */
2478 #define FUNCTION_MODE Pmode
2480 /* Define this if addresses of constant functions
2481 shouldn't be put through pseudo regs where they can be cse'd.
2482 Desirable on machines where ordinary constants are expensive
2483 but a CALL with constant address is cheap. */
2484 #define NO_FUNCTION_CSE
2486 /* alloca should avoid clobbering the old register save area. */
2487 #define SETJMP_VIA_SAVE_AREA
2489 /* Define subroutines to call to handle multiply and divide.
2490 Use the subroutines that Sun's library provides.
2491 The `*' prevents an underscore from being prepended by the compiler. */
2493 #define DIVSI3_LIBCALL "*.div"
2494 #define UDIVSI3_LIBCALL "*.udiv"
2495 #define MODSI3_LIBCALL "*.rem"
2496 #define UMODSI3_LIBCALL "*.urem"
2497 /* .umul is a little faster than .mul. */
2498 #define MULSI3_LIBCALL "*.umul"
2500 /* Define library calls for quad FP operations. These are all part of the
2502 #define ADDTF3_LIBCALL "_Q_add"
2503 #define SUBTF3_LIBCALL "_Q_sub"
2504 #define NEGTF2_LIBCALL "_Q_neg"
2505 #define MULTF3_LIBCALL "_Q_mul"
2506 #define DIVTF3_LIBCALL "_Q_div"
2507 #define FLOATSITF2_LIBCALL "_Q_itoq"
2508 #define FIX_TRUNCTFSI2_LIBCALL "_Q_qtoi"
2509 #define FIXUNS_TRUNCTFSI2_LIBCALL "_Q_qtou"
2510 #define EXTENDSFTF2_LIBCALL "_Q_stoq"
2511 #define TRUNCTFSF2_LIBCALL "_Q_qtos"
2512 #define EXTENDDFTF2_LIBCALL "_Q_dtoq"
2513 #define TRUNCTFDF2_LIBCALL "_Q_qtod"
2514 #define EQTF2_LIBCALL "_Q_feq"
2515 #define NETF2_LIBCALL "_Q_fne"
2516 #define GTTF2_LIBCALL "_Q_fgt"
2517 #define GETF2_LIBCALL "_Q_fge"
2518 #define LTTF2_LIBCALL "_Q_flt"
2519 #define LETF2_LIBCALL "_Q_fle"
2521 /* Assume by default that the _Qp_* 64-bit libcalls are implemented such
2522 that the inputs are fully consumed before the output memory is clobbered. */
2524 #define TARGET_BUGGY_QP_LIB 0
2526 /* We can define the TFmode sqrt optab only if TARGET_FPU. This is because
2527 with soft-float, the SFmode and DFmode sqrt instructions will be absent,
2528 and the compiler will notice and try to use the TFmode sqrt instruction
2529 for calls to the builtin function sqrt, but this fails. */
2530 #define INIT_TARGET_OPTABS \
2532 if (TARGET_ARCH32) \
2534 add_optab->handlers[(int) TFmode].libfunc \
2535 = init_one_libfunc (ADDTF3_LIBCALL); \
2536 sub_optab->handlers[(int) TFmode].libfunc \
2537 = init_one_libfunc (SUBTF3_LIBCALL); \
2538 neg_optab->handlers[(int) TFmode].libfunc \
2539 = init_one_libfunc (NEGTF2_LIBCALL); \
2540 smul_optab->handlers[(int) TFmode].libfunc \
2541 = init_one_libfunc (MULTF3_LIBCALL); \
2542 sdiv_optab->handlers[(int) TFmode].libfunc \
2543 = init_one_libfunc (DIVTF3_LIBCALL); \
2544 eqtf2_libfunc = init_one_libfunc (EQTF2_LIBCALL); \
2545 netf2_libfunc = init_one_libfunc (NETF2_LIBCALL); \
2546 gttf2_libfunc = init_one_libfunc (GTTF2_LIBCALL); \
2547 getf2_libfunc = init_one_libfunc (GETF2_LIBCALL); \
2548 lttf2_libfunc = init_one_libfunc (LTTF2_LIBCALL); \
2549 letf2_libfunc = init_one_libfunc (LETF2_LIBCALL); \
2550 trunctfsf2_libfunc = init_one_libfunc (TRUNCTFSF2_LIBCALL); \
2551 trunctfdf2_libfunc = init_one_libfunc (TRUNCTFDF2_LIBCALL); \
2552 extendsftf2_libfunc = init_one_libfunc (EXTENDSFTF2_LIBCALL); \
2553 extenddftf2_libfunc = init_one_libfunc (EXTENDDFTF2_LIBCALL); \
2554 floatsitf_libfunc = init_one_libfunc (FLOATSITF2_LIBCALL); \
2555 fixtfsi_libfunc = init_one_libfunc (FIX_TRUNCTFSI2_LIBCALL); \
2556 fixunstfsi_libfunc \
2557 = init_one_libfunc (FIXUNS_TRUNCTFSI2_LIBCALL); \
2559 sqrt_optab->handlers[(int) TFmode].libfunc \
2560 = init_one_libfunc ("_Q_sqrt"); \
2562 if (TARGET_ARCH64) \
2564 /* In the SPARC 64bit ABI, these libfuncs do not exist in the \
2565 library. Make sure the compiler does not emit calls to them \
2567 sdiv_optab->handlers[(int) SImode].libfunc = NULL; \
2568 udiv_optab->handlers[(int) SImode].libfunc = NULL; \
2569 smod_optab->handlers[(int) SImode].libfunc = NULL; \
2570 umod_optab->handlers[(int) SImode].libfunc = NULL; \
2571 smul_optab->handlers[(int) SImode].libfunc = NULL; \
2573 INIT_SUBTARGET_OPTABS; \
2576 /* This is meant to be redefined in the host dependent files */
2577 #define INIT_SUBTARGET_OPTABS
2579 /* Nonzero if a floating point comparison library call for
2580 mode MODE that will return a boolean value. Zero if one
2581 of the libgcc2 functions is used. */
2582 #define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) ((MODE) == TFmode)
2584 /* Compute extra cost of moving data between one register class
2586 #define GENERAL_OR_I64(C) ((C) == GENERAL_REGS || (C) == I64_REGS)
2587 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
2588 (((FP_REG_CLASS_P (CLASS1) && GENERAL_OR_I64 (CLASS2)) \
2589 || (GENERAL_OR_I64 (CLASS1) && FP_REG_CLASS_P (CLASS2)) \
2590 || (CLASS1) == FPCC_REGS || (CLASS2) == FPCC_REGS) \
2591 ? ((sparc_cpu == PROCESSOR_ULTRASPARC \
2592 || sparc_cpu == PROCESSOR_ULTRASPARC3) ? 12 : 6) : 2)
2594 /* Provide the cost of a branch. For pre-v9 processors we use
2595 a value of 3 to take into account the potential annulling of
2596 the delay slot (which ends up being a bubble in the pipeline slot)
2597 plus a cycle to take into consideration the instruction cache
2600 On v9 and later, which have branch prediction facilities, we set
2601 it to the depth of the pipeline as that is the cost of a
2602 mispredicted branch. */
2604 #define BRANCH_COST \
2605 ((sparc_cpu == PROCESSOR_V9 \
2606 || sparc_cpu == PROCESSOR_ULTRASPARC) \
2608 : (sparc_cpu == PROCESSOR_ULTRASPARC3 \
2611 #define ADDRESS_COST(RTX) 1
2613 #define PREFETCH_BLOCK \
2614 ((sparc_cpu == PROCESSOR_ULTRASPARC \
2615 || sparc_cpu == PROCESSOR_ULTRASPARC3) \
2618 #define SIMULTANEOUS_PREFETCHES \
2619 ((sparc_cpu == PROCESSOR_ULTRASPARC) \
2621 : (sparc_cpu == PROCESSOR_ULTRASPARC3 \
2624 /* Control the assembler format that we output. */
2626 /* Output at beginning of assembler file. */
2628 #define ASM_FILE_START(file)
2630 /* A C string constant describing how to begin a comment in the target
2631 assembler language. The compiler assumes that the comment will end at
2632 the end of the line. */
2634 #define ASM_COMMENT_START "!"
2636 /* Output to assembler file text saying following lines
2637 may contain character constants, extra white space, comments, etc. */
2639 #define ASM_APP_ON ""
2641 /* Output to assembler file text saying following lines
2642 no longer contain unusual constructs. */
2644 #define ASM_APP_OFF ""
2646 /* ??? Try to make the style consistent here (_OP?). */
2648 #define ASM_FLOAT ".single"
2649 #define ASM_DOUBLE ".double"
2650 #define ASM_LONGDOUBLE ".xxx" /* ??? Not known (or used yet). */
2652 /* How to refer to registers in assembler output.
2653 This sequence is indexed by compiler's hard-register-number (see above). */
2655 #define REGISTER_NAMES \
2656 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \
2657 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \
2658 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \
2659 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \
2660 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \
2661 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \
2662 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \
2663 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \
2664 "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \
2665 "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \
2666 "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \
2667 "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \
2668 "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc", "%sfp" }
2670 /* Define additional names for use in asm clobbers and asm declarations. */
2672 #define ADDITIONAL_REGISTER_NAMES \
2673 {{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}}
2675 /* On Sun 4, this limit is 2048. We use 1000 to be safe, since the length
2676 can run past this up to a continuation point. Once we used 1500, but
2677 a single entry in C++ can run more than 500 bytes, due to the length of
2678 mangled symbol names. dbxout.c should really be fixed to do
2679 continuations when they are actually needed instead of trying to
2681 #define DBX_CONTIN_LENGTH 1000
2683 /* This is how to output a command to make the user-level label named NAME
2684 defined for reference from other files. */
2686 /* Globalizing directive for a label. */
2687 #define GLOBAL_ASM_OP "\t.global "
2689 /* The prefix to add to user-visible assembler symbols. */
2691 #define USER_LABEL_PREFIX "_"
2693 /* This is how to store into the string LABEL
2694 the symbol_ref name of an internal numbered label where
2695 PREFIX is the class of label and NUM is the number within the class.
2696 This is suitable for output with `assemble_name'. */
2698 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2699 sprintf ((LABEL), "*%s%ld", (PREFIX), (long)(NUM))
2701 /* This is how we hook in and defer the case-vector until the end of
2703 #define ASM_OUTPUT_ADDR_VEC(LAB,VEC) \
2704 sparc_defer_case_vector ((LAB),(VEC), 0)
2706 #define ASM_OUTPUT_ADDR_DIFF_VEC(LAB,VEC) \
2707 sparc_defer_case_vector ((LAB),(VEC), 1)
2709 /* This is how to output an element of a case-vector that is absolute. */
2711 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2714 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
2715 if (CASE_VECTOR_MODE == SImode) \
2716 fprintf (FILE, "\t.word\t"); \
2718 fprintf (FILE, "\t.xword\t"); \
2719 assemble_name (FILE, label); \
2720 fputc ('\n', FILE); \
2723 /* This is how to output an element of a case-vector that is relative.
2724 (SPARC uses such vectors only when generating PIC.) */
2726 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2729 ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE)); \
2730 if (CASE_VECTOR_MODE == SImode) \
2731 fprintf (FILE, "\t.word\t"); \
2733 fprintf (FILE, "\t.xword\t"); \
2734 assemble_name (FILE, label); \
2735 ASM_GENERATE_INTERNAL_LABEL (label, "L", (REL)); \
2736 fputc ('-', FILE); \
2737 assemble_name (FILE, label); \
2738 fputc ('\n', FILE); \
2741 /* This is what to output before and after case-vector (both
2742 relative and absolute). If .subsection -1 works, we put case-vectors
2743 at the beginning of the current section. */
2745 #ifdef HAVE_GAS_SUBSECTION_ORDERING
2747 #define ASM_OUTPUT_ADDR_VEC_START(FILE) \
2748 fprintf(FILE, "\t.subsection\t-1\n")
2750 #define ASM_OUTPUT_ADDR_VEC_END(FILE) \
2751 fprintf(FILE, "\t.previous\n")
2755 /* This is how to output an assembler line
2756 that says to advance the location counter
2757 to a multiple of 2**LOG bytes. */
2759 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2761 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
2763 /* This is how to output an assembler line that says to advance
2764 the location counter to a multiple of 2**LOG bytes using the
2765 "nop" instruction as padding. */
2766 #define ASM_OUTPUT_ALIGN_WITH_NOP(FILE,LOG) \
2768 fprintf (FILE, "\t.align %d,0x1000000\n", (1<<(LOG)))
2770 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
2771 fprintf (FILE, "\t.skip %u\n", (SIZE))
2773 /* This says how to output an assembler line
2774 to define a global common symbol. */
2776 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
2777 ( fputs ("\t.common ", (FILE)), \
2778 assemble_name ((FILE), (NAME)), \
2779 fprintf ((FILE), ",%u,\"bss\"\n", (SIZE)))
2781 /* This says how to output an assembler line to define a local common
2784 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \
2785 ( fputs ("\t.reserve ", (FILE)), \
2786 assemble_name ((FILE), (NAME)), \
2787 fprintf ((FILE), ",%u,\"bss\",%u\n", \
2788 (SIZE), ((ALIGNED) / BITS_PER_UNIT)))
2790 /* A C statement (sans semicolon) to output to the stdio stream
2791 FILE the assembler definition of uninitialized global DECL named
2792 NAME whose size is SIZE bytes and alignment is ALIGN bytes.
2793 Try to use asm_output_aligned_bss to implement this macro. */
2795 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2797 fputs (".globl ", (FILE)); \
2798 assemble_name ((FILE), (NAME)); \
2799 fputs ("\n", (FILE)); \
2800 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \
2803 #define IDENT_ASM_OP "\t.ident\t"
2805 /* Output #ident as a .ident. */
2807 #define ASM_OUTPUT_IDENT(FILE, NAME) \
2808 fprintf (FILE, "%s\"%s\"\n", IDENT_ASM_OP, NAME);
2810 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
2811 ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '(' || (CHAR) == '_')
2813 /* Print operand X (an rtx) in assembler syntax to file FILE.
2814 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2815 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2817 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2819 /* Print a memory address as an operand to reference that memory location. */
2821 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2822 { register rtx base, index = 0; \
2824 register rtx addr = ADDR; \
2825 if (GET_CODE (addr) == REG) \
2826 fputs (reg_names[REGNO (addr)], FILE); \
2827 else if (GET_CODE (addr) == PLUS) \
2829 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
2830 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\
2831 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
2832 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\
2834 base = XEXP (addr, 0), index = XEXP (addr, 1); \
2835 if (GET_CODE (base) == LO_SUM) \
2837 if (! USE_AS_OFFSETABLE_LO10 \
2839 || TARGET_CM_MEDMID) \
2841 output_operand (XEXP (base, 0), 0); \
2842 fputs ("+%lo(", FILE); \
2843 output_address (XEXP (base, 1)); \
2844 fprintf (FILE, ")+%d", offset); \
2848 fputs (reg_names[REGNO (base)], FILE); \
2850 fprintf (FILE, "%+d", offset); \
2851 else if (GET_CODE (index) == REG) \
2852 fprintf (FILE, "+%s", reg_names[REGNO (index)]); \
2853 else if (GET_CODE (index) == SYMBOL_REF \
2854 || GET_CODE (index) == CONST) \
2855 fputc ('+', FILE), output_addr_const (FILE, index); \
2859 else if (GET_CODE (addr) == MINUS \
2860 && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \
2862 output_addr_const (FILE, XEXP (addr, 0)); \
2863 fputs ("-(", FILE); \
2864 output_addr_const (FILE, XEXP (addr, 1)); \
2865 fputs ("-.)", FILE); \
2867 else if (GET_CODE (addr) == LO_SUM) \
2869 output_operand (XEXP (addr, 0), 0); \
2870 if (TARGET_CM_MEDMID) \
2871 fputs ("+%l44(", FILE); \
2873 fputs ("+%lo(", FILE); \
2874 output_address (XEXP (addr, 1)); \
2875 fputc (')', FILE); \
2877 else if (flag_pic && GET_CODE (addr) == CONST \
2878 && GET_CODE (XEXP (addr, 0)) == MINUS \
2879 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \
2880 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \
2881 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \
2883 addr = XEXP (addr, 0); \
2884 output_addr_const (FILE, XEXP (addr, 0)); \
2885 /* Group the args of the second CONST in parenthesis. */ \
2886 fputs ("-(", FILE); \
2887 /* Skip past the second CONST--it does nothing for us. */\
2888 output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \
2889 /* Close the parenthesis. */ \
2890 fputc (')', FILE); \
2894 output_addr_const (FILE, addr); \
2898 /* Define the codes that are matched by predicates in sparc.c. */
2900 #define PREDICATE_CODES \
2901 {"reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2902 {"const1_operand", {CONST_INT}}, \
2903 {"fp_zero_operand", {CONST_DOUBLE}}, \
2904 {"fp_register_operand", {SUBREG, REG}}, \
2905 {"intreg_operand", {SUBREG, REG}}, \
2906 {"fcc_reg_operand", {REG}}, \
2907 {"fcc0_reg_operand", {REG}}, \
2908 {"icc_or_fcc_reg_operand", {REG}}, \
2909 {"restore_operand", {REG}}, \
2910 {"call_operand", {MEM}}, \
2911 {"call_operand_address", {SYMBOL_REF, LABEL_REF, CONST, CONST_DOUBLE, \
2912 ADDRESSOF, SUBREG, REG, PLUS, LO_SUM, CONST_INT}}, \
2913 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
2914 {"symbolic_memory_operand", {SUBREG, MEM}}, \
2915 {"label_ref_operand", {LABEL_REF}}, \
2916 {"sp64_medium_pic_operand", {CONST}}, \
2917 {"data_segment_operand", {SYMBOL_REF, PLUS, CONST}}, \
2918 {"text_segment_operand", {LABEL_REF, SYMBOL_REF, PLUS, CONST}}, \
2919 {"reg_or_nonsymb_mem_operand", {SUBREG, REG, MEM}}, \
2920 {"splittable_symbolic_memory_operand", {MEM}}, \
2921 {"splittable_immediate_memory_operand", {MEM}}, \
2922 {"eq_or_neq", {EQ, NE}}, \
2923 {"normal_comp_operator", {GE, GT, LE, LT, GTU, LEU}}, \
2924 {"noov_compare_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}}, \
2925 {"noov_compare64_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}}, \
2926 {"v9_regcmp_op", {EQ, NE, GE, LT, LE, GT}}, \
2927 {"extend_op", {SIGN_EXTEND, ZERO_EXTEND}}, \
2928 {"cc_arithop", {AND, IOR, XOR}}, \
2929 {"cc_arithopn", {AND, IOR}}, \
2930 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
2931 {"arith_add_operand", {SUBREG, REG, CONST_INT}}, \
2932 {"arith11_operand", {SUBREG, REG, CONST_INT}}, \
2933 {"arith10_operand", {SUBREG, REG, CONST_INT}}, \
2934 {"arith_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2935 {"arith_double_add_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2936 {"arith11_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2937 {"arith10_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2938 {"small_int", {CONST_INT}}, \
2939 {"small_int_or_double", {CONST_INT, CONST_DOUBLE}}, \
2940 {"uns_small_int", {CONST_INT}}, \
2941 {"uns_arith_operand", {SUBREG, REG, CONST_INT}}, \
2942 {"clobbered_register", {REG}}, \
2943 {"input_operand", {SUBREG, REG, CONST_INT, MEM, CONST}}, \
2944 {"const64_operand", {CONST_INT, CONST_DOUBLE}}, \
2945 {"const64_high_operand", {CONST_INT, CONST_DOUBLE}},
2947 /* The number of Pmode words for the setjmp buffer. */
2948 #define JMP_BUF_SIZE 12
2950 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (flag_pic)
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