1 /* Definitions of target machine for GNU compiler, for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1994, 1995, 1996, 1997, 1998, 1999
3 2000, 2001, 2002 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com).
5 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 /* Note that some other tm.h files include this one and then override
26 whatever definitions are necessary. */
28 /* Specify this in a cover file to provide bi-architecture (32/64) support. */
29 /* #define SPARC_BI_ARCH */
31 /* Macro used later in this file to determine default architecture. */
32 #define DEFAULT_ARCH32_P ((TARGET_DEFAULT & MASK_64BIT) == 0)
34 /* TARGET_ARCH{32,64} are the main macros to decide which of the two
35 architectures to compile for. We allow targets to choose compile time or
38 #if defined(__sparcv9) || defined(__arch64__)
39 #define TARGET_ARCH32 0
41 #define TARGET_ARCH32 1
45 #define TARGET_ARCH32 (! TARGET_64BIT)
47 #define TARGET_ARCH32 (DEFAULT_ARCH32_P)
48 #endif /* SPARC_BI_ARCH */
49 #endif /* IN_LIBGCC2 */
50 #define TARGET_ARCH64 (! TARGET_ARCH32)
52 /* Code model selection.
53 -mcmodel is used to select the v9 code model.
54 Different code models aren't supported for v7/8 code.
56 TARGET_CM_32: 32 bit address space, top 32 bits = 0,
57 pointers are 32 bits. Note that this isn't intended
60 TARGET_CM_MEDLOW: 32 bit address space, top 32 bits = 0,
61 avoid generating %uhi and %ulo terms,
64 TARGET_CM_MEDMID: 64 bit address space.
65 The executable must be in the low 16 TB of memory.
66 This corresponds to the low 44 bits, and the %[hml]44
67 relocs are used. The text segment has a maximum size
70 TARGET_CM_MEDANY: 64 bit address space.
71 The text and data segments have a maximum size of 31
72 bits and may be located anywhere. The maximum offset
73 from any instruction to the label _GLOBAL_OFFSET_TABLE_
76 TARGET_CM_EMBMEDANY: 64 bit address space.
77 The text and data segments have a maximum size of 31 bits
78 and may be located anywhere. Register %g4 contains
79 the start address of the data segment.
90 /* Value of -mcmodel specified by user. */
91 extern const char *sparc_cmodel_string;
93 extern enum cmodel sparc_cmodel;
95 /* V9 code model selection. */
96 #define TARGET_CM_MEDLOW (sparc_cmodel == CM_MEDLOW)
97 #define TARGET_CM_MEDMID (sparc_cmodel == CM_MEDMID)
98 #define TARGET_CM_MEDANY (sparc_cmodel == CM_MEDANY)
99 #define TARGET_CM_EMBMEDANY (sparc_cmodel == CM_EMBMEDANY)
101 #define SPARC_DEFAULT_CMODEL CM_32
103 /* This is call-clobbered in the normal ABI, but is reserved in the
104 home grown (aka upward compatible) embedded ABI. */
105 #define EMBMEDANY_BASE_REG "%g4"
107 /* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile,
108 and specified by the user via --with-cpu=foo.
109 This specifies the cpu implementation, not the architecture size. */
110 /* Note that TARGET_CPU_v9 is assumed to start the list of 64-bit
112 #define TARGET_CPU_sparc 0
113 #define TARGET_CPU_v7 0 /* alias for previous */
114 #define TARGET_CPU_sparclet 1
115 #define TARGET_CPU_sparclite 2
116 #define TARGET_CPU_v8 3 /* generic v8 implementation */
117 #define TARGET_CPU_supersparc 4
118 #define TARGET_CPU_hypersparc 5
119 #define TARGET_CPU_sparc86x 6
120 #define TARGET_CPU_sparclite86x 6
121 #define TARGET_CPU_v9 7 /* generic v9 implementation */
122 #define TARGET_CPU_sparcv9 7 /* alias */
123 #define TARGET_CPU_sparc64 7 /* alias */
124 #define TARGET_CPU_ultrasparc 8
126 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
127 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc
129 #define CPP_CPU32_DEFAULT_SPEC ""
130 #define ASM_CPU32_DEFAULT_SPEC ""
132 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9
133 /* ??? What does Sun's CC pass? */
134 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
135 /* ??? It's not clear how other assemblers will handle this, so by default
136 use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case
137 is handled in sol2.h. */
138 #define ASM_CPU64_DEFAULT_SPEC "-Av9"
140 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc
141 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
142 #define ASM_CPU64_DEFAULT_SPEC "-Av9a"
147 #define CPP_CPU64_DEFAULT_SPEC ""
148 #define ASM_CPU64_DEFAULT_SPEC ""
150 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc \
151 || TARGET_CPU_DEFAULT == TARGET_CPU_v8
152 #define CPP_CPU32_DEFAULT_SPEC ""
153 #define ASM_CPU32_DEFAULT_SPEC ""
156 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet
157 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclet__"
158 #define ASM_CPU32_DEFAULT_SPEC "-Asparclet"
161 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite
162 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite__"
163 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
166 #if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc
167 #define CPP_CPU32_DEFAULT_SPEC "-D__supersparc__ -D__sparc_v8__"
168 #define ASM_CPU32_DEFAULT_SPEC ""
171 #if TARGET_CPU_DEFAULT == TARGET_CPU_hypersparc
172 #define CPP_CPU32_DEFAULT_SPEC "-D__hypersparc__ -D__sparc_v8__"
173 #define ASM_CPU32_DEFAULT_SPEC ""
176 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite86x
177 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite86x__"
178 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
183 #if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC)
184 Unrecognized value in TARGET_CPU_DEFAULT.
189 #define CPP_CPU_DEFAULT_SPEC \
190 (DEFAULT_ARCH32_P ? "\
191 %{m64:" CPP_CPU64_DEFAULT_SPEC "} \
192 %{!m64:" CPP_CPU32_DEFAULT_SPEC "} \
194 %{m32:" CPP_CPU32_DEFAULT_SPEC "} \
195 %{!m32:" CPP_CPU64_DEFAULT_SPEC "} \
197 #define ASM_CPU_DEFAULT_SPEC \
198 (DEFAULT_ARCH32_P ? "\
199 %{m64:" ASM_CPU64_DEFAULT_SPEC "} \
200 %{!m64:" ASM_CPU32_DEFAULT_SPEC "} \
202 %{m32:" ASM_CPU32_DEFAULT_SPEC "} \
203 %{!m32:" ASM_CPU64_DEFAULT_SPEC "} \
206 #else /* !SPARC_BI_ARCH */
208 #define CPP_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? CPP_CPU32_DEFAULT_SPEC : CPP_CPU64_DEFAULT_SPEC)
209 #define ASM_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? ASM_CPU32_DEFAULT_SPEC : ASM_CPU64_DEFAULT_SPEC)
211 #endif /* !SPARC_BI_ARCH */
213 /* Define macros to distinguish architectures. */
215 /* Common CPP definitions used by CPP_SPEC amongst the various targets
216 for handling -mcpu=xxx switches. */
217 #define CPP_CPU_SPEC "\
218 %{msoft-float:-D_SOFT_FLOAT} \
220 %{msparclite:-D__sparclite__} \
221 %{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \
222 %{mv8:-D__sparc_v8__} \
223 %{msupersparc:-D__supersparc__ -D__sparc_v8__} \
224 %{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \
225 %{mcpu=sparclite:-D__sparclite__} \
226 %{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \
227 %{mcpu=v8:-D__sparc_v8__} \
228 %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \
229 %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \
230 %{mcpu=sparclite86x:-D__sparclite86x__} \
231 %{mcpu=v9:-D__sparc_v9__} \
232 %{mcpu=ultrasparc:-D__sparc_v9__} \
233 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \
236 /* ??? The GCC_NEW_VARARGS macro is now obsolete, because gcc always uses
237 the right varags.h file when bootstrapping. */
238 /* ??? It's not clear what value we want to use for -Acpu/machine for
239 sparc64 in 32 bit environments, so for now we only use `sparc64' in
240 64 bit environments. */
244 #define CPP_ARCH32_SPEC "-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int \
245 -D__GCC_NEW_VARARGS__ -Acpu=sparc -Amachine=sparc"
246 #define CPP_ARCH64_SPEC "-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int \
247 -D__arch64__ -Acpu=sparc64 -Amachine=sparc64"
251 #define CPP_ARCH32_SPEC "-D__GCC_NEW_VARARGS__ -Acpu=sparc -Amachine=sparc"
252 #define CPP_ARCH64_SPEC "-D__arch64__ -Acpu=sparc64 -Amachine=sparc64"
256 #define CPP_ARCH_DEFAULT_SPEC \
257 (DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC)
259 #define CPP_ARCH_SPEC "\
260 %{m32:%(cpp_arch32)} \
261 %{m64:%(cpp_arch64)} \
262 %{!m32:%{!m64:%(cpp_arch_default)}} \
265 /* Macros to distinguish endianness. */
266 #define CPP_ENDIAN_SPEC "\
267 %{mlittle-endian:-D__LITTLE_ENDIAN__} \
268 %{mlittle-endian-data:-D__LITTLE_ENDIAN_DATA__}"
270 /* Macros to distinguish the particular subtarget. */
271 #define CPP_SUBTARGET_SPEC ""
273 #define CPP_SPEC "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_subtarget)"
275 /* Prevent error on `-sun4' and `-target sun4' options. */
276 /* This used to translate -dalign to -malign, but that is no good
277 because it can't turn off the usual meaning of making debugging dumps. */
278 /* Translate old style -m<cpu> into new style -mcpu=<cpu>.
279 ??? Delete support for -m<cpu> for 2.9. */
282 %{sun4:} %{target:} \
283 %{mcypress:-mcpu=cypress} \
284 %{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \
285 %{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \
288 /* Override in target specific files. */
289 #define ASM_CPU_SPEC "\
290 %{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \
291 %{msparclite:-Asparclite} \
292 %{mf930:-Asparclite} %{mf934:-Asparclite} \
293 %{mcpu=sparclite:-Asparclite} \
294 %{mcpu=sparclite86x:-Asparclite} \
295 %{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \
296 %{mv8plus:-Av8plus} \
298 %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \
299 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_cpu_default)}}}}}}} \
302 /* Word size selection, among other things.
303 This is what GAS uses. Add %(asm_arch) to ASM_SPEC to enable. */
305 #define ASM_ARCH32_SPEC "-32"
306 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
307 #define ASM_ARCH64_SPEC "-64 -no-undeclared-regs"
309 #define ASM_ARCH64_SPEC "-64"
311 #define ASM_ARCH_DEFAULT_SPEC \
312 (DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC)
314 #define ASM_ARCH_SPEC "\
315 %{m32:%(asm_arch32)} \
316 %{m64:%(asm_arch64)} \
317 %{!m32:%{!m64:%(asm_arch_default)}} \
320 #ifdef HAVE_AS_RELAX_OPTION
321 #define ASM_RELAX_SPEC "%{!mno-relax:-relax}"
323 #define ASM_RELAX_SPEC ""
326 /* Special flags to the Sun-4 assembler when using pipe for input. */
329 %| %{R} %{!pg:%{!p:%{fpic:-k} %{fPIC:-k}}} %{keep-local-as-symbols:-L} \
330 %(asm_cpu) %(asm_relax)"
332 /* This macro defines names of additional specifications to put in the specs
333 that can be used in various specifications like CC1_SPEC. Its definition
334 is an initializer with a subgrouping for each command option.
336 Each subgrouping contains a string constant, that defines the
337 specification name, and a string constant that used by the GNU CC driver
340 Do not define this macro if it does not need to do anything. */
342 #define EXTRA_SPECS \
343 { "cpp_cpu", CPP_CPU_SPEC }, \
344 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
345 { "cpp_arch32", CPP_ARCH32_SPEC }, \
346 { "cpp_arch64", CPP_ARCH64_SPEC }, \
347 { "cpp_arch_default", CPP_ARCH_DEFAULT_SPEC },\
348 { "cpp_arch", CPP_ARCH_SPEC }, \
349 { "cpp_endian", CPP_ENDIAN_SPEC }, \
350 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \
351 { "asm_cpu", ASM_CPU_SPEC }, \
352 { "asm_cpu_default", ASM_CPU_DEFAULT_SPEC }, \
353 { "asm_arch32", ASM_ARCH32_SPEC }, \
354 { "asm_arch64", ASM_ARCH64_SPEC }, \
355 { "asm_relax", ASM_RELAX_SPEC }, \
356 { "asm_arch_default", ASM_ARCH_DEFAULT_SPEC },\
357 { "asm_arch", ASM_ARCH_SPEC }, \
358 SUBTARGET_EXTRA_SPECS
360 #define SUBTARGET_EXTRA_SPECS
363 #define NO_BUILTIN_PTRDIFF_TYPE
364 #define NO_BUILTIN_SIZE_TYPE
366 #define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int")
367 #define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int")
369 /* ??? This should be 32 bits for v9 but what can we do? */
370 #define WCHAR_TYPE "short unsigned int"
371 #define WCHAR_TYPE_SIZE 16
372 #define MAX_WCHAR_TYPE_SIZE 16
374 /* Show we can debug even without a frame pointer. */
375 #define CAN_DEBUG_WITHOUT_FP
377 /* To make profiling work with -f{pic,PIC}, we need to emit the profiling
378 code into the rtl. Also, if we are profiling, we cannot eliminate
379 the frame pointer (because the return address will get smashed). */
381 #define OVERRIDE_OPTIONS \
383 if (profile_flag || profile_arc_flag) \
387 const char *const pic_string = (flag_pic == 1) ? "-fpic" : "-fPIC";\
388 warning ("%s and profiling conflict: disabling %s", \
389 pic_string, pic_string); \
392 flag_omit_frame_pointer = 0; \
394 sparc_override_options (); \
395 SUBTARGET_OVERRIDE_OPTIONS; \
398 /* This is meant to be redefined in the host dependent files. */
399 #define SUBTARGET_OVERRIDE_OPTIONS
401 /* Generate DBX debugging information. */
403 #define DBX_DEBUGGING_INFO
405 /* Run-time compilation parameters selecting different hardware subsets. */
407 extern int target_flags;
409 /* Nonzero if we should generate code to use the fpu. */
411 #define TARGET_FPU (target_flags & MASK_FPU)
413 /* Nonzero if we should use function_epilogue(). Otherwise, we
414 use fast return insns, but lose some generality. */
415 #define MASK_EPILOGUE 2
416 #define TARGET_EPILOGUE (target_flags & MASK_EPILOGUE)
418 /* Nonzero if we should assume that double pointers might be unaligned.
419 This can happen when linking gcc compiled code with other compilers,
420 because the ABI only guarantees 4 byte alignment. */
421 #define MASK_UNALIGNED_DOUBLES 4
422 #define TARGET_UNALIGNED_DOUBLES (target_flags & MASK_UNALIGNED_DOUBLES)
424 /* Nonzero means that we should generate code for a v8 sparc. */
426 #define TARGET_V8 (target_flags & MASK_V8)
428 /* Nonzero means that we should generate code for a sparclite.
429 This enables the sparclite specific instructions, but does not affect
430 whether FPU instructions are emitted. */
431 #define MASK_SPARCLITE 0x10
432 #define TARGET_SPARCLITE (target_flags & MASK_SPARCLITE)
434 /* Nonzero if we're compiling for the sparclet. */
435 #define MASK_SPARCLET 0x20
436 #define TARGET_SPARCLET (target_flags & MASK_SPARCLET)
438 /* Nonzero if we're compiling for v9 sparc.
439 Note that v9's can run in 32 bit mode so this doesn't necessarily mean
440 the word size is 64. */
442 #define TARGET_V9 (target_flags & MASK_V9)
444 /* Non-zero to generate code that uses the instructions deprecated in
445 the v9 architecture. This option only applies to v9 systems. */
446 /* ??? This isn't user selectable yet. It's used to enable such insns
447 on 32 bit v9 systems and for the moment they're permanently disabled
448 on 64 bit v9 systems. */
449 #define MASK_DEPRECATED_V8_INSNS 0x80
450 #define TARGET_DEPRECATED_V8_INSNS (target_flags & MASK_DEPRECATED_V8_INSNS)
452 /* Mask of all CPU selection flags. */
454 (MASK_V8 + MASK_SPARCLITE + MASK_SPARCLET + MASK_V9 + MASK_DEPRECATED_V8_INSNS)
456 /* Non-zero means don't pass `-assert pure-text' to the linker. */
457 #define MASK_IMPURE_TEXT 0x100
458 #define TARGET_IMPURE_TEXT (target_flags & MASK_IMPURE_TEXT)
460 /* Nonzero means that we should generate code using a flat register window
461 model, i.e. no save/restore instructions are generated, which is
462 compatible with normal sparc code.
463 The frame pointer is %i7 instead of %fp. */
464 #define MASK_FLAT 0x200
465 #define TARGET_FLAT (target_flags & MASK_FLAT)
467 /* Nonzero means use the registers that the Sparc ABI reserves for
468 application software. This must be the default to coincide with the
469 setting in FIXED_REGISTERS. */
470 #define MASK_APP_REGS 0x400
471 #define TARGET_APP_REGS (target_flags & MASK_APP_REGS)
473 /* Option to select how quad word floating point is implemented.
474 When TARGET_HARD_QUAD is true, we use the hardware quad instructions.
475 Otherwise, we use the SPARC ABI quad library functions. */
476 #define MASK_HARD_QUAD 0x800
477 #define TARGET_HARD_QUAD (target_flags & MASK_HARD_QUAD)
479 /* Non-zero on little-endian machines. */
480 /* ??? Little endian support currently only exists for sparclet-aout and
481 sparc64-elf configurations. May eventually want to expand the support
482 to all targets, but for now it's kept local to only those two. */
483 #define MASK_LITTLE_ENDIAN 0x1000
484 #define TARGET_LITTLE_ENDIAN (target_flags & MASK_LITTLE_ENDIAN)
486 /* 0x2000, 0x4000 are unused */
488 /* Nonzero if pointers are 64 bits. */
489 #define MASK_PTR64 0x8000
490 #define TARGET_PTR64 (target_flags & MASK_PTR64)
492 /* Nonzero if generating code to run in a 64 bit environment.
493 This is intended to only be used by TARGET_ARCH{32,64} as they are the
494 mechanism used to control compile time or run time selection. */
495 #define MASK_64BIT 0x10000
496 #define TARGET_64BIT (target_flags & MASK_64BIT)
498 /* 0x20000,0x40000 unused */
500 /* Non-zero means use a stack bias of 2047. Stack offsets are obtained by
501 adding 2047 to %sp. This option is for v9 only and is the default. */
502 #define MASK_STACK_BIAS 0x80000
503 #define TARGET_STACK_BIAS (target_flags & MASK_STACK_BIAS)
505 /* 0x100000,0x200000 unused */
507 /* Non-zero means -m{,no-}fpu was passed on the command line. */
508 #define MASK_FPU_SET 0x400000
509 #define TARGET_FPU_SET (target_flags & MASK_FPU_SET)
511 /* Use the UltraSPARC Visual Instruction Set extensions. */
512 #define MASK_VIS 0x1000000
513 #define TARGET_VIS (target_flags & MASK_VIS)
515 /* Compile for Solaris V8+. 32 bit Solaris preserves the high bits of
516 the current out and global registers and Linux 2.2+ as well. */
517 #define MASK_V8PLUS 0x2000000
518 #define TARGET_V8PLUS (target_flags & MASK_V8PLUS)
520 /* Force a the fastest alignment on structures to take advantage of
522 #define MASK_FASTER_STRUCTS 0x4000000
523 #define TARGET_FASTER_STRUCTS (target_flags & MASK_FASTER_STRUCTS)
525 /* Use IEEE quad long double. */
526 #define MASK_LONG_DOUBLE_128 0x8000000
527 #define TARGET_LONG_DOUBLE_128 (target_flags & MASK_LONG_DOUBLE_128)
529 /* TARGET_HARD_MUL: Use hardware multiply instructions but not %y.
530 TARGET_HARD_MUL32: Use hardware multiply instructions with rd %y
531 to get high 32 bits. False in V8+ or V9 because multiply stores
532 a 64 bit result in a register. */
534 #define TARGET_HARD_MUL32 \
535 ((TARGET_V8 || TARGET_SPARCLITE \
536 || TARGET_SPARCLET || TARGET_DEPRECATED_V8_INSNS) \
537 && ! TARGET_V8PLUS && TARGET_ARCH32)
539 #define TARGET_HARD_MUL \
540 (TARGET_V8 || TARGET_SPARCLITE || TARGET_SPARCLET \
541 || TARGET_DEPRECATED_V8_INSNS || TARGET_V8PLUS)
544 /* Macro to define tables used to set the flags.
545 This is a list in braces of pairs in braces,
546 each pair being { "NAME", VALUE }
547 where VALUE is the bits to set or minus the bits to clear.
548 An empty string NAME is used to identify the default VALUE. */
550 #define TARGET_SWITCHES \
551 { {"fpu", MASK_FPU | MASK_FPU_SET, \
552 N_("Use hardware fp") }, \
553 {"no-fpu", -MASK_FPU, \
554 N_("Do not use hardware fp") }, \
555 {"no-fpu", MASK_FPU_SET, NULL, }, \
556 {"hard-float", MASK_FPU | MASK_FPU_SET, \
557 N_("Use hardware fp") }, \
558 {"soft-float", -MASK_FPU, \
559 N_("Do not use hardware fp") }, \
560 {"soft-float", MASK_FPU_SET, NULL }, \
561 {"epilogue", MASK_EPILOGUE, \
562 N_("Use function_epilogue()") }, \
563 {"no-epilogue", -MASK_EPILOGUE, \
564 N_("Do not use function_epilogue()") }, \
565 {"unaligned-doubles", MASK_UNALIGNED_DOUBLES, \
566 N_("Assume possible double misalignment") }, \
567 {"no-unaligned-doubles", -MASK_UNALIGNED_DOUBLES, \
568 N_("Assume all doubles are aligned") }, \
569 {"impure-text", MASK_IMPURE_TEXT, \
570 N_("Pass -assert pure-text to linker") }, \
571 {"no-impure-text", -MASK_IMPURE_TEXT, \
572 N_("Do not pass -assert pure-text to linker") }, \
573 {"flat", MASK_FLAT, \
574 N_("Use flat register window model") }, \
575 {"no-flat", -MASK_FLAT, \
576 N_("Do not use flat register window model") }, \
577 {"app-regs", MASK_APP_REGS, \
578 N_("Use ABI reserved registers") }, \
579 {"no-app-regs", -MASK_APP_REGS, \
580 N_("Do not use ABI reserved registers") }, \
581 {"hard-quad-float", MASK_HARD_QUAD, \
582 N_("Use hardware quad fp instructions") }, \
583 {"soft-quad-float", -MASK_HARD_QUAD, \
584 N_("Do not use hardware quad fp instructions") }, \
585 {"v8plus", MASK_V8PLUS, \
586 N_("Compile for v8plus ABI") }, \
587 {"no-v8plus", -MASK_V8PLUS, \
588 N_("Do not compile for v8plus ABI") }, \
590 N_("Utilize Visual Instruction Set") }, \
591 {"no-vis", -MASK_VIS, \
592 N_("Do not utilize Visual Instruction Set") }, \
593 /* ??? These are deprecated, coerced to -mcpu=. Delete in 2.9. */ \
595 N_("Optimize for Cypress processors") }, \
597 N_("Optimize for SparcLite processors") }, \
599 N_("Optimize for F930 processors") }, \
601 N_("Optimize for F934 processors") }, \
603 N_("Use V8 Sparc ISA") }, \
605 N_("Optimize for SuperSparc processors") }, \
606 /* End of deprecated options. */ \
607 {"ptr64", MASK_PTR64, \
608 N_("Pointers are 64-bit") }, \
609 {"ptr32", -MASK_PTR64, \
610 N_("Pointers are 32-bit") }, \
611 {"32", -MASK_64BIT, \
612 N_("Use 32-bit ABI") }, \
614 N_("Use 64-bit ABI") }, \
615 {"stack-bias", MASK_STACK_BIAS, \
616 N_("Use stack bias") }, \
617 {"no-stack-bias", -MASK_STACK_BIAS, \
618 N_("Do not use stack bias") }, \
619 {"faster-structs", MASK_FASTER_STRUCTS, \
620 N_("Use structs on stronger alignment for double-word copies") }, \
621 {"no-faster-structs", -MASK_FASTER_STRUCTS, \
622 N_("Do not use structs on stronger alignment for double-word copies") }, \
624 N_("Optimize tail call instructions in assembler and linker") }, \
626 N_("Do not optimize tail call instructions in assembler or linker") }, \
628 { "", TARGET_DEFAULT, ""}}
630 /* MASK_APP_REGS must always be the default because that's what
631 FIXED_REGISTERS is set to and -ffixed- is processed before
632 CONDITIONAL_REGISTER_USAGE is called (where we process -mno-app-regs). */
633 #define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU)
635 /* This is meant to be redefined in target specific files. */
636 #define SUBTARGET_SWITCHES
639 These must match the values for the cpu attribute in sparc.md. */
640 enum processor_type {
644 PROCESSOR_SUPERSPARC,
648 PROCESSOR_HYPERSPARC,
649 PROCESSOR_SPARCLITE86X,
656 /* This is set from -m{cpu,tune}=xxx. */
657 extern enum processor_type sparc_cpu;
659 /* Recast the cpu class to be the cpu attribute.
660 Every file includes us, but not every file includes insn-attr.h. */
661 #define sparc_cpu_attr ((enum attr_cpu) sparc_cpu)
663 #define TARGET_OPTIONS \
665 { "cpu=", &sparc_select[1].string, \
666 N_("Use features of and schedule code for given CPU") }, \
667 { "tune=", &sparc_select[2].string, \
668 N_("Schedule code for given CPU") }, \
669 { "cmodel=", &sparc_cmodel_string, \
670 N_("Use given Sparc code model") }, \
674 /* This is meant to be redefined in target specific files. */
675 #define SUBTARGET_OPTIONS
677 /* sparc_select[0] is reserved for the default cpu. */
678 struct sparc_cpu_select
681 const char *const name;
682 const int set_tune_p;
683 const int set_arch_p;
686 extern struct sparc_cpu_select sparc_select[];
688 /* target machine storage layout */
690 /* Define this if most significant bit is lowest numbered
691 in instructions that operate on numbered bit-fields. */
692 #define BITS_BIG_ENDIAN 1
694 /* Define this if most significant byte of a word is the lowest numbered. */
695 #define BYTES_BIG_ENDIAN 1
697 /* Define this if most significant word of a multiword number is the lowest
699 #define WORDS_BIG_ENDIAN 1
701 /* Define this to set the endianness to use in libgcc2.c, which can
702 not depend on target_flags. */
703 #if defined (__LITTLE_ENDIAN__) || defined(__LITTLE_ENDIAN_DATA__)
704 #define LIBGCC2_WORDS_BIG_ENDIAN 0
706 #define LIBGCC2_WORDS_BIG_ENDIAN 1
709 #define MAX_BITS_PER_WORD 64
711 /* Width of a word, in units (bytes). */
712 #define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4)
713 #define MIN_UNITS_PER_WORD 4
715 /* Now define the sizes of the C data types. */
717 #define SHORT_TYPE_SIZE 16
718 #define INT_TYPE_SIZE 32
719 #define LONG_TYPE_SIZE (TARGET_ARCH64 ? 64 : 32)
720 #define LONG_LONG_TYPE_SIZE 64
721 #define FLOAT_TYPE_SIZE 32
722 #define DOUBLE_TYPE_SIZE 64
725 #define MAX_LONG_TYPE_SIZE 64
729 /* ??? This does not work in SunOS 4.x, so it is not enabled here.
730 Instead, it is enabled in sol2.h, because it does work under Solaris. */
731 /* Define for support of TFmode long double.
732 Sparc ABI says that long double is 4 words. */
733 #define LONG_DOUBLE_TYPE_SIZE 128
736 /* Width in bits of a pointer.
737 See also the macro `Pmode' defined below. */
738 #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32)
740 /* If we have to extend pointers (only when TARGET_ARCH64 and not
741 TARGET_PTR64), we want to do it unsigned. This macro does nothing
742 if ptr_mode and Pmode are the same. */
743 #define POINTERS_EXTEND_UNSIGNED 1
745 /* A macro to update MODE and UNSIGNEDP when an object whose type
746 is TYPE and which has the specified mode and signedness is to be
747 stored in a register. This macro is only called when TYPE is a
749 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
751 && GET_MODE_CLASS (MODE) == MODE_INT \
752 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
755 /* Define this macro if the promotion described by PROMOTE_MODE
756 should also be done for outgoing function arguments. */
757 /* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op
758 for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test
760 #define PROMOTE_FUNCTION_ARGS
762 /* Define this macro if the promotion described by PROMOTE_MODE
763 should also be done for the return value of functions.
764 If this macro is defined, FUNCTION_VALUE must perform the same
765 promotions done by PROMOTE_MODE. */
766 /* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op
767 for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test
769 #define PROMOTE_FUNCTION_RETURN
771 /* Define this macro if the promotion described by PROMOTE_MODE
772 should _only_ be performed for outgoing function arguments or
773 function return values, as specified by PROMOTE_FUNCTION_ARGS
774 and PROMOTE_FUNCTION_RETURN, respectively. */
775 /* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op
776 for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test
777 for this value. For TARGET_ARCH64 we need it, as we don't have instructions
778 for arithmetic operations which do zero/sign extension at the same time,
779 so without this we end up with a srl/sra after every assignment to an
780 user variable, which means very very bad code. */
781 #define PROMOTE_FOR_CALL_ONLY
783 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
784 #define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
786 /* Boundary (in *bits*) on which stack pointer should be aligned. */
787 #define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64)
789 /* ALIGN FRAMES on double word boundaries */
791 #define SPARC_STACK_ALIGN(LOC) \
792 (TARGET_ARCH64 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7))
794 /* Allocation boundary (in *bits*) for the code of a function. */
795 #define FUNCTION_BOUNDARY 32
797 /* Alignment of field after `int : 0' in a structure. */
798 #define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
800 /* Every structure's size must be a multiple of this. */
801 #define STRUCTURE_SIZE_BOUNDARY 8
803 /* A bitfield declared as `int' forces `int' alignment for the struct. */
804 #define PCC_BITFIELD_TYPE_MATTERS 1
806 /* No data type wants to be aligned rounder than this. */
807 #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64)
809 /* The best alignment to use in cases where we have a choice. */
810 #define FASTEST_ALIGNMENT 64
812 /* Define this macro as an expression for the alignment of a structure
813 (given by STRUCT as a tree node) if the alignment computed in the
814 usual way is COMPUTED and the alignment explicitly specified was
817 The default is to use SPECIFIED if it is larger; otherwise, use
818 the smaller of COMPUTED and `BIGGEST_ALIGNMENT' */
819 #define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \
820 (TARGET_FASTER_STRUCTS ? \
821 ((TREE_CODE (STRUCT) == RECORD_TYPE \
822 || TREE_CODE (STRUCT) == UNION_TYPE \
823 || TREE_CODE (STRUCT) == QUAL_UNION_TYPE) \
824 && TYPE_FIELDS (STRUCT) != 0 \
825 ? MAX (MAX ((COMPUTED), (SPECIFIED)), BIGGEST_ALIGNMENT) \
826 : MAX ((COMPUTED), (SPECIFIED))) \
827 : MAX ((COMPUTED), (SPECIFIED)))
829 /* Make strings word-aligned so strcpy from constants will be faster. */
830 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
831 ((TREE_CODE (EXP) == STRING_CST \
832 && (ALIGN) < FASTEST_ALIGNMENT) \
833 ? FASTEST_ALIGNMENT : (ALIGN))
835 /* Make arrays of chars word-aligned for the same reasons. */
836 #define DATA_ALIGNMENT(TYPE, ALIGN) \
837 (TREE_CODE (TYPE) == ARRAY_TYPE \
838 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
839 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
841 /* Set this nonzero if move instructions will actually fail to work
842 when given unaligned data. */
843 #define STRICT_ALIGNMENT 1
845 /* Things that must be doubleword aligned cannot go in the text section,
846 because the linker fails to align the text section enough!
847 Put them in the data section. This macro is only used in this file. */
848 #define MAX_TEXT_ALIGN 32
850 /* This forces all variables and constants to the data section when PIC.
851 This is because the SunOS 4 shared library scheme thinks everything in
852 text is a function, and patches the address to point to a loader stub. */
853 /* This is defined to zero for every system which doesn't use the a.out object
855 #ifndef SUNOS4_SHARED_LIBRARIES
856 #define SUNOS4_SHARED_LIBRARIES 0
860 /* Use text section for a constant
861 unless we need more alignment than that offers. */
862 /* This is defined differently for v9 in a cover file. */
863 #define SELECT_RTX_SECTION(MODE, X, ALIGN) \
865 if (GET_MODE_BITSIZE (MODE) <= MAX_TEXT_ALIGN \
866 && ! (flag_pic && (symbolic_operand ((X), (MODE)) || SUNOS4_SHARED_LIBRARIES))) \
872 /* Standard register usage. */
874 /* Number of actual hardware registers.
875 The hardware registers are assigned numbers for the compiler
876 from 0 to just below FIRST_PSEUDO_REGISTER.
877 All registers that the compiler knows about must be given numbers,
878 even those that are not normally considered general registers.
880 SPARC has 32 integer registers and 32 floating point registers.
881 64 bit SPARC has 32 additional fp regs, but the odd numbered ones are not
882 accessible. We still account for them to simplify register computations
883 (eg: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so
885 Register 100 is used as the integer condition code register.
886 Register 101 is used as the soft frame pointer register. */
888 #define FIRST_PSEUDO_REGISTER 102
890 #define SPARC_FIRST_FP_REG 32
891 /* Additional V9 fp regs. */
892 #define SPARC_FIRST_V9_FP_REG 64
893 #define SPARC_LAST_V9_FP_REG 95
894 /* V9 %fcc[0123]. V8 uses (figuratively) %fcc0. */
895 #define SPARC_FIRST_V9_FCC_REG 96
896 #define SPARC_LAST_V9_FCC_REG 99
898 #define SPARC_FCC_REG 96
899 /* Integer CC reg. We don't distinguish %icc from %xcc. */
900 #define SPARC_ICC_REG 100
902 /* Nonzero if REGNO is an fp reg. */
903 #define SPARC_FP_REG_P(REGNO) \
904 ((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG)
906 /* Argument passing regs. */
907 #define SPARC_OUTGOING_INT_ARG_FIRST 8
908 #define SPARC_INCOMING_INT_ARG_FIRST (TARGET_FLAT ? 8 : 24)
909 #define SPARC_FP_ARG_FIRST 32
911 /* 1 for registers that have pervasive standard uses
912 and are not available for the register allocator.
915 g1 is free to use as temporary.
916 g2-g4 are reserved for applications. Gcc normally uses them as
917 temporaries, but this can be disabled via the -mno-app-regs option.
918 g5 through g7 are reserved for the operating system.
921 g1,g5 are free to use as temporaries, and are free to use between calls
922 if the call is to an external function via the PLT.
923 g4 is free to use as a temporary in the non-embedded case.
924 g4 is reserved in the embedded case.
925 g2-g3 are reserved for applications. Gcc normally uses them as
926 temporaries, but this can be disabled via the -mno-app-regs option.
927 g6-g7 are reserved for the operating system (or application in
929 ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must
930 currently be a fixed register until this pattern is rewritten.
931 Register 1 is also used when restoring call-preserved registers in large
934 Registers fixed in arch32 and not arch64 (or vice-versa) are marked in
935 CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-.
938 #define FIXED_REGISTERS \
939 {1, 0, 2, 2, 2, 2, 1, 1, \
940 0, 0, 0, 0, 0, 0, 1, 0, \
941 0, 0, 0, 0, 0, 0, 0, 0, \
942 0, 0, 0, 0, 0, 0, 1, 1, \
944 0, 0, 0, 0, 0, 0, 0, 0, \
945 0, 0, 0, 0, 0, 0, 0, 0, \
946 0, 0, 0, 0, 0, 0, 0, 0, \
947 0, 0, 0, 0, 0, 0, 0, 0, \
949 0, 0, 0, 0, 0, 0, 0, 0, \
950 0, 0, 0, 0, 0, 0, 0, 0, \
951 0, 0, 0, 0, 0, 0, 0, 0, \
952 0, 0, 0, 0, 0, 0, 0, 0, \
956 /* 1 for registers not available across function calls.
957 These must include the FIXED_REGISTERS and also any
958 registers that can be used without being saved.
959 The latter must include the registers where values are returned
960 and the register where structure-value addresses are passed.
961 Aside from that, you can include as many other registers as you like. */
963 #define CALL_USED_REGISTERS \
964 {1, 1, 1, 1, 1, 1, 1, 1, \
965 1, 1, 1, 1, 1, 1, 1, 1, \
966 0, 0, 0, 0, 0, 0, 0, 0, \
967 0, 0, 0, 0, 0, 0, 1, 1, \
969 1, 1, 1, 1, 1, 1, 1, 1, \
970 1, 1, 1, 1, 1, 1, 1, 1, \
971 1, 1, 1, 1, 1, 1, 1, 1, \
972 1, 1, 1, 1, 1, 1, 1, 1, \
974 1, 1, 1, 1, 1, 1, 1, 1, \
975 1, 1, 1, 1, 1, 1, 1, 1, \
976 1, 1, 1, 1, 1, 1, 1, 1, \
977 1, 1, 1, 1, 1, 1, 1, 1, \
981 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
982 they won't be allocated. */
984 #define CONDITIONAL_REGISTER_USAGE \
987 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
989 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
990 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
992 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */ \
993 /* then honour it. */ \
994 if (TARGET_ARCH32 && fixed_regs[5]) \
996 else if (TARGET_ARCH64 && fixed_regs[5] == 2) \
1001 for (regno = SPARC_FIRST_V9_FP_REG; \
1002 regno <= SPARC_LAST_V9_FP_REG; \
1004 fixed_regs[regno] = 1; \
1005 /* %fcc0 is used by v8 and v9. */ \
1006 for (regno = SPARC_FIRST_V9_FCC_REG + 1; \
1007 regno <= SPARC_LAST_V9_FCC_REG; \
1009 fixed_regs[regno] = 1; \
1014 for (regno = 32; regno < SPARC_LAST_V9_FCC_REG; regno++) \
1015 fixed_regs[regno] = 1; \
1017 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */ \
1018 /* then honour it. Likewise with g3 and g4. */ \
1019 if (fixed_regs[2] == 2) \
1020 fixed_regs[2] = ! TARGET_APP_REGS; \
1021 if (fixed_regs[3] == 2) \
1022 fixed_regs[3] = ! TARGET_APP_REGS; \
1023 if (TARGET_ARCH32 && fixed_regs[4] == 2) \
1024 fixed_regs[4] = ! TARGET_APP_REGS; \
1025 else if (TARGET_CM_EMBMEDANY) \
1026 fixed_regs[4] = 1; \
1027 else if (fixed_regs[4] == 2) \
1028 fixed_regs[4] = 0; \
1031 /* Let the compiler believe the frame pointer is still \
1032 %fp, but output it as %i7. */ \
1033 fixed_regs[31] = 1; \
1034 reg_names[HARD_FRAME_POINTER_REGNUM] = "%i7"; \
1035 /* Disable leaf functions */ \
1036 memset (sparc_leaf_regs, 0, FIRST_PSEUDO_REGISTER); \
1041 /* Return number of consecutive hard regs needed starting at reg REGNO
1042 to hold something of mode MODE.
1043 This is ordinarily the length in words of a value of mode MODE
1044 but can be less for certain modes in special long registers.
1046 On SPARC, ordinary registers hold 32 bits worth;
1047 this means both integer and floating point registers.
1048 On v9, integer regs hold 64 bits worth; floating point regs hold
1049 32 bits worth (this includes the new fp regs as even the odd ones are
1050 included in the hard register count). */
1052 #define HARD_REGNO_NREGS(REGNO, MODE) \
1054 ? ((REGNO) < 32 || (REGNO) == FRAME_POINTER_REGNUM \
1055 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \
1056 : (GET_MODE_SIZE (MODE) + 3) / 4) \
1057 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1059 /* Due to the ARCH64 descrepancy above we must override this next
1061 #define REGMODE_NATURAL_SIZE(MODE) \
1062 ((TARGET_ARCH64 && FLOAT_MODE_P (MODE)) ? 4 : UNITS_PER_WORD)
1064 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
1065 See sparc.c for how we initialize this. */
1066 extern const int *hard_regno_mode_classes;
1067 extern int sparc_mode_class[];
1069 /* ??? Because of the funny way we pass parameters we should allow certain
1070 ??? types of float/complex values to be in integer registers during
1071 ??? RTL generation. This only matters on arch32. */
1072 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1073 ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0)
1075 /* Value is 1 if it is a good idea to tie two pseudo registers
1076 when one has mode MODE1 and one has mode MODE2.
1077 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1078 for any hard reg, then this must be 0 for correct output.
1080 For V9: SFmode can't be combined with other float modes, because they can't
1081 be allocated to the %d registers. Also, DFmode won't fit in odd %f
1082 registers, but SFmode will. */
1083 #define MODES_TIEABLE_P(MODE1, MODE2) \
1084 ((MODE1) == (MODE2) \
1085 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
1087 || (GET_MODE_CLASS (MODE1) != MODE_FLOAT \
1088 || (MODE1 != SFmode && MODE2 != SFmode)))))
1090 /* Specify the registers used for certain standard purposes.
1091 The values of these macros are register numbers. */
1093 /* SPARC pc isn't overloaded on a register that the compiler knows about. */
1094 /* #define PC_REGNUM */
1096 /* Register to use for pushing function arguments. */
1097 #define STACK_POINTER_REGNUM 14
1099 /* The stack bias (amount by which the hardware register is offset by). */
1100 #define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0)
1102 /* Actual top-of-stack address is 92/176 greater than the contents of the
1103 stack pointer register for !v9/v9. That is:
1104 - !v9: 64 bytes for the in and local registers, 4 bytes for structure return
1105 address, and 6*4 bytes for the 6 register parameters.
1106 - v9: 128 bytes for the in and local registers + 6*8 bytes for the integer
1108 #define STACK_POINTER_OFFSET (FIRST_PARM_OFFSET(0) + SPARC_STACK_BIAS)
1110 /* Base register for access to local variables of the function. */
1111 #define HARD_FRAME_POINTER_REGNUM 30
1113 /* The soft frame pointer does not have the stack bias applied. */
1114 #define FRAME_POINTER_REGNUM 101
1116 /* Given the stack bias, the stack pointer isn't actually aligned. */
1117 #define INIT_EXPANDERS \
1119 if (cfun && cfun->emit->regno_pointer_align && SPARC_STACK_BIAS) \
1121 REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = BITS_PER_UNIT; \
1122 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT; \
1126 /* Value should be nonzero if functions must have frame pointers.
1127 Zero means the frame pointer need not be set up (and parms
1128 may be accessed via the stack pointer) in functions that seem suitable.
1129 This is computed in `reload', in reload1.c.
1130 Used in flow.c, global.c, and reload1.c.
1132 Being a non-leaf function does not mean a frame pointer is needed in the
1133 flat window model. However, the debugger won't be able to backtrace through
1135 #define FRAME_POINTER_REQUIRED \
1137 ? (current_function_calls_alloca \
1138 || current_function_varargs \
1139 || !leaf_function_p ()) \
1140 : ! (leaf_function_p () && only_leaf_regs_used ()))
1142 /* C statement to store the difference between the frame pointer
1143 and the stack pointer values immediately after the function prologue.
1145 Note, we always pretend that this is a leaf function because if
1146 it's not, there's no point in trying to eliminate the
1147 frame pointer. If it is a leaf function, we guessed right! */
1148 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
1149 ((VAR) = (TARGET_FLAT ? sparc_flat_compute_frame_size (get_frame_size ()) \
1150 : compute_frame_size (get_frame_size (), 1)))
1152 /* Base register for access to arguments of the function. */
1153 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM
1155 /* Register in which static-chain is passed to a function. This must
1156 not be a register used by the prologue. */
1157 #define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2)
1159 /* Register which holds offset table for position-independent
1162 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 23 : INVALID_REGNUM)
1164 /* Pick a default value we can notice from override_options:
1166 v9: Default is off. */
1168 #define DEFAULT_PCC_STRUCT_RETURN -1
1170 /* Sparc ABI says that quad-precision floats and all structures are returned
1172 For v9: unions <= 32 bytes in size are returned in int regs,
1173 structures up to 32 bytes are returned in int and fp regs. */
1175 #define RETURN_IN_MEMORY(TYPE) \
1177 ? (TYPE_MODE (TYPE) == BLKmode \
1178 || TYPE_MODE (TYPE) == TFmode \
1179 || TYPE_MODE (TYPE) == TCmode) \
1180 : (TYPE_MODE (TYPE) == BLKmode \
1181 && (unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) > 32))
1183 /* Functions which return large structures get the address
1184 to place the wanted value at offset 64 from the frame.
1185 Must reserve 64 bytes for the in and local registers.
1186 v9: Functions which return large structures get the address to place the
1187 wanted value from an invisible first argument. */
1188 /* Used only in other #defines in this file. */
1189 #define STRUCT_VALUE_OFFSET 64
1191 #define STRUCT_VALUE \
1194 : gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, \
1195 STRUCT_VALUE_OFFSET)))
1197 #define STRUCT_VALUE_INCOMING \
1200 : gen_rtx_MEM (Pmode, plus_constant (frame_pointer_rtx, \
1201 STRUCT_VALUE_OFFSET)))
1203 /* Define the classes of registers for register constraints in the
1204 machine description. Also define ranges of constants.
1206 One of the classes must always be named ALL_REGS and include all hard regs.
1207 If there is more than one class, another class must be named NO_REGS
1208 and contain no registers.
1210 The name GENERAL_REGS must be the name of a class (or an alias for
1211 another name such as ALL_REGS). This is the class of registers
1212 that is allowed by "g" or "r" in a register constraint.
1213 Also, registers outside this class are allocated only when
1214 instructions express preferences for them.
1216 The classes must be numbered in nondecreasing order; that is,
1217 a larger-numbered class must never be contained completely
1218 in a smaller-numbered class.
1220 For any two classes, it is very desirable that there be another
1221 class that represents their union. */
1223 /* The SPARC has various kinds of registers: general, floating point,
1224 and condition codes [well, it has others as well, but none that we
1225 care directly about].
1227 For v9 we must distinguish between the upper and lower floating point
1228 registers because the upper ones can't hold SFmode values.
1229 HARD_REGNO_MODE_OK won't help here because reload assumes that register(s)
1230 satisfying a group need for a class will also satisfy a single need for
1231 that class. EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp
1234 It is important that one class contains all the general and all the standard
1235 fp regs. Otherwise find_reg() won't properly allocate int regs for moves,
1236 because reg_class_record() will bias the selection in favor of fp regs,
1237 because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS,
1238 because FP_REGS > GENERAL_REGS.
1240 It is also important that one class contain all the general and all the
1241 fp regs. Otherwise when spilling a DFmode reg, it may be from EXTRA_FP_REGS
1242 but find_reloads() may use class GENERAL_OR_FP_REGS. This will cause
1243 allocate_reload_reg() to bypass it causing an abort because the compiler
1244 thinks it doesn't have a spill reg when in fact it does.
1246 v9 also has 4 floating point condition code registers. Since we don't
1247 have a class that is the union of FPCC_REGS with either of the others,
1248 it is important that it appear first. Otherwise the compiler will die
1249 trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its
1252 It is important that SPARC_ICC_REG have class NO_REGS. Otherwise combine
1253 may try to use it to hold an SImode value. See register_operand.
1254 ??? Should %fcc[0123] be handled similarly?
1257 enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS,
1258 EXTRA_FP_REGS, GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS,
1259 ALL_REGS, LIM_REG_CLASSES };
1261 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1263 /* Give names of register classes as strings for dump file. */
1265 #define REG_CLASS_NAMES \
1266 { "NO_REGS", "FPCC_REGS", "I64_REGS", "GENERAL_REGS", "FP_REGS", \
1267 "EXTRA_FP_REGS", "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", \
1270 /* Define which registers fit in which classes.
1271 This is an initializer for a vector of HARD_REG_SET
1272 of length N_REG_CLASSES. */
1274 #define REG_CLASS_CONTENTS \
1275 {{0, 0, 0, 0}, /* NO_REGS */ \
1276 {0, 0, 0, 0xf}, /* FPCC_REGS */ \
1277 {0xffff, 0, 0, 0}, /* I64_REGS */ \
1278 {-1, 0, 0, 0x20}, /* GENERAL_REGS */ \
1279 {0, -1, 0, 0}, /* FP_REGS */ \
1280 {0, -1, -1, 0}, /* EXTRA_FP_REGS */ \
1281 {-1, -1, 0, 0x20}, /* GENERAL_OR_FP_REGS */ \
1282 {-1, -1, -1, 0x20}, /* GENERAL_OR_EXTRA_FP_REGS */ \
1283 {-1, -1, -1, 0x3f}} /* ALL_REGS */
1285 /* The same information, inverted:
1286 Return the class number of the smallest class containing
1287 reg number REGNO. This could be a conditional expression
1288 or could index an array. */
1290 extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
1292 #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)]
1294 /* This is the order in which to allocate registers normally.
1296 We put %f0/%f1 last among the float registers, so as to make it more
1297 likely that a pseudo-register which dies in the float return register
1298 will get allocated to the float return register, thus saving a move
1299 instruction at the end of the function. */
1301 #define REG_ALLOC_ORDER \
1302 { 8, 9, 10, 11, 12, 13, 2, 3, \
1303 15, 16, 17, 18, 19, 20, 21, 22, \
1304 23, 24, 25, 26, 27, 28, 29, 31, \
1305 34, 35, 36, 37, 38, 39, /* %f2-%f7 */ \
1306 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \
1307 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \
1308 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \
1309 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \
1310 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \
1311 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \
1312 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \
1313 32, 33, /* %f0,%f1 */ \
1314 96, 97, 98, 99, 100, /* %fcc0-3, %icc */ \
1315 1, 4, 5, 6, 7, 0, 14, 30, 101}
1317 /* This is the order in which to allocate registers for
1318 leaf functions. If all registers can fit in the "gi" registers,
1319 then we have the possibility of having a leaf function. */
1321 #define REG_LEAF_ALLOC_ORDER \
1322 { 2, 3, 24, 25, 26, 27, 28, 29, \
1324 15, 8, 9, 10, 11, 12, 13, \
1325 16, 17, 18, 19, 20, 21, 22, 23, \
1326 34, 35, 36, 37, 38, 39, \
1327 40, 41, 42, 43, 44, 45, 46, 47, \
1328 48, 49, 50, 51, 52, 53, 54, 55, \
1329 56, 57, 58, 59, 60, 61, 62, 63, \
1330 64, 65, 66, 67, 68, 69, 70, 71, \
1331 72, 73, 74, 75, 76, 77, 78, 79, \
1332 80, 81, 82, 83, 84, 85, 86, 87, \
1333 88, 89, 90, 91, 92, 93, 94, 95, \
1335 96, 97, 98, 99, 100, \
1338 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
1340 extern char sparc_leaf_regs[];
1341 #define LEAF_REGISTERS sparc_leaf_regs
1343 extern const char leaf_reg_remap[];
1344 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO])
1346 /* The class value for index registers, and the one for base regs. */
1347 #define INDEX_REG_CLASS GENERAL_REGS
1348 #define BASE_REG_CLASS GENERAL_REGS
1350 /* Local macro to handle the two v9 classes of FP regs. */
1351 #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS)
1353 /* Get reg_class from a letter such as appears in the machine description.
1354 In the not-v9 case, coerce v9's 'e' class to 'f', so we can use 'e' in the
1355 .md file for v8 and v9.
1356 'd' and 'b' are used for single and double precision VIS operations,
1358 'h' is used for V8+ 64 bit global and out registers. */
1360 #define REG_CLASS_FROM_LETTER(C) \
1362 ? ((C) == 'f' ? FP_REGS \
1363 : (C) == 'e' ? EXTRA_FP_REGS \
1364 : (C) == 'c' ? FPCC_REGS \
1365 : ((C) == 'd' && TARGET_VIS) ? FP_REGS\
1366 : ((C) == 'b' && TARGET_VIS) ? EXTRA_FP_REGS\
1367 : ((C) == 'h' && TARGET_V8PLUS) ? I64_REGS\
1369 : ((C) == 'f' ? FP_REGS \
1370 : (C) == 'e' ? FP_REGS \
1371 : (C) == 'c' ? FPCC_REGS \
1374 /* The letters I, J, K, L and M in a register constraint string
1375 can be used to stand for particular ranges of immediate operands.
1376 This macro defines what the ranges are.
1377 C is the letter, and VALUE is a constant value.
1378 Return 1 if VALUE is in the range specified by C.
1380 `I' is used for the range of constants an insn can actually contain.
1381 `J' is used for the range which is just zero (since that is R0).
1382 `K' is used for constants which can be loaded with a single sethi insn.
1383 `L' is used for the range of constants supported by the movcc insns.
1384 `M' is used for the range of constants supported by the movrcc insns.
1385 `N' is like K, but for constants wider than 32 bits. */
1387 #define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400)
1388 #define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800)
1389 #define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000)
1390 /* 10 and 11 bit immediates are only used for a few specific insns.
1391 SMALL_INT is used throughout the port so we continue to use it. */
1392 #define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X)))
1393 /* 13 bit immediate, considering only the low 32 bits */
1394 #define SMALL_INT32(X) (SPARC_SIMM13_P (trunc_int_for_mode \
1395 (INTVAL (X), SImode)))
1396 #define SPARC_SETHI_P(X) \
1397 (((unsigned HOST_WIDE_INT) (X) \
1398 & ((unsigned HOST_WIDE_INT) 0x3ff - GET_MODE_MASK (SImode) - 1)) == 0)
1399 #define SPARC_SETHI32_P(X) \
1400 (SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode)))
1402 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1403 ((C) == 'I' ? SPARC_SIMM13_P (VALUE) \
1404 : (C) == 'J' ? (VALUE) == 0 \
1405 : (C) == 'K' ? SPARC_SETHI32_P (VALUE) \
1406 : (C) == 'L' ? SPARC_SIMM11_P (VALUE) \
1407 : (C) == 'M' ? SPARC_SIMM10_P (VALUE) \
1408 : (C) == 'N' ? SPARC_SETHI_P (VALUE) \
1411 /* Similar, but for floating constants, and defining letters G and H.
1412 Here VALUE is the CONST_DOUBLE rtx itself. */
1414 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1415 ((C) == 'G' ? fp_zero_operand (VALUE, GET_MODE (VALUE)) \
1416 : (C) == 'H' ? arith_double_operand (VALUE, DImode) \
1419 /* Given an rtx X being reloaded into a reg required to be
1420 in class CLASS, return the class of reg to actually use.
1421 In general this is just CLASS; but on some machines
1422 in some cases it is preferable to use a more restrictive class. */
1423 /* - We can't load constants into FP registers.
1424 - We can't load FP constants into integer registers when soft-float,
1425 because there is no soft-float pattern with a r/F constraint.
1426 - We can't load FP constants into integer registers for TFmode unless
1427 it is 0.0L, because there is no movtf pattern with a r/F constraint.
1428 - Try and reload integer constants (symbolic or otherwise) back into
1429 registers directly, rather than having them dumped to memory. */
1431 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1433 ? ((FP_REG_CLASS_P (CLASS) \
1434 || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1436 || (GET_MODE (X) == TFmode \
1437 && ! fp_zero_operand (X, TFmode))) \
1439 : (!FP_REG_CLASS_P (CLASS) \
1440 && GET_MODE_CLASS (GET_MODE (X)) == MODE_INT) \
1445 /* Return the register class of a scratch register needed to load IN into
1446 a register of class CLASS in MODE.
1448 We need a temporary when loading/storing a HImode/QImode value
1449 between memory and the FPU registers. This can happen when combine puts
1450 a paradoxical subreg in a float/fix conversion insn. */
1452 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1453 ((FP_REG_CLASS_P (CLASS) \
1454 && ((MODE) == HImode || (MODE) == QImode) \
1455 && (GET_CODE (IN) == MEM \
1456 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1457 && true_regnum (IN) == -1))) \
1459 : (((TARGET_CM_MEDANY \
1460 && symbolic_operand ((IN), (MODE))) \
1461 || (TARGET_CM_EMBMEDANY \
1462 && text_segment_operand ((IN), (MODE)))) \
1467 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1468 ((FP_REG_CLASS_P (CLASS) \
1469 && ((MODE) == HImode || (MODE) == QImode) \
1470 && (GET_CODE (IN) == MEM \
1471 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1472 && true_regnum (IN) == -1))) \
1474 : (((TARGET_CM_MEDANY \
1475 && symbolic_operand ((IN), (MODE))) \
1476 || (TARGET_CM_EMBMEDANY \
1477 && text_segment_operand ((IN), (MODE)))) \
1482 /* On SPARC it is not possible to directly move data between
1483 GENERAL_REGS and FP_REGS. */
1484 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1485 (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2))
1487 /* Return the stack location to use for secondary memory needed reloads.
1488 We want to use the reserved location just below the frame pointer.
1489 However, we must ensure that there is a frame, so use assign_stack_local
1490 if the frame size is zero. */
1491 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
1492 (get_frame_size () == 0 \
1493 ? assign_stack_local (MODE, GET_MODE_SIZE (MODE), 0) \
1494 : gen_rtx_MEM (MODE, plus_constant (frame_pointer_rtx, \
1495 STARTING_FRAME_OFFSET)))
1497 /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9
1498 because the movsi and movsf patterns don't handle r/f moves.
1499 For v8 we copy the default definition. */
1500 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
1502 ? (GET_MODE_BITSIZE (MODE) < 32 \
1503 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
1505 : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \
1506 ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0) \
1509 /* Return the maximum number of consecutive registers
1510 needed to represent mode MODE in a register of class CLASS. */
1511 /* On SPARC, this is the size of MODE in words. */
1512 #define CLASS_MAX_NREGS(CLASS, MODE) \
1513 (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \
1514 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1516 /* Stack layout; function entry, exit and calling. */
1518 /* Define the number of register that can hold parameters.
1519 This macro is only used in other macro definitions below and in sparc.c.
1520 MODE is the mode of the argument.
1521 !v9: All args are passed in %o0-%o5.
1522 v9: %o0-%o5 and %f0-%f31 are cumulatively used to pass values.
1523 See the description in sparc.c. */
1524 #define NPARM_REGS(MODE) \
1526 ? (GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 6) \
1529 /* Define this if pushing a word on the stack
1530 makes the stack pointer a smaller address. */
1531 #define STACK_GROWS_DOWNWARD
1533 /* Define this if the nominal address of the stack frame
1534 is at the high-address end of the local variables;
1535 that is, each additional local variable allocated
1536 goes at a more negative offset in the frame. */
1537 #define FRAME_GROWS_DOWNWARD
1539 /* Offset within stack frame to start allocating local variables at.
1540 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1541 first local allocated. Otherwise, it is the offset to the BEGINNING
1542 of the first local allocated. */
1543 /* This allows space for one TFmode floating point value. */
1544 #define STARTING_FRAME_OFFSET \
1545 (TARGET_ARCH64 ? -16 \
1546 : (-SPARC_STACK_ALIGN (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)))
1548 /* If we generate an insn to push BYTES bytes,
1549 this says how many the stack pointer really advances by.
1550 On SPARC, don't define this because there are no push insns. */
1551 /* #define PUSH_ROUNDING(BYTES) */
1553 /* Offset of first parameter from the argument pointer register value.
1554 !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg
1555 even if this function isn't going to use it.
1556 v9: This is 128 for the ins and locals. */
1557 #define FIRST_PARM_OFFSET(FNDECL) \
1558 (TARGET_ARCH64 ? 16 * UNITS_PER_WORD : STRUCT_VALUE_OFFSET + UNITS_PER_WORD)
1560 /* Offset from the argument pointer register value to the CFA.
1561 This is different from FIRST_PARM_OFFSET because the register window
1562 comes between the CFA and the arguments. */
1563 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1565 /* When a parameter is passed in a register, stack space is still
1567 !v9: All 6 possible integer registers have backing store allocated.
1568 v9: Only space for the arguments passed is allocated. */
1569 /* ??? Ideally, we'd use zero here (as the minimum), but zero has special
1570 meaning to the backend. Further, we need to be able to detect if a
1571 varargs/unprototyped function is called, as they may want to spill more
1572 registers than we've provided space. Ugly, ugly. So for now we retain
1573 all 6 slots even for v9. */
1574 #define REG_PARM_STACK_SPACE(DECL) (6 * UNITS_PER_WORD)
1576 /* Definitions for register elimination. */
1577 /* ??? In TARGET_FLAT mode we needn't have a hard frame pointer. */
1579 #define ELIMINABLE_REGS \
1580 {{ FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
1582 #define CAN_ELIMINATE(FROM, TO) 1
1584 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1585 ((OFFSET) = SPARC_STACK_BIAS)
1587 /* Keep the stack pointer constant throughout the function.
1588 This is both an optimization and a necessity: longjmp
1589 doesn't behave itself when the stack pointer moves within
1591 #define ACCUMULATE_OUTGOING_ARGS 1
1593 /* Value is the number of bytes of arguments automatically
1594 popped when returning from a subroutine call.
1595 FUNDECL is the declaration node of the function (as a tree),
1596 FUNTYPE is the data type of the function (as a tree),
1597 or for a library call it is an identifier node for the subroutine name.
1598 SIZE is the number of bytes of arguments passed on the stack. */
1600 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1602 /* Some subroutine macros specific to this machine.
1603 When !TARGET_FPU, put float return values in the general registers,
1604 since we don't have any fp registers. */
1605 #define BASE_RETURN_VALUE_REG(MODE) \
1607 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 : 8) \
1608 : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 : 8))
1610 #define BASE_OUTGOING_VALUE_REG(MODE) \
1612 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 \
1613 : TARGET_FLAT ? 8 : 24) \
1614 : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 \
1615 : (TARGET_FLAT ? 8 : 24)))
1617 #define BASE_PASSING_ARG_REG(MODE) \
1619 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 : 8) \
1622 /* ??? FIXME -- seems wrong for v9 structure passing... */
1623 #define BASE_INCOMING_ARG_REG(MODE) \
1625 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 \
1626 : TARGET_FLAT ? 8 : 24) \
1627 : (TARGET_FLAT ? 8 : 24))
1629 /* Define this macro if the target machine has "register windows". This
1630 C expression returns the register number as seen by the called function
1631 corresponding to register number OUT as seen by the calling function.
1632 Return OUT if register number OUT is not an outbound register. */
1634 #define INCOMING_REGNO(OUT) \
1635 ((TARGET_FLAT || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16)
1637 /* Define this macro if the target machine has "register windows". This
1638 C expression returns the register number as seen by the calling function
1639 corresponding to register number IN as seen by the called function.
1640 Return IN if register number IN is not an inbound register. */
1642 #define OUTGOING_REGNO(IN) \
1643 ((TARGET_FLAT || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16)
1645 /* Define this macro if the target machine has register windows. This
1646 C expression returns true if the register is call-saved but is in the
1649 #define LOCAL_REGNO(REGNO) \
1650 (TARGET_FLAT ? 0 : (REGNO) >= 16 && (REGNO) <= 31)
1652 /* Define how to find the value returned by a function.
1653 VALTYPE is the data type of the value (as a tree).
1654 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1655 otherwise, FUNC is 0. */
1657 /* On SPARC the value is found in the first "output" register. */
1659 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1660 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 1)
1662 /* But the called function leaves it in the first "input" register. */
1664 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
1665 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 0)
1667 /* Define how to find the value returned by a library function
1668 assuming the value has mode MODE. */
1670 #define LIBCALL_VALUE(MODE) \
1671 function_value (NULL_TREE, (MODE), 1)
1673 /* 1 if N is a possible register number for a function value
1674 as seen by the caller.
1675 On SPARC, the first "output" reg is used for integer values,
1676 and the first floating point register is used for floating point values. */
1678 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32)
1680 /* Define the size of space to allocate for the return value of an
1683 #define APPLY_RESULT_SIZE 16
1685 /* 1 if N is a possible register number for function argument passing.
1686 On SPARC, these are the "output" registers. v9 also uses %f0-%f31. */
1688 #define FUNCTION_ARG_REGNO_P(N) \
1690 ? (((N) >= 8 && (N) <= 13) || ((N) >= 32 && (N) <= 63)) \
1691 : ((N) >= 8 && (N) <= 13))
1693 /* Define a data type for recording info about an argument list
1694 during the scan of that argument list. This data type should
1695 hold all necessary information about the function itself
1696 and about the args processed so far, enough to enable macros
1697 such as FUNCTION_ARG to determine where the next arg should go.
1699 On SPARC (!v9), this is a single integer, which is a number of words
1700 of arguments scanned so far (including the invisible argument,
1701 if any, which holds the structure-value-address).
1702 Thus 7 or more means all following args should go on the stack.
1704 For v9, we also need to know whether a prototype is present. */
1707 int words; /* number of words passed so far */
1708 int prototype_p; /* non-zero if a prototype is present */
1709 int libcall_p; /* non-zero if a library call */
1711 #define CUMULATIVE_ARGS struct sparc_args
1713 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1714 for a call to a function whose data type is FNTYPE.
1715 For a library call, FNTYPE is 0. */
1717 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1718 init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (INDIRECT));
1720 /* Update the data in CUM to advance over an argument
1721 of mode MODE and data type TYPE.
1722 TYPE is null for libcalls where that information may not be available. */
1724 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1725 function_arg_advance (& (CUM), (MODE), (TYPE), (NAMED))
1727 /* Nonzero if we do not know how to pass TYPE solely in registers. */
1729 #define MUST_PASS_IN_STACK(MODE,TYPE) \
1731 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1732 || TREE_ADDRESSABLE (TYPE)))
1734 /* Determine where to put an argument to a function.
1735 Value is zero to push the argument on the stack,
1736 or a hard register in which to store the argument.
1738 MODE is the argument's machine mode.
1739 TYPE is the data type of the argument (as a tree).
1740 This is null for libcalls where that information may
1742 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1743 the preceding args and about the function being called.
1744 NAMED is nonzero if this argument is a named parameter
1745 (otherwise it is an extra parameter matching an ellipsis). */
1747 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1748 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 0)
1750 /* Define where a function finds its arguments.
1751 This is different from FUNCTION_ARG because of register windows. */
1753 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
1754 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 1)
1756 /* For an arg passed partly in registers and partly in memory,
1757 this is the number of registers used.
1758 For args passed entirely in registers or entirely in memory, zero. */
1760 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1761 function_arg_partial_nregs (& (CUM), (MODE), (TYPE), (NAMED))
1763 /* A C expression that indicates when an argument must be passed by reference.
1764 If nonzero for an argument, a copy of that argument is made in memory and a
1765 pointer to the argument is passed instead of the argument itself.
1766 The pointer is passed in whatever way is appropriate for passing a pointer
1769 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1770 function_arg_pass_by_reference (& (CUM), (MODE), (TYPE), (NAMED))
1772 /* If defined, a C expression which determines whether, and in which direction,
1773 to pad out an argument with extra space. The value should be of type
1774 `enum direction': either `upward' to pad above the argument,
1775 `downward' to pad below, or `none' to inhibit padding. */
1777 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1778 function_arg_padding ((MODE), (TYPE))
1780 /* If defined, a C expression that gives the alignment boundary, in bits,
1781 of an argument with the specified mode and type. If it is not defined,
1782 PARM_BOUNDARY is used for all arguments.
1783 For sparc64, objects requiring 16 byte alignment are passed that way. */
1785 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1787 && (GET_MODE_ALIGNMENT (MODE) == 128 \
1788 || ((TYPE) && TYPE_ALIGN (TYPE) == 128))) \
1789 ? 128 : PARM_BOUNDARY)
1791 /* Define the information needed to generate branch and scc insns. This is
1792 stored from the compare operation. Note that we can't use "rtx" here
1793 since it hasn't been defined! */
1795 extern struct rtx_def *sparc_compare_op0, *sparc_compare_op1;
1798 /* Generate the special assembly code needed to tell the assembler whatever
1799 it might need to know about the return value of a function.
1801 For Sparc assemblers, we need to output a .proc pseudo-op which conveys
1802 information to the assembler relating to peephole optimization (done in
1805 #define ASM_DECLARE_RESULT(FILE, RESULT) \
1806 fprintf ((FILE), "\t.proc\t0%lo\n", sparc_type_code (TREE_TYPE (RESULT)))
1808 /* Output the special assembly code needed to tell the assembler some
1809 register is used as global register variable.
1811 SPARC 64bit psABI declares registers %g2 and %g3 as application
1812 registers and %g6 and %g7 as OS registers. Any object using them
1813 should declare (for %g2/%g3 has to, for %g6/%g7 can) that it uses them
1814 and how they are used (scratch or some global variable).
1815 Linker will then refuse to link together objects which use those
1816 registers incompatibly.
1818 Unless the registers are used for scratch, two different global
1819 registers cannot be declared to the same name, so in the unlikely
1820 case of a global register variable occupying more than one register
1821 we prefix the second and following registers with .gnu.part1. etc. */
1823 extern char sparc_hard_reg_printed[8];
1825 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
1826 #define ASM_DECLARE_REGISTER_GLOBAL(FILE, DECL, REGNO, NAME) \
1828 if (TARGET_ARCH64) \
1830 int end = HARD_REGNO_NREGS ((REGNO), DECL_MODE (decl)) + (REGNO); \
1832 for (reg = (REGNO); reg < 8 && reg < end; reg++) \
1833 if ((reg & ~1) == 2 || (reg & ~1) == 6) \
1835 if (reg == (REGNO)) \
1836 fprintf ((FILE), "\t.register\t%%g%d, %s\n", reg, (NAME)); \
1838 fprintf ((FILE), "\t.register\t%%g%d, .gnu.part%d.%s\n", \
1839 reg, reg - (REGNO), (NAME)); \
1840 sparc_hard_reg_printed[reg] = 1; \
1847 /* Output assembler code to FILE to increment profiler label # LABELNO
1848 for profiling a function entry. */
1850 #define FUNCTION_PROFILER(FILE, LABELNO) \
1851 sparc_function_profiler(FILE, LABELNO)
1853 /* Set the name of the mcount function for the system. */
1855 #define MCOUNT_FUNCTION "*mcount"
1857 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1858 the stack pointer does not matter. The value is tested only in
1859 functions that have frame pointers.
1860 No definition is equivalent to always zero. */
1862 #define EXIT_IGNORE_STACK \
1863 (get_frame_size () != 0 \
1864 || current_function_calls_alloca || current_function_outgoing_args_size)
1866 #define DELAY_SLOTS_FOR_EPILOGUE \
1867 (TARGET_FLAT ? sparc_flat_epilogue_delay_slots () : 1)
1868 #define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \
1869 (TARGET_FLAT ? sparc_flat_eligible_for_epilogue_delay (trial, slots_filled) \
1870 : eligible_for_epilogue_delay (trial, slots_filled))
1872 /* Define registers used by the epilogue and return instruction. */
1873 #define EPILOGUE_USES(REGNO) \
1874 (!TARGET_FLAT && REGNO == 31)
1876 /* Length in units of the trampoline for entering a nested function. */
1878 #define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 32 : 16)
1880 #define TRAMPOLINE_ALIGNMENT 128 /* 16 bytes */
1882 /* Emit RTL insns to initialize the variable parts of a trampoline.
1883 FNADDR is an RTX for the address of the function's pure code.
1884 CXT is an RTX for the static chain value for the function. */
1886 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1887 if (TARGET_ARCH64) \
1888 sparc64_initialize_trampoline (TRAMP, FNADDR, CXT); \
1890 sparc_initialize_trampoline (TRAMP, FNADDR, CXT)
1892 /* Generate necessary RTL for __builtin_saveregs(). */
1894 #define EXPAND_BUILTIN_SAVEREGS() sparc_builtin_saveregs ()
1896 /* Implement `va_start' for varargs and stdarg. */
1897 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
1898 sparc_va_start (stdarg, valist, nextarg)
1900 /* Implement `va_arg'. */
1901 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1902 sparc_va_arg (valist, type)
1904 /* Define this macro if the location where a function argument is passed
1905 depends on whether or not it is a named argument.
1907 This macro controls how the NAMED argument to FUNCTION_ARG
1908 is set for varargs and stdarg functions. With this macro defined,
1909 the NAMED argument is always true for named arguments, and false for
1910 unnamed arguments. If this is not defined, but SETUP_INCOMING_VARARGS
1911 is defined, then all arguments are treated as named. Otherwise, all named
1912 arguments except the last are treated as named.
1913 For the v9 we want NAMED to mean what it says it means. */
1915 #define STRICT_ARGUMENT_NAMING TARGET_V9
1917 /* We do not allow sibling calls if -mflat, nor
1918 we do not allow indirect calls to be optimized into sibling calls. */
1919 #define FUNCTION_OK_FOR_SIBCALL(DECL) (DECL && ! TARGET_FLAT)
1921 /* Generate RTL to flush the register windows so as to make arbitrary frames
1923 #define SETUP_FRAME_ADDRESSES() \
1924 emit_insn (gen_flush_register_windows ())
1926 /* Given an rtx for the address of a frame,
1927 return an rtx for the address of the word in the frame
1928 that holds the dynamic chain--the previous frame's address.
1929 ??? -mflat support? */
1930 #define DYNAMIC_CHAIN_ADDRESS(frame) plus_constant (frame, 14 * UNITS_PER_WORD)
1932 /* The return address isn't on the stack, it is in a register, so we can't
1933 access it from the current frame pointer. We can access it from the
1934 previous frame pointer though by reading a value from the register window
1936 #define RETURN_ADDR_IN_PREVIOUS_FRAME
1938 /* This is the offset of the return address to the true next instruction to be
1939 executed for the current function. */
1940 #define RETURN_ADDR_OFFSET \
1941 (8 + 4 * (! TARGET_ARCH64 && current_function_returns_struct))
1943 /* The current return address is in %i7. The return address of anything
1944 farther back is in the register window save area at [%fp+60]. */
1945 /* ??? This ignores the fact that the actual return address is +8 for normal
1946 returns, and +12 for structure returns. */
1947 #define RETURN_ADDR_RTX(count, frame) \
1949 ? gen_rtx_REG (Pmode, 31) \
1950 : gen_rtx_MEM (Pmode, \
1951 memory_address (Pmode, plus_constant (frame, \
1952 15 * UNITS_PER_WORD \
1953 + SPARC_STACK_BIAS))))
1955 /* Before the prologue, the return address is %o7 + 8. OK, sometimes it's
1956 +12, but always using +8 is close enough for frame unwind purposes.
1957 Actually, just using %o7 is close enough for unwinding, but %o7+8
1958 is something you can return to. */
1959 #define INCOMING_RETURN_ADDR_RTX \
1960 plus_constant (gen_rtx_REG (word_mode, 15), 8)
1961 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (15)
1963 /* The offset from the incoming value of %sp to the top of the stack frame
1964 for the current function. On sparc64, we have to account for the stack
1966 #define INCOMING_FRAME_SP_OFFSET SPARC_STACK_BIAS
1968 /* Describe how we implement __builtin_eh_return. */
1969 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 24 : INVALID_REGNUM)
1970 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 1) /* %g1 */
1971 #define EH_RETURN_HANDLER_RTX gen_rtx_REG (Pmode, 31) /* %i7 */
1973 /* Select a format to encode pointers in exception handling data. CODE
1974 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
1975 true if the symbol may be affected by dynamic relocations.
1977 If assembler and linker properly support .uaword %r_disp32(foo),
1978 then use PC relative 32-bit relocations instead of absolute relocs
1979 for shared libraries. On sparc64, use pc relative 32-bit relocs even
1980 for binaries, to save memory. */
1981 #ifdef HAVE_AS_SPARC_UA_PCREL
1982 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
1984 ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\
1985 : ((TARGET_ARCH64 && ! GLOBAL) \
1986 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \
1989 /* Emit a PC-relative relocation. */
1990 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \
1992 fputs (integer_asm_op (SIZE, FALSE), FILE); \
1993 fprintf (FILE, "%%r_disp%d(", SIZE * 8); \
1994 assemble_name (FILE, LABEL); \
1995 fputc (')', FILE); \
1999 /* Addressing modes, and classification of registers for them. */
2001 /* #define HAVE_POST_INCREMENT 0 */
2002 /* #define HAVE_POST_DECREMENT 0 */
2004 /* #define HAVE_PRE_DECREMENT 0 */
2005 /* #define HAVE_PRE_INCREMENT 0 */
2007 /* Macros to check register numbers against specific register classes. */
2009 /* These assume that REGNO is a hard or pseudo reg number.
2010 They give nonzero only if REGNO is a hard reg of the suitable class
2011 or a pseudo reg currently allocated to a suitable hard reg.
2012 Since they use reg_renumber, they are safe only once reg_renumber
2013 has been allocated, which happens in local-alloc.c. */
2015 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2016 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < (unsigned)32 \
2017 || (REGNO) == FRAME_POINTER_REGNUM \
2018 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)
2020 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO)
2022 #define REGNO_OK_FOR_FP_P(REGNO) \
2023 (((unsigned) (REGNO) - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)) \
2024 || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)))
2025 #define REGNO_OK_FOR_CCFP_P(REGNO) \
2027 && (((unsigned) (REGNO) - 96 < (unsigned)4) \
2028 || ((unsigned) reg_renumber[REGNO] - 96 < (unsigned)4)))
2030 /* Now macros that check whether X is a register and also,
2031 strictly, whether it is in a specified class.
2033 These macros are specific to the SPARC, and may be used only
2034 in code for printing assembler insns and in conditions for
2035 define_optimization. */
2037 /* 1 if X is an fp register. */
2039 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
2041 /* Is X, a REG, an in or global register? i.e. is regno 0..7 or 24..31 */
2042 #define IN_OR_GLOBAL_P(X) (REGNO (X) < 8 || (REGNO (X) >= 24 && REGNO (X) <= 31))
2044 /* Maximum number of registers that can appear in a valid memory address. */
2046 #define MAX_REGS_PER_ADDRESS 2
2048 /* Recognize any constant value that is a valid address.
2049 When PIC, we do not accept an address that would require a scratch reg
2050 to load into a register. */
2052 #define CONSTANT_ADDRESS_P(X) \
2053 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2054 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
2055 || (GET_CODE (X) == CONST \
2056 && ! (flag_pic && pic_address_needs_scratch (X))))
2058 /* Define this, so that when PIC, reload won't try to reload invalid
2059 addresses which require two reload registers. */
2061 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
2063 /* Nonzero if the constant value X is a legitimate general operand.
2064 Anything can be made to work except floating point constants.
2065 If TARGET_VIS, 0.0 can be made to work as well. */
2067 #define LEGITIMATE_CONSTANT_P(X) \
2068 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode || \
2070 (GET_MODE (X) == SFmode || GET_MODE (X) == DFmode || \
2071 GET_MODE (X) == TFmode) && \
2072 fp_zero_operand (X, GET_MODE (X))))
2074 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2075 and check its validity for a certain class.
2076 We have two alternate definitions for each of them.
2077 The usual definition accepts all pseudo regs; the other rejects
2078 them unless they have been allocated suitable hard regs.
2079 The symbol REG_OK_STRICT causes the latter definition to be used.
2081 Most source files want to accept pseudo regs in the hope that
2082 they will get allocated to the class that the insn wants them to be in.
2083 Source files for reload pass need to be strict.
2084 After reload, it makes no difference, since pseudo regs have
2085 been eliminated by then. */
2087 /* Optional extra constraints for this machine.
2089 'Q' handles floating point constants which can be moved into
2090 an integer register with a single sethi instruction.
2092 'R' handles floating point constants which can be moved into
2093 an integer register with a single mov instruction.
2095 'S' handles floating point constants which can be moved into
2096 an integer register using a high/lo_sum sequence.
2098 'T' handles memory addresses where the alignment is known to
2099 be at least 8 bytes.
2101 `U' handles all pseudo registers or a hard even numbered
2102 integer register, needed for ldd/std instructions. */
2104 #define EXTRA_CONSTRAINT_BASE(OP, C) \
2105 ((C) == 'Q' ? fp_sethi_p(OP) \
2106 : (C) == 'R' ? fp_mov_p(OP) \
2107 : (C) == 'S' ? fp_high_losum_p(OP) \
2110 #ifndef REG_OK_STRICT
2112 /* Nonzero if X is a hard reg that can be used as an index
2113 or if it is a pseudo reg. */
2114 #define REG_OK_FOR_INDEX_P(X) \
2116 || REGNO (X) == FRAME_POINTER_REGNUM \
2117 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2119 /* Nonzero if X is a hard reg that can be used as a base reg
2120 or if it is a pseudo reg. */
2121 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_INDEX_P (X)
2123 /* 'T', 'U' are for aligned memory loads which aren't needed for arch64. */
2125 #define EXTRA_CONSTRAINT(OP, C) \
2126 (EXTRA_CONSTRAINT_BASE(OP, C) \
2127 || ((! TARGET_ARCH64 && (C) == 'T') \
2128 ? (mem_min_alignment (OP, 8)) \
2129 : ((! TARGET_ARCH64 && (C) == 'U') \
2130 ? (register_ok_for_ldd (OP)) \
2135 /* Nonzero if X is a hard reg that can be used as an index. */
2136 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
2137 /* Nonzero if X is a hard reg that can be used as a base reg. */
2138 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
2140 #define EXTRA_CONSTRAINT(OP, C) \
2141 (EXTRA_CONSTRAINT_BASE(OP, C) \
2142 || ((! TARGET_ARCH64 && (C) == 'T') \
2143 ? mem_min_alignment (OP, 8) && strict_memory_address_p (Pmode, XEXP (OP, 0)) \
2144 : ((! TARGET_ARCH64 && (C) == 'U') \
2145 ? (GET_CODE (OP) == REG \
2146 && (REGNO (OP) < FIRST_PSEUDO_REGISTER \
2147 || reg_renumber[REGNO (OP)] >= 0) \
2148 && register_ok_for_ldd (OP)) \
2153 /* Should gcc use [%reg+%lo(xx)+offset] addresses? */
2155 #ifdef HAVE_AS_OFFSETABLE_LO10
2156 #define USE_AS_OFFSETABLE_LO10 1
2158 #define USE_AS_OFFSETABLE_LO10 0
2161 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2162 that is a valid memory address for an instruction.
2163 The MODE argument is the machine mode for the MEM expression
2164 that wants to use this address.
2166 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
2167 ordinarily. This changes a bit when generating PIC.
2169 If you change this, execute "rm explow.o recog.o reload.o". */
2171 #define RTX_OK_FOR_BASE_P(X) \
2172 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2173 || (GET_CODE (X) == SUBREG \
2174 && GET_CODE (SUBREG_REG (X)) == REG \
2175 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2177 #define RTX_OK_FOR_INDEX_P(X) \
2178 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2179 || (GET_CODE (X) == SUBREG \
2180 && GET_CODE (SUBREG_REG (X)) == REG \
2181 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
2183 #define RTX_OK_FOR_OFFSET_P(X) \
2184 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000 - 8)
2186 #define RTX_OK_FOR_OLO10_P(X) \
2187 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0xc00 - 8)
2189 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2190 { if (RTX_OK_FOR_BASE_P (X)) \
2192 else if (GET_CODE (X) == PLUS) \
2194 register rtx op0 = XEXP (X, 0); \
2195 register rtx op1 = XEXP (X, 1); \
2196 if (flag_pic && op0 == pic_offset_table_rtx) \
2198 if (RTX_OK_FOR_BASE_P (op1)) \
2200 else if (flag_pic == 1 \
2201 && GET_CODE (op1) != REG \
2202 && GET_CODE (op1) != LO_SUM \
2203 && GET_CODE (op1) != MEM \
2204 && (GET_CODE (op1) != CONST_INT \
2205 || SMALL_INT (op1))) \
2208 else if (RTX_OK_FOR_BASE_P (op0)) \
2210 if ((RTX_OK_FOR_INDEX_P (op1) \
2211 /* We prohibit REG + REG for TFmode when \
2212 there are no instructions which accept \
2213 REG+REG instructions. We do this \
2214 because REG+REG is not an offsetable \
2215 address. If we get the situation \
2216 in reload where source and destination \
2217 of a movtf pattern are both MEMs with \
2218 REG+REG address, then only one of them \
2219 gets converted to an offsetable \
2221 && (MODE != TFmode \
2222 || (TARGET_FPU && TARGET_ARCH64 \
2224 && TARGET_HARD_QUAD)) \
2225 /* We prohibit REG + REG on ARCH32 if \
2226 not optimizing for DFmode/DImode \
2227 because then mem_min_alignment is \
2228 likely to be zero after reload and the \
2229 forced split would lack a matching \
2230 splitter pattern. */ \
2231 && (TARGET_ARCH64 || optimize \
2232 || (MODE != DFmode \
2233 && MODE != DImode))) \
2234 || RTX_OK_FOR_OFFSET_P (op1)) \
2237 else if (RTX_OK_FOR_BASE_P (op1)) \
2239 if ((RTX_OK_FOR_INDEX_P (op0) \
2240 /* See the previous comment. */ \
2241 && (MODE != TFmode \
2242 || (TARGET_FPU && TARGET_ARCH64 \
2244 && TARGET_HARD_QUAD)) \
2245 && (TARGET_ARCH64 || optimize \
2246 || (MODE != DFmode \
2247 && MODE != DImode))) \
2248 || RTX_OK_FOR_OFFSET_P (op0)) \
2251 else if (USE_AS_OFFSETABLE_LO10 \
2252 && GET_CODE (op0) == LO_SUM \
2254 && ! TARGET_CM_MEDMID \
2255 && RTX_OK_FOR_OLO10_P (op1)) \
2257 register rtx op00 = XEXP (op0, 0); \
2258 register rtx op01 = XEXP (op0, 1); \
2259 if (RTX_OK_FOR_BASE_P (op00) \
2260 && CONSTANT_P (op01)) \
2263 else if (USE_AS_OFFSETABLE_LO10 \
2264 && GET_CODE (op1) == LO_SUM \
2266 && ! TARGET_CM_MEDMID \
2267 && RTX_OK_FOR_OLO10_P (op0)) \
2269 register rtx op10 = XEXP (op1, 0); \
2270 register rtx op11 = XEXP (op1, 1); \
2271 if (RTX_OK_FOR_BASE_P (op10) \
2272 && CONSTANT_P (op11)) \
2276 else if (GET_CODE (X) == LO_SUM) \
2278 register rtx op0 = XEXP (X, 0); \
2279 register rtx op1 = XEXP (X, 1); \
2280 if (RTX_OK_FOR_BASE_P (op0) \
2281 && CONSTANT_P (op1) \
2282 /* We can't allow TFmode, because an offset \
2283 greater than or equal to the alignment (8) \
2284 may cause the LO_SUM to overflow if !v9. */\
2285 && (MODE != TFmode || TARGET_V9)) \
2288 else if (GET_CODE (X) == CONST_INT && SMALL_INT (X)) \
2292 /* Try machine-dependent ways of modifying an illegitimate address
2293 to be legitimate. If we find one, return the new, valid address.
2294 This macro is used in only one place: `memory_address' in explow.c.
2296 OLDX is the address as it was before break_out_memory_refs was called.
2297 In some cases it is useful to look at this to decide what needs to be done.
2299 MODE and WIN are passed so that this macro can use
2300 GO_IF_LEGITIMATE_ADDRESS.
2302 It is always safe for this macro to do nothing. It exists to recognize
2303 opportunities to optimize the output. */
2305 /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
2306 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2307 { rtx sparc_x = (X); \
2308 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \
2309 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 1), \
2310 force_operand (XEXP (X, 0), NULL_RTX)); \
2311 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \
2312 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2313 force_operand (XEXP (X, 1), NULL_RTX)); \
2314 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \
2315 (X) = gen_rtx_PLUS (Pmode, force_operand (XEXP (X, 0), NULL_RTX),\
2317 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \
2318 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2319 force_operand (XEXP (X, 1), NULL_RTX)); \
2320 if (sparc_x != (X) && memory_address_p (MODE, X)) \
2322 if (flag_pic) (X) = legitimize_pic_address (X, MODE, 0); \
2323 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
2324 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2325 copy_to_mode_reg (Pmode, XEXP (X, 1))); \
2326 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0))) \
2327 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 1), \
2328 copy_to_mode_reg (Pmode, XEXP (X, 0))); \
2329 else if (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
2330 || GET_CODE (X) == LABEL_REF) \
2331 (X) = copy_to_suggested_reg (X, NULL_RTX, Pmode); \
2332 if (memory_address_p (MODE, X)) \
2335 /* Try a machine-dependent way of reloading an illegitimate address
2336 operand. If we find one, push the reload and jump to WIN. This
2337 macro is used in only one place: `find_reloads_address' in reload.c.
2339 For Sparc 32, we wish to handle addresses by splitting them into
2340 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
2341 This cuts the number of extra insns by one.
2343 Do nothing when generating PIC code and the address is a
2344 symbolic operand or requires a scratch register. */
2346 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2348 /* Decompose SImode constants into hi+lo_sum. We do have to \
2349 rerecognize what we produce, so be careful. */ \
2350 if (CONSTANT_P (X) \
2351 && (MODE != TFmode || TARGET_V9) \
2352 && GET_MODE (X) == SImode \
2353 && GET_CODE (X) != LO_SUM && GET_CODE (X) != HIGH \
2355 && (symbolic_operand (X, Pmode) \
2356 || pic_address_needs_scratch (X)))) \
2358 X = gen_rtx_LO_SUM (GET_MODE (X), \
2359 gen_rtx_HIGH (GET_MODE (X), X), X); \
2360 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
2361 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
2365 /* ??? 64-bit reloads. */ \
2368 /* Go to LABEL if ADDR (a legitimate address expression)
2369 has an effect that depends on the machine mode it is used for.
2370 On the SPARC this is never true. */
2372 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
2374 /* If we are referencing a function make the SYMBOL_REF special.
2375 In the Embedded Medium/Anywhere code model, %g4 points to the data segment
2376 so we must not add it to function addresses. */
2378 #define ENCODE_SECTION_INFO(DECL, FIRST) \
2380 if (TARGET_CM_EMBMEDANY && TREE_CODE (DECL) == FUNCTION_DECL) \
2381 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
2384 /* Specify the machine mode that this machine uses
2385 for the index in the tablejump instruction. */
2386 /* If we ever implement any of the full models (such as CM_FULLANY),
2387 this has to be DImode in that case */
2388 #ifdef HAVE_GAS_SUBSECTION_ORDERING
2389 #define CASE_VECTOR_MODE \
2390 (! TARGET_PTR64 ? SImode : flag_pic ? SImode : TARGET_CM_MEDLOW ? SImode : DImode)
2392 /* If assembler does not have working .subsection -1, we use DImode for pic, as otherwise
2393 we have to sign extend which slows things down. */
2394 #define CASE_VECTOR_MODE \
2395 (! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode)
2398 /* Define as C expression which evaluates to nonzero if the tablejump
2399 instruction expects the table to contain offsets from the address of the
2401 Do not define this if the table should contain absolute addresses. */
2402 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2404 /* Define this as 1 if `char' should by default be signed; else as 0. */
2405 #define DEFAULT_SIGNED_CHAR 1
2407 /* Max number of bytes we can move from memory to memory
2408 in one reasonably fast instruction. */
2411 #if 0 /* Sun 4 has matherr, so this is no good. */
2412 /* This is the value of the error code EDOM for this machine,
2413 used by the sqrt instruction. */
2414 #define TARGET_EDOM 33
2416 /* This is how to refer to the variable errno. */
2417 #define GEN_ERRNO_RTX \
2418 gen_rtx_MEM (SImode, gen_rtx_SYMBOL_REF (Pmode, "errno"))
2421 /* Define if operations between registers always perform the operation
2422 on the full register even if a narrower mode is specified. */
2423 #define WORD_REGISTER_OPERATIONS
2425 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2426 will either zero-extend or sign-extend. The value of this macro should
2427 be the code that says which one of the two operations is implicitly
2428 done, NIL if none. */
2429 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2431 /* Nonzero if access to memory by bytes is slow and undesirable.
2432 For RISC chips, it means that access to memory by bytes is no
2433 better than access by words when possible, so grab a whole word
2434 and maybe make use of that. */
2435 #define SLOW_BYTE_ACCESS 1
2437 /* We assume that the store-condition-codes instructions store 0 for false
2438 and some other value for true. This is the value stored for true. */
2440 #define STORE_FLAG_VALUE 1
2442 /* When a prototype says `char' or `short', really pass an `int'. */
2443 #define PROMOTE_PROTOTYPES (TARGET_ARCH32)
2445 /* Define this to be nonzero if shift instructions ignore all but the low-order
2447 #define SHIFT_COUNT_TRUNCATED 1
2449 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2450 is done just by pretending it is already truncated. */
2451 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2453 /* Specify the machine mode that pointers have.
2454 After generation of rtl, the compiler makes no further distinction
2455 between pointers and any other objects of this machine mode. */
2456 #define Pmode (TARGET_ARCH64 ? DImode : SImode)
2458 /* Generate calls to memcpy, memcmp and memset. */
2459 #define TARGET_MEM_FUNCTIONS
2461 /* Add any extra modes needed to represent the condition code.
2463 On the Sparc, we have a "no-overflow" mode which is used when an add or
2464 subtract insn is used to set the condition code. Different branches are
2465 used in this case for some operations.
2467 We also have two modes to indicate that the relevant condition code is
2468 in the floating-point condition code register. One for comparisons which
2469 will generate an exception if the result is unordered (CCFPEmode) and
2470 one for comparisons which will never trap (CCFPmode).
2472 CCXmode and CCX_NOOVmode are only used by v9. */
2474 #define EXTRA_CC_MODES \
2475 CC(CCXmode, "CCX") \
2476 CC(CC_NOOVmode, "CC_NOOV") \
2477 CC(CCX_NOOVmode, "CCX_NOOV") \
2478 CC(CCFPmode, "CCFP") \
2479 CC(CCFPEmode, "CCFPE")
2481 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2482 return the mode to be used for the comparison. For floating-point,
2483 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2484 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2485 processing is needed. */
2486 #define SELECT_CC_MODE(OP,X,Y) select_cc_mode ((OP), (X), (Y))
2488 /* Return non-zero if MODE implies a floating point inequality can be
2489 reversed. For Sparc this is always true because we have a full
2490 compliment of ordered and unordered comparisons, but until generic
2491 code knows how to reverse it correctly we keep the old definition. */
2492 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode && (MODE) != CCFPmode)
2494 /* A function address in a call instruction for indexing purposes. */
2495 #define FUNCTION_MODE Pmode
2497 /* Define this if addresses of constant functions
2498 shouldn't be put through pseudo regs where they can be cse'd.
2499 Desirable on machines where ordinary constants are expensive
2500 but a CALL with constant address is cheap. */
2501 #define NO_FUNCTION_CSE
2503 /* alloca should avoid clobbering the old register save area. */
2504 #define SETJMP_VIA_SAVE_AREA
2506 /* Define subroutines to call to handle multiply and divide.
2507 Use the subroutines that Sun's library provides.
2508 The `*' prevents an underscore from being prepended by the compiler. */
2510 #define DIVSI3_LIBCALL "*.div"
2511 #define UDIVSI3_LIBCALL "*.udiv"
2512 #define MODSI3_LIBCALL "*.rem"
2513 #define UMODSI3_LIBCALL "*.urem"
2514 /* .umul is a little faster than .mul. */
2515 #define MULSI3_LIBCALL "*.umul"
2517 /* Define library calls for quad FP operations. These are all part of the
2519 #define ADDTF3_LIBCALL "_Q_add"
2520 #define SUBTF3_LIBCALL "_Q_sub"
2521 #define NEGTF2_LIBCALL "_Q_neg"
2522 #define MULTF3_LIBCALL "_Q_mul"
2523 #define DIVTF3_LIBCALL "_Q_div"
2524 #define FLOATSITF2_LIBCALL "_Q_itoq"
2525 #define FIX_TRUNCTFSI2_LIBCALL "_Q_qtoi"
2526 #define FIXUNS_TRUNCTFSI2_LIBCALL "_Q_qtou"
2527 #define EXTENDSFTF2_LIBCALL "_Q_stoq"
2528 #define TRUNCTFSF2_LIBCALL "_Q_qtos"
2529 #define EXTENDDFTF2_LIBCALL "_Q_dtoq"
2530 #define TRUNCTFDF2_LIBCALL "_Q_qtod"
2531 #define EQTF2_LIBCALL "_Q_feq"
2532 #define NETF2_LIBCALL "_Q_fne"
2533 #define GTTF2_LIBCALL "_Q_fgt"
2534 #define GETF2_LIBCALL "_Q_fge"
2535 #define LTTF2_LIBCALL "_Q_flt"
2536 #define LETF2_LIBCALL "_Q_fle"
2538 /* We can define the TFmode sqrt optab only if TARGET_FPU. This is because
2539 with soft-float, the SFmode and DFmode sqrt instructions will be absent,
2540 and the compiler will notice and try to use the TFmode sqrt instruction
2541 for calls to the builtin function sqrt, but this fails. */
2542 #define INIT_TARGET_OPTABS \
2544 if (TARGET_ARCH32) \
2546 add_optab->handlers[(int) TFmode].libfunc \
2547 = init_one_libfunc (ADDTF3_LIBCALL); \
2548 sub_optab->handlers[(int) TFmode].libfunc \
2549 = init_one_libfunc (SUBTF3_LIBCALL); \
2550 neg_optab->handlers[(int) TFmode].libfunc \
2551 = init_one_libfunc (NEGTF2_LIBCALL); \
2552 smul_optab->handlers[(int) TFmode].libfunc \
2553 = init_one_libfunc (MULTF3_LIBCALL); \
2554 sdiv_optab->handlers[(int) TFmode].libfunc \
2555 = init_one_libfunc (DIVTF3_LIBCALL); \
2556 eqtf2_libfunc = init_one_libfunc (EQTF2_LIBCALL); \
2557 netf2_libfunc = init_one_libfunc (NETF2_LIBCALL); \
2558 gttf2_libfunc = init_one_libfunc (GTTF2_LIBCALL); \
2559 getf2_libfunc = init_one_libfunc (GETF2_LIBCALL); \
2560 lttf2_libfunc = init_one_libfunc (LTTF2_LIBCALL); \
2561 letf2_libfunc = init_one_libfunc (LETF2_LIBCALL); \
2562 trunctfsf2_libfunc = init_one_libfunc (TRUNCTFSF2_LIBCALL); \
2563 trunctfdf2_libfunc = init_one_libfunc (TRUNCTFDF2_LIBCALL); \
2564 extendsftf2_libfunc = init_one_libfunc (EXTENDSFTF2_LIBCALL); \
2565 extenddftf2_libfunc = init_one_libfunc (EXTENDDFTF2_LIBCALL); \
2566 floatsitf_libfunc = init_one_libfunc (FLOATSITF2_LIBCALL); \
2567 fixtfsi_libfunc = init_one_libfunc (FIX_TRUNCTFSI2_LIBCALL); \
2568 fixunstfsi_libfunc \
2569 = init_one_libfunc (FIXUNS_TRUNCTFSI2_LIBCALL); \
2571 sqrt_optab->handlers[(int) TFmode].libfunc \
2572 = init_one_libfunc ("_Q_sqrt"); \
2574 INIT_SUBTARGET_OPTABS; \
2577 /* This is meant to be redefined in the host dependent files */
2578 #define INIT_SUBTARGET_OPTABS
2580 /* Nonzero if a floating point comparison library call for
2581 mode MODE that will return a boolean value. Zero if one
2582 of the libgcc2 functions is used. */
2583 #define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) ((MODE) == TFmode)
2585 /* Compute the cost of computing a constant rtl expression RTX
2586 whose rtx-code is CODE. The body of this macro is a portion
2587 of a switch statement. If the code is computed here,
2588 return it with a return statement. Otherwise, break from the switch. */
2590 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
2592 if (INTVAL (RTX) < 0x1000 && INTVAL (RTX) >= -0x1000) \
2600 case CONST_DOUBLE: \
2601 if (GET_MODE (RTX) == DImode) \
2602 if ((XINT (RTX, 3) == 0 \
2603 && (unsigned) XINT (RTX, 2) < 0x1000) \
2604 || (XINT (RTX, 3) == -1 \
2605 && XINT (RTX, 2) < 0 \
2606 && XINT (RTX, 2) >= -0x1000)) \
2610 #define ADDRESS_COST(RTX) 1
2612 /* Compute extra cost of moving data between one register class
2614 #define GENERAL_OR_I64(C) ((C) == GENERAL_REGS || (C) == I64_REGS)
2615 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
2616 (((FP_REG_CLASS_P (CLASS1) && GENERAL_OR_I64 (CLASS2)) \
2617 || (GENERAL_OR_I64 (CLASS1) && FP_REG_CLASS_P (CLASS2)) \
2618 || (CLASS1) == FPCC_REGS || (CLASS2) == FPCC_REGS) \
2619 ? (sparc_cpu == PROCESSOR_ULTRASPARC ? 12 : 6) : 2)
2621 /* Provide the costs of a rtl expression. This is in the body of a
2622 switch on CODE. The purpose for the cost of MULT is to encourage
2623 `synth_mult' to find a synthetic multiply when reasonable.
2625 If we need more than 12 insns to do a multiply, then go out-of-line,
2626 since the call overhead will be < 10% of the cost of the multiply. */
2628 #define RTX_COSTS(X,CODE,OUTER_CODE) \
2630 if (sparc_cpu == PROCESSOR_ULTRASPARC) \
2631 return (GET_MODE (X) == DImode ? \
2632 COSTS_N_INSNS (34) : COSTS_N_INSNS (19)); \
2633 return TARGET_HARD_MUL ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25); \
2638 if (sparc_cpu == PROCESSOR_ULTRASPARC) \
2639 return (GET_MODE (X) == DImode ? \
2640 COSTS_N_INSNS (68) : COSTS_N_INSNS (37)); \
2641 return COSTS_N_INSNS (25); \
2642 /* Make FLOAT and FIX more expensive than CONST_DOUBLE,\
2643 so that cse will favor the latter. */ \
2648 /* Conditional branches with empty delay slots have a length of two. */
2649 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2651 if (GET_CODE (INSN) == CALL_INSN \
2652 || (GET_CODE (INSN) == JUMP_INSN && ! simplejump_p (insn))) \
2656 /* Control the assembler format that we output. */
2658 /* Output at beginning of assembler file. */
2660 #define ASM_FILE_START(file)
2662 /* A C string constant describing how to begin a comment in the target
2663 assembler language. The compiler assumes that the comment will end at
2664 the end of the line. */
2666 #define ASM_COMMENT_START "!"
2668 /* Output to assembler file text saying following lines
2669 may contain character constants, extra white space, comments, etc. */
2671 #define ASM_APP_ON ""
2673 /* Output to assembler file text saying following lines
2674 no longer contain unusual constructs. */
2676 #define ASM_APP_OFF ""
2678 /* ??? Try to make the style consistent here (_OP?). */
2680 #define ASM_FLOAT ".single"
2681 #define ASM_DOUBLE ".double"
2682 #define ASM_LONGDOUBLE ".xxx" /* ??? Not known (or used yet). */
2684 /* How to refer to registers in assembler output.
2685 This sequence is indexed by compiler's hard-register-number (see above). */
2687 #define REGISTER_NAMES \
2688 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \
2689 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \
2690 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \
2691 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \
2692 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \
2693 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \
2694 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \
2695 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \
2696 "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \
2697 "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \
2698 "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \
2699 "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \
2700 "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc", "%sfp" }
2702 /* Define additional names for use in asm clobbers and asm declarations. */
2704 #define ADDITIONAL_REGISTER_NAMES \
2705 {{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}}
2707 /* On Sun 4, this limit is 2048. We use 1000 to be safe, since the length
2708 can run past this up to a continuation point. Once we used 1500, but
2709 a single entry in C++ can run more than 500 bytes, due to the length of
2710 mangled symbol names. dbxout.c should really be fixed to do
2711 continuations when they are actually needed instead of trying to
2713 #define DBX_CONTIN_LENGTH 1000
2715 /* This is how to output the definition of a user-level label named NAME,
2716 such as the label on a static function or variable NAME. */
2718 #define ASM_OUTPUT_LABEL(FILE,NAME) \
2719 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
2721 /* This is how to output a command to make the user-level label named NAME
2722 defined for reference from other files. */
2724 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
2725 do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
2727 /* The prefix to add to user-visible assembler symbols. */
2729 #define USER_LABEL_PREFIX "_"
2731 /* This is how to output a definition of an internal numbered label where
2732 PREFIX is the class of label and NUM is the number within the class. */
2734 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
2735 fprintf (FILE, "%s%d:\n", PREFIX, NUM)
2737 /* This is how to store into the string LABEL
2738 the symbol_ref name of an internal numbered label where
2739 PREFIX is the class of label and NUM is the number within the class.
2740 This is suitable for output with `assemble_name'. */
2742 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2743 sprintf ((LABEL), "*%s%ld", (PREFIX), (long)(NUM))
2745 /* This is how we hook in and defer the case-vector until the end of
2747 #define ASM_OUTPUT_ADDR_VEC(LAB,VEC) \
2748 sparc_defer_case_vector ((LAB),(VEC), 0)
2750 #define ASM_OUTPUT_ADDR_DIFF_VEC(LAB,VEC) \
2751 sparc_defer_case_vector ((LAB),(VEC), 1)
2753 /* This is how to output an element of a case-vector that is absolute. */
2755 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2758 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
2759 if (CASE_VECTOR_MODE == SImode) \
2760 fprintf (FILE, "\t.word\t"); \
2762 fprintf (FILE, "\t.xword\t"); \
2763 assemble_name (FILE, label); \
2764 fputc ('\n', FILE); \
2767 /* This is how to output an element of a case-vector that is relative.
2768 (SPARC uses such vectors only when generating PIC.) */
2770 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2773 ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE)); \
2774 if (CASE_VECTOR_MODE == SImode) \
2775 fprintf (FILE, "\t.word\t"); \
2777 fprintf (FILE, "\t.xword\t"); \
2778 assemble_name (FILE, label); \
2779 ASM_GENERATE_INTERNAL_LABEL (label, "L", (REL)); \
2780 fputc ('-', FILE); \
2781 assemble_name (FILE, label); \
2782 fputc ('\n', FILE); \
2785 /* This is what to output before and after case-vector (both
2786 relative and absolute). If .subsection -1 works, we put case-vectors
2787 at the beginning of the current section. */
2789 #ifdef HAVE_GAS_SUBSECTION_ORDERING
2791 #define ASM_OUTPUT_ADDR_VEC_START(FILE) \
2792 fprintf(FILE, "\t.subsection\t-1\n")
2794 #define ASM_OUTPUT_ADDR_VEC_END(FILE) \
2795 fprintf(FILE, "\t.previous\n")
2799 /* This is how to output an assembler line
2800 that says to advance the location counter
2801 to a multiple of 2**LOG bytes. */
2803 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2805 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
2807 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
2808 fprintf (FILE, "\t.skip %u\n", (SIZE))
2810 /* This says how to output an assembler line
2811 to define a global common symbol. */
2813 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
2814 ( fputs ("\t.common ", (FILE)), \
2815 assemble_name ((FILE), (NAME)), \
2816 fprintf ((FILE), ",%u,\"bss\"\n", (SIZE)))
2818 /* This says how to output an assembler line to define a local common
2821 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \
2822 ( fputs ("\t.reserve ", (FILE)), \
2823 assemble_name ((FILE), (NAME)), \
2824 fprintf ((FILE), ",%u,\"bss\",%u\n", \
2825 (SIZE), ((ALIGNED) / BITS_PER_UNIT)))
2827 /* A C statement (sans semicolon) to output to the stdio stream
2828 FILE the assembler definition of uninitialized global DECL named
2829 NAME whose size is SIZE bytes and alignment is ALIGN bytes.
2830 Try to use asm_output_aligned_bss to implement this macro. */
2832 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2834 fputs (".globl ", (FILE)); \
2835 assemble_name ((FILE), (NAME)); \
2836 fputs ("\n", (FILE)); \
2837 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \
2840 /* Store in OUTPUT a string (made with alloca) containing
2841 an assembler-name for a local static variable named NAME.
2842 LABELNO is an integer which is different for each call. */
2844 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2845 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2846 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2848 #define IDENT_ASM_OP "\t.ident\t"
2850 /* Output #ident as a .ident. */
2852 #define ASM_OUTPUT_IDENT(FILE, NAME) \
2853 fprintf (FILE, "%s\"%s\"\n", IDENT_ASM_OP, NAME);
2855 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
2856 Used for C++ multiple inheritance. */
2857 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
2862 && aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION)))) \
2864 if ((DELTA) >= 4096 || (DELTA) < -4096) \
2865 fprintf (FILE, "\tset\t%d, %%g1\n\tadd\t%%o%d, %%g1, %%o%d\n", \
2866 (int)(DELTA), reg, reg); \
2868 fprintf (FILE, "\tadd\t%%o%d, %d, %%o%d\n", reg, (int)(DELTA), reg);\
2869 fprintf (FILE, "\tor\t%%o7, %%g0, %%g1\n"); \
2870 fprintf (FILE, "\tcall\t"); \
2871 assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
2872 fprintf (FILE, ", 0\n"); \
2873 fprintf (FILE, "\t or\t%%g1, %%g0, %%o7\n"); \
2876 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
2877 ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '(' || (CHAR) == '_')
2879 /* Print operand X (an rtx) in assembler syntax to file FILE.
2880 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2881 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2883 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2885 /* Print a memory address as an operand to reference that memory location. */
2887 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2888 { register rtx base, index = 0; \
2890 register rtx addr = ADDR; \
2891 if (GET_CODE (addr) == REG) \
2892 fputs (reg_names[REGNO (addr)], FILE); \
2893 else if (GET_CODE (addr) == PLUS) \
2895 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
2896 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\
2897 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
2898 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\
2900 base = XEXP (addr, 0), index = XEXP (addr, 1); \
2901 if (GET_CODE (base) == LO_SUM) \
2903 if (! USE_AS_OFFSETABLE_LO10 \
2905 || TARGET_CM_MEDMID) \
2907 output_operand (XEXP (base, 0), 0); \
2908 fputs ("+%lo(", FILE); \
2909 output_address (XEXP (base, 1)); \
2910 fprintf (FILE, ")+%d", offset); \
2914 fputs (reg_names[REGNO (base)], FILE); \
2916 fprintf (FILE, "%+d", offset); \
2917 else if (GET_CODE (index) == REG) \
2918 fprintf (FILE, "+%s", reg_names[REGNO (index)]); \
2919 else if (GET_CODE (index) == SYMBOL_REF \
2920 || GET_CODE (index) == CONST) \
2921 fputc ('+', FILE), output_addr_const (FILE, index); \
2925 else if (GET_CODE (addr) == MINUS \
2926 && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \
2928 output_addr_const (FILE, XEXP (addr, 0)); \
2929 fputs ("-(", FILE); \
2930 output_addr_const (FILE, XEXP (addr, 1)); \
2931 fputs ("-.)", FILE); \
2933 else if (GET_CODE (addr) == LO_SUM) \
2935 output_operand (XEXP (addr, 0), 0); \
2936 if (TARGET_CM_MEDMID) \
2937 fputs ("+%l44(", FILE); \
2939 fputs ("+%lo(", FILE); \
2940 output_address (XEXP (addr, 1)); \
2941 fputc (')', FILE); \
2943 else if (flag_pic && GET_CODE (addr) == CONST \
2944 && GET_CODE (XEXP (addr, 0)) == MINUS \
2945 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \
2946 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \
2947 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \
2949 addr = XEXP (addr, 0); \
2950 output_addr_const (FILE, XEXP (addr, 0)); \
2951 /* Group the args of the second CONST in parenthesis. */ \
2952 fputs ("-(", FILE); \
2953 /* Skip past the second CONST--it does nothing for us. */\
2954 output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \
2955 /* Close the parenthesis. */ \
2956 fputc (')', FILE); \
2960 output_addr_const (FILE, addr); \
2964 /* Define the codes that are matched by predicates in sparc.c. */
2966 #define PREDICATE_CODES \
2967 {"reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2968 {"fp_zero_operand", {CONST_DOUBLE}}, \
2969 {"intreg_operand", {SUBREG, REG}}, \
2970 {"fcc_reg_operand", {REG}}, \
2971 {"icc_or_fcc_reg_operand", {REG}}, \
2972 {"restore_operand", {REG}}, \
2973 {"call_operand", {MEM}}, \
2974 {"call_operand_address", {SYMBOL_REF, LABEL_REF, CONST, CONST_DOUBLE, \
2975 ADDRESSOF, SUBREG, REG, PLUS, LO_SUM, CONST_INT}}, \
2976 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
2977 {"symbolic_memory_operand", {SUBREG, MEM}}, \
2978 {"label_ref_operand", {LABEL_REF}}, \
2979 {"sp64_medium_pic_operand", {CONST}}, \
2980 {"data_segment_operand", {SYMBOL_REF, PLUS, CONST}}, \
2981 {"text_segment_operand", {LABEL_REF, SYMBOL_REF, PLUS, CONST}}, \
2982 {"reg_or_nonsymb_mem_operand", {SUBREG, REG, MEM}}, \
2983 {"splittable_symbolic_memory_operand", {MEM}}, \
2984 {"splittable_immediate_memory_operand", {MEM}}, \
2985 {"eq_or_neq", {EQ, NE}}, \
2986 {"normal_comp_operator", {GE, GT, LE, LT, GTU, LEU}}, \
2987 {"noov_compare_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}}, \
2988 {"v9_regcmp_op", {EQ, NE, GE, LT, LE, GT}}, \
2989 {"extend_op", {SIGN_EXTEND, ZERO_EXTEND}}, \
2990 {"cc_arithop", {AND, IOR, XOR}}, \
2991 {"cc_arithopn", {AND, IOR}}, \
2992 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
2993 {"arith_add_operand", {SUBREG, REG, CONST_INT}}, \
2994 {"arith11_operand", {SUBREG, REG, CONST_INT}}, \
2995 {"arith10_operand", {SUBREG, REG, CONST_INT}}, \
2996 {"arith_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2997 {"arith_double_add_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2998 {"arith11_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2999 {"arith10_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
3000 {"small_int", {CONST_INT}}, \
3001 {"small_int_or_double", {CONST_INT, CONST_DOUBLE}}, \
3002 {"uns_small_int", {CONST_INT}}, \
3003 {"uns_arith_operand", {SUBREG, REG, CONST_INT}}, \
3004 {"clobbered_register", {REG}}, \
3005 {"input_operand", {SUBREG, REG, CONST_INT, MEM, CONST}}, \
3006 {"const64_operand", {CONST_INT, CONST_DOUBLE}}, \
3007 {"const64_high_operand", {CONST_INT, CONST_DOUBLE}},
3009 /* The number of Pmode words for the setjmp buffer. */
3010 #define JMP_BUF_SIZE 12
3012 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (flag_pic)