1 /* Definitions of target machine for GNU compiler, for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1994, 1995, 1996, 1997, 1998, 1999
3 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com).
5 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 /* Note that some other tm.h files include this one and then override
26 whatever definitions are necessary. */
28 /* Define the specific costs for a given cpu */
30 struct processor_costs {
34 /* Integer signed load */
37 /* Integer zeroed load */
43 /* fmov, fneg, fabs */
47 const int float_plusminus;
53 const int float_cmove;
59 const int float_div_sf;
62 const int float_div_df;
65 const int float_sqrt_sf;
68 const int float_sqrt_df;
76 /* integer multiply cost for each bit set past the most
77 significant 3, so the formula for multiply cost becomes:
80 highest_bit = highest_clear_bit(rs1);
82 highest_bit = highest_set_bit(rs1);
85 cost = int_mul{,X} + ((highest_bit - 3) / int_mul_bit_factor);
87 A value of zero indicates that the multiply costs is fixed,
89 const int int_mul_bit_factor;
100 /* penalty for shifts, due to scheduling rules etc. */
101 const int shift_penalty;
104 extern const struct processor_costs *sparc_costs;
106 /* Target CPU builtins. FIXME: Defining sparc is for the benefit of
107 Solaris only; otherwise just define __sparc__. Sadly the headers
108 are such a mess there is no Solaris-specific header. */
109 #define TARGET_CPU_CPP_BUILTINS() \
112 builtin_define_std ("sparc"); \
115 builtin_assert ("cpu=sparc64"); \
116 builtin_assert ("machine=sparc64"); \
120 builtin_assert ("cpu=sparc"); \
121 builtin_assert ("machine=sparc"); \
126 /* Specify this in a cover file to provide bi-architecture (32/64) support. */
127 /* #define SPARC_BI_ARCH */
129 /* Macro used later in this file to determine default architecture. */
130 #define DEFAULT_ARCH32_P ((TARGET_DEFAULT & MASK_64BIT) == 0)
132 /* TARGET_ARCH{32,64} are the main macros to decide which of the two
133 architectures to compile for. We allow targets to choose compile time or
134 runtime selection. */
136 #if defined(__sparcv9) || defined(__arch64__)
137 #define TARGET_ARCH32 0
139 #define TARGET_ARCH32 1
143 #define TARGET_ARCH32 (! TARGET_64BIT)
145 #define TARGET_ARCH32 (DEFAULT_ARCH32_P)
146 #endif /* SPARC_BI_ARCH */
147 #endif /* IN_LIBGCC2 */
148 #define TARGET_ARCH64 (! TARGET_ARCH32)
150 /* Code model selection in 64-bit environment.
152 The machine mode used for addresses is 32-bit wide:
154 TARGET_CM_32: 32-bit address space.
155 It is the code model used when generating 32-bit code.
157 The machine mode used for addresses is 64-bit wide:
159 TARGET_CM_MEDLOW: 32-bit address space.
160 The executable must be in the low 32 bits of memory.
161 This avoids generating %uhi and %ulo terms. Programs
162 can be statically or dynamically linked.
164 TARGET_CM_MEDMID: 44-bit address space.
165 The executable must be in the low 44 bits of memory,
166 and the %[hml]44 terms are used. The text and data
167 segments have a maximum size of 2GB (31-bit span).
168 The maximum offset from any instruction to the label
169 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span).
171 TARGET_CM_MEDANY: 64-bit address space.
172 The text and data segments have a maximum size of 2GB
173 (31-bit span) and may be located anywhere in memory.
174 The maximum offset from any instruction to the label
175 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span).
177 TARGET_CM_EMBMEDANY: 64-bit address space.
178 The text and data segments have a maximum size of 2GB
179 (31-bit span) and may be located anywhere in memory.
180 The global register %g4 contains the start address of
181 the data segment. Programs are statically linked and
182 PIC is not supported.
184 Different code models are not supported in 32-bit environment. */
194 /* Value of -mcmodel specified by user. */
195 extern const char *sparc_cmodel_string;
197 extern enum cmodel sparc_cmodel;
199 /* V9 code model selection. */
200 #define TARGET_CM_MEDLOW (sparc_cmodel == CM_MEDLOW)
201 #define TARGET_CM_MEDMID (sparc_cmodel == CM_MEDMID)
202 #define TARGET_CM_MEDANY (sparc_cmodel == CM_MEDANY)
203 #define TARGET_CM_EMBMEDANY (sparc_cmodel == CM_EMBMEDANY)
205 #define SPARC_DEFAULT_CMODEL CM_32
207 /* The SPARC-V9 architecture defines a relaxed memory ordering model (RMO)
208 which requires the following macro to be true if enabled. Prior to V9,
209 there are no instructions to even talk about memory synchronization.
210 Note that the UltraSPARC III processors don't implement RMO, unlike the
211 UltraSPARC II processors.
213 Default to false; for example, Solaris never enables RMO, only ever uses
214 total memory ordering (TMO). */
215 #define SPARC_RELAXED_ORDERING false
217 /* Do not use the .note.GNU-stack convention by default. */
218 #define NEED_INDICATE_EXEC_STACK 0
220 /* This is call-clobbered in the normal ABI, but is reserved in the
221 home grown (aka upward compatible) embedded ABI. */
222 #define EMBMEDANY_BASE_REG "%g4"
224 /* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile,
225 and specified by the user via --with-cpu=foo.
226 This specifies the cpu implementation, not the architecture size. */
227 /* Note that TARGET_CPU_v9 is assumed to start the list of 64-bit
229 #define TARGET_CPU_sparc 0
230 #define TARGET_CPU_v7 0 /* alias for previous */
231 #define TARGET_CPU_sparclet 1
232 #define TARGET_CPU_sparclite 2
233 #define TARGET_CPU_v8 3 /* generic v8 implementation */
234 #define TARGET_CPU_supersparc 4
235 #define TARGET_CPU_hypersparc 5
236 #define TARGET_CPU_sparc86x 6
237 #define TARGET_CPU_sparclite86x 6
238 #define TARGET_CPU_v9 7 /* generic v9 implementation */
239 #define TARGET_CPU_sparcv9 7 /* alias */
240 #define TARGET_CPU_sparc64 7 /* alias */
241 #define TARGET_CPU_ultrasparc 8
242 #define TARGET_CPU_ultrasparc3 9
244 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
245 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \
246 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3
248 #define CPP_CPU32_DEFAULT_SPEC ""
249 #define ASM_CPU32_DEFAULT_SPEC ""
251 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9
252 /* ??? What does Sun's CC pass? */
253 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
254 /* ??? It's not clear how other assemblers will handle this, so by default
255 use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case
256 is handled in sol2.h. */
257 #define ASM_CPU64_DEFAULT_SPEC "-Av9"
259 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc
260 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
261 #define ASM_CPU64_DEFAULT_SPEC "-Av9a"
263 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3
264 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
265 #define ASM_CPU64_DEFAULT_SPEC "-Av9b"
270 #define CPP_CPU64_DEFAULT_SPEC ""
271 #define ASM_CPU64_DEFAULT_SPEC ""
273 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc \
274 || TARGET_CPU_DEFAULT == TARGET_CPU_v8
275 #define CPP_CPU32_DEFAULT_SPEC ""
276 #define ASM_CPU32_DEFAULT_SPEC ""
279 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet
280 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclet__"
281 #define ASM_CPU32_DEFAULT_SPEC "-Asparclet"
284 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite
285 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite__"
286 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
289 #if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc
290 #define CPP_CPU32_DEFAULT_SPEC "-D__supersparc__ -D__sparc_v8__"
291 #define ASM_CPU32_DEFAULT_SPEC ""
294 #if TARGET_CPU_DEFAULT == TARGET_CPU_hypersparc
295 #define CPP_CPU32_DEFAULT_SPEC "-D__hypersparc__ -D__sparc_v8__"
296 #define ASM_CPU32_DEFAULT_SPEC ""
299 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite86x
300 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite86x__"
301 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
306 #if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC)
307 #error Unrecognized value in TARGET_CPU_DEFAULT.
312 #define CPP_CPU_DEFAULT_SPEC \
313 (DEFAULT_ARCH32_P ? "\
314 %{m64:" CPP_CPU64_DEFAULT_SPEC "} \
315 %{!m64:" CPP_CPU32_DEFAULT_SPEC "} \
317 %{m32:" CPP_CPU32_DEFAULT_SPEC "} \
318 %{!m32:" CPP_CPU64_DEFAULT_SPEC "} \
320 #define ASM_CPU_DEFAULT_SPEC \
321 (DEFAULT_ARCH32_P ? "\
322 %{m64:" ASM_CPU64_DEFAULT_SPEC "} \
323 %{!m64:" ASM_CPU32_DEFAULT_SPEC "} \
325 %{m32:" ASM_CPU32_DEFAULT_SPEC "} \
326 %{!m32:" ASM_CPU64_DEFAULT_SPEC "} \
329 #else /* !SPARC_BI_ARCH */
331 #define CPP_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? CPP_CPU32_DEFAULT_SPEC : CPP_CPU64_DEFAULT_SPEC)
332 #define ASM_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? ASM_CPU32_DEFAULT_SPEC : ASM_CPU64_DEFAULT_SPEC)
334 #endif /* !SPARC_BI_ARCH */
336 /* Define macros to distinguish architectures. */
338 /* Common CPP definitions used by CPP_SPEC amongst the various targets
339 for handling -mcpu=xxx switches. */
340 #define CPP_CPU_SPEC "\
341 %{msoft-float:-D_SOFT_FLOAT} \
343 %{msparclite:-D__sparclite__} \
344 %{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \
345 %{mv8:-D__sparc_v8__} \
346 %{msupersparc:-D__supersparc__ -D__sparc_v8__} \
347 %{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \
348 %{mcpu=sparclite:-D__sparclite__} \
349 %{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \
350 %{mcpu=v8:-D__sparc_v8__} \
351 %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \
352 %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \
353 %{mcpu=sparclite86x:-D__sparclite86x__} \
354 %{mcpu=v9:-D__sparc_v9__} \
355 %{mcpu=ultrasparc:-D__sparc_v9__} \
356 %{mcpu=ultrasparc3:-D__sparc_v9__} \
357 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \
359 #define CPP_ARCH32_SPEC ""
360 #define CPP_ARCH64_SPEC "-D__arch64__"
362 #define CPP_ARCH_DEFAULT_SPEC \
363 (DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC)
365 #define CPP_ARCH_SPEC "\
366 %{m32:%(cpp_arch32)} \
367 %{m64:%(cpp_arch64)} \
368 %{!m32:%{!m64:%(cpp_arch_default)}} \
371 /* Macros to distinguish endianness. */
372 #define CPP_ENDIAN_SPEC "\
373 %{mlittle-endian:-D__LITTLE_ENDIAN__} \
374 %{mlittle-endian-data:-D__LITTLE_ENDIAN_DATA__}"
376 /* Macros to distinguish the particular subtarget. */
377 #define CPP_SUBTARGET_SPEC ""
379 #define CPP_SPEC "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_subtarget)"
381 /* Prevent error on `-sun4' and `-target sun4' options. */
382 /* This used to translate -dalign to -malign, but that is no good
383 because it can't turn off the usual meaning of making debugging dumps. */
384 /* Translate old style -m<cpu> into new style -mcpu=<cpu>.
385 ??? Delete support for -m<cpu> for 2.9. */
388 %{sun4:} %{target:} \
389 %{mcypress:-mcpu=cypress} \
390 %{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \
391 %{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \
394 /* Override in target specific files. */
395 #define ASM_CPU_SPEC "\
396 %{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \
397 %{msparclite:-Asparclite} \
398 %{mf930:-Asparclite} %{mf934:-Asparclite} \
399 %{mcpu=sparclite:-Asparclite} \
400 %{mcpu=sparclite86x:-Asparclite} \
401 %{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \
402 %{mv8plus:-Av8plus} \
404 %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \
405 %{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \
406 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_cpu_default)}}}}}}} \
409 /* Word size selection, among other things.
410 This is what GAS uses. Add %(asm_arch) to ASM_SPEC to enable. */
412 #define ASM_ARCH32_SPEC "-32"
413 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
414 #define ASM_ARCH64_SPEC "-64 -no-undeclared-regs"
416 #define ASM_ARCH64_SPEC "-64"
418 #define ASM_ARCH_DEFAULT_SPEC \
419 (DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC)
421 #define ASM_ARCH_SPEC "\
422 %{m32:%(asm_arch32)} \
423 %{m64:%(asm_arch64)} \
424 %{!m32:%{!m64:%(asm_arch_default)}} \
427 #ifdef HAVE_AS_RELAX_OPTION
428 #define ASM_RELAX_SPEC "%{!mno-relax:-relax}"
430 #define ASM_RELAX_SPEC ""
433 /* Special flags to the Sun-4 assembler when using pipe for input. */
436 %{R} %{!pg:%{!p:%{fpic|fPIC|fpie|fPIE:-k}}} %{keep-local-as-symbols:-L} \
437 %(asm_cpu) %(asm_relax)"
439 #define AS_NEEDS_DASH_FOR_PIPED_INPUT
441 /* This macro defines names of additional specifications to put in the specs
442 that can be used in various specifications like CC1_SPEC. Its definition
443 is an initializer with a subgrouping for each command option.
445 Each subgrouping contains a string constant, that defines the
446 specification name, and a string constant that used by the GCC driver
449 Do not define this macro if it does not need to do anything. */
451 #define EXTRA_SPECS \
452 { "cpp_cpu", CPP_CPU_SPEC }, \
453 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
454 { "cpp_arch32", CPP_ARCH32_SPEC }, \
455 { "cpp_arch64", CPP_ARCH64_SPEC }, \
456 { "cpp_arch_default", CPP_ARCH_DEFAULT_SPEC },\
457 { "cpp_arch", CPP_ARCH_SPEC }, \
458 { "cpp_endian", CPP_ENDIAN_SPEC }, \
459 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \
460 { "asm_cpu", ASM_CPU_SPEC }, \
461 { "asm_cpu_default", ASM_CPU_DEFAULT_SPEC }, \
462 { "asm_arch32", ASM_ARCH32_SPEC }, \
463 { "asm_arch64", ASM_ARCH64_SPEC }, \
464 { "asm_relax", ASM_RELAX_SPEC }, \
465 { "asm_arch_default", ASM_ARCH_DEFAULT_SPEC },\
466 { "asm_arch", ASM_ARCH_SPEC }, \
467 SUBTARGET_EXTRA_SPECS
469 #define SUBTARGET_EXTRA_SPECS
471 /* Because libgcc can generate references back to libc (via .umul etc.) we have
472 to list libc again after the second libgcc. */
473 #define LINK_GCC_C_SEQUENCE_SPEC "%G %L %G %L"
476 #define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int")
477 #define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int")
479 /* ??? This should be 32 bits for v9 but what can we do? */
480 #define WCHAR_TYPE "short unsigned int"
481 #define WCHAR_TYPE_SIZE 16
483 /* Show we can debug even without a frame pointer. */
484 #define CAN_DEBUG_WITHOUT_FP
486 /* Option handling. */
488 #define OVERRIDE_OPTIONS sparc_override_options ()
490 /* Mask of all CPU selection flags. */
492 (MASK_V8 + MASK_SPARCLITE + MASK_SPARCLET + MASK_V9 + MASK_DEPRECATED_V8_INSNS)
494 /* TARGET_HARD_MUL: Use hardware multiply instructions but not %y.
495 TARGET_HARD_MUL32: Use hardware multiply instructions with rd %y
496 to get high 32 bits. False in V8+ or V9 because multiply stores
497 a 64 bit result in a register. */
499 #define TARGET_HARD_MUL32 \
500 ((TARGET_V8 || TARGET_SPARCLITE \
501 || TARGET_SPARCLET || TARGET_DEPRECATED_V8_INSNS) \
502 && ! TARGET_V8PLUS && TARGET_ARCH32)
504 #define TARGET_HARD_MUL \
505 (TARGET_V8 || TARGET_SPARCLITE || TARGET_SPARCLET \
506 || TARGET_DEPRECATED_V8_INSNS || TARGET_V8PLUS)
508 /* MASK_APP_REGS must always be the default because that's what
509 FIXED_REGISTERS is set to and -ffixed- is processed before
510 CONDITIONAL_REGISTER_USAGE is called (where we process -mno-app-regs). */
511 #define TARGET_DEFAULT (MASK_APP_REGS + MASK_FPU)
514 These must match the values for the cpu attribute in sparc.md. */
515 enum processor_type {
519 PROCESSOR_SUPERSPARC,
523 PROCESSOR_HYPERSPARC,
524 PROCESSOR_SPARCLITE86X,
528 PROCESSOR_ULTRASPARC,
529 PROCESSOR_ULTRASPARC3
532 /* This is set from -m{cpu,tune}=xxx. */
533 extern enum processor_type sparc_cpu;
535 /* Recast the cpu class to be the cpu attribute.
536 Every file includes us, but not every file includes insn-attr.h. */
537 #define sparc_cpu_attr ((enum attr_cpu) sparc_cpu)
539 /* Support for a compile-time default CPU, et cetera. The rules are:
540 --with-cpu is ignored if -mcpu is specified.
541 --with-tune is ignored if -mtune is specified.
542 --with-float is ignored if -mhard-float, -msoft-float, -mfpu, or -mno-fpu
544 #define OPTION_DEFAULT_SPECS \
545 {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \
546 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
547 {"float", "%{!msoft-float:%{!mhard-float:%{!fpu:%{!no-fpu:-m%(VALUE)-float}}}}" }
549 /* sparc_select[0] is reserved for the default cpu. */
550 struct sparc_cpu_select
553 const char *const name;
554 const int set_tune_p;
555 const int set_arch_p;
558 extern struct sparc_cpu_select sparc_select[];
560 /* target machine storage layout */
562 /* Define this if most significant bit is lowest numbered
563 in instructions that operate on numbered bit-fields. */
564 #define BITS_BIG_ENDIAN 1
566 /* Define this if most significant byte of a word is the lowest numbered. */
567 #define BYTES_BIG_ENDIAN 1
569 /* Define this if most significant word of a multiword number is the lowest
571 #define WORDS_BIG_ENDIAN 1
573 /* Define this to set the endianness to use in libgcc2.c, which can
574 not depend on target_flags. */
575 #if defined (__LITTLE_ENDIAN__) || defined(__LITTLE_ENDIAN_DATA__)
576 #define LIBGCC2_WORDS_BIG_ENDIAN 0
578 #define LIBGCC2_WORDS_BIG_ENDIAN 1
581 #define MAX_BITS_PER_WORD 64
583 /* Width of a word, in units (bytes). */
584 #define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4)
586 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
588 #define MIN_UNITS_PER_WORD 4
591 #define UNITS_PER_SIMD_WORD (TARGET_VIS ? 8 : UNITS_PER_WORD)
593 /* Now define the sizes of the C data types. */
595 #define SHORT_TYPE_SIZE 16
596 #define INT_TYPE_SIZE 32
597 #define LONG_TYPE_SIZE (TARGET_ARCH64 ? 64 : 32)
598 #define LONG_LONG_TYPE_SIZE 64
599 #define FLOAT_TYPE_SIZE 32
600 #define DOUBLE_TYPE_SIZE 64
601 /* LONG_DOUBLE_TYPE_SIZE is defined per OS even though the
602 SPARC ABI says that it is 128-bit wide. */
603 /* #define LONG_DOUBLE_TYPE_SIZE 128 */
605 /* Width in bits of a pointer.
606 See also the macro `Pmode' defined below. */
607 #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32)
609 /* If we have to extend pointers (only when TARGET_ARCH64 and not
610 TARGET_PTR64), we want to do it unsigned. This macro does nothing
611 if ptr_mode and Pmode are the same. */
612 #define POINTERS_EXTEND_UNSIGNED 1
614 /* For TARGET_ARCH64 we need this, as we don't have instructions
615 for arithmetic operations which do zero/sign extension at the same time,
616 so without this we end up with a srl/sra after every assignment to an
617 user variable, which means very very bad code. */
618 #define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
620 && GET_MODE_CLASS (MODE) == MODE_INT \
621 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
624 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
625 #define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
627 /* Boundary (in *bits*) on which stack pointer should be aligned. */
628 /* FIXME, this is wrong when TARGET_ARCH64 and TARGET_STACK_BIAS, because
629 then sp+2047 is 128-bit aligned so sp is really only byte-aligned. */
630 #define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64)
631 /* Temporary hack until the FIXME above is fixed. This macro is used
632 only in pad_to_arg_alignment in function.c; see the comment there
633 for details about what it does. */
634 #define SPARC_STACK_BOUNDARY_HACK (TARGET_ARCH64 && TARGET_STACK_BIAS)
636 /* ALIGN FRAMES on double word boundaries */
638 #define SPARC_STACK_ALIGN(LOC) \
639 (TARGET_ARCH64 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7))
641 /* Allocation boundary (in *bits*) for the code of a function. */
642 #define FUNCTION_BOUNDARY 32
644 /* Alignment of field after `int : 0' in a structure. */
645 #define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
647 /* Every structure's size must be a multiple of this. */
648 #define STRUCTURE_SIZE_BOUNDARY 8
650 /* A bit-field declared as `int' forces `int' alignment for the struct. */
651 #define PCC_BITFIELD_TYPE_MATTERS 1
653 /* No data type wants to be aligned rounder than this. */
654 #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64)
656 /* The best alignment to use in cases where we have a choice. */
657 #define FASTEST_ALIGNMENT 64
659 /* Define this macro as an expression for the alignment of a structure
660 (given by STRUCT as a tree node) if the alignment computed in the
661 usual way is COMPUTED and the alignment explicitly specified was
664 The default is to use SPECIFIED if it is larger; otherwise, use
665 the smaller of COMPUTED and `BIGGEST_ALIGNMENT' */
666 #define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \
667 (TARGET_FASTER_STRUCTS ? \
668 ((TREE_CODE (STRUCT) == RECORD_TYPE \
669 || TREE_CODE (STRUCT) == UNION_TYPE \
670 || TREE_CODE (STRUCT) == QUAL_UNION_TYPE) \
671 && TYPE_FIELDS (STRUCT) != 0 \
672 ? MAX (MAX ((COMPUTED), (SPECIFIED)), BIGGEST_ALIGNMENT) \
673 : MAX ((COMPUTED), (SPECIFIED))) \
674 : MAX ((COMPUTED), (SPECIFIED)))
676 /* Make strings word-aligned so strcpy from constants will be faster. */
677 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
678 ((TREE_CODE (EXP) == STRING_CST \
679 && (ALIGN) < FASTEST_ALIGNMENT) \
680 ? FASTEST_ALIGNMENT : (ALIGN))
682 /* Make arrays of chars word-aligned for the same reasons. */
683 #define DATA_ALIGNMENT(TYPE, ALIGN) \
684 (TREE_CODE (TYPE) == ARRAY_TYPE \
685 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
686 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
688 /* Set this nonzero if move instructions will actually fail to work
689 when given unaligned data. */
690 #define STRICT_ALIGNMENT 1
692 /* Things that must be doubleword aligned cannot go in the text section,
693 because the linker fails to align the text section enough!
694 Put them in the data section. This macro is only used in this file. */
695 #define MAX_TEXT_ALIGN 32
697 /* Standard register usage. */
699 /* Number of actual hardware registers.
700 The hardware registers are assigned numbers for the compiler
701 from 0 to just below FIRST_PSEUDO_REGISTER.
702 All registers that the compiler knows about must be given numbers,
703 even those that are not normally considered general registers.
705 SPARC has 32 integer registers and 32 floating point registers.
706 64 bit SPARC has 32 additional fp regs, but the odd numbered ones are not
707 accessible. We still account for them to simplify register computations
708 (e.g.: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so
710 Register 100 is used as the integer condition code register.
711 Register 101 is used as the soft frame pointer register. */
713 #define FIRST_PSEUDO_REGISTER 102
715 #define SPARC_FIRST_FP_REG 32
716 /* Additional V9 fp regs. */
717 #define SPARC_FIRST_V9_FP_REG 64
718 #define SPARC_LAST_V9_FP_REG 95
719 /* V9 %fcc[0123]. V8 uses (figuratively) %fcc0. */
720 #define SPARC_FIRST_V9_FCC_REG 96
721 #define SPARC_LAST_V9_FCC_REG 99
723 #define SPARC_FCC_REG 96
724 /* Integer CC reg. We don't distinguish %icc from %xcc. */
725 #define SPARC_ICC_REG 100
727 /* Nonzero if REGNO is an fp reg. */
728 #define SPARC_FP_REG_P(REGNO) \
729 ((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG)
731 /* Argument passing regs. */
732 #define SPARC_OUTGOING_INT_ARG_FIRST 8
733 #define SPARC_INCOMING_INT_ARG_FIRST 24
734 #define SPARC_FP_ARG_FIRST 32
736 /* 1 for registers that have pervasive standard uses
737 and are not available for the register allocator.
740 g1 is free to use as temporary.
741 g2-g4 are reserved for applications. Gcc normally uses them as
742 temporaries, but this can be disabled via the -mno-app-regs option.
743 g5 through g7 are reserved for the operating system.
746 g1,g5 are free to use as temporaries, and are free to use between calls
747 if the call is to an external function via the PLT.
748 g4 is free to use as a temporary in the non-embedded case.
749 g4 is reserved in the embedded case.
750 g2-g3 are reserved for applications. Gcc normally uses them as
751 temporaries, but this can be disabled via the -mno-app-regs option.
752 g6-g7 are reserved for the operating system (or application in
754 ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must
755 currently be a fixed register until this pattern is rewritten.
756 Register 1 is also used when restoring call-preserved registers in large
759 Registers fixed in arch32 and not arch64 (or vice-versa) are marked in
760 CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-.
763 #define FIXED_REGISTERS \
764 {1, 0, 2, 2, 2, 2, 1, 1, \
765 0, 0, 0, 0, 0, 0, 1, 0, \
766 0, 0, 0, 0, 0, 0, 0, 0, \
767 0, 0, 0, 0, 0, 0, 1, 1, \
769 0, 0, 0, 0, 0, 0, 0, 0, \
770 0, 0, 0, 0, 0, 0, 0, 0, \
771 0, 0, 0, 0, 0, 0, 0, 0, \
772 0, 0, 0, 0, 0, 0, 0, 0, \
774 0, 0, 0, 0, 0, 0, 0, 0, \
775 0, 0, 0, 0, 0, 0, 0, 0, \
776 0, 0, 0, 0, 0, 0, 0, 0, \
777 0, 0, 0, 0, 0, 0, 0, 0, \
781 /* 1 for registers not available across function calls.
782 These must include the FIXED_REGISTERS and also any
783 registers that can be used without being saved.
784 The latter must include the registers where values are returned
785 and the register where structure-value addresses are passed.
786 Aside from that, you can include as many other registers as you like. */
788 #define CALL_USED_REGISTERS \
789 {1, 1, 1, 1, 1, 1, 1, 1, \
790 1, 1, 1, 1, 1, 1, 1, 1, \
791 0, 0, 0, 0, 0, 0, 0, 0, \
792 0, 0, 0, 0, 0, 0, 1, 1, \
794 1, 1, 1, 1, 1, 1, 1, 1, \
795 1, 1, 1, 1, 1, 1, 1, 1, \
796 1, 1, 1, 1, 1, 1, 1, 1, \
797 1, 1, 1, 1, 1, 1, 1, 1, \
799 1, 1, 1, 1, 1, 1, 1, 1, \
800 1, 1, 1, 1, 1, 1, 1, 1, \
801 1, 1, 1, 1, 1, 1, 1, 1, \
802 1, 1, 1, 1, 1, 1, 1, 1, \
806 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
807 they won't be allocated. */
809 #define CONDITIONAL_REGISTER_USAGE \
812 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
814 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
815 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
817 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */ \
818 /* then honor it. */ \
819 if (TARGET_ARCH32 && fixed_regs[5]) \
821 else if (TARGET_ARCH64 && fixed_regs[5] == 2) \
826 for (regno = SPARC_FIRST_V9_FP_REG; \
827 regno <= SPARC_LAST_V9_FP_REG; \
829 fixed_regs[regno] = 1; \
830 /* %fcc0 is used by v8 and v9. */ \
831 for (regno = SPARC_FIRST_V9_FCC_REG + 1; \
832 regno <= SPARC_LAST_V9_FCC_REG; \
834 fixed_regs[regno] = 1; \
839 for (regno = 32; regno < SPARC_LAST_V9_FCC_REG; regno++) \
840 fixed_regs[regno] = 1; \
842 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */ \
843 /* then honor it. Likewise with g3 and g4. */ \
844 if (fixed_regs[2] == 2) \
845 fixed_regs[2] = ! TARGET_APP_REGS; \
846 if (fixed_regs[3] == 2) \
847 fixed_regs[3] = ! TARGET_APP_REGS; \
848 if (TARGET_ARCH32 && fixed_regs[4] == 2) \
849 fixed_regs[4] = ! TARGET_APP_REGS; \
850 else if (TARGET_CM_EMBMEDANY) \
852 else if (fixed_regs[4] == 2) \
857 /* Return number of consecutive hard regs needed starting at reg REGNO
858 to hold something of mode MODE.
859 This is ordinarily the length in words of a value of mode MODE
860 but can be less for certain modes in special long registers.
862 On SPARC, ordinary registers hold 32 bits worth;
863 this means both integer and floating point registers.
864 On v9, integer regs hold 64 bits worth; floating point regs hold
865 32 bits worth (this includes the new fp regs as even the odd ones are
866 included in the hard register count). */
868 #define HARD_REGNO_NREGS(REGNO, MODE) \
870 ? ((REGNO) < 32 || (REGNO) == FRAME_POINTER_REGNUM \
871 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \
872 : (GET_MODE_SIZE (MODE) + 3) / 4) \
873 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
875 /* Due to the ARCH64 discrepancy above we must override this next
877 #define REGMODE_NATURAL_SIZE(MODE) \
878 ((TARGET_ARCH64 && FLOAT_MODE_P (MODE)) ? 4 : UNITS_PER_WORD)
880 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
881 See sparc.c for how we initialize this. */
882 extern const int *hard_regno_mode_classes;
883 extern int sparc_mode_class[];
885 /* ??? Because of the funny way we pass parameters we should allow certain
886 ??? types of float/complex values to be in integer registers during
887 ??? RTL generation. This only matters on arch32. */
888 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
889 ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0)
891 /* Value is 1 if it is a good idea to tie two pseudo registers
892 when one has mode MODE1 and one has mode MODE2.
893 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
894 for any hard reg, then this must be 0 for correct output.
896 For V9: SFmode can't be combined with other float modes, because they can't
897 be allocated to the %d registers. Also, DFmode won't fit in odd %f
898 registers, but SFmode will. */
899 #define MODES_TIEABLE_P(MODE1, MODE2) \
900 ((MODE1) == (MODE2) \
901 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
903 || (GET_MODE_CLASS (MODE1) != MODE_FLOAT \
904 || (MODE1 != SFmode && MODE2 != SFmode)))))
906 /* Specify the registers used for certain standard purposes.
907 The values of these macros are register numbers. */
909 /* Register to use for pushing function arguments. */
910 #define STACK_POINTER_REGNUM 14
912 /* The stack bias (amount by which the hardware register is offset by). */
913 #define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0)
915 /* Actual top-of-stack address is 92/176 greater than the contents of the
916 stack pointer register for !v9/v9. That is:
917 - !v9: 64 bytes for the in and local registers, 4 bytes for structure return
918 address, and 6*4 bytes for the 6 register parameters.
919 - v9: 128 bytes for the in and local registers + 6*8 bytes for the integer
921 #define STACK_POINTER_OFFSET (FIRST_PARM_OFFSET(0) + SPARC_STACK_BIAS)
923 /* Base register for access to local variables of the function. */
924 #define HARD_FRAME_POINTER_REGNUM 30
926 /* The soft frame pointer does not have the stack bias applied. */
927 #define FRAME_POINTER_REGNUM 101
929 /* Given the stack bias, the stack pointer isn't actually aligned. */
930 #define INIT_EXPANDERS \
932 if (cfun && cfun->emit->regno_pointer_align && SPARC_STACK_BIAS) \
934 REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = BITS_PER_UNIT; \
935 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT; \
939 /* Value should be nonzero if functions must have frame pointers.
940 Zero means the frame pointer need not be set up (and parms
941 may be accessed via the stack pointer) in functions that seem suitable.
942 Used in flow.c, global.c, ra.c and reload1.c. */
943 #define FRAME_POINTER_REQUIRED \
944 (! (leaf_function_p () && only_leaf_regs_used ()))
946 /* Base register for access to arguments of the function. */
947 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM
949 /* Register in which static-chain is passed to a function. This must
950 not be a register used by the prologue. */
951 #define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2)
953 /* Register which holds offset table for position-independent
956 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 23 : INVALID_REGNUM)
958 /* Pick a default value we can notice from override_options:
960 v9: Default is off. */
962 #define DEFAULT_PCC_STRUCT_RETURN -1
964 /* Functions which return large structures get the address
965 to place the wanted value at offset 64 from the frame.
966 Must reserve 64 bytes for the in and local registers.
967 v9: Functions which return large structures get the address to place the
968 wanted value from an invisible first argument. */
969 #define STRUCT_VALUE_OFFSET 64
971 /* Define the classes of registers for register constraints in the
972 machine description. Also define ranges of constants.
974 One of the classes must always be named ALL_REGS and include all hard regs.
975 If there is more than one class, another class must be named NO_REGS
976 and contain no registers.
978 The name GENERAL_REGS must be the name of a class (or an alias for
979 another name such as ALL_REGS). This is the class of registers
980 that is allowed by "g" or "r" in a register constraint.
981 Also, registers outside this class are allocated only when
982 instructions express preferences for them.
984 The classes must be numbered in nondecreasing order; that is,
985 a larger-numbered class must never be contained completely
986 in a smaller-numbered class.
988 For any two classes, it is very desirable that there be another
989 class that represents their union. */
991 /* The SPARC has various kinds of registers: general, floating point,
992 and condition codes [well, it has others as well, but none that we
993 care directly about].
995 For v9 we must distinguish between the upper and lower floating point
996 registers because the upper ones can't hold SFmode values.
997 HARD_REGNO_MODE_OK won't help here because reload assumes that register(s)
998 satisfying a group need for a class will also satisfy a single need for
999 that class. EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp
1002 It is important that one class contains all the general and all the standard
1003 fp regs. Otherwise find_reg() won't properly allocate int regs for moves,
1004 because reg_class_record() will bias the selection in favor of fp regs,
1005 because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS,
1006 because FP_REGS > GENERAL_REGS.
1008 It is also important that one class contain all the general and all
1009 the fp regs. Otherwise when spilling a DFmode reg, it may be from
1010 EXTRA_FP_REGS but find_reloads() may use class
1011 GENERAL_OR_FP_REGS. This will cause allocate_reload_reg() to die
1012 because the compiler thinks it doesn't have a spill reg when in
1015 v9 also has 4 floating point condition code registers. Since we don't
1016 have a class that is the union of FPCC_REGS with either of the others,
1017 it is important that it appear first. Otherwise the compiler will die
1018 trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its
1021 It is important that SPARC_ICC_REG have class NO_REGS. Otherwise combine
1022 may try to use it to hold an SImode value. See register_operand.
1023 ??? Should %fcc[0123] be handled similarly?
1026 enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS,
1027 EXTRA_FP_REGS, GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS,
1028 ALL_REGS, LIM_REG_CLASSES };
1030 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1032 /* Give names of register classes as strings for dump file. */
1034 #define REG_CLASS_NAMES \
1035 { "NO_REGS", "FPCC_REGS", "I64_REGS", "GENERAL_REGS", "FP_REGS", \
1036 "EXTRA_FP_REGS", "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", \
1039 /* Define which registers fit in which classes.
1040 This is an initializer for a vector of HARD_REG_SET
1041 of length N_REG_CLASSES. */
1043 #define REG_CLASS_CONTENTS \
1044 {{0, 0, 0, 0}, /* NO_REGS */ \
1045 {0, 0, 0, 0xf}, /* FPCC_REGS */ \
1046 {0xffff, 0, 0, 0}, /* I64_REGS */ \
1047 {-1, 0, 0, 0x20}, /* GENERAL_REGS */ \
1048 {0, -1, 0, 0}, /* FP_REGS */ \
1049 {0, -1, -1, 0}, /* EXTRA_FP_REGS */ \
1050 {-1, -1, 0, 0x20}, /* GENERAL_OR_FP_REGS */ \
1051 {-1, -1, -1, 0x20}, /* GENERAL_OR_EXTRA_FP_REGS */ \
1052 {-1, -1, -1, 0x3f}} /* ALL_REGS */
1054 /* Defines invalid mode changes. Borrowed from pa64-regs.h.
1056 SImode loads to floating-point registers are not zero-extended.
1057 The definition for LOAD_EXTEND_OP specifies that integer loads
1058 narrower than BITS_PER_WORD will be zero-extended. As a result,
1059 we inhibit changes from SImode unless they are to a mode that is
1060 identical in size. */
1062 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1064 && (FROM) == SImode \
1065 && GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1066 ? reg_classes_intersect_p (CLASS, FP_REGS) : 0)
1068 /* The same information, inverted:
1069 Return the class number of the smallest class containing
1070 reg number REGNO. This could be a conditional expression
1071 or could index an array. */
1073 extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
1075 #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)]
1077 /* This is the order in which to allocate registers normally.
1079 We put %f0-%f7 last among the float registers, so as to make it more
1080 likely that a pseudo-register which dies in the float return register
1081 area will get allocated to the float return register, thus saving a move
1082 instruction at the end of the function.
1084 Similarly for integer return value registers.
1086 We know in this case that we will not end up with a leaf function.
1088 The register allocator is given the global and out registers first
1089 because these registers are call clobbered and thus less useful to
1090 global register allocation.
1092 Next we list the local and in registers. They are not call clobbered
1093 and thus very useful for global register allocation. We list the input
1094 registers before the locals so that it is more likely the incoming
1095 arguments received in those registers can just stay there and not be
1098 #define REG_ALLOC_ORDER \
1099 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \
1100 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \
1102 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \
1103 29, 28, 27, 26, 25, 24, 31, /* %i5-%i0,%i7 */\
1104 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \
1105 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \
1106 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \
1107 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \
1108 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \
1109 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \
1110 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \
1111 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \
1112 96, 97, 98, 99, /* %fcc0-3 */ \
1113 100, 0, 14, 30, 101} /* %icc, %g0, %o6, %i6, %sfp */
1115 /* This is the order in which to allocate registers for
1116 leaf functions. If all registers can fit in the global and
1117 output registers, then we have the possibility of having a leaf
1120 The macro actually mentioned the input registers first,
1121 because they get renumbered into the output registers once
1122 we know really do have a leaf function.
1124 To be more precise, this register allocation order is used
1125 when %o7 is found to not be clobbered right before register
1126 allocation. Normally, the reason %o7 would be clobbered is
1127 due to a call which could not be transformed into a sibling
1130 As a consequence, it is possible to use the leaf register
1131 allocation order and not end up with a leaf function. We will
1132 not get suboptimal register allocation in that case because by
1133 definition of being potentially leaf, there were no function
1134 calls. Therefore, allocation order within the local register
1135 window is not critical like it is when we do have function calls. */
1137 #define REG_LEAF_ALLOC_ORDER \
1138 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \
1139 29, 28, 27, 26, 25, 24, /* %i5-%i0 */ \
1141 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \
1142 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \
1143 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \
1144 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \
1145 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \
1146 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \
1147 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \
1148 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \
1149 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \
1150 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \
1151 96, 97, 98, 99, /* %fcc0-3 */ \
1152 100, 0, 14, 30, 31, 101} /* %icc, %g0, %o6, %i6, %i7, %sfp */
1154 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
1156 extern char sparc_leaf_regs[];
1157 #define LEAF_REGISTERS sparc_leaf_regs
1159 extern char leaf_reg_remap[];
1160 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO])
1162 /* The class value for index registers, and the one for base regs. */
1163 #define INDEX_REG_CLASS GENERAL_REGS
1164 #define BASE_REG_CLASS GENERAL_REGS
1166 /* Local macro to handle the two v9 classes of FP regs. */
1167 #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS)
1169 /* Get reg_class from a letter such as appears in the machine description.
1170 In the not-v9 case, coerce v9's 'e' class to 'f', so we can use 'e' in the
1171 .md file for v8 and v9.
1172 'd' and 'b' are used for single and double precision VIS operations,
1174 'h' is used for V8+ 64 bit global and out registers. */
1176 #define REG_CLASS_FROM_LETTER(C) \
1178 ? ((C) == 'f' ? FP_REGS \
1179 : (C) == 'e' ? EXTRA_FP_REGS \
1180 : (C) == 'c' ? FPCC_REGS \
1181 : ((C) == 'd' && TARGET_VIS) ? FP_REGS\
1182 : ((C) == 'b' && TARGET_VIS) ? EXTRA_FP_REGS\
1183 : ((C) == 'h' && TARGET_V8PLUS) ? I64_REGS\
1185 : ((C) == 'f' ? FP_REGS \
1186 : (C) == 'e' ? FP_REGS \
1187 : (C) == 'c' ? FPCC_REGS \
1190 /* The letters I, J, K, L, M, N, O, P in a register constraint string
1191 can be used to stand for particular ranges of CONST_INTs.
1192 This macro defines what the ranges are.
1193 C is the letter, and VALUE is a constant value.
1194 Return 1 if VALUE is in the range specified by C.
1196 `I' is used for the range of constants an insn can actually contain.
1197 `J' is used for the range which is just zero (since that is R0).
1198 `K' is used for constants which can be loaded with a single sethi insn.
1199 `L' is used for the range of constants supported by the movcc insns.
1200 `M' is used for the range of constants supported by the movrcc insns.
1201 `N' is like K, but for constants wider than 32 bits.
1202 `O' is used for the range which is just 4096.
1205 /* Predicates for 10-bit, 11-bit and 13-bit signed constants. */
1206 #define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400)
1207 #define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800)
1208 #define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000)
1210 /* 10- and 11-bit immediates are only used for a few specific insns.
1211 SMALL_INT is used throughout the port so we continue to use it. */
1212 #define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X)))
1214 /* Predicate for constants that can be loaded with a sethi instruction.
1215 This is the general, 64-bit aware, bitwise version that ensures that
1216 only constants whose representation fits in the mask
1220 are accepted. It will reject, for example, negative SImode constants
1221 on 64-bit hosts, so correct handling is to mask the value beforehand
1222 according to the mode of the instruction. */
1223 #define SPARC_SETHI_P(X) \
1224 (((unsigned HOST_WIDE_INT) (X) \
1225 & ((unsigned HOST_WIDE_INT) 0x3ff - GET_MODE_MASK (SImode) - 1)) == 0)
1227 /* Version of the above predicate for SImode constants and below. */
1228 #define SPARC_SETHI32_P(X) \
1229 (SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode)))
1231 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1232 ((C) == 'I' ? SPARC_SIMM13_P (VALUE) \
1233 : (C) == 'J' ? (VALUE) == 0 \
1234 : (C) == 'K' ? SPARC_SETHI32_P (VALUE) \
1235 : (C) == 'L' ? SPARC_SIMM11_P (VALUE) \
1236 : (C) == 'M' ? SPARC_SIMM10_P (VALUE) \
1237 : (C) == 'N' ? SPARC_SETHI_P (VALUE) \
1238 : (C) == 'O' ? (VALUE) == 4096 \
1241 /* Similar, but for CONST_DOUBLEs, and defining letters G and H.
1242 Here VALUE is the CONST_DOUBLE rtx itself. */
1244 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1245 ((C) == 'G' ? const_zero_operand (VALUE, GET_MODE (VALUE)) \
1246 : (C) == 'H' ? arith_double_operand (VALUE, DImode) \
1249 /* Given an rtx X being reloaded into a reg required to be
1250 in class CLASS, return the class of reg to actually use.
1251 In general this is just CLASS; but on some machines
1252 in some cases it is preferable to use a more restrictive class. */
1253 /* - We can't load constants into FP registers.
1254 - We can't load FP constants into integer registers when soft-float,
1255 because there is no soft-float pattern with a r/F constraint.
1256 - We can't load FP constants into integer registers for TFmode unless
1257 it is 0.0L, because there is no movtf pattern with a r/F constraint.
1258 - Try and reload integer constants (symbolic or otherwise) back into
1259 registers directly, rather than having them dumped to memory. */
1261 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1263 ? ((FP_REG_CLASS_P (CLASS) \
1264 || (CLASS) == GENERAL_OR_FP_REGS \
1265 || (CLASS) == GENERAL_OR_EXTRA_FP_REGS \
1266 || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1268 || (GET_MODE (X) == TFmode \
1269 && ! const_zero_operand (X, TFmode))) \
1271 : (!FP_REG_CLASS_P (CLASS) \
1272 && GET_MODE_CLASS (GET_MODE (X)) == MODE_INT) \
1277 /* Return the register class of a scratch register needed to load IN into
1278 a register of class CLASS in MODE.
1280 We need a temporary when loading/storing a HImode/QImode value
1281 between memory and the FPU registers. This can happen when combine puts
1282 a paradoxical subreg in a float/fix conversion insn.
1284 We need a temporary when loading/storing a DFmode value between
1285 unaligned memory and the upper FPU registers. */
1287 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1288 ((FP_REG_CLASS_P (CLASS) \
1289 && ((MODE) == HImode || (MODE) == QImode) \
1290 && (GET_CODE (IN) == MEM \
1291 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1292 && true_regnum (IN) == -1))) \
1294 : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \
1295 && GET_CODE (IN) == MEM && TARGET_ARCH32 \
1296 && ! mem_min_alignment ((IN), 8)) \
1298 : (((TARGET_CM_MEDANY \
1299 && symbolic_operand ((IN), (MODE))) \
1300 || (TARGET_CM_EMBMEDANY \
1301 && text_segment_operand ((IN), (MODE)))) \
1306 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1307 ((FP_REG_CLASS_P (CLASS) \
1308 && ((MODE) == HImode || (MODE) == QImode) \
1309 && (GET_CODE (IN) == MEM \
1310 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1311 && true_regnum (IN) == -1))) \
1313 : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \
1314 && GET_CODE (IN) == MEM && TARGET_ARCH32 \
1315 && ! mem_min_alignment ((IN), 8)) \
1317 : (((TARGET_CM_MEDANY \
1318 && symbolic_operand ((IN), (MODE))) \
1319 || (TARGET_CM_EMBMEDANY \
1320 && text_segment_operand ((IN), (MODE)))) \
1325 /* On SPARC it is not possible to directly move data between
1326 GENERAL_REGS and FP_REGS. */
1327 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1328 (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2))
1330 /* Return the stack location to use for secondary memory needed reloads.
1331 We want to use the reserved location just below the frame pointer.
1332 However, we must ensure that there is a frame, so use assign_stack_local
1333 if the frame size is zero. */
1334 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
1335 (get_frame_size () == 0 \
1336 ? assign_stack_local (MODE, GET_MODE_SIZE (MODE), 0) \
1337 : gen_rtx_MEM (MODE, plus_constant (frame_pointer_rtx, \
1338 STARTING_FRAME_OFFSET)))
1340 /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9
1341 because the movsi and movsf patterns don't handle r/f moves.
1342 For v8 we copy the default definition. */
1343 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
1345 ? (GET_MODE_BITSIZE (MODE) < 32 \
1346 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
1348 : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \
1349 ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0) \
1352 /* Return the maximum number of consecutive registers
1353 needed to represent mode MODE in a register of class CLASS. */
1354 /* On SPARC, this is the size of MODE in words. */
1355 #define CLASS_MAX_NREGS(CLASS, MODE) \
1356 (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \
1357 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1359 /* Stack layout; function entry, exit and calling. */
1361 /* Define this if pushing a word on the stack
1362 makes the stack pointer a smaller address. */
1363 #define STACK_GROWS_DOWNWARD
1365 /* Define this if the nominal address of the stack frame
1366 is at the high-address end of the local variables;
1367 that is, each additional local variable allocated
1368 goes at a more negative offset in the frame. */
1369 #define FRAME_GROWS_DOWNWARD
1371 /* Offset within stack frame to start allocating local variables at.
1372 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1373 first local allocated. Otherwise, it is the offset to the BEGINNING
1374 of the first local allocated. */
1375 /* This allows space for one TFmode floating point value, which is used
1376 by SECONDARY_MEMORY_NEEDED_RTX. */
1377 #define STARTING_FRAME_OFFSET \
1378 (TARGET_ARCH64 ? -16 \
1379 : (-SPARC_STACK_ALIGN (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)))
1381 /* Offset of first parameter from the argument pointer register value.
1382 !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg
1383 even if this function isn't going to use it.
1384 v9: This is 128 for the ins and locals. */
1385 #define FIRST_PARM_OFFSET(FNDECL) \
1386 (TARGET_ARCH64 ? 16 * UNITS_PER_WORD : STRUCT_VALUE_OFFSET + UNITS_PER_WORD)
1388 /* Offset from the argument pointer register value to the CFA.
1389 This is different from FIRST_PARM_OFFSET because the register window
1390 comes between the CFA and the arguments. */
1391 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1393 /* When a parameter is passed in a register, stack space is still
1395 !v9: All 6 possible integer registers have backing store allocated.
1396 v9: Only space for the arguments passed is allocated. */
1397 /* ??? Ideally, we'd use zero here (as the minimum), but zero has special
1398 meaning to the backend. Further, we need to be able to detect if a
1399 varargs/unprototyped function is called, as they may want to spill more
1400 registers than we've provided space. Ugly, ugly. So for now we retain
1401 all 6 slots even for v9. */
1402 #define REG_PARM_STACK_SPACE(DECL) (6 * UNITS_PER_WORD)
1404 /* Definitions for register elimination. */
1406 #define ELIMINABLE_REGS \
1407 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1408 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM} }
1410 /* The way this is structured, we can't eliminate SFP in favor of SP
1411 if the frame pointer is required: we want to use the SFP->HFP elimination
1412 in that case. But the test in update_eliminables doesn't know we are
1413 assuming below that we only do the former elimination. */
1414 #define CAN_ELIMINATE(FROM, TO) \
1415 ((TO) == HARD_FRAME_POINTER_REGNUM || !FRAME_POINTER_REQUIRED)
1417 /* We always pretend that this is a leaf function because if it's not,
1418 there's no point in trying to eliminate the frame pointer. If it
1419 is a leaf function, we guessed right! */
1420 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1422 if ((TO) == STACK_POINTER_REGNUM) \
1423 (OFFSET) = sparc_compute_frame_size (get_frame_size (), 1); \
1426 (OFFSET) += SPARC_STACK_BIAS; \
1429 /* Keep the stack pointer constant throughout the function.
1430 This is both an optimization and a necessity: longjmp
1431 doesn't behave itself when the stack pointer moves within
1433 #define ACCUMULATE_OUTGOING_ARGS 1
1435 /* Value is the number of bytes of arguments automatically
1436 popped when returning from a subroutine call.
1437 FUNDECL is the declaration node of the function (as a tree),
1438 FUNTYPE is the data type of the function (as a tree),
1439 or for a library call it is an identifier node for the subroutine name.
1440 SIZE is the number of bytes of arguments passed on the stack. */
1442 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1444 /* Define this macro if the target machine has "register windows". This
1445 C expression returns the register number as seen by the called function
1446 corresponding to register number OUT as seen by the calling function.
1447 Return OUT if register number OUT is not an outbound register. */
1449 #define INCOMING_REGNO(OUT) \
1450 (((OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16)
1452 /* Define this macro if the target machine has "register windows". This
1453 C expression returns the register number as seen by the calling function
1454 corresponding to register number IN as seen by the called function.
1455 Return IN if register number IN is not an inbound register. */
1457 #define OUTGOING_REGNO(IN) \
1458 (((IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16)
1460 /* Define this macro if the target machine has register windows. This
1461 C expression returns true if the register is call-saved but is in the
1464 #define LOCAL_REGNO(REGNO) \
1465 ((REGNO) >= 16 && (REGNO) <= 31)
1467 /* Define how to find the value returned by a function.
1468 VALTYPE is the data type of the value (as a tree).
1469 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1470 otherwise, FUNC is 0. */
1472 /* On SPARC the value is found in the first "output" register. */
1474 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1475 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 1)
1477 /* But the called function leaves it in the first "input" register. */
1479 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
1480 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 0)
1482 /* Define how to find the value returned by a library function
1483 assuming the value has mode MODE. */
1485 #define LIBCALL_VALUE(MODE) \
1486 function_value (NULL_TREE, (MODE), 1)
1488 /* 1 if N is a possible register number for a function value
1489 as seen by the caller.
1490 On SPARC, the first "output" reg is used for integer values,
1491 and the first floating point register is used for floating point values. */
1493 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32)
1495 /* Define the size of space to allocate for the return value of an
1498 #define APPLY_RESULT_SIZE (TARGET_ARCH64 ? 24 : 16)
1500 /* 1 if N is a possible register number for function argument passing.
1501 On SPARC, these are the "output" registers. v9 also uses %f0-%f31. */
1503 #define FUNCTION_ARG_REGNO_P(N) \
1505 ? (((N) >= 8 && (N) <= 13) || ((N) >= 32 && (N) <= 63)) \
1506 : ((N) >= 8 && (N) <= 13))
1508 /* Define a data type for recording info about an argument list
1509 during the scan of that argument list. This data type should
1510 hold all necessary information about the function itself
1511 and about the args processed so far, enough to enable macros
1512 such as FUNCTION_ARG to determine where the next arg should go.
1514 On SPARC (!v9), this is a single integer, which is a number of words
1515 of arguments scanned so far (including the invisible argument,
1516 if any, which holds the structure-value-address).
1517 Thus 7 or more means all following args should go on the stack.
1519 For v9, we also need to know whether a prototype is present. */
1522 int words; /* number of words passed so far */
1523 int prototype_p; /* nonzero if a prototype is present */
1524 int libcall_p; /* nonzero if a library call */
1526 #define CUMULATIVE_ARGS struct sparc_args
1528 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1529 for a call to a function whose data type is FNTYPE.
1530 For a library call, FNTYPE is 0. */
1532 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1533 init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL));
1535 /* Update the data in CUM to advance over an argument
1536 of mode MODE and data type TYPE.
1537 TYPE is null for libcalls where that information may not be available. */
1539 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1540 function_arg_advance (& (CUM), (MODE), (TYPE), (NAMED))
1542 /* Determine where to put an argument to a function.
1543 Value is zero to push the argument on the stack,
1544 or a hard register in which to store the argument.
1546 MODE is the argument's machine mode.
1547 TYPE is the data type of the argument (as a tree).
1548 This is null for libcalls where that information may
1550 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1551 the preceding args and about the function being called.
1552 NAMED is nonzero if this argument is a named parameter
1553 (otherwise it is an extra parameter matching an ellipsis). */
1555 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1556 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 0)
1558 /* Define where a function finds its arguments.
1559 This is different from FUNCTION_ARG because of register windows. */
1561 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
1562 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 1)
1564 /* If defined, a C expression which determines whether, and in which direction,
1565 to pad out an argument with extra space. The value should be of type
1566 `enum direction': either `upward' to pad above the argument,
1567 `downward' to pad below, or `none' to inhibit padding. */
1569 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1570 function_arg_padding ((MODE), (TYPE))
1572 /* If defined, a C expression that gives the alignment boundary, in bits,
1573 of an argument with the specified mode and type. If it is not defined,
1574 PARM_BOUNDARY is used for all arguments.
1575 For sparc64, objects requiring 16 byte alignment are passed that way. */
1577 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1579 && (GET_MODE_ALIGNMENT (MODE) == 128 \
1580 || ((TYPE) && TYPE_ALIGN (TYPE) == 128))) \
1581 ? 128 : PARM_BOUNDARY)
1583 /* Define the information needed to generate branch and scc insns. This is
1584 stored from the compare operation. Note that we can't use "rtx" here
1585 since it hasn't been defined! */
1587 extern GTY(()) rtx sparc_compare_op0;
1588 extern GTY(()) rtx sparc_compare_op1;
1591 /* Generate the special assembly code needed to tell the assembler whatever
1592 it might need to know about the return value of a function.
1594 For SPARC assemblers, we need to output a .proc pseudo-op which conveys
1595 information to the assembler relating to peephole optimization (done in
1598 #define ASM_DECLARE_RESULT(FILE, RESULT) \
1599 fprintf ((FILE), "\t.proc\t0%lo\n", sparc_type_code (TREE_TYPE (RESULT)))
1601 /* Output the special assembly code needed to tell the assembler some
1602 register is used as global register variable.
1604 SPARC 64bit psABI declares registers %g2 and %g3 as application
1605 registers and %g6 and %g7 as OS registers. Any object using them
1606 should declare (for %g2/%g3 has to, for %g6/%g7 can) that it uses them
1607 and how they are used (scratch or some global variable).
1608 Linker will then refuse to link together objects which use those
1609 registers incompatibly.
1611 Unless the registers are used for scratch, two different global
1612 registers cannot be declared to the same name, so in the unlikely
1613 case of a global register variable occupying more than one register
1614 we prefix the second and following registers with .gnu.part1. etc. */
1616 extern GTY(()) char sparc_hard_reg_printed[8];
1618 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
1619 #define ASM_DECLARE_REGISTER_GLOBAL(FILE, DECL, REGNO, NAME) \
1621 if (TARGET_ARCH64) \
1623 int end = HARD_REGNO_NREGS ((REGNO), DECL_MODE (decl)) + (REGNO); \
1625 for (reg = (REGNO); reg < 8 && reg < end; reg++) \
1626 if ((reg & ~1) == 2 || (reg & ~1) == 6) \
1628 if (reg == (REGNO)) \
1629 fprintf ((FILE), "\t.register\t%%g%d, %s\n", reg, (NAME)); \
1631 fprintf ((FILE), "\t.register\t%%g%d, .gnu.part%d.%s\n", \
1632 reg, reg - (REGNO), (NAME)); \
1633 sparc_hard_reg_printed[reg] = 1; \
1640 /* Emit rtl for profiling. */
1641 #define PROFILE_HOOK(LABEL) sparc_profile_hook (LABEL)
1643 /* All the work done in PROFILE_HOOK, but still required. */
1644 #define FUNCTION_PROFILER(FILE, LABELNO) do { } while (0)
1646 /* Set the name of the mcount function for the system. */
1647 #define MCOUNT_FUNCTION "*mcount"
1649 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1650 the stack pointer does not matter. The value is tested only in
1651 functions that have frame pointers.
1652 No definition is equivalent to always zero. */
1654 #define EXIT_IGNORE_STACK \
1655 (get_frame_size () != 0 \
1656 || current_function_calls_alloca || current_function_outgoing_args_size)
1658 /* Define registers used by the epilogue and return instruction. */
1659 #define EPILOGUE_USES(REGNO) ((REGNO) == 31 \
1660 || (current_function_calls_eh_return && (REGNO) == 1))
1662 /* Length in units of the trampoline for entering a nested function. */
1664 #define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 32 : 16)
1666 #define TRAMPOLINE_ALIGNMENT 128 /* 16 bytes */
1668 /* Emit RTL insns to initialize the variable parts of a trampoline.
1669 FNADDR is an RTX for the address of the function's pure code.
1670 CXT is an RTX for the static chain value for the function. */
1672 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1673 if (TARGET_ARCH64) \
1674 sparc64_initialize_trampoline (TRAMP, FNADDR, CXT); \
1676 sparc_initialize_trampoline (TRAMP, FNADDR, CXT)
1678 /* Implement `va_start' for varargs and stdarg. */
1679 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
1680 sparc_va_start (valist, nextarg)
1682 /* Generate RTL to flush the register windows so as to make arbitrary frames
1684 #define SETUP_FRAME_ADDRESSES() \
1685 emit_insn (gen_flush_register_windows ())
1687 /* Given an rtx for the address of a frame,
1688 return an rtx for the address of the word in the frame
1689 that holds the dynamic chain--the previous frame's address. */
1690 #define DYNAMIC_CHAIN_ADDRESS(frame) \
1691 plus_constant (frame, 14 * UNITS_PER_WORD + SPARC_STACK_BIAS)
1693 /* The return address isn't on the stack, it is in a register, so we can't
1694 access it from the current frame pointer. We can access it from the
1695 previous frame pointer though by reading a value from the register window
1697 #define RETURN_ADDR_IN_PREVIOUS_FRAME
1699 /* This is the offset of the return address to the true next instruction to be
1700 executed for the current function. */
1701 #define RETURN_ADDR_OFFSET \
1702 (8 + 4 * (! TARGET_ARCH64 && current_function_returns_struct))
1704 /* The current return address is in %i7. The return address of anything
1705 farther back is in the register window save area at [%fp+60]. */
1706 /* ??? This ignores the fact that the actual return address is +8 for normal
1707 returns, and +12 for structure returns. */
1708 #define RETURN_ADDR_RTX(count, frame) \
1710 ? gen_rtx_REG (Pmode, 31) \
1711 : gen_rtx_MEM (Pmode, \
1712 memory_address (Pmode, plus_constant (frame, \
1713 15 * UNITS_PER_WORD \
1714 + SPARC_STACK_BIAS))))
1716 /* Before the prologue, the return address is %o7 + 8. OK, sometimes it's
1717 +12, but always using +8 is close enough for frame unwind purposes.
1718 Actually, just using %o7 is close enough for unwinding, but %o7+8
1719 is something you can return to. */
1720 #define INCOMING_RETURN_ADDR_RTX \
1721 plus_constant (gen_rtx_REG (word_mode, 15), 8)
1722 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (15)
1724 /* The offset from the incoming value of %sp to the top of the stack frame
1725 for the current function. On sparc64, we have to account for the stack
1727 #define INCOMING_FRAME_SP_OFFSET SPARC_STACK_BIAS
1729 /* Describe how we implement __builtin_eh_return. */
1730 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 24 : INVALID_REGNUM)
1731 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 1) /* %g1 */
1732 #define EH_RETURN_HANDLER_RTX gen_rtx_REG (Pmode, 31) /* %i7 */
1734 /* Select a format to encode pointers in exception handling data. CODE
1735 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
1736 true if the symbol may be affected by dynamic relocations.
1738 If assembler and linker properly support .uaword %r_disp32(foo),
1739 then use PC relative 32-bit relocations instead of absolute relocs
1740 for shared libraries. On sparc64, use pc relative 32-bit relocs even
1741 for binaries, to save memory.
1743 binutils 2.12 would emit a R_SPARC_DISP32 dynamic relocation if the
1744 symbol %r_disp32() is against was not local, but .hidden. In that
1745 case, we have to use DW_EH_PE_absptr for pic personality. */
1746 #ifdef HAVE_AS_SPARC_UA_PCREL
1747 #ifdef HAVE_AS_SPARC_UA_PCREL_HIDDEN
1748 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
1750 ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\
1751 : ((TARGET_ARCH64 && ! GLOBAL) \
1752 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \
1755 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
1757 ? (GLOBAL ? DW_EH_PE_absptr : (DW_EH_PE_pcrel | DW_EH_PE_sdata4)) \
1758 : ((TARGET_ARCH64 && ! GLOBAL) \
1759 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \
1763 /* Emit a PC-relative relocation. */
1764 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \
1766 fputs (integer_asm_op (SIZE, FALSE), FILE); \
1767 fprintf (FILE, "%%r_disp%d(", SIZE * 8); \
1768 assemble_name (FILE, LABEL); \
1769 fputc (')', FILE); \
1773 /* Addressing modes, and classification of registers for them. */
1775 /* Macros to check register numbers against specific register classes. */
1777 /* These assume that REGNO is a hard or pseudo reg number.
1778 They give nonzero only if REGNO is a hard reg of the suitable class
1779 or a pseudo reg currently allocated to a suitable hard reg.
1780 Since they use reg_renumber, they are safe only once reg_renumber
1781 has been allocated, which happens in local-alloc.c. */
1783 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1784 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < (unsigned)32 \
1785 || (REGNO) == FRAME_POINTER_REGNUM \
1786 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)
1788 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO)
1790 #define REGNO_OK_FOR_FP_P(REGNO) \
1791 (((unsigned) (REGNO) - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)) \
1792 || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)))
1793 #define REGNO_OK_FOR_CCFP_P(REGNO) \
1795 && (((unsigned) (REGNO) - 96 < (unsigned)4) \
1796 || ((unsigned) reg_renumber[REGNO] - 96 < (unsigned)4)))
1798 /* Now macros that check whether X is a register and also,
1799 strictly, whether it is in a specified class.
1801 These macros are specific to the SPARC, and may be used only
1802 in code for printing assembler insns and in conditions for
1803 define_optimization. */
1805 /* 1 if X is an fp register. */
1807 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1809 /* Is X, a REG, an in or global register? i.e. is regno 0..7 or 24..31 */
1810 #define IN_OR_GLOBAL_P(X) (REGNO (X) < 8 || (REGNO (X) >= 24 && REGNO (X) <= 31))
1812 /* Maximum number of registers that can appear in a valid memory address. */
1814 #define MAX_REGS_PER_ADDRESS 2
1816 /* Recognize any constant value that is a valid address.
1817 When PIC, we do not accept an address that would require a scratch reg
1818 to load into a register. */
1820 #define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1822 /* Define this, so that when PIC, reload won't try to reload invalid
1823 addresses which require two reload registers. */
1825 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
1827 /* Nonzero if the constant value X is a legitimate general operand.
1828 Anything can be made to work except floating point constants.
1829 If TARGET_VIS, 0.0 can be made to work as well. */
1831 #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X)
1833 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1834 and check its validity for a certain class.
1835 We have two alternate definitions for each of them.
1836 The usual definition accepts all pseudo regs; the other rejects
1837 them unless they have been allocated suitable hard regs.
1838 The symbol REG_OK_STRICT causes the latter definition to be used.
1840 Most source files want to accept pseudo regs in the hope that
1841 they will get allocated to the class that the insn wants them to be in.
1842 Source files for reload pass need to be strict.
1843 After reload, it makes no difference, since pseudo regs have
1844 been eliminated by then. */
1846 /* Optional extra constraints for this machine.
1848 'Q' handles floating point constants which can be moved into
1849 an integer register with a single sethi instruction.
1851 'R' handles floating point constants which can be moved into
1852 an integer register with a single mov instruction.
1854 'S' handles floating point constants which can be moved into
1855 an integer register using a high/lo_sum sequence.
1857 'T' handles memory addresses where the alignment is known to
1858 be at least 8 bytes.
1860 `U' handles all pseudo registers or a hard even numbered
1861 integer register, needed for ldd/std instructions.
1863 'W' handles the memory operand when moving operands in/out
1864 of 'e' constraint floating point registers.
1866 'Y' handles the zero vector constant. */
1868 #ifndef REG_OK_STRICT
1870 /* Nonzero if X is a hard reg that can be used as an index
1871 or if it is a pseudo reg. */
1872 #define REG_OK_FOR_INDEX_P(X) \
1874 || REGNO (X) == FRAME_POINTER_REGNUM \
1875 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1877 /* Nonzero if X is a hard reg that can be used as a base reg
1878 or if it is a pseudo reg. */
1879 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_INDEX_P (X)
1881 /* 'T', 'U' are for aligned memory loads which aren't needed for arch64.
1882 'W' is like 'T' but is assumed true on arch64.
1884 Remember to accept pseudo-registers for memory constraints if reload is
1887 #define EXTRA_CONSTRAINT(OP, C) \
1888 sparc_extra_constraint_check(OP, C, 0)
1892 /* Nonzero if X is a hard reg that can be used as an index. */
1893 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1894 /* Nonzero if X is a hard reg that can be used as a base reg. */
1895 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1897 #define EXTRA_CONSTRAINT(OP, C) \
1898 sparc_extra_constraint_check(OP, C, 1)
1902 /* Should gcc use [%reg+%lo(xx)+offset] addresses? */
1904 #ifdef HAVE_AS_OFFSETABLE_LO10
1905 #define USE_AS_OFFSETABLE_LO10 1
1907 #define USE_AS_OFFSETABLE_LO10 0
1910 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1911 that is a valid memory address for an instruction.
1912 The MODE argument is the machine mode for the MEM expression
1913 that wants to use this address.
1915 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
1916 ordinarily. This changes a bit when generating PIC.
1918 If you change this, execute "rm explow.o recog.o reload.o". */
1920 #define SYMBOLIC_CONST(X) symbolic_operand (X, VOIDmode)
1922 #define RTX_OK_FOR_BASE_P(X) \
1923 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1924 || (GET_CODE (X) == SUBREG \
1925 && GET_CODE (SUBREG_REG (X)) == REG \
1926 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
1928 #define RTX_OK_FOR_INDEX_P(X) \
1929 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
1930 || (GET_CODE (X) == SUBREG \
1931 && GET_CODE (SUBREG_REG (X)) == REG \
1932 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
1934 #define RTX_OK_FOR_OFFSET_P(X) \
1935 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000 - 8)
1937 #define RTX_OK_FOR_OLO10_P(X) \
1938 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0xc00 - 8)
1940 #ifdef REG_OK_STRICT
1941 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1943 if (legitimate_address_p (MODE, X, 1)) \
1947 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1949 if (legitimate_address_p (MODE, X, 0)) \
1954 /* Go to LABEL if ADDR (a legitimate address expression)
1955 has an effect that depends on the machine mode it is used for.
1961 is not equivalent to
1963 (mem:QI [%l7+a]) (mem:QI [%l7+a+1])
1965 because [%l7+a+1] is interpreted as the address of (a+1). */
1967 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1969 if (flag_pic == 1) \
1971 if (GET_CODE (ADDR) == PLUS) \
1973 rtx op0 = XEXP (ADDR, 0); \
1974 rtx op1 = XEXP (ADDR, 1); \
1975 if (op0 == pic_offset_table_rtx \
1976 && SYMBOLIC_CONST (op1)) \
1982 /* Try machine-dependent ways of modifying an illegitimate address
1983 to be legitimate. If we find one, return the new, valid address.
1984 This macro is used in only one place: `memory_address' in explow.c.
1986 OLDX is the address as it was before break_out_memory_refs was called.
1987 In some cases it is useful to look at this to decide what needs to be done.
1989 MODE and WIN are passed so that this macro can use
1990 GO_IF_LEGITIMATE_ADDRESS.
1992 It is always safe for this macro to do nothing. It exists to recognize
1993 opportunities to optimize the output. */
1995 /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
1996 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1998 (X) = legitimize_address (X, OLDX, MODE); \
1999 if (memory_address_p (MODE, X)) \
2003 /* Try a machine-dependent way of reloading an illegitimate address
2004 operand. If we find one, push the reload and jump to WIN. This
2005 macro is used in only one place: `find_reloads_address' in reload.c.
2007 For SPARC 32, we wish to handle addresses by splitting them into
2008 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
2009 This cuts the number of extra insns by one.
2011 Do nothing when generating PIC code and the address is a
2012 symbolic operand or requires a scratch register. */
2014 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2016 /* Decompose SImode constants into hi+lo_sum. We do have to \
2017 rerecognize what we produce, so be careful. */ \
2018 if (CONSTANT_P (X) \
2019 && (MODE != TFmode || TARGET_ARCH64) \
2020 && GET_MODE (X) == SImode \
2021 && GET_CODE (X) != LO_SUM && GET_CODE (X) != HIGH \
2023 && (symbolic_operand (X, Pmode) \
2024 || pic_address_needs_scratch (X))) \
2025 && sparc_cmodel <= CM_MEDLOW) \
2027 X = gen_rtx_LO_SUM (GET_MODE (X), \
2028 gen_rtx_HIGH (GET_MODE (X), X), X); \
2029 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
2030 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
2034 /* ??? 64-bit reloads. */ \
2037 /* Specify the machine mode that this machine uses
2038 for the index in the tablejump instruction. */
2039 /* If we ever implement any of the full models (such as CM_FULLANY),
2040 this has to be DImode in that case */
2041 #ifdef HAVE_GAS_SUBSECTION_ORDERING
2042 #define CASE_VECTOR_MODE \
2043 (! TARGET_PTR64 ? SImode : flag_pic ? SImode : TARGET_CM_MEDLOW ? SImode : DImode)
2045 /* If assembler does not have working .subsection -1, we use DImode for pic, as otherwise
2046 we have to sign extend which slows things down. */
2047 #define CASE_VECTOR_MODE \
2048 (! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode)
2051 /* Define this as 1 if `char' should by default be signed; else as 0. */
2052 #define DEFAULT_SIGNED_CHAR 1
2054 /* Max number of bytes we can move from memory to memory
2055 in one reasonably fast instruction. */
2058 /* If a memory-to-memory move would take MOVE_RATIO or more simple
2059 move-instruction pairs, we will do a movmem or libcall instead. */
2061 #define MOVE_RATIO (optimize_size ? 3 : 8)
2063 /* Define if operations between registers always perform the operation
2064 on the full register even if a narrower mode is specified. */
2065 #define WORD_REGISTER_OPERATIONS
2067 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2068 will either zero-extend or sign-extend. The value of this macro should
2069 be the code that says which one of the two operations is implicitly
2070 done, UNKNOWN if none. */
2071 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2073 /* Nonzero if access to memory by bytes is slow and undesirable.
2074 For RISC chips, it means that access to memory by bytes is no
2075 better than access by words when possible, so grab a whole word
2076 and maybe make use of that. */
2077 #define SLOW_BYTE_ACCESS 1
2079 /* Define this to be nonzero if shift instructions ignore all but the low-order
2081 #define SHIFT_COUNT_TRUNCATED 1
2083 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2084 is done just by pretending it is already truncated. */
2085 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2087 /* Specify the machine mode used for addresses. */
2088 #define Pmode (TARGET_ARCH64 ? DImode : SImode)
2090 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2091 return the mode to be used for the comparison. For floating-point,
2092 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2093 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2094 processing is needed. */
2095 #define SELECT_CC_MODE(OP,X,Y) select_cc_mode ((OP), (X), (Y))
2097 /* Return nonzero if MODE implies a floating point inequality can be
2098 reversed. For SPARC this is always true because we have a full
2099 compliment of ordered and unordered comparisons, but until generic
2100 code knows how to reverse it correctly we keep the old definition. */
2101 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode && (MODE) != CCFPmode)
2103 /* A function address in a call instruction for indexing purposes. */
2104 #define FUNCTION_MODE Pmode
2106 /* Define this if addresses of constant functions
2107 shouldn't be put through pseudo regs where they can be cse'd.
2108 Desirable on machines where ordinary constants are expensive
2109 but a CALL with constant address is cheap. */
2110 #define NO_FUNCTION_CSE
2112 /* alloca should avoid clobbering the old register save area. */
2113 #define SETJMP_VIA_SAVE_AREA
2115 /* The _Q_* comparison libcalls return booleans. */
2116 #define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) ((MODE) == TFmode)
2118 /* Assume by default that the _Qp_* 64-bit libcalls are implemented such
2119 that the inputs are fully consumed before the output memory is clobbered. */
2121 #define TARGET_BUGGY_QP_LIB 0
2123 /* Assume by default that we do not have the Solaris-specific conversion
2124 routines nor 64-bit integer multiply and divide routines. */
2126 #define SUN_CONVERSION_LIBFUNCS 0
2127 #define DITF_CONVERSION_LIBFUNCS 0
2128 #define SUN_INTEGER_MULTIPLY_64 0
2130 /* Compute extra cost of moving data between one register class
2132 #define GENERAL_OR_I64(C) ((C) == GENERAL_REGS || (C) == I64_REGS)
2133 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
2134 (((FP_REG_CLASS_P (CLASS1) && GENERAL_OR_I64 (CLASS2)) \
2135 || (GENERAL_OR_I64 (CLASS1) && FP_REG_CLASS_P (CLASS2)) \
2136 || (CLASS1) == FPCC_REGS || (CLASS2) == FPCC_REGS) \
2137 ? ((sparc_cpu == PROCESSOR_ULTRASPARC \
2138 || sparc_cpu == PROCESSOR_ULTRASPARC3) ? 12 : 6) : 2)
2140 /* Provide the cost of a branch. For pre-v9 processors we use
2141 a value of 3 to take into account the potential annulling of
2142 the delay slot (which ends up being a bubble in the pipeline slot)
2143 plus a cycle to take into consideration the instruction cache
2146 On v9 and later, which have branch prediction facilities, we set
2147 it to the depth of the pipeline as that is the cost of a
2148 mispredicted branch. */
2150 #define BRANCH_COST \
2151 ((sparc_cpu == PROCESSOR_V9 \
2152 || sparc_cpu == PROCESSOR_ULTRASPARC) \
2154 : (sparc_cpu == PROCESSOR_ULTRASPARC3 \
2157 #define PREFETCH_BLOCK \
2158 ((sparc_cpu == PROCESSOR_ULTRASPARC \
2159 || sparc_cpu == PROCESSOR_ULTRASPARC3) \
2162 #define SIMULTANEOUS_PREFETCHES \
2163 ((sparc_cpu == PROCESSOR_ULTRASPARC) \
2165 : (sparc_cpu == PROCESSOR_ULTRASPARC3 \
2168 /* Control the assembler format that we output. */
2170 /* A C string constant describing how to begin a comment in the target
2171 assembler language. The compiler assumes that the comment will end at
2172 the end of the line. */
2174 #define ASM_COMMENT_START "!"
2176 /* Output to assembler file text saying following lines
2177 may contain character constants, extra white space, comments, etc. */
2179 #define ASM_APP_ON ""
2181 /* Output to assembler file text saying following lines
2182 no longer contain unusual constructs. */
2184 #define ASM_APP_OFF ""
2186 /* How to refer to registers in assembler output.
2187 This sequence is indexed by compiler's hard-register-number (see above). */
2189 #define REGISTER_NAMES \
2190 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \
2191 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \
2192 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \
2193 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \
2194 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \
2195 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \
2196 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \
2197 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \
2198 "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \
2199 "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \
2200 "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \
2201 "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \
2202 "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc", "%sfp" }
2204 /* Define additional names for use in asm clobbers and asm declarations. */
2206 #define ADDITIONAL_REGISTER_NAMES \
2207 {{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}}
2209 /* On Sun 4, this limit is 2048. We use 1000 to be safe, since the length
2210 can run past this up to a continuation point. Once we used 1500, but
2211 a single entry in C++ can run more than 500 bytes, due to the length of
2212 mangled symbol names. dbxout.c should really be fixed to do
2213 continuations when they are actually needed instead of trying to
2215 #define DBX_CONTIN_LENGTH 1000
2217 /* This is how to output a command to make the user-level label named NAME
2218 defined for reference from other files. */
2220 /* Globalizing directive for a label. */
2221 #define GLOBAL_ASM_OP "\t.global "
2223 /* The prefix to add to user-visible assembler symbols. */
2225 #define USER_LABEL_PREFIX "_"
2227 /* This is how to store into the string LABEL
2228 the symbol_ref name of an internal numbered label where
2229 PREFIX is the class of label and NUM is the number within the class.
2230 This is suitable for output with `assemble_name'. */
2232 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2233 sprintf ((LABEL), "*%s%ld", (PREFIX), (long)(NUM))
2235 /* This is how we hook in and defer the case-vector until the end of
2237 #define ASM_OUTPUT_ADDR_VEC(LAB,VEC) \
2238 sparc_defer_case_vector ((LAB),(VEC), 0)
2240 #define ASM_OUTPUT_ADDR_DIFF_VEC(LAB,VEC) \
2241 sparc_defer_case_vector ((LAB),(VEC), 1)
2243 /* This is how to output an element of a case-vector that is absolute. */
2245 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2248 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
2249 if (CASE_VECTOR_MODE == SImode) \
2250 fprintf (FILE, "\t.word\t"); \
2252 fprintf (FILE, "\t.xword\t"); \
2253 assemble_name (FILE, label); \
2254 fputc ('\n', FILE); \
2257 /* This is how to output an element of a case-vector that is relative.
2258 (SPARC uses such vectors only when generating PIC.) */
2260 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2263 ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE)); \
2264 if (CASE_VECTOR_MODE == SImode) \
2265 fprintf (FILE, "\t.word\t"); \
2267 fprintf (FILE, "\t.xword\t"); \
2268 assemble_name (FILE, label); \
2269 ASM_GENERATE_INTERNAL_LABEL (label, "L", (REL)); \
2270 fputc ('-', FILE); \
2271 assemble_name (FILE, label); \
2272 fputc ('\n', FILE); \
2275 /* This is what to output before and after case-vector (both
2276 relative and absolute). If .subsection -1 works, we put case-vectors
2277 at the beginning of the current section. */
2279 #ifdef HAVE_GAS_SUBSECTION_ORDERING
2281 #define ASM_OUTPUT_ADDR_VEC_START(FILE) \
2282 fprintf(FILE, "\t.subsection\t-1\n")
2284 #define ASM_OUTPUT_ADDR_VEC_END(FILE) \
2285 fprintf(FILE, "\t.previous\n")
2289 /* This is how to output an assembler line
2290 that says to advance the location counter
2291 to a multiple of 2**LOG bytes. */
2293 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2295 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
2297 /* This is how to output an assembler line that says to advance
2298 the location counter to a multiple of 2**LOG bytes using the
2299 "nop" instruction as padding. */
2300 #define ASM_OUTPUT_ALIGN_WITH_NOP(FILE,LOG) \
2302 fprintf (FILE, "\t.align %d,0x1000000\n", (1<<(LOG)))
2304 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
2305 fprintf (FILE, "\t.skip "HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2307 /* This says how to output an assembler line
2308 to define a global common symbol. */
2310 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
2311 ( fputs ("\t.common ", (FILE)), \
2312 assemble_name ((FILE), (NAME)), \
2313 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\"\n", (SIZE)))
2315 /* This says how to output an assembler line to define a local common
2318 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \
2319 ( fputs ("\t.reserve ", (FILE)), \
2320 assemble_name ((FILE), (NAME)), \
2321 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\",%u\n", \
2322 (SIZE), ((ALIGNED) / BITS_PER_UNIT)))
2324 /* A C statement (sans semicolon) to output to the stdio stream
2325 FILE the assembler definition of uninitialized global DECL named
2326 NAME whose size is SIZE bytes and alignment is ALIGN bytes.
2327 Try to use asm_output_aligned_bss to implement this macro. */
2329 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2331 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \
2334 #define IDENT_ASM_OP "\t.ident\t"
2336 /* Output #ident as a .ident. */
2338 #define ASM_OUTPUT_IDENT(FILE, NAME) \
2339 fprintf (FILE, "%s\"%s\"\n", IDENT_ASM_OP, NAME);
2341 /* Prettify the assembly. */
2343 extern int sparc_indent_opcode;
2345 #define ASM_OUTPUT_OPCODE(FILE, PTR) \
2347 if (sparc_indent_opcode) \
2350 sparc_indent_opcode = 0; \
2354 /* Emit a dtp-relative reference to a TLS variable. */
2357 #define ASM_OUTPUT_DWARF_DTPREL(FILE, SIZE, X) \
2358 sparc_output_dwarf_dtprel (FILE, SIZE, X)
2361 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
2362 ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '(' \
2363 || (CHAR) == ')' || (CHAR) == '_' || (CHAR) == '&')
2365 /* Print operand X (an rtx) in assembler syntax to file FILE.
2366 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2367 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2369 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2371 /* Print a memory address as an operand to reference that memory location. */
2373 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2374 { register rtx base, index = 0; \
2376 register rtx addr = ADDR; \
2377 if (GET_CODE (addr) == REG) \
2378 fputs (reg_names[REGNO (addr)], FILE); \
2379 else if (GET_CODE (addr) == PLUS) \
2381 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
2382 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\
2383 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
2384 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\
2386 base = XEXP (addr, 0), index = XEXP (addr, 1); \
2387 if (GET_CODE (base) == LO_SUM) \
2389 gcc_assert (USE_AS_OFFSETABLE_LO10 \
2391 && ! TARGET_CM_MEDMID); \
2392 output_operand (XEXP (base, 0), 0); \
2393 fputs ("+%lo(", FILE); \
2394 output_address (XEXP (base, 1)); \
2395 fprintf (FILE, ")+%d", offset); \
2399 fputs (reg_names[REGNO (base)], FILE); \
2401 fprintf (FILE, "%+d", offset); \
2402 else if (GET_CODE (index) == REG) \
2403 fprintf (FILE, "+%s", reg_names[REGNO (index)]); \
2404 else if (GET_CODE (index) == SYMBOL_REF \
2405 || GET_CODE (index) == CONST) \
2406 fputc ('+', FILE), output_addr_const (FILE, index); \
2407 else gcc_unreachable (); \
2410 else if (GET_CODE (addr) == MINUS \
2411 && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \
2413 output_addr_const (FILE, XEXP (addr, 0)); \
2414 fputs ("-(", FILE); \
2415 output_addr_const (FILE, XEXP (addr, 1)); \
2416 fputs ("-.)", FILE); \
2418 else if (GET_CODE (addr) == LO_SUM) \
2420 output_operand (XEXP (addr, 0), 0); \
2421 if (TARGET_CM_MEDMID) \
2422 fputs ("+%l44(", FILE); \
2424 fputs ("+%lo(", FILE); \
2425 output_address (XEXP (addr, 1)); \
2426 fputc (')', FILE); \
2428 else if (flag_pic && GET_CODE (addr) == CONST \
2429 && GET_CODE (XEXP (addr, 0)) == MINUS \
2430 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \
2431 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \
2432 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \
2434 addr = XEXP (addr, 0); \
2435 output_addr_const (FILE, XEXP (addr, 0)); \
2436 /* Group the args of the second CONST in parenthesis. */ \
2437 fputs ("-(", FILE); \
2438 /* Skip past the second CONST--it does nothing for us. */\
2439 output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \
2440 /* Close the parenthesis. */ \
2441 fputc (')', FILE); \
2445 output_addr_const (FILE, addr); \
2450 #define TARGET_TLS 1
2452 #define TARGET_TLS 0
2454 #define TARGET_SUN_TLS TARGET_TLS
2455 #define TARGET_GNU_TLS 0
2457 /* The number of Pmode words for the setjmp buffer. */
2458 #define JMP_BUF_SIZE 12