1 /* Definitions of target machine for GNU compiler, for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1994, 1995, 1996, 1997, 1998, 1999
3 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com).
5 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 /* Note that some other tm.h files include this one and then override
26 whatever definitions are necessary. */
28 /* Define the specific costs for a given cpu */
30 struct processor_costs {
34 /* Integer signed load */
37 /* Integer zeroed load */
43 /* fmov, fneg, fabs */
47 const int float_plusminus;
53 const int float_cmove;
59 const int float_div_sf;
62 const int float_div_df;
65 const int float_sqrt_sf;
68 const int float_sqrt_df;
76 /* integer multiply cost for each bit set past the most
77 significant 3, so the formula for multiply cost becomes:
80 highest_bit = highest_clear_bit(rs1);
82 highest_bit = highest_set_bit(rs1);
85 cost = int_mul{,X} + ((highest_bit - 3) / int_mul_bit_factor);
87 A value of zero indicates that the multiply costs is fixed,
89 const int int_mul_bit_factor;
100 /* penalty for shifts, due to scheduling rules etc. */
101 const int shift_penalty;
104 extern const struct processor_costs *sparc_costs;
106 /* Target CPU builtins. FIXME: Defining sparc is for the benefit of
107 Solaris only; otherwise just define __sparc__. Sadly the headers
108 are such a mess there is no Solaris-specific header. */
109 #define TARGET_CPU_CPP_BUILTINS() \
112 builtin_define_std ("sparc"); \
115 builtin_assert ("cpu=sparc64"); \
116 builtin_assert ("machine=sparc64"); \
120 builtin_assert ("cpu=sparc"); \
121 builtin_assert ("machine=sparc"); \
126 /* Specify this in a cover file to provide bi-architecture (32/64) support. */
127 /* #define SPARC_BI_ARCH */
129 /* Macro used later in this file to determine default architecture. */
130 #define DEFAULT_ARCH32_P ((TARGET_DEFAULT & MASK_64BIT) == 0)
132 /* TARGET_ARCH{32,64} are the main macros to decide which of the two
133 architectures to compile for. We allow targets to choose compile time or
134 runtime selection. */
136 #if defined(__sparcv9) || defined(__arch64__)
137 #define TARGET_ARCH32 0
139 #define TARGET_ARCH32 1
143 #define TARGET_ARCH32 (! TARGET_64BIT)
145 #define TARGET_ARCH32 (DEFAULT_ARCH32_P)
146 #endif /* SPARC_BI_ARCH */
147 #endif /* IN_LIBGCC2 */
148 #define TARGET_ARCH64 (! TARGET_ARCH32)
150 /* Code model selection in 64-bit environment.
152 The machine mode used for addresses is 32-bit wide:
154 TARGET_CM_32: 32-bit address space.
155 It is the code model used when generating 32-bit code.
157 The machine mode used for addresses is 64-bit wide:
159 TARGET_CM_MEDLOW: 32-bit address space.
160 The executable must be in the low 32 bits of memory.
161 This avoids generating %uhi and %ulo terms. Programs
162 can be statically or dynamically linked.
164 TARGET_CM_MEDMID: 44-bit address space.
165 The executable must be in the low 44 bits of memory,
166 and the %[hml]44 terms are used. The text and data
167 segments have a maximum size of 2GB (31-bit span).
168 The maximum offset from any instruction to the label
169 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span).
171 TARGET_CM_MEDANY: 64-bit address space.
172 The text and data segments have a maximum size of 2GB
173 (31-bit span) and may be located anywhere in memory.
174 The maximum offset from any instruction to the label
175 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span).
177 TARGET_CM_EMBMEDANY: 64-bit address space.
178 The text and data segments have a maximum size of 2GB
179 (31-bit span) and may be located anywhere in memory.
180 The global register %g4 contains the start address of
181 the data segment. Programs are statically linked and
182 PIC is not supported.
184 Different code models are not supported in 32-bit environment. */
194 /* Value of -mcmodel specified by user. */
195 extern const char *sparc_cmodel_string;
197 extern enum cmodel sparc_cmodel;
199 /* V9 code model selection. */
200 #define TARGET_CM_MEDLOW (sparc_cmodel == CM_MEDLOW)
201 #define TARGET_CM_MEDMID (sparc_cmodel == CM_MEDMID)
202 #define TARGET_CM_MEDANY (sparc_cmodel == CM_MEDANY)
203 #define TARGET_CM_EMBMEDANY (sparc_cmodel == CM_EMBMEDANY)
205 #define SPARC_DEFAULT_CMODEL CM_32
207 /* The SPARC-V9 architecture defines a relaxed memory ordering model (RMO)
208 which requires the following macro to be true if enabled. Prior to V9,
209 there are no instructions to even talk about memory synchronization.
210 Note that the UltraSPARC III processors don't implement RMO, unlike the
211 UltraSPARC II processors.
213 Default to false; for example, Solaris never enables RMO, only ever uses
214 total memory ordering (TMO). */
215 #define SPARC_RELAXED_ORDERING false
217 /* Do not use the .note.GNU-stack convention by default. */
218 #define NEED_INDICATE_EXEC_STACK 0
220 /* This is call-clobbered in the normal ABI, but is reserved in the
221 home grown (aka upward compatible) embedded ABI. */
222 #define EMBMEDANY_BASE_REG "%g4"
224 /* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile,
225 and specified by the user via --with-cpu=foo.
226 This specifies the cpu implementation, not the architecture size. */
227 /* Note that TARGET_CPU_v9 is assumed to start the list of 64-bit
229 #define TARGET_CPU_sparc 0
230 #define TARGET_CPU_v7 0 /* alias for previous */
231 #define TARGET_CPU_sparclet 1
232 #define TARGET_CPU_sparclite 2
233 #define TARGET_CPU_v8 3 /* generic v8 implementation */
234 #define TARGET_CPU_supersparc 4
235 #define TARGET_CPU_hypersparc 5
236 #define TARGET_CPU_sparc86x 6
237 #define TARGET_CPU_sparclite86x 6
238 #define TARGET_CPU_v9 7 /* generic v9 implementation */
239 #define TARGET_CPU_sparcv9 7 /* alias */
240 #define TARGET_CPU_sparc64 7 /* alias */
241 #define TARGET_CPU_ultrasparc 8
242 #define TARGET_CPU_ultrasparc3 9
244 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
245 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \
246 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3
248 #define CPP_CPU32_DEFAULT_SPEC ""
249 #define ASM_CPU32_DEFAULT_SPEC ""
251 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9
252 /* ??? What does Sun's CC pass? */
253 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
254 /* ??? It's not clear how other assemblers will handle this, so by default
255 use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case
256 is handled in sol2.h. */
257 #define ASM_CPU64_DEFAULT_SPEC "-Av9"
259 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc
260 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
261 #define ASM_CPU64_DEFAULT_SPEC "-Av9a"
263 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3
264 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
265 #define ASM_CPU64_DEFAULT_SPEC "-Av9b"
270 #define CPP_CPU64_DEFAULT_SPEC ""
271 #define ASM_CPU64_DEFAULT_SPEC ""
273 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc \
274 || TARGET_CPU_DEFAULT == TARGET_CPU_v8
275 #define CPP_CPU32_DEFAULT_SPEC ""
276 #define ASM_CPU32_DEFAULT_SPEC ""
279 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet
280 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclet__"
281 #define ASM_CPU32_DEFAULT_SPEC "-Asparclet"
284 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite
285 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite__"
286 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
289 #if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc
290 #define CPP_CPU32_DEFAULT_SPEC "-D__supersparc__ -D__sparc_v8__"
291 #define ASM_CPU32_DEFAULT_SPEC ""
294 #if TARGET_CPU_DEFAULT == TARGET_CPU_hypersparc
295 #define CPP_CPU32_DEFAULT_SPEC "-D__hypersparc__ -D__sparc_v8__"
296 #define ASM_CPU32_DEFAULT_SPEC ""
299 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite86x
300 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite86x__"
301 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
306 #if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC)
307 #error Unrecognized value in TARGET_CPU_DEFAULT.
312 #define CPP_CPU_DEFAULT_SPEC \
313 (DEFAULT_ARCH32_P ? "\
314 %{m64:" CPP_CPU64_DEFAULT_SPEC "} \
315 %{!m64:" CPP_CPU32_DEFAULT_SPEC "} \
317 %{m32:" CPP_CPU32_DEFAULT_SPEC "} \
318 %{!m32:" CPP_CPU64_DEFAULT_SPEC "} \
320 #define ASM_CPU_DEFAULT_SPEC \
321 (DEFAULT_ARCH32_P ? "\
322 %{m64:" ASM_CPU64_DEFAULT_SPEC "} \
323 %{!m64:" ASM_CPU32_DEFAULT_SPEC "} \
325 %{m32:" ASM_CPU32_DEFAULT_SPEC "} \
326 %{!m32:" ASM_CPU64_DEFAULT_SPEC "} \
329 #else /* !SPARC_BI_ARCH */
331 #define CPP_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? CPP_CPU32_DEFAULT_SPEC : CPP_CPU64_DEFAULT_SPEC)
332 #define ASM_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? ASM_CPU32_DEFAULT_SPEC : ASM_CPU64_DEFAULT_SPEC)
334 #endif /* !SPARC_BI_ARCH */
336 /* Define macros to distinguish architectures. */
338 /* Common CPP definitions used by CPP_SPEC amongst the various targets
339 for handling -mcpu=xxx switches. */
340 #define CPP_CPU_SPEC "\
341 %{msoft-float:-D_SOFT_FLOAT} \
343 %{msparclite:-D__sparclite__} \
344 %{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \
345 %{mv8:-D__sparc_v8__} \
346 %{msupersparc:-D__supersparc__ -D__sparc_v8__} \
347 %{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \
348 %{mcpu=sparclite:-D__sparclite__} \
349 %{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \
350 %{mcpu=v8:-D__sparc_v8__} \
351 %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \
352 %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \
353 %{mcpu=sparclite86x:-D__sparclite86x__} \
354 %{mcpu=v9:-D__sparc_v9__} \
355 %{mcpu=ultrasparc:-D__sparc_v9__} \
356 %{mcpu=ultrasparc3:-D__sparc_v9__} \
357 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \
359 #define CPP_ARCH32_SPEC ""
360 #define CPP_ARCH64_SPEC "-D__arch64__"
362 #define CPP_ARCH_DEFAULT_SPEC \
363 (DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC)
365 #define CPP_ARCH_SPEC "\
366 %{m32:%(cpp_arch32)} \
367 %{m64:%(cpp_arch64)} \
368 %{!m32:%{!m64:%(cpp_arch_default)}} \
371 /* Macros to distinguish endianness. */
372 #define CPP_ENDIAN_SPEC "\
373 %{mlittle-endian:-D__LITTLE_ENDIAN__} \
374 %{mlittle-endian-data:-D__LITTLE_ENDIAN_DATA__}"
376 /* Macros to distinguish the particular subtarget. */
377 #define CPP_SUBTARGET_SPEC ""
379 #define CPP_SPEC "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_subtarget)"
381 /* Prevent error on `-sun4' and `-target sun4' options. */
382 /* This used to translate -dalign to -malign, but that is no good
383 because it can't turn off the usual meaning of making debugging dumps. */
384 /* Translate old style -m<cpu> into new style -mcpu=<cpu>.
385 ??? Delete support for -m<cpu> for 2.9. */
388 %{sun4:} %{target:} \
389 %{mcypress:-mcpu=cypress} \
390 %{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \
391 %{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \
394 /* Override in target specific files. */
395 #define ASM_CPU_SPEC "\
396 %{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \
397 %{msparclite:-Asparclite} \
398 %{mf930:-Asparclite} %{mf934:-Asparclite} \
399 %{mcpu=sparclite:-Asparclite} \
400 %{mcpu=sparclite86x:-Asparclite} \
401 %{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \
402 %{mv8plus:-Av8plus} \
404 %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \
405 %{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \
406 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_cpu_default)}}}}}}} \
409 /* Word size selection, among other things.
410 This is what GAS uses. Add %(asm_arch) to ASM_SPEC to enable. */
412 #define ASM_ARCH32_SPEC "-32"
413 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
414 #define ASM_ARCH64_SPEC "-64 -no-undeclared-regs"
416 #define ASM_ARCH64_SPEC "-64"
418 #define ASM_ARCH_DEFAULT_SPEC \
419 (DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC)
421 #define ASM_ARCH_SPEC "\
422 %{m32:%(asm_arch32)} \
423 %{m64:%(asm_arch64)} \
424 %{!m32:%{!m64:%(asm_arch_default)}} \
427 #ifdef HAVE_AS_RELAX_OPTION
428 #define ASM_RELAX_SPEC "%{!mno-relax:-relax}"
430 #define ASM_RELAX_SPEC ""
433 /* Special flags to the Sun-4 assembler when using pipe for input. */
436 %{R} %{!pg:%{!p:%{fpic|fPIC|fpie|fPIE:-k}}} %{keep-local-as-symbols:-L} \
437 %(asm_cpu) %(asm_relax)"
439 #define AS_NEEDS_DASH_FOR_PIPED_INPUT
441 /* This macro defines names of additional specifications to put in the specs
442 that can be used in various specifications like CC1_SPEC. Its definition
443 is an initializer with a subgrouping for each command option.
445 Each subgrouping contains a string constant, that defines the
446 specification name, and a string constant that used by the GCC driver
449 Do not define this macro if it does not need to do anything. */
451 #define EXTRA_SPECS \
452 { "cpp_cpu", CPP_CPU_SPEC }, \
453 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
454 { "cpp_arch32", CPP_ARCH32_SPEC }, \
455 { "cpp_arch64", CPP_ARCH64_SPEC }, \
456 { "cpp_arch_default", CPP_ARCH_DEFAULT_SPEC },\
457 { "cpp_arch", CPP_ARCH_SPEC }, \
458 { "cpp_endian", CPP_ENDIAN_SPEC }, \
459 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \
460 { "asm_cpu", ASM_CPU_SPEC }, \
461 { "asm_cpu_default", ASM_CPU_DEFAULT_SPEC }, \
462 { "asm_arch32", ASM_ARCH32_SPEC }, \
463 { "asm_arch64", ASM_ARCH64_SPEC }, \
464 { "asm_relax", ASM_RELAX_SPEC }, \
465 { "asm_arch_default", ASM_ARCH_DEFAULT_SPEC },\
466 { "asm_arch", ASM_ARCH_SPEC }, \
467 SUBTARGET_EXTRA_SPECS
469 #define SUBTARGET_EXTRA_SPECS
471 /* Because libgcc can generate references back to libc (via .umul etc.) we have
472 to list libc again after the second libgcc. */
473 #define LINK_GCC_C_SEQUENCE_SPEC "%G %L %G %L"
476 #define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int")
477 #define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int")
479 /* ??? This should be 32 bits for v9 but what can we do? */
480 #define WCHAR_TYPE "short unsigned int"
481 #define WCHAR_TYPE_SIZE 16
483 /* Show we can debug even without a frame pointer. */
484 #define CAN_DEBUG_WITHOUT_FP
486 /* Option handling. */
488 #define OVERRIDE_OPTIONS sparc_override_options ()
490 /* Mask of all CPU selection flags. */
492 (MASK_V8 + MASK_SPARCLITE + MASK_SPARCLET + MASK_V9 + MASK_DEPRECATED_V8_INSNS)
494 /* TARGET_HARD_MUL: Use hardware multiply instructions but not %y.
495 TARGET_HARD_MUL32: Use hardware multiply instructions with rd %y
496 to get high 32 bits. False in V8+ or V9 because multiply stores
497 a 64 bit result in a register. */
499 #define TARGET_HARD_MUL32 \
500 ((TARGET_V8 || TARGET_SPARCLITE \
501 || TARGET_SPARCLET || TARGET_DEPRECATED_V8_INSNS) \
502 && ! TARGET_V8PLUS && TARGET_ARCH32)
504 #define TARGET_HARD_MUL \
505 (TARGET_V8 || TARGET_SPARCLITE || TARGET_SPARCLET \
506 || TARGET_DEPRECATED_V8_INSNS || TARGET_V8PLUS)
508 /* MASK_APP_REGS must always be the default because that's what
509 FIXED_REGISTERS is set to and -ffixed- is processed before
510 CONDITIONAL_REGISTER_USAGE is called (where we process -mno-app-regs). */
511 #define TARGET_DEFAULT (MASK_APP_REGS + MASK_FPU)
514 These must match the values for the cpu attribute in sparc.md. */
515 enum processor_type {
519 PROCESSOR_SUPERSPARC,
523 PROCESSOR_HYPERSPARC,
524 PROCESSOR_SPARCLITE86X,
528 PROCESSOR_ULTRASPARC,
529 PROCESSOR_ULTRASPARC3
532 /* This is set from -m{cpu,tune}=xxx. */
533 extern enum processor_type sparc_cpu;
535 /* Recast the cpu class to be the cpu attribute.
536 Every file includes us, but not every file includes insn-attr.h. */
537 #define sparc_cpu_attr ((enum attr_cpu) sparc_cpu)
539 /* Support for a compile-time default CPU, et cetera. The rules are:
540 --with-cpu is ignored if -mcpu is specified.
541 --with-tune is ignored if -mtune is specified.
542 --with-float is ignored if -mhard-float, -msoft-float, -mfpu, or -mno-fpu
544 #define OPTION_DEFAULT_SPECS \
545 {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \
546 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
547 {"float", "%{!msoft-float:%{!mhard-float:%{!fpu:%{!no-fpu:-m%(VALUE)-float}}}}" }
549 /* sparc_select[0] is reserved for the default cpu. */
550 struct sparc_cpu_select
553 const char *const name;
554 const int set_tune_p;
555 const int set_arch_p;
558 extern struct sparc_cpu_select sparc_select[];
560 /* target machine storage layout */
562 /* Define this if most significant bit is lowest numbered
563 in instructions that operate on numbered bit-fields. */
564 #define BITS_BIG_ENDIAN 1
566 /* Define this if most significant byte of a word is the lowest numbered. */
567 #define BYTES_BIG_ENDIAN 1
569 /* Define this if most significant word of a multiword number is the lowest
571 #define WORDS_BIG_ENDIAN 1
573 /* Define this to set the endianness to use in libgcc2.c, which can
574 not depend on target_flags. */
575 #if defined (__LITTLE_ENDIAN__) || defined(__LITTLE_ENDIAN_DATA__)
576 #define LIBGCC2_WORDS_BIG_ENDIAN 0
578 #define LIBGCC2_WORDS_BIG_ENDIAN 1
581 #define MAX_BITS_PER_WORD 64
583 /* Width of a word, in units (bytes). */
584 #define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4)
586 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
588 #define MIN_UNITS_PER_WORD 4
591 #define UNITS_PER_SIMD_WORD (TARGET_VIS ? 8 : 0)
593 /* Now define the sizes of the C data types. */
595 #define SHORT_TYPE_SIZE 16
596 #define INT_TYPE_SIZE 32
597 #define LONG_TYPE_SIZE (TARGET_ARCH64 ? 64 : 32)
598 #define LONG_LONG_TYPE_SIZE 64
599 #define FLOAT_TYPE_SIZE 32
600 #define DOUBLE_TYPE_SIZE 64
601 /* LONG_DOUBLE_TYPE_SIZE is defined per OS even though the
602 SPARC ABI says that it is 128-bit wide. */
603 /* #define LONG_DOUBLE_TYPE_SIZE 128 */
605 /* Width in bits of a pointer.
606 See also the macro `Pmode' defined below. */
607 #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32)
609 /* If we have to extend pointers (only when TARGET_ARCH64 and not
610 TARGET_PTR64), we want to do it unsigned. This macro does nothing
611 if ptr_mode and Pmode are the same. */
612 #define POINTERS_EXTEND_UNSIGNED 1
614 /* For TARGET_ARCH64 we need this, as we don't have instructions
615 for arithmetic operations which do zero/sign extension at the same time,
616 so without this we end up with a srl/sra after every assignment to an
617 user variable, which means very very bad code. */
618 #define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
620 && GET_MODE_CLASS (MODE) == MODE_INT \
621 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
624 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
625 #define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
627 /* Boundary (in *bits*) on which stack pointer should be aligned. */
628 /* FIXME, this is wrong when TARGET_ARCH64 and TARGET_STACK_BIAS, because
629 then sp+2047 is 128-bit aligned so sp is really only byte-aligned. */
630 #define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64)
631 /* Temporary hack until the FIXME above is fixed. This macro is used
632 only in pad_to_arg_alignment in function.c; see the comment there
633 for details about what it does. */
634 #define SPARC_STACK_BOUNDARY_HACK (TARGET_ARCH64 && TARGET_STACK_BIAS)
636 /* ALIGN FRAMES on double word boundaries */
638 #define SPARC_STACK_ALIGN(LOC) \
639 (TARGET_ARCH64 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7))
641 /* Allocation boundary (in *bits*) for the code of a function. */
642 #define FUNCTION_BOUNDARY 32
644 /* Alignment of field after `int : 0' in a structure. */
645 #define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
647 /* Every structure's size must be a multiple of this. */
648 #define STRUCTURE_SIZE_BOUNDARY 8
650 /* A bit-field declared as `int' forces `int' alignment for the struct. */
651 #define PCC_BITFIELD_TYPE_MATTERS 1
653 /* No data type wants to be aligned rounder than this. */
654 #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64)
656 /* The best alignment to use in cases where we have a choice. */
657 #define FASTEST_ALIGNMENT 64
659 /* Define this macro as an expression for the alignment of a structure
660 (given by STRUCT as a tree node) if the alignment computed in the
661 usual way is COMPUTED and the alignment explicitly specified was
664 The default is to use SPECIFIED if it is larger; otherwise, use
665 the smaller of COMPUTED and `BIGGEST_ALIGNMENT' */
666 #define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \
667 (TARGET_FASTER_STRUCTS ? \
668 ((TREE_CODE (STRUCT) == RECORD_TYPE \
669 || TREE_CODE (STRUCT) == UNION_TYPE \
670 || TREE_CODE (STRUCT) == QUAL_UNION_TYPE) \
671 && TYPE_FIELDS (STRUCT) != 0 \
672 ? MAX (MAX ((COMPUTED), (SPECIFIED)), BIGGEST_ALIGNMENT) \
673 : MAX ((COMPUTED), (SPECIFIED))) \
674 : MAX ((COMPUTED), (SPECIFIED)))
676 /* Make strings word-aligned so strcpy from constants will be faster. */
677 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
678 ((TREE_CODE (EXP) == STRING_CST \
679 && (ALIGN) < FASTEST_ALIGNMENT) \
680 ? FASTEST_ALIGNMENT : (ALIGN))
682 /* Make arrays of chars word-aligned for the same reasons. */
683 #define DATA_ALIGNMENT(TYPE, ALIGN) \
684 (TREE_CODE (TYPE) == ARRAY_TYPE \
685 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
686 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
688 /* Set this nonzero if move instructions will actually fail to work
689 when given unaligned data. */
690 #define STRICT_ALIGNMENT 1
692 /* Things that must be doubleword aligned cannot go in the text section,
693 because the linker fails to align the text section enough!
694 Put them in the data section. This macro is only used in this file. */
695 #define MAX_TEXT_ALIGN 32
697 /* Standard register usage. */
699 /* Number of actual hardware registers.
700 The hardware registers are assigned numbers for the compiler
701 from 0 to just below FIRST_PSEUDO_REGISTER.
702 All registers that the compiler knows about must be given numbers,
703 even those that are not normally considered general registers.
705 SPARC has 32 integer registers and 32 floating point registers.
706 64 bit SPARC has 32 additional fp regs, but the odd numbered ones are not
707 accessible. We still account for them to simplify register computations
708 (e.g.: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so
710 Register 100 is used as the integer condition code register.
711 Register 101 is used as the soft frame pointer register. */
713 #define FIRST_PSEUDO_REGISTER 102
715 #define SPARC_FIRST_FP_REG 32
716 /* Additional V9 fp regs. */
717 #define SPARC_FIRST_V9_FP_REG 64
718 #define SPARC_LAST_V9_FP_REG 95
719 /* V9 %fcc[0123]. V8 uses (figuratively) %fcc0. */
720 #define SPARC_FIRST_V9_FCC_REG 96
721 #define SPARC_LAST_V9_FCC_REG 99
723 #define SPARC_FCC_REG 96
724 /* Integer CC reg. We don't distinguish %icc from %xcc. */
725 #define SPARC_ICC_REG 100
727 /* Nonzero if REGNO is an fp reg. */
728 #define SPARC_FP_REG_P(REGNO) \
729 ((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG)
731 /* Argument passing regs. */
732 #define SPARC_OUTGOING_INT_ARG_FIRST 8
733 #define SPARC_INCOMING_INT_ARG_FIRST 24
734 #define SPARC_FP_ARG_FIRST 32
736 /* 1 for registers that have pervasive standard uses
737 and are not available for the register allocator.
740 g1 is free to use as temporary.
741 g2-g4 are reserved for applications. Gcc normally uses them as
742 temporaries, but this can be disabled via the -mno-app-regs option.
743 g5 through g7 are reserved for the operating system.
746 g1,g5 are free to use as temporaries, and are free to use between calls
747 if the call is to an external function via the PLT.
748 g4 is free to use as a temporary in the non-embedded case.
749 g4 is reserved in the embedded case.
750 g2-g3 are reserved for applications. Gcc normally uses them as
751 temporaries, but this can be disabled via the -mno-app-regs option.
752 g6-g7 are reserved for the operating system (or application in
754 ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must
755 currently be a fixed register until this pattern is rewritten.
756 Register 1 is also used when restoring call-preserved registers in large
759 Registers fixed in arch32 and not arch64 (or vice-versa) are marked in
760 CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-.
763 #define FIXED_REGISTERS \
764 {1, 0, 2, 2, 2, 2, 1, 1, \
765 0, 0, 0, 0, 0, 0, 1, 0, \
766 0, 0, 0, 0, 0, 0, 0, 0, \
767 0, 0, 0, 0, 0, 0, 1, 1, \
769 0, 0, 0, 0, 0, 0, 0, 0, \
770 0, 0, 0, 0, 0, 0, 0, 0, \
771 0, 0, 0, 0, 0, 0, 0, 0, \
772 0, 0, 0, 0, 0, 0, 0, 0, \
774 0, 0, 0, 0, 0, 0, 0, 0, \
775 0, 0, 0, 0, 0, 0, 0, 0, \
776 0, 0, 0, 0, 0, 0, 0, 0, \
777 0, 0, 0, 0, 0, 0, 0, 0, \
781 /* 1 for registers not available across function calls.
782 These must include the FIXED_REGISTERS and also any
783 registers that can be used without being saved.
784 The latter must include the registers where values are returned
785 and the register where structure-value addresses are passed.
786 Aside from that, you can include as many other registers as you like. */
788 #define CALL_USED_REGISTERS \
789 {1, 1, 1, 1, 1, 1, 1, 1, \
790 1, 1, 1, 1, 1, 1, 1, 1, \
791 0, 0, 0, 0, 0, 0, 0, 0, \
792 0, 0, 0, 0, 0, 0, 1, 1, \
794 1, 1, 1, 1, 1, 1, 1, 1, \
795 1, 1, 1, 1, 1, 1, 1, 1, \
796 1, 1, 1, 1, 1, 1, 1, 1, \
797 1, 1, 1, 1, 1, 1, 1, 1, \
799 1, 1, 1, 1, 1, 1, 1, 1, \
800 1, 1, 1, 1, 1, 1, 1, 1, \
801 1, 1, 1, 1, 1, 1, 1, 1, \
802 1, 1, 1, 1, 1, 1, 1, 1, \
806 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
807 they won't be allocated. */
809 #define CONDITIONAL_REGISTER_USAGE \
812 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
814 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
815 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
817 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */ \
818 /* then honor it. */ \
819 if (TARGET_ARCH32 && fixed_regs[5]) \
821 else if (TARGET_ARCH64 && fixed_regs[5] == 2) \
826 for (regno = SPARC_FIRST_V9_FP_REG; \
827 regno <= SPARC_LAST_V9_FP_REG; \
829 fixed_regs[regno] = 1; \
830 /* %fcc0 is used by v8 and v9. */ \
831 for (regno = SPARC_FIRST_V9_FCC_REG + 1; \
832 regno <= SPARC_LAST_V9_FCC_REG; \
834 fixed_regs[regno] = 1; \
839 for (regno = 32; regno < SPARC_LAST_V9_FCC_REG; regno++) \
840 fixed_regs[regno] = 1; \
842 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */ \
843 /* then honor it. Likewise with g3 and g4. */ \
844 if (fixed_regs[2] == 2) \
845 fixed_regs[2] = ! TARGET_APP_REGS; \
846 if (fixed_regs[3] == 2) \
847 fixed_regs[3] = ! TARGET_APP_REGS; \
848 if (TARGET_ARCH32 && fixed_regs[4] == 2) \
849 fixed_regs[4] = ! TARGET_APP_REGS; \
850 else if (TARGET_CM_EMBMEDANY) \
852 else if (fixed_regs[4] == 2) \
857 /* Return number of consecutive hard regs needed starting at reg REGNO
858 to hold something of mode MODE.
859 This is ordinarily the length in words of a value of mode MODE
860 but can be less for certain modes in special long registers.
862 On SPARC, ordinary registers hold 32 bits worth;
863 this means both integer and floating point registers.
864 On v9, integer regs hold 64 bits worth; floating point regs hold
865 32 bits worth (this includes the new fp regs as even the odd ones are
866 included in the hard register count). */
868 #define HARD_REGNO_NREGS(REGNO, MODE) \
870 ? ((REGNO) < 32 || (REGNO) == FRAME_POINTER_REGNUM \
871 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \
872 : (GET_MODE_SIZE (MODE) + 3) / 4) \
873 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
875 /* Due to the ARCH64 discrepancy above we must override this next
877 #define REGMODE_NATURAL_SIZE(MODE) \
878 ((TARGET_ARCH64 && FLOAT_MODE_P (MODE)) ? 4 : UNITS_PER_WORD)
880 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
881 See sparc.c for how we initialize this. */
882 extern const int *hard_regno_mode_classes;
883 extern int sparc_mode_class[];
885 /* ??? Because of the funny way we pass parameters we should allow certain
886 ??? types of float/complex values to be in integer registers during
887 ??? RTL generation. This only matters on arch32. */
888 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
889 ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0)
891 /* Value is 1 if it is a good idea to tie two pseudo registers
892 when one has mode MODE1 and one has mode MODE2.
893 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
894 for any hard reg, then this must be 0 for correct output.
896 For V9: SFmode can't be combined with other float modes, because they can't
897 be allocated to the %d registers. Also, DFmode won't fit in odd %f
898 registers, but SFmode will. */
899 #define MODES_TIEABLE_P(MODE1, MODE2) \
900 ((MODE1) == (MODE2) \
901 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
903 || (GET_MODE_CLASS (MODE1) != MODE_FLOAT \
904 || (MODE1 != SFmode && MODE2 != SFmode)))))
906 /* Specify the registers used for certain standard purposes.
907 The values of these macros are register numbers. */
909 /* SPARC pc isn't overloaded on a register that the compiler knows about. */
910 /* #define PC_REGNUM */
912 /* Register to use for pushing function arguments. */
913 #define STACK_POINTER_REGNUM 14
915 /* The stack bias (amount by which the hardware register is offset by). */
916 #define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0)
918 /* Actual top-of-stack address is 92/176 greater than the contents of the
919 stack pointer register for !v9/v9. That is:
920 - !v9: 64 bytes for the in and local registers, 4 bytes for structure return
921 address, and 6*4 bytes for the 6 register parameters.
922 - v9: 128 bytes for the in and local registers + 6*8 bytes for the integer
924 #define STACK_POINTER_OFFSET (FIRST_PARM_OFFSET(0) + SPARC_STACK_BIAS)
926 /* Base register for access to local variables of the function. */
927 #define HARD_FRAME_POINTER_REGNUM 30
929 /* The soft frame pointer does not have the stack bias applied. */
930 #define FRAME_POINTER_REGNUM 101
932 /* Given the stack bias, the stack pointer isn't actually aligned. */
933 #define INIT_EXPANDERS \
935 if (cfun && cfun->emit->regno_pointer_align && SPARC_STACK_BIAS) \
937 REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = BITS_PER_UNIT; \
938 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT; \
942 /* Value should be nonzero if functions must have frame pointers.
943 Zero means the frame pointer need not be set up (and parms
944 may be accessed via the stack pointer) in functions that seem suitable.
945 Used in flow.c, global.c, ra.c and reload1.c. */
946 #define FRAME_POINTER_REQUIRED \
947 (! (leaf_function_p () && only_leaf_regs_used ()))
949 /* Base register for access to arguments of the function. */
950 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM
952 /* Register in which static-chain is passed to a function. This must
953 not be a register used by the prologue. */
954 #define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2)
956 /* Register which holds offset table for position-independent
959 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 23 : INVALID_REGNUM)
961 /* Pick a default value we can notice from override_options:
963 v9: Default is off. */
965 #define DEFAULT_PCC_STRUCT_RETURN -1
967 /* Functions which return large structures get the address
968 to place the wanted value at offset 64 from the frame.
969 Must reserve 64 bytes for the in and local registers.
970 v9: Functions which return large structures get the address to place the
971 wanted value from an invisible first argument. */
972 #define STRUCT_VALUE_OFFSET 64
974 /* Define the classes of registers for register constraints in the
975 machine description. Also define ranges of constants.
977 One of the classes must always be named ALL_REGS and include all hard regs.
978 If there is more than one class, another class must be named NO_REGS
979 and contain no registers.
981 The name GENERAL_REGS must be the name of a class (or an alias for
982 another name such as ALL_REGS). This is the class of registers
983 that is allowed by "g" or "r" in a register constraint.
984 Also, registers outside this class are allocated only when
985 instructions express preferences for them.
987 The classes must be numbered in nondecreasing order; that is,
988 a larger-numbered class must never be contained completely
989 in a smaller-numbered class.
991 For any two classes, it is very desirable that there be another
992 class that represents their union. */
994 /* The SPARC has various kinds of registers: general, floating point,
995 and condition codes [well, it has others as well, but none that we
996 care directly about].
998 For v9 we must distinguish between the upper and lower floating point
999 registers because the upper ones can't hold SFmode values.
1000 HARD_REGNO_MODE_OK won't help here because reload assumes that register(s)
1001 satisfying a group need for a class will also satisfy a single need for
1002 that class. EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp
1005 It is important that one class contains all the general and all the standard
1006 fp regs. Otherwise find_reg() won't properly allocate int regs for moves,
1007 because reg_class_record() will bias the selection in favor of fp regs,
1008 because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS,
1009 because FP_REGS > GENERAL_REGS.
1011 It is also important that one class contain all the general and all the
1012 fp regs. Otherwise when spilling a DFmode reg, it may be from EXTRA_FP_REGS
1013 but find_reloads() may use class GENERAL_OR_FP_REGS. This will cause
1014 allocate_reload_reg() to bypass it causing an abort because the compiler
1015 thinks it doesn't have a spill reg when in fact it does.
1017 v9 also has 4 floating point condition code registers. Since we don't
1018 have a class that is the union of FPCC_REGS with either of the others,
1019 it is important that it appear first. Otherwise the compiler will die
1020 trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its
1023 It is important that SPARC_ICC_REG have class NO_REGS. Otherwise combine
1024 may try to use it to hold an SImode value. See register_operand.
1025 ??? Should %fcc[0123] be handled similarly?
1028 enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS,
1029 EXTRA_FP_REGS, GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS,
1030 ALL_REGS, LIM_REG_CLASSES };
1032 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1034 /* Give names of register classes as strings for dump file. */
1036 #define REG_CLASS_NAMES \
1037 { "NO_REGS", "FPCC_REGS", "I64_REGS", "GENERAL_REGS", "FP_REGS", \
1038 "EXTRA_FP_REGS", "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", \
1041 /* Define which registers fit in which classes.
1042 This is an initializer for a vector of HARD_REG_SET
1043 of length N_REG_CLASSES. */
1045 #define REG_CLASS_CONTENTS \
1046 {{0, 0, 0, 0}, /* NO_REGS */ \
1047 {0, 0, 0, 0xf}, /* FPCC_REGS */ \
1048 {0xffff, 0, 0, 0}, /* I64_REGS */ \
1049 {-1, 0, 0, 0x20}, /* GENERAL_REGS */ \
1050 {0, -1, 0, 0}, /* FP_REGS */ \
1051 {0, -1, -1, 0}, /* EXTRA_FP_REGS */ \
1052 {-1, -1, 0, 0x20}, /* GENERAL_OR_FP_REGS */ \
1053 {-1, -1, -1, 0x20}, /* GENERAL_OR_EXTRA_FP_REGS */ \
1054 {-1, -1, -1, 0x3f}} /* ALL_REGS */
1056 /* Defines invalid mode changes. Borrowed from pa64-regs.h.
1058 SImode loads to floating-point registers are not zero-extended.
1059 The definition for LOAD_EXTEND_OP specifies that integer loads
1060 narrower than BITS_PER_WORD will be zero-extended. As a result,
1061 we inhibit changes from SImode unless they are to a mode that is
1062 identical in size. */
1064 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1066 && (FROM) == SImode \
1067 && GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1068 ? reg_classes_intersect_p (CLASS, FP_REGS) : 0)
1070 /* The same information, inverted:
1071 Return the class number of the smallest class containing
1072 reg number REGNO. This could be a conditional expression
1073 or could index an array. */
1075 extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
1077 #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)]
1079 /* This is the order in which to allocate registers normally.
1081 We put %f0-%f7 last among the float registers, so as to make it more
1082 likely that a pseudo-register which dies in the float return register
1083 area will get allocated to the float return register, thus saving a move
1084 instruction at the end of the function.
1086 Similarly for integer return value registers.
1088 We know in this case that we will not end up with a leaf function.
1090 The register allocator is given the global and out registers first
1091 because these registers are call clobbered and thus less useful to
1092 global register allocation.
1094 Next we list the local and in registers. They are not call clobbered
1095 and thus very useful for global register allocation. We list the input
1096 registers before the locals so that it is more likely the incoming
1097 arguments received in those registers can just stay there and not be
1100 #define REG_ALLOC_ORDER \
1101 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \
1102 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \
1104 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \
1105 29, 28, 27, 26, 25, 24, 31, /* %i5-%i0,%i7 */\
1106 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \
1107 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \
1108 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \
1109 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \
1110 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \
1111 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \
1112 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \
1113 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \
1114 96, 97, 98, 99, /* %fcc0-3 */ \
1115 100, 0, 14, 30, 101} /* %icc, %g0, %o6, %i6, %sfp */
1117 /* This is the order in which to allocate registers for
1118 leaf functions. If all registers can fit in the global and
1119 output registers, then we have the possibility of having a leaf
1122 The macro actually mentioned the input registers first,
1123 because they get renumbered into the output registers once
1124 we know really do have a leaf function.
1126 To be more precise, this register allocation order is used
1127 when %o7 is found to not be clobbered right before register
1128 allocation. Normally, the reason %o7 would be clobbered is
1129 due to a call which could not be transformed into a sibling
1132 As a consequence, it is possible to use the leaf register
1133 allocation order and not end up with a leaf function. We will
1134 not get suboptimal register allocation in that case because by
1135 definition of being potentially leaf, there were no function
1136 calls. Therefore, allocation order within the local register
1137 window is not critical like it is when we do have function calls. */
1139 #define REG_LEAF_ALLOC_ORDER \
1140 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \
1141 29, 28, 27, 26, 25, 24, /* %i5-%i0 */ \
1143 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \
1144 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \
1145 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \
1146 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \
1147 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \
1148 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \
1149 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \
1150 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \
1151 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \
1152 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \
1153 96, 97, 98, 99, /* %fcc0-3 */ \
1154 100, 0, 14, 30, 31, 101} /* %icc, %g0, %o6, %i6, %i7, %sfp */
1156 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
1158 extern char sparc_leaf_regs[];
1159 #define LEAF_REGISTERS sparc_leaf_regs
1161 extern char leaf_reg_remap[];
1162 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO])
1164 /* The class value for index registers, and the one for base regs. */
1165 #define INDEX_REG_CLASS GENERAL_REGS
1166 #define BASE_REG_CLASS GENERAL_REGS
1168 /* Local macro to handle the two v9 classes of FP regs. */
1169 #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS)
1171 /* Get reg_class from a letter such as appears in the machine description.
1172 In the not-v9 case, coerce v9's 'e' class to 'f', so we can use 'e' in the
1173 .md file for v8 and v9.
1174 'd' and 'b' are used for single and double precision VIS operations,
1176 'h' is used for V8+ 64 bit global and out registers. */
1178 #define REG_CLASS_FROM_LETTER(C) \
1180 ? ((C) == 'f' ? FP_REGS \
1181 : (C) == 'e' ? EXTRA_FP_REGS \
1182 : (C) == 'c' ? FPCC_REGS \
1183 : ((C) == 'd' && TARGET_VIS) ? FP_REGS\
1184 : ((C) == 'b' && TARGET_VIS) ? EXTRA_FP_REGS\
1185 : ((C) == 'h' && TARGET_V8PLUS) ? I64_REGS\
1187 : ((C) == 'f' ? FP_REGS \
1188 : (C) == 'e' ? FP_REGS \
1189 : (C) == 'c' ? FPCC_REGS \
1192 /* The letters I, J, K, L and M in a register constraint string
1193 can be used to stand for particular ranges of immediate operands.
1194 This macro defines what the ranges are.
1195 C is the letter, and VALUE is a constant value.
1196 Return 1 if VALUE is in the range specified by C.
1198 `I' is used for the range of constants an insn can actually contain.
1199 `J' is used for the range which is just zero (since that is R0).
1200 `K' is used for constants which can be loaded with a single sethi insn.
1201 `L' is used for the range of constants supported by the movcc insns.
1202 `M' is used for the range of constants supported by the movrcc insns.
1203 `N' is like K, but for constants wider than 32 bits.
1204 `O' is used for the range which is just 4096. */
1206 #define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400)
1207 #define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800)
1208 #define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000)
1209 /* 10 and 11 bit immediates are only used for a few specific insns.
1210 SMALL_INT is used throughout the port so we continue to use it. */
1211 #define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X)))
1212 /* 13 bit immediate, considering only the low 32 bits */
1213 #define SMALL_INT32(X) (SPARC_SIMM13_P (trunc_int_for_mode \
1214 (INTVAL (X), SImode)))
1215 #define SPARC_SETHI_P(X) \
1216 (((unsigned HOST_WIDE_INT) (X) \
1217 & ((unsigned HOST_WIDE_INT) 0x3ff - GET_MODE_MASK (SImode) - 1)) == 0)
1218 #define SPARC_SETHI32_P(X) \
1219 (SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode)))
1221 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1222 ((C) == 'I' ? SPARC_SIMM13_P (VALUE) \
1223 : (C) == 'J' ? (VALUE) == 0 \
1224 : (C) == 'K' ? SPARC_SETHI32_P (VALUE) \
1225 : (C) == 'L' ? SPARC_SIMM11_P (VALUE) \
1226 : (C) == 'M' ? SPARC_SIMM10_P (VALUE) \
1227 : (C) == 'N' ? SPARC_SETHI_P (VALUE) \
1228 : (C) == 'O' ? (VALUE) == 4096 \
1231 /* Similar, but for floating constants, and defining letters G and H.
1232 Here VALUE is the CONST_DOUBLE rtx itself. */
1234 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1235 ((C) == 'G' ? fp_zero_operand (VALUE, GET_MODE (VALUE)) \
1236 : (C) == 'H' ? arith_double_operand (VALUE, DImode) \
1237 : (C) == 'O' ? arith_double_4096_operand (VALUE, DImode) \
1240 /* Given an rtx X being reloaded into a reg required to be
1241 in class CLASS, return the class of reg to actually use.
1242 In general this is just CLASS; but on some machines
1243 in some cases it is preferable to use a more restrictive class. */
1244 /* - We can't load constants into FP registers.
1245 - We can't load FP constants into integer registers when soft-float,
1246 because there is no soft-float pattern with a r/F constraint.
1247 - We can't load FP constants into integer registers for TFmode unless
1248 it is 0.0L, because there is no movtf pattern with a r/F constraint.
1249 - Try and reload integer constants (symbolic or otherwise) back into
1250 registers directly, rather than having them dumped to memory. */
1252 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1254 ? ((FP_REG_CLASS_P (CLASS) \
1255 || (CLASS) == GENERAL_OR_FP_REGS \
1256 || (CLASS) == GENERAL_OR_EXTRA_FP_REGS \
1257 || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1259 || (GET_MODE (X) == TFmode \
1260 && ! fp_zero_operand (X, TFmode))) \
1262 : (!FP_REG_CLASS_P (CLASS) \
1263 && GET_MODE_CLASS (GET_MODE (X)) == MODE_INT) \
1268 /* Return the register class of a scratch register needed to load IN into
1269 a register of class CLASS in MODE.
1271 We need a temporary when loading/storing a HImode/QImode value
1272 between memory and the FPU registers. This can happen when combine puts
1273 a paradoxical subreg in a float/fix conversion insn.
1275 We need a temporary when loading/storing a DFmode value between
1276 unaligned memory and the upper FPU registers. */
1278 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1279 ((FP_REG_CLASS_P (CLASS) \
1280 && ((MODE) == HImode || (MODE) == QImode) \
1281 && (GET_CODE (IN) == MEM \
1282 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1283 && true_regnum (IN) == -1))) \
1285 : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \
1286 && GET_CODE (IN) == MEM && TARGET_ARCH32 \
1287 && ! mem_min_alignment ((IN), 8)) \
1289 : (((TARGET_CM_MEDANY \
1290 && symbolic_operand ((IN), (MODE))) \
1291 || (TARGET_CM_EMBMEDANY \
1292 && text_segment_operand ((IN), (MODE)))) \
1297 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1298 ((FP_REG_CLASS_P (CLASS) \
1299 && ((MODE) == HImode || (MODE) == QImode) \
1300 && (GET_CODE (IN) == MEM \
1301 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1302 && true_regnum (IN) == -1))) \
1304 : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \
1305 && GET_CODE (IN) == MEM && TARGET_ARCH32 \
1306 && ! mem_min_alignment ((IN), 8)) \
1308 : (((TARGET_CM_MEDANY \
1309 && symbolic_operand ((IN), (MODE))) \
1310 || (TARGET_CM_EMBMEDANY \
1311 && text_segment_operand ((IN), (MODE)))) \
1316 /* On SPARC it is not possible to directly move data between
1317 GENERAL_REGS and FP_REGS. */
1318 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1319 (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2))
1321 /* Return the stack location to use for secondary memory needed reloads.
1322 We want to use the reserved location just below the frame pointer.
1323 However, we must ensure that there is a frame, so use assign_stack_local
1324 if the frame size is zero. */
1325 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
1326 (get_frame_size () == 0 \
1327 ? assign_stack_local (MODE, GET_MODE_SIZE (MODE), 0) \
1328 : gen_rtx_MEM (MODE, plus_constant (frame_pointer_rtx, \
1329 STARTING_FRAME_OFFSET)))
1331 /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9
1332 because the movsi and movsf patterns don't handle r/f moves.
1333 For v8 we copy the default definition. */
1334 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
1336 ? (GET_MODE_BITSIZE (MODE) < 32 \
1337 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
1339 : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \
1340 ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0) \
1343 /* Return the maximum number of consecutive registers
1344 needed to represent mode MODE in a register of class CLASS. */
1345 /* On SPARC, this is the size of MODE in words. */
1346 #define CLASS_MAX_NREGS(CLASS, MODE) \
1347 (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \
1348 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1350 /* Stack layout; function entry, exit and calling. */
1352 /* Define this if pushing a word on the stack
1353 makes the stack pointer a smaller address. */
1354 #define STACK_GROWS_DOWNWARD
1356 /* Define this if the nominal address of the stack frame
1357 is at the high-address end of the local variables;
1358 that is, each additional local variable allocated
1359 goes at a more negative offset in the frame. */
1360 #define FRAME_GROWS_DOWNWARD
1362 /* Offset within stack frame to start allocating local variables at.
1363 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1364 first local allocated. Otherwise, it is the offset to the BEGINNING
1365 of the first local allocated. */
1366 /* This allows space for one TFmode floating point value. */
1367 #define STARTING_FRAME_OFFSET \
1368 (TARGET_ARCH64 ? -16 \
1369 : (-SPARC_STACK_ALIGN (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)))
1371 /* If we generate an insn to push BYTES bytes,
1372 this says how many the stack pointer really advances by.
1373 On SPARC, don't define this because there are no push insns. */
1374 /* #define PUSH_ROUNDING(BYTES) */
1376 /* Offset of first parameter from the argument pointer register value.
1377 !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg
1378 even if this function isn't going to use it.
1379 v9: This is 128 for the ins and locals. */
1380 #define FIRST_PARM_OFFSET(FNDECL) \
1381 (TARGET_ARCH64 ? 16 * UNITS_PER_WORD : STRUCT_VALUE_OFFSET + UNITS_PER_WORD)
1383 /* Offset from the argument pointer register value to the CFA.
1384 This is different from FIRST_PARM_OFFSET because the register window
1385 comes between the CFA and the arguments. */
1386 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1388 /* When a parameter is passed in a register, stack space is still
1390 !v9: All 6 possible integer registers have backing store allocated.
1391 v9: Only space for the arguments passed is allocated. */
1392 /* ??? Ideally, we'd use zero here (as the minimum), but zero has special
1393 meaning to the backend. Further, we need to be able to detect if a
1394 varargs/unprototyped function is called, as they may want to spill more
1395 registers than we've provided space. Ugly, ugly. So for now we retain
1396 all 6 slots even for v9. */
1397 #define REG_PARM_STACK_SPACE(DECL) (6 * UNITS_PER_WORD)
1399 /* Definitions for register elimination. */
1401 #define ELIMINABLE_REGS \
1402 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1403 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM} }
1405 /* The way this is structured, we can't eliminate SFP in favor of SP
1406 if the frame pointer is required: we want to use the SFP->HFP elimination
1407 in that case. But the test in update_eliminables doesn't know we are
1408 assuming below that we only do the former elimination. */
1409 #define CAN_ELIMINATE(FROM, TO) \
1410 ((TO) == HARD_FRAME_POINTER_REGNUM || !FRAME_POINTER_REQUIRED)
1412 /* We always pretend that this is a leaf function because if it's not,
1413 there's no point in trying to eliminate the frame pointer. If it
1414 is a leaf function, we guessed right! */
1415 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1417 if ((TO) == STACK_POINTER_REGNUM) \
1418 (OFFSET) = sparc_compute_frame_size (get_frame_size (), 1); \
1421 (OFFSET) += SPARC_STACK_BIAS; \
1424 /* Keep the stack pointer constant throughout the function.
1425 This is both an optimization and a necessity: longjmp
1426 doesn't behave itself when the stack pointer moves within
1428 #define ACCUMULATE_OUTGOING_ARGS 1
1430 /* Value is the number of bytes of arguments automatically
1431 popped when returning from a subroutine call.
1432 FUNDECL is the declaration node of the function (as a tree),
1433 FUNTYPE is the data type of the function (as a tree),
1434 or for a library call it is an identifier node for the subroutine name.
1435 SIZE is the number of bytes of arguments passed on the stack. */
1437 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1439 /* Define this macro if the target machine has "register windows". This
1440 C expression returns the register number as seen by the called function
1441 corresponding to register number OUT as seen by the calling function.
1442 Return OUT if register number OUT is not an outbound register. */
1444 #define INCOMING_REGNO(OUT) \
1445 (((OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16)
1447 /* Define this macro if the target machine has "register windows". This
1448 C expression returns the register number as seen by the calling function
1449 corresponding to register number IN as seen by the called function.
1450 Return IN if register number IN is not an inbound register. */
1452 #define OUTGOING_REGNO(IN) \
1453 (((IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16)
1455 /* Define this macro if the target machine has register windows. This
1456 C expression returns true if the register is call-saved but is in the
1459 #define LOCAL_REGNO(REGNO) \
1460 ((REGNO) >= 16 && (REGNO) <= 31)
1462 /* Define how to find the value returned by a function.
1463 VALTYPE is the data type of the value (as a tree).
1464 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1465 otherwise, FUNC is 0. */
1467 /* On SPARC the value is found in the first "output" register. */
1469 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1470 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 1)
1472 /* But the called function leaves it in the first "input" register. */
1474 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
1475 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 0)
1477 /* Define how to find the value returned by a library function
1478 assuming the value has mode MODE. */
1480 #define LIBCALL_VALUE(MODE) \
1481 function_value (NULL_TREE, (MODE), 1)
1483 /* 1 if N is a possible register number for a function value
1484 as seen by the caller.
1485 On SPARC, the first "output" reg is used for integer values,
1486 and the first floating point register is used for floating point values. */
1488 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32)
1490 /* Define the size of space to allocate for the return value of an
1493 #define APPLY_RESULT_SIZE (TARGET_ARCH64 ? 24 : 16)
1495 /* 1 if N is a possible register number for function argument passing.
1496 On SPARC, these are the "output" registers. v9 also uses %f0-%f31. */
1498 #define FUNCTION_ARG_REGNO_P(N) \
1500 ? (((N) >= 8 && (N) <= 13) || ((N) >= 32 && (N) <= 63)) \
1501 : ((N) >= 8 && (N) <= 13))
1503 /* Define a data type for recording info about an argument list
1504 during the scan of that argument list. This data type should
1505 hold all necessary information about the function itself
1506 and about the args processed so far, enough to enable macros
1507 such as FUNCTION_ARG to determine where the next arg should go.
1509 On SPARC (!v9), this is a single integer, which is a number of words
1510 of arguments scanned so far (including the invisible argument,
1511 if any, which holds the structure-value-address).
1512 Thus 7 or more means all following args should go on the stack.
1514 For v9, we also need to know whether a prototype is present. */
1517 int words; /* number of words passed so far */
1518 int prototype_p; /* nonzero if a prototype is present */
1519 int libcall_p; /* nonzero if a library call */
1521 #define CUMULATIVE_ARGS struct sparc_args
1523 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1524 for a call to a function whose data type is FNTYPE.
1525 For a library call, FNTYPE is 0. */
1527 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1528 init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL));
1530 /* Update the data in CUM to advance over an argument
1531 of mode MODE and data type TYPE.
1532 TYPE is null for libcalls where that information may not be available. */
1534 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1535 function_arg_advance (& (CUM), (MODE), (TYPE), (NAMED))
1537 /* Determine where to put an argument to a function.
1538 Value is zero to push the argument on the stack,
1539 or a hard register in which to store the argument.
1541 MODE is the argument's machine mode.
1542 TYPE is the data type of the argument (as a tree).
1543 This is null for libcalls where that information may
1545 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1546 the preceding args and about the function being called.
1547 NAMED is nonzero if this argument is a named parameter
1548 (otherwise it is an extra parameter matching an ellipsis). */
1550 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1551 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 0)
1553 /* Define where a function finds its arguments.
1554 This is different from FUNCTION_ARG because of register windows. */
1556 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
1557 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 1)
1559 /* If defined, a C expression which determines whether, and in which direction,
1560 to pad out an argument with extra space. The value should be of type
1561 `enum direction': either `upward' to pad above the argument,
1562 `downward' to pad below, or `none' to inhibit padding. */
1564 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1565 function_arg_padding ((MODE), (TYPE))
1567 /* If defined, a C expression that gives the alignment boundary, in bits,
1568 of an argument with the specified mode and type. If it is not defined,
1569 PARM_BOUNDARY is used for all arguments.
1570 For sparc64, objects requiring 16 byte alignment are passed that way. */
1572 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1574 && (GET_MODE_ALIGNMENT (MODE) == 128 \
1575 || ((TYPE) && TYPE_ALIGN (TYPE) == 128))) \
1576 ? 128 : PARM_BOUNDARY)
1578 /* Define the information needed to generate branch and scc insns. This is
1579 stored from the compare operation. Note that we can't use "rtx" here
1580 since it hasn't been defined! */
1582 extern GTY(()) rtx sparc_compare_op0;
1583 extern GTY(()) rtx sparc_compare_op1;
1586 /* Generate the special assembly code needed to tell the assembler whatever
1587 it might need to know about the return value of a function.
1589 For SPARC assemblers, we need to output a .proc pseudo-op which conveys
1590 information to the assembler relating to peephole optimization (done in
1593 #define ASM_DECLARE_RESULT(FILE, RESULT) \
1594 fprintf ((FILE), "\t.proc\t0%lo\n", sparc_type_code (TREE_TYPE (RESULT)))
1596 /* Output the special assembly code needed to tell the assembler some
1597 register is used as global register variable.
1599 SPARC 64bit psABI declares registers %g2 and %g3 as application
1600 registers and %g6 and %g7 as OS registers. Any object using them
1601 should declare (for %g2/%g3 has to, for %g6/%g7 can) that it uses them
1602 and how they are used (scratch or some global variable).
1603 Linker will then refuse to link together objects which use those
1604 registers incompatibly.
1606 Unless the registers are used for scratch, two different global
1607 registers cannot be declared to the same name, so in the unlikely
1608 case of a global register variable occupying more than one register
1609 we prefix the second and following registers with .gnu.part1. etc. */
1611 extern GTY(()) char sparc_hard_reg_printed[8];
1613 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
1614 #define ASM_DECLARE_REGISTER_GLOBAL(FILE, DECL, REGNO, NAME) \
1616 if (TARGET_ARCH64) \
1618 int end = HARD_REGNO_NREGS ((REGNO), DECL_MODE (decl)) + (REGNO); \
1620 for (reg = (REGNO); reg < 8 && reg < end; reg++) \
1621 if ((reg & ~1) == 2 || (reg & ~1) == 6) \
1623 if (reg == (REGNO)) \
1624 fprintf ((FILE), "\t.register\t%%g%d, %s\n", reg, (NAME)); \
1626 fprintf ((FILE), "\t.register\t%%g%d, .gnu.part%d.%s\n", \
1627 reg, reg - (REGNO), (NAME)); \
1628 sparc_hard_reg_printed[reg] = 1; \
1635 /* Emit rtl for profiling. */
1636 #define PROFILE_HOOK(LABEL) sparc_profile_hook (LABEL)
1638 /* All the work done in PROFILE_HOOK, but still required. */
1639 #define FUNCTION_PROFILER(FILE, LABELNO) do { } while (0)
1641 /* Set the name of the mcount function for the system. */
1642 #define MCOUNT_FUNCTION "*mcount"
1644 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1645 the stack pointer does not matter. The value is tested only in
1646 functions that have frame pointers.
1647 No definition is equivalent to always zero. */
1649 #define EXIT_IGNORE_STACK \
1650 (get_frame_size () != 0 \
1651 || current_function_calls_alloca || current_function_outgoing_args_size)
1653 /* Define registers used by the epilogue and return instruction. */
1654 #define EPILOGUE_USES(REGNO) ((REGNO) == 31 \
1655 || (current_function_calls_eh_return && (REGNO) == 1))
1657 /* Length in units of the trampoline for entering a nested function. */
1659 #define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 32 : 16)
1661 #define TRAMPOLINE_ALIGNMENT 128 /* 16 bytes */
1663 /* Emit RTL insns to initialize the variable parts of a trampoline.
1664 FNADDR is an RTX for the address of the function's pure code.
1665 CXT is an RTX for the static chain value for the function. */
1667 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1668 if (TARGET_ARCH64) \
1669 sparc64_initialize_trampoline (TRAMP, FNADDR, CXT); \
1671 sparc_initialize_trampoline (TRAMP, FNADDR, CXT)
1673 /* Implement `va_start' for varargs and stdarg. */
1674 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
1675 sparc_va_start (valist, nextarg)
1677 /* Generate RTL to flush the register windows so as to make arbitrary frames
1679 #define SETUP_FRAME_ADDRESSES() \
1680 emit_insn (gen_flush_register_windows ())
1682 /* Given an rtx for the address of a frame,
1683 return an rtx for the address of the word in the frame
1684 that holds the dynamic chain--the previous frame's address. */
1685 #define DYNAMIC_CHAIN_ADDRESS(frame) \
1686 plus_constant (frame, 14 * UNITS_PER_WORD + SPARC_STACK_BIAS)
1688 /* The return address isn't on the stack, it is in a register, so we can't
1689 access it from the current frame pointer. We can access it from the
1690 previous frame pointer though by reading a value from the register window
1692 #define RETURN_ADDR_IN_PREVIOUS_FRAME
1694 /* This is the offset of the return address to the true next instruction to be
1695 executed for the current function. */
1696 #define RETURN_ADDR_OFFSET \
1697 (8 + 4 * (! TARGET_ARCH64 && current_function_returns_struct))
1699 /* The current return address is in %i7. The return address of anything
1700 farther back is in the register window save area at [%fp+60]. */
1701 /* ??? This ignores the fact that the actual return address is +8 for normal
1702 returns, and +12 for structure returns. */
1703 #define RETURN_ADDR_RTX(count, frame) \
1705 ? gen_rtx_REG (Pmode, 31) \
1706 : gen_rtx_MEM (Pmode, \
1707 memory_address (Pmode, plus_constant (frame, \
1708 15 * UNITS_PER_WORD \
1709 + SPARC_STACK_BIAS))))
1711 /* Before the prologue, the return address is %o7 + 8. OK, sometimes it's
1712 +12, but always using +8 is close enough for frame unwind purposes.
1713 Actually, just using %o7 is close enough for unwinding, but %o7+8
1714 is something you can return to. */
1715 #define INCOMING_RETURN_ADDR_RTX \
1716 plus_constant (gen_rtx_REG (word_mode, 15), 8)
1717 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (15)
1719 /* The offset from the incoming value of %sp to the top of the stack frame
1720 for the current function. On sparc64, we have to account for the stack
1722 #define INCOMING_FRAME_SP_OFFSET SPARC_STACK_BIAS
1724 /* Describe how we implement __builtin_eh_return. */
1725 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 24 : INVALID_REGNUM)
1726 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 1) /* %g1 */
1727 #define EH_RETURN_HANDLER_RTX gen_rtx_REG (Pmode, 31) /* %i7 */
1729 /* Select a format to encode pointers in exception handling data. CODE
1730 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
1731 true if the symbol may be affected by dynamic relocations.
1733 If assembler and linker properly support .uaword %r_disp32(foo),
1734 then use PC relative 32-bit relocations instead of absolute relocs
1735 for shared libraries. On sparc64, use pc relative 32-bit relocs even
1736 for binaries, to save memory.
1738 binutils 2.12 would emit a R_SPARC_DISP32 dynamic relocation if the
1739 symbol %r_disp32() is against was not local, but .hidden. In that
1740 case, we have to use DW_EH_PE_absptr for pic personality. */
1741 #ifdef HAVE_AS_SPARC_UA_PCREL
1742 #ifdef HAVE_AS_SPARC_UA_PCREL_HIDDEN
1743 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
1745 ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\
1746 : ((TARGET_ARCH64 && ! GLOBAL) \
1747 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \
1750 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
1752 ? (GLOBAL ? DW_EH_PE_absptr : (DW_EH_PE_pcrel | DW_EH_PE_sdata4)) \
1753 : ((TARGET_ARCH64 && ! GLOBAL) \
1754 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \
1758 /* Emit a PC-relative relocation. */
1759 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \
1761 fputs (integer_asm_op (SIZE, FALSE), FILE); \
1762 fprintf (FILE, "%%r_disp%d(", SIZE * 8); \
1763 assemble_name (FILE, LABEL); \
1764 fputc (')', FILE); \
1768 /* Addressing modes, and classification of registers for them. */
1770 /* Macros to check register numbers against specific register classes. */
1772 /* These assume that REGNO is a hard or pseudo reg number.
1773 They give nonzero only if REGNO is a hard reg of the suitable class
1774 or a pseudo reg currently allocated to a suitable hard reg.
1775 Since they use reg_renumber, they are safe only once reg_renumber
1776 has been allocated, which happens in local-alloc.c. */
1778 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1779 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < (unsigned)32 \
1780 || (REGNO) == FRAME_POINTER_REGNUM \
1781 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)
1783 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO)
1785 #define REGNO_OK_FOR_FP_P(REGNO) \
1786 (((unsigned) (REGNO) - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)) \
1787 || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)))
1788 #define REGNO_OK_FOR_CCFP_P(REGNO) \
1790 && (((unsigned) (REGNO) - 96 < (unsigned)4) \
1791 || ((unsigned) reg_renumber[REGNO] - 96 < (unsigned)4)))
1793 /* Now macros that check whether X is a register and also,
1794 strictly, whether it is in a specified class.
1796 These macros are specific to the SPARC, and may be used only
1797 in code for printing assembler insns and in conditions for
1798 define_optimization. */
1800 /* 1 if X is an fp register. */
1802 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1804 /* Is X, a REG, an in or global register? i.e. is regno 0..7 or 24..31 */
1805 #define IN_OR_GLOBAL_P(X) (REGNO (X) < 8 || (REGNO (X) >= 24 && REGNO (X) <= 31))
1807 /* Maximum number of registers that can appear in a valid memory address. */
1809 #define MAX_REGS_PER_ADDRESS 2
1811 /* Recognize any constant value that is a valid address.
1812 When PIC, we do not accept an address that would require a scratch reg
1813 to load into a register. */
1815 #define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1817 /* Define this, so that when PIC, reload won't try to reload invalid
1818 addresses which require two reload registers. */
1820 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
1822 /* Nonzero if the constant value X is a legitimate general operand.
1823 Anything can be made to work except floating point constants.
1824 If TARGET_VIS, 0.0 can be made to work as well. */
1826 #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X)
1828 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1829 and check its validity for a certain class.
1830 We have two alternate definitions for each of them.
1831 The usual definition accepts all pseudo regs; the other rejects
1832 them unless they have been allocated suitable hard regs.
1833 The symbol REG_OK_STRICT causes the latter definition to be used.
1835 Most source files want to accept pseudo regs in the hope that
1836 they will get allocated to the class that the insn wants them to be in.
1837 Source files for reload pass need to be strict.
1838 After reload, it makes no difference, since pseudo regs have
1839 been eliminated by then. */
1841 /* Optional extra constraints for this machine.
1843 'Q' handles floating point constants which can be moved into
1844 an integer register with a single sethi instruction.
1846 'R' handles floating point constants which can be moved into
1847 an integer register with a single mov instruction.
1849 'S' handles floating point constants which can be moved into
1850 an integer register using a high/lo_sum sequence.
1852 'T' handles memory addresses where the alignment is known to
1853 be at least 8 bytes.
1855 `U' handles all pseudo registers or a hard even numbered
1856 integer register, needed for ldd/std instructions.
1858 'W' handles the memory operand when moving operands in/out
1859 of 'e' constraint floating point registers.
1861 'Y' handles the zero vector constant. */
1863 #ifndef REG_OK_STRICT
1865 /* Nonzero if X is a hard reg that can be used as an index
1866 or if it is a pseudo reg. */
1867 #define REG_OK_FOR_INDEX_P(X) \
1869 || REGNO (X) == FRAME_POINTER_REGNUM \
1870 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1872 /* Nonzero if X is a hard reg that can be used as a base reg
1873 or if it is a pseudo reg. */
1874 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_INDEX_P (X)
1876 /* 'T', 'U' are for aligned memory loads which aren't needed for arch64.
1877 'W' is like 'T' but is assumed true on arch64.
1879 Remember to accept pseudo-registers for memory constraints if reload is
1882 #define EXTRA_CONSTRAINT(OP, C) \
1883 sparc_extra_constraint_check(OP, C, 0)
1887 /* Nonzero if X is a hard reg that can be used as an index. */
1888 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1889 /* Nonzero if X is a hard reg that can be used as a base reg. */
1890 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1892 #define EXTRA_CONSTRAINT(OP, C) \
1893 sparc_extra_constraint_check(OP, C, 1)
1897 /* Should gcc use [%reg+%lo(xx)+offset] addresses? */
1899 #ifdef HAVE_AS_OFFSETABLE_LO10
1900 #define USE_AS_OFFSETABLE_LO10 1
1902 #define USE_AS_OFFSETABLE_LO10 0
1905 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1906 that is a valid memory address for an instruction.
1907 The MODE argument is the machine mode for the MEM expression
1908 that wants to use this address.
1910 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
1911 ordinarily. This changes a bit when generating PIC.
1913 If you change this, execute "rm explow.o recog.o reload.o". */
1915 #define SYMBOLIC_CONST(X) symbolic_operand (X, VOIDmode)
1917 #define RTX_OK_FOR_BASE_P(X) \
1918 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1919 || (GET_CODE (X) == SUBREG \
1920 && GET_CODE (SUBREG_REG (X)) == REG \
1921 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
1923 #define RTX_OK_FOR_INDEX_P(X) \
1924 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
1925 || (GET_CODE (X) == SUBREG \
1926 && GET_CODE (SUBREG_REG (X)) == REG \
1927 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
1929 #define RTX_OK_FOR_OFFSET_P(X) \
1930 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000 - 8)
1932 #define RTX_OK_FOR_OLO10_P(X) \
1933 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0xc00 - 8)
1935 #ifdef REG_OK_STRICT
1936 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1938 if (legitimate_address_p (MODE, X, 1)) \
1942 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1944 if (legitimate_address_p (MODE, X, 0)) \
1949 /* Go to LABEL if ADDR (a legitimate address expression)
1950 has an effect that depends on the machine mode it is used for.
1956 is not equivalent to
1958 (mem:QI [%l7+a]) (mem:QI [%l7+a+1])
1960 because [%l7+a+1] is interpreted as the address of (a+1). */
1962 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1964 if (flag_pic == 1) \
1966 if (GET_CODE (ADDR) == PLUS) \
1968 rtx op0 = XEXP (ADDR, 0); \
1969 rtx op1 = XEXP (ADDR, 1); \
1970 if (op0 == pic_offset_table_rtx \
1971 && SYMBOLIC_CONST (op1)) \
1977 /* Try machine-dependent ways of modifying an illegitimate address
1978 to be legitimate. If we find one, return the new, valid address.
1979 This macro is used in only one place: `memory_address' in explow.c.
1981 OLDX is the address as it was before break_out_memory_refs was called.
1982 In some cases it is useful to look at this to decide what needs to be done.
1984 MODE and WIN are passed so that this macro can use
1985 GO_IF_LEGITIMATE_ADDRESS.
1987 It is always safe for this macro to do nothing. It exists to recognize
1988 opportunities to optimize the output. */
1990 /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
1991 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1993 (X) = legitimize_address (X, OLDX, MODE); \
1994 if (memory_address_p (MODE, X)) \
1998 /* Try a machine-dependent way of reloading an illegitimate address
1999 operand. If we find one, push the reload and jump to WIN. This
2000 macro is used in only one place: `find_reloads_address' in reload.c.
2002 For SPARC 32, we wish to handle addresses by splitting them into
2003 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
2004 This cuts the number of extra insns by one.
2006 Do nothing when generating PIC code and the address is a
2007 symbolic operand or requires a scratch register. */
2009 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2011 /* Decompose SImode constants into hi+lo_sum. We do have to \
2012 rerecognize what we produce, so be careful. */ \
2013 if (CONSTANT_P (X) \
2014 && (MODE != TFmode || TARGET_ARCH64) \
2015 && GET_MODE (X) == SImode \
2016 && GET_CODE (X) != LO_SUM && GET_CODE (X) != HIGH \
2018 && (symbolic_operand (X, Pmode) \
2019 || pic_address_needs_scratch (X))) \
2020 && sparc_cmodel <= CM_MEDLOW) \
2022 X = gen_rtx_LO_SUM (GET_MODE (X), \
2023 gen_rtx_HIGH (GET_MODE (X), X), X); \
2024 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
2025 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
2029 /* ??? 64-bit reloads. */ \
2032 /* Specify the machine mode that this machine uses
2033 for the index in the tablejump instruction. */
2034 /* If we ever implement any of the full models (such as CM_FULLANY),
2035 this has to be DImode in that case */
2036 #ifdef HAVE_GAS_SUBSECTION_ORDERING
2037 #define CASE_VECTOR_MODE \
2038 (! TARGET_PTR64 ? SImode : flag_pic ? SImode : TARGET_CM_MEDLOW ? SImode : DImode)
2040 /* If assembler does not have working .subsection -1, we use DImode for pic, as otherwise
2041 we have to sign extend which slows things down. */
2042 #define CASE_VECTOR_MODE \
2043 (! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode)
2046 /* Define this as 1 if `char' should by default be signed; else as 0. */
2047 #define DEFAULT_SIGNED_CHAR 1
2049 /* Max number of bytes we can move from memory to memory
2050 in one reasonably fast instruction. */
2053 /* If a memory-to-memory move would take MOVE_RATIO or more simple
2054 move-instruction pairs, we will do a movmem or libcall instead. */
2056 #define MOVE_RATIO (optimize_size ? 3 : 8)
2058 /* Define if operations between registers always perform the operation
2059 on the full register even if a narrower mode is specified. */
2060 #define WORD_REGISTER_OPERATIONS
2062 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2063 will either zero-extend or sign-extend. The value of this macro should
2064 be the code that says which one of the two operations is implicitly
2065 done, UNKNOWN if none. */
2066 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2068 /* Nonzero if access to memory by bytes is slow and undesirable.
2069 For RISC chips, it means that access to memory by bytes is no
2070 better than access by words when possible, so grab a whole word
2071 and maybe make use of that. */
2072 #define SLOW_BYTE_ACCESS 1
2074 /* Define this to be nonzero if shift instructions ignore all but the low-order
2076 #define SHIFT_COUNT_TRUNCATED 1
2078 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2079 is done just by pretending it is already truncated. */
2080 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2082 /* Specify the machine mode used for addresses. */
2083 #define Pmode (TARGET_ARCH64 ? DImode : SImode)
2085 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2086 return the mode to be used for the comparison. For floating-point,
2087 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2088 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2089 processing is needed. */
2090 #define SELECT_CC_MODE(OP,X,Y) select_cc_mode ((OP), (X), (Y))
2092 /* Return nonzero if MODE implies a floating point inequality can be
2093 reversed. For SPARC this is always true because we have a full
2094 compliment of ordered and unordered comparisons, but until generic
2095 code knows how to reverse it correctly we keep the old definition. */
2096 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode && (MODE) != CCFPmode)
2098 /* A function address in a call instruction for indexing purposes. */
2099 #define FUNCTION_MODE Pmode
2101 /* Define this if addresses of constant functions
2102 shouldn't be put through pseudo regs where they can be cse'd.
2103 Desirable on machines where ordinary constants are expensive
2104 but a CALL with constant address is cheap. */
2105 #define NO_FUNCTION_CSE
2107 /* alloca should avoid clobbering the old register save area. */
2108 #define SETJMP_VIA_SAVE_AREA
2110 /* The _Q_* comparison libcalls return booleans. */
2111 #define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) ((MODE) == TFmode)
2113 /* Assume by default that the _Qp_* 64-bit libcalls are implemented such
2114 that the inputs are fully consumed before the output memory is clobbered. */
2116 #define TARGET_BUGGY_QP_LIB 0
2118 /* Assume by default that we do not have the Solaris-specific conversion
2119 routines nor 64-bit integer multiply and divide routines. */
2121 #define SUN_CONVERSION_LIBFUNCS 0
2122 #define DITF_CONVERSION_LIBFUNCS 0
2123 #define SUN_INTEGER_MULTIPLY_64 0
2125 /* Compute extra cost of moving data between one register class
2127 #define GENERAL_OR_I64(C) ((C) == GENERAL_REGS || (C) == I64_REGS)
2128 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
2129 (((FP_REG_CLASS_P (CLASS1) && GENERAL_OR_I64 (CLASS2)) \
2130 || (GENERAL_OR_I64 (CLASS1) && FP_REG_CLASS_P (CLASS2)) \
2131 || (CLASS1) == FPCC_REGS || (CLASS2) == FPCC_REGS) \
2132 ? ((sparc_cpu == PROCESSOR_ULTRASPARC \
2133 || sparc_cpu == PROCESSOR_ULTRASPARC3) ? 12 : 6) : 2)
2135 /* Provide the cost of a branch. For pre-v9 processors we use
2136 a value of 3 to take into account the potential annulling of
2137 the delay slot (which ends up being a bubble in the pipeline slot)
2138 plus a cycle to take into consideration the instruction cache
2141 On v9 and later, which have branch prediction facilities, we set
2142 it to the depth of the pipeline as that is the cost of a
2143 mispredicted branch. */
2145 #define BRANCH_COST \
2146 ((sparc_cpu == PROCESSOR_V9 \
2147 || sparc_cpu == PROCESSOR_ULTRASPARC) \
2149 : (sparc_cpu == PROCESSOR_ULTRASPARC3 \
2152 #define PREFETCH_BLOCK \
2153 ((sparc_cpu == PROCESSOR_ULTRASPARC \
2154 || sparc_cpu == PROCESSOR_ULTRASPARC3) \
2157 #define SIMULTANEOUS_PREFETCHES \
2158 ((sparc_cpu == PROCESSOR_ULTRASPARC) \
2160 : (sparc_cpu == PROCESSOR_ULTRASPARC3 \
2163 /* Control the assembler format that we output. */
2165 /* A C string constant describing how to begin a comment in the target
2166 assembler language. The compiler assumes that the comment will end at
2167 the end of the line. */
2169 #define ASM_COMMENT_START "!"
2171 /* Output to assembler file text saying following lines
2172 may contain character constants, extra white space, comments, etc. */
2174 #define ASM_APP_ON ""
2176 /* Output to assembler file text saying following lines
2177 no longer contain unusual constructs. */
2179 #define ASM_APP_OFF ""
2181 /* How to refer to registers in assembler output.
2182 This sequence is indexed by compiler's hard-register-number (see above). */
2184 #define REGISTER_NAMES \
2185 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \
2186 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \
2187 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \
2188 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \
2189 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \
2190 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \
2191 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \
2192 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \
2193 "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \
2194 "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \
2195 "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \
2196 "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \
2197 "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc", "%sfp" }
2199 /* Define additional names for use in asm clobbers and asm declarations. */
2201 #define ADDITIONAL_REGISTER_NAMES \
2202 {{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}}
2204 /* On Sun 4, this limit is 2048. We use 1000 to be safe, since the length
2205 can run past this up to a continuation point. Once we used 1500, but
2206 a single entry in C++ can run more than 500 bytes, due to the length of
2207 mangled symbol names. dbxout.c should really be fixed to do
2208 continuations when they are actually needed instead of trying to
2210 #define DBX_CONTIN_LENGTH 1000
2212 /* This is how to output a command to make the user-level label named NAME
2213 defined for reference from other files. */
2215 /* Globalizing directive for a label. */
2216 #define GLOBAL_ASM_OP "\t.global "
2218 /* The prefix to add to user-visible assembler symbols. */
2220 #define USER_LABEL_PREFIX "_"
2222 /* This is how to store into the string LABEL
2223 the symbol_ref name of an internal numbered label where
2224 PREFIX is the class of label and NUM is the number within the class.
2225 This is suitable for output with `assemble_name'. */
2227 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2228 sprintf ((LABEL), "*%s%ld", (PREFIX), (long)(NUM))
2230 /* This is how we hook in and defer the case-vector until the end of
2232 #define ASM_OUTPUT_ADDR_VEC(LAB,VEC) \
2233 sparc_defer_case_vector ((LAB),(VEC), 0)
2235 #define ASM_OUTPUT_ADDR_DIFF_VEC(LAB,VEC) \
2236 sparc_defer_case_vector ((LAB),(VEC), 1)
2238 /* This is how to output an element of a case-vector that is absolute. */
2240 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2243 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
2244 if (CASE_VECTOR_MODE == SImode) \
2245 fprintf (FILE, "\t.word\t"); \
2247 fprintf (FILE, "\t.xword\t"); \
2248 assemble_name (FILE, label); \
2249 fputc ('\n', FILE); \
2252 /* This is how to output an element of a case-vector that is relative.
2253 (SPARC uses such vectors only when generating PIC.) */
2255 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2258 ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE)); \
2259 if (CASE_VECTOR_MODE == SImode) \
2260 fprintf (FILE, "\t.word\t"); \
2262 fprintf (FILE, "\t.xword\t"); \
2263 assemble_name (FILE, label); \
2264 ASM_GENERATE_INTERNAL_LABEL (label, "L", (REL)); \
2265 fputc ('-', FILE); \
2266 assemble_name (FILE, label); \
2267 fputc ('\n', FILE); \
2270 /* This is what to output before and after case-vector (both
2271 relative and absolute). If .subsection -1 works, we put case-vectors
2272 at the beginning of the current section. */
2274 #ifdef HAVE_GAS_SUBSECTION_ORDERING
2276 #define ASM_OUTPUT_ADDR_VEC_START(FILE) \
2277 fprintf(FILE, "\t.subsection\t-1\n")
2279 #define ASM_OUTPUT_ADDR_VEC_END(FILE) \
2280 fprintf(FILE, "\t.previous\n")
2284 /* This is how to output an assembler line
2285 that says to advance the location counter
2286 to a multiple of 2**LOG bytes. */
2288 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2290 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
2292 /* This is how to output an assembler line that says to advance
2293 the location counter to a multiple of 2**LOG bytes using the
2294 "nop" instruction as padding. */
2295 #define ASM_OUTPUT_ALIGN_WITH_NOP(FILE,LOG) \
2297 fprintf (FILE, "\t.align %d,0x1000000\n", (1<<(LOG)))
2299 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
2300 fprintf (FILE, "\t.skip "HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2302 /* This says how to output an assembler line
2303 to define a global common symbol. */
2305 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
2306 ( fputs ("\t.common ", (FILE)), \
2307 assemble_name ((FILE), (NAME)), \
2308 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\"\n", (SIZE)))
2310 /* This says how to output an assembler line to define a local common
2313 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \
2314 ( fputs ("\t.reserve ", (FILE)), \
2315 assemble_name ((FILE), (NAME)), \
2316 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\",%u\n", \
2317 (SIZE), ((ALIGNED) / BITS_PER_UNIT)))
2319 /* A C statement (sans semicolon) to output to the stdio stream
2320 FILE the assembler definition of uninitialized global DECL named
2321 NAME whose size is SIZE bytes and alignment is ALIGN bytes.
2322 Try to use asm_output_aligned_bss to implement this macro. */
2324 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2326 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \
2329 #define IDENT_ASM_OP "\t.ident\t"
2331 /* Output #ident as a .ident. */
2333 #define ASM_OUTPUT_IDENT(FILE, NAME) \
2334 fprintf (FILE, "%s\"%s\"\n", IDENT_ASM_OP, NAME);
2336 /* Prettify the assembly. */
2338 extern int sparc_indent_opcode;
2340 #define ASM_OUTPUT_OPCODE(FILE, PTR) \
2342 if (sparc_indent_opcode) \
2345 sparc_indent_opcode = 0; \
2349 /* Emit a dtp-relative reference to a TLS variable. */
2352 #define ASM_OUTPUT_DWARF_DTPREL(FILE, SIZE, X) \
2353 sparc_output_dwarf_dtprel (FILE, SIZE, X)
2356 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
2357 ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '(' \
2358 || (CHAR) == ')' || (CHAR) == '_' || (CHAR) == '&')
2360 /* Print operand X (an rtx) in assembler syntax to file FILE.
2361 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2362 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2364 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2366 /* Print a memory address as an operand to reference that memory location. */
2368 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2369 { register rtx base, index = 0; \
2371 register rtx addr = ADDR; \
2372 if (GET_CODE (addr) == REG) \
2373 fputs (reg_names[REGNO (addr)], FILE); \
2374 else if (GET_CODE (addr) == PLUS) \
2376 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
2377 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\
2378 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
2379 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\
2381 base = XEXP (addr, 0), index = XEXP (addr, 1); \
2382 if (GET_CODE (base) == LO_SUM) \
2384 gcc_assert (USE_AS_OFFSETABLE_LO10 \
2386 && ! TARGET_CM_MEDMID); \
2387 output_operand (XEXP (base, 0), 0); \
2388 fputs ("+%lo(", FILE); \
2389 output_address (XEXP (base, 1)); \
2390 fprintf (FILE, ")+%d", offset); \
2394 fputs (reg_names[REGNO (base)], FILE); \
2396 fprintf (FILE, "%+d", offset); \
2397 else if (GET_CODE (index) == REG) \
2398 fprintf (FILE, "+%s", reg_names[REGNO (index)]); \
2399 else if (GET_CODE (index) == SYMBOL_REF \
2400 || GET_CODE (index) == CONST) \
2401 fputc ('+', FILE), output_addr_const (FILE, index); \
2402 else gcc_unreachable (); \
2405 else if (GET_CODE (addr) == MINUS \
2406 && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \
2408 output_addr_const (FILE, XEXP (addr, 0)); \
2409 fputs ("-(", FILE); \
2410 output_addr_const (FILE, XEXP (addr, 1)); \
2411 fputs ("-.)", FILE); \
2413 else if (GET_CODE (addr) == LO_SUM) \
2415 output_operand (XEXP (addr, 0), 0); \
2416 if (TARGET_CM_MEDMID) \
2417 fputs ("+%l44(", FILE); \
2419 fputs ("+%lo(", FILE); \
2420 output_address (XEXP (addr, 1)); \
2421 fputc (')', FILE); \
2423 else if (flag_pic && GET_CODE (addr) == CONST \
2424 && GET_CODE (XEXP (addr, 0)) == MINUS \
2425 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \
2426 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \
2427 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \
2429 addr = XEXP (addr, 0); \
2430 output_addr_const (FILE, XEXP (addr, 0)); \
2431 /* Group the args of the second CONST in parenthesis. */ \
2432 fputs ("-(", FILE); \
2433 /* Skip past the second CONST--it does nothing for us. */\
2434 output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \
2435 /* Close the parenthesis. */ \
2436 fputc (')', FILE); \
2440 output_addr_const (FILE, addr); \
2445 #define TARGET_TLS 1
2447 #define TARGET_TLS 0
2449 #define TARGET_SUN_TLS TARGET_TLS
2450 #define TARGET_GNU_TLS 0
2452 /* Define the codes that are matched by predicates in sparc.c. */
2454 #define PREDICATE_CODES \
2455 {"reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2456 {"const1_operand", {CONST_INT}}, \
2457 {"fp_zero_operand", {CONST_DOUBLE}}, \
2458 {"fp_register_operand", {SUBREG, REG}}, \
2459 {"intreg_operand", {SUBREG, REG}}, \
2460 {"fcc_reg_operand", {REG}}, \
2461 {"fcc0_reg_operand", {REG}}, \
2462 {"icc_or_fcc_reg_operand", {REG}}, \
2463 {"call_operand", {MEM}}, \
2464 {"call_operand_address", {SYMBOL_REF, LABEL_REF, CONST, CONST_DOUBLE, \
2465 SUBREG, REG, PLUS, LO_SUM, CONST_INT}}, \
2466 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
2467 {"symbolic_memory_operand", {SUBREG, MEM}}, \
2468 {"label_ref_operand", {LABEL_REF}}, \
2469 {"sp64_medium_pic_operand", {CONST}}, \
2470 {"data_segment_operand", {SYMBOL_REF, PLUS, CONST}}, \
2471 {"text_segment_operand", {LABEL_REF, SYMBOL_REF, PLUS, CONST}}, \
2472 {"reg_or_nonsymb_mem_operand", {SUBREG, REG, MEM}}, \
2473 {"splittable_symbolic_memory_operand", {MEM}}, \
2474 {"splittable_immediate_memory_operand", {MEM}}, \
2475 {"eq_or_neq", {EQ, NE}}, \
2476 {"normal_comp_operator", {GE, GT, LE, LT, GTU, LEU}}, \
2477 {"noov_compare_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}}, \
2478 {"noov_compare64_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}}, \
2479 {"v9_regcmp_op", {EQ, NE, GE, LT, LE, GT}}, \
2480 {"extend_op", {SIGN_EXTEND, ZERO_EXTEND}}, \
2481 {"cc_arithop", {AND, IOR, XOR}}, \
2482 {"cc_arithopn", {AND, IOR}}, \
2483 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
2484 {"arith_add_operand", {SUBREG, REG, CONST_INT}}, \
2485 {"arith11_operand", {SUBREG, REG, CONST_INT}}, \
2486 {"arith10_operand", {SUBREG, REG, CONST_INT}}, \
2487 {"arith_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2488 {"arith_double_add_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2489 {"arith11_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2490 {"arith10_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2491 {"small_int", {CONST_INT}}, \
2492 {"small_int_or_double", {CONST_INT, CONST_DOUBLE}}, \
2493 {"uns_small_int", {CONST_INT}}, \
2494 {"uns_arith_operand", {SUBREG, REG, CONST_INT}}, \
2495 {"clobbered_register", {REG}}, \
2496 {"input_operand", {SUBREG, REG, CONST_INT, MEM, CONST}}, \
2497 {"compare_operand", {SUBREG, REG, ZERO_EXTRACT}}, \
2498 {"const64_operand", {CONST_INT, CONST_DOUBLE}}, \
2499 {"const64_high_operand", {CONST_INT, CONST_DOUBLE}}, \
2500 {"tgd_symbolic_operand", {SYMBOL_REF}}, \
2501 {"tld_symbolic_operand", {SYMBOL_REF}}, \
2502 {"tie_symbolic_operand", {SYMBOL_REF}}, \
2503 {"tle_symbolic_operand", {SYMBOL_REF}},
2505 /* The number of Pmode words for the setjmp buffer. */
2506 #define JMP_BUF_SIZE 12