1 /* Definitions of target machine for GNU compiler, for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1994, 1995, 1996, 1997, 1998, 1999
3 2000, 2001 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com).
5 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 /* Note that some other tm.h files include this one and then override
26 whatever definitions are necessary. */
28 /* Specify this in a cover file to provide bi-architecture (32/64) support. */
29 /* #define SPARC_BI_ARCH */
31 /* Macro used later in this file to determine default architecture. */
32 #define DEFAULT_ARCH32_P ((TARGET_DEFAULT & MASK_64BIT) == 0)
34 /* TARGET_ARCH{32,64} are the main macros to decide which of the two
35 architectures to compile for. We allow targets to choose compile time or
38 #if defined(__sparcv9) || defined(__arch64__)
39 #define TARGET_ARCH32 0
41 #define TARGET_ARCH32 1
45 #define TARGET_ARCH32 (! TARGET_64BIT)
47 #define TARGET_ARCH32 (DEFAULT_ARCH32_P)
48 #endif /* SPARC_BI_ARCH */
49 #endif /* IN_LIBGCC2 */
50 #define TARGET_ARCH64 (! TARGET_ARCH32)
52 /* Code model selection.
53 -mcmodel is used to select the v9 code model.
54 Different code models aren't supported for v7/8 code.
56 TARGET_CM_32: 32 bit address space, top 32 bits = 0,
57 pointers are 32 bits. Note that this isn't intended
60 TARGET_CM_MEDLOW: 32 bit address space, top 32 bits = 0,
61 avoid generating %uhi and %ulo terms,
64 TARGET_CM_MEDMID: 64 bit address space.
65 The executable must be in the low 16 TB of memory.
66 This corresponds to the low 44 bits, and the %[hml]44
67 relocs are used. The text segment has a maximum size
70 TARGET_CM_MEDANY: 64 bit address space.
71 The text and data segments have a maximum size of 31
72 bits and may be located anywhere. The maximum offset
73 from any instruction to the label _GLOBAL_OFFSET_TABLE_
76 TARGET_CM_EMBMEDANY: 64 bit address space.
77 The text and data segments have a maximum size of 31 bits
78 and may be located anywhere. Register %g4 contains
79 the start address of the data segment.
90 /* Value of -mcmodel specified by user. */
91 extern const char *sparc_cmodel_string;
93 extern enum cmodel sparc_cmodel;
95 /* V9 code model selection. */
96 #define TARGET_CM_MEDLOW (sparc_cmodel == CM_MEDLOW)
97 #define TARGET_CM_MEDMID (sparc_cmodel == CM_MEDMID)
98 #define TARGET_CM_MEDANY (sparc_cmodel == CM_MEDANY)
99 #define TARGET_CM_EMBMEDANY (sparc_cmodel == CM_EMBMEDANY)
101 #define SPARC_DEFAULT_CMODEL CM_32
103 /* This is call-clobbered in the normal ABI, but is reserved in the
104 home grown (aka upward compatible) embedded ABI. */
105 #define EMBMEDANY_BASE_REG "%g4"
107 /* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile,
108 and specified by the user via --with-cpu=foo.
109 This specifies the cpu implementation, not the architecture size. */
110 /* Note that TARGET_CPU_v9 is assumed to start the list of 64-bit
112 #define TARGET_CPU_sparc 0
113 #define TARGET_CPU_v7 0 /* alias for previous */
114 #define TARGET_CPU_sparclet 1
115 #define TARGET_CPU_sparclite 2
116 #define TARGET_CPU_v8 3 /* generic v8 implementation */
117 #define TARGET_CPU_supersparc 4
118 #define TARGET_CPU_hypersparc 5
119 #define TARGET_CPU_sparc86x 6
120 #define TARGET_CPU_sparclite86x 6
121 #define TARGET_CPU_v9 7 /* generic v9 implementation */
122 #define TARGET_CPU_sparcv9 7 /* alias */
123 #define TARGET_CPU_sparc64 7 /* alias */
124 #define TARGET_CPU_ultrasparc 8
126 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
127 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc
129 #define CPP_CPU32_DEFAULT_SPEC ""
130 #define ASM_CPU32_DEFAULT_SPEC ""
132 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9
133 /* ??? What does Sun's CC pass? */
134 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
135 /* ??? It's not clear how other assemblers will handle this, so by default
136 use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case
137 is handled in sol2.h. */
138 #define ASM_CPU64_DEFAULT_SPEC "-Av9"
140 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc
141 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
142 #define ASM_CPU64_DEFAULT_SPEC "-Av9a"
147 #define CPP_CPU64_DEFAULT_SPEC ""
148 #define ASM_CPU64_DEFAULT_SPEC ""
150 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc \
151 || TARGET_CPU_DEFAULT == TARGET_CPU_v8
152 #define CPP_CPU32_DEFAULT_SPEC ""
153 #define ASM_CPU32_DEFAULT_SPEC ""
156 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet
157 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclet__"
158 #define ASM_CPU32_DEFAULT_SPEC "-Asparclet"
161 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite
162 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite__"
163 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
166 #if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc
167 #define CPP_CPU32_DEFAULT_SPEC "-D__supersparc__ -D__sparc_v8__"
168 #define ASM_CPU32_DEFAULT_SPEC ""
171 #if TARGET_CPU_DEFAULT == TARGET_CPU_hypersparc
172 #define CPP_CPU32_DEFAULT_SPEC "-D__hypersparc__ -D__sparc_v8__"
173 #define ASM_CPU32_DEFAULT_SPEC ""
176 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite86x
177 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite86x__"
178 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
183 #if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC)
184 Unrecognized value in TARGET_CPU_DEFAULT.
189 #define CPP_CPU_DEFAULT_SPEC \
190 (DEFAULT_ARCH32_P ? "\
191 %{m64:" CPP_CPU64_DEFAULT_SPEC "} \
192 %{!m64:" CPP_CPU32_DEFAULT_SPEC "} \
194 %{m32:" CPP_CPU32_DEFAULT_SPEC "} \
195 %{!m32:" CPP_CPU64_DEFAULT_SPEC "} \
197 #define ASM_CPU_DEFAULT_SPEC \
198 (DEFAULT_ARCH32_P ? "\
199 %{m64:" ASM_CPU64_DEFAULT_SPEC "} \
200 %{!m64:" ASM_CPU32_DEFAULT_SPEC "} \
202 %{m32:" ASM_CPU32_DEFAULT_SPEC "} \
203 %{!m32:" ASM_CPU64_DEFAULT_SPEC "} \
206 #else /* !SPARC_BI_ARCH */
208 #define CPP_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? CPP_CPU32_DEFAULT_SPEC : CPP_CPU64_DEFAULT_SPEC)
209 #define ASM_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? ASM_CPU32_DEFAULT_SPEC : ASM_CPU64_DEFAULT_SPEC)
211 #endif /* !SPARC_BI_ARCH */
213 /* Names to predefine in the preprocessor for this target machine.
214 ??? It would be nice to not include any subtarget specific values here,
215 however there's no way to portably provide subtarget values to
216 CPP_PREFINES. Also, -D values in CPP_SUBTARGET_SPEC don't get turned into
217 foo, __foo and __foo__. */
219 #define CPP_PREDEFINES "-Dsparc -Dsun -Dunix -Asystem=unix -Asystem=bsd"
221 /* Define macros to distinguish architectures. */
223 /* Common CPP definitions used by CPP_SPEC amongst the various targets
224 for handling -mcpu=xxx switches. */
225 #define CPP_CPU_SPEC "\
227 %{msparclite:-D__sparclite__} \
228 %{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \
229 %{mv8:-D__sparc_v8__} \
230 %{msupersparc:-D__supersparc__ -D__sparc_v8__} \
231 %{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \
232 %{mcpu=sparclite:-D__sparclite__} \
233 %{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \
234 %{mcpu=v8:-D__sparc_v8__} \
235 %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \
236 %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \
237 %{mcpu=sparclite86x:-D__sparclite86x__} \
238 %{mcpu=v9:-D__sparc_v9__} \
239 %{mcpu=ultrasparc:-D__sparc_v9__} \
240 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \
243 /* ??? The GCC_NEW_VARARGS macro is now obsolete, because gcc always uses
244 the right varags.h file when bootstrapping. */
245 /* ??? It's not clear what value we want to use for -Acpu/machine for
246 sparc64 in 32 bit environments, so for now we only use `sparc64' in
247 64 bit environments. */
251 #define CPP_ARCH32_SPEC "-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int \
252 -D__GCC_NEW_VARARGS__ -Acpu=sparc -Amachine=sparc"
253 #define CPP_ARCH64_SPEC "-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int \
254 -D__arch64__ -Acpu=sparc64 -Amachine=sparc64"
258 #define CPP_ARCH32_SPEC "-D__GCC_NEW_VARARGS__ -Acpu=sparc -Amachine=sparc"
259 #define CPP_ARCH64_SPEC "-D__arch64__ -Acpu=sparc64 -Amachine=sparc64"
263 #define CPP_ARCH_DEFAULT_SPEC \
264 (DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC)
266 #define CPP_ARCH_SPEC "\
267 %{m32:%(cpp_arch32)} \
268 %{m64:%(cpp_arch64)} \
269 %{!m32:%{!m64:%(cpp_arch_default)}} \
272 /* Macros to distinguish endianness. */
273 #define CPP_ENDIAN_SPEC "\
274 %{mlittle-endian:-D__LITTLE_ENDIAN__} \
275 %{mlittle-endian-data:-D__LITTLE_ENDIAN_DATA__}"
277 /* Macros to distinguish the particular subtarget. */
278 #define CPP_SUBTARGET_SPEC ""
280 #define CPP_SPEC "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_subtarget)"
282 /* Prevent error on `-sun4' and `-target sun4' options. */
283 /* This used to translate -dalign to -malign, but that is no good
284 because it can't turn off the usual meaning of making debugging dumps. */
285 /* Translate old style -m<cpu> into new style -mcpu=<cpu>.
286 ??? Delete support for -m<cpu> for 2.9. */
289 %{sun4:} %{target:} \
290 %{mcypress:-mcpu=cypress} \
291 %{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \
292 %{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \
295 /* Override in target specific files. */
296 #define ASM_CPU_SPEC "\
297 %{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \
298 %{msparclite:-Asparclite} \
299 %{mf930:-Asparclite} %{mf934:-Asparclite} \
300 %{mcpu=sparclite:-Asparclite} \
301 %{mcpu=sparclite86x:-Asparclite} \
302 %{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \
303 %{mv8plus:-Av8plus} \
305 %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \
306 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_cpu_default)}}}}}}} \
309 /* Word size selection, among other things.
310 This is what GAS uses. Add %(asm_arch) to ASM_SPEC to enable. */
312 #define ASM_ARCH32_SPEC "-32"
313 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
314 #define ASM_ARCH64_SPEC "-64 -no-undeclared-regs"
316 #define ASM_ARCH64_SPEC "-64"
318 #define ASM_ARCH_DEFAULT_SPEC \
319 (DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC)
321 #define ASM_ARCH_SPEC "\
322 %{m32:%(asm_arch32)} \
323 %{m64:%(asm_arch64)} \
324 %{!m32:%{!m64:%(asm_arch_default)}} \
327 #ifdef HAVE_AS_RELAX_OPTION
328 #define ASM_RELAX_SPEC "%{!mno-relax:-relax}"
330 #define ASM_RELAX_SPEC ""
333 /* Special flags to the Sun-4 assembler when using pipe for input. */
336 %| %{R} %{!pg:%{!p:%{fpic:-k} %{fPIC:-k}}} %{keep-local-as-symbols:-L} \
337 %(asm_cpu) %(asm_relax)"
339 #define LIB_SPEC "%{!shared:%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} %{g:-lg}}"
341 /* Provide required defaults for linker -e and -d switches. */
344 "%{!shared:%{!nostdlib:%{!r*:%{!e*:-e start}}} -dc -dp} %{static:-Bstatic} \
345 %{assert*} %{shared:%{!mimpure-text:-assert pure-text}}"
347 /* This macro defines names of additional specifications to put in the specs
348 that can be used in various specifications like CC1_SPEC. Its definition
349 is an initializer with a subgrouping for each command option.
351 Each subgrouping contains a string constant, that defines the
352 specification name, and a string constant that used by the GNU CC driver
355 Do not define this macro if it does not need to do anything. */
357 #define EXTRA_SPECS \
358 { "cpp_cpu", CPP_CPU_SPEC }, \
359 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
360 { "cpp_arch32", CPP_ARCH32_SPEC }, \
361 { "cpp_arch64", CPP_ARCH64_SPEC }, \
362 { "cpp_arch_default", CPP_ARCH_DEFAULT_SPEC },\
363 { "cpp_arch", CPP_ARCH_SPEC }, \
364 { "cpp_endian", CPP_ENDIAN_SPEC }, \
365 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \
366 { "asm_cpu", ASM_CPU_SPEC }, \
367 { "asm_cpu_default", ASM_CPU_DEFAULT_SPEC }, \
368 { "asm_arch32", ASM_ARCH32_SPEC }, \
369 { "asm_arch64", ASM_ARCH64_SPEC }, \
370 { "asm_relax", ASM_RELAX_SPEC }, \
371 { "asm_arch_default", ASM_ARCH_DEFAULT_SPEC },\
372 { "asm_arch", ASM_ARCH_SPEC }, \
373 SUBTARGET_EXTRA_SPECS
375 #define SUBTARGET_EXTRA_SPECS
378 #define NO_BUILTIN_PTRDIFF_TYPE
379 #define NO_BUILTIN_SIZE_TYPE
381 #define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int")
382 #define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int")
384 /* ??? This should be 32 bits for v9 but what can we do? */
385 #define WCHAR_TYPE "short unsigned int"
386 #define WCHAR_TYPE_SIZE 16
387 #define MAX_WCHAR_TYPE_SIZE 16
389 /* Show we can debug even without a frame pointer. */
390 #define CAN_DEBUG_WITHOUT_FP
392 /* To make profiling work with -f{pic,PIC}, we need to emit the profiling
393 code into the rtl. Also, if we are profiling, we cannot eliminate
394 the frame pointer (because the return address will get smashed). */
396 #define OVERRIDE_OPTIONS \
398 if (profile_flag || profile_block_flag || profile_arc_flag) \
402 const char *pic_string = (flag_pic == 1) ? "-fpic" : "-fPIC";\
403 warning ("%s and profiling conflict: disabling %s", \
404 pic_string, pic_string); \
407 flag_omit_frame_pointer = 0; \
409 sparc_override_options (); \
410 SUBTARGET_OVERRIDE_OPTIONS; \
413 /* This is meant to be redefined in the host dependent files. */
414 #define SUBTARGET_OVERRIDE_OPTIONS
416 /* These compiler options take an argument. We ignore -target for now. */
418 #define WORD_SWITCH_TAKES_ARG(STR) \
419 (DEFAULT_WORD_SWITCH_TAKES_ARG (STR) \
420 || !strcmp (STR, "target") || !strcmp (STR, "assert"))
422 /* Print subsidiary information on the compiler version in use. */
424 #define TARGET_VERSION fprintf (stderr, " (sparc)");
426 /* Generate DBX debugging information. */
428 #define DBX_DEBUGGING_INFO
430 /* Run-time compilation parameters selecting different hardware subsets. */
432 extern int target_flags;
434 /* Nonzero if we should generate code to use the fpu. */
436 #define TARGET_FPU (target_flags & MASK_FPU)
438 /* Nonzero if we should use FUNCTION_EPILOGUE. Otherwise, we
439 use fast return insns, but lose some generality. */
440 #define MASK_EPILOGUE 2
441 #define TARGET_EPILOGUE (target_flags & MASK_EPILOGUE)
443 /* Nonzero if we should assume that double pointers might be unaligned.
444 This can happen when linking gcc compiled code with other compilers,
445 because the ABI only guarantees 4 byte alignment. */
446 #define MASK_UNALIGNED_DOUBLES 4
447 #define TARGET_UNALIGNED_DOUBLES (target_flags & MASK_UNALIGNED_DOUBLES)
449 /* Nonzero means that we should generate code for a v8 sparc. */
451 #define TARGET_V8 (target_flags & MASK_V8)
453 /* Nonzero means that we should generate code for a sparclite.
454 This enables the sparclite specific instructions, but does not affect
455 whether FPU instructions are emitted. */
456 #define MASK_SPARCLITE 0x10
457 #define TARGET_SPARCLITE (target_flags & MASK_SPARCLITE)
459 /* Nonzero if we're compiling for the sparclet. */
460 #define MASK_SPARCLET 0x20
461 #define TARGET_SPARCLET (target_flags & MASK_SPARCLET)
463 /* Nonzero if we're compiling for v9 sparc.
464 Note that v9's can run in 32 bit mode so this doesn't necessarily mean
465 the word size is 64. */
467 #define TARGET_V9 (target_flags & MASK_V9)
469 /* Non-zero to generate code that uses the instructions deprecated in
470 the v9 architecture. This option only applies to v9 systems. */
471 /* ??? This isn't user selectable yet. It's used to enable such insns
472 on 32 bit v9 systems and for the moment they're permanently disabled
473 on 64 bit v9 systems. */
474 #define MASK_DEPRECATED_V8_INSNS 0x80
475 #define TARGET_DEPRECATED_V8_INSNS (target_flags & MASK_DEPRECATED_V8_INSNS)
477 /* Mask of all CPU selection flags. */
479 (MASK_V8 + MASK_SPARCLITE + MASK_SPARCLET + MASK_V9 + MASK_DEPRECATED_V8_INSNS)
481 /* Non-zero means don't pass `-assert pure-text' to the linker. */
482 #define MASK_IMPURE_TEXT 0x100
483 #define TARGET_IMPURE_TEXT (target_flags & MASK_IMPURE_TEXT)
485 /* Nonzero means that we should generate code using a flat register window
486 model, i.e. no save/restore instructions are generated, which is
487 compatible with normal sparc code.
488 The frame pointer is %i7 instead of %fp. */
489 #define MASK_FLAT 0x200
490 #define TARGET_FLAT (target_flags & MASK_FLAT)
492 /* Nonzero means use the registers that the Sparc ABI reserves for
493 application software. This must be the default to coincide with the
494 setting in FIXED_REGISTERS. */
495 #define MASK_APP_REGS 0x400
496 #define TARGET_APP_REGS (target_flags & MASK_APP_REGS)
498 /* Option to select how quad word floating point is implemented.
499 When TARGET_HARD_QUAD is true, we use the hardware quad instructions.
500 Otherwise, we use the SPARC ABI quad library functions. */
501 #define MASK_HARD_QUAD 0x800
502 #define TARGET_HARD_QUAD (target_flags & MASK_HARD_QUAD)
504 /* Non-zero on little-endian machines. */
505 /* ??? Little endian support currently only exists for sparclet-aout and
506 sparc64-elf configurations. May eventually want to expand the support
507 to all targets, but for now it's kept local to only those two. */
508 #define MASK_LITTLE_ENDIAN 0x1000
509 #define TARGET_LITTLE_ENDIAN (target_flags & MASK_LITTLE_ENDIAN)
511 /* 0x2000, 0x4000 are unused */
513 /* Nonzero if pointers are 64 bits.
514 At the moment it must follow architecture size flag. */
515 #define MASK_PTR64 0x8000
516 #define TARGET_PTR64 (target_flags & MASK_PTR64)
518 /* Nonzero if generating code to run in a 64 bit environment.
519 This is intended to only be used by TARGET_ARCH{32,64} as they are the
520 mechanism used to control compile time or run time selection. */
521 #define MASK_64BIT 0x10000
522 #define TARGET_64BIT (target_flags & MASK_64BIT)
524 /* 0x20000,0x40000 unused */
526 /* Non-zero means use a stack bias of 2047. Stack offsets are obtained by
527 adding 2047 to %sp. This option is for v9 only and is the default. */
528 #define MASK_STACK_BIAS 0x80000
529 #define TARGET_STACK_BIAS (target_flags & MASK_STACK_BIAS)
531 /* 0x100000,0x200000 unused */
533 /* Non-zero means -m{,no-}fpu was passed on the command line. */
534 #define MASK_FPU_SET 0x400000
535 #define TARGET_FPU_SET (target_flags & MASK_FPU_SET)
537 /* Use the UltraSPARC Visual Instruction Set extensions. */
538 #define MASK_VIS 0x1000000
539 #define TARGET_VIS (target_flags & MASK_VIS)
541 /* Compile for Solaris V8+. 32 bit Solaris preserves the high bits of
542 the current out and global registers and Linux 2.2+ as well. */
543 #define MASK_V8PLUS 0x2000000
544 #define TARGET_V8PLUS (target_flags & MASK_V8PLUS)
546 /* Force a the fastest alignment on structures to take advantage of
548 #define MASK_FASTER_STRUCTS 0x4000000
549 #define TARGET_FASTER_STRUCTS (target_flags & MASK_FASTER_STRUCTS)
551 /* Use IEEE quad long double. */
552 #define MASK_LONG_DOUBLE_128 0x8000000
553 #define TARGET_LONG_DOUBLE_128 (target_flags & MASK_LONG_DOUBLE_128)
555 /* TARGET_HARD_MUL: Use hardware multiply instructions but not %y.
556 TARGET_HARD_MUL32: Use hardware multiply instructions with rd %y
557 to get high 32 bits. False in V8+ or V9 because multiply stores
558 a 64 bit result in a register. */
560 #define TARGET_HARD_MUL32 \
561 ((TARGET_V8 || TARGET_SPARCLITE \
562 || TARGET_SPARCLET || TARGET_DEPRECATED_V8_INSNS) \
563 && ! TARGET_V8PLUS && TARGET_ARCH32)
565 #define TARGET_HARD_MUL \
566 (TARGET_V8 || TARGET_SPARCLITE || TARGET_SPARCLET \
567 || TARGET_DEPRECATED_V8_INSNS || TARGET_V8PLUS)
570 /* Macro to define tables used to set the flags.
571 This is a list in braces of pairs in braces,
572 each pair being { "NAME", VALUE }
573 where VALUE is the bits to set or minus the bits to clear.
574 An empty string NAME is used to identify the default VALUE. */
576 #define TARGET_SWITCHES \
577 { {"fpu", MASK_FPU | MASK_FPU_SET, \
578 N_("Use hardware fp") }, \
579 {"no-fpu", -MASK_FPU, \
580 N_("Do not use hardware fp") }, \
581 {"no-fpu", MASK_FPU_SET, NULL, }, \
582 {"hard-float", MASK_FPU | MASK_FPU_SET, \
583 N_("Use hardware fp") }, \
584 {"soft-float", -MASK_FPU, \
585 N_("Do not use hardware fp") }, \
586 {"soft-float", MASK_FPU_SET, NULL }, \
587 {"epilogue", MASK_EPILOGUE, \
588 N_("Use FUNCTION_EPILOGUE") }, \
589 {"no-epilogue", -MASK_EPILOGUE, \
590 N_("Do not use FUNCTION_EPILOGUE") }, \
591 {"unaligned-doubles", MASK_UNALIGNED_DOUBLES, \
592 N_("Assume possible double misalignment") }, \
593 {"no-unaligned-doubles", -MASK_UNALIGNED_DOUBLES, \
594 N_("Assume all doubles are aligned") }, \
595 {"impure-text", MASK_IMPURE_TEXT, \
596 N_("Pass -assert pure-text to linker") }, \
597 {"no-impure-text", -MASK_IMPURE_TEXT, \
598 N_("Do not pass -assert pure-text to linker") }, \
599 {"flat", MASK_FLAT, \
600 N_("Use flat register window model") }, \
601 {"no-flat", -MASK_FLAT, \
602 N_("Do not use flat register window model") }, \
603 {"app-regs", MASK_APP_REGS, \
604 N_("Use ABI reserved registers") }, \
605 {"no-app-regs", -MASK_APP_REGS, \
606 N_("Do not use ABI reserved registers") }, \
607 {"hard-quad-float", MASK_HARD_QUAD, \
608 N_("Use hardware quad fp instructions") }, \
609 {"soft-quad-float", -MASK_HARD_QUAD, \
610 N_("Do not use hardware quad fp instructions") }, \
611 {"v8plus", MASK_V8PLUS, \
612 N_("Compile for v8plus ABI") }, \
613 {"no-v8plus", -MASK_V8PLUS, \
614 N_("Do not compile for v8plus ABI") }, \
616 N_("Utilize Visual Instruction Set") }, \
617 {"no-vis", -MASK_VIS, \
618 N_("Do not utilize Visual Instruction Set") }, \
619 /* ??? These are deprecated, coerced to -mcpu=. Delete in 2.9. */ \
621 N_("Optimize for Cypress processors") }, \
623 N_("Optimize for SparcLite processors") }, \
625 N_("Optimize for F930 processors") }, \
627 N_("Optimize for F934 processors") }, \
629 N_("Use V8 Sparc ISA") }, \
631 N_("Optimize for SuperSparc processors") }, \
632 /* End of deprecated options. */ \
633 {"ptr64", MASK_PTR64, \
634 N_("Pointers are 64-bit") }, \
635 {"ptr32", -MASK_PTR64, \
636 N_("Pointers are 32-bit") }, \
637 {"32", -MASK_64BIT, \
638 N_("Use 32-bit ABI") }, \
640 N_("Use 64-bit ABI") }, \
641 {"stack-bias", MASK_STACK_BIAS, \
642 N_("Use stack bias") }, \
643 {"no-stack-bias", -MASK_STACK_BIAS, \
644 N_("Do not use stack bias") }, \
645 {"faster-structs", MASK_FASTER_STRUCTS, \
646 N_("Use structs on stronger alignment for double-word copies") }, \
647 {"no-faster-structs", -MASK_FASTER_STRUCTS, \
648 N_("Do not use structs on stronger alignment for double-word copies") }, \
650 N_("Optimize tail call instructions in assembler and linker") }, \
652 N_("Do not optimize tail call instructions in assembler or linker") }, \
654 { "", TARGET_DEFAULT, ""}}
656 /* MASK_APP_REGS must always be the default because that's what
657 FIXED_REGISTERS is set to and -ffixed- is processed before
658 CONDITIONAL_REGISTER_USAGE is called (where we process -mno-app-regs). */
659 #define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU)
661 /* This is meant to be redefined in target specific files. */
662 #define SUBTARGET_SWITCHES
665 These must match the values for the cpu attribute in sparc.md. */
666 enum processor_type {
670 PROCESSOR_SUPERSPARC,
674 PROCESSOR_HYPERSPARC,
675 PROCESSOR_SPARCLITE86X,
682 /* This is set from -m{cpu,tune}=xxx. */
683 extern enum processor_type sparc_cpu;
685 /* Recast the cpu class to be the cpu attribute.
686 Every file includes us, but not every file includes insn-attr.h. */
687 #define sparc_cpu_attr ((enum attr_cpu) sparc_cpu)
689 /* This macro is similar to `TARGET_SWITCHES' but defines names of
690 command options that have values. Its definition is an
691 initializer with a subgrouping for each command option.
693 Each subgrouping contains a string constant, that defines the
694 fixed part of the option name, and the address of a variable.
695 The variable, type `char *', is set to the variable part of the
696 given option if the fixed part matches. The actual option name
697 is made by appending `-m' to the specified name.
699 Here is an example which defines `-mshort-data-NUMBER'. If the
700 given option is `-mshort-data-512', the variable `m88k_short_data'
701 will be set to the string `"512"'.
703 extern char *m88k_short_data;
704 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
706 #define TARGET_OPTIONS \
708 { "cpu=", &sparc_select[1].string, \
709 N_("Use features of and schedule code for given CPU") }, \
710 { "tune=", &sparc_select[2].string, \
711 N_("Schedule code for given CPU") }, \
712 { "cmodel=", &sparc_cmodel_string, \
713 N_("Use given Sparc code model") }, \
717 /* This is meant to be redefined in target specific files. */
718 #define SUBTARGET_OPTIONS
720 /* sparc_select[0] is reserved for the default cpu. */
721 struct sparc_cpu_select
729 extern struct sparc_cpu_select sparc_select[];
731 /* target machine storage layout */
733 /* Define for cross-compilation to a sparc target with no TFmode from a host
734 with a different float format (e.g. VAX). */
735 #define REAL_ARITHMETIC
737 /* Define this if most significant bit is lowest numbered
738 in instructions that operate on numbered bit-fields. */
739 #define BITS_BIG_ENDIAN 1
741 /* Define this if most significant byte of a word is the lowest numbered. */
742 #define BYTES_BIG_ENDIAN 1
744 /* Define this if most significant word of a multiword number is the lowest
746 #define WORDS_BIG_ENDIAN 1
748 /* Define this to set the endianness to use in libgcc2.c, which can
749 not depend on target_flags. */
750 #if defined (__LITTLE_ENDIAN__) || defined(__LITTLE_ENDIAN_DATA__)
751 #define LIBGCC2_WORDS_BIG_ENDIAN 0
753 #define LIBGCC2_WORDS_BIG_ENDIAN 1
756 /* number of bits in an addressable storage unit */
757 #define BITS_PER_UNIT 8
759 /* Width in bits of a "word", which is the contents of a machine register.
760 Note that this is not necessarily the width of data type `int';
761 if using 16-bit ints on a 68000, this would still be 32.
762 But on a machine with 16-bit registers, this would be 16. */
763 #define BITS_PER_WORD (TARGET_ARCH64 ? 64 : 32)
764 #define MAX_BITS_PER_WORD 64
766 /* Width of a word, in units (bytes). */
767 #define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4)
768 #define MIN_UNITS_PER_WORD 4
770 /* Now define the sizes of the C data types. */
772 #define SHORT_TYPE_SIZE 16
773 #define INT_TYPE_SIZE 32
774 #define LONG_TYPE_SIZE (TARGET_ARCH64 ? 64 : 32)
775 #define LONG_LONG_TYPE_SIZE 64
776 #define FLOAT_TYPE_SIZE 32
777 #define DOUBLE_TYPE_SIZE 64
780 #define MAX_LONG_TYPE_SIZE 64
784 /* ??? This does not work in SunOS 4.x, so it is not enabled here.
785 Instead, it is enabled in sol2.h, because it does work under Solaris. */
786 /* Define for support of TFmode long double and REAL_ARITHMETIC.
787 Sparc ABI says that long double is 4 words. */
788 #define LONG_DOUBLE_TYPE_SIZE 128
791 /* Width in bits of a pointer.
792 See also the macro `Pmode' defined below. */
793 #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32)
795 /* If we have to extend pointers (only when TARGET_ARCH64 and not
796 TARGET_PTR64), we want to do it unsigned. This macro does nothing
797 if ptr_mode and Pmode are the same. */
798 #define POINTERS_EXTEND_UNSIGNED 1
800 /* A macro to update MODE and UNSIGNEDP when an object whose type
801 is TYPE and which has the specified mode and signedness is to be
802 stored in a register. This macro is only called when TYPE is a
804 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
806 && GET_MODE_CLASS (MODE) == MODE_INT \
807 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
810 /* Define this macro if the promotion described by PROMOTE_MODE
811 should also be done for outgoing function arguments. */
812 /* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op
813 for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test
815 #define PROMOTE_FUNCTION_ARGS
817 /* Define this macro if the promotion described by PROMOTE_MODE
818 should also be done for the return value of functions.
819 If this macro is defined, FUNCTION_VALUE must perform the same
820 promotions done by PROMOTE_MODE. */
821 /* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op
822 for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test
824 #define PROMOTE_FUNCTION_RETURN
826 /* Define this macro if the promotion described by PROMOTE_MODE
827 should _only_ be performed for outgoing function arguments or
828 function return values, as specified by PROMOTE_FUNCTION_ARGS
829 and PROMOTE_FUNCTION_RETURN, respectively. */
830 /* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op
831 for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test
832 for this value. For TARGET_ARCH64 we need it, as we don't have instructions
833 for arithmetic operations which do zero/sign extension at the same time,
834 so without this we end up with a srl/sra after every assignment to an
835 user variable, which means very very bad code. */
836 #define PROMOTE_FOR_CALL_ONLY
838 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
839 #define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
841 /* Boundary (in *bits*) on which stack pointer should be aligned. */
842 #define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64)
844 /* ALIGN FRAMES on double word boundaries */
846 #define SPARC_STACK_ALIGN(LOC) \
847 (TARGET_ARCH64 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7))
849 /* Allocation boundary (in *bits*) for the code of a function. */
850 #define FUNCTION_BOUNDARY 32
852 /* Alignment of field after `int : 0' in a structure. */
853 #define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
855 /* Every structure's size must be a multiple of this. */
856 #define STRUCTURE_SIZE_BOUNDARY 8
858 /* A bitfield declared as `int' forces `int' alignment for the struct. */
859 #define PCC_BITFIELD_TYPE_MATTERS 1
861 /* No data type wants to be aligned rounder than this. */
862 #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64)
864 /* The best alignment to use in cases where we have a choice. */
865 #define FASTEST_ALIGNMENT 64
867 /* Define this macro as an expression for the alignment of a structure
868 (given by STRUCT as a tree node) if the alignment computed in the
869 usual way is COMPUTED and the alignment explicitly specified was
872 The default is to use SPECIFIED if it is larger; otherwise, use
873 the smaller of COMPUTED and `BIGGEST_ALIGNMENT' */
874 #define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \
875 (TARGET_FASTER_STRUCTS ? \
876 ((TREE_CODE (STRUCT) == RECORD_TYPE \
877 || TREE_CODE (STRUCT) == UNION_TYPE \
878 || TREE_CODE (STRUCT) == QUAL_UNION_TYPE) \
879 && TYPE_FIELDS (STRUCT) != 0 \
880 ? MAX (MAX ((COMPUTED), (SPECIFIED)), BIGGEST_ALIGNMENT) \
881 : MAX ((COMPUTED), (SPECIFIED))) \
882 : MAX ((COMPUTED), (SPECIFIED)))
884 /* Make strings word-aligned so strcpy from constants will be faster. */
885 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
886 ((TREE_CODE (EXP) == STRING_CST \
887 && (ALIGN) < FASTEST_ALIGNMENT) \
888 ? FASTEST_ALIGNMENT : (ALIGN))
890 /* Make arrays of chars word-aligned for the same reasons. */
891 #define DATA_ALIGNMENT(TYPE, ALIGN) \
892 (TREE_CODE (TYPE) == ARRAY_TYPE \
893 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
894 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
896 /* Set this nonzero if move instructions will actually fail to work
897 when given unaligned data. */
898 #define STRICT_ALIGNMENT 1
900 /* Things that must be doubleword aligned cannot go in the text section,
901 because the linker fails to align the text section enough!
902 Put them in the data section. This macro is only used in this file. */
903 #define MAX_TEXT_ALIGN 32
905 /* This forces all variables and constants to the data section when PIC.
906 This is because the SunOS 4 shared library scheme thinks everything in
907 text is a function, and patches the address to point to a loader stub. */
908 /* This is defined to zero for every system which doesn't use the a.out object
910 #ifndef SUNOS4_SHARED_LIBRARIES
911 #define SUNOS4_SHARED_LIBRARIES 0
914 /* This is defined differently for v9 in a cover file. */
915 #define SELECT_SECTION(T,RELOC) \
917 if (TREE_CODE (T) == VAR_DECL) \
919 if (TREE_READONLY (T) && ! TREE_SIDE_EFFECTS (T) \
920 && DECL_INITIAL (T) \
921 && (DECL_INITIAL (T) == error_mark_node \
922 || TREE_CONSTANT (DECL_INITIAL (T))) \
923 && DECL_ALIGN (T) <= MAX_TEXT_ALIGN \
924 && ! (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES))) \
929 else if (TREE_CODE (T) == CONSTRUCTOR) \
931 if (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES)) \
934 else if (TREE_CODE_CLASS (TREE_CODE (T)) == 'c') \
936 if ((TREE_CODE (T) == STRING_CST && flag_writable_strings) \
937 || TYPE_ALIGN (TREE_TYPE (T)) > MAX_TEXT_ALIGN \
938 || (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES))) \
945 /* Use text section for a constant
946 unless we need more alignment than that offers. */
947 /* This is defined differently for v9 in a cover file. */
948 #define SELECT_RTX_SECTION(MODE, X) \
950 if (GET_MODE_BITSIZE (MODE) <= MAX_TEXT_ALIGN \
951 && ! (flag_pic && (symbolic_operand ((X), (MODE)) || SUNOS4_SHARED_LIBRARIES))) \
957 /* Standard register usage. */
959 /* Number of actual hardware registers.
960 The hardware registers are assigned numbers for the compiler
961 from 0 to just below FIRST_PSEUDO_REGISTER.
962 All registers that the compiler knows about must be given numbers,
963 even those that are not normally considered general registers.
965 SPARC has 32 integer registers and 32 floating point registers.
966 64 bit SPARC has 32 additional fp regs, but the odd numbered ones are not
967 accessible. We still account for them to simplify register computations
968 (eg: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so
970 Register 100 is used as the integer condition code register. */
972 #define FIRST_PSEUDO_REGISTER 101
974 #define SPARC_FIRST_FP_REG 32
975 /* Additional V9 fp regs. */
976 #define SPARC_FIRST_V9_FP_REG 64
977 #define SPARC_LAST_V9_FP_REG 95
978 /* V9 %fcc[0123]. V8 uses (figuratively) %fcc0. */
979 #define SPARC_FIRST_V9_FCC_REG 96
980 #define SPARC_LAST_V9_FCC_REG 99
982 #define SPARC_FCC_REG 96
983 /* Integer CC reg. We don't distinguish %icc from %xcc. */
984 #define SPARC_ICC_REG 100
986 /* Nonzero if REGNO is an fp reg. */
987 #define SPARC_FP_REG_P(REGNO) \
988 ((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG)
990 /* Argument passing regs. */
991 #define SPARC_OUTGOING_INT_ARG_FIRST 8
992 #define SPARC_INCOMING_INT_ARG_FIRST (TARGET_FLAT ? 8 : 24)
993 #define SPARC_FP_ARG_FIRST 32
995 /* 1 for registers that have pervasive standard uses
996 and are not available for the register allocator.
999 g1 is free to use as temporary.
1000 g2-g4 are reserved for applications. Gcc normally uses them as
1001 temporaries, but this can be disabled via the -mno-app-regs option.
1002 g5 through g7 are reserved for the operating system.
1005 g1,g5 are free to use as temporaries, and are free to use between calls
1006 if the call is to an external function via the PLT.
1007 g4 is free to use as a temporary in the non-embedded case.
1008 g4 is reserved in the embedded case.
1009 g2-g3 are reserved for applications. Gcc normally uses them as
1010 temporaries, but this can be disabled via the -mno-app-regs option.
1011 g6-g7 are reserved for the operating system (or application in
1013 ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must
1014 currently be a fixed register until this pattern is rewritten.
1015 Register 1 is also used when restoring call-preserved registers in large
1018 Registers fixed in arch32 and not arch64 (or vice-versa) are marked in
1019 CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-.
1022 #define FIXED_REGISTERS \
1023 {1, 0, 2, 2, 2, 2, 1, 1, \
1024 0, 0, 0, 0, 0, 0, 1, 0, \
1025 0, 0, 0, 0, 0, 0, 0, 0, \
1026 0, 0, 0, 0, 0, 0, 1, 1, \
1028 0, 0, 0, 0, 0, 0, 0, 0, \
1029 0, 0, 0, 0, 0, 0, 0, 0, \
1030 0, 0, 0, 0, 0, 0, 0, 0, \
1031 0, 0, 0, 0, 0, 0, 0, 0, \
1033 0, 0, 0, 0, 0, 0, 0, 0, \
1034 0, 0, 0, 0, 0, 0, 0, 0, \
1035 0, 0, 0, 0, 0, 0, 0, 0, \
1036 0, 0, 0, 0, 0, 0, 0, 0, \
1040 /* 1 for registers not available across function calls.
1041 These must include the FIXED_REGISTERS and also any
1042 registers that can be used without being saved.
1043 The latter must include the registers where values are returned
1044 and the register where structure-value addresses are passed.
1045 Aside from that, you can include as many other registers as you like. */
1047 #define CALL_USED_REGISTERS \
1048 {1, 1, 1, 1, 1, 1, 1, 1, \
1049 1, 1, 1, 1, 1, 1, 1, 1, \
1050 0, 0, 0, 0, 0, 0, 0, 0, \
1051 0, 0, 0, 0, 0, 0, 1, 1, \
1053 1, 1, 1, 1, 1, 1, 1, 1, \
1054 1, 1, 1, 1, 1, 1, 1, 1, \
1055 1, 1, 1, 1, 1, 1, 1, 1, \
1056 1, 1, 1, 1, 1, 1, 1, 1, \
1058 1, 1, 1, 1, 1, 1, 1, 1, \
1059 1, 1, 1, 1, 1, 1, 1, 1, \
1060 1, 1, 1, 1, 1, 1, 1, 1, \
1061 1, 1, 1, 1, 1, 1, 1, 1, \
1065 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
1066 they won't be allocated. */
1068 #define CONDITIONAL_REGISTER_USAGE \
1073 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
1074 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
1076 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */ \
1077 /* then honour it. */ \
1078 if (TARGET_ARCH32 && fixed_regs[5]) \
1079 fixed_regs[5] = 1; \
1080 else if (TARGET_ARCH64 && fixed_regs[5] == 2) \
1081 fixed_regs[5] = 0; \
1085 for (regno = SPARC_FIRST_V9_FP_REG; \
1086 regno <= SPARC_LAST_V9_FP_REG; \
1088 fixed_regs[regno] = 1; \
1089 /* %fcc0 is used by v8 and v9. */ \
1090 for (regno = SPARC_FIRST_V9_FCC_REG + 1; \
1091 regno <= SPARC_LAST_V9_FCC_REG; \
1093 fixed_regs[regno] = 1; \
1098 for (regno = 32; regno < SPARC_LAST_V9_FCC_REG; regno++) \
1099 fixed_regs[regno] = 1; \
1101 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */ \
1102 /* then honour it. Likewise with g3 and g4. */ \
1103 if (fixed_regs[2] == 2) \
1104 fixed_regs[2] = ! TARGET_APP_REGS; \
1105 if (fixed_regs[3] == 2) \
1106 fixed_regs[3] = ! TARGET_APP_REGS; \
1107 if (TARGET_ARCH32 && fixed_regs[4] == 2) \
1108 fixed_regs[4] = ! TARGET_APP_REGS; \
1109 else if (TARGET_CM_EMBMEDANY) \
1110 fixed_regs[4] = 1; \
1111 else if (fixed_regs[4] == 2) \
1112 fixed_regs[4] = 0; \
1115 /* Let the compiler believe the frame pointer is still \
1116 %fp, but output it as %i7. */ \
1117 fixed_regs[31] = 1; \
1118 reg_names[FRAME_POINTER_REGNUM] = "%i7"; \
1119 /* Disable leaf functions */ \
1120 memset (sparc_leaf_regs, 0, FIRST_PSEUDO_REGISTER); \
1122 if (profile_block_flag) \
1124 /* %g1 and %g2 (sparc32) resp. %g4 (sparc64) must be \
1125 fixed, because BLOCK_PROFILER uses them. */ \
1126 fixed_regs[1] = 1; \
1127 fixed_regs[TARGET_ARCH64 ? 4 : 2] = 1; \
1132 /* Return number of consecutive hard regs needed starting at reg REGNO
1133 to hold something of mode MODE.
1134 This is ordinarily the length in words of a value of mode MODE
1135 but can be less for certain modes in special long registers.
1137 On SPARC, ordinary registers hold 32 bits worth;
1138 this means both integer and floating point registers.
1139 On v9, integer regs hold 64 bits worth; floating point regs hold
1140 32 bits worth (this includes the new fp regs as even the odd ones are
1141 included in the hard register count). */
1143 #define HARD_REGNO_NREGS(REGNO, MODE) \
1146 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \
1147 : (GET_MODE_SIZE (MODE) + 3) / 4) \
1148 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1150 /* A subreg in 64 bit mode will have the wrong offset for a floating point
1151 register. The least significant part is at offset 1, compared to 0 for
1152 integer registers. This only applies when FMODE is a larger mode.
1153 We also need to handle a special case of TF-->DF conversions. */
1154 #define ALTER_HARD_SUBREG(TMODE, WORD, FMODE, REGNO) \
1156 && (REGNO) >= SPARC_FIRST_FP_REG \
1157 && (REGNO) <= SPARC_LAST_V9_FP_REG \
1158 && (TMODE) == SImode \
1159 && !((FMODE) == QImode || (FMODE) == HImode) \
1161 : ((TMODE) == DFmode && (FMODE) == TFmode) \
1162 ? ((REGNO) + ((WORD) * 2)) \
1163 : ((REGNO) + (WORD)))
1165 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
1166 See sparc.c for how we initialize this. */
1167 extern int *hard_regno_mode_classes;
1168 extern int sparc_mode_class[];
1169 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1170 ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0)
1172 /* Value is 1 if it is a good idea to tie two pseudo registers
1173 when one has mode MODE1 and one has mode MODE2.
1174 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1175 for any hard reg, then this must be 0 for correct output.
1177 For V9: SFmode can't be combined with other float modes, because they can't
1178 be allocated to the %d registers. Also, DFmode won't fit in odd %f
1179 registers, but SFmode will. */
1180 #define MODES_TIEABLE_P(MODE1, MODE2) \
1181 ((MODE1) == (MODE2) \
1182 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
1184 || (GET_MODE_CLASS (MODE1) != MODE_FLOAT \
1185 || (MODE1 != SFmode && MODE2 != SFmode)))))
1187 /* Specify the registers used for certain standard purposes.
1188 The values of these macros are register numbers. */
1190 /* SPARC pc isn't overloaded on a register that the compiler knows about. */
1191 /* #define PC_REGNUM */
1193 /* Register to use for pushing function arguments. */
1194 #define STACK_POINTER_REGNUM 14
1196 /* Actual top-of-stack address is 92/176 greater than the contents of the
1197 stack pointer register for !v9/v9. That is:
1198 - !v9: 64 bytes for the in and local registers, 4 bytes for structure return
1199 address, and 6*4 bytes for the 6 register parameters.
1200 - v9: 128 bytes for the in and local registers + 6*8 bytes for the integer
1202 #define STACK_POINTER_OFFSET FIRST_PARM_OFFSET(0)
1204 /* The stack bias (amount by which the hardware register is offset by). */
1205 #define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0)
1207 /* Is stack biased? */
1208 #define STACK_BIAS SPARC_STACK_BIAS
1210 /* Base register for access to local variables of the function. */
1211 #define FRAME_POINTER_REGNUM 30
1214 /* Register that is used for the return address for the flat model. */
1215 #define RETURN_ADDR_REGNUM 15
1218 /* Value should be nonzero if functions must have frame pointers.
1219 Zero means the frame pointer need not be set up (and parms
1220 may be accessed via the stack pointer) in functions that seem suitable.
1221 This is computed in `reload', in reload1.c.
1222 Used in flow.c, global.c, and reload1.c.
1224 Being a non-leaf function does not mean a frame pointer is needed in the
1225 flat window model. However, the debugger won't be able to backtrace through
1227 #define FRAME_POINTER_REQUIRED \
1228 (TARGET_FLAT ? (current_function_calls_alloca || current_function_varargs \
1229 || !leaf_function_p ()) \
1230 : ! (leaf_function_p () && only_leaf_regs_used ()))
1232 /* C statement to store the difference between the frame pointer
1233 and the stack pointer values immediately after the function prologue.
1235 Note, we always pretend that this is a leaf function because if
1236 it's not, there's no point in trying to eliminate the
1237 frame pointer. If it is a leaf function, we guessed right! */
1238 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
1239 ((VAR) = (TARGET_FLAT ? sparc_flat_compute_frame_size (get_frame_size ()) \
1240 : compute_frame_size (get_frame_size (), 1)))
1242 /* Base register for access to arguments of the function. */
1243 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM
1245 /* Register in which static-chain is passed to a function. This must
1246 not be a register used by the prologue. */
1247 #define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2)
1249 /* Register which holds offset table for position-independent
1252 #define PIC_OFFSET_TABLE_REGNUM 23
1254 /* Pick a default value we can notice from override_options:
1256 v9: Default is off. */
1258 #define DEFAULT_PCC_STRUCT_RETURN -1
1260 /* Sparc ABI says that quad-precision floats and all structures are returned
1262 For v9: unions <= 32 bytes in size are returned in int regs,
1263 structures up to 32 bytes are returned in int and fp regs. */
1265 #define RETURN_IN_MEMORY(TYPE) \
1267 ? (TYPE_MODE (TYPE) == BLKmode \
1268 || TYPE_MODE (TYPE) == TFmode \
1269 || TYPE_MODE (TYPE) == TCmode) \
1270 : (TYPE_MODE (TYPE) == BLKmode \
1271 && int_size_in_bytes (TYPE) > 32))
1273 /* Functions which return large structures get the address
1274 to place the wanted value at offset 64 from the frame.
1275 Must reserve 64 bytes for the in and local registers.
1276 v9: Functions which return large structures get the address to place the
1277 wanted value from an invisible first argument. */
1278 /* Used only in other #defines in this file. */
1279 #define STRUCT_VALUE_OFFSET 64
1281 #define STRUCT_VALUE \
1284 : gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, \
1285 STRUCT_VALUE_OFFSET)))
1287 #define STRUCT_VALUE_INCOMING \
1290 : gen_rtx_MEM (Pmode, plus_constant (frame_pointer_rtx, \
1291 STRUCT_VALUE_OFFSET)))
1293 /* Define the classes of registers for register constraints in the
1294 machine description. Also define ranges of constants.
1296 One of the classes must always be named ALL_REGS and include all hard regs.
1297 If there is more than one class, another class must be named NO_REGS
1298 and contain no registers.
1300 The name GENERAL_REGS must be the name of a class (or an alias for
1301 another name such as ALL_REGS). This is the class of registers
1302 that is allowed by "g" or "r" in a register constraint.
1303 Also, registers outside this class are allocated only when
1304 instructions express preferences for them.
1306 The classes must be numbered in nondecreasing order; that is,
1307 a larger-numbered class must never be contained completely
1308 in a smaller-numbered class.
1310 For any two classes, it is very desirable that there be another
1311 class that represents their union. */
1313 /* The SPARC has various kinds of registers: general, floating point,
1314 and condition codes [well, it has others as well, but none that we
1315 care directly about].
1317 For v9 we must distinguish between the upper and lower floating point
1318 registers because the upper ones can't hold SFmode values.
1319 HARD_REGNO_MODE_OK won't help here because reload assumes that register(s)
1320 satisfying a group need for a class will also satisfy a single need for
1321 that class. EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp
1324 It is important that one class contains all the general and all the standard
1325 fp regs. Otherwise find_reg() won't properly allocate int regs for moves,
1326 because reg_class_record() will bias the selection in favor of fp regs,
1327 because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS,
1328 because FP_REGS > GENERAL_REGS.
1330 It is also important that one class contain all the general and all the
1331 fp regs. Otherwise when spilling a DFmode reg, it may be from EXTRA_FP_REGS
1332 but find_reloads() may use class GENERAL_OR_FP_REGS. This will cause
1333 allocate_reload_reg() to bypass it causing an abort because the compiler
1334 thinks it doesn't have a spill reg when in fact it does.
1336 v9 also has 4 floating point condition code registers. Since we don't
1337 have a class that is the union of FPCC_REGS with either of the others,
1338 it is important that it appear first. Otherwise the compiler will die
1339 trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its
1342 It is important that SPARC_ICC_REG have class NO_REGS. Otherwise combine
1343 may try to use it to hold an SImode value. See register_operand.
1344 ??? Should %fcc[0123] be handled similarly?
1347 enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS,
1348 EXTRA_FP_REGS, GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS,
1349 ALL_REGS, LIM_REG_CLASSES };
1351 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1353 /* Give names of register classes as strings for dump file. */
1355 #define REG_CLASS_NAMES \
1356 { "NO_REGS", "FPCC_REGS", "I64_REGS", "GENERAL_REGS", "FP_REGS", \
1357 "EXTRA_FP_REGS", "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", \
1360 /* Define which registers fit in which classes.
1361 This is an initializer for a vector of HARD_REG_SET
1362 of length N_REG_CLASSES. */
1364 #define REG_CLASS_CONTENTS \
1365 {{0, 0, 0, 0}, {0, 0, 0, 0xf}, {0xffff, 0, 0, 0}, \
1366 {-1, 0, 0, 0}, {0, -1, 0, 0}, {0, -1, -1, 0}, \
1367 {-1, -1, 0, 0}, {-1, -1, -1, 0}, {-1, -1, -1, 0x1f}}
1369 /* The same information, inverted:
1370 Return the class number of the smallest class containing
1371 reg number REGNO. This could be a conditional expression
1372 or could index an array. */
1374 extern enum reg_class sparc_regno_reg_class[];
1376 #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)]
1378 /* This is the order in which to allocate registers normally.
1380 We put %f0/%f1 last among the float registers, so as to make it more
1381 likely that a pseudo-register which dies in the float return register
1382 will get allocated to the float return register, thus saving a move
1383 instruction at the end of the function. */
1385 #define REG_ALLOC_ORDER \
1386 { 8, 9, 10, 11, 12, 13, 2, 3, \
1387 15, 16, 17, 18, 19, 20, 21, 22, \
1388 23, 24, 25, 26, 27, 28, 29, 31, \
1389 34, 35, 36, 37, 38, 39, /* %f2-%f7 */ \
1390 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \
1391 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \
1392 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \
1393 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \
1394 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \
1395 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \
1396 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \
1397 32, 33, /* %f0,%f1 */ \
1398 96, 97, 98, 99, 100, /* %fcc0-3, %icc */ \
1399 1, 4, 5, 6, 7, 0, 14, 30}
1401 /* This is the order in which to allocate registers for
1402 leaf functions. If all registers can fit in the "gi" registers,
1403 then we have the possibility of having a leaf function. */
1405 #define REG_LEAF_ALLOC_ORDER \
1406 { 2, 3, 24, 25, 26, 27, 28, 29, \
1408 15, 8, 9, 10, 11, 12, 13, \
1409 16, 17, 18, 19, 20, 21, 22, 23, \
1410 34, 35, 36, 37, 38, 39, \
1411 40, 41, 42, 43, 44, 45, 46, 47, \
1412 48, 49, 50, 51, 52, 53, 54, 55, \
1413 56, 57, 58, 59, 60, 61, 62, 63, \
1414 64, 65, 66, 67, 68, 69, 70, 71, \
1415 72, 73, 74, 75, 76, 77, 78, 79, \
1416 80, 81, 82, 83, 84, 85, 86, 87, \
1417 88, 89, 90, 91, 92, 93, 94, 95, \
1419 96, 97, 98, 99, 100, \
1422 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
1424 extern char sparc_leaf_regs[];
1425 #define LEAF_REGISTERS sparc_leaf_regs
1427 extern char leaf_reg_remap[];
1428 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO])
1430 /* The class value for index registers, and the one for base regs. */
1431 #define INDEX_REG_CLASS GENERAL_REGS
1432 #define BASE_REG_CLASS GENERAL_REGS
1434 /* Local macro to handle the two v9 classes of FP regs. */
1435 #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS)
1437 /* Get reg_class from a letter such as appears in the machine description.
1438 In the not-v9 case, coerce v9's 'e' class to 'f', so we can use 'e' in the
1439 .md file for v8 and v9.
1440 'd' and 'b' are used for single and double precision VIS operations,
1442 'h' is used for V8+ 64 bit global and out registers. */
1444 #define REG_CLASS_FROM_LETTER(C) \
1446 ? ((C) == 'f' ? FP_REGS \
1447 : (C) == 'e' ? EXTRA_FP_REGS \
1448 : (C) == 'c' ? FPCC_REGS \
1449 : ((C) == 'd' && TARGET_VIS) ? FP_REGS\
1450 : ((C) == 'b' && TARGET_VIS) ? EXTRA_FP_REGS\
1451 : ((C) == 'h' && TARGET_V8PLUS) ? I64_REGS\
1453 : ((C) == 'f' ? FP_REGS \
1454 : (C) == 'e' ? FP_REGS \
1455 : (C) == 'c' ? FPCC_REGS \
1458 /* The letters I, J, K, L and M in a register constraint string
1459 can be used to stand for particular ranges of immediate operands.
1460 This macro defines what the ranges are.
1461 C is the letter, and VALUE is a constant value.
1462 Return 1 if VALUE is in the range specified by C.
1464 `I' is used for the range of constants an insn can actually contain.
1465 `J' is used for the range which is just zero (since that is R0).
1466 `K' is used for constants which can be loaded with a single sethi insn.
1467 `L' is used for the range of constants supported by the movcc insns.
1468 `M' is used for the range of constants supported by the movrcc insns. */
1470 #define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400)
1471 #define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800)
1472 #define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000)
1473 /* 10 and 11 bit immediates are only used for a few specific insns.
1474 SMALL_INT is used throughout the port so we continue to use it. */
1475 #define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X)))
1476 /* 13 bit immediate, considering only the low 32 bits */
1477 #define SMALL_INT32(X) (SPARC_SIMM13_P ((int)INTVAL (X) & 0xffffffff))
1478 #define SPARC_SETHI_P(X) \
1479 (((unsigned HOST_WIDE_INT) (X) & \
1480 (TARGET_ARCH64 ? ~(unsigned HOST_WIDE_INT) 0xfffffc00 : 0x3ff)) == 0)
1482 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1483 ((C) == 'I' ? SPARC_SIMM13_P (VALUE) \
1484 : (C) == 'J' ? (VALUE) == 0 \
1485 : (C) == 'K' ? SPARC_SETHI_P (VALUE) \
1486 : (C) == 'L' ? SPARC_SIMM11_P (VALUE) \
1487 : (C) == 'M' ? SPARC_SIMM10_P (VALUE) \
1490 /* Similar, but for floating constants, and defining letters G and H.
1491 Here VALUE is the CONST_DOUBLE rtx itself. */
1493 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1494 ((C) == 'G' ? fp_zero_operand (VALUE, GET_MODE (VALUE)) \
1495 : (C) == 'H' ? arith_double_operand (VALUE, DImode) \
1498 /* Given an rtx X being reloaded into a reg required to be
1499 in class CLASS, return the class of reg to actually use.
1500 In general this is just CLASS; but on some machines
1501 in some cases it is preferable to use a more restrictive class. */
1502 /* - We can't load constants into FP registers.
1503 - We can't load FP constants into integer registers when soft-float,
1504 because there is no soft-float pattern with a r/F constraint.
1505 - We can't load FP constants into integer registers for TFmode unless
1506 it is 0.0L, because there is no movtf pattern with a r/F constraint.
1507 - Try and reload integer constants (symbolic or otherwise) back into
1508 registers directly, rather than having them dumped to memory. */
1510 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1512 ? ((FP_REG_CLASS_P (CLASS) \
1513 || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1515 || (GET_MODE (X) == TFmode \
1516 && ! fp_zero_operand (X, TFmode))) \
1518 : (!FP_REG_CLASS_P (CLASS) \
1519 && GET_MODE_CLASS (GET_MODE (X)) == MODE_INT) \
1524 /* Return the register class of a scratch register needed to load IN into
1525 a register of class CLASS in MODE.
1527 We need a temporary when loading/storing a HImode/QImode value
1528 between memory and the FPU registers. This can happen when combine puts
1529 a paradoxical subreg in a float/fix conversion insn. */
1531 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1532 ((FP_REG_CLASS_P (CLASS) \
1533 && ((MODE) == HImode || (MODE) == QImode) \
1534 && (GET_CODE (IN) == MEM \
1535 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1536 && true_regnum (IN) == -1))) \
1538 : (((TARGET_CM_MEDANY \
1539 && symbolic_operand ((IN), (MODE))) \
1540 || (TARGET_CM_EMBMEDANY \
1541 && text_segment_operand ((IN), (MODE)))) \
1546 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1547 ((FP_REG_CLASS_P (CLASS) \
1548 && ((MODE) == HImode || (MODE) == QImode) \
1549 && (GET_CODE (IN) == MEM \
1550 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1551 && true_regnum (IN) == -1))) \
1553 : (((TARGET_CM_MEDANY \
1554 && symbolic_operand ((IN), (MODE))) \
1555 || (TARGET_CM_EMBMEDANY \
1556 && text_segment_operand ((IN), (MODE)))) \
1561 /* On SPARC it is not possible to directly move data between
1562 GENERAL_REGS and FP_REGS. */
1563 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1564 (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2))
1566 /* Return the stack location to use for secondary memory needed reloads.
1567 We want to use the reserved location just below the frame pointer.
1568 However, we must ensure that there is a frame, so use assign_stack_local
1569 if the frame size is zero. */
1570 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
1571 (get_frame_size () == 0 \
1572 ? assign_stack_local (MODE, GET_MODE_SIZE (MODE), 0) \
1573 : gen_rtx_MEM (MODE, plus_constant (frame_pointer_rtx, \
1574 STARTING_FRAME_OFFSET)))
1576 /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9
1577 because the movsi and movsf patterns don't handle r/f moves.
1578 For v8 we copy the default definition. */
1579 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
1581 ? (GET_MODE_BITSIZE (MODE) < 32 \
1582 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
1584 : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \
1585 ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0) \
1588 /* Return the maximum number of consecutive registers
1589 needed to represent mode MODE in a register of class CLASS. */
1590 /* On SPARC, this is the size of MODE in words. */
1591 #define CLASS_MAX_NREGS(CLASS, MODE) \
1592 (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \
1593 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1595 /* Stack layout; function entry, exit and calling. */
1597 /* Define the number of register that can hold parameters.
1598 This macro is only used in other macro definitions below and in sparc.c.
1599 MODE is the mode of the argument.
1600 !v9: All args are passed in %o0-%o5.
1601 v9: %o0-%o5 and %f0-%f31 are cumulatively used to pass values.
1602 See the description in sparc.c. */
1603 #define NPARM_REGS(MODE) \
1605 ? (GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 6) \
1608 /* Define this if pushing a word on the stack
1609 makes the stack pointer a smaller address. */
1610 #define STACK_GROWS_DOWNWARD
1612 /* Define this if the nominal address of the stack frame
1613 is at the high-address end of the local variables;
1614 that is, each additional local variable allocated
1615 goes at a more negative offset in the frame. */
1616 #define FRAME_GROWS_DOWNWARD
1618 /* Offset within stack frame to start allocating local variables at.
1619 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1620 first local allocated. Otherwise, it is the offset to the BEGINNING
1621 of the first local allocated. */
1622 /* This allows space for one TFmode floating point value. */
1623 #define STARTING_FRAME_OFFSET \
1624 (TARGET_ARCH64 ? (SPARC_STACK_BIAS - 16) \
1625 : (-SPARC_STACK_ALIGN (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)))
1627 /* If we generate an insn to push BYTES bytes,
1628 this says how many the stack pointer really advances by.
1629 On SPARC, don't define this because there are no push insns. */
1630 /* #define PUSH_ROUNDING(BYTES) */
1632 /* Offset of first parameter from the argument pointer register value.
1633 !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg
1634 even if this function isn't going to use it.
1635 v9: This is 128 for the ins and locals. */
1636 #define FIRST_PARM_OFFSET(FNDECL) \
1637 (TARGET_ARCH64 ? (SPARC_STACK_BIAS + 16 * UNITS_PER_WORD) \
1638 : (STRUCT_VALUE_OFFSET + UNITS_PER_WORD))
1640 /* Offset from the argument pointer register value to the CFA.
1641 This is different from FIRST_PARM_OFFSET because the register window
1642 comes between the CFA and the arguments. */
1644 #define ARG_POINTER_CFA_OFFSET(FNDECL) SPARC_STACK_BIAS
1646 /* When a parameter is passed in a register, stack space is still
1648 !v9: All 6 possible integer registers have backing store allocated.
1649 v9: Only space for the arguments passed is allocated. */
1650 /* ??? Ideally, we'd use zero here (as the minimum), but zero has special
1651 meaning to the backend. Further, we need to be able to detect if a
1652 varargs/unprototyped function is called, as they may want to spill more
1653 registers than we've provided space. Ugly, ugly. So for now we retain
1654 all 6 slots even for v9. */
1655 #define REG_PARM_STACK_SPACE(DECL) (6 * UNITS_PER_WORD)
1657 /* Keep the stack pointer constant throughout the function.
1658 This is both an optimization and a necessity: longjmp
1659 doesn't behave itself when the stack pointer moves within
1661 #define ACCUMULATE_OUTGOING_ARGS 1
1663 /* Value is the number of bytes of arguments automatically
1664 popped when returning from a subroutine call.
1665 FUNDECL is the declaration node of the function (as a tree),
1666 FUNTYPE is the data type of the function (as a tree),
1667 or for a library call it is an identifier node for the subroutine name.
1668 SIZE is the number of bytes of arguments passed on the stack. */
1670 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1672 /* Some subroutine macros specific to this machine.
1673 When !TARGET_FPU, put float return values in the general registers,
1674 since we don't have any fp registers. */
1675 #define BASE_RETURN_VALUE_REG(MODE) \
1677 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 : 8) \
1678 : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 : 8))
1680 #define BASE_OUTGOING_VALUE_REG(MODE) \
1682 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 \
1683 : TARGET_FLAT ? 8 : 24) \
1684 : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 \
1685 : (TARGET_FLAT ? 8 : 24)))
1687 #define BASE_PASSING_ARG_REG(MODE) \
1689 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 : 8) \
1692 /* ??? FIXME -- seems wrong for v9 structure passing... */
1693 #define BASE_INCOMING_ARG_REG(MODE) \
1695 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 \
1696 : TARGET_FLAT ? 8 : 24) \
1697 : (TARGET_FLAT ? 8 : 24))
1699 /* Define this macro if the target machine has "register windows". This
1700 C expression returns the register number as seen by the called function
1701 corresponding to register number OUT as seen by the calling function.
1702 Return OUT if register number OUT is not an outbound register. */
1704 #define INCOMING_REGNO(OUT) \
1705 ((TARGET_FLAT || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16)
1707 /* Define this macro if the target machine has "register windows". This
1708 C expression returns the register number as seen by the calling function
1709 corresponding to register number IN as seen by the called function.
1710 Return IN if register number IN is not an inbound register. */
1712 #define OUTGOING_REGNO(IN) \
1713 ((TARGET_FLAT || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16)
1715 /* Define this macro if the target machine has register windows. This
1716 C expression returns true if the register is call-saved but is in the
1719 #define LOCAL_REGNO(REGNO) \
1720 (TARGET_FLAT ? 0 : (REGNO) >= 16 && (REGNO) <= 31)
1722 /* Define how to find the value returned by a function.
1723 VALTYPE is the data type of the value (as a tree).
1724 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1725 otherwise, FUNC is 0. */
1727 /* On SPARC the value is found in the first "output" register. */
1729 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1730 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 1)
1732 /* But the called function leaves it in the first "input" register. */
1734 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
1735 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 0)
1737 /* Define how to find the value returned by a library function
1738 assuming the value has mode MODE. */
1740 #define LIBCALL_VALUE(MODE) \
1741 function_value (NULL_TREE, (MODE), 1)
1743 /* 1 if N is a possible register number for a function value
1744 as seen by the caller.
1745 On SPARC, the first "output" reg is used for integer values,
1746 and the first floating point register is used for floating point values. */
1748 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32)
1750 /* Define the size of space to allocate for the return value of an
1753 #define APPLY_RESULT_SIZE 16
1755 /* 1 if N is a possible register number for function argument passing.
1756 On SPARC, these are the "output" registers. v9 also uses %f0-%f31. */
1758 #define FUNCTION_ARG_REGNO_P(N) \
1760 ? (((N) >= 8 && (N) <= 13) || ((N) >= 32 && (N) <= 63)) \
1761 : ((N) >= 8 && (N) <= 13))
1763 /* Define a data type for recording info about an argument list
1764 during the scan of that argument list. This data type should
1765 hold all necessary information about the function itself
1766 and about the args processed so far, enough to enable macros
1767 such as FUNCTION_ARG to determine where the next arg should go.
1769 On SPARC (!v9), this is a single integer, which is a number of words
1770 of arguments scanned so far (including the invisible argument,
1771 if any, which holds the structure-value-address).
1772 Thus 7 or more means all following args should go on the stack.
1774 For v9, we also need to know whether a prototype is present. */
1777 int words; /* number of words passed so far */
1778 int prototype_p; /* non-zero if a prototype is present */
1779 int libcall_p; /* non-zero if a library call */
1781 #define CUMULATIVE_ARGS struct sparc_args
1783 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1784 for a call to a function whose data type is FNTYPE.
1785 For a library call, FNTYPE is 0. */
1787 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1788 init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (INDIRECT));
1790 /* Update the data in CUM to advance over an argument
1791 of mode MODE and data type TYPE.
1792 TYPE is null for libcalls where that information may not be available. */
1794 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1795 function_arg_advance (& (CUM), (MODE), (TYPE), (NAMED))
1797 /* Nonzero if we do not know how to pass TYPE solely in registers. */
1799 #define MUST_PASS_IN_STACK(MODE,TYPE) \
1801 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1802 || TREE_ADDRESSABLE (TYPE)))
1804 /* Determine where to put an argument to a function.
1805 Value is zero to push the argument on the stack,
1806 or a hard register in which to store the argument.
1808 MODE is the argument's machine mode.
1809 TYPE is the data type of the argument (as a tree).
1810 This is null for libcalls where that information may
1812 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1813 the preceding args and about the function being called.
1814 NAMED is nonzero if this argument is a named parameter
1815 (otherwise it is an extra parameter matching an ellipsis). */
1817 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1818 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 0)
1820 /* Define where a function finds its arguments.
1821 This is different from FUNCTION_ARG because of register windows. */
1823 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
1824 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 1)
1826 /* For an arg passed partly in registers and partly in memory,
1827 this is the number of registers used.
1828 For args passed entirely in registers or entirely in memory, zero. */
1830 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1831 function_arg_partial_nregs (& (CUM), (MODE), (TYPE), (NAMED))
1833 /* A C expression that indicates when an argument must be passed by reference.
1834 If nonzero for an argument, a copy of that argument is made in memory and a
1835 pointer to the argument is passed instead of the argument itself.
1836 The pointer is passed in whatever way is appropriate for passing a pointer
1839 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1840 function_arg_pass_by_reference (& (CUM), (MODE), (TYPE), (NAMED))
1842 /* If defined, a C expression which determines whether, and in which direction,
1843 to pad out an argument with extra space. The value should be of type
1844 `enum direction': either `upward' to pad above the argument,
1845 `downward' to pad below, or `none' to inhibit padding. */
1847 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1848 function_arg_padding ((MODE), (TYPE))
1850 /* If defined, a C expression that gives the alignment boundary, in bits,
1851 of an argument with the specified mode and type. If it is not defined,
1852 PARM_BOUNDARY is used for all arguments.
1853 For sparc64, objects requiring 16 byte alignment are passed that way. */
1855 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1857 && (GET_MODE_ALIGNMENT (MODE) == 128 \
1858 || ((TYPE) && TYPE_ALIGN (TYPE) == 128))) \
1859 ? 128 : PARM_BOUNDARY)
1861 /* Define the information needed to generate branch and scc insns. This is
1862 stored from the compare operation. Note that we can't use "rtx" here
1863 since it hasn't been defined! */
1865 extern struct rtx_def *sparc_compare_op0, *sparc_compare_op1;
1868 /* Generate the special assembly code needed to tell the assembler whatever
1869 it might need to know about the return value of a function.
1871 For Sparc assemblers, we need to output a .proc pseudo-op which conveys
1872 information to the assembler relating to peephole optimization (done in
1875 #define ASM_DECLARE_RESULT(FILE, RESULT) \
1876 fprintf ((FILE), "\t.proc\t0%lo\n", sparc_type_code (TREE_TYPE (RESULT)))
1878 /* Output the label for a function definition. */
1880 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
1882 ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \
1883 ASM_OUTPUT_LABEL (FILE, NAME); \
1886 /* Output the special assembly code needed to tell the assembler some
1887 register is used as global register variable.
1889 SPARC 64bit psABI declares registers %g2 and %g3 as application
1890 registers and %g6 and %g7 as OS registers. Any object using them
1891 should declare (for %g2/%g3 has to, for %g6/%g7 can) that it uses them
1892 and how they are used (scratch or some global variable).
1893 Linker will then refuse to link together objects which use those
1894 registers incompatibly.
1896 Unless the registers are used for scratch, two different global
1897 registers cannot be declared to the same name, so in the unlikely
1898 case of a global register variable occupying more than one register
1899 we prefix the second and following registers with .gnu.part1. etc. */
1901 extern char sparc_hard_reg_printed[8];
1903 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
1904 #define ASM_DECLARE_REGISTER_GLOBAL(FILE, DECL, REGNO, NAME) \
1906 if (TARGET_ARCH64) \
1908 int end = HARD_REGNO_NREGS ((REGNO), DECL_MODE (decl)) + (REGNO); \
1910 for (reg = (REGNO); reg < 8 && reg < end; reg++) \
1911 if ((reg & ~1) == 2 || (reg & ~1) == 6) \
1913 if (reg == (REGNO)) \
1914 fprintf ((FILE), "\t.register\t%%g%d, %s\n", reg, (NAME)); \
1916 fprintf ((FILE), "\t.register\t%%g%d, .gnu.part%d.%s\n", \
1917 reg, reg - (REGNO), (NAME)); \
1918 sparc_hard_reg_printed[reg] = 1; \
1924 /* This macro generates the assembly code for function entry.
1925 FILE is a stdio stream to output the code to.
1926 SIZE is an int: how many units of temporary storage to allocate.
1927 Refer to the array `regs_ever_live' to determine which registers
1928 to save; `regs_ever_live[I]' is nonzero if register number I
1929 is ever used in the function. This macro is responsible for
1930 knowing which registers should not be saved even if used. */
1932 /* On SPARC, move-double insns between fpu and cpu need an 8-byte block
1933 of memory. If any fpu reg is used in the function, we allocate
1934 such a block here, at the bottom of the frame, just in case it's needed.
1936 If this function is a leaf procedure, then we may choose not
1937 to do a "save" insn. The decision about whether or not
1938 to do this is made in regclass.c. */
1940 #define FUNCTION_PROLOGUE(FILE, SIZE) \
1941 (TARGET_FLAT ? sparc_flat_output_function_prologue (FILE, (int)SIZE) \
1942 : output_function_prologue (FILE, (int)SIZE, \
1943 current_function_uses_only_leaf_regs))
1945 /* Output assembler code to FILE to increment profiler label # LABELNO
1946 for profiling a function entry. */
1948 #define FUNCTION_PROFILER(FILE, LABELNO) \
1949 sparc_function_profiler(FILE, LABELNO)
1951 /* Set the name of the mcount function for the system. */
1953 #define MCOUNT_FUNCTION "*mcount"
1955 /* The following macro shall output assembler code to FILE
1956 to initialize basic-block profiling. */
1958 #define FUNCTION_BLOCK_PROFILER(FILE, BLOCK_OR_LABEL) \
1959 sparc_function_block_profiler(FILE, BLOCK_OR_LABEL)
1961 /* The following macro shall output assembler code to FILE
1962 to increment a counter associated with basic block number BLOCKNO. */
1964 #define BLOCK_PROFILER(FILE, BLOCKNO) \
1965 sparc_block_profiler (FILE, BLOCKNO)
1967 /* The following macro shall output assembler code to FILE
1968 to indicate a return from function during basic-block profiling. */
1970 #define FUNCTION_BLOCK_PROFILER_EXIT(FILE) \
1971 sparc_function_block_profiler_exit(FILE)
1975 /* The function `__bb_trace_func' is called in every basic block
1976 and is not allowed to change the machine state. Saving (restoring)
1977 the state can either be done in the BLOCK_PROFILER macro,
1978 before calling function (rsp. after returning from function)
1979 `__bb_trace_func', or it can be done inside the function by
1980 defining the macros:
1982 MACHINE_STATE_SAVE(ID)
1983 MACHINE_STATE_RESTORE(ID)
1985 In the latter case care must be taken, that the prologue code
1986 of function `__bb_trace_func' does not already change the
1987 state prior to saving it with MACHINE_STATE_SAVE.
1989 The parameter `ID' is a string identifying a unique macro use.
1991 On sparc it is sufficient to save the psw register to memory.
1992 Unfortunately the psw register can be read in supervisor mode only,
1993 so we read only the condition codes by using branch instructions
1994 and hope that this is enough.
1996 On V9, life is much sweater: there is a user accessible %ccr
1997 register, but we use it for 64bit libraries only. */
2001 #define MACHINE_STATE_SAVE(ID) \
2002 int ms_flags, ms_saveret; \
2015 bneg,a LFLGNN"ID"\n\
2018 : "=r"(ms_flags), "=r"(ms_saveret));
2022 #define MACHINE_STATE_SAVE(ID) \
2023 unsigned long ms_flags, ms_saveret; \
2027 : "=r"(ms_flags), "=r"(ms_saveret));
2031 /* On sparc MACHINE_STATE_RESTORE restores the psw register from memory.
2032 The psw register can be written in supervisor mode only,
2033 which is true even for simple condition codes.
2034 We use some combination of instructions to produce the
2035 proper condition codes, but some flag combinations can not
2036 be generated in this way. If this happens an unimplemented
2037 instruction will be executed to abort the program. */
2041 #define MACHINE_STATE_RESTORE(ID) \
2042 { extern char flgtab[] __asm__("LFLGTAB"ID); \
2046 ! Do part of VC in the delay slot here, as it needs 3 insns.\n\
2063 subcc %%g0,%%g0,%%g0\n\
2072 orcc %%g0,-1,%%g0\n\
2075 addcc %%g0,%3,%%g0\n\
2097 : "r"(ms_flags*8), "r"(flgtab), "r"(-1), \
2098 "r"(0x80000000), "r"(ms_saveret) \
2103 #define MACHINE_STATE_RESTORE(ID) \
2107 : : "r"(ms_flags), "r"(ms_saveret) \
2112 #endif /* IN_LIBGCC2 */
2114 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2115 the stack pointer does not matter. The value is tested only in
2116 functions that have frame pointers.
2117 No definition is equivalent to always zero. */
2119 #define EXIT_IGNORE_STACK \
2120 (get_frame_size () != 0 \
2121 || current_function_calls_alloca || current_function_outgoing_args_size)
2123 /* This macro generates the assembly code for function exit,
2124 on machines that need it. If FUNCTION_EPILOGUE is not defined
2125 then individual return instructions are generated for each
2126 return statement. Args are same as for FUNCTION_PROLOGUE.
2128 The function epilogue should not depend on the current stack pointer!
2129 It should use the frame pointer only. This is mandatory because
2130 of alloca; we also take advantage of it to omit stack adjustments
2131 before returning. */
2133 #define FUNCTION_EPILOGUE(FILE, SIZE) \
2134 (TARGET_FLAT ? sparc_flat_output_function_epilogue (FILE, (int)SIZE) \
2135 : output_function_epilogue (FILE, (int)SIZE, \
2136 current_function_uses_only_leaf_regs))
2138 #define DELAY_SLOTS_FOR_EPILOGUE \
2139 (TARGET_FLAT ? sparc_flat_epilogue_delay_slots () : 1)
2140 #define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \
2141 (TARGET_FLAT ? sparc_flat_eligible_for_epilogue_delay (trial, slots_filled) \
2142 : eligible_for_epilogue_delay (trial, slots_filled))
2144 /* Define registers used by the epilogue and return instruction. */
2145 #define EPILOGUE_USES(REGNO) \
2146 (!TARGET_FLAT && REGNO == 31)
2148 /* Length in units of the trampoline for entering a nested function. */
2150 #define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 32 : 16)
2152 #define TRAMPOLINE_ALIGNMENT 128 /* 16 bytes */
2154 /* Emit RTL insns to initialize the variable parts of a trampoline.
2155 FNADDR is an RTX for the address of the function's pure code.
2156 CXT is an RTX for the static chain value for the function. */
2158 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2159 if (TARGET_ARCH64) \
2160 sparc64_initialize_trampoline (TRAMP, FNADDR, CXT); \
2162 sparc_initialize_trampoline (TRAMP, FNADDR, CXT)
2164 /* Generate necessary RTL for __builtin_saveregs(). */
2166 #define EXPAND_BUILTIN_SAVEREGS() sparc_builtin_saveregs ()
2168 /* Implement `va_start' for varargs and stdarg. */
2169 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
2170 sparc_va_start (stdarg, valist, nextarg)
2172 /* Implement `va_arg'. */
2173 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2174 sparc_va_arg (valist, type)
2176 /* Define this macro if the location where a function argument is passed
2177 depends on whether or not it is a named argument.
2179 This macro controls how the NAMED argument to FUNCTION_ARG
2180 is set for varargs and stdarg functions. With this macro defined,
2181 the NAMED argument is always true for named arguments, and false for
2182 unnamed arguments. If this is not defined, but SETUP_INCOMING_VARARGS
2183 is defined, then all arguments are treated as named. Otherwise, all named
2184 arguments except the last are treated as named.
2185 For the v9 we want NAMED to mean what it says it means. */
2187 #define STRICT_ARGUMENT_NAMING TARGET_V9
2189 /* We do not allow sibling calls if -mflat, nor
2190 we do not allow indirect calls to be optimized into sibling calls. */
2191 #define FUNCTION_OK_FOR_SIBCALL(DECL) (DECL && ! TARGET_FLAT)
2193 /* Generate RTL to flush the register windows so as to make arbitrary frames
2195 #define SETUP_FRAME_ADDRESSES() \
2196 emit_insn (gen_flush_register_windows ())
2198 /* Given an rtx for the address of a frame,
2199 return an rtx for the address of the word in the frame
2200 that holds the dynamic chain--the previous frame's address.
2201 ??? -mflat support? */
2202 #define DYNAMIC_CHAIN_ADDRESS(frame) plus_constant (frame, 14 * UNITS_PER_WORD)
2204 /* The return address isn't on the stack, it is in a register, so we can't
2205 access it from the current frame pointer. We can access it from the
2206 previous frame pointer though by reading a value from the register window
2208 #define RETURN_ADDR_IN_PREVIOUS_FRAME
2210 /* This is the offset of the return address to the true next instruction to be
2211 executed for the current function. */
2212 #define RETURN_ADDR_OFFSET \
2213 (8 + 4 * (! TARGET_ARCH64 && current_function_returns_struct))
2215 /* The current return address is in %i7. The return address of anything
2216 farther back is in the register window save area at [%fp+60]. */
2217 /* ??? This ignores the fact that the actual return address is +8 for normal
2218 returns, and +12 for structure returns. */
2219 #define RETURN_ADDR_RTX(count, frame) \
2221 ? gen_rtx_REG (Pmode, 31) \
2222 : gen_rtx_MEM (Pmode, \
2223 memory_address (Pmode, plus_constant (frame, \
2224 15 * UNITS_PER_WORD))))
2226 /* Before the prologue, the return address is %o7 + 8. OK, sometimes it's
2227 +12, but always using +8 is close enough for frame unwind purposes.
2228 Actually, just using %o7 is close enough for unwinding, but %o7+8
2229 is something you can return to. */
2230 #define INCOMING_RETURN_ADDR_RTX \
2231 plus_constant (gen_rtx_REG (word_mode, 15), 8)
2232 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (15)
2234 /* The offset from the incoming value of %sp to the top of the stack frame
2235 for the current function. On sparc64, we have to account for the stack
2237 #define INCOMING_FRAME_SP_OFFSET SPARC_STACK_BIAS
2239 #define DOESNT_NEED_UNWINDER (! TARGET_FLAT)
2241 /* Addressing modes, and classification of registers for them. */
2243 /* #define HAVE_POST_INCREMENT 0 */
2244 /* #define HAVE_POST_DECREMENT 0 */
2246 /* #define HAVE_PRE_DECREMENT 0 */
2247 /* #define HAVE_PRE_INCREMENT 0 */
2249 /* Macros to check register numbers against specific register classes. */
2251 /* These assume that REGNO is a hard or pseudo reg number.
2252 They give nonzero only if REGNO is a hard reg of the suitable class
2253 or a pseudo reg currently allocated to a suitable hard reg.
2254 Since they use reg_renumber, they are safe only once reg_renumber
2255 has been allocated, which happens in local-alloc.c. */
2257 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2258 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < (unsigned)32)
2259 #define REGNO_OK_FOR_BASE_P(REGNO) \
2260 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < (unsigned)32)
2261 #define REGNO_OK_FOR_FP_P(REGNO) \
2262 (((unsigned) (REGNO) - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)) \
2263 || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)))
2264 #define REGNO_OK_FOR_CCFP_P(REGNO) \
2266 && (((unsigned) (REGNO) - 96 < (unsigned)4) \
2267 || ((unsigned) reg_renumber[REGNO] - 96 < (unsigned)4)))
2269 /* Now macros that check whether X is a register and also,
2270 strictly, whether it is in a specified class.
2272 These macros are specific to the SPARC, and may be used only
2273 in code for printing assembler insns and in conditions for
2274 define_optimization. */
2276 /* 1 if X is an fp register. */
2278 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
2280 /* Is X, a REG, an in or global register? i.e. is regno 0..7 or 24..31 */
2281 #define IN_OR_GLOBAL_P(X) (REGNO (X) < 8 || (REGNO (X) >= 24 && REGNO (X) <= 31))
2283 /* Maximum number of registers that can appear in a valid memory address. */
2285 #define MAX_REGS_PER_ADDRESS 2
2287 /* Recognize any constant value that is a valid address.
2288 When PIC, we do not accept an address that would require a scratch reg
2289 to load into a register. */
2291 #define CONSTANT_ADDRESS_P(X) \
2292 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2293 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
2294 || (GET_CODE (X) == CONST \
2295 && ! (flag_pic && pic_address_needs_scratch (X))))
2297 /* Define this, so that when PIC, reload won't try to reload invalid
2298 addresses which require two reload registers. */
2300 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
2302 /* Nonzero if the constant value X is a legitimate general operand.
2303 Anything can be made to work except floating point constants.
2304 If TARGET_VIS, 0.0 can be made to work as well. */
2306 #define LEGITIMATE_CONSTANT_P(X) \
2307 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode || \
2309 (GET_MODE (X) == SFmode || GET_MODE (X) == DFmode || \
2310 GET_MODE (X) == TFmode) && \
2311 fp_zero_operand (X, GET_MODE (X))))
2313 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2314 and check its validity for a certain class.
2315 We have two alternate definitions for each of them.
2316 The usual definition accepts all pseudo regs; the other rejects
2317 them unless they have been allocated suitable hard regs.
2318 The symbol REG_OK_STRICT causes the latter definition to be used.
2320 Most source files want to accept pseudo regs in the hope that
2321 they will get allocated to the class that the insn wants them to be in.
2322 Source files for reload pass need to be strict.
2323 After reload, it makes no difference, since pseudo regs have
2324 been eliminated by then. */
2326 /* Optional extra constraints for this machine.
2328 'Q' handles floating point constants which can be moved into
2329 an integer register with a single sethi instruction.
2331 'R' handles floating point constants which can be moved into
2332 an integer register with a single mov instruction.
2334 'S' handles floating point constants which can be moved into
2335 an integer register using a high/lo_sum sequence.
2337 'T' handles memory addresses where the alignment is known to
2338 be at least 8 bytes.
2340 `U' handles all pseudo registers or a hard even numbered
2341 integer register, needed for ldd/std instructions. */
2343 #define EXTRA_CONSTRAINT_BASE(OP, C) \
2344 ((C) == 'Q' ? fp_sethi_p(OP) \
2345 : (C) == 'R' ? fp_mov_p(OP) \
2346 : (C) == 'S' ? fp_high_losum_p(OP) \
2349 #ifndef REG_OK_STRICT
2351 /* Nonzero if X is a hard reg that can be used as an index
2352 or if it is a pseudo reg. */
2353 #define REG_OK_FOR_INDEX_P(X) \
2354 (((unsigned) REGNO (X)) - 32 >= (FIRST_PSEUDO_REGISTER - 32))
2355 /* Nonzero if X is a hard reg that can be used as a base reg
2356 or if it is a pseudo reg. */
2357 #define REG_OK_FOR_BASE_P(X) \
2358 (((unsigned) REGNO (X)) - 32 >= (FIRST_PSEUDO_REGISTER - 32))
2360 /* 'T', 'U' are for aligned memory loads which aren't needed for arch64. */
2362 #define EXTRA_CONSTRAINT(OP, C) \
2363 (EXTRA_CONSTRAINT_BASE(OP, C) \
2364 || ((! TARGET_ARCH64 && (C) == 'T') \
2365 ? (mem_min_alignment (OP, 8)) \
2366 : ((! TARGET_ARCH64 && (C) == 'U') \
2367 ? (register_ok_for_ldd (OP)) \
2372 /* Nonzero if X is a hard reg that can be used as an index. */
2373 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
2374 /* Nonzero if X is a hard reg that can be used as a base reg. */
2375 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
2377 #define EXTRA_CONSTRAINT(OP, C) \
2378 (EXTRA_CONSTRAINT_BASE(OP, C) \
2379 || ((! TARGET_ARCH64 && (C) == 'T') \
2380 ? mem_min_alignment (OP, 8) && strict_memory_address_p (Pmode, XEXP (OP, 0)) \
2381 : ((! TARGET_ARCH64 && (C) == 'U') \
2382 ? (GET_CODE (OP) == REG \
2383 && (REGNO (OP) < FIRST_PSEUDO_REGISTER \
2384 || reg_renumber[REGNO (OP)] >= 0) \
2385 && register_ok_for_ldd (OP)) \
2390 /* Should gcc use [%reg+%lo(xx)+offset] addresses? */
2392 #ifdef HAVE_AS_OFFSETABLE_LO10
2393 #define USE_AS_OFFSETABLE_LO10 1
2395 #define USE_AS_OFFSETABLE_LO10 0
2398 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2399 that is a valid memory address for an instruction.
2400 The MODE argument is the machine mode for the MEM expression
2401 that wants to use this address.
2403 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
2404 ordinarily. This changes a bit when generating PIC.
2406 If you change this, execute "rm explow.o recog.o reload.o". */
2408 #define RTX_OK_FOR_BASE_P(X) \
2409 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2410 || (GET_CODE (X) == SUBREG \
2411 && GET_CODE (SUBREG_REG (X)) == REG \
2412 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2414 #define RTX_OK_FOR_INDEX_P(X) \
2415 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2416 || (GET_CODE (X) == SUBREG \
2417 && GET_CODE (SUBREG_REG (X)) == REG \
2418 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
2420 #define RTX_OK_FOR_OFFSET_P(X) \
2421 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000 - 8)
2423 #define RTX_OK_FOR_OLO10_P(X) \
2424 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0xc00 - 8)
2426 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2427 { if (RTX_OK_FOR_BASE_P (X)) \
2429 else if (GET_CODE (X) == PLUS) \
2431 register rtx op0 = XEXP (X, 0); \
2432 register rtx op1 = XEXP (X, 1); \
2433 if (flag_pic && op0 == pic_offset_table_rtx) \
2435 if (RTX_OK_FOR_BASE_P (op1)) \
2437 else if (flag_pic == 1 \
2438 && GET_CODE (op1) != REG \
2439 && GET_CODE (op1) != LO_SUM \
2440 && GET_CODE (op1) != MEM \
2441 && (GET_CODE (op1) != CONST_INT \
2442 || SMALL_INT (op1))) \
2445 else if (RTX_OK_FOR_BASE_P (op0)) \
2447 if ((RTX_OK_FOR_INDEX_P (op1) \
2448 /* We prohibit REG + REG for TFmode when \
2449 there are no instructions which accept \
2450 REG+REG instructions. We do this \
2451 because REG+REG is not an offsetable \
2452 address. If we get the situation \
2453 in reload where source and destination \
2454 of a movtf pattern are both MEMs with \
2455 REG+REG address, then only one of them \
2456 gets converted to an offsetable \
2458 && (MODE != TFmode \
2459 || (TARGET_FPU && TARGET_ARCH64 \
2461 && TARGET_HARD_QUAD)) \
2462 /* We prohibit REG + REG on ARCH32 if \
2463 not optimizing for DFmode/DImode \
2464 because then mem_min_alignment is \
2465 likely to be zero after reload and the \
2466 forced split would lack a matching \
2467 splitter pattern. */ \
2468 && (TARGET_ARCH64 || optimize \
2469 || (MODE != DFmode \
2470 && MODE != DImode))) \
2471 || RTX_OK_FOR_OFFSET_P (op1)) \
2474 else if (RTX_OK_FOR_BASE_P (op1)) \
2476 if ((RTX_OK_FOR_INDEX_P (op0) \
2477 /* See the previous comment. */ \
2478 && (MODE != TFmode \
2479 || (TARGET_FPU && TARGET_ARCH64 \
2481 && TARGET_HARD_QUAD)) \
2482 && (TARGET_ARCH64 || optimize \
2483 || (MODE != DFmode \
2484 && MODE != DImode))) \
2485 || RTX_OK_FOR_OFFSET_P (op0)) \
2488 else if (USE_AS_OFFSETABLE_LO10 \
2489 && GET_CODE (op0) == LO_SUM \
2491 && ! TARGET_CM_MEDMID \
2492 && RTX_OK_FOR_OLO10_P (op1)) \
2494 register rtx op00 = XEXP (op0, 0); \
2495 register rtx op01 = XEXP (op0, 1); \
2496 if (RTX_OK_FOR_BASE_P (op00) \
2497 && CONSTANT_P (op01)) \
2500 else if (USE_AS_OFFSETABLE_LO10 \
2501 && GET_CODE (op1) == LO_SUM \
2503 && ! TARGET_CM_MEDMID \
2504 && RTX_OK_FOR_OLO10_P (op0)) \
2506 register rtx op10 = XEXP (op1, 0); \
2507 register rtx op11 = XEXP (op1, 1); \
2508 if (RTX_OK_FOR_BASE_P (op10) \
2509 && CONSTANT_P (op11)) \
2513 else if (GET_CODE (X) == LO_SUM) \
2515 register rtx op0 = XEXP (X, 0); \
2516 register rtx op1 = XEXP (X, 1); \
2517 if (RTX_OK_FOR_BASE_P (op0) \
2518 && CONSTANT_P (op1) \
2519 /* We can't allow TFmode, because an offset \
2520 greater than or equal to the alignment (8) \
2521 may cause the LO_SUM to overflow if !v9. */\
2522 && (MODE != TFmode || TARGET_V9)) \
2525 else if (GET_CODE (X) == CONST_INT && SMALL_INT (X)) \
2529 /* Try machine-dependent ways of modifying an illegitimate address
2530 to be legitimate. If we find one, return the new, valid address.
2531 This macro is used in only one place: `memory_address' in explow.c.
2533 OLDX is the address as it was before break_out_memory_refs was called.
2534 In some cases it is useful to look at this to decide what needs to be done.
2536 MODE and WIN are passed so that this macro can use
2537 GO_IF_LEGITIMATE_ADDRESS.
2539 It is always safe for this macro to do nothing. It exists to recognize
2540 opportunities to optimize the output. */
2542 /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
2543 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2544 { rtx sparc_x = (X); \
2545 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \
2546 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 1), \
2547 force_operand (XEXP (X, 0), NULL_RTX)); \
2548 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \
2549 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2550 force_operand (XEXP (X, 1), NULL_RTX)); \
2551 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \
2552 (X) = gen_rtx_PLUS (Pmode, force_operand (XEXP (X, 0), NULL_RTX),\
2554 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \
2555 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2556 force_operand (XEXP (X, 1), NULL_RTX)); \
2557 if (sparc_x != (X) && memory_address_p (MODE, X)) \
2559 if (flag_pic) (X) = legitimize_pic_address (X, MODE, 0); \
2560 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
2561 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2562 copy_to_mode_reg (Pmode, XEXP (X, 1))); \
2563 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0))) \
2564 (X) = gen_rtx_PLUS (Pmode, XEXP (X, 1), \
2565 copy_to_mode_reg (Pmode, XEXP (X, 0))); \
2566 else if (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
2567 || GET_CODE (X) == LABEL_REF) \
2568 (X) = copy_to_suggested_reg (X, NULL_RTX, Pmode); \
2569 if (memory_address_p (MODE, X)) \
2572 /* Try a machine-dependent way of reloading an illegitimate address
2573 operand. If we find one, push the reload and jump to WIN. This
2574 macro is used in only one place: `find_reloads_address' in reload.c.
2576 For Sparc 32, we wish to handle addresses by splitting them into
2577 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
2578 This cuts the number of extra insns by one.
2580 Do nothing when generating PIC code and the address is a
2581 symbolic operand or requires a scratch register. */
2583 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2585 /* Decompose SImode constants into hi+lo_sum. We do have to \
2586 rerecognize what we produce, so be careful. */ \
2587 if (CONSTANT_P (X) \
2588 && (MODE != TFmode || TARGET_V9) \
2589 && GET_MODE (X) == SImode \
2590 && GET_CODE (X) != LO_SUM && GET_CODE (X) != HIGH \
2592 && (symbolic_operand (X, Pmode) \
2593 || pic_address_needs_scratch (X)))) \
2595 X = gen_rtx_LO_SUM (GET_MODE (X), \
2596 gen_rtx_HIGH (GET_MODE (X), X), X); \
2597 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR, \
2598 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
2602 /* ??? 64-bit reloads. */ \
2605 /* Go to LABEL if ADDR (a legitimate address expression)
2606 has an effect that depends on the machine mode it is used for.
2607 On the SPARC this is never true. */
2609 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
2611 /* If we are referencing a function make the SYMBOL_REF special.
2612 In the Embedded Medium/Anywhere code model, %g4 points to the data segment
2613 so we must not add it to function addresses. */
2615 #define ENCODE_SECTION_INFO(DECL) \
2617 if (TARGET_CM_EMBMEDANY && TREE_CODE (DECL) == FUNCTION_DECL) \
2618 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
2621 /* Specify the machine mode that this machine uses
2622 for the index in the tablejump instruction. */
2623 /* If we ever implement any of the full models (such as CM_FULLANY),
2624 this has to be DImode in that case */
2625 #ifdef HAVE_GAS_SUBSECTION_ORDERING
2626 #define CASE_VECTOR_MODE \
2627 (! TARGET_PTR64 ? SImode : flag_pic ? SImode : TARGET_CM_MEDLOW ? SImode : DImode)
2629 /* If assembler does not have working .subsection -1, we use DImode for pic, as otherwise
2630 we have to sign extend which slows things down. */
2631 #define CASE_VECTOR_MODE \
2632 (! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode)
2635 /* Define as C expression which evaluates to nonzero if the tablejump
2636 instruction expects the table to contain offsets from the address of the
2638 Do not define this if the table should contain absolute addresses. */
2639 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2641 /* Specify the tree operation to be used to convert reals to integers. */
2642 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
2644 /* This is the kind of divide that is easiest to do in the general case. */
2645 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
2647 /* Define this as 1 if `char' should by default be signed; else as 0. */
2648 #define DEFAULT_SIGNED_CHAR 1
2650 /* Max number of bytes we can move from memory to memory
2651 in one reasonably fast instruction. */
2654 #if 0 /* Sun 4 has matherr, so this is no good. */
2655 /* This is the value of the error code EDOM for this machine,
2656 used by the sqrt instruction. */
2657 #define TARGET_EDOM 33
2659 /* This is how to refer to the variable errno. */
2660 #define GEN_ERRNO_RTX \
2661 gen_rtx_MEM (SImode, gen_rtx_SYMBOL_REF (Pmode, "errno"))
2664 /* Define if operations between registers always perform the operation
2665 on the full register even if a narrower mode is specified. */
2666 #define WORD_REGISTER_OPERATIONS
2668 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2669 will either zero-extend or sign-extend. The value of this macro should
2670 be the code that says which one of the two operations is implicitly
2671 done, NIL if none. */
2672 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2674 /* Nonzero if access to memory by bytes is slow and undesirable.
2675 For RISC chips, it means that access to memory by bytes is no
2676 better than access by words when possible, so grab a whole word
2677 and maybe make use of that. */
2678 #define SLOW_BYTE_ACCESS 1
2680 /* We assume that the store-condition-codes instructions store 0 for false
2681 and some other value for true. This is the value stored for true. */
2683 #define STORE_FLAG_VALUE 1
2685 /* When a prototype says `char' or `short', really pass an `int'. */
2686 #define PROMOTE_PROTOTYPES (TARGET_ARCH32)
2688 /* Define this to be nonzero if shift instructions ignore all but the low-order
2690 #define SHIFT_COUNT_TRUNCATED 1
2692 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2693 is done just by pretending it is already truncated. */
2694 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2696 /* Specify the machine mode that pointers have.
2697 After generation of rtl, the compiler makes no further distinction
2698 between pointers and any other objects of this machine mode. */
2699 #define Pmode (TARGET_ARCH64 ? DImode : SImode)
2701 /* Generate calls to memcpy, memcmp and memset. */
2702 #define TARGET_MEM_FUNCTIONS
2704 /* Add any extra modes needed to represent the condition code.
2706 On the Sparc, we have a "no-overflow" mode which is used when an add or
2707 subtract insn is used to set the condition code. Different branches are
2708 used in this case for some operations.
2710 We also have two modes to indicate that the relevant condition code is
2711 in the floating-point condition code register. One for comparisons which
2712 will generate an exception if the result is unordered (CCFPEmode) and
2713 one for comparisons which will never trap (CCFPmode).
2715 CCXmode and CCX_NOOVmode are only used by v9. */
2717 #define EXTRA_CC_MODES \
2718 CC(CCXmode, "CCX") \
2719 CC(CC_NOOVmode, "CC_NOOV") \
2720 CC(CCX_NOOVmode, "CCX_NOOV") \
2721 CC(CCFPmode, "CCFP") \
2722 CC(CCFPEmode, "CCFPE")
2724 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2725 return the mode to be used for the comparison. For floating-point,
2726 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2727 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2728 processing is needed. */
2729 #define SELECT_CC_MODE(OP,X,Y) select_cc_mode ((OP), (X), (Y))
2731 /* Return non-zero if MODE implies a floating point inequality can be
2732 reversed. For Sparc this is always true because we have a full
2733 compliment of ordered and unordered comparisons, but until generic
2734 code knows how to reverse it correctly we keep the old definition. */
2735 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode && (MODE) != CCFPmode)
2737 /* A function address in a call instruction for indexing purposes. */
2738 #define FUNCTION_MODE Pmode
2740 /* Define this if addresses of constant functions
2741 shouldn't be put through pseudo regs where they can be cse'd.
2742 Desirable on machines where ordinary constants are expensive
2743 but a CALL with constant address is cheap. */
2744 #define NO_FUNCTION_CSE
2746 /* alloca should avoid clobbering the old register save area. */
2747 #define SETJMP_VIA_SAVE_AREA
2749 /* Define subroutines to call to handle multiply and divide.
2750 Use the subroutines that Sun's library provides.
2751 The `*' prevents an underscore from being prepended by the compiler. */
2753 #define DIVSI3_LIBCALL "*.div"
2754 #define UDIVSI3_LIBCALL "*.udiv"
2755 #define MODSI3_LIBCALL "*.rem"
2756 #define UMODSI3_LIBCALL "*.urem"
2757 /* .umul is a little faster than .mul. */
2758 #define MULSI3_LIBCALL "*.umul"
2760 /* Define library calls for quad FP operations. These are all part of the
2762 #define ADDTF3_LIBCALL "_Q_add"
2763 #define SUBTF3_LIBCALL "_Q_sub"
2764 #define NEGTF2_LIBCALL "_Q_neg"
2765 #define MULTF3_LIBCALL "_Q_mul"
2766 #define DIVTF3_LIBCALL "_Q_div"
2767 #define FLOATSITF2_LIBCALL "_Q_itoq"
2768 #define FIX_TRUNCTFSI2_LIBCALL "_Q_qtoi"
2769 #define FIXUNS_TRUNCTFSI2_LIBCALL "_Q_qtou"
2770 #define EXTENDSFTF2_LIBCALL "_Q_stoq"
2771 #define TRUNCTFSF2_LIBCALL "_Q_qtos"
2772 #define EXTENDDFTF2_LIBCALL "_Q_dtoq"
2773 #define TRUNCTFDF2_LIBCALL "_Q_qtod"
2774 #define EQTF2_LIBCALL "_Q_feq"
2775 #define NETF2_LIBCALL "_Q_fne"
2776 #define GTTF2_LIBCALL "_Q_fgt"
2777 #define GETF2_LIBCALL "_Q_fge"
2778 #define LTTF2_LIBCALL "_Q_flt"
2779 #define LETF2_LIBCALL "_Q_fle"
2781 /* We can define the TFmode sqrt optab only if TARGET_FPU. This is because
2782 with soft-float, the SFmode and DFmode sqrt instructions will be absent,
2783 and the compiler will notice and try to use the TFmode sqrt instruction
2784 for calls to the builtin function sqrt, but this fails. */
2785 #define INIT_TARGET_OPTABS \
2787 if (TARGET_ARCH32) \
2789 add_optab->handlers[(int) TFmode].libfunc \
2790 = init_one_libfunc (ADDTF3_LIBCALL); \
2791 sub_optab->handlers[(int) TFmode].libfunc \
2792 = init_one_libfunc (SUBTF3_LIBCALL); \
2793 neg_optab->handlers[(int) TFmode].libfunc \
2794 = init_one_libfunc (NEGTF2_LIBCALL); \
2795 smul_optab->handlers[(int) TFmode].libfunc \
2796 = init_one_libfunc (MULTF3_LIBCALL); \
2797 flodiv_optab->handlers[(int) TFmode].libfunc \
2798 = init_one_libfunc (DIVTF3_LIBCALL); \
2799 eqtf2_libfunc = init_one_libfunc (EQTF2_LIBCALL); \
2800 netf2_libfunc = init_one_libfunc (NETF2_LIBCALL); \
2801 gttf2_libfunc = init_one_libfunc (GTTF2_LIBCALL); \
2802 getf2_libfunc = init_one_libfunc (GETF2_LIBCALL); \
2803 lttf2_libfunc = init_one_libfunc (LTTF2_LIBCALL); \
2804 letf2_libfunc = init_one_libfunc (LETF2_LIBCALL); \
2805 trunctfsf2_libfunc = init_one_libfunc (TRUNCTFSF2_LIBCALL); \
2806 trunctfdf2_libfunc = init_one_libfunc (TRUNCTFDF2_LIBCALL); \
2807 extendsftf2_libfunc = init_one_libfunc (EXTENDSFTF2_LIBCALL); \
2808 extenddftf2_libfunc = init_one_libfunc (EXTENDDFTF2_LIBCALL); \
2809 floatsitf_libfunc = init_one_libfunc (FLOATSITF2_LIBCALL); \
2810 fixtfsi_libfunc = init_one_libfunc (FIX_TRUNCTFSI2_LIBCALL); \
2811 fixunstfsi_libfunc \
2812 = init_one_libfunc (FIXUNS_TRUNCTFSI2_LIBCALL); \
2814 sqrt_optab->handlers[(int) TFmode].libfunc \
2815 = init_one_libfunc ("_Q_sqrt"); \
2817 INIT_SUBTARGET_OPTABS; \
2820 /* This is meant to be redefined in the host dependent files */
2821 #define INIT_SUBTARGET_OPTABS
2823 /* Nonzero if a floating point comparison library call for
2824 mode MODE that will return a boolean value. Zero if one
2825 of the libgcc2 functions is used. */
2826 #define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) ((MODE) == TFmode)
2828 /* Compute the cost of computing a constant rtl expression RTX
2829 whose rtx-code is CODE. The body of this macro is a portion
2830 of a switch statement. If the code is computed here,
2831 return it with a return statement. Otherwise, break from the switch. */
2833 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
2835 if (INTVAL (RTX) < 0x1000 && INTVAL (RTX) >= -0x1000) \
2843 case CONST_DOUBLE: \
2844 if (GET_MODE (RTX) == DImode) \
2845 if ((XINT (RTX, 3) == 0 \
2846 && (unsigned) XINT (RTX, 2) < 0x1000) \
2847 || (XINT (RTX, 3) == -1 \
2848 && XINT (RTX, 2) < 0 \
2849 && XINT (RTX, 2) >= -0x1000)) \
2853 #define ADDRESS_COST(RTX) 1
2855 /* Compute extra cost of moving data between one register class
2857 #define GENERAL_OR_I64(C) ((C) == GENERAL_REGS || (C) == I64_REGS)
2858 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
2859 (((FP_REG_CLASS_P (CLASS1) && GENERAL_OR_I64 (CLASS2)) \
2860 || (GENERAL_OR_I64 (CLASS1) && FP_REG_CLASS_P (CLASS2)) \
2861 || (CLASS1) == FPCC_REGS || (CLASS2) == FPCC_REGS) \
2862 ? (sparc_cpu == PROCESSOR_ULTRASPARC ? 12 : 6) : 2)
2864 /* Provide the costs of a rtl expression. This is in the body of a
2865 switch on CODE. The purpose for the cost of MULT is to encourage
2866 `synth_mult' to find a synthetic multiply when reasonable.
2868 If we need more than 12 insns to do a multiply, then go out-of-line,
2869 since the call overhead will be < 10% of the cost of the multiply. */
2871 #define RTX_COSTS(X,CODE,OUTER_CODE) \
2873 if (sparc_cpu == PROCESSOR_ULTRASPARC) \
2874 return (GET_MODE (X) == DImode ? \
2875 COSTS_N_INSNS (34) : COSTS_N_INSNS (19)); \
2876 return TARGET_HARD_MUL ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25); \
2881 if (sparc_cpu == PROCESSOR_ULTRASPARC) \
2882 return (GET_MODE (X) == DImode ? \
2883 COSTS_N_INSNS (68) : COSTS_N_INSNS (37)); \
2884 return COSTS_N_INSNS (25); \
2885 /* Make FLOAT and FIX more expensive than CONST_DOUBLE,\
2886 so that cse will favor the latter. */ \
2891 #define ISSUE_RATE sparc_issue_rate()
2893 /* Adjust the cost of dependencies. */
2894 #define ADJUST_COST(INSN,LINK,DEP,COST) \
2895 (COST) = sparc_adjust_cost(INSN, LINK, DEP, COST)
2897 #define MD_SCHED_INIT(DUMP, SCHED_VERBOSE, MAX_READY) \
2898 if (sparc_cpu == PROCESSOR_ULTRASPARC) \
2899 ultrasparc_sched_init (DUMP, SCHED_VERBOSE)
2901 #define MD_SCHED_REORDER(DUMP, SCHED_VERBOSE, READY, N_READY, CLOCK, CIM) \
2903 if (sparc_cpu == PROCESSOR_ULTRASPARC) \
2904 ultrasparc_sched_reorder (DUMP, SCHED_VERBOSE, READY, N_READY); \
2908 #define MD_SCHED_VARIABLE_ISSUE(DUMP, SCHED_VERBOSE, INSN, CAN_ISSUE_MORE) \
2910 if (sparc_cpu == PROCESSOR_ULTRASPARC) \
2911 (CAN_ISSUE_MORE) = ultrasparc_variable_issue (INSN); \
2913 (CAN_ISSUE_MORE)--; \
2916 /* Conditional branches with empty delay slots have a length of two. */
2917 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2919 if (GET_CODE (INSN) == CALL_INSN \
2920 || (GET_CODE (INSN) == JUMP_INSN && ! simplejump_p (insn))) \
2924 /* Control the assembler format that we output. */
2926 /* Output at beginning of assembler file. */
2928 #define ASM_FILE_START(file)
2930 /* A C string constant describing how to begin a comment in the target
2931 assembler language. The compiler assumes that the comment will end at
2932 the end of the line. */
2934 #define ASM_COMMENT_START "!"
2936 /* Output to assembler file text saying following lines
2937 may contain character constants, extra white space, comments, etc. */
2939 #define ASM_APP_ON ""
2941 /* Output to assembler file text saying following lines
2942 no longer contain unusual constructs. */
2944 #define ASM_APP_OFF ""
2946 /* ??? Try to make the style consistent here (_OP?). */
2948 #define ASM_LONGLONG ".xword"
2949 #define ASM_LONG ".word"
2950 #define ASM_SHORT ".half"
2951 #define ASM_BYTE_OP "\t.byte\t"
2952 #define ASM_FLOAT ".single"
2953 #define ASM_DOUBLE ".double"
2954 #define ASM_LONGDOUBLE ".xxx" /* ??? Not known (or used yet). */
2956 /* Output before read-only data. */
2958 #define TEXT_SECTION_ASM_OP "\t.text"
2960 /* Output before writable data. */
2962 #define DATA_SECTION_ASM_OP "\t.data"
2964 /* How to refer to registers in assembler output.
2965 This sequence is indexed by compiler's hard-register-number (see above). */
2967 #define REGISTER_NAMES \
2968 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \
2969 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \
2970 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \
2971 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \
2972 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \
2973 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \
2974 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \
2975 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \
2976 "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \
2977 "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \
2978 "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \
2979 "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \
2980 "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc"}
2982 /* Define additional names for use in asm clobbers and asm declarations. */
2984 #define ADDITIONAL_REGISTER_NAMES \
2985 {{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}}
2987 /* How to renumber registers for dbx and gdb. In the flat model, the frame
2988 pointer is really %i7. */
2990 #define DBX_REGISTER_NUMBER(REGNO) \
2991 (TARGET_FLAT && REGNO == FRAME_POINTER_REGNUM ? 31 : REGNO)
2993 /* On Sun 4, this limit is 2048. We use 1000 to be safe, since the length
2994 can run past this up to a continuation point. Once we used 1500, but
2995 a single entry in C++ can run more than 500 bytes, due to the length of
2996 mangled symbol names. dbxout.c should really be fixed to do
2997 continuations when they are actually needed instead of trying to
2999 #define DBX_CONTIN_LENGTH 1000
3001 /* This is how to output a note to DBX telling it the line number
3002 to which the following sequence of instructions corresponds.
3004 This is needed for SunOS 4.0, and should not hurt for 3.2
3006 #define ASM_OUTPUT_SOURCE_LINE(file, line) \
3007 { static int sym_lineno = 1; \
3008 fprintf (file, ".stabn 68,0,%d,LM%d\nLM%d:\n", \
3009 line, sym_lineno, sym_lineno); \
3012 /* This is how to output the definition of a user-level label named NAME,
3013 such as the label on a static function or variable NAME. */
3015 #define ASM_OUTPUT_LABEL(FILE,NAME) \
3016 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
3018 /* This is how to output a command to make the user-level label named NAME
3019 defined for reference from other files. */
3021 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
3022 do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
3024 /* The prefix to add to user-visible assembler symbols. */
3026 #define USER_LABEL_PREFIX "_"
3028 /* This is how to output a definition of an internal numbered label where
3029 PREFIX is the class of label and NUM is the number within the class. */
3031 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
3032 fprintf (FILE, "%s%d:\n", PREFIX, NUM)
3034 /* This is how to store into the string LABEL
3035 the symbol_ref name of an internal numbered label where
3036 PREFIX is the class of label and NUM is the number within the class.
3037 This is suitable for output with `assemble_name'. */
3039 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
3040 sprintf ((LABEL), "*%s%ld", (PREFIX), (long)(NUM))
3042 /* This is how to output an assembler line defining a `float' constant.
3043 We always have to use a .long pseudo-op to do this because the native
3044 SVR4 ELF assembler is buggy and it generates incorrect values when we
3045 try to use the .float pseudo-op instead. */
3047 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
3051 REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \
3052 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str); \
3053 fprintf (FILE, "\t%s\t0x%lx %s ~%s\n", ASM_LONG, t, \
3054 ASM_COMMENT_START, str); \
3057 /* This is how to output an assembler line defining a `double' constant.
3058 We always have to use a .long pseudo-op to do this because the native
3059 SVR4 ELF assembler is buggy and it generates incorrect values when we
3060 try to use the .float pseudo-op instead. */
3062 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
3066 REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \
3067 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str); \
3068 fprintf (FILE, "\t%s\t0x%lx %s ~%s\n", ASM_LONG, t[0], \
3069 ASM_COMMENT_START, str); \
3070 fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t[1]); \
3073 /* This is how to output an assembler line defining a `long double'
3076 #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \
3080 REAL_VALUE_TO_TARGET_LONG_DOUBLE ((VALUE), t); \
3081 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str); \
3082 fprintf (FILE, "\t%s\t0x%lx %s ~%s\n", ASM_LONG, t[0], \
3083 ASM_COMMENT_START, str); \
3084 fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t[1]); \
3085 fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t[2]); \
3086 fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t[3]); \
3089 /* This is how to output an assembler line defining an `int' constant. */
3091 #define ASM_OUTPUT_INT(FILE,VALUE) \
3092 ( fprintf (FILE, "\t%s\t", ASM_LONG), \
3093 output_addr_const (FILE, (VALUE)), \
3094 fprintf (FILE, "\n"))
3096 /* This is how to output an assembler line defining a DImode constant. */
3097 #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \
3098 output_double_int (FILE, VALUE)
3100 /* Likewise for `char' and `short' constants. */
3102 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
3103 ( fprintf (FILE, "\t%s\t", ASM_SHORT), \
3104 output_addr_const (FILE, (VALUE)), \
3105 fprintf (FILE, "\n"))
3107 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
3108 ( fprintf (FILE, "%s", ASM_BYTE_OP), \
3109 output_addr_const (FILE, (VALUE)), \
3110 fprintf (FILE, "\n"))
3112 /* This is how to output an assembler line for a numeric constant byte. */
3114 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
3115 fprintf (FILE, "%s0x%x\n", ASM_BYTE_OP, (VALUE))
3117 /* This is how we hook in and defer the case-vector until the end of
3119 #define ASM_OUTPUT_ADDR_VEC(LAB,VEC) \
3120 sparc_defer_case_vector ((LAB),(VEC), 0)
3122 #define ASM_OUTPUT_ADDR_DIFF_VEC(LAB,VEC) \
3123 sparc_defer_case_vector ((LAB),(VEC), 1)
3125 /* This is how to output an element of a case-vector that is absolute. */
3127 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
3130 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
3131 if (CASE_VECTOR_MODE == SImode) \
3132 fprintf (FILE, "\t.word\t"); \
3134 fprintf (FILE, "\t.xword\t"); \
3135 assemble_name (FILE, label); \
3136 fputc ('\n', FILE); \
3139 /* This is how to output an element of a case-vector that is relative.
3140 (SPARC uses such vectors only when generating PIC.) */
3142 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
3145 ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE)); \
3146 if (CASE_VECTOR_MODE == SImode) \
3147 fprintf (FILE, "\t.word\t"); \
3149 fprintf (FILE, "\t.xword\t"); \
3150 assemble_name (FILE, label); \
3151 ASM_GENERATE_INTERNAL_LABEL (label, "L", (REL)); \
3152 fputc ('-', FILE); \
3153 assemble_name (FILE, label); \
3154 fputc ('\n', FILE); \
3157 /* This is what to output before and after case-vector (both
3158 relative and absolute). If .subsection -1 works, we put case-vectors
3159 at the beginning of the current section. */
3161 #ifdef HAVE_GAS_SUBSECTION_ORDERING
3163 #define ASM_OUTPUT_ADDR_VEC_START(FILE) \
3164 fprintf(FILE, "\t.subsection\t-1\n")
3166 #define ASM_OUTPUT_ADDR_VEC_END(FILE) \
3167 fprintf(FILE, "\t.previous\n")
3171 /* This is how to output an assembler line
3172 that says to advance the location counter
3173 to a multiple of 2**LOG bytes. */
3175 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
3177 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
3179 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
3180 fprintf (FILE, "\t.skip %u\n", (SIZE))
3182 /* This says how to output an assembler line
3183 to define a global common symbol. */
3185 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
3186 ( fputs ("\t.common ", (FILE)), \
3187 assemble_name ((FILE), (NAME)), \
3188 fprintf ((FILE), ",%u,\"bss\"\n", (SIZE)))
3190 /* This says how to output an assembler line to define a local common
3193 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \
3194 ( fputs ("\t.reserve ", (FILE)), \
3195 assemble_name ((FILE), (NAME)), \
3196 fprintf ((FILE), ",%u,\"bss\",%u\n", \
3197 (SIZE), ((ALIGNED) / BITS_PER_UNIT)))
3199 /* A C statement (sans semicolon) to output to the stdio stream
3200 FILE the assembler definition of uninitialized global DECL named
3201 NAME whose size is SIZE bytes and alignment is ALIGN bytes.
3202 Try to use asm_output_aligned_bss to implement this macro. */
3204 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
3206 fputs (".globl ", (FILE)); \
3207 assemble_name ((FILE), (NAME)); \
3208 fputs ("\n", (FILE)); \
3209 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \
3212 /* Store in OUTPUT a string (made with alloca) containing
3213 an assembler-name for a local static variable named NAME.
3214 LABELNO is an integer which is different for each call. */
3216 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
3217 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
3218 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
3220 #define IDENT_ASM_OP "\t.ident\t"
3222 /* Output #ident as a .ident. */
3224 #define ASM_OUTPUT_IDENT(FILE, NAME) \
3225 fprintf (FILE, "%s\"%s\"\n", IDENT_ASM_OP, NAME);
3227 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
3228 Used for C++ multiple inheritance. */
3229 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
3234 && aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION)))) \
3236 if ((DELTA) >= 4096 || (DELTA) < -4096) \
3237 fprintf (FILE, "\tset\t%d, %%g1\n\tadd\t%%o%d, %%g1, %%o%d\n", \
3238 (int)(DELTA), reg, reg); \
3240 fprintf (FILE, "\tadd\t%%o%d, %d, %%o%d\n", reg, (int)(DELTA), reg);\
3241 fprintf (FILE, "\tor\t%%o7, %%g0, %%g1\n"); \
3242 fprintf (FILE, "\tcall\t"); \
3243 assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
3244 fprintf (FILE, ", 0\n"); \
3245 fprintf (FILE, "\t or\t%%g1, %%g0, %%o7\n"); \
3248 /* Define the parentheses used to group arithmetic operations
3249 in assembler code. */
3251 #define ASM_OPEN_PAREN "("
3252 #define ASM_CLOSE_PAREN ")"
3254 /* Define results of standard character escape sequences. */
3255 #define TARGET_BELL 007
3256 #define TARGET_BS 010
3257 #define TARGET_TAB 011
3258 #define TARGET_NEWLINE 012
3259 #define TARGET_VT 013
3260 #define TARGET_FF 014
3261 #define TARGET_CR 015
3263 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
3264 ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '(' || (CHAR) == '_')
3266 /* Print operand X (an rtx) in assembler syntax to file FILE.
3267 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3268 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3270 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
3272 /* Print a memory address as an operand to reference that memory location. */
3274 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
3275 { register rtx base, index = 0; \
3277 register rtx addr = ADDR; \
3278 if (GET_CODE (addr) == REG) \
3279 fputs (reg_names[REGNO (addr)], FILE); \
3280 else if (GET_CODE (addr) == PLUS) \
3282 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
3283 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\
3284 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
3285 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\
3287 base = XEXP (addr, 0), index = XEXP (addr, 1); \
3288 if (GET_CODE (base) == LO_SUM) \
3290 if (! USE_AS_OFFSETABLE_LO10 \
3292 || TARGET_CM_MEDMID) \
3294 output_operand (XEXP (base, 0), 0); \
3295 fputs ("+%lo(", FILE); \
3296 output_address (XEXP (base, 1)); \
3297 fprintf (FILE, ")+%d", offset); \
3301 fputs (reg_names[REGNO (base)], FILE); \
3303 fprintf (FILE, "%+d", offset); \
3304 else if (GET_CODE (index) == REG) \
3305 fprintf (FILE, "+%s", reg_names[REGNO (index)]); \
3306 else if (GET_CODE (index) == SYMBOL_REF \
3307 || GET_CODE (index) == CONST) \
3308 fputc ('+', FILE), output_addr_const (FILE, index); \
3312 else if (GET_CODE (addr) == MINUS \
3313 && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \
3315 output_addr_const (FILE, XEXP (addr, 0)); \
3316 fputs ("-(", FILE); \
3317 output_addr_const (FILE, XEXP (addr, 1)); \
3318 fputs ("-.)", FILE); \
3320 else if (GET_CODE (addr) == LO_SUM) \
3322 output_operand (XEXP (addr, 0), 0); \
3323 if (TARGET_CM_MEDMID) \
3324 fputs ("+%l44(", FILE); \
3326 fputs ("+%lo(", FILE); \
3327 output_address (XEXP (addr, 1)); \
3328 fputc (')', FILE); \
3330 else if (flag_pic && GET_CODE (addr) == CONST \
3331 && GET_CODE (XEXP (addr, 0)) == MINUS \
3332 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \
3333 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \
3334 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \
3336 addr = XEXP (addr, 0); \
3337 output_addr_const (FILE, XEXP (addr, 0)); \
3338 /* Group the args of the second CONST in parenthesis. */ \
3339 fputs ("-(", FILE); \
3340 /* Skip past the second CONST--it does nothing for us. */\
3341 output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \
3342 /* Close the parenthesis. */ \
3343 fputc (')', FILE); \
3347 output_addr_const (FILE, addr); \
3351 /* Define the codes that are matched by predicates in sparc.c. */
3353 #define PREDICATE_CODES \
3354 {"reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
3355 {"fp_zero_operand", {CONST_DOUBLE}}, \
3356 {"fp_sethi_p", {CONST_DOUBLE}}, \
3357 {"fp_mov_p", {CONST_DOUBLE}}, \
3358 {"fp_high_losum_p", {CONST_DOUBLE}}, \
3359 {"intreg_operand", {SUBREG, REG}}, \
3360 {"fcc_reg_operand", {REG}}, \
3361 {"icc_or_fcc_reg_operand", {REG}}, \
3362 {"restore_operand", {REG}}, \
3363 {"call_operand", {MEM}}, \
3364 {"call_operand_address", {SYMBOL_REF, LABEL_REF, CONST, CONST_DOUBLE, \
3365 ADDRESSOF, SUBREG, REG, PLUS, LO_SUM, CONST_INT}}, \
3366 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
3367 {"symbolic_memory_operand", {SUBREG, MEM}}, \
3368 {"label_ref_operand", {LABEL_REF}}, \
3369 {"sp64_medium_pic_operand", {CONST}}, \
3370 {"data_segment_operand", {SYMBOL_REF, PLUS, CONST}}, \
3371 {"text_segment_operand", {LABEL_REF, SYMBOL_REF, PLUS, CONST}}, \
3372 {"reg_or_nonsymb_mem_operand", {SUBREG, REG, MEM}}, \
3373 {"splittable_symbolic_memory_operand", {MEM}}, \
3374 {"splittable_immediate_memory_operand", {MEM}}, \
3375 {"eq_or_neq", {EQ, NE}}, \
3376 {"normal_comp_operator", {GE, GT, LE, LT, GTU, LEU}}, \
3377 {"noov_compare_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}}, \
3378 {"v9_regcmp_op", {EQ, NE, GE, LT, LE, GT}}, \
3379 {"extend_op", {SIGN_EXTEND, ZERO_EXTEND}}, \
3380 {"cc_arithop", {AND, IOR, XOR}}, \
3381 {"cc_arithopn", {AND, IOR}}, \
3382 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
3383 {"arith_add_operand", {SUBREG, REG, CONST_INT}}, \
3384 {"arith11_operand", {SUBREG, REG, CONST_INT}}, \
3385 {"arith10_operand", {SUBREG, REG, CONST_INT}}, \
3386 {"arith_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
3387 {"arith_double_add_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
3388 {"arith11_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
3389 {"arith10_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
3390 {"small_int", {CONST_INT}}, \
3391 {"small_int_or_double", {CONST_INT, CONST_DOUBLE}}, \
3392 {"uns_small_int", {CONST_INT}}, \
3393 {"uns_arith_operand", {SUBREG, REG, CONST_INT}}, \
3394 {"clobbered_register", {REG}}, \
3395 {"input_operand", {SUBREG, REG, CONST_INT, MEM, CONST}}, \
3396 {"const64_operand", {CONST_INT, CONST_DOUBLE}}, \
3397 {"const64_high_operand", {CONST_INT, CONST_DOUBLE}},
3399 /* The number of Pmode words for the setjmp buffer. */
3400 #define JMP_BUF_SIZE 12
3402 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (flag_pic)
3404 /* Defined in flags.h, but insn-emit.c does not include flags.h. */
3406 extern int flag_pic;