1 /* Definitions of target machine for GNU compiler, for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1994, 1995, 1996, 1997, 1998, 1999
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
5 Contributed by Michael Tiemann (tiemann@cygnus.com).
6 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING3. If not see
23 <http://www.gnu.org/licenses/>. */
25 #include "config/vxworks-dummy.h"
27 /* Note that some other tm.h files include this one and then override
28 whatever definitions are necessary. */
30 /* Define the specific costs for a given cpu */
32 struct processor_costs {
36 /* Integer signed load */
39 /* Integer zeroed load */
45 /* fmov, fneg, fabs */
49 const int float_plusminus;
55 const int float_cmove;
61 const int float_div_sf;
64 const int float_div_df;
67 const int float_sqrt_sf;
70 const int float_sqrt_df;
78 /* integer multiply cost for each bit set past the most
79 significant 3, so the formula for multiply cost becomes:
82 highest_bit = highest_clear_bit(rs1);
84 highest_bit = highest_set_bit(rs1);
87 cost = int_mul{,X} + ((highest_bit - 3) / int_mul_bit_factor);
89 A value of zero indicates that the multiply costs is fixed,
91 const int int_mul_bit_factor;
102 /* penalty for shifts, due to scheduling rules etc. */
103 const int shift_penalty;
106 extern const struct processor_costs *sparc_costs;
108 /* Target CPU builtins. FIXME: Defining sparc is for the benefit of
109 Solaris only; otherwise just define __sparc__. Sadly the headers
110 are such a mess there is no Solaris-specific header. */
111 #define TARGET_CPU_CPP_BUILTINS() \
114 builtin_define_std ("sparc"); \
117 builtin_assert ("cpu=sparc64"); \
118 builtin_assert ("machine=sparc64"); \
122 builtin_assert ("cpu=sparc"); \
123 builtin_assert ("machine=sparc"); \
128 /* Specify this in a cover file to provide bi-architecture (32/64) support. */
129 /* #define SPARC_BI_ARCH */
131 /* Macro used later in this file to determine default architecture. */
132 #define DEFAULT_ARCH32_P ((TARGET_DEFAULT & MASK_64BIT) == 0)
134 /* TARGET_ARCH{32,64} are the main macros to decide which of the two
135 architectures to compile for. We allow targets to choose compile time or
136 runtime selection. */
138 #if defined(__sparcv9) || defined(__arch64__)
139 #define TARGET_ARCH32 0
141 #define TARGET_ARCH32 1
145 #define TARGET_ARCH32 (! TARGET_64BIT)
147 #define TARGET_ARCH32 (DEFAULT_ARCH32_P)
148 #endif /* SPARC_BI_ARCH */
149 #endif /* IN_LIBGCC2 */
150 #define TARGET_ARCH64 (! TARGET_ARCH32)
152 /* Code model selection in 64-bit environment.
154 The machine mode used for addresses is 32-bit wide:
156 TARGET_CM_32: 32-bit address space.
157 It is the code model used when generating 32-bit code.
159 The machine mode used for addresses is 64-bit wide:
161 TARGET_CM_MEDLOW: 32-bit address space.
162 The executable must be in the low 32 bits of memory.
163 This avoids generating %uhi and %ulo terms. Programs
164 can be statically or dynamically linked.
166 TARGET_CM_MEDMID: 44-bit address space.
167 The executable must be in the low 44 bits of memory,
168 and the %[hml]44 terms are used. The text and data
169 segments have a maximum size of 2GB (31-bit span).
170 The maximum offset from any instruction to the label
171 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span).
173 TARGET_CM_MEDANY: 64-bit address space.
174 The text and data segments have a maximum size of 2GB
175 (31-bit span) and may be located anywhere in memory.
176 The maximum offset from any instruction to the label
177 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span).
179 TARGET_CM_EMBMEDANY: 64-bit address space.
180 The text and data segments have a maximum size of 2GB
181 (31-bit span) and may be located anywhere in memory.
182 The global register %g4 contains the start address of
183 the data segment. Programs are statically linked and
184 PIC is not supported.
186 Different code models are not supported in 32-bit environment. */
197 extern enum cmodel sparc_cmodel;
199 /* V9 code model selection. */
200 #define TARGET_CM_MEDLOW (sparc_cmodel == CM_MEDLOW)
201 #define TARGET_CM_MEDMID (sparc_cmodel == CM_MEDMID)
202 #define TARGET_CM_MEDANY (sparc_cmodel == CM_MEDANY)
203 #define TARGET_CM_EMBMEDANY (sparc_cmodel == CM_EMBMEDANY)
205 #define SPARC_DEFAULT_CMODEL CM_32
207 /* The SPARC-V9 architecture defines a relaxed memory ordering model (RMO)
208 which requires the following macro to be true if enabled. Prior to V9,
209 there are no instructions to even talk about memory synchronization.
210 Note that the UltraSPARC III processors don't implement RMO, unlike the
211 UltraSPARC II processors. Niagara and Niagara-2 do not implement RMO
214 Default to false; for example, Solaris never enables RMO, only ever uses
215 total memory ordering (TMO). */
216 #define SPARC_RELAXED_ORDERING false
218 /* Do not use the .note.GNU-stack convention by default. */
219 #define NEED_INDICATE_EXEC_STACK 0
221 /* This is call-clobbered in the normal ABI, but is reserved in the
222 home grown (aka upward compatible) embedded ABI. */
223 #define EMBMEDANY_BASE_REG "%g4"
225 /* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile,
226 and specified by the user via --with-cpu=foo.
227 This specifies the cpu implementation, not the architecture size. */
228 /* Note that TARGET_CPU_v9 is assumed to start the list of 64-bit
230 #define TARGET_CPU_sparc 0
231 #define TARGET_CPU_v7 0 /* alias */
232 #define TARGET_CPU_cypress 0 /* alias */
233 #define TARGET_CPU_v8 1 /* generic v8 implementation */
234 #define TARGET_CPU_supersparc 2
235 #define TARGET_CPU_hypersparc 3
236 #define TARGET_CPU_leon 4
237 #define TARGET_CPU_sparclite 5
238 #define TARGET_CPU_f930 5 /* alias */
239 #define TARGET_CPU_f934 5 /* alias */
240 #define TARGET_CPU_sparclite86x 6
241 #define TARGET_CPU_sparclet 7
242 #define TARGET_CPU_tsc701 7 /* alias */
243 #define TARGET_CPU_v9 8 /* generic v9 implementation */
244 #define TARGET_CPU_sparcv9 8 /* alias */
245 #define TARGET_CPU_sparc64 8 /* alias */
246 #define TARGET_CPU_ultrasparc 9
247 #define TARGET_CPU_ultrasparc3 10
248 #define TARGET_CPU_niagara 11
249 #define TARGET_CPU_niagara2 12
251 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
252 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \
253 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 \
254 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara \
255 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara2
257 #define CPP_CPU32_DEFAULT_SPEC ""
258 #define ASM_CPU32_DEFAULT_SPEC ""
260 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9
261 /* ??? What does Sun's CC pass? */
262 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
263 /* ??? It's not clear how other assemblers will handle this, so by default
264 use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case
265 is handled in sol2.h. */
266 #define ASM_CPU64_DEFAULT_SPEC "-Av9"
268 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc
269 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
270 #define ASM_CPU64_DEFAULT_SPEC "-Av9a"
272 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3
273 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
274 #define ASM_CPU64_DEFAULT_SPEC "-Av9b"
276 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara
277 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
278 #define ASM_CPU64_DEFAULT_SPEC "-Av9b"
280 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara2
281 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
282 #define ASM_CPU64_DEFAULT_SPEC "-Av9b"
287 #define CPP_CPU64_DEFAULT_SPEC ""
288 #define ASM_CPU64_DEFAULT_SPEC ""
290 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc \
291 || TARGET_CPU_DEFAULT == TARGET_CPU_v8
292 #define CPP_CPU32_DEFAULT_SPEC ""
293 #define ASM_CPU32_DEFAULT_SPEC ""
296 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet
297 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclet__"
298 #define ASM_CPU32_DEFAULT_SPEC "-Asparclet"
301 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite
302 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite__"
303 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
306 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite86x
307 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite86x__"
308 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
311 #if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc
312 #define CPP_CPU32_DEFAULT_SPEC "-D__supersparc__ -D__sparc_v8__"
313 #define ASM_CPU32_DEFAULT_SPEC ""
316 #if TARGET_CPU_DEFAULT == TARGET_CPU_hypersparc
317 #define CPP_CPU32_DEFAULT_SPEC "-D__hypersparc__ -D__sparc_v8__"
318 #define ASM_CPU32_DEFAULT_SPEC ""
321 #if TARGET_CPU_DEFAULT == TARGET_CPU_leon
322 #define CPP_CPU32_DEFAULT_SPEC "-D__leon__ -D__sparc_v8__"
323 #define ASM_CPU32_DEFAULT_SPEC ""
328 #if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC)
329 #error Unrecognized value in TARGET_CPU_DEFAULT.
334 #define CPP_CPU_DEFAULT_SPEC \
335 (DEFAULT_ARCH32_P ? "\
336 %{m64:" CPP_CPU64_DEFAULT_SPEC "} \
337 %{!m64:" CPP_CPU32_DEFAULT_SPEC "} \
339 %{m32:" CPP_CPU32_DEFAULT_SPEC "} \
340 %{!m32:" CPP_CPU64_DEFAULT_SPEC "} \
342 #define ASM_CPU_DEFAULT_SPEC \
343 (DEFAULT_ARCH32_P ? "\
344 %{m64:" ASM_CPU64_DEFAULT_SPEC "} \
345 %{!m64:" ASM_CPU32_DEFAULT_SPEC "} \
347 %{m32:" ASM_CPU32_DEFAULT_SPEC "} \
348 %{!m32:" ASM_CPU64_DEFAULT_SPEC "} \
351 #else /* !SPARC_BI_ARCH */
353 #define CPP_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? CPP_CPU32_DEFAULT_SPEC : CPP_CPU64_DEFAULT_SPEC)
354 #define ASM_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? ASM_CPU32_DEFAULT_SPEC : ASM_CPU64_DEFAULT_SPEC)
356 #endif /* !SPARC_BI_ARCH */
358 /* Define macros to distinguish architectures. */
360 /* Common CPP definitions used by CPP_SPEC amongst the various targets
361 for handling -mcpu=xxx switches. */
362 #define CPP_CPU_SPEC "\
363 %{msoft-float:-D_SOFT_FLOAT} \
364 %{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \
365 %{mcpu=sparclite:-D__sparclite__} \
366 %{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \
367 %{mcpu=sparclite86x:-D__sparclite86x__} \
368 %{mcpu=v8:-D__sparc_v8__} \
369 %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \
370 %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \
371 %{mcpu=leon:-D__leon__ -D__sparc_v8__} \
372 %{mcpu=v9:-D__sparc_v9__} \
373 %{mcpu=ultrasparc:-D__sparc_v9__} \
374 %{mcpu=ultrasparc3:-D__sparc_v9__} \
375 %{mcpu=niagara:-D__sparc_v9__} \
376 %{mcpu=niagara2:-D__sparc_v9__} \
377 %{!mcpu*:%(cpp_cpu_default)} \
379 #define CPP_ARCH32_SPEC ""
380 #define CPP_ARCH64_SPEC "-D__arch64__"
382 #define CPP_ARCH_DEFAULT_SPEC \
383 (DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC)
385 #define CPP_ARCH_SPEC "\
386 %{m32:%(cpp_arch32)} \
387 %{m64:%(cpp_arch64)} \
388 %{!m32:%{!m64:%(cpp_arch_default)}} \
391 /* Macros to distinguish endianness. */
392 #define CPP_ENDIAN_SPEC "\
393 %{mlittle-endian:-D__LITTLE_ENDIAN__} \
394 %{mlittle-endian-data:-D__LITTLE_ENDIAN_DATA__}"
396 /* Macros to distinguish the particular subtarget. */
397 #define CPP_SUBTARGET_SPEC ""
399 #define CPP_SPEC "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_subtarget)"
401 /* Prevent error on `-sun4' and `-target sun4' options. */
402 /* This used to translate -dalign to -malign, but that is no good
403 because it can't turn off the usual meaning of making debugging dumps. */
404 /* Translate old style -m<cpu> into new style -mcpu=<cpu>.
405 ??? Delete support for -m<cpu> for 2.9. */
408 %{sun4:} %{target:} \
411 /* Override in target specific files. */
412 #define ASM_CPU_SPEC "\
413 %{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \
414 %{mcpu=sparclite:-Asparclite} \
415 %{mcpu=sparclite86x:-Asparclite} \
416 %{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \
417 %{mv8plus:-Av8plus} \
419 %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \
420 %{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \
421 %{mcpu=niagara:%{!mv8plus:-Av9b}} \
422 %{mcpu=niagara2:%{!mv8plus:-Av9b}} \
423 %{!mcpu*:%(asm_cpu_default)} \
426 /* Word size selection, among other things.
427 This is what GAS uses. Add %(asm_arch) to ASM_SPEC to enable. */
429 #define ASM_ARCH32_SPEC "-32"
430 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
431 #define ASM_ARCH64_SPEC "-64 -no-undeclared-regs"
433 #define ASM_ARCH64_SPEC "-64"
435 #define ASM_ARCH_DEFAULT_SPEC \
436 (DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC)
438 #define ASM_ARCH_SPEC "\
439 %{m32:%(asm_arch32)} \
440 %{m64:%(asm_arch64)} \
441 %{!m32:%{!m64:%(asm_arch_default)}} \
444 #ifdef HAVE_AS_RELAX_OPTION
445 #define ASM_RELAX_SPEC "%{!mno-relax:-relax}"
447 #define ASM_RELAX_SPEC ""
450 /* Special flags to the Sun-4 assembler when using pipe for input. */
453 %{!pg:%{!p:%{fpic|fPIC|fpie|fPIE:-k}}} %{keep-local-as-symbols:-L} \
454 %(asm_cpu) %(asm_relax)"
456 /* This macro defines names of additional specifications to put in the specs
457 that can be used in various specifications like CC1_SPEC. Its definition
458 is an initializer with a subgrouping for each command option.
460 Each subgrouping contains a string constant, that defines the
461 specification name, and a string constant that used by the GCC driver
464 Do not define this macro if it does not need to do anything. */
466 #define EXTRA_SPECS \
467 { "cpp_cpu", CPP_CPU_SPEC }, \
468 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
469 { "cpp_arch32", CPP_ARCH32_SPEC }, \
470 { "cpp_arch64", CPP_ARCH64_SPEC }, \
471 { "cpp_arch_default", CPP_ARCH_DEFAULT_SPEC },\
472 { "cpp_arch", CPP_ARCH_SPEC }, \
473 { "cpp_endian", CPP_ENDIAN_SPEC }, \
474 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \
475 { "asm_cpu", ASM_CPU_SPEC }, \
476 { "asm_cpu_default", ASM_CPU_DEFAULT_SPEC }, \
477 { "asm_arch32", ASM_ARCH32_SPEC }, \
478 { "asm_arch64", ASM_ARCH64_SPEC }, \
479 { "asm_relax", ASM_RELAX_SPEC }, \
480 { "asm_arch_default", ASM_ARCH_DEFAULT_SPEC },\
481 { "asm_arch", ASM_ARCH_SPEC }, \
482 SUBTARGET_EXTRA_SPECS
484 #define SUBTARGET_EXTRA_SPECS
486 /* Because libgcc can generate references back to libc (via .umul etc.) we have
487 to list libc again after the second libgcc. */
488 #define LINK_GCC_C_SEQUENCE_SPEC "%G %L %G %L"
491 #define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int")
492 #define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int")
494 /* ??? This should be 32 bits for v9 but what can we do? */
495 #define WCHAR_TYPE "short unsigned int"
496 #define WCHAR_TYPE_SIZE 16
498 /* Mask of all CPU selection flags. */
500 (MASK_V8 + MASK_SPARCLITE + MASK_SPARCLET + MASK_V9 + MASK_DEPRECATED_V8_INSNS)
502 /* TARGET_HARD_MUL: Use hardware multiply instructions but not %y.
503 TARGET_HARD_MUL32: Use hardware multiply instructions with rd %y
504 to get high 32 bits. False in V8+ or V9 because multiply stores
505 a 64-bit result in a register. */
507 #define TARGET_HARD_MUL32 \
508 ((TARGET_V8 || TARGET_SPARCLITE \
509 || TARGET_SPARCLET || TARGET_DEPRECATED_V8_INSNS) \
510 && ! TARGET_V8PLUS && TARGET_ARCH32)
512 #define TARGET_HARD_MUL \
513 (TARGET_V8 || TARGET_SPARCLITE || TARGET_SPARCLET \
514 || TARGET_DEPRECATED_V8_INSNS || TARGET_V8PLUS)
516 /* MASK_APP_REGS must always be the default because that's what
517 FIXED_REGISTERS is set to and -ffixed- is processed before
518 TARGET_CONDITIONAL_REGISTER_USAGE is called (where we process
520 #define TARGET_DEFAULT (MASK_APP_REGS + MASK_FPU)
523 These must match the values for the cpu attribute in sparc.md. */
524 enum processor_type {
528 PROCESSOR_SUPERSPARC,
529 PROCESSOR_HYPERSPARC,
534 PROCESSOR_SPARCLITE86X,
538 PROCESSOR_ULTRASPARC,
539 PROCESSOR_ULTRASPARC3,
544 /* This is set from -m{cpu,tune}=xxx. */
545 extern enum processor_type sparc_cpu;
547 /* Recast the cpu class to be the cpu attribute.
548 Every file includes us, but not every file includes insn-attr.h. */
549 #define sparc_cpu_attr ((enum attr_cpu) sparc_cpu)
551 /* Support for a compile-time default CPU, et cetera. The rules are:
552 --with-cpu is ignored if -mcpu is specified.
553 --with-tune is ignored if -mtune is specified.
554 --with-float is ignored if -mhard-float, -msoft-float, -mfpu, or -mno-fpu
556 #define OPTION_DEFAULT_SPECS \
557 {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \
558 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
559 {"float", "%{!msoft-float:%{!mhard-float:%{!fpu:%{!no-fpu:-m%(VALUE)-float}}}}" }
561 /* sparc_select[0] is reserved for the default cpu. */
562 struct sparc_cpu_select
565 const char *const name;
566 const int set_tune_p;
567 const int set_arch_p;
570 extern struct sparc_cpu_select sparc_select[];
572 /* target machine storage layout */
574 /* Define this if most significant bit is lowest numbered
575 in instructions that operate on numbered bit-fields. */
576 #define BITS_BIG_ENDIAN 1
578 /* Define this if most significant byte of a word is the lowest numbered. */
579 #define BYTES_BIG_ENDIAN 1
581 /* Define this if most significant word of a multiword number is the lowest
583 #define WORDS_BIG_ENDIAN 1
585 #define MAX_BITS_PER_WORD 64
587 /* Width of a word, in units (bytes). */
588 #define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4)
590 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
592 #define MIN_UNITS_PER_WORD 4
595 /* Now define the sizes of the C data types. */
597 #define SHORT_TYPE_SIZE 16
598 #define INT_TYPE_SIZE 32
599 #define LONG_TYPE_SIZE (TARGET_ARCH64 ? 64 : 32)
600 #define LONG_LONG_TYPE_SIZE 64
601 #define FLOAT_TYPE_SIZE 32
602 #define DOUBLE_TYPE_SIZE 64
604 /* LONG_DOUBLE_TYPE_SIZE is defined per OS even though the
605 SPARC ABI says that it is 128-bit wide. */
606 /* #define LONG_DOUBLE_TYPE_SIZE 128 */
608 /* The widest floating-point format really supported by the hardware. */
609 #define WIDEST_HARDWARE_FP_SIZE 64
611 /* Width in bits of a pointer. This is the size of ptr_mode. */
612 #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32)
614 /* This is the machine mode used for addresses. */
615 #define Pmode (TARGET_ARCH64 ? DImode : SImode)
617 /* If we have to extend pointers (only when TARGET_ARCH64 and not
618 TARGET_PTR64), we want to do it unsigned. This macro does nothing
619 if ptr_mode and Pmode are the same. */
620 #define POINTERS_EXTEND_UNSIGNED 1
622 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
623 #define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
625 /* Boundary (in *bits*) on which stack pointer should be aligned. */
626 /* FIXME, this is wrong when TARGET_ARCH64 and TARGET_STACK_BIAS, because
627 then %sp+2047 is 128-bit aligned so %sp is really only byte-aligned. */
628 #define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64)
629 /* Temporary hack until the FIXME above is fixed. */
630 #define SPARC_STACK_BOUNDARY_HACK (TARGET_ARCH64 && TARGET_STACK_BIAS)
632 /* ALIGN FRAMES on double word boundaries */
634 #define SPARC_STACK_ALIGN(LOC) \
635 (TARGET_ARCH64 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7))
637 /* Allocation boundary (in *bits*) for the code of a function. */
638 #define FUNCTION_BOUNDARY 32
640 /* Alignment of field after `int : 0' in a structure. */
641 #define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
643 /* Every structure's size must be a multiple of this. */
644 #define STRUCTURE_SIZE_BOUNDARY 8
646 /* A bit-field declared as `int' forces `int' alignment for the struct. */
647 #define PCC_BITFIELD_TYPE_MATTERS 1
649 /* No data type wants to be aligned rounder than this. */
650 #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64)
652 /* The best alignment to use in cases where we have a choice. */
653 #define FASTEST_ALIGNMENT 64
655 /* Define this macro as an expression for the alignment of a structure
656 (given by STRUCT as a tree node) if the alignment computed in the
657 usual way is COMPUTED and the alignment explicitly specified was
660 The default is to use SPECIFIED if it is larger; otherwise, use
661 the smaller of COMPUTED and `BIGGEST_ALIGNMENT' */
662 #define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \
663 (TARGET_FASTER_STRUCTS ? \
664 ((TREE_CODE (STRUCT) == RECORD_TYPE \
665 || TREE_CODE (STRUCT) == UNION_TYPE \
666 || TREE_CODE (STRUCT) == QUAL_UNION_TYPE) \
667 && TYPE_FIELDS (STRUCT) != 0 \
668 ? MAX (MAX ((COMPUTED), (SPECIFIED)), BIGGEST_ALIGNMENT) \
669 : MAX ((COMPUTED), (SPECIFIED))) \
670 : MAX ((COMPUTED), (SPECIFIED)))
672 /* Make strings word-aligned so strcpy from constants will be faster. */
673 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
674 ((TREE_CODE (EXP) == STRING_CST \
675 && (ALIGN) < FASTEST_ALIGNMENT) \
676 ? FASTEST_ALIGNMENT : (ALIGN))
678 /* Make arrays of chars word-aligned for the same reasons. */
679 #define DATA_ALIGNMENT(TYPE, ALIGN) \
680 (TREE_CODE (TYPE) == ARRAY_TYPE \
681 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
682 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
684 /* Make local arrays of chars word-aligned for the same reasons. */
685 #define LOCAL_ALIGNMENT(TYPE, ALIGN) DATA_ALIGNMENT (TYPE, ALIGN)
687 /* Set this nonzero if move instructions will actually fail to work
688 when given unaligned data. */
689 #define STRICT_ALIGNMENT 1
691 /* Things that must be doubleword aligned cannot go in the text section,
692 because the linker fails to align the text section enough!
693 Put them in the data section. This macro is only used in this file. */
694 #define MAX_TEXT_ALIGN 32
696 /* Standard register usage. */
698 /* Number of actual hardware registers.
699 The hardware registers are assigned numbers for the compiler
700 from 0 to just below FIRST_PSEUDO_REGISTER.
701 All registers that the compiler knows about must be given numbers,
702 even those that are not normally considered general registers.
704 SPARC has 32 integer registers and 32 floating point registers.
705 64-bit SPARC has 32 additional fp regs, but the odd numbered ones are not
706 accessible. We still account for them to simplify register computations
707 (e.g.: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so
709 Register 100 is used as the integer condition code register.
710 Register 101 is used as the soft frame pointer register. */
712 #define FIRST_PSEUDO_REGISTER 102
714 #define SPARC_FIRST_FP_REG 32
715 /* Additional V9 fp regs. */
716 #define SPARC_FIRST_V9_FP_REG 64
717 #define SPARC_LAST_V9_FP_REG 95
718 /* V9 %fcc[0123]. V8 uses (figuratively) %fcc0. */
719 #define SPARC_FIRST_V9_FCC_REG 96
720 #define SPARC_LAST_V9_FCC_REG 99
722 #define SPARC_FCC_REG 96
723 /* Integer CC reg. We don't distinguish %icc from %xcc. */
724 #define SPARC_ICC_REG 100
726 /* Nonzero if REGNO is an fp reg. */
727 #define SPARC_FP_REG_P(REGNO) \
728 ((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG)
730 /* Argument passing regs. */
731 #define SPARC_OUTGOING_INT_ARG_FIRST 8
732 #define SPARC_INCOMING_INT_ARG_FIRST 24
733 #define SPARC_FP_ARG_FIRST 32
735 /* 1 for registers that have pervasive standard uses
736 and are not available for the register allocator.
739 g1 is free to use as temporary.
740 g2-g4 are reserved for applications. Gcc normally uses them as
741 temporaries, but this can be disabled via the -mno-app-regs option.
742 g5 through g7 are reserved for the operating system.
745 g1,g5 are free to use as temporaries, and are free to use between calls
746 if the call is to an external function via the PLT.
747 g4 is free to use as a temporary in the non-embedded case.
748 g4 is reserved in the embedded case.
749 g2-g3 are reserved for applications. Gcc normally uses them as
750 temporaries, but this can be disabled via the -mno-app-regs option.
751 g6-g7 are reserved for the operating system (or application in
753 ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must
754 currently be a fixed register until this pattern is rewritten.
755 Register 1 is also used when restoring call-preserved registers in large
758 Registers fixed in arch32 and not arch64 (or vice-versa) are marked in
759 TARGET_CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-.
762 #define FIXED_REGISTERS \
763 {1, 0, 2, 2, 2, 2, 1, 1, \
764 0, 0, 0, 0, 0, 0, 1, 0, \
765 0, 0, 0, 0, 0, 0, 0, 0, \
766 0, 0, 0, 0, 0, 0, 1, 1, \
768 0, 0, 0, 0, 0, 0, 0, 0, \
769 0, 0, 0, 0, 0, 0, 0, 0, \
770 0, 0, 0, 0, 0, 0, 0, 0, \
771 0, 0, 0, 0, 0, 0, 0, 0, \
773 0, 0, 0, 0, 0, 0, 0, 0, \
774 0, 0, 0, 0, 0, 0, 0, 0, \
775 0, 0, 0, 0, 0, 0, 0, 0, \
776 0, 0, 0, 0, 0, 0, 0, 0, \
780 /* 1 for registers not available across function calls.
781 These must include the FIXED_REGISTERS and also any
782 registers that can be used without being saved.
783 The latter must include the registers where values are returned
784 and the register where structure-value addresses are passed.
785 Aside from that, you can include as many other registers as you like. */
787 #define CALL_USED_REGISTERS \
788 {1, 1, 1, 1, 1, 1, 1, 1, \
789 1, 1, 1, 1, 1, 1, 1, 1, \
790 0, 0, 0, 0, 0, 0, 0, 0, \
791 0, 0, 0, 0, 0, 0, 1, 1, \
793 1, 1, 1, 1, 1, 1, 1, 1, \
794 1, 1, 1, 1, 1, 1, 1, 1, \
795 1, 1, 1, 1, 1, 1, 1, 1, \
796 1, 1, 1, 1, 1, 1, 1, 1, \
798 1, 1, 1, 1, 1, 1, 1, 1, \
799 1, 1, 1, 1, 1, 1, 1, 1, \
800 1, 1, 1, 1, 1, 1, 1, 1, \
801 1, 1, 1, 1, 1, 1, 1, 1, \
805 /* Return number of consecutive hard regs needed starting at reg REGNO
806 to hold something of mode MODE.
807 This is ordinarily the length in words of a value of mode MODE
808 but can be less for certain modes in special long registers.
810 On SPARC, ordinary registers hold 32 bits worth;
811 this means both integer and floating point registers.
812 On v9, integer regs hold 64 bits worth; floating point regs hold
813 32 bits worth (this includes the new fp regs as even the odd ones are
814 included in the hard register count). */
816 #define HARD_REGNO_NREGS(REGNO, MODE) \
818 ? ((REGNO) < 32 || (REGNO) == FRAME_POINTER_REGNUM \
819 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \
820 : (GET_MODE_SIZE (MODE) + 3) / 4) \
821 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
823 /* Due to the ARCH64 discrepancy above we must override this next
825 #define REGMODE_NATURAL_SIZE(MODE) \
826 ((TARGET_ARCH64 && FLOAT_MODE_P (MODE)) ? 4 : UNITS_PER_WORD)
828 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
829 See sparc.c for how we initialize this. */
830 extern const int *hard_regno_mode_classes;
831 extern int sparc_mode_class[];
833 /* ??? Because of the funny way we pass parameters we should allow certain
834 ??? types of float/complex values to be in integer registers during
835 ??? RTL generation. This only matters on arch32. */
836 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
837 ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0)
839 /* Value is 1 if it is OK to rename a hard register FROM to another hard
840 register TO. We cannot rename %g1 as it may be used before the save
841 register window instruction in the prologue. */
842 #define HARD_REGNO_RENAME_OK(FROM, TO) ((FROM) != 1)
844 /* Value is 1 if it is a good idea to tie two pseudo registers
845 when one has mode MODE1 and one has mode MODE2.
846 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
847 for any hard reg, then this must be 0 for correct output.
849 For V9: SFmode can't be combined with other float modes, because they can't
850 be allocated to the %d registers. Also, DFmode won't fit in odd %f
851 registers, but SFmode will. */
852 #define MODES_TIEABLE_P(MODE1, MODE2) \
853 ((MODE1) == (MODE2) \
854 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
856 || (GET_MODE_CLASS (MODE1) != MODE_FLOAT \
857 || (MODE1 != SFmode && MODE2 != SFmode)))))
859 /* Specify the registers used for certain standard purposes.
860 The values of these macros are register numbers. */
862 /* Register to use for pushing function arguments. */
863 #define STACK_POINTER_REGNUM 14
865 /* The stack bias (amount by which the hardware register is offset by). */
866 #define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0)
868 /* Actual top-of-stack address is 92/176 greater than the contents of the
869 stack pointer register for !v9/v9. That is:
870 - !v9: 64 bytes for the in and local registers, 4 bytes for structure return
871 address, and 6*4 bytes for the 6 register parameters.
872 - v9: 128 bytes for the in and local registers + 6*8 bytes for the integer
874 #define STACK_POINTER_OFFSET (FIRST_PARM_OFFSET(0) + SPARC_STACK_BIAS)
876 /* Base register for access to local variables of the function. */
877 #define HARD_FRAME_POINTER_REGNUM 30
879 /* The soft frame pointer does not have the stack bias applied. */
880 #define FRAME_POINTER_REGNUM 101
882 /* Given the stack bias, the stack pointer isn't actually aligned. */
883 #define INIT_EXPANDERS \
885 if (crtl->emit.regno_pointer_align && SPARC_STACK_BIAS) \
887 REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = BITS_PER_UNIT; \
888 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT; \
892 /* Base register for access to arguments of the function. */
893 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM
895 /* Register in which static-chain is passed to a function. This must
896 not be a register used by the prologue. */
897 #define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2)
899 /* Register which holds the global offset table, if any. */
901 #define GLOBAL_OFFSET_TABLE_REGNUM 23
903 /* Register which holds offset table for position-independent
906 #define PIC_OFFSET_TABLE_REGNUM \
907 (flag_pic ? GLOBAL_OFFSET_TABLE_REGNUM : INVALID_REGNUM)
909 /* Pick a default value we can notice from override_options:
912 Originally it was -1, but later on the container of options changed to
913 unsigned byte, so we decided to pick 127 as default value, which does
914 reflect an undefined default value in case of 0/1. */
916 #define DEFAULT_PCC_STRUCT_RETURN 127
918 /* Functions which return large structures get the address
919 to place the wanted value at offset 64 from the frame.
920 Must reserve 64 bytes for the in and local registers.
921 v9: Functions which return large structures get the address to place the
922 wanted value from an invisible first argument. */
923 #define STRUCT_VALUE_OFFSET 64
925 /* Define the classes of registers for register constraints in the
926 machine description. Also define ranges of constants.
928 One of the classes must always be named ALL_REGS and include all hard regs.
929 If there is more than one class, another class must be named NO_REGS
930 and contain no registers.
932 The name GENERAL_REGS must be the name of a class (or an alias for
933 another name such as ALL_REGS). This is the class of registers
934 that is allowed by "g" or "r" in a register constraint.
935 Also, registers outside this class are allocated only when
936 instructions express preferences for them.
938 The classes must be numbered in nondecreasing order; that is,
939 a larger-numbered class must never be contained completely
940 in a smaller-numbered class.
942 For any two classes, it is very desirable that there be another
943 class that represents their union. */
945 /* The SPARC has various kinds of registers: general, floating point,
946 and condition codes [well, it has others as well, but none that we
947 care directly about].
949 For v9 we must distinguish between the upper and lower floating point
950 registers because the upper ones can't hold SFmode values.
951 HARD_REGNO_MODE_OK won't help here because reload assumes that register(s)
952 satisfying a group need for a class will also satisfy a single need for
953 that class. EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp
956 It is important that one class contains all the general and all the standard
957 fp regs. Otherwise find_reg() won't properly allocate int regs for moves,
958 because reg_class_record() will bias the selection in favor of fp regs,
959 because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS,
960 because FP_REGS > GENERAL_REGS.
962 It is also important that one class contain all the general and all
963 the fp regs. Otherwise when spilling a DFmode reg, it may be from
964 EXTRA_FP_REGS but find_reloads() may use class
965 GENERAL_OR_FP_REGS. This will cause allocate_reload_reg() to die
966 because the compiler thinks it doesn't have a spill reg when in
969 v9 also has 4 floating point condition code registers. Since we don't
970 have a class that is the union of FPCC_REGS with either of the others,
971 it is important that it appear first. Otherwise the compiler will die
972 trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its
975 It is important that SPARC_ICC_REG have class NO_REGS. Otherwise combine
976 may try to use it to hold an SImode value. See register_operand.
977 ??? Should %fcc[0123] be handled similarly?
980 enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS,
981 EXTRA_FP_REGS, GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS,
982 ALL_REGS, LIM_REG_CLASSES };
984 #define N_REG_CLASSES (int) LIM_REG_CLASSES
986 /* Give names of register classes as strings for dump file. */
988 #define REG_CLASS_NAMES \
989 { "NO_REGS", "FPCC_REGS", "I64_REGS", "GENERAL_REGS", "FP_REGS", \
990 "EXTRA_FP_REGS", "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", \
993 /* Define which registers fit in which classes.
994 This is an initializer for a vector of HARD_REG_SET
995 of length N_REG_CLASSES. */
997 #define REG_CLASS_CONTENTS \
998 {{0, 0, 0, 0}, /* NO_REGS */ \
999 {0, 0, 0, 0xf}, /* FPCC_REGS */ \
1000 {0xffff, 0, 0, 0}, /* I64_REGS */ \
1001 {-1, 0, 0, 0x20}, /* GENERAL_REGS */ \
1002 {0, -1, 0, 0}, /* FP_REGS */ \
1003 {0, -1, -1, 0}, /* EXTRA_FP_REGS */ \
1004 {-1, -1, 0, 0x20}, /* GENERAL_OR_FP_REGS */ \
1005 {-1, -1, -1, 0x20}, /* GENERAL_OR_EXTRA_FP_REGS */ \
1006 {-1, -1, -1, 0x3f}} /* ALL_REGS */
1008 /* The same information, inverted:
1009 Return the class number of the smallest class containing
1010 reg number REGNO. This could be a conditional expression
1011 or could index an array. */
1013 extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
1015 #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)]
1017 /* The following macro defines cover classes for Integrated Register
1018 Allocator. Cover classes is a set of non-intersected register
1019 classes covering all hard registers used for register allocation
1020 purpose. Any move between two registers of a cover class should be
1021 cheaper than load or store of the registers. The macro value is
1022 array of register classes with LIM_REG_CLASSES used as the end
1025 #define IRA_COVER_CLASSES \
1027 GENERAL_REGS, EXTRA_FP_REGS, FPCC_REGS, LIM_REG_CLASSES \
1030 /* Defines invalid mode changes. Borrowed from pa64-regs.h.
1032 SImode loads to floating-point registers are not zero-extended.
1033 The definition for LOAD_EXTEND_OP specifies that integer loads
1034 narrower than BITS_PER_WORD will be zero-extended. As a result,
1035 we inhibit changes from SImode unless they are to a mode that is
1036 identical in size. */
1038 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1040 && (FROM) == SImode \
1041 && GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1042 ? reg_classes_intersect_p (CLASS, FP_REGS) : 0)
1044 /* This is the order in which to allocate registers normally.
1046 We put %f0-%f7 last among the float registers, so as to make it more
1047 likely that a pseudo-register which dies in the float return register
1048 area will get allocated to the float return register, thus saving a move
1049 instruction at the end of the function.
1051 Similarly for integer return value registers.
1053 We know in this case that we will not end up with a leaf function.
1055 The register allocator is given the global and out registers first
1056 because these registers are call clobbered and thus less useful to
1057 global register allocation.
1059 Next we list the local and in registers. They are not call clobbered
1060 and thus very useful for global register allocation. We list the input
1061 registers before the locals so that it is more likely the incoming
1062 arguments received in those registers can just stay there and not be
1065 #define REG_ALLOC_ORDER \
1066 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \
1067 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \
1069 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \
1070 29, 28, 27, 26, 25, 24, 31, /* %i5-%i0,%i7 */\
1071 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \
1072 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \
1073 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \
1074 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \
1075 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \
1076 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \
1077 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \
1078 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \
1079 96, 97, 98, 99, /* %fcc0-3 */ \
1080 100, 0, 14, 30, 101} /* %icc, %g0, %o6, %i6, %sfp */
1082 /* This is the order in which to allocate registers for
1083 leaf functions. If all registers can fit in the global and
1084 output registers, then we have the possibility of having a leaf
1087 The macro actually mentioned the input registers first,
1088 because they get renumbered into the output registers once
1089 we know really do have a leaf function.
1091 To be more precise, this register allocation order is used
1092 when %o7 is found to not be clobbered right before register
1093 allocation. Normally, the reason %o7 would be clobbered is
1094 due to a call which could not be transformed into a sibling
1097 As a consequence, it is possible to use the leaf register
1098 allocation order and not end up with a leaf function. We will
1099 not get suboptimal register allocation in that case because by
1100 definition of being potentially leaf, there were no function
1101 calls. Therefore, allocation order within the local register
1102 window is not critical like it is when we do have function calls. */
1104 #define REG_LEAF_ALLOC_ORDER \
1105 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \
1106 29, 28, 27, 26, 25, 24, /* %i5-%i0 */ \
1108 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \
1109 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \
1110 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \
1111 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \
1112 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \
1113 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \
1114 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \
1115 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \
1116 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \
1117 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \
1118 96, 97, 98, 99, /* %fcc0-3 */ \
1119 100, 0, 14, 30, 31, 101} /* %icc, %g0, %o6, %i6, %i7, %sfp */
1121 #define ADJUST_REG_ALLOC_ORDER order_regs_for_local_alloc ()
1123 extern char sparc_leaf_regs[];
1124 #define LEAF_REGISTERS sparc_leaf_regs
1126 extern char leaf_reg_remap[];
1127 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO])
1129 /* The class value for index registers, and the one for base regs. */
1130 #define INDEX_REG_CLASS GENERAL_REGS
1131 #define BASE_REG_CLASS GENERAL_REGS
1133 /* Local macro to handle the two v9 classes of FP regs. */
1134 #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS)
1136 /* Predicates for 10-bit, 11-bit and 13-bit signed constants. */
1137 #define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400)
1138 #define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800)
1139 #define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000)
1141 /* 10- and 11-bit immediates are only used for a few specific insns.
1142 SMALL_INT is used throughout the port so we continue to use it. */
1143 #define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X)))
1145 /* Predicate for constants that can be loaded with a sethi instruction.
1146 This is the general, 64-bit aware, bitwise version that ensures that
1147 only constants whose representation fits in the mask
1151 are accepted. It will reject, for example, negative SImode constants
1152 on 64-bit hosts, so correct handling is to mask the value beforehand
1153 according to the mode of the instruction. */
1154 #define SPARC_SETHI_P(X) \
1155 (((unsigned HOST_WIDE_INT) (X) \
1156 & ((unsigned HOST_WIDE_INT) 0x3ff - GET_MODE_MASK (SImode) - 1)) == 0)
1158 /* Version of the above predicate for SImode constants and below. */
1159 #define SPARC_SETHI32_P(X) \
1160 (SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode)))
1162 /* Given an rtx X being reloaded into a reg required to be
1163 in class CLASS, return the class of reg to actually use.
1164 In general this is just CLASS; but on some machines
1165 in some cases it is preferable to use a more restrictive class. */
1166 /* - We can't load constants into FP registers.
1167 - We can't load FP constants into integer registers when soft-float,
1168 because there is no soft-float pattern with a r/F constraint.
1169 - We can't load FP constants into integer registers for TFmode unless
1170 it is 0.0L, because there is no movtf pattern with a r/F constraint.
1171 - Try and reload integer constants (symbolic or otherwise) back into
1172 registers directly, rather than having them dumped to memory. */
1174 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1176 ? ((FP_REG_CLASS_P (CLASS) \
1177 || (CLASS) == GENERAL_OR_FP_REGS \
1178 || (CLASS) == GENERAL_OR_EXTRA_FP_REGS \
1179 || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1181 || (GET_MODE (X) == TFmode \
1182 && ! const_zero_operand (X, TFmode))) \
1184 : (!FP_REG_CLASS_P (CLASS) \
1185 && GET_MODE_CLASS (GET_MODE (X)) == MODE_INT) \
1190 /* Return the register class of a scratch register needed to load IN into
1191 a register of class CLASS in MODE.
1193 We need a temporary when loading/storing a HImode/QImode value
1194 between memory and the FPU registers. This can happen when combine puts
1195 a paradoxical subreg in a float/fix conversion insn.
1197 We need a temporary when loading/storing a DFmode value between
1198 unaligned memory and the upper FPU registers. */
1200 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1201 ((FP_REG_CLASS_P (CLASS) \
1202 && ((MODE) == HImode || (MODE) == QImode) \
1203 && (GET_CODE (IN) == MEM \
1204 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1205 && true_regnum (IN) == -1))) \
1207 : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \
1208 && GET_CODE (IN) == MEM && TARGET_ARCH32 \
1209 && ! mem_min_alignment ((IN), 8)) \
1211 : (((TARGET_CM_MEDANY \
1212 && symbolic_operand ((IN), (MODE))) \
1213 || (TARGET_CM_EMBMEDANY \
1214 && text_segment_operand ((IN), (MODE)))) \
1219 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1220 ((FP_REG_CLASS_P (CLASS) \
1221 && ((MODE) == HImode || (MODE) == QImode) \
1222 && (GET_CODE (IN) == MEM \
1223 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1224 && true_regnum (IN) == -1))) \
1226 : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \
1227 && GET_CODE (IN) == MEM && TARGET_ARCH32 \
1228 && ! mem_min_alignment ((IN), 8)) \
1230 : (((TARGET_CM_MEDANY \
1231 && symbolic_operand ((IN), (MODE))) \
1232 || (TARGET_CM_EMBMEDANY \
1233 && text_segment_operand ((IN), (MODE)))) \
1238 /* On SPARC it is not possible to directly move data between
1239 GENERAL_REGS and FP_REGS. */
1240 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1241 (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2))
1243 /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9
1244 because the movsi and movsf patterns don't handle r/f moves.
1245 For v8 we copy the default definition. */
1246 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
1248 ? (GET_MODE_BITSIZE (MODE) < 32 \
1249 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
1251 : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \
1252 ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0) \
1255 /* Return the maximum number of consecutive registers
1256 needed to represent mode MODE in a register of class CLASS. */
1257 /* On SPARC, this is the size of MODE in words. */
1258 #define CLASS_MAX_NREGS(CLASS, MODE) \
1259 (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \
1260 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1262 /* Stack layout; function entry, exit and calling. */
1264 /* Define this if pushing a word on the stack
1265 makes the stack pointer a smaller address. */
1266 #define STACK_GROWS_DOWNWARD
1268 /* Define this to nonzero if the nominal address of the stack frame
1269 is at the high-address end of the local variables;
1270 that is, each additional local variable allocated
1271 goes at a more negative offset in the frame. */
1272 #define FRAME_GROWS_DOWNWARD 1
1274 /* Offset within stack frame to start allocating local variables at.
1275 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1276 first local allocated. Otherwise, it is the offset to the BEGINNING
1277 of the first local allocated. */
1278 #define STARTING_FRAME_OFFSET 0
1280 /* Offset of first parameter from the argument pointer register value.
1281 !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg
1282 even if this function isn't going to use it.
1283 v9: This is 128 for the ins and locals. */
1284 #define FIRST_PARM_OFFSET(FNDECL) \
1285 (TARGET_ARCH64 ? 16 * UNITS_PER_WORD : STRUCT_VALUE_OFFSET + UNITS_PER_WORD)
1287 /* Offset from the argument pointer register value to the CFA.
1288 This is different from FIRST_PARM_OFFSET because the register window
1289 comes between the CFA and the arguments. */
1290 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1292 /* When a parameter is passed in a register, stack space is still
1294 !v9: All 6 possible integer registers have backing store allocated.
1295 v9: Only space for the arguments passed is allocated. */
1296 /* ??? Ideally, we'd use zero here (as the minimum), but zero has special
1297 meaning to the backend. Further, we need to be able to detect if a
1298 varargs/unprototyped function is called, as they may want to spill more
1299 registers than we've provided space. Ugly, ugly. So for now we retain
1300 all 6 slots even for v9. */
1301 #define REG_PARM_STACK_SPACE(DECL) (6 * UNITS_PER_WORD)
1303 /* Definitions for register elimination. */
1305 #define ELIMINABLE_REGS \
1306 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1307 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM} }
1309 /* We always pretend that this is a leaf function because if it's not,
1310 there's no point in trying to eliminate the frame pointer. If it
1311 is a leaf function, we guessed right! */
1312 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1314 if ((TO) == STACK_POINTER_REGNUM) \
1315 (OFFSET) = sparc_compute_frame_size (get_frame_size (), 1); \
1318 (OFFSET) += SPARC_STACK_BIAS; \
1321 /* Keep the stack pointer constant throughout the function.
1322 This is both an optimization and a necessity: longjmp
1323 doesn't behave itself when the stack pointer moves within
1325 #define ACCUMULATE_OUTGOING_ARGS 1
1327 /* Define this macro if the target machine has "register windows". This
1328 C expression returns the register number as seen by the called function
1329 corresponding to register number OUT as seen by the calling function.
1330 Return OUT if register number OUT is not an outbound register. */
1332 #define INCOMING_REGNO(OUT) \
1333 (((OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16)
1335 /* Define this macro if the target machine has "register windows". This
1336 C expression returns the register number as seen by the calling function
1337 corresponding to register number IN as seen by the called function.
1338 Return IN if register number IN is not an inbound register. */
1340 #define OUTGOING_REGNO(IN) \
1341 (((IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16)
1343 /* Define this macro if the target machine has register windows. This
1344 C expression returns true if the register is call-saved but is in the
1347 #define LOCAL_REGNO(REGNO) \
1348 ((REGNO) >= 16 && (REGNO) <= 31)
1350 /* Define the size of space to allocate for the return value of an
1353 #define APPLY_RESULT_SIZE (TARGET_ARCH64 ? 24 : 16)
1355 /* 1 if N is a possible register number for function argument passing.
1356 On SPARC, these are the "output" registers. v9 also uses %f0-%f31. */
1358 #define FUNCTION_ARG_REGNO_P(N) \
1360 ? (((N) >= 8 && (N) <= 13) || ((N) >= 32 && (N) <= 63)) \
1361 : ((N) >= 8 && (N) <= 13))
1363 /* Define a data type for recording info about an argument list
1364 during the scan of that argument list. This data type should
1365 hold all necessary information about the function itself
1366 and about the args processed so far, enough to enable macros
1367 such as FUNCTION_ARG to determine where the next arg should go.
1369 On SPARC (!v9), this is a single integer, which is a number of words
1370 of arguments scanned so far (including the invisible argument,
1371 if any, which holds the structure-value-address).
1372 Thus 7 or more means all following args should go on the stack.
1374 For v9, we also need to know whether a prototype is present. */
1377 int words; /* number of words passed so far */
1378 int prototype_p; /* nonzero if a prototype is present */
1379 int libcall_p; /* nonzero if a library call */
1381 #define CUMULATIVE_ARGS struct sparc_args
1383 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1384 for a call to a function whose data type is FNTYPE.
1385 For a library call, FNTYPE is 0. */
1387 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1388 init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL));
1390 /* If defined, a C expression which determines whether, and in which direction,
1391 to pad out an argument with extra space. The value should be of type
1392 `enum direction': either `upward' to pad above the argument,
1393 `downward' to pad below, or `none' to inhibit padding. */
1395 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1396 function_arg_padding ((MODE), (TYPE))
1399 /* Generate the special assembly code needed to tell the assembler whatever
1400 it might need to know about the return value of a function.
1402 For SPARC assemblers, we need to output a .proc pseudo-op which conveys
1403 information to the assembler relating to peephole optimization (done in
1406 #define ASM_DECLARE_RESULT(FILE, RESULT) \
1407 fprintf ((FILE), "\t.proc\t0%lo\n", sparc_type_code (TREE_TYPE (RESULT)))
1409 /* Output the special assembly code needed to tell the assembler some
1410 register is used as global register variable.
1412 SPARC 64bit psABI declares registers %g2 and %g3 as application
1413 registers and %g6 and %g7 as OS registers. Any object using them
1414 should declare (for %g2/%g3 has to, for %g6/%g7 can) that it uses them
1415 and how they are used (scratch or some global variable).
1416 Linker will then refuse to link together objects which use those
1417 registers incompatibly.
1419 Unless the registers are used for scratch, two different global
1420 registers cannot be declared to the same name, so in the unlikely
1421 case of a global register variable occupying more than one register
1422 we prefix the second and following registers with .gnu.part1. etc. */
1424 extern GTY(()) char sparc_hard_reg_printed[8];
1426 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
1427 #define ASM_DECLARE_REGISTER_GLOBAL(FILE, DECL, REGNO, NAME) \
1429 if (TARGET_ARCH64) \
1431 int end = HARD_REGNO_NREGS ((REGNO), DECL_MODE (decl)) + (REGNO); \
1433 for (reg = (REGNO); reg < 8 && reg < end; reg++) \
1434 if ((reg & ~1) == 2 || (reg & ~1) == 6) \
1436 if (reg == (REGNO)) \
1437 fprintf ((FILE), "\t.register\t%%g%d, %s\n", reg, (NAME)); \
1439 fprintf ((FILE), "\t.register\t%%g%d, .gnu.part%d.%s\n", \
1440 reg, reg - (REGNO), (NAME)); \
1441 sparc_hard_reg_printed[reg] = 1; \
1448 /* Emit rtl for profiling. */
1449 #define PROFILE_HOOK(LABEL) sparc_profile_hook (LABEL)
1451 /* All the work done in PROFILE_HOOK, but still required. */
1452 #define FUNCTION_PROFILER(FILE, LABELNO) do { } while (0)
1454 /* Set the name of the mcount function for the system. */
1455 #define MCOUNT_FUNCTION "*mcount"
1457 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1458 the stack pointer does not matter. The value is tested only in
1459 functions that have frame pointers.
1460 No definition is equivalent to always zero. */
1462 #define EXIT_IGNORE_STACK \
1463 (get_frame_size () != 0 \
1464 || cfun->calls_alloca || crtl->outgoing_args_size)
1466 /* Define registers used by the epilogue and return instruction. */
1467 #define EPILOGUE_USES(REGNO) ((REGNO) == 31 \
1468 || (crtl->calls_eh_return && (REGNO) == 1))
1470 /* Length in units of the trampoline for entering a nested function. */
1472 #define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 32 : 16)
1474 #define TRAMPOLINE_ALIGNMENT 128 /* 16 bytes */
1476 /* Generate RTL to flush the register windows so as to make arbitrary frames
1478 #define SETUP_FRAME_ADDRESSES() \
1479 emit_insn (gen_flush_register_windows ())
1481 /* Given an rtx for the address of a frame,
1482 return an rtx for the address of the word in the frame
1483 that holds the dynamic chain--the previous frame's address. */
1484 #define DYNAMIC_CHAIN_ADDRESS(frame) \
1485 plus_constant (frame, 14 * UNITS_PER_WORD + SPARC_STACK_BIAS)
1487 /* Given an rtx for the frame pointer,
1488 return an rtx for the address of the frame. */
1489 #define FRAME_ADDR_RTX(frame) plus_constant (frame, SPARC_STACK_BIAS)
1491 /* The return address isn't on the stack, it is in a register, so we can't
1492 access it from the current frame pointer. We can access it from the
1493 previous frame pointer though by reading a value from the register window
1495 #define RETURN_ADDR_IN_PREVIOUS_FRAME
1497 /* This is the offset of the return address to the true next instruction to be
1498 executed for the current function. */
1499 #define RETURN_ADDR_OFFSET \
1500 (8 + 4 * (! TARGET_ARCH64 && cfun->returns_struct))
1502 /* The current return address is in %i7. The return address of anything
1503 farther back is in the register window save area at [%fp+60]. */
1504 /* ??? This ignores the fact that the actual return address is +8 for normal
1505 returns, and +12 for structure returns. */
1506 #define RETURN_ADDR_RTX(count, frame) \
1508 ? gen_rtx_REG (Pmode, 31) \
1509 : gen_rtx_MEM (Pmode, \
1510 memory_address (Pmode, plus_constant (frame, \
1511 15 * UNITS_PER_WORD \
1512 + SPARC_STACK_BIAS))))
1514 /* Before the prologue, the return address is %o7 + 8. OK, sometimes it's
1515 +12, but always using +8 is close enough for frame unwind purposes.
1516 Actually, just using %o7 is close enough for unwinding, but %o7+8
1517 is something you can return to. */
1518 #define INCOMING_RETURN_ADDR_RTX \
1519 plus_constant (gen_rtx_REG (word_mode, 15), 8)
1520 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (15)
1522 /* The offset from the incoming value of %sp to the top of the stack frame
1523 for the current function. On sparc64, we have to account for the stack
1525 #define INCOMING_FRAME_SP_OFFSET SPARC_STACK_BIAS
1527 /* Describe how we implement __builtin_eh_return. */
1528 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 24 : INVALID_REGNUM)
1529 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 1) /* %g1 */
1530 #define EH_RETURN_HANDLER_RTX gen_rtx_REG (Pmode, 31) /* %i7 */
1532 /* Select a format to encode pointers in exception handling data. CODE
1533 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
1534 true if the symbol may be affected by dynamic relocations.
1536 If assembler and linker properly support .uaword %r_disp32(foo),
1537 then use PC relative 32-bit relocations instead of absolute relocs
1538 for shared libraries. On sparc64, use pc relative 32-bit relocs even
1539 for binaries, to save memory.
1541 binutils 2.12 would emit a R_SPARC_DISP32 dynamic relocation if the
1542 symbol %r_disp32() is against was not local, but .hidden. In that
1543 case, we have to use DW_EH_PE_absptr for pic personality. */
1544 #ifdef HAVE_AS_SPARC_UA_PCREL
1545 #ifdef HAVE_AS_SPARC_UA_PCREL_HIDDEN
1546 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
1548 ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\
1549 : ((TARGET_ARCH64 && ! GLOBAL) \
1550 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \
1553 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
1555 ? (GLOBAL ? DW_EH_PE_absptr : (DW_EH_PE_pcrel | DW_EH_PE_sdata4)) \
1556 : ((TARGET_ARCH64 && ! GLOBAL) \
1557 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \
1561 /* Emit a PC-relative relocation. */
1562 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \
1564 fputs (integer_asm_op (SIZE, FALSE), FILE); \
1565 fprintf (FILE, "%%r_disp%d(", SIZE * 8); \
1566 assemble_name (FILE, LABEL); \
1567 fputc (')', FILE); \
1571 /* Addressing modes, and classification of registers for them. */
1573 /* Macros to check register numbers against specific register classes. */
1575 /* These assume that REGNO is a hard or pseudo reg number.
1576 They give nonzero only if REGNO is a hard reg of the suitable class
1577 or a pseudo reg currently allocated to a suitable hard reg.
1578 Since they use reg_renumber, they are safe only once reg_renumber
1579 has been allocated, which happens in local-alloc.c. */
1581 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1582 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < (unsigned)32 \
1583 || (REGNO) == FRAME_POINTER_REGNUM \
1584 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)
1586 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO)
1588 #define REGNO_OK_FOR_FP_P(REGNO) \
1589 (((unsigned) (REGNO) - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)) \
1590 || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)))
1591 #define REGNO_OK_FOR_CCFP_P(REGNO) \
1593 && (((unsigned) (REGNO) - 96 < (unsigned)4) \
1594 || ((unsigned) reg_renumber[REGNO] - 96 < (unsigned)4)))
1596 /* Now macros that check whether X is a register and also,
1597 strictly, whether it is in a specified class.
1599 These macros are specific to the SPARC, and may be used only
1600 in code for printing assembler insns and in conditions for
1601 define_optimization. */
1603 /* 1 if X is an fp register. */
1605 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1607 /* Is X, a REG, an in or global register? i.e. is regno 0..7 or 24..31 */
1608 #define IN_OR_GLOBAL_P(X) (REGNO (X) < 8 || (REGNO (X) >= 24 && REGNO (X) <= 31))
1610 /* Maximum number of registers that can appear in a valid memory address. */
1612 #define MAX_REGS_PER_ADDRESS 2
1614 /* Recognize any constant value that is a valid address.
1615 When PIC, we do not accept an address that would require a scratch reg
1616 to load into a register. */
1618 #define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1620 /* Define this, so that when PIC, reload won't try to reload invalid
1621 addresses which require two reload registers. */
1623 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
1625 /* Nonzero if the constant value X is a legitimate general operand.
1626 Anything can be made to work except floating point constants.
1627 If TARGET_VIS, 0.0 can be made to work as well. */
1629 #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X)
1631 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1632 and check its validity for a certain class.
1633 We have two alternate definitions for each of them.
1634 The usual definition accepts all pseudo regs; the other rejects
1635 them unless they have been allocated suitable hard regs.
1636 The symbol REG_OK_STRICT causes the latter definition to be used.
1638 Most source files want to accept pseudo regs in the hope that
1639 they will get allocated to the class that the insn wants them to be in.
1640 Source files for reload pass need to be strict.
1641 After reload, it makes no difference, since pseudo regs have
1642 been eliminated by then. */
1644 #ifndef REG_OK_STRICT
1646 /* Nonzero if X is a hard reg that can be used as an index
1647 or if it is a pseudo reg. */
1648 #define REG_OK_FOR_INDEX_P(X) \
1650 || REGNO (X) == FRAME_POINTER_REGNUM \
1651 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1653 /* Nonzero if X is a hard reg that can be used as a base reg
1654 or if it is a pseudo reg. */
1655 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_INDEX_P (X)
1659 /* Nonzero if X is a hard reg that can be used as an index. */
1660 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1661 /* Nonzero if X is a hard reg that can be used as a base reg. */
1662 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1666 /* Should gcc use [%reg+%lo(xx)+offset] addresses? */
1668 #ifdef HAVE_AS_OFFSETABLE_LO10
1669 #define USE_AS_OFFSETABLE_LO10 1
1671 #define USE_AS_OFFSETABLE_LO10 0
1674 /* On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
1675 ordinarily. This changes a bit when generating PIC. The details are
1676 in sparc.c's implementation of TARGET_LEGITIMATE_ADDRESS_P. */
1678 #define SYMBOLIC_CONST(X) symbolic_operand (X, VOIDmode)
1680 #define RTX_OK_FOR_BASE_P(X) \
1681 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1682 || (GET_CODE (X) == SUBREG \
1683 && GET_CODE (SUBREG_REG (X)) == REG \
1684 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
1686 #define RTX_OK_FOR_INDEX_P(X) \
1687 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
1688 || (GET_CODE (X) == SUBREG \
1689 && GET_CODE (SUBREG_REG (X)) == REG \
1690 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
1692 #define RTX_OK_FOR_OFFSET_P(X) \
1693 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000 - 8)
1695 #define RTX_OK_FOR_OLO10_P(X) \
1696 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0xc00 - 8)
1699 /* Try a machine-dependent way of reloading an illegitimate address
1700 operand. If we find one, push the reload and jump to WIN. This
1701 macro is used in only one place: `find_reloads_address' in reload.c. */
1702 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1705 (X) = sparc_legitimize_reload_address ((X), (MODE), (OPNUM), \
1706 (int)(TYPE), (IND_LEVELS), &win); \
1711 /* Specify the machine mode that this machine uses
1712 for the index in the tablejump instruction. */
1713 /* If we ever implement any of the full models (such as CM_FULLANY),
1714 this has to be DImode in that case */
1715 #ifdef HAVE_GAS_SUBSECTION_ORDERING
1716 #define CASE_VECTOR_MODE \
1717 (! TARGET_PTR64 ? SImode : flag_pic ? SImode : TARGET_CM_MEDLOW ? SImode : DImode)
1719 /* If assembler does not have working .subsection -1, we use DImode for pic, as otherwise
1720 we have to sign extend which slows things down. */
1721 #define CASE_VECTOR_MODE \
1722 (! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode)
1725 /* Define this as 1 if `char' should by default be signed; else as 0. */
1726 #define DEFAULT_SIGNED_CHAR 1
1728 /* Max number of bytes we can move from memory to memory
1729 in one reasonably fast instruction. */
1732 /* If a memory-to-memory move would take MOVE_RATIO or more simple
1733 move-instruction pairs, we will do a movmem or libcall instead. */
1735 #define MOVE_RATIO(speed) ((speed) ? 8 : 3)
1737 /* Define if operations between registers always perform the operation
1738 on the full register even if a narrower mode is specified. */
1739 #define WORD_REGISTER_OPERATIONS
1741 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1742 will either zero-extend or sign-extend. The value of this macro should
1743 be the code that says which one of the two operations is implicitly
1744 done, UNKNOWN if none. */
1745 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1747 /* Nonzero if access to memory by bytes is slow and undesirable.
1748 For RISC chips, it means that access to memory by bytes is no
1749 better than access by words when possible, so grab a whole word
1750 and maybe make use of that. */
1751 #define SLOW_BYTE_ACCESS 1
1753 /* Define this to be nonzero if shift instructions ignore all but the low-order
1755 #define SHIFT_COUNT_TRUNCATED 1
1757 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1758 is done just by pretending it is already truncated. */
1759 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1761 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1762 return the mode to be used for the comparison. For floating-point,
1763 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
1764 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
1765 processing is needed. */
1766 #define SELECT_CC_MODE(OP,X,Y) select_cc_mode ((OP), (X), (Y))
1768 /* Return nonzero if MODE implies a floating point inequality can be
1769 reversed. For SPARC this is always true because we have a full
1770 compliment of ordered and unordered comparisons, but until generic
1771 code knows how to reverse it correctly we keep the old definition. */
1772 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode && (MODE) != CCFPmode)
1774 /* A function address in a call instruction for indexing purposes. */
1775 #define FUNCTION_MODE Pmode
1777 /* Define this if addresses of constant functions
1778 shouldn't be put through pseudo regs where they can be cse'd.
1779 Desirable on machines where ordinary constants are expensive
1780 but a CALL with constant address is cheap. */
1781 #define NO_FUNCTION_CSE
1783 /* alloca should avoid clobbering the old register save area. */
1784 #define SETJMP_VIA_SAVE_AREA
1786 /* The _Q_* comparison libcalls return booleans. */
1787 #define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) ((MODE) == TFmode)
1789 /* Assume by default that the _Qp_* 64-bit libcalls are implemented such
1790 that the inputs are fully consumed before the output memory is clobbered. */
1792 #define TARGET_BUGGY_QP_LIB 0
1794 /* Assume by default that we do not have the Solaris-specific conversion
1795 routines nor 64-bit integer multiply and divide routines. */
1797 #define SUN_CONVERSION_LIBFUNCS 0
1798 #define DITF_CONVERSION_LIBFUNCS 0
1799 #define SUN_INTEGER_MULTIPLY_64 0
1801 /* Compute extra cost of moving data between one register class
1803 #define GENERAL_OR_I64(C) ((C) == GENERAL_REGS || (C) == I64_REGS)
1804 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
1805 (((FP_REG_CLASS_P (CLASS1) && GENERAL_OR_I64 (CLASS2)) \
1806 || (GENERAL_OR_I64 (CLASS1) && FP_REG_CLASS_P (CLASS2)) \
1807 || (CLASS1) == FPCC_REGS || (CLASS2) == FPCC_REGS) \
1808 ? ((sparc_cpu == PROCESSOR_ULTRASPARC \
1809 || sparc_cpu == PROCESSOR_ULTRASPARC3 \
1810 || sparc_cpu == PROCESSOR_NIAGARA \
1811 || sparc_cpu == PROCESSOR_NIAGARA2) ? 12 : 6) : 2)
1813 /* Provide the cost of a branch. For pre-v9 processors we use
1814 a value of 3 to take into account the potential annulling of
1815 the delay slot (which ends up being a bubble in the pipeline slot)
1816 plus a cycle to take into consideration the instruction cache
1819 On v9 and later, which have branch prediction facilities, we set
1820 it to the depth of the pipeline as that is the cost of a
1821 mispredicted branch.
1823 On Niagara, normal branches insert 3 bubbles into the pipe
1824 and annulled branches insert 4 bubbles.
1826 On Niagara-2, a not-taken branch costs 1 cycle whereas a taken
1827 branch costs 6 cycles. */
1829 #define BRANCH_COST(speed_p, predictable_p) \
1830 ((sparc_cpu == PROCESSOR_V9 \
1831 || sparc_cpu == PROCESSOR_ULTRASPARC) \
1833 : (sparc_cpu == PROCESSOR_ULTRASPARC3 \
1835 : (sparc_cpu == PROCESSOR_NIAGARA \
1837 : (sparc_cpu == PROCESSOR_NIAGARA2 \
1841 /* Control the assembler format that we output. */
1843 /* A C string constant describing how to begin a comment in the target
1844 assembler language. The compiler assumes that the comment will end at
1845 the end of the line. */
1847 #define ASM_COMMENT_START "!"
1849 /* Output to assembler file text saying following lines
1850 may contain character constants, extra white space, comments, etc. */
1852 #define ASM_APP_ON ""
1854 /* Output to assembler file text saying following lines
1855 no longer contain unusual constructs. */
1857 #define ASM_APP_OFF ""
1859 /* How to refer to registers in assembler output.
1860 This sequence is indexed by compiler's hard-register-number (see above). */
1862 #define REGISTER_NAMES \
1863 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \
1864 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \
1865 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \
1866 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \
1867 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \
1868 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \
1869 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \
1870 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \
1871 "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \
1872 "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \
1873 "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \
1874 "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \
1875 "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc", "%sfp" }
1877 /* Define additional names for use in asm clobbers and asm declarations. */
1879 #define ADDITIONAL_REGISTER_NAMES \
1880 {{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}}
1882 /* On Sun 4, this limit is 2048. We use 1000 to be safe, since the length
1883 can run past this up to a continuation point. Once we used 1500, but
1884 a single entry in C++ can run more than 500 bytes, due to the length of
1885 mangled symbol names. dbxout.c should really be fixed to do
1886 continuations when they are actually needed instead of trying to
1888 #define DBX_CONTIN_LENGTH 1000
1890 /* This is how to output a command to make the user-level label named NAME
1891 defined for reference from other files. */
1893 /* Globalizing directive for a label. */
1894 #define GLOBAL_ASM_OP "\t.global "
1896 /* The prefix to add to user-visible assembler symbols. */
1898 #define USER_LABEL_PREFIX "_"
1900 /* This is how to store into the string LABEL
1901 the symbol_ref name of an internal numbered label where
1902 PREFIX is the class of label and NUM is the number within the class.
1903 This is suitable for output with `assemble_name'. */
1905 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1906 sprintf ((LABEL), "*%s%ld", (PREFIX), (long)(NUM))
1908 /* This is how we hook in and defer the case-vector until the end of
1910 #define ASM_OUTPUT_ADDR_VEC(LAB,VEC) \
1911 sparc_defer_case_vector ((LAB),(VEC), 0)
1913 #define ASM_OUTPUT_ADDR_DIFF_VEC(LAB,VEC) \
1914 sparc_defer_case_vector ((LAB),(VEC), 1)
1916 /* This is how to output an element of a case-vector that is absolute. */
1918 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1921 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1922 if (CASE_VECTOR_MODE == SImode) \
1923 fprintf (FILE, "\t.word\t"); \
1925 fprintf (FILE, "\t.xword\t"); \
1926 assemble_name (FILE, label); \
1927 fputc ('\n', FILE); \
1930 /* This is how to output an element of a case-vector that is relative.
1931 (SPARC uses such vectors only when generating PIC.) */
1933 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1936 ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE)); \
1937 if (CASE_VECTOR_MODE == SImode) \
1938 fprintf (FILE, "\t.word\t"); \
1940 fprintf (FILE, "\t.xword\t"); \
1941 assemble_name (FILE, label); \
1942 ASM_GENERATE_INTERNAL_LABEL (label, "L", (REL)); \
1943 fputc ('-', FILE); \
1944 assemble_name (FILE, label); \
1945 fputc ('\n', FILE); \
1948 /* This is what to output before and after case-vector (both
1949 relative and absolute). If .subsection -1 works, we put case-vectors
1950 at the beginning of the current section. */
1952 #ifdef HAVE_GAS_SUBSECTION_ORDERING
1954 #define ASM_OUTPUT_ADDR_VEC_START(FILE) \
1955 fprintf(FILE, "\t.subsection\t-1\n")
1957 #define ASM_OUTPUT_ADDR_VEC_END(FILE) \
1958 fprintf(FILE, "\t.previous\n")
1962 /* This is how to output an assembler line
1963 that says to advance the location counter
1964 to a multiple of 2**LOG bytes. */
1966 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1968 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
1970 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1971 fprintf (FILE, "\t.skip "HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
1973 /* This says how to output an assembler line
1974 to define a global common symbol. */
1976 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1977 ( fputs ("\t.common ", (FILE)), \
1978 assemble_name ((FILE), (NAME)), \
1979 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\"\n", (SIZE)))
1981 /* This says how to output an assembler line to define a local common
1984 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \
1985 ( fputs ("\t.reserve ", (FILE)), \
1986 assemble_name ((FILE), (NAME)), \
1987 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\",%u\n", \
1988 (SIZE), ((ALIGNED) / BITS_PER_UNIT)))
1990 /* A C statement (sans semicolon) to output to the stdio stream
1991 FILE the assembler definition of uninitialized global DECL named
1992 NAME whose size is SIZE bytes and alignment is ALIGN bytes.
1993 Try to use asm_output_aligned_bss to implement this macro. */
1995 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1997 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \
2000 #define IDENT_ASM_OP "\t.ident\t"
2002 /* Output #ident as a .ident. */
2004 #define ASM_OUTPUT_IDENT(FILE, NAME) \
2005 fprintf (FILE, "%s\"%s\"\n", IDENT_ASM_OP, NAME);
2007 /* Prettify the assembly. */
2009 extern int sparc_indent_opcode;
2011 #define ASM_OUTPUT_OPCODE(FILE, PTR) \
2013 if (sparc_indent_opcode) \
2016 sparc_indent_opcode = 0; \
2020 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
2021 ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '(' \
2022 || (CHAR) == ')' || (CHAR) == '_' || (CHAR) == '&')
2024 /* Print operand X (an rtx) in assembler syntax to file FILE.
2025 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2026 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2028 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2030 /* Print a memory address as an operand to reference that memory location. */
2032 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2033 { register rtx base, index = 0; \
2035 register rtx addr = ADDR; \
2036 if (GET_CODE (addr) == REG) \
2037 fputs (reg_names[REGNO (addr)], FILE); \
2038 else if (GET_CODE (addr) == PLUS) \
2040 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
2041 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\
2042 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
2043 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\
2045 base = XEXP (addr, 0), index = XEXP (addr, 1); \
2046 if (GET_CODE (base) == LO_SUM) \
2048 gcc_assert (USE_AS_OFFSETABLE_LO10 \
2050 && ! TARGET_CM_MEDMID); \
2051 output_operand (XEXP (base, 0), 0); \
2052 fputs ("+%lo(", FILE); \
2053 output_address (XEXP (base, 1)); \
2054 fprintf (FILE, ")+%d", offset); \
2058 fputs (reg_names[REGNO (base)], FILE); \
2060 fprintf (FILE, "%+d", offset); \
2061 else if (GET_CODE (index) == REG) \
2062 fprintf (FILE, "+%s", reg_names[REGNO (index)]); \
2063 else if (GET_CODE (index) == SYMBOL_REF \
2064 || GET_CODE (index) == LABEL_REF \
2065 || GET_CODE (index) == CONST) \
2066 fputc ('+', FILE), output_addr_const (FILE, index); \
2067 else gcc_unreachable (); \
2070 else if (GET_CODE (addr) == MINUS \
2071 && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \
2073 output_addr_const (FILE, XEXP (addr, 0)); \
2074 fputs ("-(", FILE); \
2075 output_addr_const (FILE, XEXP (addr, 1)); \
2076 fputs ("-.)", FILE); \
2078 else if (GET_CODE (addr) == LO_SUM) \
2080 output_operand (XEXP (addr, 0), 0); \
2081 if (TARGET_CM_MEDMID) \
2082 fputs ("+%l44(", FILE); \
2084 fputs ("+%lo(", FILE); \
2085 output_address (XEXP (addr, 1)); \
2086 fputc (')', FILE); \
2088 else if (flag_pic && GET_CODE (addr) == CONST \
2089 && GET_CODE (XEXP (addr, 0)) == MINUS \
2090 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \
2091 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \
2092 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \
2094 addr = XEXP (addr, 0); \
2095 output_addr_const (FILE, XEXP (addr, 0)); \
2096 /* Group the args of the second CONST in parenthesis. */ \
2097 fputs ("-(", FILE); \
2098 /* Skip past the second CONST--it does nothing for us. */\
2099 output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \
2100 /* Close the parenthesis. */ \
2101 fputc (')', FILE); \
2105 output_addr_const (FILE, addr); \
2109 /* TLS support defaulting to original Sun flavor. GNU extensions
2110 must be activated in separate configuration files. */
2112 #define TARGET_TLS 1
2114 #define TARGET_TLS 0
2117 #define TARGET_SUN_TLS TARGET_TLS
2118 #define TARGET_GNU_TLS 0
2120 /* The number of Pmode words for the setjmp buffer. */
2121 #define JMP_BUF_SIZE 12
2123 /* We use gcc _mcount for profiling. */
2124 #define NO_PROFILE_COUNTERS 0