1 /* Definitions of target machine for GNU compiler, for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1994, 1995, 1996, 1997, 1998, 1999
3 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com).
5 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 /* Note that some other tm.h files include this one and then override
26 whatever definitions are necessary. */
28 /* Target CPU builtins. FIXME: Defining sparc is for the benefit of
29 Solaris only; otherwise just define __sparc__. Sadly the headers
30 are such a mess there is no Solaris-specific header. */
31 #define TARGET_CPU_CPP_BUILTINS() \
34 builtin_define_std ("sparc"); \
37 builtin_assert ("cpu=sparc64"); \
38 builtin_assert ("machine=sparc64"); \
42 builtin_assert ("cpu=sparc"); \
43 builtin_assert ("machine=sparc"); \
48 /* Specify this in a cover file to provide bi-architecture (32/64) support. */
49 /* #define SPARC_BI_ARCH */
51 /* Macro used later in this file to determine default architecture. */
52 #define DEFAULT_ARCH32_P ((TARGET_DEFAULT & MASK_64BIT) == 0)
54 /* TARGET_ARCH{32,64} are the main macros to decide which of the two
55 architectures to compile for. We allow targets to choose compile time or
58 #if defined(__sparcv9) || defined(__arch64__)
59 #define TARGET_ARCH32 0
61 #define TARGET_ARCH32 1
65 #define TARGET_ARCH32 (! TARGET_64BIT)
67 #define TARGET_ARCH32 (DEFAULT_ARCH32_P)
68 #endif /* SPARC_BI_ARCH */
69 #endif /* IN_LIBGCC2 */
70 #define TARGET_ARCH64 (! TARGET_ARCH32)
72 /* Code model selection.
73 -mcmodel is used to select the v9 code model.
74 Different code models aren't supported for v7/8 code.
76 TARGET_CM_32: 32 bit address space, top 32 bits = 0,
77 pointers are 32 bits. Note that this isn't intended
80 TARGET_CM_MEDLOW: 32 bit address space, top 32 bits = 0,
81 avoid generating %uhi and %ulo terms,
84 TARGET_CM_MEDMID: 64 bit address space.
85 The executable must be in the low 16 TB of memory.
86 This corresponds to the low 44 bits, and the %[hml]44
87 relocs are used. The text segment has a maximum size
90 TARGET_CM_MEDANY: 64 bit address space.
91 The text and data segments have a maximum size of 31
92 bits and may be located anywhere. The maximum offset
93 from any instruction to the label _GLOBAL_OFFSET_TABLE_
96 TARGET_CM_EMBMEDANY: 64 bit address space.
97 The text and data segments have a maximum size of 31 bits
98 and may be located anywhere. Register %g4 contains
99 the start address of the data segment.
110 /* Value of -mcmodel specified by user. */
111 extern const char *sparc_cmodel_string;
113 extern enum cmodel sparc_cmodel;
115 /* V9 code model selection. */
116 #define TARGET_CM_MEDLOW (sparc_cmodel == CM_MEDLOW)
117 #define TARGET_CM_MEDMID (sparc_cmodel == CM_MEDMID)
118 #define TARGET_CM_MEDANY (sparc_cmodel == CM_MEDANY)
119 #define TARGET_CM_EMBMEDANY (sparc_cmodel == CM_EMBMEDANY)
121 #define SPARC_DEFAULT_CMODEL CM_32
123 /* This is call-clobbered in the normal ABI, but is reserved in the
124 home grown (aka upward compatible) embedded ABI. */
125 #define EMBMEDANY_BASE_REG "%g4"
127 /* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile,
128 and specified by the user via --with-cpu=foo.
129 This specifies the cpu implementation, not the architecture size. */
130 /* Note that TARGET_CPU_v9 is assumed to start the list of 64-bit
132 #define TARGET_CPU_sparc 0
133 #define TARGET_CPU_v7 0 /* alias for previous */
134 #define TARGET_CPU_sparclet 1
135 #define TARGET_CPU_sparclite 2
136 #define TARGET_CPU_v8 3 /* generic v8 implementation */
137 #define TARGET_CPU_supersparc 4
138 #define TARGET_CPU_hypersparc 5
139 #define TARGET_CPU_sparc86x 6
140 #define TARGET_CPU_sparclite86x 6
141 #define TARGET_CPU_v9 7 /* generic v9 implementation */
142 #define TARGET_CPU_sparcv9 7 /* alias */
143 #define TARGET_CPU_sparc64 7 /* alias */
144 #define TARGET_CPU_ultrasparc 8
145 #define TARGET_CPU_ultrasparc3 9
147 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
148 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \
149 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3
151 #define CPP_CPU32_DEFAULT_SPEC ""
152 #define ASM_CPU32_DEFAULT_SPEC ""
154 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9
155 /* ??? What does Sun's CC pass? */
156 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
157 /* ??? It's not clear how other assemblers will handle this, so by default
158 use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case
159 is handled in sol2.h. */
160 #define ASM_CPU64_DEFAULT_SPEC "-Av9"
162 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc
163 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
164 #define ASM_CPU64_DEFAULT_SPEC "-Av9a"
166 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3
167 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
168 #define ASM_CPU64_DEFAULT_SPEC "-Av9b"
173 #define CPP_CPU64_DEFAULT_SPEC ""
174 #define ASM_CPU64_DEFAULT_SPEC ""
176 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc \
177 || TARGET_CPU_DEFAULT == TARGET_CPU_v8
178 #define CPP_CPU32_DEFAULT_SPEC ""
179 #define ASM_CPU32_DEFAULT_SPEC ""
182 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet
183 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclet__"
184 #define ASM_CPU32_DEFAULT_SPEC "-Asparclet"
187 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite
188 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite__"
189 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
192 #if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc
193 #define CPP_CPU32_DEFAULT_SPEC "-D__supersparc__ -D__sparc_v8__"
194 #define ASM_CPU32_DEFAULT_SPEC ""
197 #if TARGET_CPU_DEFAULT == TARGET_CPU_hypersparc
198 #define CPP_CPU32_DEFAULT_SPEC "-D__hypersparc__ -D__sparc_v8__"
199 #define ASM_CPU32_DEFAULT_SPEC ""
202 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite86x
203 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite86x__"
204 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
209 #if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC)
210 #error Unrecognized value in TARGET_CPU_DEFAULT.
215 #define CPP_CPU_DEFAULT_SPEC \
216 (DEFAULT_ARCH32_P ? "\
217 %{m64:" CPP_CPU64_DEFAULT_SPEC "} \
218 %{!m64:" CPP_CPU32_DEFAULT_SPEC "} \
220 %{m32:" CPP_CPU32_DEFAULT_SPEC "} \
221 %{!m32:" CPP_CPU64_DEFAULT_SPEC "} \
223 #define ASM_CPU_DEFAULT_SPEC \
224 (DEFAULT_ARCH32_P ? "\
225 %{m64:" ASM_CPU64_DEFAULT_SPEC "} \
226 %{!m64:" ASM_CPU32_DEFAULT_SPEC "} \
228 %{m32:" ASM_CPU32_DEFAULT_SPEC "} \
229 %{!m32:" ASM_CPU64_DEFAULT_SPEC "} \
232 #else /* !SPARC_BI_ARCH */
234 #define CPP_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? CPP_CPU32_DEFAULT_SPEC : CPP_CPU64_DEFAULT_SPEC)
235 #define ASM_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? ASM_CPU32_DEFAULT_SPEC : ASM_CPU64_DEFAULT_SPEC)
237 #endif /* !SPARC_BI_ARCH */
239 /* Define macros to distinguish architectures. */
241 /* Common CPP definitions used by CPP_SPEC amongst the various targets
242 for handling -mcpu=xxx switches. */
243 #define CPP_CPU_SPEC "\
244 %{msoft-float:-D_SOFT_FLOAT} \
246 %{msparclite:-D__sparclite__} \
247 %{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \
248 %{mv8:-D__sparc_v8__} \
249 %{msupersparc:-D__supersparc__ -D__sparc_v8__} \
250 %{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \
251 %{mcpu=sparclite:-D__sparclite__} \
252 %{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \
253 %{mcpu=v8:-D__sparc_v8__} \
254 %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \
255 %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \
256 %{mcpu=sparclite86x:-D__sparclite86x__} \
257 %{mcpu=v9:-D__sparc_v9__} \
258 %{mcpu=ultrasparc:-D__sparc_v9__} \
259 %{mcpu=ultrasparc3:-D__sparc_v9__} \
260 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \
262 #define CPP_ARCH32_SPEC ""
263 #define CPP_ARCH64_SPEC "-D__arch64__"
265 #define CPP_ARCH_DEFAULT_SPEC \
266 (DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC)
268 #define CPP_ARCH_SPEC "\
269 %{m32:%(cpp_arch32)} \
270 %{m64:%(cpp_arch64)} \
271 %{!m32:%{!m64:%(cpp_arch_default)}} \
274 /* Macros to distinguish endianness. */
275 #define CPP_ENDIAN_SPEC "\
276 %{mlittle-endian:-D__LITTLE_ENDIAN__} \
277 %{mlittle-endian-data:-D__LITTLE_ENDIAN_DATA__}"
279 /* Macros to distinguish the particular subtarget. */
280 #define CPP_SUBTARGET_SPEC ""
282 #define CPP_SPEC "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_subtarget)"
284 /* Prevent error on `-sun4' and `-target sun4' options. */
285 /* This used to translate -dalign to -malign, but that is no good
286 because it can't turn off the usual meaning of making debugging dumps. */
287 /* Translate old style -m<cpu> into new style -mcpu=<cpu>.
288 ??? Delete support for -m<cpu> for 2.9. */
291 %{sun4:} %{target:} \
292 %{mcypress:-mcpu=cypress} \
293 %{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \
294 %{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \
297 /* Override in target specific files. */
298 #define ASM_CPU_SPEC "\
299 %{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \
300 %{msparclite:-Asparclite} \
301 %{mf930:-Asparclite} %{mf934:-Asparclite} \
302 %{mcpu=sparclite:-Asparclite} \
303 %{mcpu=sparclite86x:-Asparclite} \
304 %{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \
305 %{mv8plus:-Av8plus} \
307 %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \
308 %{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \
309 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_cpu_default)}}}}}}} \
312 /* Word size selection, among other things.
313 This is what GAS uses. Add %(asm_arch) to ASM_SPEC to enable. */
315 #define ASM_ARCH32_SPEC "-32"
316 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
317 #define ASM_ARCH64_SPEC "-64 -no-undeclared-regs"
319 #define ASM_ARCH64_SPEC "-64"
321 #define ASM_ARCH_DEFAULT_SPEC \
322 (DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC)
324 #define ASM_ARCH_SPEC "\
325 %{m32:%(asm_arch32)} \
326 %{m64:%(asm_arch64)} \
327 %{!m32:%{!m64:%(asm_arch_default)}} \
330 #ifdef HAVE_AS_RELAX_OPTION
331 #define ASM_RELAX_SPEC "%{!mno-relax:-relax}"
333 #define ASM_RELAX_SPEC ""
336 /* Special flags to the Sun-4 assembler when using pipe for input. */
339 %{R} %{!pg:%{!p:%{fpic|fPIC|fpie|fPIE:-k}}} %{keep-local-as-symbols:-L} \
340 %(asm_cpu) %(asm_relax)"
342 #define AS_NEEDS_DASH_FOR_PIPED_INPUT
344 /* This macro defines names of additional specifications to put in the specs
345 that can be used in various specifications like CC1_SPEC. Its definition
346 is an initializer with a subgrouping for each command option.
348 Each subgrouping contains a string constant, that defines the
349 specification name, and a string constant that used by the GCC driver
352 Do not define this macro if it does not need to do anything. */
354 #define EXTRA_SPECS \
355 { "cpp_cpu", CPP_CPU_SPEC }, \
356 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
357 { "cpp_arch32", CPP_ARCH32_SPEC }, \
358 { "cpp_arch64", CPP_ARCH64_SPEC }, \
359 { "cpp_arch_default", CPP_ARCH_DEFAULT_SPEC },\
360 { "cpp_arch", CPP_ARCH_SPEC }, \
361 { "cpp_endian", CPP_ENDIAN_SPEC }, \
362 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \
363 { "asm_cpu", ASM_CPU_SPEC }, \
364 { "asm_cpu_default", ASM_CPU_DEFAULT_SPEC }, \
365 { "asm_arch32", ASM_ARCH32_SPEC }, \
366 { "asm_arch64", ASM_ARCH64_SPEC }, \
367 { "asm_relax", ASM_RELAX_SPEC }, \
368 { "asm_arch_default", ASM_ARCH_DEFAULT_SPEC },\
369 { "asm_arch", ASM_ARCH_SPEC }, \
370 SUBTARGET_EXTRA_SPECS
372 #define SUBTARGET_EXTRA_SPECS
374 /* Because libgcc can generate references back to libc (via .umul etc.) we have
375 to list libc again after the second libgcc. */
376 #define LINK_GCC_C_SEQUENCE_SPEC "%G %L %G %L"
379 #define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int")
380 #define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int")
382 /* ??? This should be 32 bits for v9 but what can we do? */
383 #define WCHAR_TYPE "short unsigned int"
384 #define WCHAR_TYPE_SIZE 16
386 /* Show we can debug even without a frame pointer. */
387 #define CAN_DEBUG_WITHOUT_FP
389 #define OVERRIDE_OPTIONS sparc_override_options ()
391 /* Generate DBX debugging information. */
393 #define DBX_DEBUGGING_INFO 1
395 /* Run-time compilation parameters selecting different hardware subsets. */
397 extern int target_flags;
399 /* Nonzero if we should generate code to use the fpu. */
401 #define TARGET_FPU (target_flags & MASK_FPU)
403 /* Nonzero if we should assume that double pointers might be unaligned.
404 This can happen when linking gcc compiled code with other compilers,
405 because the ABI only guarantees 4 byte alignment. */
406 #define MASK_UNALIGNED_DOUBLES 4
407 #define TARGET_UNALIGNED_DOUBLES (target_flags & MASK_UNALIGNED_DOUBLES)
409 /* Nonzero means that we should generate code for a v8 sparc. */
411 #define TARGET_V8 (target_flags & MASK_V8)
413 /* Nonzero means that we should generate code for a sparclite.
414 This enables the sparclite specific instructions, but does not affect
415 whether FPU instructions are emitted. */
416 #define MASK_SPARCLITE 0x10
417 #define TARGET_SPARCLITE (target_flags & MASK_SPARCLITE)
419 /* Nonzero if we're compiling for the sparclet. */
420 #define MASK_SPARCLET 0x20
421 #define TARGET_SPARCLET (target_flags & MASK_SPARCLET)
423 /* Nonzero if we're compiling for v9 sparc.
424 Note that v9's can run in 32 bit mode so this doesn't necessarily mean
425 the word size is 64. */
427 #define TARGET_V9 (target_flags & MASK_V9)
429 /* Nonzero to generate code that uses the instructions deprecated in
430 the v9 architecture. This option only applies to v9 systems. */
431 /* ??? This isn't user selectable yet. It's used to enable such insns
432 on 32 bit v9 systems and for the moment they're permanently disabled
433 on 64 bit v9 systems. */
434 #define MASK_DEPRECATED_V8_INSNS 0x80
435 #define TARGET_DEPRECATED_V8_INSNS (target_flags & MASK_DEPRECATED_V8_INSNS)
437 /* Mask of all CPU selection flags. */
439 (MASK_V8 + MASK_SPARCLITE + MASK_SPARCLET + MASK_V9 + MASK_DEPRECATED_V8_INSNS)
441 /* Nonzero means don't pass `-assert pure-text' to the linker. */
442 #define MASK_IMPURE_TEXT 0x100
443 #define TARGET_IMPURE_TEXT (target_flags & MASK_IMPURE_TEXT)
445 /* Nonzero means that we should generate code using a flat register window
446 model, i.e. no save/restore instructions are generated, which is
447 compatible with normal sparc code.
448 The frame pointer is %i7 instead of %fp. */
449 #define MASK_FLAT 0x200
450 #define TARGET_FLAT (target_flags & MASK_FLAT)
452 /* Nonzero means use the registers that the SPARC ABI reserves for
453 application software. This must be the default to coincide with the
454 setting in FIXED_REGISTERS. */
455 #define MASK_APP_REGS 0x400
456 #define TARGET_APP_REGS (target_flags & MASK_APP_REGS)
458 /* Option to select how quad word floating point is implemented.
459 When TARGET_HARD_QUAD is true, we use the hardware quad instructions.
460 Otherwise, we use the SPARC ABI quad library functions. */
461 #define MASK_HARD_QUAD 0x800
462 #define TARGET_HARD_QUAD (target_flags & MASK_HARD_QUAD)
464 /* Nonzero on little-endian machines. */
465 /* ??? Little endian support currently only exists for sparclet-aout and
466 sparc64-elf configurations. May eventually want to expand the support
467 to all targets, but for now it's kept local to only those two. */
468 #define MASK_LITTLE_ENDIAN 0x1000
469 #define TARGET_LITTLE_ENDIAN (target_flags & MASK_LITTLE_ENDIAN)
471 /* 0x2000, 0x4000 are unused */
473 /* Nonzero if pointers are 64 bits. */
474 #define MASK_PTR64 0x8000
475 #define TARGET_PTR64 (target_flags & MASK_PTR64)
477 /* Nonzero if generating code to run in a 64 bit environment.
478 This is intended to only be used by TARGET_ARCH{32,64} as they are the
479 mechanism used to control compile time or run time selection. */
480 #define MASK_64BIT 0x10000
481 #define TARGET_64BIT (target_flags & MASK_64BIT)
483 /* 0x20000,0x40000 unused */
485 /* Nonzero means use a stack bias of 2047. Stack offsets are obtained by
486 adding 2047 to %sp. This option is for v9 only and is the default. */
487 #define MASK_STACK_BIAS 0x80000
488 #define TARGET_STACK_BIAS (target_flags & MASK_STACK_BIAS)
490 /* 0x100000,0x200000 unused */
492 /* Nonzero means -m{,no-}fpu was passed on the command line. */
493 #define MASK_FPU_SET 0x400000
494 #define TARGET_FPU_SET (target_flags & MASK_FPU_SET)
496 /* Use the UltraSPARC Visual Instruction Set extensions. */
497 #define MASK_VIS 0x1000000
498 #define TARGET_VIS (target_flags & MASK_VIS)
500 /* Compile for Solaris V8+. 32 bit Solaris preserves the high bits of
501 the current out and global registers and Linux 2.2+ as well. */
502 #define MASK_V8PLUS 0x2000000
503 #define TARGET_V8PLUS (target_flags & MASK_V8PLUS)
505 /* Force a the fastest alignment on structures to take advantage of
507 #define MASK_FASTER_STRUCTS 0x4000000
508 #define TARGET_FASTER_STRUCTS (target_flags & MASK_FASTER_STRUCTS)
510 /* Use IEEE quad long double. */
511 #define MASK_LONG_DOUBLE_128 0x8000000
512 #define TARGET_LONG_DOUBLE_128 (target_flags & MASK_LONG_DOUBLE_128)
514 /* TARGET_HARD_MUL: Use hardware multiply instructions but not %y.
515 TARGET_HARD_MUL32: Use hardware multiply instructions with rd %y
516 to get high 32 bits. False in V8+ or V9 because multiply stores
517 a 64 bit result in a register. */
519 #define TARGET_HARD_MUL32 \
520 ((TARGET_V8 || TARGET_SPARCLITE \
521 || TARGET_SPARCLET || TARGET_DEPRECATED_V8_INSNS) \
522 && ! TARGET_V8PLUS && TARGET_ARCH32)
524 #define TARGET_HARD_MUL \
525 (TARGET_V8 || TARGET_SPARCLITE || TARGET_SPARCLET \
526 || TARGET_DEPRECATED_V8_INSNS || TARGET_V8PLUS)
529 /* Macro to define tables used to set the flags.
530 This is a list in braces of pairs in braces,
531 each pair being { "NAME", VALUE }
532 where VALUE is the bits to set or minus the bits to clear.
533 An empty string NAME is used to identify the default VALUE. */
535 #define TARGET_SWITCHES \
536 { {"fpu", MASK_FPU | MASK_FPU_SET, \
537 N_("Use hardware fp") }, \
538 {"no-fpu", -MASK_FPU, \
539 N_("Do not use hardware fp") }, \
540 {"no-fpu", MASK_FPU_SET, NULL, }, \
541 {"hard-float", MASK_FPU | MASK_FPU_SET, \
542 N_("Use hardware fp") }, \
543 {"soft-float", -MASK_FPU, \
544 N_("Do not use hardware fp") }, \
545 {"soft-float", MASK_FPU_SET, NULL }, \
546 {"unaligned-doubles", MASK_UNALIGNED_DOUBLES, \
547 N_("Assume possible double misalignment") }, \
548 {"no-unaligned-doubles", -MASK_UNALIGNED_DOUBLES, \
549 N_("Assume all doubles are aligned") }, \
550 {"impure-text", MASK_IMPURE_TEXT, \
551 N_("Pass -assert pure-text to linker") }, \
552 {"no-impure-text", -MASK_IMPURE_TEXT, \
553 N_("Do not pass -assert pure-text to linker") }, \
554 {"flat", MASK_FLAT, \
555 N_("Use flat register window model") }, \
556 {"no-flat", -MASK_FLAT, \
557 N_("Do not use flat register window model") }, \
558 {"app-regs", MASK_APP_REGS, \
559 N_("Use ABI reserved registers") }, \
560 {"no-app-regs", -MASK_APP_REGS, \
561 N_("Do not use ABI reserved registers") }, \
562 {"hard-quad-float", MASK_HARD_QUAD, \
563 N_("Use hardware quad fp instructions") }, \
564 {"soft-quad-float", -MASK_HARD_QUAD, \
565 N_("Do not use hardware quad fp instructions") }, \
566 {"v8plus", MASK_V8PLUS, \
567 N_("Compile for v8plus ABI") }, \
568 {"no-v8plus", -MASK_V8PLUS, \
569 N_("Do not compile for v8plus ABI") }, \
571 N_("Utilize Visual Instruction Set") }, \
572 {"no-vis", -MASK_VIS, \
573 N_("Do not utilize Visual Instruction Set") }, \
574 /* ??? These are deprecated, coerced to -mcpu=. Delete in 2.9. */ \
576 N_("Optimize for Cypress processors") }, \
578 N_("Optimize for SPARCLite processors") }, \
580 N_("Optimize for F930 processors") }, \
582 N_("Optimize for F934 processors") }, \
584 N_("Use V8 SPARC ISA") }, \
586 N_("Optimize for SuperSPARC processors") }, \
587 /* End of deprecated options. */ \
588 {"ptr64", MASK_PTR64, \
589 N_("Pointers are 64-bit") }, \
590 {"ptr32", -MASK_PTR64, \
591 N_("Pointers are 32-bit") }, \
592 {"32", -MASK_64BIT, \
593 N_("Use 32-bit ABI") }, \
595 N_("Use 64-bit ABI") }, \
596 {"stack-bias", MASK_STACK_BIAS, \
597 N_("Use stack bias") }, \
598 {"no-stack-bias", -MASK_STACK_BIAS, \
599 N_("Do not use stack bias") }, \
600 {"faster-structs", MASK_FASTER_STRUCTS, \
601 N_("Use structs on stronger alignment for double-word copies") }, \
602 {"no-faster-structs", -MASK_FASTER_STRUCTS, \
603 N_("Do not use structs on stronger alignment for double-word copies") }, \
605 N_("Optimize tail call instructions in assembler and linker") }, \
607 N_("Do not optimize tail call instructions in assembler or linker") }, \
609 { "", TARGET_DEFAULT, ""}}
611 /* MASK_APP_REGS must always be the default because that's what
612 FIXED_REGISTERS is set to and -ffixed- is processed before
613 CONDITIONAL_REGISTER_USAGE is called (where we process -mno-app-regs). */
614 #define TARGET_DEFAULT (MASK_APP_REGS + MASK_FPU)
616 /* This is meant to be redefined in target specific files. */
617 #define SUBTARGET_SWITCHES
620 These must match the values for the cpu attribute in sparc.md. */
621 enum processor_type {
625 PROCESSOR_SUPERSPARC,
629 PROCESSOR_HYPERSPARC,
630 PROCESSOR_SPARCLITE86X,
634 PROCESSOR_ULTRASPARC,
635 PROCESSOR_ULTRASPARC3
638 /* This is set from -m{cpu,tune}=xxx. */
639 extern enum processor_type sparc_cpu;
641 /* Recast the cpu class to be the cpu attribute.
642 Every file includes us, but not every file includes insn-attr.h. */
643 #define sparc_cpu_attr ((enum attr_cpu) sparc_cpu)
645 #define TARGET_OPTIONS \
647 { "cpu=", &sparc_select[1].string, \
648 N_("Use features of and schedule code for given CPU"), 0}, \
649 { "tune=", &sparc_select[2].string, \
650 N_("Schedule code for given CPU"), 0}, \
651 { "cmodel=", &sparc_cmodel_string, \
652 N_("Use given SPARC code model"), 0}, \
656 /* This is meant to be redefined in target specific files. */
657 #define SUBTARGET_OPTIONS
659 /* Support for a compile-time default CPU, et cetera. The rules are:
660 --with-cpu is ignored if -mcpu is specified.
661 --with-tune is ignored if -mtune is specified.
662 --with-float is ignored if -mhard-float, -msoft-float, -mfpu, or -mno-fpu
664 #define OPTION_DEFAULT_SPECS \
665 {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \
666 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
667 {"float", "%{!msoft-float:%{!mhard-float:%{!fpu:%{!no-fpu:-m%(VALUE)-float}}}}" }
669 /* sparc_select[0] is reserved for the default cpu. */
670 struct sparc_cpu_select
673 const char *const name;
674 const int set_tune_p;
675 const int set_arch_p;
678 extern struct sparc_cpu_select sparc_select[];
680 /* target machine storage layout */
682 /* Define this if most significant bit is lowest numbered
683 in instructions that operate on numbered bit-fields. */
684 #define BITS_BIG_ENDIAN 1
686 /* Define this if most significant byte of a word is the lowest numbered. */
687 #define BYTES_BIG_ENDIAN 1
689 /* Define this if most significant word of a multiword number is the lowest
691 #define WORDS_BIG_ENDIAN 1
693 /* Define this to set the endianness to use in libgcc2.c, which can
694 not depend on target_flags. */
695 #if defined (__LITTLE_ENDIAN__) || defined(__LITTLE_ENDIAN_DATA__)
696 #define LIBGCC2_WORDS_BIG_ENDIAN 0
698 #define LIBGCC2_WORDS_BIG_ENDIAN 1
701 #define MAX_BITS_PER_WORD 64
703 /* Width of a word, in units (bytes). */
704 #define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4)
706 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
708 #define MIN_UNITS_PER_WORD 4
711 /* Now define the sizes of the C data types. */
713 #define SHORT_TYPE_SIZE 16
714 #define INT_TYPE_SIZE 32
715 #define LONG_TYPE_SIZE (TARGET_ARCH64 ? 64 : 32)
716 #define LONG_LONG_TYPE_SIZE 64
717 #define FLOAT_TYPE_SIZE 32
718 #define DOUBLE_TYPE_SIZE 64
721 #define MAX_LONG_TYPE_SIZE 64
725 /* ??? This does not work in SunOS 4.x, so it is not enabled here.
726 Instead, it is enabled in sol2.h, because it does work under Solaris. */
727 /* Define for support of TFmode long double.
728 SPARC ABI says that long double is 4 words. */
729 #define LONG_DOUBLE_TYPE_SIZE 128
732 /* Width in bits of a pointer.
733 See also the macro `Pmode' defined below. */
734 #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32)
736 /* If we have to extend pointers (only when TARGET_ARCH64 and not
737 TARGET_PTR64), we want to do it unsigned. This macro does nothing
738 if ptr_mode and Pmode are the same. */
739 #define POINTERS_EXTEND_UNSIGNED 1
741 /* A macro to update MODE and UNSIGNEDP when an object whose type
742 is TYPE and which has the specified mode and signedness is to be
743 stored in a register. This macro is only called when TYPE is a
745 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
747 && GET_MODE_CLASS (MODE) == MODE_INT \
748 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
751 /* Define this macro if the promotion described by PROMOTE_MODE
752 should _only_ be performed for outgoing function arguments or
753 function return values, as specified by PROMOTE_FUNCTION_ARGS
754 and PROMOTE_FUNCTION_RETURN, respectively. */
755 /* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op
756 for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test
757 for this value. For TARGET_ARCH64 we need it, as we don't have instructions
758 for arithmetic operations which do zero/sign extension at the same time,
759 so without this we end up with a srl/sra after every assignment to an
760 user variable, which means very very bad code. */
761 #define PROMOTE_FOR_CALL_ONLY
763 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
764 #define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
766 /* Boundary (in *bits*) on which stack pointer should be aligned. */
767 /* FIXME, this is wrong when TARGET_ARCH64 and TARGET_STACK_BIAS, because
768 then sp+2047 is 128-bit aligned so sp is really only byte-aligned. */
769 #define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64)
770 /* Temporary hack until the FIXME above is fixed. This macro is used
771 only in pad_to_arg_alignment in function.c; see the comment there
772 for details about what it does. */
773 #define SPARC_STACK_BOUNDARY_HACK (TARGET_ARCH64 && TARGET_STACK_BIAS)
775 /* ALIGN FRAMES on double word boundaries */
777 #define SPARC_STACK_ALIGN(LOC) \
778 (TARGET_ARCH64 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7))
780 /* Allocation boundary (in *bits*) for the code of a function. */
781 #define FUNCTION_BOUNDARY 32
783 /* Alignment of field after `int : 0' in a structure. */
784 #define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
786 /* Every structure's size must be a multiple of this. */
787 #define STRUCTURE_SIZE_BOUNDARY 8
789 /* A bit-field declared as `int' forces `int' alignment for the struct. */
790 #define PCC_BITFIELD_TYPE_MATTERS 1
792 /* No data type wants to be aligned rounder than this. */
793 #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64)
795 /* The best alignment to use in cases where we have a choice. */
796 #define FASTEST_ALIGNMENT 64
798 /* Define this macro as an expression for the alignment of a structure
799 (given by STRUCT as a tree node) if the alignment computed in the
800 usual way is COMPUTED and the alignment explicitly specified was
803 The default is to use SPECIFIED if it is larger; otherwise, use
804 the smaller of COMPUTED and `BIGGEST_ALIGNMENT' */
805 #define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \
806 (TARGET_FASTER_STRUCTS ? \
807 ((TREE_CODE (STRUCT) == RECORD_TYPE \
808 || TREE_CODE (STRUCT) == UNION_TYPE \
809 || TREE_CODE (STRUCT) == QUAL_UNION_TYPE) \
810 && TYPE_FIELDS (STRUCT) != 0 \
811 ? MAX (MAX ((COMPUTED), (SPECIFIED)), BIGGEST_ALIGNMENT) \
812 : MAX ((COMPUTED), (SPECIFIED))) \
813 : MAX ((COMPUTED), (SPECIFIED)))
815 /* Make strings word-aligned so strcpy from constants will be faster. */
816 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
817 ((TREE_CODE (EXP) == STRING_CST \
818 && (ALIGN) < FASTEST_ALIGNMENT) \
819 ? FASTEST_ALIGNMENT : (ALIGN))
821 /* Make arrays of chars word-aligned for the same reasons. */
822 #define DATA_ALIGNMENT(TYPE, ALIGN) \
823 (TREE_CODE (TYPE) == ARRAY_TYPE \
824 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
825 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
827 /* Set this nonzero if move instructions will actually fail to work
828 when given unaligned data. */
829 #define STRICT_ALIGNMENT 1
831 /* Things that must be doubleword aligned cannot go in the text section,
832 because the linker fails to align the text section enough!
833 Put them in the data section. This macro is only used in this file. */
834 #define MAX_TEXT_ALIGN 32
836 /* This forces all variables and constants to the data section when PIC.
837 This is because the SunOS 4 shared library scheme thinks everything in
838 text is a function, and patches the address to point to a loader stub. */
839 /* This is defined to zero for every system which doesn't use the a.out object
841 #ifndef SUNOS4_SHARED_LIBRARIES
842 #define SUNOS4_SHARED_LIBRARIES 0
845 /* Standard register usage. */
847 /* Number of actual hardware registers.
848 The hardware registers are assigned numbers for the compiler
849 from 0 to just below FIRST_PSEUDO_REGISTER.
850 All registers that the compiler knows about must be given numbers,
851 even those that are not normally considered general registers.
853 SPARC has 32 integer registers and 32 floating point registers.
854 64 bit SPARC has 32 additional fp regs, but the odd numbered ones are not
855 accessible. We still account for them to simplify register computations
856 (eg: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so
858 Register 100 is used as the integer condition code register.
859 Register 101 is used as the soft frame pointer register. */
861 #define FIRST_PSEUDO_REGISTER 102
863 #define SPARC_FIRST_FP_REG 32
864 /* Additional V9 fp regs. */
865 #define SPARC_FIRST_V9_FP_REG 64
866 #define SPARC_LAST_V9_FP_REG 95
867 /* V9 %fcc[0123]. V8 uses (figuratively) %fcc0. */
868 #define SPARC_FIRST_V9_FCC_REG 96
869 #define SPARC_LAST_V9_FCC_REG 99
871 #define SPARC_FCC_REG 96
872 /* Integer CC reg. We don't distinguish %icc from %xcc. */
873 #define SPARC_ICC_REG 100
875 /* Nonzero if REGNO is an fp reg. */
876 #define SPARC_FP_REG_P(REGNO) \
877 ((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG)
879 /* Argument passing regs. */
880 #define SPARC_OUTGOING_INT_ARG_FIRST 8
881 #define SPARC_INCOMING_INT_ARG_FIRST (TARGET_FLAT ? 8 : 24)
882 #define SPARC_FP_ARG_FIRST 32
884 /* 1 for registers that have pervasive standard uses
885 and are not available for the register allocator.
888 g1 is free to use as temporary.
889 g2-g4 are reserved for applications. Gcc normally uses them as
890 temporaries, but this can be disabled via the -mno-app-regs option.
891 g5 through g7 are reserved for the operating system.
894 g1,g5 are free to use as temporaries, and are free to use between calls
895 if the call is to an external function via the PLT.
896 g4 is free to use as a temporary in the non-embedded case.
897 g4 is reserved in the embedded case.
898 g2-g3 are reserved for applications. Gcc normally uses them as
899 temporaries, but this can be disabled via the -mno-app-regs option.
900 g6-g7 are reserved for the operating system (or application in
902 ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must
903 currently be a fixed register until this pattern is rewritten.
904 Register 1 is also used when restoring call-preserved registers in large
907 Registers fixed in arch32 and not arch64 (or vice-versa) are marked in
908 CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-.
911 #define FIXED_REGISTERS \
912 {1, 0, 2, 2, 2, 2, 1, 1, \
913 0, 0, 0, 0, 0, 0, 1, 0, \
914 0, 0, 0, 0, 0, 0, 0, 0, \
915 0, 0, 0, 0, 0, 0, 1, 1, \
917 0, 0, 0, 0, 0, 0, 0, 0, \
918 0, 0, 0, 0, 0, 0, 0, 0, \
919 0, 0, 0, 0, 0, 0, 0, 0, \
920 0, 0, 0, 0, 0, 0, 0, 0, \
922 0, 0, 0, 0, 0, 0, 0, 0, \
923 0, 0, 0, 0, 0, 0, 0, 0, \
924 0, 0, 0, 0, 0, 0, 0, 0, \
925 0, 0, 0, 0, 0, 0, 0, 0, \
929 /* 1 for registers not available across function calls.
930 These must include the FIXED_REGISTERS and also any
931 registers that can be used without being saved.
932 The latter must include the registers where values are returned
933 and the register where structure-value addresses are passed.
934 Aside from that, you can include as many other registers as you like. */
936 #define CALL_USED_REGISTERS \
937 {1, 1, 1, 1, 1, 1, 1, 1, \
938 1, 1, 1, 1, 1, 1, 1, 1, \
939 0, 0, 0, 0, 0, 0, 0, 0, \
940 0, 0, 0, 0, 0, 0, 1, 1, \
942 1, 1, 1, 1, 1, 1, 1, 1, \
943 1, 1, 1, 1, 1, 1, 1, 1, \
944 1, 1, 1, 1, 1, 1, 1, 1, \
945 1, 1, 1, 1, 1, 1, 1, 1, \
947 1, 1, 1, 1, 1, 1, 1, 1, \
948 1, 1, 1, 1, 1, 1, 1, 1, \
949 1, 1, 1, 1, 1, 1, 1, 1, \
950 1, 1, 1, 1, 1, 1, 1, 1, \
954 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
955 they won't be allocated. */
957 #define CONDITIONAL_REGISTER_USAGE \
960 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
962 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
963 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
965 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */ \
966 /* then honor it. */ \
967 if (TARGET_ARCH32 && fixed_regs[5]) \
969 else if (TARGET_ARCH64 && fixed_regs[5] == 2) \
974 for (regno = SPARC_FIRST_V9_FP_REG; \
975 regno <= SPARC_LAST_V9_FP_REG; \
977 fixed_regs[regno] = 1; \
978 /* %fcc0 is used by v8 and v9. */ \
979 for (regno = SPARC_FIRST_V9_FCC_REG + 1; \
980 regno <= SPARC_LAST_V9_FCC_REG; \
982 fixed_regs[regno] = 1; \
987 for (regno = 32; regno < SPARC_LAST_V9_FCC_REG; regno++) \
988 fixed_regs[regno] = 1; \
990 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */ \
991 /* then honor it. Likewise with g3 and g4. */ \
992 if (fixed_regs[2] == 2) \
993 fixed_regs[2] = ! TARGET_APP_REGS; \
994 if (fixed_regs[3] == 2) \
995 fixed_regs[3] = ! TARGET_APP_REGS; \
996 if (TARGET_ARCH32 && fixed_regs[4] == 2) \
997 fixed_regs[4] = ! TARGET_APP_REGS; \
998 else if (TARGET_CM_EMBMEDANY) \
1000 else if (fixed_regs[4] == 2) \
1001 fixed_regs[4] = 0; \
1005 /* Let the compiler believe the frame pointer is still \
1006 %fp, but output it as %i7. */ \
1007 fixed_regs[31] = 1; \
1008 reg_names[HARD_FRAME_POINTER_REGNUM] = "%i7"; \
1009 /* Disable leaf functions */ \
1010 memset (sparc_leaf_regs, 0, FIRST_PSEUDO_REGISTER); \
1011 /* Make LEAF_REG_REMAP a noop. */ \
1012 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
1013 leaf_reg_remap [regno] = regno; \
1018 /* Return number of consecutive hard regs needed starting at reg REGNO
1019 to hold something of mode MODE.
1020 This is ordinarily the length in words of a value of mode MODE
1021 but can be less for certain modes in special long registers.
1023 On SPARC, ordinary registers hold 32 bits worth;
1024 this means both integer and floating point registers.
1025 On v9, integer regs hold 64 bits worth; floating point regs hold
1026 32 bits worth (this includes the new fp regs as even the odd ones are
1027 included in the hard register count). */
1029 #define HARD_REGNO_NREGS(REGNO, MODE) \
1031 ? ((REGNO) < 32 || (REGNO) == FRAME_POINTER_REGNUM \
1032 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \
1033 : (GET_MODE_SIZE (MODE) + 3) / 4) \
1034 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1036 /* Due to the ARCH64 discrepancy above we must override this next
1038 #define REGMODE_NATURAL_SIZE(MODE) \
1039 ((TARGET_ARCH64 && FLOAT_MODE_P (MODE)) ? 4 : UNITS_PER_WORD)
1041 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
1042 See sparc.c for how we initialize this. */
1043 extern const int *hard_regno_mode_classes;
1044 extern int sparc_mode_class[];
1046 /* ??? Because of the funny way we pass parameters we should allow certain
1047 ??? types of float/complex values to be in integer registers during
1048 ??? RTL generation. This only matters on arch32. */
1049 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1050 ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0)
1052 /* Value is 1 if it is a good idea to tie two pseudo registers
1053 when one has mode MODE1 and one has mode MODE2.
1054 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1055 for any hard reg, then this must be 0 for correct output.
1057 For V9: SFmode can't be combined with other float modes, because they can't
1058 be allocated to the %d registers. Also, DFmode won't fit in odd %f
1059 registers, but SFmode will. */
1060 #define MODES_TIEABLE_P(MODE1, MODE2) \
1061 ((MODE1) == (MODE2) \
1062 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
1064 || (GET_MODE_CLASS (MODE1) != MODE_FLOAT \
1065 || (MODE1 != SFmode && MODE2 != SFmode)))))
1067 /* Specify the registers used for certain standard purposes.
1068 The values of these macros are register numbers. */
1070 /* SPARC pc isn't overloaded on a register that the compiler knows about. */
1071 /* #define PC_REGNUM */
1073 /* Register to use for pushing function arguments. */
1074 #define STACK_POINTER_REGNUM 14
1076 /* The stack bias (amount by which the hardware register is offset by). */
1077 #define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0)
1079 /* Actual top-of-stack address is 92/176 greater than the contents of the
1080 stack pointer register for !v9/v9. That is:
1081 - !v9: 64 bytes for the in and local registers, 4 bytes for structure return
1082 address, and 6*4 bytes for the 6 register parameters.
1083 - v9: 128 bytes for the in and local registers + 6*8 bytes for the integer
1085 #define STACK_POINTER_OFFSET (FIRST_PARM_OFFSET(0) + SPARC_STACK_BIAS)
1087 /* Base register for access to local variables of the function. */
1088 #define HARD_FRAME_POINTER_REGNUM 30
1090 /* The soft frame pointer does not have the stack bias applied. */
1091 #define FRAME_POINTER_REGNUM 101
1093 /* Given the stack bias, the stack pointer isn't actually aligned. */
1094 #define INIT_EXPANDERS \
1096 if (cfun && cfun->emit->regno_pointer_align && SPARC_STACK_BIAS) \
1098 REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = BITS_PER_UNIT; \
1099 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT; \
1103 /* Value should be nonzero if functions must have frame pointers.
1104 Zero means the frame pointer need not be set up (and parms
1105 may be accessed via the stack pointer) in functions that seem suitable.
1106 This is computed in `reload', in reload1.c.
1107 Used in flow.c, global.c, and reload1.c.
1109 Being a non-leaf function does not mean a frame pointer is needed in the
1110 flat window model. However, the debugger won't be able to backtrace through
1112 #define FRAME_POINTER_REQUIRED \
1114 ? (current_function_calls_alloca \
1115 || !leaf_function_p ()) \
1116 : ! (leaf_function_p () && only_leaf_regs_used ()))
1118 /* Base register for access to arguments of the function. */
1119 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM
1121 /* Register in which static-chain is passed to a function. This must
1122 not be a register used by the prologue. */
1123 #define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2)
1125 /* Register which holds offset table for position-independent
1128 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 23 : INVALID_REGNUM)
1130 /* Pick a default value we can notice from override_options:
1132 v9: Default is off. */
1134 #define DEFAULT_PCC_STRUCT_RETURN -1
1136 /* Functions which return large structures get the address
1137 to place the wanted value at offset 64 from the frame.
1138 Must reserve 64 bytes for the in and local registers.
1139 v9: Functions which return large structures get the address to place the
1140 wanted value from an invisible first argument. */
1141 #define STRUCT_VALUE_OFFSET 64
1143 /* Define the classes of registers for register constraints in the
1144 machine description. Also define ranges of constants.
1146 One of the classes must always be named ALL_REGS and include all hard regs.
1147 If there is more than one class, another class must be named NO_REGS
1148 and contain no registers.
1150 The name GENERAL_REGS must be the name of a class (or an alias for
1151 another name such as ALL_REGS). This is the class of registers
1152 that is allowed by "g" or "r" in a register constraint.
1153 Also, registers outside this class are allocated only when
1154 instructions express preferences for them.
1156 The classes must be numbered in nondecreasing order; that is,
1157 a larger-numbered class must never be contained completely
1158 in a smaller-numbered class.
1160 For any two classes, it is very desirable that there be another
1161 class that represents their union. */
1163 /* The SPARC has various kinds of registers: general, floating point,
1164 and condition codes [well, it has others as well, but none that we
1165 care directly about].
1167 For v9 we must distinguish between the upper and lower floating point
1168 registers because the upper ones can't hold SFmode values.
1169 HARD_REGNO_MODE_OK won't help here because reload assumes that register(s)
1170 satisfying a group need for a class will also satisfy a single need for
1171 that class. EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp
1174 It is important that one class contains all the general and all the standard
1175 fp regs. Otherwise find_reg() won't properly allocate int regs for moves,
1176 because reg_class_record() will bias the selection in favor of fp regs,
1177 because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS,
1178 because FP_REGS > GENERAL_REGS.
1180 It is also important that one class contain all the general and all the
1181 fp regs. Otherwise when spilling a DFmode reg, it may be from EXTRA_FP_REGS
1182 but find_reloads() may use class GENERAL_OR_FP_REGS. This will cause
1183 allocate_reload_reg() to bypass it causing an abort because the compiler
1184 thinks it doesn't have a spill reg when in fact it does.
1186 v9 also has 4 floating point condition code registers. Since we don't
1187 have a class that is the union of FPCC_REGS with either of the others,
1188 it is important that it appear first. Otherwise the compiler will die
1189 trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its
1192 It is important that SPARC_ICC_REG have class NO_REGS. Otherwise combine
1193 may try to use it to hold an SImode value. See register_operand.
1194 ??? Should %fcc[0123] be handled similarly?
1197 enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS,
1198 EXTRA_FP_REGS, GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS,
1199 ALL_REGS, LIM_REG_CLASSES };
1201 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1203 /* Give names of register classes as strings for dump file. */
1205 #define REG_CLASS_NAMES \
1206 { "NO_REGS", "FPCC_REGS", "I64_REGS", "GENERAL_REGS", "FP_REGS", \
1207 "EXTRA_FP_REGS", "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", \
1210 /* Define which registers fit in which classes.
1211 This is an initializer for a vector of HARD_REG_SET
1212 of length N_REG_CLASSES. */
1214 #define REG_CLASS_CONTENTS \
1215 {{0, 0, 0, 0}, /* NO_REGS */ \
1216 {0, 0, 0, 0xf}, /* FPCC_REGS */ \
1217 {0xffff, 0, 0, 0}, /* I64_REGS */ \
1218 {-1, 0, 0, 0x20}, /* GENERAL_REGS */ \
1219 {0, -1, 0, 0}, /* FP_REGS */ \
1220 {0, -1, -1, 0}, /* EXTRA_FP_REGS */ \
1221 {-1, -1, 0, 0x20}, /* GENERAL_OR_FP_REGS */ \
1222 {-1, -1, -1, 0x20}, /* GENERAL_OR_EXTRA_FP_REGS */ \
1223 {-1, -1, -1, 0x3f}} /* ALL_REGS */
1225 /* Defines invalid mode changes. Borrowed from pa64-regs.h.
1227 SImode loads to floating-point registers are not zero-extended.
1228 The definition for LOAD_EXTEND_OP specifies that integer loads
1229 narrower than BITS_PER_WORD will be zero-extended. As a result,
1230 we inhibit changes from SImode unless they are to a mode that is
1231 identical in size. */
1233 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1235 && (FROM) == SImode \
1236 && GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1237 ? reg_classes_intersect_p (CLASS, FP_REGS) : 0)
1239 /* The same information, inverted:
1240 Return the class number of the smallest class containing
1241 reg number REGNO. This could be a conditional expression
1242 or could index an array. */
1244 extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
1246 #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)]
1248 /* This is the order in which to allocate registers normally.
1250 We put %f0-%f7 last among the float registers, so as to make it more
1251 likely that a pseudo-register which dies in the float return register
1252 area will get allocated to the float return register, thus saving a move
1253 instruction at the end of the function.
1255 Similarly for integer return value registers.
1257 We know in this case that we will not end up with a leaf function.
1259 The register allocator is given the global and out registers first
1260 because these registers are call clobbered and thus less useful to
1261 global register allocation.
1263 Next we list the local and in registers. They are not call clobbered
1264 and thus very useful for global register allocation. We list the input
1265 registers before the locals so that it is more likely the incoming
1266 arguments received in those registers can just stay there and not be
1269 #define REG_ALLOC_ORDER \
1270 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \
1271 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \
1273 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \
1274 29, 28, 27, 26, 25, 24, 31, /* %i5-%i0,%i7 */\
1275 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \
1276 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \
1277 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \
1278 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \
1279 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \
1280 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \
1281 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \
1282 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \
1283 96, 97, 98, 99, /* %fcc0-3 */ \
1284 100, 0, 14, 30, 101} /* %icc, %g0, %o6, %i6, %sfp */
1286 /* This is the order in which to allocate registers for
1287 leaf functions. If all registers can fit in the global and
1288 output registers, then we have the possibility of having a leaf
1291 The macro actually mentioned the input registers first,
1292 because they get renumbered into the output registers once
1293 we know really do have a leaf function.
1295 To be more precise, this register allocation order is used
1296 when %o7 is found to not be clobbered right before register
1297 allocation. Normally, the reason %o7 would be clobbered is
1298 due to a call which could not be transformed into a sibling
1301 As a consequence, it is possible to use the leaf register
1302 allocation order and not end up with a leaf function. We will
1303 not get suboptimal register allocation in that case because by
1304 definition of being potentially leaf, there were no function
1305 calls. Therefore, allocation order within the local register
1306 window is not critical like it is when we do have function calls. */
1308 #define REG_LEAF_ALLOC_ORDER \
1309 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \
1310 29, 28, 27, 26, 25, 24, /* %i5-%i0 */ \
1312 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \
1313 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \
1314 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \
1315 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \
1316 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \
1317 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \
1318 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \
1319 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \
1320 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \
1321 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \
1322 96, 97, 98, 99, /* %fcc0-3 */ \
1323 100, 0, 14, 30, 31, 101} /* %icc, %g0, %o6, %i6, %i7, %sfp */
1325 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
1327 extern char sparc_leaf_regs[];
1328 #define LEAF_REGISTERS sparc_leaf_regs
1330 extern char leaf_reg_remap[];
1331 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO])
1333 /* The class value for index registers, and the one for base regs. */
1334 #define INDEX_REG_CLASS GENERAL_REGS
1335 #define BASE_REG_CLASS GENERAL_REGS
1337 /* Local macro to handle the two v9 classes of FP regs. */
1338 #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS)
1340 /* Get reg_class from a letter such as appears in the machine description.
1341 In the not-v9 case, coerce v9's 'e' class to 'f', so we can use 'e' in the
1342 .md file for v8 and v9.
1343 'd' and 'b' are used for single and double precision VIS operations,
1345 'h' is used for V8+ 64 bit global and out registers. */
1347 #define REG_CLASS_FROM_LETTER(C) \
1349 ? ((C) == 'f' ? FP_REGS \
1350 : (C) == 'e' ? EXTRA_FP_REGS \
1351 : (C) == 'c' ? FPCC_REGS \
1352 : ((C) == 'd' && TARGET_VIS) ? FP_REGS\
1353 : ((C) == 'b' && TARGET_VIS) ? EXTRA_FP_REGS\
1354 : ((C) == 'h' && TARGET_V8PLUS) ? I64_REGS\
1356 : ((C) == 'f' ? FP_REGS \
1357 : (C) == 'e' ? FP_REGS \
1358 : (C) == 'c' ? FPCC_REGS \
1361 /* The letters I, J, K, L and M in a register constraint string
1362 can be used to stand for particular ranges of immediate operands.
1363 This macro defines what the ranges are.
1364 C is the letter, and VALUE is a constant value.
1365 Return 1 if VALUE is in the range specified by C.
1367 `I' is used for the range of constants an insn can actually contain.
1368 `J' is used for the range which is just zero (since that is R0).
1369 `K' is used for constants which can be loaded with a single sethi insn.
1370 `L' is used for the range of constants supported by the movcc insns.
1371 `M' is used for the range of constants supported by the movrcc insns.
1372 `N' is like K, but for constants wider than 32 bits.
1373 `O' is used for the range which is just 4096. */
1375 #define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400)
1376 #define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800)
1377 #define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000)
1378 /* 10 and 11 bit immediates are only used for a few specific insns.
1379 SMALL_INT is used throughout the port so we continue to use it. */
1380 #define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X)))
1381 /* 13 bit immediate, considering only the low 32 bits */
1382 #define SMALL_INT32(X) (SPARC_SIMM13_P (trunc_int_for_mode \
1383 (INTVAL (X), SImode)))
1384 #define SPARC_SETHI_P(X) \
1385 (((unsigned HOST_WIDE_INT) (X) \
1386 & ((unsigned HOST_WIDE_INT) 0x3ff - GET_MODE_MASK (SImode) - 1)) == 0)
1387 #define SPARC_SETHI32_P(X) \
1388 (SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode)))
1390 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1391 ((C) == 'I' ? SPARC_SIMM13_P (VALUE) \
1392 : (C) == 'J' ? (VALUE) == 0 \
1393 : (C) == 'K' ? SPARC_SETHI32_P (VALUE) \
1394 : (C) == 'L' ? SPARC_SIMM11_P (VALUE) \
1395 : (C) == 'M' ? SPARC_SIMM10_P (VALUE) \
1396 : (C) == 'N' ? SPARC_SETHI_P (VALUE) \
1397 : (C) == 'O' ? (VALUE) == 4096 \
1400 /* Similar, but for floating constants, and defining letters G and H.
1401 Here VALUE is the CONST_DOUBLE rtx itself. */
1403 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1404 ((C) == 'G' ? fp_zero_operand (VALUE, GET_MODE (VALUE)) \
1405 : (C) == 'H' ? arith_double_operand (VALUE, DImode) \
1406 : (C) == 'O' ? arith_double_4096_operand (VALUE, DImode) \
1409 /* Given an rtx X being reloaded into a reg required to be
1410 in class CLASS, return the class of reg to actually use.
1411 In general this is just CLASS; but on some machines
1412 in some cases it is preferable to use a more restrictive class. */
1413 /* - We can't load constants into FP registers.
1414 - We can't load FP constants into integer registers when soft-float,
1415 because there is no soft-float pattern with a r/F constraint.
1416 - We can't load FP constants into integer registers for TFmode unless
1417 it is 0.0L, because there is no movtf pattern with a r/F constraint.
1418 - Try and reload integer constants (symbolic or otherwise) back into
1419 registers directly, rather than having them dumped to memory. */
1421 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1423 ? ((FP_REG_CLASS_P (CLASS) \
1424 || (CLASS) == GENERAL_OR_FP_REGS \
1425 || (CLASS) == GENERAL_OR_EXTRA_FP_REGS \
1426 || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1428 || (GET_MODE (X) == TFmode \
1429 && ! fp_zero_operand (X, TFmode))) \
1431 : (!FP_REG_CLASS_P (CLASS) \
1432 && GET_MODE_CLASS (GET_MODE (X)) == MODE_INT) \
1437 /* Return the register class of a scratch register needed to load IN into
1438 a register of class CLASS in MODE.
1440 We need a temporary when loading/storing a HImode/QImode value
1441 between memory and the FPU registers. This can happen when combine puts
1442 a paradoxical subreg in a float/fix conversion insn.
1444 We need a temporary when loading/storing a DFmode value between
1445 unaligned memory and the upper FPU registers. */
1447 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1448 ((FP_REG_CLASS_P (CLASS) \
1449 && ((MODE) == HImode || (MODE) == QImode) \
1450 && (GET_CODE (IN) == MEM \
1451 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1452 && true_regnum (IN) == -1))) \
1454 : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \
1455 && GET_CODE (IN) == MEM && TARGET_ARCH32 \
1456 && ! mem_min_alignment ((IN), 8)) \
1458 : (((TARGET_CM_MEDANY \
1459 && symbolic_operand ((IN), (MODE))) \
1460 || (TARGET_CM_EMBMEDANY \
1461 && text_segment_operand ((IN), (MODE)))) \
1466 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1467 ((FP_REG_CLASS_P (CLASS) \
1468 && ((MODE) == HImode || (MODE) == QImode) \
1469 && (GET_CODE (IN) == MEM \
1470 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1471 && true_regnum (IN) == -1))) \
1473 : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \
1474 && GET_CODE (IN) == MEM && TARGET_ARCH32 \
1475 && ! mem_min_alignment ((IN), 8)) \
1477 : (((TARGET_CM_MEDANY \
1478 && symbolic_operand ((IN), (MODE))) \
1479 || (TARGET_CM_EMBMEDANY \
1480 && text_segment_operand ((IN), (MODE)))) \
1485 /* On SPARC it is not possible to directly move data between
1486 GENERAL_REGS and FP_REGS. */
1487 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1488 (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2))
1490 /* Return the stack location to use for secondary memory needed reloads.
1491 We want to use the reserved location just below the frame pointer.
1492 However, we must ensure that there is a frame, so use assign_stack_local
1493 if the frame size is zero. */
1494 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
1495 (get_frame_size () == 0 \
1496 ? assign_stack_local (MODE, GET_MODE_SIZE (MODE), 0) \
1497 : gen_rtx_MEM (MODE, plus_constant (frame_pointer_rtx, \
1498 STARTING_FRAME_OFFSET)))
1500 /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9
1501 because the movsi and movsf patterns don't handle r/f moves.
1502 For v8 we copy the default definition. */
1503 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
1505 ? (GET_MODE_BITSIZE (MODE) < 32 \
1506 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
1508 : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \
1509 ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0) \
1512 /* Return the maximum number of consecutive registers
1513 needed to represent mode MODE in a register of class CLASS. */
1514 /* On SPARC, this is the size of MODE in words. */
1515 #define CLASS_MAX_NREGS(CLASS, MODE) \
1516 (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \
1517 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1519 /* Stack layout; function entry, exit and calling. */
1521 /* Define the number of register that can hold parameters.
1522 This macro is only used in other macro definitions below and in sparc.c.
1523 MODE is the mode of the argument.
1524 !v9: All args are passed in %o0-%o5.
1525 v9: %o0-%o5 and %f0-%f31 are cumulatively used to pass values.
1526 See the description in sparc.c. */
1527 #define NPARM_REGS(MODE) \
1529 ? (GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 6) \
1532 /* Define this if pushing a word on the stack
1533 makes the stack pointer a smaller address. */
1534 #define STACK_GROWS_DOWNWARD
1536 /* Define this if the nominal address of the stack frame
1537 is at the high-address end of the local variables;
1538 that is, each additional local variable allocated
1539 goes at a more negative offset in the frame. */
1540 #define FRAME_GROWS_DOWNWARD
1542 /* Offset within stack frame to start allocating local variables at.
1543 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1544 first local allocated. Otherwise, it is the offset to the BEGINNING
1545 of the first local allocated. */
1546 /* This allows space for one TFmode floating point value. */
1547 #define STARTING_FRAME_OFFSET \
1548 (TARGET_ARCH64 ? -16 \
1549 : (-SPARC_STACK_ALIGN (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)))
1551 /* If we generate an insn to push BYTES bytes,
1552 this says how many the stack pointer really advances by.
1553 On SPARC, don't define this because there are no push insns. */
1554 /* #define PUSH_ROUNDING(BYTES) */
1556 /* Offset of first parameter from the argument pointer register value.
1557 !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg
1558 even if this function isn't going to use it.
1559 v9: This is 128 for the ins and locals. */
1560 #define FIRST_PARM_OFFSET(FNDECL) \
1561 (TARGET_ARCH64 ? 16 * UNITS_PER_WORD : STRUCT_VALUE_OFFSET + UNITS_PER_WORD)
1563 /* Offset from the argument pointer register value to the CFA.
1564 This is different from FIRST_PARM_OFFSET because the register window
1565 comes between the CFA and the arguments. */
1566 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1568 /* When a parameter is passed in a register, stack space is still
1570 !v9: All 6 possible integer registers have backing store allocated.
1571 v9: Only space for the arguments passed is allocated. */
1572 /* ??? Ideally, we'd use zero here (as the minimum), but zero has special
1573 meaning to the backend. Further, we need to be able to detect if a
1574 varargs/unprototyped function is called, as they may want to spill more
1575 registers than we've provided space. Ugly, ugly. So for now we retain
1576 all 6 slots even for v9. */
1577 #define REG_PARM_STACK_SPACE(DECL) (6 * UNITS_PER_WORD)
1579 /* Definitions for register elimination. */
1580 /* ??? In TARGET_FLAT mode we needn't have a hard frame pointer. */
1582 #define ELIMINABLE_REGS \
1583 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1584 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM} }
1586 /* The way this is structured, we can't eliminate SFP in favor of SP
1587 if the frame pointer is required: we want to use the SFP->HFP elimination
1588 in that case. But the test in update_eliminables doesn't know we are
1589 assuming below that we only do the former elimination. */
1590 #define CAN_ELIMINATE(FROM, TO) \
1591 ((TO) == HARD_FRAME_POINTER_REGNUM || !FRAME_POINTER_REQUIRED)
1593 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1596 if ((TO) == STACK_POINTER_REGNUM) \
1598 /* Note, we always pretend that this is a leaf function \
1599 because if it's not, there's no point in trying to \
1600 eliminate the frame pointer. If it is a leaf \
1601 function, we guessed right! */ \
1604 sparc_flat_compute_frame_size (get_frame_size ()); \
1606 (OFFSET) = compute_frame_size (get_frame_size (), 1); \
1608 (OFFSET) += SPARC_STACK_BIAS; \
1611 /* Keep the stack pointer constant throughout the function.
1612 This is both an optimization and a necessity: longjmp
1613 doesn't behave itself when the stack pointer moves within
1615 #define ACCUMULATE_OUTGOING_ARGS 1
1617 /* Value is the number of bytes of arguments automatically
1618 popped when returning from a subroutine call.
1619 FUNDECL is the declaration node of the function (as a tree),
1620 FUNTYPE is the data type of the function (as a tree),
1621 or for a library call it is an identifier node for the subroutine name.
1622 SIZE is the number of bytes of arguments passed on the stack. */
1624 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1626 /* Some subroutine macros specific to this machine.
1627 When !TARGET_FPU, put float return values in the general registers,
1628 since we don't have any fp registers. */
1629 #define BASE_RETURN_VALUE_REG(MODE) \
1631 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 : 8) \
1632 : (TARGET_FPU && FLOAT_MODE_P (MODE) && (MODE) != TFmode ? 32 : 8))
1634 #define BASE_OUTGOING_VALUE_REG(MODE) \
1636 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 \
1637 : TARGET_FLAT ? 8 : 24) \
1638 : (TARGET_FPU && FLOAT_MODE_P (MODE) && (MODE) != TFmode ? 32\
1639 : (TARGET_FLAT ? 8 : 24)))
1641 #define BASE_PASSING_ARG_REG(MODE) \
1643 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 : 8) \
1646 /* ??? FIXME -- seems wrong for v9 structure passing... */
1647 #define BASE_INCOMING_ARG_REG(MODE) \
1649 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 \
1650 : TARGET_FLAT ? 8 : 24) \
1651 : (TARGET_FLAT ? 8 : 24))
1653 /* Define this macro if the target machine has "register windows". This
1654 C expression returns the register number as seen by the called function
1655 corresponding to register number OUT as seen by the calling function.
1656 Return OUT if register number OUT is not an outbound register. */
1658 #define INCOMING_REGNO(OUT) \
1659 ((TARGET_FLAT || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16)
1661 /* Define this macro if the target machine has "register windows". This
1662 C expression returns the register number as seen by the calling function
1663 corresponding to register number IN as seen by the called function.
1664 Return IN if register number IN is not an inbound register. */
1666 #define OUTGOING_REGNO(IN) \
1667 ((TARGET_FLAT || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16)
1669 /* Define this macro if the target machine has register windows. This
1670 C expression returns true if the register is call-saved but is in the
1673 #define LOCAL_REGNO(REGNO) \
1674 (TARGET_FLAT ? 0 : (REGNO) >= 16 && (REGNO) <= 31)
1676 /* Define how to find the value returned by a function.
1677 VALTYPE is the data type of the value (as a tree).
1678 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1679 otherwise, FUNC is 0. */
1681 /* On SPARC the value is found in the first "output" register. */
1683 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1684 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 1)
1686 /* But the called function leaves it in the first "input" register. */
1688 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
1689 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 0)
1691 /* Define how to find the value returned by a library function
1692 assuming the value has mode MODE. */
1694 #define LIBCALL_VALUE(MODE) \
1695 function_value (NULL_TREE, (MODE), 1)
1697 /* 1 if N is a possible register number for a function value
1698 as seen by the caller.
1699 On SPARC, the first "output" reg is used for integer values,
1700 and the first floating point register is used for floating point values. */
1702 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32)
1704 /* Define the size of space to allocate for the return value of an
1707 #define APPLY_RESULT_SIZE 16
1709 /* 1 if N is a possible register number for function argument passing.
1710 On SPARC, these are the "output" registers. v9 also uses %f0-%f31. */
1712 #define FUNCTION_ARG_REGNO_P(N) \
1714 ? (((N) >= 8 && (N) <= 13) || ((N) >= 32 && (N) <= 63)) \
1715 : ((N) >= 8 && (N) <= 13))
1717 /* Define a data type for recording info about an argument list
1718 during the scan of that argument list. This data type should
1719 hold all necessary information about the function itself
1720 and about the args processed so far, enough to enable macros
1721 such as FUNCTION_ARG to determine where the next arg should go.
1723 On SPARC (!v9), this is a single integer, which is a number of words
1724 of arguments scanned so far (including the invisible argument,
1725 if any, which holds the structure-value-address).
1726 Thus 7 or more means all following args should go on the stack.
1728 For v9, we also need to know whether a prototype is present. */
1731 int words; /* number of words passed so far */
1732 int prototype_p; /* nonzero if a prototype is present */
1733 int libcall_p; /* nonzero if a library call */
1735 #define CUMULATIVE_ARGS struct sparc_args
1737 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1738 for a call to a function whose data type is FNTYPE.
1739 For a library call, FNTYPE is 0. */
1741 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL) \
1742 init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL));
1744 /* Update the data in CUM to advance over an argument
1745 of mode MODE and data type TYPE.
1746 TYPE is null for libcalls where that information may not be available. */
1748 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1749 function_arg_advance (& (CUM), (MODE), (TYPE), (NAMED))
1751 /* Nonzero if we do not know how to pass TYPE solely in registers. */
1753 #define MUST_PASS_IN_STACK(MODE,TYPE) \
1755 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1756 || TREE_ADDRESSABLE (TYPE)))
1758 /* Determine where to put an argument to a function.
1759 Value is zero to push the argument on the stack,
1760 or a hard register in which to store the argument.
1762 MODE is the argument's machine mode.
1763 TYPE is the data type of the argument (as a tree).
1764 This is null for libcalls where that information may
1766 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1767 the preceding args and about the function being called.
1768 NAMED is nonzero if this argument is a named parameter
1769 (otherwise it is an extra parameter matching an ellipsis). */
1771 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1772 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 0)
1774 /* Define where a function finds its arguments.
1775 This is different from FUNCTION_ARG because of register windows. */
1777 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
1778 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 1)
1780 /* For an arg passed partly in registers and partly in memory,
1781 this is the number of registers used.
1782 For args passed entirely in registers or entirely in memory, zero. */
1784 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1785 function_arg_partial_nregs (& (CUM), (MODE), (TYPE), (NAMED))
1787 /* A C expression that indicates when an argument must be passed by reference.
1788 If nonzero for an argument, a copy of that argument is made in memory and a
1789 pointer to the argument is passed instead of the argument itself.
1790 The pointer is passed in whatever way is appropriate for passing a pointer
1793 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1794 function_arg_pass_by_reference (& (CUM), (MODE), (TYPE), (NAMED))
1796 /* If defined, a C expression which determines whether, and in which direction,
1797 to pad out an argument with extra space. The value should be of type
1798 `enum direction': either `upward' to pad above the argument,
1799 `downward' to pad below, or `none' to inhibit padding. */
1801 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1802 function_arg_padding ((MODE), (TYPE))
1804 /* If defined, a C expression that gives the alignment boundary, in bits,
1805 of an argument with the specified mode and type. If it is not defined,
1806 PARM_BOUNDARY is used for all arguments.
1807 For sparc64, objects requiring 16 byte alignment are passed that way. */
1809 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1811 && (GET_MODE_ALIGNMENT (MODE) == 128 \
1812 || ((TYPE) && TYPE_ALIGN (TYPE) == 128))) \
1813 ? 128 : PARM_BOUNDARY)
1815 /* Define the information needed to generate branch and scc insns. This is
1816 stored from the compare operation. Note that we can't use "rtx" here
1817 since it hasn't been defined! */
1819 extern GTY(()) rtx sparc_compare_op0;
1820 extern GTY(()) rtx sparc_compare_op1;
1823 /* Generate the special assembly code needed to tell the assembler whatever
1824 it might need to know about the return value of a function.
1826 For SPARC assemblers, we need to output a .proc pseudo-op which conveys
1827 information to the assembler relating to peephole optimization (done in
1830 #define ASM_DECLARE_RESULT(FILE, RESULT) \
1831 fprintf ((FILE), "\t.proc\t0%lo\n", sparc_type_code (TREE_TYPE (RESULT)))
1833 /* Output the special assembly code needed to tell the assembler some
1834 register is used as global register variable.
1836 SPARC 64bit psABI declares registers %g2 and %g3 as application
1837 registers and %g6 and %g7 as OS registers. Any object using them
1838 should declare (for %g2/%g3 has to, for %g6/%g7 can) that it uses them
1839 and how they are used (scratch or some global variable).
1840 Linker will then refuse to link together objects which use those
1841 registers incompatibly.
1843 Unless the registers are used for scratch, two different global
1844 registers cannot be declared to the same name, so in the unlikely
1845 case of a global register variable occupying more than one register
1846 we prefix the second and following registers with .gnu.part1. etc. */
1848 extern char sparc_hard_reg_printed[8];
1850 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
1851 #define ASM_DECLARE_REGISTER_GLOBAL(FILE, DECL, REGNO, NAME) \
1853 if (TARGET_ARCH64) \
1855 int end = HARD_REGNO_NREGS ((REGNO), DECL_MODE (decl)) + (REGNO); \
1857 for (reg = (REGNO); reg < 8 && reg < end; reg++) \
1858 if ((reg & ~1) == 2 || (reg & ~1) == 6) \
1860 if (reg == (REGNO)) \
1861 fprintf ((FILE), "\t.register\t%%g%d, %s\n", reg, (NAME)); \
1863 fprintf ((FILE), "\t.register\t%%g%d, .gnu.part%d.%s\n", \
1864 reg, reg - (REGNO), (NAME)); \
1865 sparc_hard_reg_printed[reg] = 1; \
1872 /* Emit rtl for profiling. */
1873 #define PROFILE_HOOK(LABEL) sparc_profile_hook (LABEL)
1875 /* All the work done in PROFILE_HOOK, but still required. */
1876 #define FUNCTION_PROFILER(FILE, LABELNO) do { } while (0)
1878 /* Set the name of the mcount function for the system. */
1879 #define MCOUNT_FUNCTION "*mcount"
1881 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1882 the stack pointer does not matter. The value is tested only in
1883 functions that have frame pointers.
1884 No definition is equivalent to always zero. */
1886 #define EXIT_IGNORE_STACK \
1887 (get_frame_size () != 0 \
1888 || current_function_calls_alloca || current_function_outgoing_args_size)
1890 #define DELAY_SLOTS_FOR_EPILOGUE \
1891 (TARGET_FLAT ? sparc_flat_epilogue_delay_slots () : 1)
1892 #define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \
1893 (TARGET_FLAT ? sparc_flat_eligible_for_epilogue_delay (trial, slots_filled) \
1894 : eligible_for_epilogue_delay (trial, slots_filled))
1896 /* Define registers used by the epilogue and return instruction. */
1897 #define EPILOGUE_USES(REGNO) \
1898 (!TARGET_FLAT && REGNO == 31)
1900 /* Length in units of the trampoline for entering a nested function. */
1902 #define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 32 : 16)
1904 #define TRAMPOLINE_ALIGNMENT 128 /* 16 bytes */
1906 /* Emit RTL insns to initialize the variable parts of a trampoline.
1907 FNADDR is an RTX for the address of the function's pure code.
1908 CXT is an RTX for the static chain value for the function. */
1910 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1911 if (TARGET_ARCH64) \
1912 sparc64_initialize_trampoline (TRAMP, FNADDR, CXT); \
1914 sparc_initialize_trampoline (TRAMP, FNADDR, CXT)
1916 /* Implement `va_start' for varargs and stdarg. */
1917 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
1918 sparc_va_start (valist, nextarg)
1920 /* Implement `va_arg'. */
1921 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1922 sparc_va_arg (valist, type)
1924 /* Generate RTL to flush the register windows so as to make arbitrary frames
1926 #define SETUP_FRAME_ADDRESSES() \
1927 emit_insn (gen_flush_register_windows ())
1929 /* Given an rtx for the address of a frame,
1930 return an rtx for the address of the word in the frame
1931 that holds the dynamic chain--the previous frame's address.
1932 ??? -mflat support? */
1933 #define DYNAMIC_CHAIN_ADDRESS(frame) \
1934 plus_constant (frame, 14 * UNITS_PER_WORD + SPARC_STACK_BIAS)
1936 /* The return address isn't on the stack, it is in a register, so we can't
1937 access it from the current frame pointer. We can access it from the
1938 previous frame pointer though by reading a value from the register window
1940 #define RETURN_ADDR_IN_PREVIOUS_FRAME
1942 /* This is the offset of the return address to the true next instruction to be
1943 executed for the current function. */
1944 #define RETURN_ADDR_OFFSET \
1945 (8 + 4 * (! TARGET_ARCH64 && current_function_returns_struct))
1947 /* The current return address is in %i7. The return address of anything
1948 farther back is in the register window save area at [%fp+60]. */
1949 /* ??? This ignores the fact that the actual return address is +8 for normal
1950 returns, and +12 for structure returns. */
1951 #define RETURN_ADDR_RTX(count, frame) \
1953 ? gen_rtx_REG (Pmode, 31) \
1954 : gen_rtx_MEM (Pmode, \
1955 memory_address (Pmode, plus_constant (frame, \
1956 15 * UNITS_PER_WORD \
1957 + SPARC_STACK_BIAS))))
1959 /* Before the prologue, the return address is %o7 + 8. OK, sometimes it's
1960 +12, but always using +8 is close enough for frame unwind purposes.
1961 Actually, just using %o7 is close enough for unwinding, but %o7+8
1962 is something you can return to. */
1963 #define INCOMING_RETURN_ADDR_RTX \
1964 plus_constant (gen_rtx_REG (word_mode, 15), 8)
1965 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (15)
1967 /* The offset from the incoming value of %sp to the top of the stack frame
1968 for the current function. On sparc64, we have to account for the stack
1970 #define INCOMING_FRAME_SP_OFFSET SPARC_STACK_BIAS
1972 /* Describe how we implement __builtin_eh_return. */
1973 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 24 : INVALID_REGNUM)
1974 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 1) /* %g1 */
1975 #define EH_RETURN_HANDLER_RTX gen_rtx_REG (Pmode, 31) /* %i7 */
1977 /* Select a format to encode pointers in exception handling data. CODE
1978 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
1979 true if the symbol may be affected by dynamic relocations.
1981 If assembler and linker properly support .uaword %r_disp32(foo),
1982 then use PC relative 32-bit relocations instead of absolute relocs
1983 for shared libraries. On sparc64, use pc relative 32-bit relocs even
1984 for binaries, to save memory.
1986 binutils 2.12 would emit a R_SPARC_DISP32 dynamic relocation if the
1987 symbol %r_disp32() is against was not local, but .hidden. In that
1988 case, we have to use DW_EH_PE_absptr for pic personality. */
1989 #ifdef HAVE_AS_SPARC_UA_PCREL
1990 #ifdef HAVE_AS_SPARC_UA_PCREL_HIDDEN
1991 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
1993 ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\
1994 : ((TARGET_ARCH64 && ! GLOBAL) \
1995 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \
1998 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
2000 ? (GLOBAL ? DW_EH_PE_absptr : (DW_EH_PE_pcrel | DW_EH_PE_sdata4)) \
2001 : ((TARGET_ARCH64 && ! GLOBAL) \
2002 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \
2006 /* Emit a PC-relative relocation. */
2007 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \
2009 fputs (integer_asm_op (SIZE, FALSE), FILE); \
2010 fprintf (FILE, "%%r_disp%d(", SIZE * 8); \
2011 assemble_name (FILE, LABEL); \
2012 fputc (')', FILE); \
2016 /* Addressing modes, and classification of registers for them. */
2018 /* Macros to check register numbers against specific register classes. */
2020 /* These assume that REGNO is a hard or pseudo reg number.
2021 They give nonzero only if REGNO is a hard reg of the suitable class
2022 or a pseudo reg currently allocated to a suitable hard reg.
2023 Since they use reg_renumber, they are safe only once reg_renumber
2024 has been allocated, which happens in local-alloc.c. */
2026 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2027 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < (unsigned)32 \
2028 || (REGNO) == FRAME_POINTER_REGNUM \
2029 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)
2031 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO)
2033 #define REGNO_OK_FOR_FP_P(REGNO) \
2034 (((unsigned) (REGNO) - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)) \
2035 || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)))
2036 #define REGNO_OK_FOR_CCFP_P(REGNO) \
2038 && (((unsigned) (REGNO) - 96 < (unsigned)4) \
2039 || ((unsigned) reg_renumber[REGNO] - 96 < (unsigned)4)))
2041 /* Now macros that check whether X is a register and also,
2042 strictly, whether it is in a specified class.
2044 These macros are specific to the SPARC, and may be used only
2045 in code for printing assembler insns and in conditions for
2046 define_optimization. */
2048 /* 1 if X is an fp register. */
2050 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
2052 /* Is X, a REG, an in or global register? i.e. is regno 0..7 or 24..31 */
2053 #define IN_OR_GLOBAL_P(X) (REGNO (X) < 8 || (REGNO (X) >= 24 && REGNO (X) <= 31))
2055 /* Maximum number of registers that can appear in a valid memory address. */
2057 #define MAX_REGS_PER_ADDRESS 2
2059 /* Recognize any constant value that is a valid address.
2060 When PIC, we do not accept an address that would require a scratch reg
2061 to load into a register. */
2063 #define CONSTANT_ADDRESS_P(X) constant_address_p (X)
2065 /* Define this, so that when PIC, reload won't try to reload invalid
2066 addresses which require two reload registers. */
2068 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
2070 /* Nonzero if the constant value X is a legitimate general operand.
2071 Anything can be made to work except floating point constants.
2072 If TARGET_VIS, 0.0 can be made to work as well. */
2074 #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X)
2076 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2077 and check its validity for a certain class.
2078 We have two alternate definitions for each of them.
2079 The usual definition accepts all pseudo regs; the other rejects
2080 them unless they have been allocated suitable hard regs.
2081 The symbol REG_OK_STRICT causes the latter definition to be used.
2083 Most source files want to accept pseudo regs in the hope that
2084 they will get allocated to the class that the insn wants them to be in.
2085 Source files for reload pass need to be strict.
2086 After reload, it makes no difference, since pseudo regs have
2087 been eliminated by then. */
2089 /* Optional extra constraints for this machine.
2091 'Q' handles floating point constants which can be moved into
2092 an integer register with a single sethi instruction.
2094 'R' handles floating point constants which can be moved into
2095 an integer register with a single mov instruction.
2097 'S' handles floating point constants which can be moved into
2098 an integer register using a high/lo_sum sequence.
2100 'T' handles memory addresses where the alignment is known to
2101 be at least 8 bytes.
2103 `U' handles all pseudo registers or a hard even numbered
2104 integer register, needed for ldd/std instructions.
2106 'W' handles the memory operand when moving operands in/out
2107 of 'e' constraint floating point registers. */
2109 #ifndef REG_OK_STRICT
2111 /* Nonzero if X is a hard reg that can be used as an index
2112 or if it is a pseudo reg. */
2113 #define REG_OK_FOR_INDEX_P(X) \
2115 || REGNO (X) == FRAME_POINTER_REGNUM \
2116 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2118 /* Nonzero if X is a hard reg that can be used as a base reg
2119 or if it is a pseudo reg. */
2120 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_INDEX_P (X)
2122 /* 'T', 'U' are for aligned memory loads which aren't needed for arch64.
2123 'W' is like 'T' but is assumed true on arch64.
2125 Remember to accept pseudo-registers for memory constraints if reload is
2128 #define EXTRA_CONSTRAINT(OP, C) \
2129 sparc_extra_constraint_check(OP, C, 0)
2133 /* Nonzero if X is a hard reg that can be used as an index. */
2134 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
2135 /* Nonzero if X is a hard reg that can be used as a base reg. */
2136 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
2138 #define EXTRA_CONSTRAINT(OP, C) \
2139 sparc_extra_constraint_check(OP, C, 1)
2143 /* Should gcc use [%reg+%lo(xx)+offset] addresses? */
2145 #ifdef HAVE_AS_OFFSETABLE_LO10
2146 #define USE_AS_OFFSETABLE_LO10 1
2148 #define USE_AS_OFFSETABLE_LO10 0
2151 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2152 that is a valid memory address for an instruction.
2153 The MODE argument is the machine mode for the MEM expression
2154 that wants to use this address.
2156 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
2157 ordinarily. This changes a bit when generating PIC.
2159 If you change this, execute "rm explow.o recog.o reload.o". */
2161 #define SYMBOLIC_CONST(X) symbolic_operand (X, VOIDmode)
2163 #define RTX_OK_FOR_BASE_P(X) \
2164 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2165 || (GET_CODE (X) == SUBREG \
2166 && GET_CODE (SUBREG_REG (X)) == REG \
2167 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2169 #define RTX_OK_FOR_INDEX_P(X) \
2170 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2171 || (GET_CODE (X) == SUBREG \
2172 && GET_CODE (SUBREG_REG (X)) == REG \
2173 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
2175 #define RTX_OK_FOR_OFFSET_P(X) \
2176 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000 - 8)
2178 #define RTX_OK_FOR_OLO10_P(X) \
2179 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0xc00 - 8)
2181 #ifdef REG_OK_STRICT
2182 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2184 if (legitimate_address_p (MODE, X, 1)) \
2188 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2190 if (legitimate_address_p (MODE, X, 0)) \
2195 /* Go to LABEL if ADDR (a legitimate address expression)
2196 has an effect that depends on the machine mode it is used for.
2202 is not equivalent to
2204 (mem:QI [%l7+a]) (mem:QI [%l7+a+1])
2206 because [%l7+a+1] is interpreted as the address of (a+1). */
2208 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2210 if (flag_pic == 1) \
2212 if (GET_CODE (ADDR) == PLUS) \
2214 rtx op0 = XEXP (ADDR, 0); \
2215 rtx op1 = XEXP (ADDR, 1); \
2216 if (op0 == pic_offset_table_rtx \
2217 && SYMBOLIC_CONST (op1)) \
2223 /* Try machine-dependent ways of modifying an illegitimate address
2224 to be legitimate. If we find one, return the new, valid address.
2225 This macro is used in only one place: `memory_address' in explow.c.
2227 OLDX is the address as it was before break_out_memory_refs was called.
2228 In some cases it is useful to look at this to decide what needs to be done.
2230 MODE and WIN are passed so that this macro can use
2231 GO_IF_LEGITIMATE_ADDRESS.
2233 It is always safe for this macro to do nothing. It exists to recognize
2234 opportunities to optimize the output. */
2236 /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
2237 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2239 (X) = legitimize_address (X, OLDX, MODE); \
2240 if (memory_address_p (MODE, X)) \
2244 /* Try a machine-dependent way of reloading an illegitimate address
2245 operand. If we find one, push the reload and jump to WIN. This
2246 macro is used in only one place: `find_reloads_address' in reload.c.
2248 For SPARC 32, we wish to handle addresses by splitting them into
2249 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
2250 This cuts the number of extra insns by one.
2252 Do nothing when generating PIC code and the address is a
2253 symbolic operand or requires a scratch register. */
2255 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2257 /* Decompose SImode constants into hi+lo_sum. We do have to \
2258 rerecognize what we produce, so be careful. */ \
2259 if (CONSTANT_P (X) \
2260 && (MODE != TFmode || TARGET_ARCH64) \
2261 && GET_MODE (X) == SImode \
2262 && GET_CODE (X) != LO_SUM && GET_CODE (X) != HIGH \
2264 && (symbolic_operand (X, Pmode) \
2265 || pic_address_needs_scratch (X))) \
2266 && sparc_cmodel <= CM_MEDLOW) \
2268 X = gen_rtx_LO_SUM (GET_MODE (X), \
2269 gen_rtx_HIGH (GET_MODE (X), X), X); \
2270 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
2271 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
2275 /* ??? 64-bit reloads. */ \
2278 /* Specify the machine mode that this machine uses
2279 for the index in the tablejump instruction. */
2280 /* If we ever implement any of the full models (such as CM_FULLANY),
2281 this has to be DImode in that case */
2282 #ifdef HAVE_GAS_SUBSECTION_ORDERING
2283 #define CASE_VECTOR_MODE \
2284 (! TARGET_PTR64 ? SImode : flag_pic ? SImode : TARGET_CM_MEDLOW ? SImode : DImode)
2286 /* If assembler does not have working .subsection -1, we use DImode for pic, as otherwise
2287 we have to sign extend which slows things down. */
2288 #define CASE_VECTOR_MODE \
2289 (! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode)
2292 /* Define as C expression which evaluates to nonzero if the tablejump
2293 instruction expects the table to contain offsets from the address of the
2295 Do not define this if the table should contain absolute addresses. */
2296 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2298 /* Define this as 1 if `char' should by default be signed; else as 0. */
2299 #define DEFAULT_SIGNED_CHAR 1
2301 /* Max number of bytes we can move from memory to memory
2302 in one reasonably fast instruction. */
2305 #if 0 /* Sun 4 has matherr, so this is no good. */
2306 /* This is the value of the error code EDOM for this machine,
2307 used by the sqrt instruction. */
2308 #define TARGET_EDOM 33
2310 /* This is how to refer to the variable errno. */
2311 #define GEN_ERRNO_RTX \
2312 gen_rtx_MEM (SImode, gen_rtx_SYMBOL_REF (Pmode, "errno"))
2315 /* Define if operations between registers always perform the operation
2316 on the full register even if a narrower mode is specified. */
2317 #define WORD_REGISTER_OPERATIONS
2319 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2320 will either zero-extend or sign-extend. The value of this macro should
2321 be the code that says which one of the two operations is implicitly
2322 done, NIL if none. */
2323 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2325 /* Nonzero if access to memory by bytes is slow and undesirable.
2326 For RISC chips, it means that access to memory by bytes is no
2327 better than access by words when possible, so grab a whole word
2328 and maybe make use of that. */
2329 #define SLOW_BYTE_ACCESS 1
2331 /* Define this to be nonzero if shift instructions ignore all but the low-order
2333 #define SHIFT_COUNT_TRUNCATED 1
2335 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2336 is done just by pretending it is already truncated. */
2337 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2339 /* Specify the machine mode that pointers have.
2340 After generation of rtl, the compiler makes no further distinction
2341 between pointers and any other objects of this machine mode. */
2342 #define Pmode (TARGET_ARCH64 ? DImode : SImode)
2344 /* Generate calls to memcpy, memcmp and memset. */
2345 #define TARGET_MEM_FUNCTIONS
2347 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2348 return the mode to be used for the comparison. For floating-point,
2349 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2350 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2351 processing is needed. */
2352 #define SELECT_CC_MODE(OP,X,Y) select_cc_mode ((OP), (X), (Y))
2354 /* Return nonzero if MODE implies a floating point inequality can be
2355 reversed. For SPARC this is always true because we have a full
2356 compliment of ordered and unordered comparisons, but until generic
2357 code knows how to reverse it correctly we keep the old definition. */
2358 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode && (MODE) != CCFPmode)
2360 /* A function address in a call instruction for indexing purposes. */
2361 #define FUNCTION_MODE Pmode
2363 /* Define this if addresses of constant functions
2364 shouldn't be put through pseudo regs where they can be cse'd.
2365 Desirable on machines where ordinary constants are expensive
2366 but a CALL with constant address is cheap. */
2367 #define NO_FUNCTION_CSE
2369 /* alloca should avoid clobbering the old register save area. */
2370 #define SETJMP_VIA_SAVE_AREA
2372 /* The _Q_* comparison libcalls return booleans. */
2373 #define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) ((MODE) == TFmode)
2375 /* Assume by default that the _Qp_* 64-bit libcalls are implemented such
2376 that the inputs are fully consumed before the output memory is clobbered. */
2378 #define TARGET_BUGGY_QP_LIB 0
2380 /* Assume by default that we do not have the Solaris-specific conversion
2381 routines nor 64-bit integer multiply and divide routines. */
2383 #define SUN_CONVERSION_LIBFUNCS 0
2384 #define SUN_INTEGER_MULTIPLY_64 0
2386 /* Compute extra cost of moving data between one register class
2388 #define GENERAL_OR_I64(C) ((C) == GENERAL_REGS || (C) == I64_REGS)
2389 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
2390 (((FP_REG_CLASS_P (CLASS1) && GENERAL_OR_I64 (CLASS2)) \
2391 || (GENERAL_OR_I64 (CLASS1) && FP_REG_CLASS_P (CLASS2)) \
2392 || (CLASS1) == FPCC_REGS || (CLASS2) == FPCC_REGS) \
2393 ? ((sparc_cpu == PROCESSOR_ULTRASPARC \
2394 || sparc_cpu == PROCESSOR_ULTRASPARC3) ? 12 : 6) : 2)
2396 /* Provide the cost of a branch. For pre-v9 processors we use
2397 a value of 3 to take into account the potential annulling of
2398 the delay slot (which ends up being a bubble in the pipeline slot)
2399 plus a cycle to take into consideration the instruction cache
2402 On v9 and later, which have branch prediction facilities, we set
2403 it to the depth of the pipeline as that is the cost of a
2404 mispredicted branch. */
2406 #define BRANCH_COST \
2407 ((sparc_cpu == PROCESSOR_V9 \
2408 || sparc_cpu == PROCESSOR_ULTRASPARC) \
2410 : (sparc_cpu == PROCESSOR_ULTRASPARC3 \
2413 #define PREFETCH_BLOCK \
2414 ((sparc_cpu == PROCESSOR_ULTRASPARC \
2415 || sparc_cpu == PROCESSOR_ULTRASPARC3) \
2418 #define SIMULTANEOUS_PREFETCHES \
2419 ((sparc_cpu == PROCESSOR_ULTRASPARC) \
2421 : (sparc_cpu == PROCESSOR_ULTRASPARC3 \
2424 /* Control the assembler format that we output. */
2426 /* A C string constant describing how to begin a comment in the target
2427 assembler language. The compiler assumes that the comment will end at
2428 the end of the line. */
2430 #define ASM_COMMENT_START "!"
2432 /* Output to assembler file text saying following lines
2433 may contain character constants, extra white space, comments, etc. */
2435 #define ASM_APP_ON ""
2437 /* Output to assembler file text saying following lines
2438 no longer contain unusual constructs. */
2440 #define ASM_APP_OFF ""
2442 /* ??? Try to make the style consistent here (_OP?). */
2444 #define ASM_FLOAT ".single"
2445 #define ASM_DOUBLE ".double"
2446 #define ASM_LONGDOUBLE ".xxx" /* ??? Not known (or used yet). */
2448 /* How to refer to registers in assembler output.
2449 This sequence is indexed by compiler's hard-register-number (see above). */
2451 #define REGISTER_NAMES \
2452 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \
2453 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \
2454 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \
2455 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \
2456 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \
2457 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \
2458 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \
2459 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \
2460 "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \
2461 "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \
2462 "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \
2463 "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \
2464 "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc", "%sfp" }
2466 /* Define additional names for use in asm clobbers and asm declarations. */
2468 #define ADDITIONAL_REGISTER_NAMES \
2469 {{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}}
2471 /* On Sun 4, this limit is 2048. We use 1000 to be safe, since the length
2472 can run past this up to a continuation point. Once we used 1500, but
2473 a single entry in C++ can run more than 500 bytes, due to the length of
2474 mangled symbol names. dbxout.c should really be fixed to do
2475 continuations when they are actually needed instead of trying to
2477 #define DBX_CONTIN_LENGTH 1000
2479 /* This is how to output a command to make the user-level label named NAME
2480 defined for reference from other files. */
2482 /* Globalizing directive for a label. */
2483 #define GLOBAL_ASM_OP "\t.global "
2485 /* The prefix to add to user-visible assembler symbols. */
2487 #define USER_LABEL_PREFIX "_"
2489 /* This is how to store into the string LABEL
2490 the symbol_ref name of an internal numbered label where
2491 PREFIX is the class of label and NUM is the number within the class.
2492 This is suitable for output with `assemble_name'. */
2494 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2495 sprintf ((LABEL), "*%s%ld", (PREFIX), (long)(NUM))
2497 /* This is how we hook in and defer the case-vector until the end of
2499 #define ASM_OUTPUT_ADDR_VEC(LAB,VEC) \
2500 sparc_defer_case_vector ((LAB),(VEC), 0)
2502 #define ASM_OUTPUT_ADDR_DIFF_VEC(LAB,VEC) \
2503 sparc_defer_case_vector ((LAB),(VEC), 1)
2505 /* This is how to output an element of a case-vector that is absolute. */
2507 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2510 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
2511 if (CASE_VECTOR_MODE == SImode) \
2512 fprintf (FILE, "\t.word\t"); \
2514 fprintf (FILE, "\t.xword\t"); \
2515 assemble_name (FILE, label); \
2516 fputc ('\n', FILE); \
2519 /* This is how to output an element of a case-vector that is relative.
2520 (SPARC uses such vectors only when generating PIC.) */
2522 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2525 ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE)); \
2526 if (CASE_VECTOR_MODE == SImode) \
2527 fprintf (FILE, "\t.word\t"); \
2529 fprintf (FILE, "\t.xword\t"); \
2530 assemble_name (FILE, label); \
2531 ASM_GENERATE_INTERNAL_LABEL (label, "L", (REL)); \
2532 fputc ('-', FILE); \
2533 assemble_name (FILE, label); \
2534 fputc ('\n', FILE); \
2537 /* This is what to output before and after case-vector (both
2538 relative and absolute). If .subsection -1 works, we put case-vectors
2539 at the beginning of the current section. */
2541 #ifdef HAVE_GAS_SUBSECTION_ORDERING
2543 #define ASM_OUTPUT_ADDR_VEC_START(FILE) \
2544 fprintf(FILE, "\t.subsection\t-1\n")
2546 #define ASM_OUTPUT_ADDR_VEC_END(FILE) \
2547 fprintf(FILE, "\t.previous\n")
2551 /* This is how to output an assembler line
2552 that says to advance the location counter
2553 to a multiple of 2**LOG bytes. */
2555 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2557 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
2559 /* This is how to output an assembler line that says to advance
2560 the location counter to a multiple of 2**LOG bytes using the
2561 "nop" instruction as padding. */
2562 #define ASM_OUTPUT_ALIGN_WITH_NOP(FILE,LOG) \
2564 fprintf (FILE, "\t.align %d,0x1000000\n", (1<<(LOG)))
2566 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
2567 fprintf (FILE, "\t.skip "HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2569 /* This says how to output an assembler line
2570 to define a global common symbol. */
2572 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
2573 ( fputs ("\t.common ", (FILE)), \
2574 assemble_name ((FILE), (NAME)), \
2575 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\"\n", (SIZE)))
2577 /* This says how to output an assembler line to define a local common
2580 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \
2581 ( fputs ("\t.reserve ", (FILE)), \
2582 assemble_name ((FILE), (NAME)), \
2583 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\",%u\n", \
2584 (SIZE), ((ALIGNED) / BITS_PER_UNIT)))
2586 /* A C statement (sans semicolon) to output to the stdio stream
2587 FILE the assembler definition of uninitialized global DECL named
2588 NAME whose size is SIZE bytes and alignment is ALIGN bytes.
2589 Try to use asm_output_aligned_bss to implement this macro. */
2591 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2593 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \
2596 #define IDENT_ASM_OP "\t.ident\t"
2598 /* Output #ident as a .ident. */
2600 #define ASM_OUTPUT_IDENT(FILE, NAME) \
2601 fprintf (FILE, "%s\"%s\"\n", IDENT_ASM_OP, NAME);
2603 /* Emit a dtp-relative reference to a TLS variable. */
2606 #define ASM_OUTPUT_DWARF_DTPREL(FILE, SIZE, X) \
2607 sparc_output_dwarf_dtprel (FILE, SIZE, X)
2610 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
2611 ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' \
2612 || (CHAR) == '(' || (CHAR) == '_' || (CHAR) == '&')
2614 /* Print operand X (an rtx) in assembler syntax to file FILE.
2615 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2616 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2618 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2620 /* Print a memory address as an operand to reference that memory location. */
2622 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2623 { register rtx base, index = 0; \
2625 register rtx addr = ADDR; \
2626 if (GET_CODE (addr) == REG) \
2627 fputs (reg_names[REGNO (addr)], FILE); \
2628 else if (GET_CODE (addr) == PLUS) \
2630 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
2631 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\
2632 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
2633 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\
2635 base = XEXP (addr, 0), index = XEXP (addr, 1); \
2636 if (GET_CODE (base) == LO_SUM) \
2638 if (! USE_AS_OFFSETABLE_LO10 \
2640 || TARGET_CM_MEDMID) \
2642 output_operand (XEXP (base, 0), 0); \
2643 fputs ("+%lo(", FILE); \
2644 output_address (XEXP (base, 1)); \
2645 fprintf (FILE, ")+%d", offset); \
2649 fputs (reg_names[REGNO (base)], FILE); \
2651 fprintf (FILE, "%+d", offset); \
2652 else if (GET_CODE (index) == REG) \
2653 fprintf (FILE, "+%s", reg_names[REGNO (index)]); \
2654 else if (GET_CODE (index) == SYMBOL_REF \
2655 || GET_CODE (index) == CONST) \
2656 fputc ('+', FILE), output_addr_const (FILE, index); \
2660 else if (GET_CODE (addr) == MINUS \
2661 && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \
2663 output_addr_const (FILE, XEXP (addr, 0)); \
2664 fputs ("-(", FILE); \
2665 output_addr_const (FILE, XEXP (addr, 1)); \
2666 fputs ("-.)", FILE); \
2668 else if (GET_CODE (addr) == LO_SUM) \
2670 output_operand (XEXP (addr, 0), 0); \
2671 if (TARGET_CM_MEDMID) \
2672 fputs ("+%l44(", FILE); \
2674 fputs ("+%lo(", FILE); \
2675 output_address (XEXP (addr, 1)); \
2676 fputc (')', FILE); \
2678 else if (flag_pic && GET_CODE (addr) == CONST \
2679 && GET_CODE (XEXP (addr, 0)) == MINUS \
2680 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \
2681 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \
2682 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \
2684 addr = XEXP (addr, 0); \
2685 output_addr_const (FILE, XEXP (addr, 0)); \
2686 /* Group the args of the second CONST in parenthesis. */ \
2687 fputs ("-(", FILE); \
2688 /* Skip past the second CONST--it does nothing for us. */\
2689 output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \
2690 /* Close the parenthesis. */ \
2691 fputc (')', FILE); \
2695 output_addr_const (FILE, addr); \
2700 #define TARGET_TLS 1
2702 #define TARGET_TLS 0
2704 #define TARGET_SUN_TLS TARGET_TLS
2705 #define TARGET_GNU_TLS 0
2707 /* Define the codes that are matched by predicates in sparc.c. */
2709 #define PREDICATE_CODES \
2710 {"reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2711 {"const1_operand", {CONST_INT}}, \
2712 {"fp_zero_operand", {CONST_DOUBLE}}, \
2713 {"fp_register_operand", {SUBREG, REG}}, \
2714 {"intreg_operand", {SUBREG, REG}}, \
2715 {"fcc_reg_operand", {REG}}, \
2716 {"fcc0_reg_operand", {REG}}, \
2717 {"icc_or_fcc_reg_operand", {REG}}, \
2718 {"restore_operand", {REG}}, \
2719 {"call_operand", {MEM}}, \
2720 {"call_operand_address", {SYMBOL_REF, LABEL_REF, CONST, CONST_DOUBLE, \
2721 ADDRESSOF, SUBREG, REG, PLUS, LO_SUM, CONST_INT}}, \
2722 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
2723 {"symbolic_memory_operand", {SUBREG, MEM}}, \
2724 {"label_ref_operand", {LABEL_REF}}, \
2725 {"sp64_medium_pic_operand", {CONST}}, \
2726 {"data_segment_operand", {SYMBOL_REF, PLUS, CONST}}, \
2727 {"text_segment_operand", {LABEL_REF, SYMBOL_REF, PLUS, CONST}}, \
2728 {"reg_or_nonsymb_mem_operand", {SUBREG, REG, MEM}}, \
2729 {"splittable_symbolic_memory_operand", {MEM}}, \
2730 {"splittable_immediate_memory_operand", {MEM}}, \
2731 {"eq_or_neq", {EQ, NE}}, \
2732 {"normal_comp_operator", {GE, GT, LE, LT, GTU, LEU}}, \
2733 {"noov_compare_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}}, \
2734 {"noov_compare64_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}}, \
2735 {"v9_regcmp_op", {EQ, NE, GE, LT, LE, GT}}, \
2736 {"extend_op", {SIGN_EXTEND, ZERO_EXTEND}}, \
2737 {"cc_arithop", {AND, IOR, XOR}}, \
2738 {"cc_arithopn", {AND, IOR}}, \
2739 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
2740 {"arith_add_operand", {SUBREG, REG, CONST_INT}}, \
2741 {"arith11_operand", {SUBREG, REG, CONST_INT}}, \
2742 {"arith10_operand", {SUBREG, REG, CONST_INT}}, \
2743 {"arith_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2744 {"arith_double_add_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2745 {"arith11_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2746 {"arith10_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2747 {"small_int", {CONST_INT}}, \
2748 {"small_int_or_double", {CONST_INT, CONST_DOUBLE}}, \
2749 {"uns_small_int", {CONST_INT}}, \
2750 {"uns_arith_operand", {SUBREG, REG, CONST_INT}}, \
2751 {"clobbered_register", {REG}}, \
2752 {"input_operand", {SUBREG, REG, CONST_INT, MEM, CONST}}, \
2753 {"const64_operand", {CONST_INT, CONST_DOUBLE}}, \
2754 {"const64_high_operand", {CONST_INT, CONST_DOUBLE}}, \
2755 {"tgd_symbolic_operand", {SYMBOL_REF}}, \
2756 {"tld_symbolic_operand", {SYMBOL_REF}}, \
2757 {"tie_symbolic_operand", {SYMBOL_REF}}, \
2758 {"tle_symbolic_operand", {SYMBOL_REF}},
2760 /* The number of Pmode words for the setjmp buffer. */
2761 #define JMP_BUF_SIZE 12
2763 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (flag_pic)
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